476 lines
17 KiB
Verilog
476 lines
17 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// uart_receiver.v ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Documentation related to this project: ////
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//// - http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Projects compatibility: ////
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//// - WISHBONE ////
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//// RS232 Protocol ////
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//// 16550D uart (mostly supported) ////
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//// ////
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//// Overview (main Features): ////
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//// UART core receiver logic ////
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//// ////
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//// Known problems (limits): ////
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//// None known ////
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//// ////
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//// To Do: ////
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//// Thourough testing. ////
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//// ////
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//// Author(s): ////
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//// - gorban@opencores.org ////
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//// - Jacob Gorban ////
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//// - Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// Created: 2001/05/12 ////
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//// Last Updated: 2001/05/17 ////
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//// (See log for the revision history) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000, 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.29 2002/07/29 21:16:18 gorban
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// The uart_defines.v file is included again in sources.
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//
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// Revision 1.28 2002/07/22 23:02:23 gorban
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// Bug Fixes:
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// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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// Problem reported by Kenny.Tung.
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// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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// * Made FIFO's as general inferrable memory where possible.
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// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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// * Added optional baudrate output (baud_o).
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// This is identical to BAUDOUT* signal on 16550 chip.
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// It outputs 16xbit_clock_rate - the divided clock.
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// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.27 2001/12/30 20:39:13 mohor
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// More than one character was stored in case of break. End of the break
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// was not detected correctly.
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//
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// Revision 1.26 2001/12/20 13:28:27 mohor
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// Missing declaration of rf_push_q fixed.
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//
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// Revision 1.25 2001/12/20 13:25:46 mohor
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// rx push changed to be only one cycle wide.
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//
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// Revision 1.24 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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//
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// Revision 1.23 2001/12/19 07:33:54 mohor
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// Synplicity was having troubles with the comment.
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//
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// Revision 1.22 2001/12/17 14:46:48 mohor
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// overrun signal was moved to separate block because many sequential lsr
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// reads were preventing data from being written to rx fifo.
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// underrun signal was not used and was removed from the project.
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//
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// Revision 1.21 2001/12/13 10:31:16 mohor
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// timeout irq must be set regardless of the rda irq (rda irq does not reset the
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// timeout counter).
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//
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// Revision 1.20 2001/12/10 19:52:05 gorban
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// Igor fixed break condition bugs
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//
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// Revision 1.19 2001/12/06 14:51:04 gorban
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// Bug in LSR[0] is fixed.
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// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
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//
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// Revision 1.18 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.17 2001/11/28 19:36:39 gorban
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// Fixed: timeout and break didn't pay attention to current data format when counting time
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//
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// Revision 1.16 2001/11/27 22:17:09 gorban
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// Fixed bug that prevented synthesis in uart_receiver.v
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//
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// Revision 1.15 2001/11/26 21:38:54 gorban
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// Lots of fixes:
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// Break condition wasn't handled correctly at all.
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// LSR bits could lose their values.
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// LSR value after reset was wrong.
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// Timing of THRE interrupt signal corrected.
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// LSR bit 0 timing corrected.
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//
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// Revision 1.14 2001/11/10 12:43:21 gorban
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// Logic Synthesis bugs fixed. Some other minor changes
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//
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// Revision 1.13 2001/11/08 14:54:23 mohor
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// Comments in Slovene language deleted, few small fixes for better work of
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// old tools. IRQs need to be fix.
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//
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// Revision 1.12 2001/11/07 17:51:52 gorban
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// Heavily rewritten interrupt and LSR subsystems.
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// Many bugs hopefully squashed.
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//
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// Revision 1.11 2001/10/31 15:19:22 gorban
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// Fixes to break and timeout conditions
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//
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// Revision 1.10 2001/10/20 09:58:40 gorban
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// Small synopsis fixes
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//
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// Revision 1.9 2001/08/24 21:01:12 mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.8 2001/08/23 16:05:05 mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.6 2001/06/23 11:21:48 gorban
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// DL made 16-bit long. Fixed transmission/reception bugs.
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//
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// Revision 1.5 2001/06/02 14:28:14 gorban
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// Fixed receiver and transmitter. Major bug fixed.
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//
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// Revision 1.4 2001/05/31 20:08:01 gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3 2001/05/27 17:37:49 gorban
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// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
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//
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// Revision 1.2 2001/05/21 19:12:02 gorban
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// Corrected some Linter messages.
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//
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// Revision 1.1 2001/05/17 18:34:18 gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0 2001-05-17 21:27:11+02 jacob
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// Initial revision
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//
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//
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`include "uart_defines.v"
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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input clk;
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input wb_rst_i;
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input [7:0] lcr;
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input rf_pop;
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input srx_pad_i;
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input enable;
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input rx_reset;
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input lsr_mask;
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output [9:0] counter_t;
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output [`UART_FIFO_COUNTER_W-1:0] rf_count;
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output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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output rf_overrun;
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output rf_error_bit;
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output [3:0] rstate;
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output rf_push_pulse;
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reg [3:0] rstate;
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reg [3:0] rcounter16;
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reg [2:0] rbit_counter;
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reg [7:0] rshift; // receiver shift register
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reg rparity; // received parity
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reg rparity_error;
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reg rframing_error; // framing error flag
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reg rparity_xor;
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reg [7:0] counter_b; // counts the 0 (low) signals
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reg rf_push_q;
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// RX FIFO signals
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reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
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wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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wire rf_push_pulse;
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reg rf_push;
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wire rf_pop;
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wire rf_overrun;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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wire break_error = (counter_b == 0);
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// RX FIFO instance
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uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.data_in( rf_data_in ),
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.data_out( rf_data_out ),
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.push( rf_push_pulse ),
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.pop( rf_pop ),
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.overrun( rf_overrun ),
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.count( rf_count ),
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.error_bit( rf_error_bit ),
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.fifo_reset( rx_reset ),
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.reset_status(lsr_mask)
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);
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wire rcounter16_eq_7 = (rcounter16 == 4'd7);
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wire rcounter16_eq_0 = (rcounter16 == 4'd0);
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wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1;
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parameter sr_idle = 4'd0;
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parameter sr_rec_start = 4'd1;
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parameter sr_rec_bit = 4'd2;
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parameter sr_rec_parity = 4'd3;
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parameter sr_rec_stop = 4'd4;
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parameter sr_check_parity = 4'd5;
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parameter sr_rec_prepare = 4'd6;
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parameter sr_end_bit = 4'd7;
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parameter sr_ca_lc_parity = 4'd8;
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parameter sr_wait1 = 4'd9;
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parameter sr_push = 4'd10;
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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begin
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rstate <= sr_idle;
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rcounter16 <= 0;
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rbit_counter <= 0;
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rparity_xor <= 1'b0;
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rframing_error <= 1'b0;
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rparity_error <= 1'b0;
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rparity <= 1'b0;
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rshift <= 0;
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rf_push <= 1'b0;
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rf_data_in <= 0;
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end
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else
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if (enable)
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begin
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case (rstate)
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sr_idle : begin
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rf_push <= 1'b0;
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rf_data_in <= 0;
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rcounter16 <= 4'b1110;
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if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
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begin
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rstate <= sr_rec_start;
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end
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end
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sr_rec_start : begin
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rf_push <= 1'b0;
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if (rcounter16_eq_7) // check the pulse
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if (srx_pad_i==1'b1) // no start bit
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rstate <= sr_idle;
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else // start bit detected
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rstate <= sr_rec_prepare;
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rcounter16 <= rcounter16_minus_1;
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end
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sr_rec_prepare:begin
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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2'b00 : rbit_counter <= 3'b100;
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2'b01 : rbit_counter <= 3'b101;
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2'b10 : rbit_counter <= 3'b110;
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2'b11 : rbit_counter <= 3'b111;
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endcase
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if (rcounter16_eq_0)
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begin
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rstate <= sr_rec_bit;
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rcounter16 <= 4'b1110;
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rshift <= 0;
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end
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else
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rstate <= sr_rec_prepare;
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rcounter16 <= rcounter16_minus_1;
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end
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sr_rec_bit : begin
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if (rcounter16_eq_0)
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rstate <= sr_end_bit;
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if (rcounter16_eq_7) // read the bit
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
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2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
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2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
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2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
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endcase
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rcounter16 <= rcounter16_minus_1;
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end
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sr_end_bit : begin
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if (rbit_counter==3'b0) // no more bits in word
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if (lcr[`UART_LC_PE]) // choose state based on parity
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rstate <= sr_rec_parity;
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else
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begin
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rstate <= sr_rec_stop;
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rparity_error <= 1'b0; // no parity - no error :)
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end
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else // else we have more bits to read
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begin
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rstate <= sr_rec_bit;
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rbit_counter <= rbit_counter - 3'd1;
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end
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rcounter16 <= 4'b1110;
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end
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sr_rec_parity: begin
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if (rcounter16_eq_7) // read the parity
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begin
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rparity <= srx_pad_i;
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rstate <= sr_ca_lc_parity;
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end
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rcounter16 <= rcounter16_minus_1;
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end
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sr_ca_lc_parity : begin // rcounter equals 6
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rcounter16 <= rcounter16_minus_1;
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rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data
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rstate <= sr_check_parity;
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end
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sr_check_parity: begin // rcounter equals 5
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case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
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2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1
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2'b01: rparity_error <= ~rparity; // parity should sticked to 1
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2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd
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2'b11: rparity_error <= rparity; // parity should be sticked to 0
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endcase
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rcounter16 <= rcounter16_minus_1;
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rstate <= sr_wait1;
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end
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sr_wait1 : if (rcounter16_eq_0)
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begin
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rstate <= sr_rec_stop;
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rcounter16 <= 4'b1110;
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end
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else
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rcounter16 <= rcounter16_minus_1;
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sr_rec_stop : begin
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if (rcounter16_eq_7) // read the parity
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begin
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rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit)
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rstate <= sr_push;
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end
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rcounter16 <= rcounter16_minus_1;
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end
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sr_push : begin
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///////////////////////////////////////
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// $display($time, ": received: %b", rf_data_in);
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if(srx_pad_i | break_error)
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begin
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if(break_error)
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rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
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else
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rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
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rf_push <= 1'b1;
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rstate <= sr_idle;
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end
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else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
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begin
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rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
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rf_push <= 1'b1;
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rcounter16 <= 4'b1110;
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rstate <= sr_rec_start;
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end
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end
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default : rstate <= sr_idle;
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endcase
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end // if (enable)
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end // always of receiver
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always @ (posedge clk or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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rf_push_q <= 0;
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else
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rf_push_q <= rf_push;
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end
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assign rf_push_pulse = rf_push & ~rf_push_q;
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//
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// Break condition detection.
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// Works in conjuction with the receiver state machine
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reg [9:0] toc_value; // value to be set to timeout counter
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always @(lcr)
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case (lcr[3:0])
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4'b0000 : toc_value = 447; // 7 bits
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4'b0100 : toc_value = 479; // 7.5 bits
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4'b0001, 4'b1000 : toc_value = 511; // 8 bits
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4'b1100 : toc_value = 543; // 8.5 bits
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4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
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4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
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4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
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4'b1111 : toc_value = 767; // 12 bits
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endcase // case(lcr[3:0])
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wire [7:0] brc_value; // value to be set to break counter
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assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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counter_b <= 8'd159;
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else
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if (srx_pad_i)
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counter_b <= brc_value; // character time length - 1
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else
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if(enable & counter_b != 8'b0) // only work on enable times break not reached.
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counter_b <= counter_b - 8'd1; // decrement break counter
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end // always of break condition detection
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///
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/// Timeout condition detection
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reg [9:0] counter_t; // counts the timeout condition clocks
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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counter_t <= 10'd639; // 10 bits for the default 8N1
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else
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if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
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counter_t <= toc_value;
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else
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if (enable && counter_t != 10'b0) // we don't want to underflow
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counter_t <= counter_t - 10'd1;
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end
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endmodule
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