118 lines
5.5 KiB
Verilog
118 lines
5.5 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// uart_sync_flops.v ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Documentation related to this project: ////
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//// - http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Projects compatibility: ////
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//// - WISHBONE ////
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//// RS232 Protocol ////
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//// 16550D uart (mostly supported) ////
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//// ////
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//// Overview (main Features): ////
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//// UART core receiver logic ////
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//// ////
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//// Known problems (limits): ////
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//// None known ////
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//// ////
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//// To Do: ////
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//// Thourough testing. ////
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//// ////
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//// Author(s): ////
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//// - Andrej Erzen (andreje@flextronics.si) ////
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//// - Tadej Markovic (tadejm@flextronics.si) ////
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//// ////
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//// Created: 2004/05/20 ////
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//// Last Updated: 2004/05/20 ////
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//// (See log for the revision history) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000, 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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module uart_sync_flops
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(
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// internal signals
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rst_i,
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clk_i,
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stage1_rst_i,
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stage1_clk_en_i,
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async_dat_i,
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sync_dat_o
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);
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parameter width = 1;
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parameter init_value = 1'b0;
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input rst_i; // reset input
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input clk_i; // clock input
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input stage1_rst_i; // synchronous reset for stage 1 FF
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input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
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input [width-1:0] async_dat_i; // asynchronous data input
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output [width-1:0] sync_dat_o; // synchronous data output
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//
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// Interal signal declarations
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//
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reg [width-1:0] sync_dat_o;
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reg [width-1:0] flop_0;
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// first stage
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always @ (posedge clk_i or posedge rst_i)
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begin
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if (rst_i)
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flop_0 <= {width{init_value}};
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else
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flop_0 <= async_dat_i;
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end
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// second stage
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always @ (posedge clk_i or posedge rst_i)
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begin
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if (rst_i)
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sync_dat_o <= {width{init_value}};
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else if (stage1_rst_i)
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sync_dat_o <= {width{init_value}};
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else if (stage1_clk_en_i)
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sync_dat_o <= flop_0;
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end
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endmodule
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