105190 lines
4.9 MiB
105190 lines
4.9 MiB
module rvclkhdr(
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input io_clk,
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input io_en
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);
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wire clkhdr_Q; // @[lib.scala 340:26]
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wire clkhdr_CK; // @[lib.scala 340:26]
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wire clkhdr_EN; // @[lib.scala 340:26]
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wire clkhdr_SE; // @[lib.scala 340:26]
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gated_latch clkhdr ( // @[lib.scala 340:26]
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.Q(clkhdr_Q),
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.CK(clkhdr_CK),
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.EN(clkhdr_EN),
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.SE(clkhdr_SE)
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);
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assign clkhdr_CK = io_clk; // @[lib.scala 342:18]
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assign clkhdr_EN = io_en; // @[lib.scala 343:18]
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assign clkhdr_SE = 1'h0; // @[lib.scala 344:18]
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endmodule
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module ifu_mem_ctl(
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input clock,
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input reset,
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input io_free_l2clk,
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input io_active_clk,
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input io_exu_flush_final,
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input io_dec_mem_ctrl_dec_tlu_flush_err_wb,
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input io_dec_mem_ctrl_dec_tlu_i0_commit_cmt,
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input io_dec_mem_ctrl_dec_tlu_force_halt,
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input io_dec_mem_ctrl_dec_tlu_fence_i_wb,
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input [70:0] io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata,
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input [16:0] io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics,
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input io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid,
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input io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid,
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input io_dec_mem_ctrl_dec_tlu_core_ecc_disable,
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output io_dec_mem_ctrl_ifu_pmu_ic_miss,
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output io_dec_mem_ctrl_ifu_pmu_ic_hit,
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output io_dec_mem_ctrl_ifu_pmu_bus_error,
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output io_dec_mem_ctrl_ifu_pmu_bus_busy,
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output io_dec_mem_ctrl_ifu_pmu_bus_trxn,
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output io_dec_mem_ctrl_ifu_ic_error_start,
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output io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
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output [70:0] io_dec_mem_ctrl_ifu_ic_debug_rd_data,
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output io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid,
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output io_dec_mem_ctrl_ifu_miss_state_idle,
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input [30:0] io_ifc_fetch_addr_bf,
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input io_ifc_fetch_uncacheable_bf,
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input io_ifc_fetch_req_bf,
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input io_ifc_fetch_req_bf_raw,
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input io_ifc_iccm_access_bf,
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input io_ifc_region_acc_fault_bf,
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input io_ifc_dma_access_ok,
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input io_ifu_bp_hit_taken_f,
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input io_ifu_bp_inst_mask_f,
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input io_ifu_axi_ar_ready,
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output io_ifu_axi_ar_valid,
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output [2:0] io_ifu_axi_ar_bits_id,
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output [31:0] io_ifu_axi_ar_bits_addr,
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output [3:0] io_ifu_axi_ar_bits_region,
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output io_ifu_axi_r_ready,
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input io_ifu_axi_r_valid,
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input [2:0] io_ifu_axi_r_bits_id,
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input [63:0] io_ifu_axi_r_bits_data,
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input [1:0] io_ifu_axi_r_bits_resp,
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input io_ifu_bus_clk_en,
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input io_dma_mem_ctl_dma_iccm_req,
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input [31:0] io_dma_mem_ctl_dma_mem_addr,
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input [2:0] io_dma_mem_ctl_dma_mem_sz,
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input io_dma_mem_ctl_dma_mem_write,
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input [63:0] io_dma_mem_ctl_dma_mem_wdata,
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input [2:0] io_dma_mem_ctl_dma_mem_tag,
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output [14:0] io_iccm_rw_addr,
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output io_iccm_buf_correct_ecc,
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output io_iccm_correction_state,
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output io_iccm_wren,
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output io_iccm_rden,
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output [2:0] io_iccm_wr_size,
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output [77:0] io_iccm_wr_data,
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input [63:0] io_iccm_rd_data,
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input [77:0] io_iccm_rd_data_ecc,
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output [30:0] io_ic_rw_addr,
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output [1:0] io_ic_tag_valid,
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output [1:0] io_ic_wr_en,
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output io_ic_rd_en,
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output [70:0] io_ic_wr_data_0,
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output [70:0] io_ic_wr_data_1,
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output [70:0] io_ic_debug_wr_data,
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output [9:0] io_ic_debug_addr,
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input [63:0] io_ic_rd_data,
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input [70:0] io_ic_debug_rd_data,
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input [25:0] io_ic_tag_debug_rd_data,
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input [1:0] io_ic_eccerr,
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input [1:0] io_ic_rd_hit,
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input io_ic_tag_perr,
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output io_ic_debug_rd_en,
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output io_ic_debug_wr_en,
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output io_ic_debug_tag_array,
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output [1:0] io_ic_debug_way,
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output [63:0] io_ic_premux_data,
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output io_ic_sel_premux_data,
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input [1:0] io_ifu_fetch_val,
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output io_ifu_ic_mb_empty,
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output io_ic_dma_active,
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output io_ic_write_stall,
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output io_iccm_dma_ecc_error,
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output io_iccm_dma_rvalid,
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output [63:0] io_iccm_dma_rdata,
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output [2:0] io_iccm_dma_rtag,
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output io_iccm_ready,
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input io_dec_tlu_flush_lower_wb,
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output [1:0] io_iccm_rd_ecc_double_err,
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output io_iccm_dma_sb_error,
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output io_ic_hit_f,
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output [1:0] io_ic_access_fault_f,
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output [1:0] io_ic_access_fault_type_f,
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output io_ifu_async_error_start,
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output [1:0] io_ic_fetch_val_f,
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output [31:0] io_ic_data_f
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_2;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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reg [31:0] _RAND_5;
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reg [31:0] _RAND_6;
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reg [31:0] _RAND_7;
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reg [31:0] _RAND_8;
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reg [31:0] _RAND_9;
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reg [31:0] _RAND_10;
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reg [31:0] _RAND_11;
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reg [31:0] _RAND_12;
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reg [31:0] _RAND_13;
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reg [31:0] _RAND_14;
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reg [31:0] _RAND_15;
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reg [31:0] _RAND_16;
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reg [31:0] _RAND_17;
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reg [31:0] _RAND_18;
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reg [31:0] _RAND_19;
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reg [31:0] _RAND_20;
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reg [31:0] _RAND_21;
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reg [31:0] _RAND_22;
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reg [31:0] _RAND_23;
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reg [31:0] _RAND_24;
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reg [31:0] _RAND_25;
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reg [31:0] _RAND_26;
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reg [31:0] _RAND_27;
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reg [31:0] _RAND_28;
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reg [31:0] _RAND_29;
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reg [31:0] _RAND_30;
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reg [31:0] _RAND_31;
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reg [31:0] _RAND_32;
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reg [31:0] _RAND_33;
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reg [31:0] _RAND_34;
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reg [31:0] _RAND_35;
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reg [31:0] _RAND_36;
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reg [31:0] _RAND_37;
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reg [31:0] _RAND_38;
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reg [31:0] _RAND_39;
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reg [31:0] _RAND_40;
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reg [31:0] _RAND_41;
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reg [31:0] _RAND_42;
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reg [31:0] _RAND_43;
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reg [31:0] _RAND_44;
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reg [31:0] _RAND_45;
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reg [31:0] _RAND_46;
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reg [31:0] _RAND_47;
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reg [31:0] _RAND_48;
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reg [31:0] _RAND_49;
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reg [31:0] _RAND_50;
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reg [31:0] _RAND_51;
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reg [31:0] _RAND_52;
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reg [31:0] _RAND_53;
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reg [31:0] _RAND_54;
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reg [31:0] _RAND_55;
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reg [31:0] _RAND_56;
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reg [31:0] _RAND_57;
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reg [31:0] _RAND_58;
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reg [31:0] _RAND_59;
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reg [31:0] _RAND_60;
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reg [31:0] _RAND_61;
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reg [31:0] _RAND_62;
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reg [31:0] _RAND_63;
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reg [31:0] _RAND_64;
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reg [31:0] _RAND_65;
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reg [31:0] _RAND_66;
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reg [31:0] _RAND_67;
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reg [31:0] _RAND_68;
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reg [31:0] _RAND_69;
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reg [31:0] _RAND_70;
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reg [31:0] _RAND_71;
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reg [31:0] _RAND_72;
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reg [31:0] _RAND_73;
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reg [31:0] _RAND_74;
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reg [31:0] _RAND_75;
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reg [31:0] _RAND_76;
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reg [31:0] _RAND_77;
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reg [31:0] _RAND_78;
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reg [31:0] _RAND_79;
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reg [31:0] _RAND_80;
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reg [31:0] _RAND_81;
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reg [31:0] _RAND_82;
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reg [31:0] _RAND_83;
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reg [31:0] _RAND_84;
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reg [31:0] _RAND_85;
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reg [31:0] _RAND_86;
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reg [31:0] _RAND_87;
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reg [31:0] _RAND_88;
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reg [31:0] _RAND_89;
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reg [31:0] _RAND_90;
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reg [31:0] _RAND_91;
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reg [31:0] _RAND_92;
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reg [31:0] _RAND_93;
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reg [31:0] _RAND_94;
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reg [31:0] _RAND_95;
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reg [31:0] _RAND_96;
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reg [31:0] _RAND_97;
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reg [31:0] _RAND_98;
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reg [31:0] _RAND_99;
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reg [31:0] _RAND_100;
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reg [31:0] _RAND_101;
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reg [31:0] _RAND_102;
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reg [31:0] _RAND_103;
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reg [31:0] _RAND_104;
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reg [31:0] _RAND_105;
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reg [31:0] _RAND_106;
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reg [31:0] _RAND_107;
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reg [31:0] _RAND_108;
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reg [31:0] _RAND_109;
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reg [31:0] _RAND_110;
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reg [31:0] _RAND_111;
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reg [31:0] _RAND_112;
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reg [31:0] _RAND_113;
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reg [31:0] _RAND_114;
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reg [31:0] _RAND_115;
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reg [31:0] _RAND_116;
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reg [31:0] _RAND_117;
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reg [31:0] _RAND_118;
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reg [31:0] _RAND_119;
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reg [31:0] _RAND_120;
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reg [31:0] _RAND_121;
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reg [31:0] _RAND_122;
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reg [31:0] _RAND_123;
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reg [31:0] _RAND_124;
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reg [31:0] _RAND_125;
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reg [31:0] _RAND_126;
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reg [31:0] _RAND_127;
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reg [31:0] _RAND_128;
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reg [31:0] _RAND_129;
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reg [31:0] _RAND_130;
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reg [31:0] _RAND_131;
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reg [31:0] _RAND_132;
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reg [31:0] _RAND_133;
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reg [31:0] _RAND_134;
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reg [31:0] _RAND_135;
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reg [31:0] _RAND_136;
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reg [31:0] _RAND_137;
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reg [31:0] _RAND_138;
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reg [31:0] _RAND_139;
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reg [31:0] _RAND_140;
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reg [31:0] _RAND_141;
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reg [31:0] _RAND_142;
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reg [31:0] _RAND_143;
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reg [31:0] _RAND_144;
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reg [31:0] _RAND_145;
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reg [31:0] _RAND_146;
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reg [31:0] _RAND_147;
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reg [31:0] _RAND_148;
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reg [31:0] _RAND_149;
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reg [31:0] _RAND_150;
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reg [31:0] _RAND_151;
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reg [31:0] _RAND_152;
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reg [31:0] _RAND_153;
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reg [31:0] _RAND_154;
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reg [31:0] _RAND_155;
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reg [31:0] _RAND_156;
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reg [31:0] _RAND_157;
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reg [31:0] _RAND_158;
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reg [31:0] _RAND_159;
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reg [31:0] _RAND_160;
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reg [31:0] _RAND_161;
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reg [31:0] _RAND_162;
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reg [31:0] _RAND_163;
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reg [63:0] _RAND_164;
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reg [31:0] _RAND_165;
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reg [31:0] _RAND_166;
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reg [31:0] _RAND_167;
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reg [31:0] _RAND_168;
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reg [31:0] _RAND_169;
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reg [31:0] _RAND_170;
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reg [31:0] _RAND_171;
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reg [31:0] _RAND_172;
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reg [31:0] _RAND_173;
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reg [31:0] _RAND_174;
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reg [31:0] _RAND_175;
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reg [31:0] _RAND_176;
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reg [31:0] _RAND_177;
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reg [31:0] _RAND_178;
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reg [31:0] _RAND_179;
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reg [31:0] _RAND_180;
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reg [31:0] _RAND_181;
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reg [31:0] _RAND_182;
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reg [31:0] _RAND_183;
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reg [31:0] _RAND_184;
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reg [31:0] _RAND_185;
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reg [31:0] _RAND_186;
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reg [31:0] _RAND_187;
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reg [31:0] _RAND_188;
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reg [31:0] _RAND_189;
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reg [31:0] _RAND_190;
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reg [31:0] _RAND_191;
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reg [31:0] _RAND_192;
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reg [31:0] _RAND_193;
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reg [31:0] _RAND_194;
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reg [31:0] _RAND_195;
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reg [31:0] _RAND_196;
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reg [31:0] _RAND_197;
|
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reg [31:0] _RAND_198;
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reg [31:0] _RAND_199;
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reg [31:0] _RAND_200;
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reg [31:0] _RAND_201;
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reg [31:0] _RAND_202;
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|
reg [31:0] _RAND_203;
|
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reg [31:0] _RAND_204;
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reg [31:0] _RAND_205;
|
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reg [31:0] _RAND_206;
|
|
reg [31:0] _RAND_207;
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|
reg [31:0] _RAND_208;
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|
reg [31:0] _RAND_209;
|
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reg [31:0] _RAND_210;
|
|
reg [31:0] _RAND_211;
|
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reg [31:0] _RAND_212;
|
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reg [31:0] _RAND_213;
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|
reg [31:0] _RAND_214;
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|
reg [31:0] _RAND_215;
|
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reg [31:0] _RAND_216;
|
|
reg [31:0] _RAND_217;
|
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reg [31:0] _RAND_218;
|
|
reg [31:0] _RAND_219;
|
|
reg [31:0] _RAND_220;
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|
reg [31:0] _RAND_221;
|
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reg [31:0] _RAND_222;
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|
reg [31:0] _RAND_223;
|
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reg [31:0] _RAND_224;
|
|
reg [31:0] _RAND_225;
|
|
reg [31:0] _RAND_226;
|
|
reg [31:0] _RAND_227;
|
|
reg [31:0] _RAND_228;
|
|
reg [31:0] _RAND_229;
|
|
reg [31:0] _RAND_230;
|
|
reg [31:0] _RAND_231;
|
|
reg [31:0] _RAND_232;
|
|
reg [31:0] _RAND_233;
|
|
reg [31:0] _RAND_234;
|
|
reg [31:0] _RAND_235;
|
|
reg [31:0] _RAND_236;
|
|
reg [31:0] _RAND_237;
|
|
reg [31:0] _RAND_238;
|
|
reg [31:0] _RAND_239;
|
|
reg [31:0] _RAND_240;
|
|
reg [31:0] _RAND_241;
|
|
reg [31:0] _RAND_242;
|
|
reg [31:0] _RAND_243;
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reg [31:0] _RAND_244;
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|
reg [31:0] _RAND_245;
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|
reg [31:0] _RAND_246;
|
|
reg [31:0] _RAND_247;
|
|
reg [31:0] _RAND_248;
|
|
reg [31:0] _RAND_249;
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reg [31:0] _RAND_250;
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reg [31:0] _RAND_251;
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reg [31:0] _RAND_252;
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reg [31:0] _RAND_253;
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reg [31:0] _RAND_254;
|
|
reg [31:0] _RAND_255;
|
|
reg [31:0] _RAND_256;
|
|
reg [31:0] _RAND_257;
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|
reg [31:0] _RAND_258;
|
|
reg [31:0] _RAND_259;
|
|
reg [31:0] _RAND_260;
|
|
reg [31:0] _RAND_261;
|
|
reg [31:0] _RAND_262;
|
|
reg [31:0] _RAND_263;
|
|
reg [31:0] _RAND_264;
|
|
reg [31:0] _RAND_265;
|
|
reg [31:0] _RAND_266;
|
|
reg [31:0] _RAND_267;
|
|
reg [31:0] _RAND_268;
|
|
reg [31:0] _RAND_269;
|
|
reg [31:0] _RAND_270;
|
|
reg [31:0] _RAND_271;
|
|
reg [31:0] _RAND_272;
|
|
reg [31:0] _RAND_273;
|
|
reg [31:0] _RAND_274;
|
|
reg [31:0] _RAND_275;
|
|
reg [31:0] _RAND_276;
|
|
reg [31:0] _RAND_277;
|
|
reg [31:0] _RAND_278;
|
|
reg [31:0] _RAND_279;
|
|
reg [31:0] _RAND_280;
|
|
reg [31:0] _RAND_281;
|
|
reg [31:0] _RAND_282;
|
|
reg [31:0] _RAND_283;
|
|
reg [31:0] _RAND_284;
|
|
reg [31:0] _RAND_285;
|
|
reg [31:0] _RAND_286;
|
|
reg [31:0] _RAND_287;
|
|
reg [31:0] _RAND_288;
|
|
reg [31:0] _RAND_289;
|
|
reg [31:0] _RAND_290;
|
|
reg [31:0] _RAND_291;
|
|
reg [31:0] _RAND_292;
|
|
reg [31:0] _RAND_293;
|
|
reg [31:0] _RAND_294;
|
|
reg [31:0] _RAND_295;
|
|
reg [31:0] _RAND_296;
|
|
reg [31:0] _RAND_297;
|
|
reg [31:0] _RAND_298;
|
|
reg [31:0] _RAND_299;
|
|
reg [31:0] _RAND_300;
|
|
reg [31:0] _RAND_301;
|
|
reg [31:0] _RAND_302;
|
|
reg [31:0] _RAND_303;
|
|
reg [31:0] _RAND_304;
|
|
reg [31:0] _RAND_305;
|
|
reg [31:0] _RAND_306;
|
|
reg [31:0] _RAND_307;
|
|
reg [31:0] _RAND_308;
|
|
reg [31:0] _RAND_309;
|
|
reg [31:0] _RAND_310;
|
|
reg [31:0] _RAND_311;
|
|
reg [31:0] _RAND_312;
|
|
reg [31:0] _RAND_313;
|
|
reg [31:0] _RAND_314;
|
|
reg [31:0] _RAND_315;
|
|
reg [31:0] _RAND_316;
|
|
reg [31:0] _RAND_317;
|
|
reg [31:0] _RAND_318;
|
|
reg [31:0] _RAND_319;
|
|
reg [31:0] _RAND_320;
|
|
reg [31:0] _RAND_321;
|
|
reg [31:0] _RAND_322;
|
|
reg [31:0] _RAND_323;
|
|
reg [31:0] _RAND_324;
|
|
reg [31:0] _RAND_325;
|
|
reg [31:0] _RAND_326;
|
|
reg [31:0] _RAND_327;
|
|
reg [31:0] _RAND_328;
|
|
reg [31:0] _RAND_329;
|
|
reg [31:0] _RAND_330;
|
|
reg [31:0] _RAND_331;
|
|
reg [31:0] _RAND_332;
|
|
reg [31:0] _RAND_333;
|
|
reg [31:0] _RAND_334;
|
|
reg [31:0] _RAND_335;
|
|
reg [31:0] _RAND_336;
|
|
reg [31:0] _RAND_337;
|
|
reg [31:0] _RAND_338;
|
|
reg [31:0] _RAND_339;
|
|
reg [31:0] _RAND_340;
|
|
reg [31:0] _RAND_341;
|
|
reg [31:0] _RAND_342;
|
|
reg [31:0] _RAND_343;
|
|
reg [31:0] _RAND_344;
|
|
reg [31:0] _RAND_345;
|
|
reg [31:0] _RAND_346;
|
|
reg [31:0] _RAND_347;
|
|
reg [31:0] _RAND_348;
|
|
reg [31:0] _RAND_349;
|
|
reg [31:0] _RAND_350;
|
|
reg [31:0] _RAND_351;
|
|
reg [31:0] _RAND_352;
|
|
reg [31:0] _RAND_353;
|
|
reg [31:0] _RAND_354;
|
|
reg [31:0] _RAND_355;
|
|
reg [31:0] _RAND_356;
|
|
reg [31:0] _RAND_357;
|
|
reg [31:0] _RAND_358;
|
|
reg [31:0] _RAND_359;
|
|
reg [31:0] _RAND_360;
|
|
reg [31:0] _RAND_361;
|
|
reg [31:0] _RAND_362;
|
|
reg [31:0] _RAND_363;
|
|
reg [31:0] _RAND_364;
|
|
reg [31:0] _RAND_365;
|
|
reg [31:0] _RAND_366;
|
|
reg [31:0] _RAND_367;
|
|
reg [31:0] _RAND_368;
|
|
reg [31:0] _RAND_369;
|
|
reg [31:0] _RAND_370;
|
|
reg [31:0] _RAND_371;
|
|
reg [31:0] _RAND_372;
|
|
reg [31:0] _RAND_373;
|
|
reg [31:0] _RAND_374;
|
|
reg [31:0] _RAND_375;
|
|
reg [31:0] _RAND_376;
|
|
reg [31:0] _RAND_377;
|
|
reg [31:0] _RAND_378;
|
|
reg [31:0] _RAND_379;
|
|
reg [31:0] _RAND_380;
|
|
reg [31:0] _RAND_381;
|
|
reg [31:0] _RAND_382;
|
|
reg [31:0] _RAND_383;
|
|
reg [31:0] _RAND_384;
|
|
reg [31:0] _RAND_385;
|
|
reg [31:0] _RAND_386;
|
|
reg [31:0] _RAND_387;
|
|
reg [31:0] _RAND_388;
|
|
reg [31:0] _RAND_389;
|
|
reg [31:0] _RAND_390;
|
|
reg [31:0] _RAND_391;
|
|
reg [31:0] _RAND_392;
|
|
reg [31:0] _RAND_393;
|
|
reg [31:0] _RAND_394;
|
|
reg [31:0] _RAND_395;
|
|
reg [31:0] _RAND_396;
|
|
reg [31:0] _RAND_397;
|
|
reg [31:0] _RAND_398;
|
|
reg [31:0] _RAND_399;
|
|
reg [31:0] _RAND_400;
|
|
reg [31:0] _RAND_401;
|
|
reg [31:0] _RAND_402;
|
|
reg [31:0] _RAND_403;
|
|
reg [31:0] _RAND_404;
|
|
reg [31:0] _RAND_405;
|
|
reg [31:0] _RAND_406;
|
|
reg [31:0] _RAND_407;
|
|
reg [31:0] _RAND_408;
|
|
reg [31:0] _RAND_409;
|
|
reg [31:0] _RAND_410;
|
|
reg [31:0] _RAND_411;
|
|
reg [31:0] _RAND_412;
|
|
reg [31:0] _RAND_413;
|
|
reg [31:0] _RAND_414;
|
|
reg [31:0] _RAND_415;
|
|
reg [31:0] _RAND_416;
|
|
reg [31:0] _RAND_417;
|
|
reg [31:0] _RAND_418;
|
|
reg [31:0] _RAND_419;
|
|
reg [31:0] _RAND_420;
|
|
reg [31:0] _RAND_421;
|
|
reg [31:0] _RAND_422;
|
|
reg [31:0] _RAND_423;
|
|
reg [31:0] _RAND_424;
|
|
reg [31:0] _RAND_425;
|
|
reg [31:0] _RAND_426;
|
|
reg [31:0] _RAND_427;
|
|
reg [31:0] _RAND_428;
|
|
reg [31:0] _RAND_429;
|
|
reg [31:0] _RAND_430;
|
|
reg [31:0] _RAND_431;
|
|
reg [31:0] _RAND_432;
|
|
reg [31:0] _RAND_433;
|
|
reg [31:0] _RAND_434;
|
|
reg [31:0] _RAND_435;
|
|
reg [31:0] _RAND_436;
|
|
reg [31:0] _RAND_437;
|
|
reg [31:0] _RAND_438;
|
|
reg [31:0] _RAND_439;
|
|
reg [31:0] _RAND_440;
|
|
reg [31:0] _RAND_441;
|
|
reg [95:0] _RAND_442;
|
|
reg [31:0] _RAND_443;
|
|
reg [31:0] _RAND_444;
|
|
reg [31:0] _RAND_445;
|
|
reg [31:0] _RAND_446;
|
|
reg [31:0] _RAND_447;
|
|
reg [31:0] _RAND_448;
|
|
reg [31:0] _RAND_449;
|
|
reg [31:0] _RAND_450;
|
|
reg [31:0] _RAND_451;
|
|
reg [63:0] _RAND_452;
|
|
reg [31:0] _RAND_453;
|
|
reg [31:0] _RAND_454;
|
|
reg [31:0] _RAND_455;
|
|
reg [31:0] _RAND_456;
|
|
reg [31:0] _RAND_457;
|
|
reg [63:0] _RAND_458;
|
|
reg [31:0] _RAND_459;
|
|
reg [31:0] _RAND_460;
|
|
reg [31:0] _RAND_461;
|
|
reg [31:0] _RAND_462;
|
|
reg [31:0] _RAND_463;
|
|
reg [31:0] _RAND_464;
|
|
reg [31:0] _RAND_465;
|
|
reg [31:0] _RAND_466;
|
|
reg [31:0] _RAND_467;
|
|
reg [31:0] _RAND_468;
|
|
reg [31:0] _RAND_469;
|
|
reg [31:0] _RAND_470;
|
|
reg [31:0] _RAND_471;
|
|
reg [31:0] _RAND_472;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_23_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_24_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_24_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_25_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_25_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_26_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_26_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_27_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_27_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_28_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_28_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_29_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_29_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_30_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_30_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_31_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_31_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_32_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_32_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_33_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_33_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_34_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_34_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_35_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_35_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_36_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_36_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_37_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_37_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_38_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_38_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_39_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_39_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_40_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_40_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_41_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_41_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_42_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_42_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_43_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_43_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_44_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_44_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_45_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_45_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_46_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_46_io_en; // @[lib.scala 349:22]
|
|
reg flush_final_f; // @[Reg.scala 27:20]
|
|
wire _T = io_exu_flush_final ^ flush_final_f; // @[lib.scala 488:21]
|
|
wire _T_1 = |_T; // @[lib.scala 488:29]
|
|
reg ifc_fetch_req_f_raw; // @[Reg.scala 27:20]
|
|
wire _T_339 = ~io_exu_flush_final; // @[ifu_mem_ctl.scala 225:44]
|
|
wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_339; // @[ifu_mem_ctl.scala 225:42]
|
|
wire _T_3 = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[ifu_mem_ctl.scala 86:53]
|
|
reg [2:0] miss_state; // @[Reg.scala 27:20]
|
|
wire miss_pending = miss_state != 3'h0; // @[ifu_mem_ctl.scala 155:30]
|
|
wire _T_4 = _T_3 | miss_pending; // @[ifu_mem_ctl.scala 86:71]
|
|
wire _T_5 = _T_4 | io_exu_flush_final; // @[ifu_mem_ctl.scala 86:86]
|
|
reg scnd_miss_req_q; // @[Reg.scala 27:20]
|
|
wire scnd_miss_req = scnd_miss_req_q & _T_339; // @[ifu_mem_ctl.scala 458:36]
|
|
wire fetch_bf_f_c1_clken = _T_5 | scnd_miss_req; // @[ifu_mem_ctl.scala 86:107]
|
|
wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 87:42]
|
|
wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
|
|
reg [30:0] ifu_fetch_addr_int_f; // @[Reg.scala 27:20]
|
|
wire [4:0] _GEN_515 = {{1'd0}, ic_fetch_val_int_f}; // @[ifu_mem_ctl.scala 561:53]
|
|
wire [4:0] ic_fetch_val_shift_right = _GEN_515 << ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 561:53]
|
|
wire _T_3199 = |ic_fetch_val_shift_right[3:2]; // @[ifu_mem_ctl.scala 563:91]
|
|
wire _T_3201 = _T_3199 & _T_339; // @[ifu_mem_ctl.scala 563:95]
|
|
reg ifc_iccm_access_f; // @[Reg.scala 27:20]
|
|
wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 177:46]
|
|
wire _T_3202 = _T_3201 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 563:117]
|
|
reg iccm_dma_rvalid_in; // @[Reg.scala 27:20]
|
|
wire _T_3203 = _T_3202 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 563:137]
|
|
wire _T_3204 = ~io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu_mem_ctl.scala 563:161]
|
|
wire _T_3205 = _T_3203 & _T_3204; // @[ifu_mem_ctl.scala 563:159]
|
|
wire _T_3191 = |ic_fetch_val_shift_right[1:0]; // @[ifu_mem_ctl.scala 563:91]
|
|
wire _T_3193 = _T_3191 & _T_339; // @[ifu_mem_ctl.scala 563:95]
|
|
wire _T_3194 = _T_3193 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 563:117]
|
|
wire _T_3195 = _T_3194 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 563:137]
|
|
wire _T_3197 = _T_3195 & _T_3204; // @[ifu_mem_ctl.scala 563:159]
|
|
wire [1:0] iccm_ecc_word_enable = {_T_3205,_T_3197}; // @[Cat.scala 29:58]
|
|
wire _T_3690 = ^io_iccm_rd_data_ecc[70:39]; // @[lib.scala 199:30]
|
|
wire _T_3691 = ^io_iccm_rd_data_ecc[77:71]; // @[lib.scala 199:44]
|
|
wire _T_3692 = _T_3690 ^ _T_3691; // @[lib.scala 199:35]
|
|
wire _T_3693 = 1'h1; // @[lib.scala 199:52]
|
|
wire [5:0] _T_3700 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[65]}; // @[lib.scala 199:76]
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|
wire _T_3701 = ^_T_3700; // @[lib.scala 199:83]
|
|
wire _T_3702 = io_iccm_rd_data_ecc[76] ^ _T_3701; // @[lib.scala 199:71]
|
|
wire [6:0] _T_3709 = {io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[50]}; // @[lib.scala 199:103]
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wire [14:0] _T_3717 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3709}; // @[lib.scala 199:103]
|
|
wire _T_3718 = ^_T_3717; // @[lib.scala 199:110]
|
|
wire _T_3719 = io_iccm_rd_data_ecc[75] ^ _T_3718; // @[lib.scala 199:98]
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|
wire [6:0] _T_3726 = {io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[43]}; // @[lib.scala 199:130]
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wire [14:0] _T_3734 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3726}; // @[lib.scala 199:130]
|
|
wire _T_3735 = ^_T_3734; // @[lib.scala 199:137]
|
|
wire _T_3736 = io_iccm_rd_data_ecc[74] ^ _T_3735; // @[lib.scala 199:125]
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wire [8:0] _T_3745 = {io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[40]}; // @[lib.scala 199:157]
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wire [17:0] _T_3754 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3745}; // @[lib.scala 199:157]
|
|
wire _T_3755 = ^_T_3754; // @[lib.scala 199:164]
|
|
wire _T_3756 = io_iccm_rd_data_ecc[73] ^ _T_3755; // @[lib.scala 199:152]
|
|
wire [8:0] _T_3765 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[39]}; // @[lib.scala 199:184]
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|
wire [17:0] _T_3774 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3765}; // @[lib.scala 199:184]
|
|
wire _T_3775 = ^_T_3774; // @[lib.scala 199:191]
|
|
wire _T_3776 = io_iccm_rd_data_ecc[72] ^ _T_3775; // @[lib.scala 199:179]
|
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wire [8:0] _T_3785 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[50],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[43],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[40],io_iccm_rd_data_ecc[39]}; // @[lib.scala 199:211]
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|
wire [17:0] _T_3794 = {io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[65],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[54],_T_3785}; // @[lib.scala 199:211]
|
|
wire _T_3795 = ^_T_3794; // @[lib.scala 199:218]
|
|
wire _T_3796 = io_iccm_rd_data_ecc[71] ^ _T_3795; // @[lib.scala 199:206]
|
|
wire [6:0] _T_3802 = {_T_3692,_T_3702,_T_3719,_T_3736,_T_3756,_T_3776,_T_3796}; // @[Cat.scala 29:58]
|
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wire _T_3803 = _T_3802 != 7'h0; // @[lib.scala 200:44]
|
|
wire _T_3804 = iccm_ecc_word_enable[1] & _T_3803; // @[lib.scala 200:32]
|
|
wire _T_3806 = _T_3804 & _T_3802[6]; // @[lib.scala 200:53]
|
|
wire _T_3305 = ^io_iccm_rd_data_ecc[31:0]; // @[lib.scala 199:30]
|
|
wire _T_3306 = ^io_iccm_rd_data_ecc[38:32]; // @[lib.scala 199:44]
|
|
wire _T_3307 = _T_3305 ^ _T_3306; // @[lib.scala 199:35]
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|
wire [5:0] _T_3315 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[26]}; // @[lib.scala 199:76]
|
|
wire _T_3316 = ^_T_3315; // @[lib.scala 199:83]
|
|
wire _T_3317 = io_iccm_rd_data_ecc[37] ^ _T_3316; // @[lib.scala 199:71]
|
|
wire [6:0] _T_3324 = {io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[11]}; // @[lib.scala 199:103]
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|
wire [14:0] _T_3332 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3324}; // @[lib.scala 199:103]
|
|
wire _T_3333 = ^_T_3332; // @[lib.scala 199:110]
|
|
wire _T_3334 = io_iccm_rd_data_ecc[36] ^ _T_3333; // @[lib.scala 199:98]
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|
wire [6:0] _T_3341 = {io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[4]}; // @[lib.scala 199:130]
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|
wire [14:0] _T_3349 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3341}; // @[lib.scala 199:130]
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|
wire _T_3350 = ^_T_3349; // @[lib.scala 199:137]
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|
wire _T_3351 = io_iccm_rd_data_ecc[35] ^ _T_3350; // @[lib.scala 199:125]
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|
wire [8:0] _T_3360 = {io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[1]}; // @[lib.scala 199:157]
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|
wire [17:0] _T_3369 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3360}; // @[lib.scala 199:157]
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wire _T_3370 = ^_T_3369; // @[lib.scala 199:164]
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wire _T_3371 = io_iccm_rd_data_ecc[34] ^ _T_3370; // @[lib.scala 199:152]
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wire [8:0] _T_3380 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[0]}; // @[lib.scala 199:184]
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wire [17:0] _T_3389 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3380}; // @[lib.scala 199:184]
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wire _T_3390 = ^_T_3389; // @[lib.scala 199:191]
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wire _T_3391 = io_iccm_rd_data_ecc[33] ^ _T_3390; // @[lib.scala 199:179]
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wire [8:0] _T_3400 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[11],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[4],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[1],io_iccm_rd_data_ecc[0]}; // @[lib.scala 199:211]
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wire [17:0] _T_3409 = {io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[26],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[15],_T_3400}; // @[lib.scala 199:211]
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wire _T_3410 = ^_T_3409; // @[lib.scala 199:218]
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wire _T_3411 = io_iccm_rd_data_ecc[32] ^ _T_3410; // @[lib.scala 199:206]
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wire [6:0] _T_3417 = {_T_3307,_T_3317,_T_3334,_T_3351,_T_3371,_T_3391,_T_3411}; // @[Cat.scala 29:58]
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wire _T_3418 = _T_3417 != 7'h0; // @[lib.scala 200:44]
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wire _T_3419 = iccm_ecc_word_enable[0] & _T_3418; // @[lib.scala 200:32]
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wire _T_3421 = _T_3419 & _T_3417[6]; // @[lib.scala 200:53]
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wire [1:0] iccm_single_ecc_error = {_T_3806,_T_3421}; // @[Cat.scala 29:58]
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wire _T_6 = |iccm_single_ecc_error; // @[ifu_mem_ctl.scala 91:52]
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reg dma_iccm_req_f; // @[Reg.scala 27:20]
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wire _T_9 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 92:74]
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reg [2:0] perr_state; // @[Reg.scala 27:20]
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wire _T_10 = perr_state == 3'h4; // @[ifu_mem_ctl.scala 93:54]
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wire iccm_correct_ecc = perr_state == 3'h3; // @[ifu_mem_ctl.scala 383:34]
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wire _T_11 = iccm_correct_ecc | _T_10; // @[ifu_mem_ctl.scala 93:40]
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reg [1:0] err_stop_state; // @[Reg.scala 27:20]
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wire _T_12 = err_stop_state == 2'h3; // @[ifu_mem_ctl.scala 93:90]
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wire _T_13 = _T_11 | _T_12; // @[ifu_mem_ctl.scala 93:72]
|
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wire _T_2547 = 2'h0 == err_stop_state; // @[Conditional.scala 37:30]
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wire _T_2552 = 2'h1 == err_stop_state; // @[Conditional.scala 37:30]
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wire _T_2572 = io_ifu_fetch_val == 2'h3; // @[ifu_mem_ctl.scala 430:48]
|
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wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[ifu_mem_ctl.scala 297:42]
|
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wire _T_2574 = io_ifu_fetch_val[0] & two_byte_instr; // @[ifu_mem_ctl.scala 430:79]
|
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wire _T_2575 = _T_2572 | _T_2574; // @[ifu_mem_ctl.scala 430:56]
|
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wire _T_2576 = io_exu_flush_final | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 430:122]
|
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wire _T_2577 = ~_T_2576; // @[ifu_mem_ctl.scala 430:101]
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wire _T_2578 = _T_2575 & _T_2577; // @[ifu_mem_ctl.scala 430:99]
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wire _T_2579 = 2'h2 == err_stop_state; // @[Conditional.scala 37:30]
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wire _T_2593 = io_ifu_fetch_val[0] & _T_339; // @[ifu_mem_ctl.scala 437:45]
|
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wire _T_2594 = ~io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 437:69]
|
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wire _T_2595 = _T_2593 & _T_2594; // @[ifu_mem_ctl.scala 437:67]
|
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wire _T_2596 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30]
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wire _GEN_76 = _T_2579 ? _T_2595 : _T_2596; // @[Conditional.scala 39:67]
|
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wire _GEN_80 = _T_2552 ? _T_2578 : _GEN_76; // @[Conditional.scala 39:67]
|
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wire err_stop_fetch = _T_2547 ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
|
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wire _T_14 = _T_13 | err_stop_fetch; // @[ifu_mem_ctl.scala 93:112]
|
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wire _T_16 = io_ifu_axi_r_valid & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 95:45]
|
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wire _T_17 = _T_16 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 95:66]
|
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wire _T_233 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 185:37]
|
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wire _T_234 = ~_T_233; // @[ifu_mem_ctl.scala 185:23]
|
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reg reset_all_tags; // @[Reg.scala 27:20]
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wire _T_235 = _T_234 | reset_all_tags; // @[ifu_mem_ctl.scala 185:41]
|
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wire _T_213 = ~ifc_iccm_access_f; // @[ifu_mem_ctl.scala 176:48]
|
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wire _T_214 = ifc_fetch_req_f & _T_213; // @[ifu_mem_ctl.scala 176:46]
|
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reg ifc_region_acc_fault_final_f; // @[Reg.scala 27:20]
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wire _T_215 = ~ifc_region_acc_fault_final_f; // @[ifu_mem_ctl.scala 176:69]
|
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wire fetch_req_icache_f = _T_214 & _T_215; // @[ifu_mem_ctl.scala 176:67]
|
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wire _T_236 = _T_235 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 185:59]
|
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wire _T_237 = ~miss_pending; // @[ifu_mem_ctl.scala 185:82]
|
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wire _T_238 = _T_236 & _T_237; // @[ifu_mem_ctl.scala 185:80]
|
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wire _T_239 = _T_238 | scnd_miss_req; // @[ifu_mem_ctl.scala 185:97]
|
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wire ic_act_miss_f = _T_239 & _T_215; // @[ifu_mem_ctl.scala 185:114]
|
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reg ifu_bus_rvalid_unq_ff; // @[Reg.scala 27:20]
|
|
reg bus_ifu_bus_clk_en_ff; // @[Reg.scala 27:20]
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|
wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 488:49]
|
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wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 516:41]
|
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reg uncacheable_miss_ff; // @[Reg.scala 27:20]
|
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reg [2:0] bus_data_beat_count; // @[Reg.scala 27:20]
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|
wire _T_2713 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 514:69]
|
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wire _T_2714 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 514:101]
|
|
wire bus_last_data_beat = uncacheable_miss_ff ? _T_2713 : _T_2714; // @[ifu_mem_ctl.scala 514:28]
|
|
wire _T_2654 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 493:68]
|
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wire _T_2655 = ic_act_miss_f | _T_2654; // @[ifu_mem_ctl.scala 493:48]
|
|
wire bus_reset_data_beat_cnt = _T_2655 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 493:91]
|
|
wire _T_2651 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 492:50]
|
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wire _T_2652 = bus_ifu_wr_en_ff & _T_2651; // @[ifu_mem_ctl.scala 492:48]
|
|
wire _T_2653 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 492:72]
|
|
wire bus_inc_data_beat_cnt = _T_2652 & _T_2653; // @[ifu_mem_ctl.scala 492:70]
|
|
wire [2:0] _T_2659 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 496:115]
|
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wire [2:0] _T_2661 = bus_inc_data_beat_cnt ? _T_2659 : 3'h0; // @[Mux.scala 27:72]
|
|
wire _T_2656 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 494:32]
|
|
wire _T_2657 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 494:57]
|
|
wire bus_hold_data_beat_cnt = _T_2656 & _T_2657; // @[ifu_mem_ctl.scala 494:55]
|
|
wire [2:0] _T_2662 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] bus_new_data_beat_count = _T_2661 | _T_2662; // @[Mux.scala 27:72]
|
|
wire _T_18 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 95:114]
|
|
wire _T_19 = _T_17 & _T_18; // @[ifu_mem_ctl.scala 95:87]
|
|
wire _T_20 = ~uncacheable_miss_ff; // @[ifu_mem_ctl.scala 96:5]
|
|
wire _T_21 = _T_19 & _T_20; // @[ifu_mem_ctl.scala 95:120]
|
|
wire _T_22 = miss_state == 3'h5; // @[ifu_mem_ctl.scala 96:41]
|
|
wire _T_27 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
|
|
wire _T_29 = ic_act_miss_f & _T_339; // @[ifu_mem_ctl.scala 102:43]
|
|
wire [2:0] _T_31 = _T_29 ? 3'h1 : 3'h2; // @[ifu_mem_ctl.scala 102:27]
|
|
wire _T_34 = 3'h1 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[ifu_mem_ctl.scala 333:45]
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wire _T_2161 = byp_fetch_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 353:127]
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reg [7:0] ic_miss_buff_data_valid; // @[ifu_mem_ctl.scala 310:62]
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wire _T_2192 = _T_2161 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
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wire _T_2165 = byp_fetch_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2193 = _T_2165 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
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wire _T_2200 = _T_2192 | _T_2193; // @[Mux.scala 27:72]
|
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wire _T_2169 = byp_fetch_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2194 = _T_2169 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
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wire _T_2201 = _T_2200 | _T_2194; // @[Mux.scala 27:72]
|
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wire _T_2173 = byp_fetch_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2195 = _T_2173 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
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wire _T_2202 = _T_2201 | _T_2195; // @[Mux.scala 27:72]
|
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wire _T_2177 = byp_fetch_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2196 = _T_2177 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
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wire _T_2203 = _T_2202 | _T_2196; // @[Mux.scala 27:72]
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wire _T_2181 = byp_fetch_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2197 = _T_2181 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
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wire _T_2204 = _T_2203 | _T_2197; // @[Mux.scala 27:72]
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wire _T_2185 = byp_fetch_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 353:127]
|
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wire _T_2198 = _T_2185 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
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wire _T_2205 = _T_2204 | _T_2198; // @[Mux.scala 27:72]
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wire _T_2189 = byp_fetch_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 353:127]
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wire _T_2199 = _T_2189 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
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wire ic_miss_buff_data_valid_bypass_index = _T_2205 | _T_2199; // @[Mux.scala 27:72]
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wire _T_2247 = ~byp_fetch_index[1]; // @[ifu_mem_ctl.scala 355:69]
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wire _T_2248 = ic_miss_buff_data_valid_bypass_index & _T_2247; // @[ifu_mem_ctl.scala 355:67]
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wire _T_2250 = ~byp_fetch_index[0]; // @[ifu_mem_ctl.scala 355:91]
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wire _T_2251 = _T_2248 & _T_2250; // @[ifu_mem_ctl.scala 355:89]
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wire _T_2256 = _T_2248 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 356:65]
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wire _T_2257 = _T_2251 | _T_2256; // @[ifu_mem_ctl.scala 355:112]
|
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wire _T_2259 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[ifu_mem_ctl.scala 357:43]
|
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wire _T_2262 = _T_2259 & _T_2250; // @[ifu_mem_ctl.scala 357:65]
|
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wire _T_2263 = _T_2257 | _T_2262; // @[ifu_mem_ctl.scala 356:88]
|
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wire _T_2267 = _T_2259 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 358:65]
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wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[ifu_mem_ctl.scala 336:75]
|
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wire _T_2207 = byp_fetch_index_inc == 3'h0; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2231 = _T_2207 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
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wire _T_2210 = byp_fetch_index_inc == 3'h1; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2232 = _T_2210 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
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wire _T_2239 = _T_2231 | _T_2232; // @[Mux.scala 27:72]
|
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wire _T_2213 = byp_fetch_index_inc == 3'h2; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2233 = _T_2213 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
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wire _T_2240 = _T_2239 | _T_2233; // @[Mux.scala 27:72]
|
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wire _T_2216 = byp_fetch_index_inc == 3'h3; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2234 = _T_2216 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
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wire _T_2241 = _T_2240 | _T_2234; // @[Mux.scala 27:72]
|
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wire _T_2219 = byp_fetch_index_inc == 3'h4; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2235 = _T_2219 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
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wire _T_2242 = _T_2241 | _T_2235; // @[Mux.scala 27:72]
|
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wire _T_2222 = byp_fetch_index_inc == 3'h5; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2236 = _T_2222 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
|
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wire _T_2243 = _T_2242 | _T_2236; // @[Mux.scala 27:72]
|
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wire _T_2225 = byp_fetch_index_inc == 3'h6; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2237 = _T_2225 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
|
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wire _T_2244 = _T_2243 | _T_2237; // @[Mux.scala 27:72]
|
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wire _T_2228 = byp_fetch_index_inc == 3'h7; // @[ifu_mem_ctl.scala 354:110]
|
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wire _T_2238 = _T_2228 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
|
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wire ic_miss_buff_data_valid_inc_bypass_index = _T_2244 | _T_2238; // @[Mux.scala 27:72]
|
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wire _T_2268 = _T_2267 & ic_miss_buff_data_valid_inc_bypass_index; // @[ifu_mem_ctl.scala 358:87]
|
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wire _T_2269 = _T_2263 | _T_2268; // @[ifu_mem_ctl.scala 357:88]
|
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wire _T_2273 = ic_miss_buff_data_valid_bypass_index & _T_2189; // @[ifu_mem_ctl.scala 359:43]
|
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wire miss_buff_hit_unq_f = _T_2269 | _T_2273; // @[ifu_mem_ctl.scala 358:131]
|
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wire _T_2289 = miss_state == 3'h4; // @[ifu_mem_ctl.scala 364:55]
|
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wire _T_2290 = miss_state == 3'h1; // @[ifu_mem_ctl.scala 364:87]
|
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wire _T_2291 = _T_2289 | _T_2290; // @[ifu_mem_ctl.scala 364:74]
|
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wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2291; // @[ifu_mem_ctl.scala 364:41]
|
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wire _T_2274 = miss_state == 3'h6; // @[ifu_mem_ctl.scala 361:30]
|
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reg [30:0] imb_ff; // @[Reg.scala 27:20]
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wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[ifu_mem_ctl.scala 352:48]
|
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wire _T_2275 = ~miss_wrap_f; // @[ifu_mem_ctl.scala 361:68]
|
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wire _T_2276 = miss_buff_hit_unq_f & _T_2275; // @[ifu_mem_ctl.scala 361:66]
|
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wire stream_hit_f = _T_2274 & _T_2276; // @[ifu_mem_ctl.scala 361:43]
|
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wire _T_221 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 180:35]
|
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wire _T_222 = _T_221 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 180:52]
|
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wire ic_byp_hit_f = _T_222 & miss_pending; // @[ifu_mem_ctl.scala 180:73]
|
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reg last_data_recieved_ff; // @[Reg.scala 27:20]
|
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wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 526:35]
|
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wire _T_35 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 106:126]
|
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wire _T_36 = last_data_recieved_ff | _T_35; // @[ifu_mem_ctl.scala 106:106]
|
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wire _T_37 = ic_byp_hit_f & _T_36; // @[ifu_mem_ctl.scala 106:80]
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wire _T_38 = _T_37 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 106:140]
|
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wire _T_39 = io_dec_mem_ctrl_dec_tlu_force_halt | _T_38; // @[ifu_mem_ctl.scala 106:64]
|
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wire _T_41 = ~last_data_recieved_ff; // @[ifu_mem_ctl.scala 107:30]
|
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wire _T_42 = ic_byp_hit_f & _T_41; // @[ifu_mem_ctl.scala 107:27]
|
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wire _T_43 = _T_42 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 107:53]
|
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wire _T_45 = ~ic_byp_hit_f; // @[ifu_mem_ctl.scala 108:16]
|
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wire _T_47 = _T_45 & _T_339; // @[ifu_mem_ctl.scala 108:30]
|
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wire _T_49 = _T_47 & _T_35; // @[ifu_mem_ctl.scala 108:52]
|
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wire _T_50 = _T_49 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 108:85]
|
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wire _T_54 = _T_35 & _T_20; // @[ifu_mem_ctl.scala 109:49]
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wire _T_57 = ic_byp_hit_f & _T_339; // @[ifu_mem_ctl.scala 110:33]
|
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wire _T_59 = ~_T_35; // @[ifu_mem_ctl.scala 110:57]
|
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wire _T_60 = _T_57 & _T_59; // @[ifu_mem_ctl.scala 110:55]
|
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wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[ifu_mem_ctl.scala 98:52]
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wire _T_61 = ~ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 110:91]
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wire _T_62 = _T_60 & _T_61; // @[ifu_mem_ctl.scala 110:89]
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wire _T_64 = _T_62 & _T_20; // @[ifu_mem_ctl.scala 110:113]
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wire _T_67 = bus_ifu_wr_en_ff & _T_339; // @[ifu_mem_ctl.scala 111:39]
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wire _T_70 = _T_67 & _T_59; // @[ifu_mem_ctl.scala 111:61]
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wire _T_72 = _T_70 & _T_61; // @[ifu_mem_ctl.scala 111:95]
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wire _T_74 = _T_72 & _T_20; // @[ifu_mem_ctl.scala 111:119]
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wire _T_82 = _T_49 & _T_20; // @[ifu_mem_ctl.scala 112:102]
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wire _T_84 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 113:46]
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wire _T_87 = _T_84 & _T_59; // @[ifu_mem_ctl.scala 113:70]
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wire [2:0] _T_89 = _T_87 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 113:24]
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wire [2:0] _T_90 = _T_82 ? 3'h0 : _T_89; // @[ifu_mem_ctl.scala 112:22]
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wire [2:0] _T_91 = _T_74 ? 3'h6 : _T_90; // @[ifu_mem_ctl.scala 111:20]
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wire [2:0] _T_92 = _T_64 ? 3'h6 : _T_91; // @[ifu_mem_ctl.scala 110:18]
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wire [2:0] _T_93 = _T_54 ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 109:16]
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wire [2:0] _T_94 = _T_50 ? 3'h4 : _T_93; // @[ifu_mem_ctl.scala 108:14]
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wire [2:0] _T_95 = _T_43 ? 3'h3 : _T_94; // @[ifu_mem_ctl.scala 107:12]
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wire [2:0] _T_96 = _T_39 ? 3'h0 : _T_95; // @[ifu_mem_ctl.scala 106:27]
|
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wire _T_105 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
|
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wire _T_109 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
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wire _T_2286 = byp_fetch_index[4:1] == 4'hf; // @[ifu_mem_ctl.scala 363:60]
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wire _T_2287 = _T_2286 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 363:94]
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wire stream_eol_f = _T_2287 & stream_hit_f; // @[ifu_mem_ctl.scala 363:112]
|
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wire _T_111 = _T_84 | stream_eol_f; // @[ifu_mem_ctl.scala 121:72]
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wire _T_114 = _T_111 & _T_59; // @[ifu_mem_ctl.scala 121:87]
|
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wire _T_116 = _T_114 & _T_2653; // @[ifu_mem_ctl.scala 121:122]
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wire [2:0] _T_118 = _T_116 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 121:27]
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wire _T_124 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
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wire _T_127 = io_exu_flush_final & _T_59; // @[ifu_mem_ctl.scala 125:48]
|
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wire _T_129 = _T_127 & _T_2653; // @[ifu_mem_ctl.scala 125:82]
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wire [2:0] _T_131 = _T_129 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 125:27]
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wire _T_135 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
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wire _T_242 = io_ic_rd_hit == 2'h0; // @[ifu_mem_ctl.scala 186:28]
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wire _T_243 = _T_242 | reset_all_tags; // @[ifu_mem_ctl.scala 186:42]
|
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wire _T_244 = _T_243 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 186:60]
|
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wire _T_245 = miss_state == 3'h2; // @[ifu_mem_ctl.scala 186:94]
|
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wire _T_246 = _T_244 & _T_245; // @[ifu_mem_ctl.scala 186:81]
|
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wire _T_249 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 187:39]
|
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wire _T_250 = _T_246 & _T_249; // @[ifu_mem_ctl.scala 186:111]
|
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wire _T_252 = _T_250 & _T_20; // @[ifu_mem_ctl.scala 187:91]
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reg sel_mb_addr_ff; // @[Reg.scala 27:20]
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wire _T_253 = ~sel_mb_addr_ff; // @[ifu_mem_ctl.scala 187:116]
|
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wire _T_254 = _T_252 & _T_253; // @[ifu_mem_ctl.scala 187:114]
|
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wire ic_miss_under_miss_f = _T_254 & _T_215; // @[ifu_mem_ctl.scala 187:132]
|
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wire _T_138 = ic_miss_under_miss_f & _T_59; // @[ifu_mem_ctl.scala 129:50]
|
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wire _T_140 = _T_138 & _T_2653; // @[ifu_mem_ctl.scala 129:84]
|
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wire _T_262 = _T_236 & _T_245; // @[ifu_mem_ctl.scala 188:85]
|
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wire _T_265 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 189:39]
|
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wire _T_266 = _T_265 | uncacheable_miss_ff; // @[ifu_mem_ctl.scala 189:91]
|
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wire ic_ignore_2nd_miss_f = _T_262 & _T_266; // @[ifu_mem_ctl.scala 188:117]
|
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wire _T_144 = ic_ignore_2nd_miss_f & _T_59; // @[ifu_mem_ctl.scala 130:35]
|
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wire _T_146 = _T_144 & _T_2653; // @[ifu_mem_ctl.scala 130:69]
|
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wire [2:0] _T_148 = _T_146 ? 3'h7 : 3'h0; // @[ifu_mem_ctl.scala 130:12]
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wire [2:0] _T_149 = _T_140 ? 3'h5 : _T_148; // @[ifu_mem_ctl.scala 129:27]
|
|
wire _T_154 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [2:0] _T_157 = _T_35 ? 3'h0 : 3'h2; // @[ifu_mem_ctl.scala 135:12]
|
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wire [2:0] _T_158 = io_exu_flush_final ? _T_157 : 3'h1; // @[ifu_mem_ctl.scala 134:75]
|
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wire [2:0] _T_159 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_158; // @[ifu_mem_ctl.scala 134:27]
|
|
wire _T_163 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
|
|
wire [2:0] _T_167 = io_exu_flush_final ? _T_157 : 3'h0; // @[ifu_mem_ctl.scala 139:75]
|
|
wire [2:0] _T_168 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_167; // @[ifu_mem_ctl.scala 139:27]
|
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wire [2:0] _GEN_1 = _T_163 ? _T_168 : 3'h0; // @[Conditional.scala 39:67]
|
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wire [2:0] _GEN_3 = _T_154 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67]
|
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wire [2:0] _GEN_5 = _T_135 ? _T_149 : _GEN_3; // @[Conditional.scala 39:67]
|
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wire [2:0] _GEN_7 = _T_124 ? _T_131 : _GEN_5; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_9 = _T_109 ? _T_118 : _GEN_7; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_11 = _T_105 ? 3'h0 : _GEN_9; // @[Conditional.scala 39:67]
|
|
wire [2:0] _GEN_13 = _T_34 ? _T_96 : _GEN_11; // @[Conditional.scala 39:67]
|
|
wire [2:0] miss_nxtstate = _T_27 ? _T_31 : _GEN_13; // @[Conditional.scala 40:58]
|
|
wire _T_23 = miss_nxtstate == 3'h5; // @[ifu_mem_ctl.scala 96:73]
|
|
wire _T_24 = _T_22 | _T_23; // @[ifu_mem_ctl.scala 96:57]
|
|
wire _T_25 = _T_21 & _T_24; // @[ifu_mem_ctl.scala 96:26]
|
|
wire scnd_miss_req_in = _T_25 & _T_339; // @[ifu_mem_ctl.scala 96:91]
|
|
wire _T_33 = ic_act_miss_f & _T_2653; // @[ifu_mem_ctl.scala 103:38]
|
|
wire _T_97 = io_dec_mem_ctrl_dec_tlu_force_halt | io_exu_flush_final; // @[ifu_mem_ctl.scala 114:59]
|
|
wire _T_98 = _T_97 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 114:80]
|
|
wire _T_99 = _T_98 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 114:95]
|
|
wire _T_101 = _T_99 | _T_35; // @[ifu_mem_ctl.scala 114:118]
|
|
wire _T_103 = bus_ifu_wr_en_ff & _T_20; // @[ifu_mem_ctl.scala 114:171]
|
|
wire _T_104 = _T_101 | _T_103; // @[ifu_mem_ctl.scala 114:151]
|
|
wire _T_106 = io_exu_flush_final | flush_final_f; // @[ifu_mem_ctl.scala 118:43]
|
|
wire _T_107 = _T_106 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 118:59]
|
|
wire _T_108 = _T_107 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 118:74]
|
|
wire _T_122 = _T_111 | _T_35; // @[ifu_mem_ctl.scala 122:84]
|
|
wire _T_123 = _T_122 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 122:118]
|
|
wire _T_133 = io_exu_flush_final | _T_35; // @[ifu_mem_ctl.scala 126:43]
|
|
wire _T_134 = _T_133 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:76]
|
|
wire _T_151 = _T_35 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 131:55]
|
|
wire _T_152 = _T_151 | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 131:78]
|
|
wire _T_153 = _T_152 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 131:101]
|
|
wire _T_161 = _T_35 | io_exu_flush_final; // @[ifu_mem_ctl.scala 136:55]
|
|
wire _T_162 = _T_161 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 136:76]
|
|
wire _GEN_2 = _T_163 & _T_162; // @[Conditional.scala 39:67]
|
|
wire _GEN_4 = _T_154 ? _T_162 : _GEN_2; // @[Conditional.scala 39:67]
|
|
wire _GEN_6 = _T_135 ? _T_153 : _GEN_4; // @[Conditional.scala 39:67]
|
|
wire _GEN_8 = _T_124 ? _T_134 : _GEN_6; // @[Conditional.scala 39:67]
|
|
wire _GEN_10 = _T_109 ? _T_123 : _GEN_8; // @[Conditional.scala 39:67]
|
|
wire _GEN_12 = _T_105 ? _T_108 : _GEN_10; // @[Conditional.scala 39:67]
|
|
wire _GEN_14 = _T_34 ? _T_104 : _GEN_12; // @[Conditional.scala 39:67]
|
|
wire miss_state_en = _T_27 ? _T_33 : _GEN_14; // @[Conditional.scala 40:58]
|
|
wire _T_177 = ~flush_final_f; // @[ifu_mem_ctl.scala 156:95]
|
|
wire _T_178 = _T_2289 & _T_177; // @[ifu_mem_ctl.scala 156:93]
|
|
wire crit_wd_byp_ok_ff = _T_2290 | _T_178; // @[ifu_mem_ctl.scala 156:58]
|
|
wire _T_181 = miss_pending & _T_59; // @[ifu_mem_ctl.scala 157:36]
|
|
wire _T_183 = _T_2289 & io_exu_flush_final; // @[ifu_mem_ctl.scala 157:106]
|
|
wire _T_184 = ~_T_183; // @[ifu_mem_ctl.scala 157:72]
|
|
wire _T_185 = _T_181 & _T_184; // @[ifu_mem_ctl.scala 157:70]
|
|
wire _T_187 = _T_2289 & crit_byp_hit_f; // @[ifu_mem_ctl.scala 158:39]
|
|
wire _T_188 = ~_T_187; // @[ifu_mem_ctl.scala 158:5]
|
|
wire _T_189 = _T_185 & _T_188; // @[ifu_mem_ctl.scala 157:128]
|
|
wire _T_190 = _T_189 | ic_act_miss_f; // @[ifu_mem_ctl.scala 158:59]
|
|
wire _T_191 = miss_nxtstate == 3'h4; // @[ifu_mem_ctl.scala 159:36]
|
|
wire _T_192 = miss_pending & _T_191; // @[ifu_mem_ctl.scala 159:19]
|
|
wire sel_hold_imb = _T_190 | _T_192; // @[ifu_mem_ctl.scala 158:75]
|
|
wire _T_194 = _T_22 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 161:57]
|
|
wire sel_hold_imb_scnd = _T_194 & _T_177; // @[ifu_mem_ctl.scala 161:81]
|
|
reg way_status_mb_scnd_ff; // @[Reg.scala 27:20]
|
|
reg [6:0] ifu_ic_rw_int_addr_ff; // @[Reg.scala 27:20]
|
|
wire _T_4900 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_0; // @[Reg.scala 27:20]
|
|
wire _T_5028 = _T_4900 & way_status_out_0; // @[Mux.scala 27:72]
|
|
wire _T_4901 = ifu_ic_rw_int_addr_ff == 7'h1; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_1; // @[Reg.scala 27:20]
|
|
wire _T_5029 = _T_4901 & way_status_out_1; // @[Mux.scala 27:72]
|
|
wire _T_5156 = _T_5028 | _T_5029; // @[Mux.scala 27:72]
|
|
wire _T_4902 = ifu_ic_rw_int_addr_ff == 7'h2; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_2; // @[Reg.scala 27:20]
|
|
wire _T_5030 = _T_4902 & way_status_out_2; // @[Mux.scala 27:72]
|
|
wire _T_5157 = _T_5156 | _T_5030; // @[Mux.scala 27:72]
|
|
wire _T_4903 = ifu_ic_rw_int_addr_ff == 7'h3; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_3; // @[Reg.scala 27:20]
|
|
wire _T_5031 = _T_4903 & way_status_out_3; // @[Mux.scala 27:72]
|
|
wire _T_5158 = _T_5157 | _T_5031; // @[Mux.scala 27:72]
|
|
wire _T_4904 = ifu_ic_rw_int_addr_ff == 7'h4; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_4; // @[Reg.scala 27:20]
|
|
wire _T_5032 = _T_4904 & way_status_out_4; // @[Mux.scala 27:72]
|
|
wire _T_5159 = _T_5158 | _T_5032; // @[Mux.scala 27:72]
|
|
wire _T_4905 = ifu_ic_rw_int_addr_ff == 7'h5; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_5; // @[Reg.scala 27:20]
|
|
wire _T_5033 = _T_4905 & way_status_out_5; // @[Mux.scala 27:72]
|
|
wire _T_5160 = _T_5159 | _T_5033; // @[Mux.scala 27:72]
|
|
wire _T_4906 = ifu_ic_rw_int_addr_ff == 7'h6; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_6; // @[Reg.scala 27:20]
|
|
wire _T_5034 = _T_4906 & way_status_out_6; // @[Mux.scala 27:72]
|
|
wire _T_5161 = _T_5160 | _T_5034; // @[Mux.scala 27:72]
|
|
wire _T_4907 = ifu_ic_rw_int_addr_ff == 7'h7; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_7; // @[Reg.scala 27:20]
|
|
wire _T_5035 = _T_4907 & way_status_out_7; // @[Mux.scala 27:72]
|
|
wire _T_5162 = _T_5161 | _T_5035; // @[Mux.scala 27:72]
|
|
wire _T_4908 = ifu_ic_rw_int_addr_ff == 7'h8; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_8; // @[Reg.scala 27:20]
|
|
wire _T_5036 = _T_4908 & way_status_out_8; // @[Mux.scala 27:72]
|
|
wire _T_5163 = _T_5162 | _T_5036; // @[Mux.scala 27:72]
|
|
wire _T_4909 = ifu_ic_rw_int_addr_ff == 7'h9; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_9; // @[Reg.scala 27:20]
|
|
wire _T_5037 = _T_4909 & way_status_out_9; // @[Mux.scala 27:72]
|
|
wire _T_5164 = _T_5163 | _T_5037; // @[Mux.scala 27:72]
|
|
wire _T_4910 = ifu_ic_rw_int_addr_ff == 7'ha; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_10; // @[Reg.scala 27:20]
|
|
wire _T_5038 = _T_4910 & way_status_out_10; // @[Mux.scala 27:72]
|
|
wire _T_5165 = _T_5164 | _T_5038; // @[Mux.scala 27:72]
|
|
wire _T_4911 = ifu_ic_rw_int_addr_ff == 7'hb; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_11; // @[Reg.scala 27:20]
|
|
wire _T_5039 = _T_4911 & way_status_out_11; // @[Mux.scala 27:72]
|
|
wire _T_5166 = _T_5165 | _T_5039; // @[Mux.scala 27:72]
|
|
wire _T_4912 = ifu_ic_rw_int_addr_ff == 7'hc; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_12; // @[Reg.scala 27:20]
|
|
wire _T_5040 = _T_4912 & way_status_out_12; // @[Mux.scala 27:72]
|
|
wire _T_5167 = _T_5166 | _T_5040; // @[Mux.scala 27:72]
|
|
wire _T_4913 = ifu_ic_rw_int_addr_ff == 7'hd; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_13; // @[Reg.scala 27:20]
|
|
wire _T_5041 = _T_4913 & way_status_out_13; // @[Mux.scala 27:72]
|
|
wire _T_5168 = _T_5167 | _T_5041; // @[Mux.scala 27:72]
|
|
wire _T_4914 = ifu_ic_rw_int_addr_ff == 7'he; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_14; // @[Reg.scala 27:20]
|
|
wire _T_5042 = _T_4914 & way_status_out_14; // @[Mux.scala 27:72]
|
|
wire _T_5169 = _T_5168 | _T_5042; // @[Mux.scala 27:72]
|
|
wire _T_4915 = ifu_ic_rw_int_addr_ff == 7'hf; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_15; // @[Reg.scala 27:20]
|
|
wire _T_5043 = _T_4915 & way_status_out_15; // @[Mux.scala 27:72]
|
|
wire _T_5170 = _T_5169 | _T_5043; // @[Mux.scala 27:72]
|
|
wire _T_4916 = ifu_ic_rw_int_addr_ff == 7'h10; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_16; // @[Reg.scala 27:20]
|
|
wire _T_5044 = _T_4916 & way_status_out_16; // @[Mux.scala 27:72]
|
|
wire _T_5171 = _T_5170 | _T_5044; // @[Mux.scala 27:72]
|
|
wire _T_4917 = ifu_ic_rw_int_addr_ff == 7'h11; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_17; // @[Reg.scala 27:20]
|
|
wire _T_5045 = _T_4917 & way_status_out_17; // @[Mux.scala 27:72]
|
|
wire _T_5172 = _T_5171 | _T_5045; // @[Mux.scala 27:72]
|
|
wire _T_4918 = ifu_ic_rw_int_addr_ff == 7'h12; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_18; // @[Reg.scala 27:20]
|
|
wire _T_5046 = _T_4918 & way_status_out_18; // @[Mux.scala 27:72]
|
|
wire _T_5173 = _T_5172 | _T_5046; // @[Mux.scala 27:72]
|
|
wire _T_4919 = ifu_ic_rw_int_addr_ff == 7'h13; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_19; // @[Reg.scala 27:20]
|
|
wire _T_5047 = _T_4919 & way_status_out_19; // @[Mux.scala 27:72]
|
|
wire _T_5174 = _T_5173 | _T_5047; // @[Mux.scala 27:72]
|
|
wire _T_4920 = ifu_ic_rw_int_addr_ff == 7'h14; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_20; // @[Reg.scala 27:20]
|
|
wire _T_5048 = _T_4920 & way_status_out_20; // @[Mux.scala 27:72]
|
|
wire _T_5175 = _T_5174 | _T_5048; // @[Mux.scala 27:72]
|
|
wire _T_4921 = ifu_ic_rw_int_addr_ff == 7'h15; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_21; // @[Reg.scala 27:20]
|
|
wire _T_5049 = _T_4921 & way_status_out_21; // @[Mux.scala 27:72]
|
|
wire _T_5176 = _T_5175 | _T_5049; // @[Mux.scala 27:72]
|
|
wire _T_4922 = ifu_ic_rw_int_addr_ff == 7'h16; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_22; // @[Reg.scala 27:20]
|
|
wire _T_5050 = _T_4922 & way_status_out_22; // @[Mux.scala 27:72]
|
|
wire _T_5177 = _T_5176 | _T_5050; // @[Mux.scala 27:72]
|
|
wire _T_4923 = ifu_ic_rw_int_addr_ff == 7'h17; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_23; // @[Reg.scala 27:20]
|
|
wire _T_5051 = _T_4923 & way_status_out_23; // @[Mux.scala 27:72]
|
|
wire _T_5178 = _T_5177 | _T_5051; // @[Mux.scala 27:72]
|
|
wire _T_4924 = ifu_ic_rw_int_addr_ff == 7'h18; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_24; // @[Reg.scala 27:20]
|
|
wire _T_5052 = _T_4924 & way_status_out_24; // @[Mux.scala 27:72]
|
|
wire _T_5179 = _T_5178 | _T_5052; // @[Mux.scala 27:72]
|
|
wire _T_4925 = ifu_ic_rw_int_addr_ff == 7'h19; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_25; // @[Reg.scala 27:20]
|
|
wire _T_5053 = _T_4925 & way_status_out_25; // @[Mux.scala 27:72]
|
|
wire _T_5180 = _T_5179 | _T_5053; // @[Mux.scala 27:72]
|
|
wire _T_4926 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_26; // @[Reg.scala 27:20]
|
|
wire _T_5054 = _T_4926 & way_status_out_26; // @[Mux.scala 27:72]
|
|
wire _T_5181 = _T_5180 | _T_5054; // @[Mux.scala 27:72]
|
|
wire _T_4927 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_27; // @[Reg.scala 27:20]
|
|
wire _T_5055 = _T_4927 & way_status_out_27; // @[Mux.scala 27:72]
|
|
wire _T_5182 = _T_5181 | _T_5055; // @[Mux.scala 27:72]
|
|
wire _T_4928 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_28; // @[Reg.scala 27:20]
|
|
wire _T_5056 = _T_4928 & way_status_out_28; // @[Mux.scala 27:72]
|
|
wire _T_5183 = _T_5182 | _T_5056; // @[Mux.scala 27:72]
|
|
wire _T_4929 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_29; // @[Reg.scala 27:20]
|
|
wire _T_5057 = _T_4929 & way_status_out_29; // @[Mux.scala 27:72]
|
|
wire _T_5184 = _T_5183 | _T_5057; // @[Mux.scala 27:72]
|
|
wire _T_4930 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_30; // @[Reg.scala 27:20]
|
|
wire _T_5058 = _T_4930 & way_status_out_30; // @[Mux.scala 27:72]
|
|
wire _T_5185 = _T_5184 | _T_5058; // @[Mux.scala 27:72]
|
|
wire _T_4931 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_31; // @[Reg.scala 27:20]
|
|
wire _T_5059 = _T_4931 & way_status_out_31; // @[Mux.scala 27:72]
|
|
wire _T_5186 = _T_5185 | _T_5059; // @[Mux.scala 27:72]
|
|
wire _T_4932 = ifu_ic_rw_int_addr_ff == 7'h20; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_32; // @[Reg.scala 27:20]
|
|
wire _T_5060 = _T_4932 & way_status_out_32; // @[Mux.scala 27:72]
|
|
wire _T_5187 = _T_5186 | _T_5060; // @[Mux.scala 27:72]
|
|
wire _T_4933 = ifu_ic_rw_int_addr_ff == 7'h21; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_33; // @[Reg.scala 27:20]
|
|
wire _T_5061 = _T_4933 & way_status_out_33; // @[Mux.scala 27:72]
|
|
wire _T_5188 = _T_5187 | _T_5061; // @[Mux.scala 27:72]
|
|
wire _T_4934 = ifu_ic_rw_int_addr_ff == 7'h22; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_34; // @[Reg.scala 27:20]
|
|
wire _T_5062 = _T_4934 & way_status_out_34; // @[Mux.scala 27:72]
|
|
wire _T_5189 = _T_5188 | _T_5062; // @[Mux.scala 27:72]
|
|
wire _T_4935 = ifu_ic_rw_int_addr_ff == 7'h23; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_35; // @[Reg.scala 27:20]
|
|
wire _T_5063 = _T_4935 & way_status_out_35; // @[Mux.scala 27:72]
|
|
wire _T_5190 = _T_5189 | _T_5063; // @[Mux.scala 27:72]
|
|
wire _T_4936 = ifu_ic_rw_int_addr_ff == 7'h24; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_36; // @[Reg.scala 27:20]
|
|
wire _T_5064 = _T_4936 & way_status_out_36; // @[Mux.scala 27:72]
|
|
wire _T_5191 = _T_5190 | _T_5064; // @[Mux.scala 27:72]
|
|
wire _T_4937 = ifu_ic_rw_int_addr_ff == 7'h25; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_37; // @[Reg.scala 27:20]
|
|
wire _T_5065 = _T_4937 & way_status_out_37; // @[Mux.scala 27:72]
|
|
wire _T_5192 = _T_5191 | _T_5065; // @[Mux.scala 27:72]
|
|
wire _T_4938 = ifu_ic_rw_int_addr_ff == 7'h26; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_38; // @[Reg.scala 27:20]
|
|
wire _T_5066 = _T_4938 & way_status_out_38; // @[Mux.scala 27:72]
|
|
wire _T_5193 = _T_5192 | _T_5066; // @[Mux.scala 27:72]
|
|
wire _T_4939 = ifu_ic_rw_int_addr_ff == 7'h27; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_39; // @[Reg.scala 27:20]
|
|
wire _T_5067 = _T_4939 & way_status_out_39; // @[Mux.scala 27:72]
|
|
wire _T_5194 = _T_5193 | _T_5067; // @[Mux.scala 27:72]
|
|
wire _T_4940 = ifu_ic_rw_int_addr_ff == 7'h28; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_40; // @[Reg.scala 27:20]
|
|
wire _T_5068 = _T_4940 & way_status_out_40; // @[Mux.scala 27:72]
|
|
wire _T_5195 = _T_5194 | _T_5068; // @[Mux.scala 27:72]
|
|
wire _T_4941 = ifu_ic_rw_int_addr_ff == 7'h29; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_41; // @[Reg.scala 27:20]
|
|
wire _T_5069 = _T_4941 & way_status_out_41; // @[Mux.scala 27:72]
|
|
wire _T_5196 = _T_5195 | _T_5069; // @[Mux.scala 27:72]
|
|
wire _T_4942 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_42; // @[Reg.scala 27:20]
|
|
wire _T_5070 = _T_4942 & way_status_out_42; // @[Mux.scala 27:72]
|
|
wire _T_5197 = _T_5196 | _T_5070; // @[Mux.scala 27:72]
|
|
wire _T_4943 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_43; // @[Reg.scala 27:20]
|
|
wire _T_5071 = _T_4943 & way_status_out_43; // @[Mux.scala 27:72]
|
|
wire _T_5198 = _T_5197 | _T_5071; // @[Mux.scala 27:72]
|
|
wire _T_4944 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_44; // @[Reg.scala 27:20]
|
|
wire _T_5072 = _T_4944 & way_status_out_44; // @[Mux.scala 27:72]
|
|
wire _T_5199 = _T_5198 | _T_5072; // @[Mux.scala 27:72]
|
|
wire _T_4945 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_45; // @[Reg.scala 27:20]
|
|
wire _T_5073 = _T_4945 & way_status_out_45; // @[Mux.scala 27:72]
|
|
wire _T_5200 = _T_5199 | _T_5073; // @[Mux.scala 27:72]
|
|
wire _T_4946 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_46; // @[Reg.scala 27:20]
|
|
wire _T_5074 = _T_4946 & way_status_out_46; // @[Mux.scala 27:72]
|
|
wire _T_5201 = _T_5200 | _T_5074; // @[Mux.scala 27:72]
|
|
wire _T_4947 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_47; // @[Reg.scala 27:20]
|
|
wire _T_5075 = _T_4947 & way_status_out_47; // @[Mux.scala 27:72]
|
|
wire _T_5202 = _T_5201 | _T_5075; // @[Mux.scala 27:72]
|
|
wire _T_4948 = ifu_ic_rw_int_addr_ff == 7'h30; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_48; // @[Reg.scala 27:20]
|
|
wire _T_5076 = _T_4948 & way_status_out_48; // @[Mux.scala 27:72]
|
|
wire _T_5203 = _T_5202 | _T_5076; // @[Mux.scala 27:72]
|
|
wire _T_4949 = ifu_ic_rw_int_addr_ff == 7'h31; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_49; // @[Reg.scala 27:20]
|
|
wire _T_5077 = _T_4949 & way_status_out_49; // @[Mux.scala 27:72]
|
|
wire _T_5204 = _T_5203 | _T_5077; // @[Mux.scala 27:72]
|
|
wire _T_4950 = ifu_ic_rw_int_addr_ff == 7'h32; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_50; // @[Reg.scala 27:20]
|
|
wire _T_5078 = _T_4950 & way_status_out_50; // @[Mux.scala 27:72]
|
|
wire _T_5205 = _T_5204 | _T_5078; // @[Mux.scala 27:72]
|
|
wire _T_4951 = ifu_ic_rw_int_addr_ff == 7'h33; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_51; // @[Reg.scala 27:20]
|
|
wire _T_5079 = _T_4951 & way_status_out_51; // @[Mux.scala 27:72]
|
|
wire _T_5206 = _T_5205 | _T_5079; // @[Mux.scala 27:72]
|
|
wire _T_4952 = ifu_ic_rw_int_addr_ff == 7'h34; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_52; // @[Reg.scala 27:20]
|
|
wire _T_5080 = _T_4952 & way_status_out_52; // @[Mux.scala 27:72]
|
|
wire _T_5207 = _T_5206 | _T_5080; // @[Mux.scala 27:72]
|
|
wire _T_4953 = ifu_ic_rw_int_addr_ff == 7'h35; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_53; // @[Reg.scala 27:20]
|
|
wire _T_5081 = _T_4953 & way_status_out_53; // @[Mux.scala 27:72]
|
|
wire _T_5208 = _T_5207 | _T_5081; // @[Mux.scala 27:72]
|
|
wire _T_4954 = ifu_ic_rw_int_addr_ff == 7'h36; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_54; // @[Reg.scala 27:20]
|
|
wire _T_5082 = _T_4954 & way_status_out_54; // @[Mux.scala 27:72]
|
|
wire _T_5209 = _T_5208 | _T_5082; // @[Mux.scala 27:72]
|
|
wire _T_4955 = ifu_ic_rw_int_addr_ff == 7'h37; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_55; // @[Reg.scala 27:20]
|
|
wire _T_5083 = _T_4955 & way_status_out_55; // @[Mux.scala 27:72]
|
|
wire _T_5210 = _T_5209 | _T_5083; // @[Mux.scala 27:72]
|
|
wire _T_4956 = ifu_ic_rw_int_addr_ff == 7'h38; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_56; // @[Reg.scala 27:20]
|
|
wire _T_5084 = _T_4956 & way_status_out_56; // @[Mux.scala 27:72]
|
|
wire _T_5211 = _T_5210 | _T_5084; // @[Mux.scala 27:72]
|
|
wire _T_4957 = ifu_ic_rw_int_addr_ff == 7'h39; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_57; // @[Reg.scala 27:20]
|
|
wire _T_5085 = _T_4957 & way_status_out_57; // @[Mux.scala 27:72]
|
|
wire _T_5212 = _T_5211 | _T_5085; // @[Mux.scala 27:72]
|
|
wire _T_4958 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_58; // @[Reg.scala 27:20]
|
|
wire _T_5086 = _T_4958 & way_status_out_58; // @[Mux.scala 27:72]
|
|
wire _T_5213 = _T_5212 | _T_5086; // @[Mux.scala 27:72]
|
|
wire _T_4959 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_59; // @[Reg.scala 27:20]
|
|
wire _T_5087 = _T_4959 & way_status_out_59; // @[Mux.scala 27:72]
|
|
wire _T_5214 = _T_5213 | _T_5087; // @[Mux.scala 27:72]
|
|
wire _T_4960 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_60; // @[Reg.scala 27:20]
|
|
wire _T_5088 = _T_4960 & way_status_out_60; // @[Mux.scala 27:72]
|
|
wire _T_5215 = _T_5214 | _T_5088; // @[Mux.scala 27:72]
|
|
wire _T_4961 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_61; // @[Reg.scala 27:20]
|
|
wire _T_5089 = _T_4961 & way_status_out_61; // @[Mux.scala 27:72]
|
|
wire _T_5216 = _T_5215 | _T_5089; // @[Mux.scala 27:72]
|
|
wire _T_4962 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_62; // @[Reg.scala 27:20]
|
|
wire _T_5090 = _T_4962 & way_status_out_62; // @[Mux.scala 27:72]
|
|
wire _T_5217 = _T_5216 | _T_5090; // @[Mux.scala 27:72]
|
|
wire _T_4963 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_63; // @[Reg.scala 27:20]
|
|
wire _T_5091 = _T_4963 & way_status_out_63; // @[Mux.scala 27:72]
|
|
wire _T_5218 = _T_5217 | _T_5091; // @[Mux.scala 27:72]
|
|
wire _T_4964 = ifu_ic_rw_int_addr_ff == 7'h40; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_64; // @[Reg.scala 27:20]
|
|
wire _T_5092 = _T_4964 & way_status_out_64; // @[Mux.scala 27:72]
|
|
wire _T_5219 = _T_5218 | _T_5092; // @[Mux.scala 27:72]
|
|
wire _T_4965 = ifu_ic_rw_int_addr_ff == 7'h41; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_65; // @[Reg.scala 27:20]
|
|
wire _T_5093 = _T_4965 & way_status_out_65; // @[Mux.scala 27:72]
|
|
wire _T_5220 = _T_5219 | _T_5093; // @[Mux.scala 27:72]
|
|
wire _T_4966 = ifu_ic_rw_int_addr_ff == 7'h42; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_66; // @[Reg.scala 27:20]
|
|
wire _T_5094 = _T_4966 & way_status_out_66; // @[Mux.scala 27:72]
|
|
wire _T_5221 = _T_5220 | _T_5094; // @[Mux.scala 27:72]
|
|
wire _T_4967 = ifu_ic_rw_int_addr_ff == 7'h43; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_67; // @[Reg.scala 27:20]
|
|
wire _T_5095 = _T_4967 & way_status_out_67; // @[Mux.scala 27:72]
|
|
wire _T_5222 = _T_5221 | _T_5095; // @[Mux.scala 27:72]
|
|
wire _T_4968 = ifu_ic_rw_int_addr_ff == 7'h44; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_68; // @[Reg.scala 27:20]
|
|
wire _T_5096 = _T_4968 & way_status_out_68; // @[Mux.scala 27:72]
|
|
wire _T_5223 = _T_5222 | _T_5096; // @[Mux.scala 27:72]
|
|
wire _T_4969 = ifu_ic_rw_int_addr_ff == 7'h45; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_69; // @[Reg.scala 27:20]
|
|
wire _T_5097 = _T_4969 & way_status_out_69; // @[Mux.scala 27:72]
|
|
wire _T_5224 = _T_5223 | _T_5097; // @[Mux.scala 27:72]
|
|
wire _T_4970 = ifu_ic_rw_int_addr_ff == 7'h46; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_70; // @[Reg.scala 27:20]
|
|
wire _T_5098 = _T_4970 & way_status_out_70; // @[Mux.scala 27:72]
|
|
wire _T_5225 = _T_5224 | _T_5098; // @[Mux.scala 27:72]
|
|
wire _T_4971 = ifu_ic_rw_int_addr_ff == 7'h47; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_71; // @[Reg.scala 27:20]
|
|
wire _T_5099 = _T_4971 & way_status_out_71; // @[Mux.scala 27:72]
|
|
wire _T_5226 = _T_5225 | _T_5099; // @[Mux.scala 27:72]
|
|
wire _T_4972 = ifu_ic_rw_int_addr_ff == 7'h48; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_72; // @[Reg.scala 27:20]
|
|
wire _T_5100 = _T_4972 & way_status_out_72; // @[Mux.scala 27:72]
|
|
wire _T_5227 = _T_5226 | _T_5100; // @[Mux.scala 27:72]
|
|
wire _T_4973 = ifu_ic_rw_int_addr_ff == 7'h49; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_73; // @[Reg.scala 27:20]
|
|
wire _T_5101 = _T_4973 & way_status_out_73; // @[Mux.scala 27:72]
|
|
wire _T_5228 = _T_5227 | _T_5101; // @[Mux.scala 27:72]
|
|
wire _T_4974 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_74; // @[Reg.scala 27:20]
|
|
wire _T_5102 = _T_4974 & way_status_out_74; // @[Mux.scala 27:72]
|
|
wire _T_5229 = _T_5228 | _T_5102; // @[Mux.scala 27:72]
|
|
wire _T_4975 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_75; // @[Reg.scala 27:20]
|
|
wire _T_5103 = _T_4975 & way_status_out_75; // @[Mux.scala 27:72]
|
|
wire _T_5230 = _T_5229 | _T_5103; // @[Mux.scala 27:72]
|
|
wire _T_4976 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_76; // @[Reg.scala 27:20]
|
|
wire _T_5104 = _T_4976 & way_status_out_76; // @[Mux.scala 27:72]
|
|
wire _T_5231 = _T_5230 | _T_5104; // @[Mux.scala 27:72]
|
|
wire _T_4977 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_77; // @[Reg.scala 27:20]
|
|
wire _T_5105 = _T_4977 & way_status_out_77; // @[Mux.scala 27:72]
|
|
wire _T_5232 = _T_5231 | _T_5105; // @[Mux.scala 27:72]
|
|
wire _T_4978 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_78; // @[Reg.scala 27:20]
|
|
wire _T_5106 = _T_4978 & way_status_out_78; // @[Mux.scala 27:72]
|
|
wire _T_5233 = _T_5232 | _T_5106; // @[Mux.scala 27:72]
|
|
wire _T_4979 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_79; // @[Reg.scala 27:20]
|
|
wire _T_5107 = _T_4979 & way_status_out_79; // @[Mux.scala 27:72]
|
|
wire _T_5234 = _T_5233 | _T_5107; // @[Mux.scala 27:72]
|
|
wire _T_4980 = ifu_ic_rw_int_addr_ff == 7'h50; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_80; // @[Reg.scala 27:20]
|
|
wire _T_5108 = _T_4980 & way_status_out_80; // @[Mux.scala 27:72]
|
|
wire _T_5235 = _T_5234 | _T_5108; // @[Mux.scala 27:72]
|
|
wire _T_4981 = ifu_ic_rw_int_addr_ff == 7'h51; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_81; // @[Reg.scala 27:20]
|
|
wire _T_5109 = _T_4981 & way_status_out_81; // @[Mux.scala 27:72]
|
|
wire _T_5236 = _T_5235 | _T_5109; // @[Mux.scala 27:72]
|
|
wire _T_4982 = ifu_ic_rw_int_addr_ff == 7'h52; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_82; // @[Reg.scala 27:20]
|
|
wire _T_5110 = _T_4982 & way_status_out_82; // @[Mux.scala 27:72]
|
|
wire _T_5237 = _T_5236 | _T_5110; // @[Mux.scala 27:72]
|
|
wire _T_4983 = ifu_ic_rw_int_addr_ff == 7'h53; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_83; // @[Reg.scala 27:20]
|
|
wire _T_5111 = _T_4983 & way_status_out_83; // @[Mux.scala 27:72]
|
|
wire _T_5238 = _T_5237 | _T_5111; // @[Mux.scala 27:72]
|
|
wire _T_4984 = ifu_ic_rw_int_addr_ff == 7'h54; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_84; // @[Reg.scala 27:20]
|
|
wire _T_5112 = _T_4984 & way_status_out_84; // @[Mux.scala 27:72]
|
|
wire _T_5239 = _T_5238 | _T_5112; // @[Mux.scala 27:72]
|
|
wire _T_4985 = ifu_ic_rw_int_addr_ff == 7'h55; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_85; // @[Reg.scala 27:20]
|
|
wire _T_5113 = _T_4985 & way_status_out_85; // @[Mux.scala 27:72]
|
|
wire _T_5240 = _T_5239 | _T_5113; // @[Mux.scala 27:72]
|
|
wire _T_4986 = ifu_ic_rw_int_addr_ff == 7'h56; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_86; // @[Reg.scala 27:20]
|
|
wire _T_5114 = _T_4986 & way_status_out_86; // @[Mux.scala 27:72]
|
|
wire _T_5241 = _T_5240 | _T_5114; // @[Mux.scala 27:72]
|
|
wire _T_4987 = ifu_ic_rw_int_addr_ff == 7'h57; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_87; // @[Reg.scala 27:20]
|
|
wire _T_5115 = _T_4987 & way_status_out_87; // @[Mux.scala 27:72]
|
|
wire _T_5242 = _T_5241 | _T_5115; // @[Mux.scala 27:72]
|
|
wire _T_4988 = ifu_ic_rw_int_addr_ff == 7'h58; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_88; // @[Reg.scala 27:20]
|
|
wire _T_5116 = _T_4988 & way_status_out_88; // @[Mux.scala 27:72]
|
|
wire _T_5243 = _T_5242 | _T_5116; // @[Mux.scala 27:72]
|
|
wire _T_4989 = ifu_ic_rw_int_addr_ff == 7'h59; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_89; // @[Reg.scala 27:20]
|
|
wire _T_5117 = _T_4989 & way_status_out_89; // @[Mux.scala 27:72]
|
|
wire _T_5244 = _T_5243 | _T_5117; // @[Mux.scala 27:72]
|
|
wire _T_4990 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_90; // @[Reg.scala 27:20]
|
|
wire _T_5118 = _T_4990 & way_status_out_90; // @[Mux.scala 27:72]
|
|
wire _T_5245 = _T_5244 | _T_5118; // @[Mux.scala 27:72]
|
|
wire _T_4991 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_91; // @[Reg.scala 27:20]
|
|
wire _T_5119 = _T_4991 & way_status_out_91; // @[Mux.scala 27:72]
|
|
wire _T_5246 = _T_5245 | _T_5119; // @[Mux.scala 27:72]
|
|
wire _T_4992 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_92; // @[Reg.scala 27:20]
|
|
wire _T_5120 = _T_4992 & way_status_out_92; // @[Mux.scala 27:72]
|
|
wire _T_5247 = _T_5246 | _T_5120; // @[Mux.scala 27:72]
|
|
wire _T_4993 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_93; // @[Reg.scala 27:20]
|
|
wire _T_5121 = _T_4993 & way_status_out_93; // @[Mux.scala 27:72]
|
|
wire _T_5248 = _T_5247 | _T_5121; // @[Mux.scala 27:72]
|
|
wire _T_4994 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_94; // @[Reg.scala 27:20]
|
|
wire _T_5122 = _T_4994 & way_status_out_94; // @[Mux.scala 27:72]
|
|
wire _T_5249 = _T_5248 | _T_5122; // @[Mux.scala 27:72]
|
|
wire _T_4995 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_95; // @[Reg.scala 27:20]
|
|
wire _T_5123 = _T_4995 & way_status_out_95; // @[Mux.scala 27:72]
|
|
wire _T_5250 = _T_5249 | _T_5123; // @[Mux.scala 27:72]
|
|
wire _T_4996 = ifu_ic_rw_int_addr_ff == 7'h60; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_96; // @[Reg.scala 27:20]
|
|
wire _T_5124 = _T_4996 & way_status_out_96; // @[Mux.scala 27:72]
|
|
wire _T_5251 = _T_5250 | _T_5124; // @[Mux.scala 27:72]
|
|
wire _T_4997 = ifu_ic_rw_int_addr_ff == 7'h61; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_97; // @[Reg.scala 27:20]
|
|
wire _T_5125 = _T_4997 & way_status_out_97; // @[Mux.scala 27:72]
|
|
wire _T_5252 = _T_5251 | _T_5125; // @[Mux.scala 27:72]
|
|
wire _T_4998 = ifu_ic_rw_int_addr_ff == 7'h62; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_98; // @[Reg.scala 27:20]
|
|
wire _T_5126 = _T_4998 & way_status_out_98; // @[Mux.scala 27:72]
|
|
wire _T_5253 = _T_5252 | _T_5126; // @[Mux.scala 27:72]
|
|
wire _T_4999 = ifu_ic_rw_int_addr_ff == 7'h63; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_99; // @[Reg.scala 27:20]
|
|
wire _T_5127 = _T_4999 & way_status_out_99; // @[Mux.scala 27:72]
|
|
wire _T_5254 = _T_5253 | _T_5127; // @[Mux.scala 27:72]
|
|
wire _T_5000 = ifu_ic_rw_int_addr_ff == 7'h64; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_100; // @[Reg.scala 27:20]
|
|
wire _T_5128 = _T_5000 & way_status_out_100; // @[Mux.scala 27:72]
|
|
wire _T_5255 = _T_5254 | _T_5128; // @[Mux.scala 27:72]
|
|
wire _T_5001 = ifu_ic_rw_int_addr_ff == 7'h65; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_101; // @[Reg.scala 27:20]
|
|
wire _T_5129 = _T_5001 & way_status_out_101; // @[Mux.scala 27:72]
|
|
wire _T_5256 = _T_5255 | _T_5129; // @[Mux.scala 27:72]
|
|
wire _T_5002 = ifu_ic_rw_int_addr_ff == 7'h66; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_102; // @[Reg.scala 27:20]
|
|
wire _T_5130 = _T_5002 & way_status_out_102; // @[Mux.scala 27:72]
|
|
wire _T_5257 = _T_5256 | _T_5130; // @[Mux.scala 27:72]
|
|
wire _T_5003 = ifu_ic_rw_int_addr_ff == 7'h67; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_103; // @[Reg.scala 27:20]
|
|
wire _T_5131 = _T_5003 & way_status_out_103; // @[Mux.scala 27:72]
|
|
wire _T_5258 = _T_5257 | _T_5131; // @[Mux.scala 27:72]
|
|
wire _T_5004 = ifu_ic_rw_int_addr_ff == 7'h68; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_104; // @[Reg.scala 27:20]
|
|
wire _T_5132 = _T_5004 & way_status_out_104; // @[Mux.scala 27:72]
|
|
wire _T_5259 = _T_5258 | _T_5132; // @[Mux.scala 27:72]
|
|
wire _T_5005 = ifu_ic_rw_int_addr_ff == 7'h69; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_105; // @[Reg.scala 27:20]
|
|
wire _T_5133 = _T_5005 & way_status_out_105; // @[Mux.scala 27:72]
|
|
wire _T_5260 = _T_5259 | _T_5133; // @[Mux.scala 27:72]
|
|
wire _T_5006 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_106; // @[Reg.scala 27:20]
|
|
wire _T_5134 = _T_5006 & way_status_out_106; // @[Mux.scala 27:72]
|
|
wire _T_5261 = _T_5260 | _T_5134; // @[Mux.scala 27:72]
|
|
wire _T_5007 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_107; // @[Reg.scala 27:20]
|
|
wire _T_5135 = _T_5007 & way_status_out_107; // @[Mux.scala 27:72]
|
|
wire _T_5262 = _T_5261 | _T_5135; // @[Mux.scala 27:72]
|
|
wire _T_5008 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_108; // @[Reg.scala 27:20]
|
|
wire _T_5136 = _T_5008 & way_status_out_108; // @[Mux.scala 27:72]
|
|
wire _T_5263 = _T_5262 | _T_5136; // @[Mux.scala 27:72]
|
|
wire _T_5009 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_109; // @[Reg.scala 27:20]
|
|
wire _T_5137 = _T_5009 & way_status_out_109; // @[Mux.scala 27:72]
|
|
wire _T_5264 = _T_5263 | _T_5137; // @[Mux.scala 27:72]
|
|
wire _T_5010 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_110; // @[Reg.scala 27:20]
|
|
wire _T_5138 = _T_5010 & way_status_out_110; // @[Mux.scala 27:72]
|
|
wire _T_5265 = _T_5264 | _T_5138; // @[Mux.scala 27:72]
|
|
wire _T_5011 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_111; // @[Reg.scala 27:20]
|
|
wire _T_5139 = _T_5011 & way_status_out_111; // @[Mux.scala 27:72]
|
|
wire _T_5266 = _T_5265 | _T_5139; // @[Mux.scala 27:72]
|
|
wire _T_5012 = ifu_ic_rw_int_addr_ff == 7'h70; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_112; // @[Reg.scala 27:20]
|
|
wire _T_5140 = _T_5012 & way_status_out_112; // @[Mux.scala 27:72]
|
|
wire _T_5267 = _T_5266 | _T_5140; // @[Mux.scala 27:72]
|
|
wire _T_5013 = ifu_ic_rw_int_addr_ff == 7'h71; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_113; // @[Reg.scala 27:20]
|
|
wire _T_5141 = _T_5013 & way_status_out_113; // @[Mux.scala 27:72]
|
|
wire _T_5268 = _T_5267 | _T_5141; // @[Mux.scala 27:72]
|
|
wire _T_5014 = ifu_ic_rw_int_addr_ff == 7'h72; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_114; // @[Reg.scala 27:20]
|
|
wire _T_5142 = _T_5014 & way_status_out_114; // @[Mux.scala 27:72]
|
|
wire _T_5269 = _T_5268 | _T_5142; // @[Mux.scala 27:72]
|
|
wire _T_5015 = ifu_ic_rw_int_addr_ff == 7'h73; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_115; // @[Reg.scala 27:20]
|
|
wire _T_5143 = _T_5015 & way_status_out_115; // @[Mux.scala 27:72]
|
|
wire _T_5270 = _T_5269 | _T_5143; // @[Mux.scala 27:72]
|
|
wire _T_5016 = ifu_ic_rw_int_addr_ff == 7'h74; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_116; // @[Reg.scala 27:20]
|
|
wire _T_5144 = _T_5016 & way_status_out_116; // @[Mux.scala 27:72]
|
|
wire _T_5271 = _T_5270 | _T_5144; // @[Mux.scala 27:72]
|
|
wire _T_5017 = ifu_ic_rw_int_addr_ff == 7'h75; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_117; // @[Reg.scala 27:20]
|
|
wire _T_5145 = _T_5017 & way_status_out_117; // @[Mux.scala 27:72]
|
|
wire _T_5272 = _T_5271 | _T_5145; // @[Mux.scala 27:72]
|
|
wire _T_5018 = ifu_ic_rw_int_addr_ff == 7'h76; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_118; // @[Reg.scala 27:20]
|
|
wire _T_5146 = _T_5018 & way_status_out_118; // @[Mux.scala 27:72]
|
|
wire _T_5273 = _T_5272 | _T_5146; // @[Mux.scala 27:72]
|
|
wire _T_5019 = ifu_ic_rw_int_addr_ff == 7'h77; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_119; // @[Reg.scala 27:20]
|
|
wire _T_5147 = _T_5019 & way_status_out_119; // @[Mux.scala 27:72]
|
|
wire _T_5274 = _T_5273 | _T_5147; // @[Mux.scala 27:72]
|
|
wire _T_5020 = ifu_ic_rw_int_addr_ff == 7'h78; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_120; // @[Reg.scala 27:20]
|
|
wire _T_5148 = _T_5020 & way_status_out_120; // @[Mux.scala 27:72]
|
|
wire _T_5275 = _T_5274 | _T_5148; // @[Mux.scala 27:72]
|
|
wire _T_5021 = ifu_ic_rw_int_addr_ff == 7'h79; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_121; // @[Reg.scala 27:20]
|
|
wire _T_5149 = _T_5021 & way_status_out_121; // @[Mux.scala 27:72]
|
|
wire _T_5276 = _T_5275 | _T_5149; // @[Mux.scala 27:72]
|
|
wire _T_5022 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_122; // @[Reg.scala 27:20]
|
|
wire _T_5150 = _T_5022 & way_status_out_122; // @[Mux.scala 27:72]
|
|
wire _T_5277 = _T_5276 | _T_5150; // @[Mux.scala 27:72]
|
|
wire _T_5023 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_123; // @[Reg.scala 27:20]
|
|
wire _T_5151 = _T_5023 & way_status_out_123; // @[Mux.scala 27:72]
|
|
wire _T_5278 = _T_5277 | _T_5151; // @[Mux.scala 27:72]
|
|
wire _T_5024 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_124; // @[Reg.scala 27:20]
|
|
wire _T_5152 = _T_5024 & way_status_out_124; // @[Mux.scala 27:72]
|
|
wire _T_5279 = _T_5278 | _T_5152; // @[Mux.scala 27:72]
|
|
wire _T_5025 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_125; // @[Reg.scala 27:20]
|
|
wire _T_5153 = _T_5025 & way_status_out_125; // @[Mux.scala 27:72]
|
|
wire _T_5280 = _T_5279 | _T_5153; // @[Mux.scala 27:72]
|
|
wire _T_5026 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_126; // @[Reg.scala 27:20]
|
|
wire _T_5154 = _T_5026 & way_status_out_126; // @[Mux.scala 27:72]
|
|
wire _T_5281 = _T_5280 | _T_5154; // @[Mux.scala 27:72]
|
|
wire _T_5027 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[ifu_mem_ctl.scala 628:80]
|
|
reg way_status_out_127; // @[Reg.scala 27:20]
|
|
wire _T_5155 = _T_5027 & way_status_out_127; // @[Mux.scala 27:72]
|
|
wire way_status = _T_5281 | _T_5155; // @[Mux.scala 27:72]
|
|
wire _T_198 = ~reset_all_tags; // @[ifu_mem_ctl.scala 164:96]
|
|
wire _T_200 = _T_198 & _T_339; // @[ifu_mem_ctl.scala 164:112]
|
|
wire [1:0] _T_202 = _T_200 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_203 = _T_202 & io_ic_tag_valid; // @[ifu_mem_ctl.scala 164:135]
|
|
reg [1:0] tagv_mb_scnd_ff; // @[Reg.scala 27:20]
|
|
reg uncacheable_miss_scnd_ff; // @[Reg.scala 27:20]
|
|
reg [30:0] imb_scnd_ff; // @[Reg.scala 27:20]
|
|
wire [2:0] _T_212 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
reg [2:0] ifu_bus_rid_ff; // @[Reg.scala 27:20]
|
|
wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_212; // @[ifu_mem_ctl.scala 173:45]
|
|
wire _T_218 = _T_237 | _T_245; // @[ifu_mem_ctl.scala 178:59]
|
|
wire _T_220 = _T_218 | _T_2274; // @[ifu_mem_ctl.scala 178:91]
|
|
wire ic_iccm_hit_f = fetch_req_iccm_f & _T_220; // @[ifu_mem_ctl.scala 178:41]
|
|
wire _T_225 = _T_233 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 184:39]
|
|
wire _T_227 = _T_225 & _T_198; // @[ifu_mem_ctl.scala 184:60]
|
|
wire _T_231 = _T_227 & _T_218; // @[ifu_mem_ctl.scala 184:78]
|
|
wire ic_act_hit_f = _T_231 & _T_253; // @[ifu_mem_ctl.scala 184:126]
|
|
wire _T_268 = ic_act_hit_f | ic_byp_hit_f; // @[ifu_mem_ctl.scala 191:31]
|
|
wire _T_269 = _T_268 | ic_iccm_hit_f; // @[ifu_mem_ctl.scala 191:46]
|
|
wire _T_270 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 191:94]
|
|
wire _T_274 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 192:84]
|
|
wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_274; // @[ifu_mem_ctl.scala 192:32]
|
|
wire _T_280 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 195:79]
|
|
wire _T_281 = _T_280 & scnd_miss_req; // @[ifu_mem_ctl.scala 195:135]
|
|
reg [1:0] ifu_bus_rresp_ff; // @[Reg.scala 27:20]
|
|
wire _T_2737 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 522:48]
|
|
wire _T_2738 = _T_2737 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 522:52]
|
|
wire bus_ifu_wr_data_error_ff = _T_2738 & miss_pending; // @[ifu_mem_ctl.scala 522:73]
|
|
reg ifu_wr_data_comb_err_ff; // @[Reg.scala 27:20]
|
|
wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 271:59]
|
|
wire _T_282 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 195:153]
|
|
wire scnd_miss_index_match = _T_281 & _T_282; // @[ifu_mem_ctl.scala 195:151]
|
|
wire _T_283 = ~scnd_miss_index_match; // @[ifu_mem_ctl.scala 198:47]
|
|
wire _T_284 = scnd_miss_req & _T_283; // @[ifu_mem_ctl.scala 198:45]
|
|
wire _T_286 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 199:24]
|
|
reg way_status_mb_ff; // @[Reg.scala 27:20]
|
|
wire _T_10506 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 680:31]
|
|
reg [1:0] tagv_mb_ff; // @[Reg.scala 27:20]
|
|
wire _T_10508 = _T_10506 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 680:49]
|
|
wire _T_10510 = _T_10508 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 680:65]
|
|
wire _T_10512 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 680:84]
|
|
wire replace_way_mb_any_0 = _T_10510 | _T_10512; // @[ifu_mem_ctl.scala 680:82]
|
|
wire [1:0] _T_293 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_10515 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 681:48]
|
|
wire _T_10517 = _T_10515 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 681:64]
|
|
wire _T_10519 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 681:83]
|
|
wire _T_10521 = _T_10519 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 681:98]
|
|
wire replace_way_mb_any_1 = _T_10517 | _T_10521; // @[ifu_mem_ctl.scala 681:81]
|
|
wire [1:0] _T_294 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_295 = _T_293 & _T_294; // @[ifu_mem_ctl.scala 203:110]
|
|
wire [1:0] _T_296 = tagv_mb_scnd_ff | _T_295; // @[ifu_mem_ctl.scala 203:62]
|
|
wire [1:0] _T_303 = io_ic_tag_valid & _T_202; // @[ifu_mem_ctl.scala 204:58]
|
|
wire _T_305 = ~scnd_miss_req_q; // @[ifu_mem_ctl.scala 207:36]
|
|
wire _T_306 = miss_pending & _T_305; // @[ifu_mem_ctl.scala 207:34]
|
|
reg reset_ic_ff; // @[Reg.scala 27:20]
|
|
wire _T_307 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 207:72]
|
|
wire reset_ic_in = _T_306 & _T_307; // @[ifu_mem_ctl.scala 207:53]
|
|
wire _T_309 = reset_ic_in ^ reset_ic_ff; // @[lib.scala 466:21]
|
|
wire _T_310 = |_T_309; // @[lib.scala 466:29]
|
|
reg fetch_uncacheable_ff; // @[Reg.scala 27:20]
|
|
wire _T_312 = io_ifc_fetch_uncacheable_bf ^ fetch_uncacheable_ff; // @[lib.scala 488:21]
|
|
wire _T_313 = |_T_312; // @[lib.scala 488:29]
|
|
reg [25:0] miss_addr; // @[Reg.scala 27:20]
|
|
wire _T_325 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 219:89]
|
|
wire _T_326 = _T_325 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 219:105]
|
|
wire _T_332 = _T_2289 & flush_final_f; // @[ifu_mem_ctl.scala 223:87]
|
|
wire _T_333 = ~_T_332; // @[ifu_mem_ctl.scala 223:55]
|
|
wire _T_334 = io_ifc_fetch_req_bf & _T_333; // @[ifu_mem_ctl.scala 223:53]
|
|
wire _T_2281 = ~_T_2276; // @[ifu_mem_ctl.scala 362:46]
|
|
wire _T_2282 = _T_2274 & _T_2281; // @[ifu_mem_ctl.scala 362:44]
|
|
wire stream_miss_f = _T_2282 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 362:84]
|
|
wire _T_335 = ~stream_miss_f; // @[ifu_mem_ctl.scala 223:106]
|
|
wire ifc_fetch_req_qual_bf = _T_334 & _T_335; // @[ifu_mem_ctl.scala 223:104]
|
|
wire _T_336 = ifc_fetch_req_qual_bf ^ ifc_fetch_req_f_raw; // @[lib.scala 488:21]
|
|
wire _T_337 = |_T_336; // @[lib.scala 488:29]
|
|
wire _T_10655 = ~io_ifc_iccm_access_bf; // @[ifu_mem_ctl.scala 737:40]
|
|
wire ifc_region_acc_okay = 1'h1; // @[ifu_mem_ctl.scala 734:160]
|
|
wire _T_10656 = ~_T_3693; // @[ifu_mem_ctl.scala 737:65]
|
|
wire _T_10657 = _T_10655 & _T_10656; // @[ifu_mem_ctl.scala 737:63]
|
|
wire ifc_region_acc_fault_memory_bf = _T_10657 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 737:86]
|
|
wire ifc_region_acc_fault_final_bf = io_ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf; // @[ifu_mem_ctl.scala 738:63]
|
|
reg ifc_region_acc_fault_f; // @[Reg.scala 27:20]
|
|
reg [2:0] bus_rd_addr_count; // @[Reg.scala 27:20]
|
|
wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58]
|
|
wire _T_345 = _T_245 | _T_2274; // @[ifu_mem_ctl.scala 231:55]
|
|
wire _T_348 = _T_345 & _T_59; // @[ifu_mem_ctl.scala 231:82]
|
|
wire _T_2295 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 367:55]
|
|
wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2295}; // @[Cat.scala 29:58]
|
|
wire _T_2296 = other_tag == 3'h0; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2320 = _T_2296 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
|
|
wire _T_2299 = other_tag == 3'h1; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2321 = _T_2299 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
|
|
wire _T_2328 = _T_2320 | _T_2321; // @[Mux.scala 27:72]
|
|
wire _T_2302 = other_tag == 3'h2; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2322 = _T_2302 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
|
|
wire _T_2329 = _T_2328 | _T_2322; // @[Mux.scala 27:72]
|
|
wire _T_2305 = other_tag == 3'h3; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2323 = _T_2305 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
|
|
wire _T_2330 = _T_2329 | _T_2323; // @[Mux.scala 27:72]
|
|
wire _T_2308 = other_tag == 3'h4; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2324 = _T_2308 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
|
|
wire _T_2331 = _T_2330 | _T_2324; // @[Mux.scala 27:72]
|
|
wire _T_2311 = other_tag == 3'h5; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2325 = _T_2311 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
|
|
wire _T_2332 = _T_2331 | _T_2325; // @[Mux.scala 27:72]
|
|
wire _T_2314 = other_tag == 3'h6; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2326 = _T_2314 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
|
|
wire _T_2333 = _T_2332 | _T_2326; // @[Mux.scala 27:72]
|
|
wire _T_2317 = other_tag == 3'h7; // @[ifu_mem_ctl.scala 368:81]
|
|
wire _T_2327 = _T_2317 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
|
|
wire second_half_available = _T_2333 | _T_2327; // @[Mux.scala 27:72]
|
|
wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 369:46]
|
|
wire _T_352 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 235:35]
|
|
wire _T_354 = _T_352 & _T_20; // @[ifu_mem_ctl.scala 235:55]
|
|
reg ic_act_miss_f_delayed; // @[Reg.scala 27:20]
|
|
wire _T_2731 = ic_act_miss_f_delayed & _T_2290; // @[ifu_mem_ctl.scala 520:53]
|
|
wire reset_tag_valid_for_miss = _T_2731 & _T_20; // @[ifu_mem_ctl.scala 520:84]
|
|
wire sel_mb_addr = _T_354 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 235:79]
|
|
wire [30:0] _T_358 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_359 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 237:5]
|
|
wire [30:0] _T_360 = sel_mb_addr ? _T_358 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_361 = _T_359 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72]
|
|
wire _T_367 = _T_354 & last_beat; // @[ifu_mem_ctl.scala 239:85]
|
|
wire _T_2722 = ~_T_2737; // @[ifu_mem_ctl.scala 517:84]
|
|
wire _T_2723 = _T_103 & _T_2722; // @[ifu_mem_ctl.scala 517:82]
|
|
wire bus_ifu_wr_en_ff_q = _T_2723 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 517:108]
|
|
wire _T_368 = _T_367 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 239:97]
|
|
wire sel_mb_status_addr = _T_368 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 239:119]
|
|
wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_358 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 240:31]
|
|
wire _T_374 = sel_mb_addr ^ sel_mb_addr_ff; // @[lib.scala 488:21]
|
|
wire _T_375 = |_T_374; // @[lib.scala 488:29]
|
|
wire _T_377 = io_ifu_bus_clk_en & io_ifu_axi_r_valid; // @[ifu_mem_ctl.scala 242:74]
|
|
reg [63:0] ifu_bus_rdata_ff; // @[Reg.scala 27:20]
|
|
wire [6:0] _T_595 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 282:13]
|
|
wire _T_596 = ^_T_595; // @[lib.scala 282:20]
|
|
wire [6:0] _T_602 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 282:30]
|
|
wire [7:0] _T_609 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[lib.scala 282:30]
|
|
wire [14:0] _T_610 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_602}; // @[lib.scala 282:30]
|
|
wire [7:0] _T_617 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[lib.scala 282:30]
|
|
wire [30:0] _T_626 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_617,_T_610}; // @[lib.scala 282:30]
|
|
wire _T_627 = ^_T_626; // @[lib.scala 282:37]
|
|
wire [6:0] _T_633 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[lib.scala 282:47]
|
|
wire [14:0] _T_641 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_633}; // @[lib.scala 282:47]
|
|
wire [30:0] _T_657 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_617,_T_641}; // @[lib.scala 282:47]
|
|
wire _T_658 = ^_T_657; // @[lib.scala 282:54]
|
|
wire [6:0] _T_664 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[lib.scala 282:64]
|
|
wire [14:0] _T_672 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_664}; // @[lib.scala 282:64]
|
|
wire [30:0] _T_688 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_609,_T_672}; // @[lib.scala 282:64]
|
|
wire _T_689 = ^_T_688; // @[lib.scala 282:71]
|
|
wire [7:0] _T_696 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[lib.scala 282:81]
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|
wire [16:0] _T_705 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_696}; // @[lib.scala 282:81]
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|
wire [8:0] _T_713 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 282:81]
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|
wire [17:0] _T_722 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_713}; // @[lib.scala 282:81]
|
|
wire [34:0] _T_723 = {_T_722,_T_705}; // @[lib.scala 282:81]
|
|
wire _T_724 = ^_T_723; // @[lib.scala 282:88]
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|
wire [7:0] _T_731 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[lib.scala 282:98]
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|
wire [16:0] _T_740 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_731}; // @[lib.scala 282:98]
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wire [8:0] _T_748 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 282:98]
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|
wire [17:0] _T_757 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_748}; // @[lib.scala 282:98]
|
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wire [34:0] _T_758 = {_T_757,_T_740}; // @[lib.scala 282:98]
|
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wire _T_759 = ^_T_758; // @[lib.scala 282:105]
|
|
wire [7:0] _T_766 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[lib.scala 282:115]
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|
wire [16:0] _T_775 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_766}; // @[lib.scala 282:115]
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|
wire [8:0] _T_783 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[lib.scala 282:115]
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|
wire [17:0] _T_792 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_783}; // @[lib.scala 282:115]
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wire [34:0] _T_793 = {_T_792,_T_775}; // @[lib.scala 282:115]
|
|
wire _T_794 = ^_T_793; // @[lib.scala 282:122]
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|
wire [3:0] _T_2336 = {ifu_bus_rid_ff[2:1],_T_2295,1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_2337 = _T_2336 == 4'h0; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_0; // @[Reg.scala 27:20]
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wire [31:0] _T_2384 = _T_2337 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_2340 = _T_2336 == 4'h1; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_1; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2385 = _T_2340 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2400 = _T_2384 | _T_2385; // @[Mux.scala 27:72]
|
|
wire _T_2343 = _T_2336 == 4'h2; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_2; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2386 = _T_2343 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2401 = _T_2400 | _T_2386; // @[Mux.scala 27:72]
|
|
wire _T_2346 = _T_2336 == 4'h3; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_3; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2387 = _T_2346 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2402 = _T_2401 | _T_2387; // @[Mux.scala 27:72]
|
|
wire _T_2349 = _T_2336 == 4'h4; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_4; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2388 = _T_2349 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2403 = _T_2402 | _T_2388; // @[Mux.scala 27:72]
|
|
wire _T_2352 = _T_2336 == 4'h5; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_5; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2389 = _T_2352 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2404 = _T_2403 | _T_2389; // @[Mux.scala 27:72]
|
|
wire _T_2355 = _T_2336 == 4'h6; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_6; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2390 = _T_2355 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2405 = _T_2404 | _T_2390; // @[Mux.scala 27:72]
|
|
wire _T_2358 = _T_2336 == 4'h7; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_7; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2391 = _T_2358 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2406 = _T_2405 | _T_2391; // @[Mux.scala 27:72]
|
|
wire _T_2361 = _T_2336 == 4'h8; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_8; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2392 = _T_2361 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2407 = _T_2406 | _T_2392; // @[Mux.scala 27:72]
|
|
wire _T_2364 = _T_2336 == 4'h9; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_9; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2393 = _T_2364 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2408 = _T_2407 | _T_2393; // @[Mux.scala 27:72]
|
|
wire _T_2367 = _T_2336 == 4'ha; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_10; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2394 = _T_2367 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2409 = _T_2408 | _T_2394; // @[Mux.scala 27:72]
|
|
wire _T_2370 = _T_2336 == 4'hb; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_11; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2395 = _T_2370 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2410 = _T_2409 | _T_2395; // @[Mux.scala 27:72]
|
|
wire _T_2373 = _T_2336 == 4'hc; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_12; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2396 = _T_2373 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2411 = _T_2410 | _T_2396; // @[Mux.scala 27:72]
|
|
wire _T_2376 = _T_2336 == 4'hd; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_13; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2397 = _T_2376 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2412 = _T_2411 | _T_2397; // @[Mux.scala 27:72]
|
|
wire _T_2379 = _T_2336 == 4'he; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_14; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2398 = _T_2379 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2413 = _T_2412 | _T_2398; // @[Mux.scala 27:72]
|
|
wire _T_2382 = _T_2336 == 4'hf; // @[ifu_mem_ctl.scala 370:89]
|
|
reg [31:0] ic_miss_buff_data_15; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_2399 = _T_2382 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2414 = _T_2413 | _T_2399; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_2416 = {ifu_bus_rid_ff[2:1],_T_2295,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_2417 = _T_2416 == 4'h0; // @[ifu_mem_ctl.scala 371:66]
|
|
wire [31:0] _T_2464 = _T_2417 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_2420 = _T_2416 == 4'h1; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2465 = _T_2420 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2480 = _T_2464 | _T_2465; // @[Mux.scala 27:72]
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wire _T_2423 = _T_2416 == 4'h2; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2466 = _T_2423 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2481 = _T_2480 | _T_2466; // @[Mux.scala 27:72]
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wire _T_2426 = _T_2416 == 4'h3; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2467 = _T_2426 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2482 = _T_2481 | _T_2467; // @[Mux.scala 27:72]
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wire _T_2429 = _T_2416 == 4'h4; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2468 = _T_2429 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2483 = _T_2482 | _T_2468; // @[Mux.scala 27:72]
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wire _T_2432 = _T_2416 == 4'h5; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2469 = _T_2432 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2484 = _T_2483 | _T_2469; // @[Mux.scala 27:72]
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wire _T_2435 = _T_2416 == 4'h6; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2470 = _T_2435 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2485 = _T_2484 | _T_2470; // @[Mux.scala 27:72]
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wire _T_2438 = _T_2416 == 4'h7; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2471 = _T_2438 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2486 = _T_2485 | _T_2471; // @[Mux.scala 27:72]
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wire _T_2441 = _T_2416 == 4'h8; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2472 = _T_2441 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2487 = _T_2486 | _T_2472; // @[Mux.scala 27:72]
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wire _T_2444 = _T_2416 == 4'h9; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2473 = _T_2444 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2488 = _T_2487 | _T_2473; // @[Mux.scala 27:72]
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wire _T_2447 = _T_2416 == 4'ha; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2474 = _T_2447 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2489 = _T_2488 | _T_2474; // @[Mux.scala 27:72]
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wire _T_2450 = _T_2416 == 4'hb; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2475 = _T_2450 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2490 = _T_2489 | _T_2475; // @[Mux.scala 27:72]
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wire _T_2453 = _T_2416 == 4'hc; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2476 = _T_2453 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2491 = _T_2490 | _T_2476; // @[Mux.scala 27:72]
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wire _T_2456 = _T_2416 == 4'hd; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2477 = _T_2456 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2492 = _T_2491 | _T_2477; // @[Mux.scala 27:72]
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wire _T_2459 = _T_2416 == 4'he; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2478 = _T_2459 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2493 = _T_2492 | _T_2478; // @[Mux.scala 27:72]
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wire _T_2462 = _T_2416 == 4'hf; // @[ifu_mem_ctl.scala 371:66]
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wire [31:0] _T_2479 = _T_2462 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_2494 = _T_2493 | _T_2479; // @[Mux.scala 27:72]
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wire [63:0] ic_miss_buff_half = {_T_2414,_T_2494}; // @[Cat.scala 29:58]
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wire [6:0] _T_1017 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[lib.scala 282:13]
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wire _T_1018 = ^_T_1017; // @[lib.scala 282:20]
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wire [6:0] _T_1024 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[lib.scala 282:30]
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wire [7:0] _T_1031 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[lib.scala 282:30]
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wire [14:0] _T_1032 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_1024}; // @[lib.scala 282:30]
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wire [7:0] _T_1039 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[lib.scala 282:30]
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wire [30:0] _T_1048 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1039,_T_1032}; // @[lib.scala 282:30]
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wire _T_1049 = ^_T_1048; // @[lib.scala 282:37]
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wire [6:0] _T_1055 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[lib.scala 282:47]
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wire [14:0] _T_1063 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1055}; // @[lib.scala 282:47]
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wire [30:0] _T_1079 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1039,_T_1063}; // @[lib.scala 282:47]
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wire _T_1080 = ^_T_1079; // @[lib.scala 282:54]
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wire [6:0] _T_1086 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[lib.scala 282:64]
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wire [14:0] _T_1094 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1086}; // @[lib.scala 282:64]
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wire [30:0] _T_1110 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1031,_T_1094}; // @[lib.scala 282:64]
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wire _T_1111 = ^_T_1110; // @[lib.scala 282:71]
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wire [7:0] _T_1118 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[lib.scala 282:81]
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wire [16:0] _T_1127 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1118}; // @[lib.scala 282:81]
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wire [8:0] _T_1135 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 282:81]
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wire [17:0] _T_1144 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1135}; // @[lib.scala 282:81]
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wire [34:0] _T_1145 = {_T_1144,_T_1127}; // @[lib.scala 282:81]
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wire _T_1146 = ^_T_1145; // @[lib.scala 282:88]
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wire [7:0] _T_1153 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[lib.scala 282:98]
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wire [16:0] _T_1162 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1153}; // @[lib.scala 282:98]
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wire [8:0] _T_1170 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 282:98]
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wire [17:0] _T_1179 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1170}; // @[lib.scala 282:98]
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wire [34:0] _T_1180 = {_T_1179,_T_1162}; // @[lib.scala 282:98]
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wire _T_1181 = ^_T_1180; // @[lib.scala 282:105]
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wire [7:0] _T_1188 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[lib.scala 282:115]
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wire [16:0] _T_1197 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1188}; // @[lib.scala 282:115]
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wire [8:0] _T_1205 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[lib.scala 282:115]
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wire [17:0] _T_1214 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1205}; // @[lib.scala 282:115]
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wire [34:0] _T_1215 = {_T_1214,_T_1197}; // @[lib.scala 282:115]
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wire _T_1216 = ^_T_1215; // @[lib.scala 282:122]
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wire [70:0] _T_1261 = {_T_596,_T_627,_T_658,_T_689,_T_724,_T_759,_T_794,ifu_bus_rdata_ff}; // @[Cat.scala 29:58]
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wire [70:0] _T_1260 = {_T_1018,_T_1049,_T_1080,_T_1111,_T_1146,_T_1181,_T_1216,_T_2414,_T_2494}; // @[Cat.scala 29:58]
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wire [141:0] _T_1262 = {_T_596,_T_627,_T_658,_T_689,_T_724,_T_759,_T_794,ifu_bus_rdata_ff,_T_1260}; // @[Cat.scala 29:58]
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wire [141:0] _T_1265 = {_T_1018,_T_1049,_T_1080,_T_1111,_T_1146,_T_1181,_T_1216,_T_2414,_T_2494,_T_1261}; // @[Cat.scala 29:58]
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wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1262 : _T_1265; // @[ifu_mem_ctl.scala 264:28]
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wire _T_1224 = |io_ic_eccerr; // @[ifu_mem_ctl.scala 252:73]
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wire _T_1225 = _T_1224 & ic_act_hit_f; // @[ifu_mem_ctl.scala 252:100]
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wire _T_2498 = io_ic_tag_perr & _T_339; // @[ifu_mem_ctl.scala 374:44]
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wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 318:28]
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wire _T_1436 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 320:114]
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wire bus_ifu_wr_en = _T_16 & miss_pending; // @[ifu_mem_ctl.scala 515:35]
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wire _T_1321 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_0 = bus_ifu_wr_en & _T_1321; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1362 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 309:118]
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wire _T_1363 = ic_miss_buff_data_valid[0] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1363; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1459 = _T_1436 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
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wire _T_1439 = bypass_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1322 = io_ifu_axi_r_bits_id == 3'h1; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_1 = bus_ifu_wr_en & _T_1322; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1366 = ic_miss_buff_data_valid[1] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1366; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1460 = _T_1439 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
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wire _T_1467 = _T_1459 | _T_1460; // @[Mux.scala 27:72]
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wire _T_1442 = bypass_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1323 = io_ifu_axi_r_bits_id == 3'h2; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_2 = bus_ifu_wr_en & _T_1323; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1369 = ic_miss_buff_data_valid[2] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1369; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1461 = _T_1442 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
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wire _T_1468 = _T_1467 | _T_1461; // @[Mux.scala 27:72]
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wire _T_1445 = bypass_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1324 = io_ifu_axi_r_bits_id == 3'h3; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_3 = bus_ifu_wr_en & _T_1324; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1372 = ic_miss_buff_data_valid[3] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1372; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1462 = _T_1445 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
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wire _T_1469 = _T_1468 | _T_1462; // @[Mux.scala 27:72]
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wire _T_1448 = bypass_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1325 = io_ifu_axi_r_bits_id == 3'h4; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_4 = bus_ifu_wr_en & _T_1325; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1375 = ic_miss_buff_data_valid[4] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1375; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1463 = _T_1448 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
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wire _T_1470 = _T_1469 | _T_1463; // @[Mux.scala 27:72]
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wire _T_1451 = bypass_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1326 = io_ifu_axi_r_bits_id == 3'h5; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_5 = bus_ifu_wr_en & _T_1326; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1378 = ic_miss_buff_data_valid[5] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1378; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1464 = _T_1451 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
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wire _T_1471 = _T_1470 | _T_1464; // @[Mux.scala 27:72]
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wire _T_1454 = bypass_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1327 = io_ifu_axi_r_bits_id == 3'h6; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_6 = bus_ifu_wr_en & _T_1327; // @[ifu_mem_ctl.scala 301:73]
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wire _T_1381 = ic_miss_buff_data_valid[6] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
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wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1381; // @[ifu_mem_ctl.scala 309:88]
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wire _T_1465 = _T_1454 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
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wire _T_1472 = _T_1471 | _T_1465; // @[Mux.scala 27:72]
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wire _T_1457 = bypass_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 320:114]
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wire _T_1328 = io_ifu_axi_r_bits_id == 3'h7; // @[ifu_mem_ctl.scala 301:96]
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wire write_fill_data_7 = bus_ifu_wr_en & _T_1328; // @[ifu_mem_ctl.scala 301:73]
|
|
wire _T_1384 = ic_miss_buff_data_valid[7] & _T_1362; // @[ifu_mem_ctl.scala 309:116]
|
|
wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1384; // @[ifu_mem_ctl.scala 309:88]
|
|
wire _T_1466 = _T_1457 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check = _T_1472 | _T_1466; // @[Mux.scala 27:72]
|
|
wire _T_1475 = ~bypass_index[1]; // @[ifu_mem_ctl.scala 321:58]
|
|
wire _T_1476 = bypass_valid_value_check & _T_1475; // @[ifu_mem_ctl.scala 321:56]
|
|
wire _T_1478 = ~bypass_index[0]; // @[ifu_mem_ctl.scala 321:77]
|
|
wire _T_1479 = _T_1476 & _T_1478; // @[ifu_mem_ctl.scala 321:75]
|
|
wire _T_1484 = _T_1476 & bypass_index[0]; // @[ifu_mem_ctl.scala 322:50]
|
|
wire _T_1485 = _T_1479 | _T_1484; // @[ifu_mem_ctl.scala 321:95]
|
|
wire _T_1487 = bypass_valid_value_check & bypass_index[1]; // @[ifu_mem_ctl.scala 323:31]
|
|
wire _T_1490 = _T_1487 & _T_1478; // @[ifu_mem_ctl.scala 323:49]
|
|
wire _T_1491 = _T_1485 | _T_1490; // @[ifu_mem_ctl.scala 322:69]
|
|
wire _T_1495 = _T_1487 & bypass_index[0]; // @[ifu_mem_ctl.scala 324:49]
|
|
wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[ifu_mem_ctl.scala 319:70]
|
|
wire _T_1496 = bypass_index_5_3_inc == 3'h0; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1512 = _T_1496 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
|
|
wire _T_1498 = bypass_index_5_3_inc == 3'h1; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1513 = _T_1498 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
|
|
wire _T_1520 = _T_1512 | _T_1513; // @[Mux.scala 27:72]
|
|
wire _T_1500 = bypass_index_5_3_inc == 3'h2; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1514 = _T_1500 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
|
|
wire _T_1521 = _T_1520 | _T_1514; // @[Mux.scala 27:72]
|
|
wire _T_1502 = bypass_index_5_3_inc == 3'h3; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1515 = _T_1502 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
|
|
wire _T_1522 = _T_1521 | _T_1515; // @[Mux.scala 27:72]
|
|
wire _T_1504 = bypass_index_5_3_inc == 3'h4; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1516 = _T_1504 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
|
|
wire _T_1523 = _T_1522 | _T_1516; // @[Mux.scala 27:72]
|
|
wire _T_1506 = bypass_index_5_3_inc == 3'h5; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1517 = _T_1506 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
|
|
wire _T_1524 = _T_1523 | _T_1517; // @[Mux.scala 27:72]
|
|
wire _T_1508 = bypass_index_5_3_inc == 3'h6; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1518 = _T_1508 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
|
|
wire _T_1525 = _T_1524 | _T_1518; // @[Mux.scala 27:72]
|
|
wire _T_1510 = bypass_index_5_3_inc == 3'h7; // @[ifu_mem_ctl.scala 324:130]
|
|
wire _T_1519 = _T_1510 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
|
|
wire _T_1526 = _T_1525 | _T_1519; // @[Mux.scala 27:72]
|
|
wire _T_1528 = _T_1495 & _T_1526; // @[ifu_mem_ctl.scala 324:67]
|
|
wire _T_1529 = _T_1491 | _T_1528; // @[ifu_mem_ctl.scala 323:69]
|
|
wire [4:0] _GEN_516 = {{2'd0}, bypass_index[4:2]}; // @[ifu_mem_ctl.scala 325:70]
|
|
wire _T_1532 = _GEN_516 == 5'h1f; // @[ifu_mem_ctl.scala 325:70]
|
|
wire _T_1533 = bypass_valid_value_check & _T_1532; // @[ifu_mem_ctl.scala 325:31]
|
|
wire bypass_data_ready_in = _T_1529 | _T_1533; // @[ifu_mem_ctl.scala 324:179]
|
|
wire _T_1534 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 329:53]
|
|
wire _T_1535 = _T_1534 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 329:73]
|
|
wire _T_1537 = _T_1535 & _T_339; // @[ifu_mem_ctl.scala 329:96]
|
|
wire _T_1539 = _T_1537 & _T_61; // @[ifu_mem_ctl.scala 329:118]
|
|
wire _T_1541 = crit_wd_byp_ok_ff & _T_20; // @[ifu_mem_ctl.scala 330:47]
|
|
wire _T_1543 = _T_1541 & _T_339; // @[ifu_mem_ctl.scala 330:70]
|
|
wire _T_1545 = _T_1543 & _T_61; // @[ifu_mem_ctl.scala 330:92]
|
|
wire _T_1546 = _T_1539 | _T_1545; // @[ifu_mem_ctl.scala 329:143]
|
|
reg ic_crit_wd_rdy_new_ff; // @[Reg.scala 27:20]
|
|
wire _T_1547 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 331:28]
|
|
wire _T_1548 = ~fetch_req_icache_f; // @[ifu_mem_ctl.scala 331:50]
|
|
wire _T_1549 = _T_1547 & _T_1548; // @[ifu_mem_ctl.scala 331:48]
|
|
wire _T_1551 = _T_1549 & _T_339; // @[ifu_mem_ctl.scala 331:70]
|
|
wire ic_crit_wd_rdy_new_in = _T_1546 | _T_1551; // @[ifu_mem_ctl.scala 330:117]
|
|
wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 525:43]
|
|
wire _T_1278 = ic_crit_wd_rdy | _T_2274; // @[ifu_mem_ctl.scala 276:38]
|
|
wire _T_1280 = _T_1278 | _T_2290; // @[ifu_mem_ctl.scala 276:64]
|
|
wire _T_1281 = miss_state == 3'h3; // @[ifu_mem_ctl.scala 276:109]
|
|
wire _T_1282 = _T_1280 | _T_1281; // @[ifu_mem_ctl.scala 276:95]
|
|
wire _T_1283 = ~_T_1282; // @[ifu_mem_ctl.scala 276:21]
|
|
wire _T_1284 = ~fetch_req_iccm_f; // @[ifu_mem_ctl.scala 276:129]
|
|
wire _T_1285 = _T_1283 & _T_1284; // @[ifu_mem_ctl.scala 276:127]
|
|
wire sel_ic_data = _T_1285 & _T_215; // @[ifu_mem_ctl.scala 276:147]
|
|
wire _T_2499 = _T_2498 & sel_ic_data; // @[ifu_mem_ctl.scala 374:66]
|
|
wire [1:0] _T_1298 = ic_byp_hit_f ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg [7:0] ic_miss_buff_data_error; // @[ifu_mem_ctl.scala 315:62]
|
|
wire [7:0] _T_1647 = ic_miss_buff_data_error >> byp_fetch_index[4:2]; // @[ifu_mem_ctl.scala 342:55]
|
|
wire _T_1651 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 343:34]
|
|
wire _T_1655 = ~_T_1647[0]; // @[ifu_mem_ctl.scala 343:63]
|
|
wire _T_1656 = _T_1651 & _T_1655; // @[ifu_mem_ctl.scala 343:61]
|
|
wire [7:0] _T_1658 = ic_miss_buff_data_error >> byp_fetch_index_inc; // @[ifu_mem_ctl.scala 344:46]
|
|
wire _T_1660 = _T_2275 & _T_1658[0]; // @[ifu_mem_ctl.scala 344:21]
|
|
wire _T_1661 = _T_1656 & _T_1660; // @[ifu_mem_ctl.scala 343:132]
|
|
wire [1:0] _T_1662 = _T_1661 ? 2'h2 : 2'h0; // @[ifu_mem_ctl.scala 343:8]
|
|
wire [1:0] ifu_byp_data_err_f = _T_1647[0] ? 2'h3 : _T_1662; // @[ifu_mem_ctl.scala 342:31]
|
|
wire [1:0] ifc_bus_acc_fault_f = _T_1298 & ifu_byp_data_err_f; // @[ifu_mem_ctl.scala 289:50]
|
|
wire _T_2500 = |ifc_bus_acc_fault_f; // @[ifu_mem_ctl.scala 374:136]
|
|
wire _T_2501 = ifc_region_acc_fault_final_f | _T_2500; // @[ifu_mem_ctl.scala 374:113]
|
|
wire _T_2502 = ~_T_2501; // @[ifu_mem_ctl.scala 374:82]
|
|
wire _T_2503 = _T_2499 & _T_2502; // @[ifu_mem_ctl.scala 374:80]
|
|
wire _T_2505 = fetch_req_icache_f & _T_198; // @[ifu_mem_ctl.scala 375:25]
|
|
wire _T_2509 = _T_2505 & _T_218; // @[ifu_mem_ctl.scala 375:43]
|
|
wire _T_2511 = _T_2509 & _T_253; // @[ifu_mem_ctl.scala 375:91]
|
|
wire ic_rd_parity_final_err = _T_2503 & _T_2511; // @[ifu_mem_ctl.scala 374:142]
|
|
reg ic_debug_ict_array_sel_ff; // @[Reg.scala 27:20]
|
|
reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20]
|
|
wire _T_10124 = _T_4900 & ic_tag_valid_out_1_0; // @[ifu_mem_ctl.scala 656:8]
|
|
reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20]
|
|
wire _T_10126 = _T_4901 & ic_tag_valid_out_1_1; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10379 = _T_10124 | _T_10126; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20]
|
|
wire _T_10128 = _T_4902 & ic_tag_valid_out_1_2; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10380 = _T_10379 | _T_10128; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20]
|
|
wire _T_10130 = _T_4903 & ic_tag_valid_out_1_3; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10381 = _T_10380 | _T_10130; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20]
|
|
wire _T_10132 = _T_4904 & ic_tag_valid_out_1_4; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10382 = _T_10381 | _T_10132; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20]
|
|
wire _T_10134 = _T_4905 & ic_tag_valid_out_1_5; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10383 = _T_10382 | _T_10134; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20]
|
|
wire _T_10136 = _T_4906 & ic_tag_valid_out_1_6; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10384 = _T_10383 | _T_10136; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20]
|
|
wire _T_10138 = _T_4907 & ic_tag_valid_out_1_7; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10385 = _T_10384 | _T_10138; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20]
|
|
wire _T_10140 = _T_4908 & ic_tag_valid_out_1_8; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10386 = _T_10385 | _T_10140; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20]
|
|
wire _T_10142 = _T_4909 & ic_tag_valid_out_1_9; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10387 = _T_10386 | _T_10142; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20]
|
|
wire _T_10144 = _T_4910 & ic_tag_valid_out_1_10; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10388 = _T_10387 | _T_10144; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20]
|
|
wire _T_10146 = _T_4911 & ic_tag_valid_out_1_11; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10389 = _T_10388 | _T_10146; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20]
|
|
wire _T_10148 = _T_4912 & ic_tag_valid_out_1_12; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10390 = _T_10389 | _T_10148; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20]
|
|
wire _T_10150 = _T_4913 & ic_tag_valid_out_1_13; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10391 = _T_10390 | _T_10150; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20]
|
|
wire _T_10152 = _T_4914 & ic_tag_valid_out_1_14; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10392 = _T_10391 | _T_10152; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20]
|
|
wire _T_10154 = _T_4915 & ic_tag_valid_out_1_15; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10393 = _T_10392 | _T_10154; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20]
|
|
wire _T_10156 = _T_4916 & ic_tag_valid_out_1_16; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10394 = _T_10393 | _T_10156; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20]
|
|
wire _T_10158 = _T_4917 & ic_tag_valid_out_1_17; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10395 = _T_10394 | _T_10158; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20]
|
|
wire _T_10160 = _T_4918 & ic_tag_valid_out_1_18; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10396 = _T_10395 | _T_10160; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20]
|
|
wire _T_10162 = _T_4919 & ic_tag_valid_out_1_19; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10397 = _T_10396 | _T_10162; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20]
|
|
wire _T_10164 = _T_4920 & ic_tag_valid_out_1_20; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10398 = _T_10397 | _T_10164; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20]
|
|
wire _T_10166 = _T_4921 & ic_tag_valid_out_1_21; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10399 = _T_10398 | _T_10166; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20]
|
|
wire _T_10168 = _T_4922 & ic_tag_valid_out_1_22; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10400 = _T_10399 | _T_10168; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20]
|
|
wire _T_10170 = _T_4923 & ic_tag_valid_out_1_23; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10401 = _T_10400 | _T_10170; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20]
|
|
wire _T_10172 = _T_4924 & ic_tag_valid_out_1_24; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10402 = _T_10401 | _T_10172; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20]
|
|
wire _T_10174 = _T_4925 & ic_tag_valid_out_1_25; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10403 = _T_10402 | _T_10174; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20]
|
|
wire _T_10176 = _T_4926 & ic_tag_valid_out_1_26; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10404 = _T_10403 | _T_10176; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20]
|
|
wire _T_10178 = _T_4927 & ic_tag_valid_out_1_27; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10405 = _T_10404 | _T_10178; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20]
|
|
wire _T_10180 = _T_4928 & ic_tag_valid_out_1_28; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10406 = _T_10405 | _T_10180; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20]
|
|
wire _T_10182 = _T_4929 & ic_tag_valid_out_1_29; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10407 = _T_10406 | _T_10182; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20]
|
|
wire _T_10184 = _T_4930 & ic_tag_valid_out_1_30; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10408 = _T_10407 | _T_10184; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20]
|
|
wire _T_10186 = _T_4931 & ic_tag_valid_out_1_31; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10409 = _T_10408 | _T_10186; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20]
|
|
wire _T_10188 = _T_4932 & ic_tag_valid_out_1_32; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10410 = _T_10409 | _T_10188; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20]
|
|
wire _T_10190 = _T_4933 & ic_tag_valid_out_1_33; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10411 = _T_10410 | _T_10190; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20]
|
|
wire _T_10192 = _T_4934 & ic_tag_valid_out_1_34; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10412 = _T_10411 | _T_10192; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20]
|
|
wire _T_10194 = _T_4935 & ic_tag_valid_out_1_35; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10413 = _T_10412 | _T_10194; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20]
|
|
wire _T_10196 = _T_4936 & ic_tag_valid_out_1_36; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10414 = _T_10413 | _T_10196; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20]
|
|
wire _T_10198 = _T_4937 & ic_tag_valid_out_1_37; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10415 = _T_10414 | _T_10198; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20]
|
|
wire _T_10200 = _T_4938 & ic_tag_valid_out_1_38; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10416 = _T_10415 | _T_10200; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20]
|
|
wire _T_10202 = _T_4939 & ic_tag_valid_out_1_39; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10417 = _T_10416 | _T_10202; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20]
|
|
wire _T_10204 = _T_4940 & ic_tag_valid_out_1_40; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10418 = _T_10417 | _T_10204; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20]
|
|
wire _T_10206 = _T_4941 & ic_tag_valid_out_1_41; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10419 = _T_10418 | _T_10206; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20]
|
|
wire _T_10208 = _T_4942 & ic_tag_valid_out_1_42; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10420 = _T_10419 | _T_10208; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20]
|
|
wire _T_10210 = _T_4943 & ic_tag_valid_out_1_43; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10421 = _T_10420 | _T_10210; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20]
|
|
wire _T_10212 = _T_4944 & ic_tag_valid_out_1_44; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10422 = _T_10421 | _T_10212; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20]
|
|
wire _T_10214 = _T_4945 & ic_tag_valid_out_1_45; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10423 = _T_10422 | _T_10214; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20]
|
|
wire _T_10216 = _T_4946 & ic_tag_valid_out_1_46; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10424 = _T_10423 | _T_10216; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20]
|
|
wire _T_10218 = _T_4947 & ic_tag_valid_out_1_47; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10425 = _T_10424 | _T_10218; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20]
|
|
wire _T_10220 = _T_4948 & ic_tag_valid_out_1_48; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10426 = _T_10425 | _T_10220; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20]
|
|
wire _T_10222 = _T_4949 & ic_tag_valid_out_1_49; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10427 = _T_10426 | _T_10222; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20]
|
|
wire _T_10224 = _T_4950 & ic_tag_valid_out_1_50; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10428 = _T_10427 | _T_10224; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20]
|
|
wire _T_10226 = _T_4951 & ic_tag_valid_out_1_51; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10429 = _T_10428 | _T_10226; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20]
|
|
wire _T_10228 = _T_4952 & ic_tag_valid_out_1_52; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10430 = _T_10429 | _T_10228; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20]
|
|
wire _T_10230 = _T_4953 & ic_tag_valid_out_1_53; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10431 = _T_10430 | _T_10230; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20]
|
|
wire _T_10232 = _T_4954 & ic_tag_valid_out_1_54; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10432 = _T_10431 | _T_10232; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20]
|
|
wire _T_10234 = _T_4955 & ic_tag_valid_out_1_55; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10433 = _T_10432 | _T_10234; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20]
|
|
wire _T_10236 = _T_4956 & ic_tag_valid_out_1_56; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10434 = _T_10433 | _T_10236; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20]
|
|
wire _T_10238 = _T_4957 & ic_tag_valid_out_1_57; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10435 = _T_10434 | _T_10238; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20]
|
|
wire _T_10240 = _T_4958 & ic_tag_valid_out_1_58; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10436 = _T_10435 | _T_10240; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20]
|
|
wire _T_10242 = _T_4959 & ic_tag_valid_out_1_59; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10437 = _T_10436 | _T_10242; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20]
|
|
wire _T_10244 = _T_4960 & ic_tag_valid_out_1_60; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10438 = _T_10437 | _T_10244; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20]
|
|
wire _T_10246 = _T_4961 & ic_tag_valid_out_1_61; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10439 = _T_10438 | _T_10246; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20]
|
|
wire _T_10248 = _T_4962 & ic_tag_valid_out_1_62; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10440 = _T_10439 | _T_10248; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20]
|
|
wire _T_10250 = _T_4963 & ic_tag_valid_out_1_63; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10441 = _T_10440 | _T_10250; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20]
|
|
wire _T_10252 = _T_4964 & ic_tag_valid_out_1_64; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10442 = _T_10441 | _T_10252; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20]
|
|
wire _T_10254 = _T_4965 & ic_tag_valid_out_1_65; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10443 = _T_10442 | _T_10254; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20]
|
|
wire _T_10256 = _T_4966 & ic_tag_valid_out_1_66; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10444 = _T_10443 | _T_10256; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20]
|
|
wire _T_10258 = _T_4967 & ic_tag_valid_out_1_67; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10445 = _T_10444 | _T_10258; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20]
|
|
wire _T_10260 = _T_4968 & ic_tag_valid_out_1_68; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10446 = _T_10445 | _T_10260; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20]
|
|
wire _T_10262 = _T_4969 & ic_tag_valid_out_1_69; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10447 = _T_10446 | _T_10262; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20]
|
|
wire _T_10264 = _T_4970 & ic_tag_valid_out_1_70; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10448 = _T_10447 | _T_10264; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20]
|
|
wire _T_10266 = _T_4971 & ic_tag_valid_out_1_71; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10449 = _T_10448 | _T_10266; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20]
|
|
wire _T_10268 = _T_4972 & ic_tag_valid_out_1_72; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10450 = _T_10449 | _T_10268; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20]
|
|
wire _T_10270 = _T_4973 & ic_tag_valid_out_1_73; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10451 = _T_10450 | _T_10270; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20]
|
|
wire _T_10272 = _T_4974 & ic_tag_valid_out_1_74; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10452 = _T_10451 | _T_10272; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20]
|
|
wire _T_10274 = _T_4975 & ic_tag_valid_out_1_75; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10453 = _T_10452 | _T_10274; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20]
|
|
wire _T_10276 = _T_4976 & ic_tag_valid_out_1_76; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10454 = _T_10453 | _T_10276; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20]
|
|
wire _T_10278 = _T_4977 & ic_tag_valid_out_1_77; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10455 = _T_10454 | _T_10278; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20]
|
|
wire _T_10280 = _T_4978 & ic_tag_valid_out_1_78; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10456 = _T_10455 | _T_10280; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20]
|
|
wire _T_10282 = _T_4979 & ic_tag_valid_out_1_79; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10457 = _T_10456 | _T_10282; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20]
|
|
wire _T_10284 = _T_4980 & ic_tag_valid_out_1_80; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10458 = _T_10457 | _T_10284; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20]
|
|
wire _T_10286 = _T_4981 & ic_tag_valid_out_1_81; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10459 = _T_10458 | _T_10286; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20]
|
|
wire _T_10288 = _T_4982 & ic_tag_valid_out_1_82; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10460 = _T_10459 | _T_10288; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20]
|
|
wire _T_10290 = _T_4983 & ic_tag_valid_out_1_83; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10461 = _T_10460 | _T_10290; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20]
|
|
wire _T_10292 = _T_4984 & ic_tag_valid_out_1_84; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10462 = _T_10461 | _T_10292; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20]
|
|
wire _T_10294 = _T_4985 & ic_tag_valid_out_1_85; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10463 = _T_10462 | _T_10294; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20]
|
|
wire _T_10296 = _T_4986 & ic_tag_valid_out_1_86; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10464 = _T_10463 | _T_10296; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20]
|
|
wire _T_10298 = _T_4987 & ic_tag_valid_out_1_87; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10465 = _T_10464 | _T_10298; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20]
|
|
wire _T_10300 = _T_4988 & ic_tag_valid_out_1_88; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10466 = _T_10465 | _T_10300; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20]
|
|
wire _T_10302 = _T_4989 & ic_tag_valid_out_1_89; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10467 = _T_10466 | _T_10302; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20]
|
|
wire _T_10304 = _T_4990 & ic_tag_valid_out_1_90; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10468 = _T_10467 | _T_10304; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20]
|
|
wire _T_10306 = _T_4991 & ic_tag_valid_out_1_91; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10469 = _T_10468 | _T_10306; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20]
|
|
wire _T_10308 = _T_4992 & ic_tag_valid_out_1_92; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10470 = _T_10469 | _T_10308; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20]
|
|
wire _T_10310 = _T_4993 & ic_tag_valid_out_1_93; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10471 = _T_10470 | _T_10310; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20]
|
|
wire _T_10312 = _T_4994 & ic_tag_valid_out_1_94; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10472 = _T_10471 | _T_10312; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20]
|
|
wire _T_10314 = _T_4995 & ic_tag_valid_out_1_95; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10473 = _T_10472 | _T_10314; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20]
|
|
wire _T_10316 = _T_4996 & ic_tag_valid_out_1_96; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10474 = _T_10473 | _T_10316; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20]
|
|
wire _T_10318 = _T_4997 & ic_tag_valid_out_1_97; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10475 = _T_10474 | _T_10318; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20]
|
|
wire _T_10320 = _T_4998 & ic_tag_valid_out_1_98; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10476 = _T_10475 | _T_10320; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20]
|
|
wire _T_10322 = _T_4999 & ic_tag_valid_out_1_99; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10477 = _T_10476 | _T_10322; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20]
|
|
wire _T_10324 = _T_5000 & ic_tag_valid_out_1_100; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10478 = _T_10477 | _T_10324; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20]
|
|
wire _T_10326 = _T_5001 & ic_tag_valid_out_1_101; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10479 = _T_10478 | _T_10326; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20]
|
|
wire _T_10328 = _T_5002 & ic_tag_valid_out_1_102; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10480 = _T_10479 | _T_10328; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20]
|
|
wire _T_10330 = _T_5003 & ic_tag_valid_out_1_103; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10481 = _T_10480 | _T_10330; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20]
|
|
wire _T_10332 = _T_5004 & ic_tag_valid_out_1_104; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10482 = _T_10481 | _T_10332; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20]
|
|
wire _T_10334 = _T_5005 & ic_tag_valid_out_1_105; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10483 = _T_10482 | _T_10334; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20]
|
|
wire _T_10336 = _T_5006 & ic_tag_valid_out_1_106; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10484 = _T_10483 | _T_10336; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20]
|
|
wire _T_10338 = _T_5007 & ic_tag_valid_out_1_107; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10485 = _T_10484 | _T_10338; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20]
|
|
wire _T_10340 = _T_5008 & ic_tag_valid_out_1_108; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10486 = _T_10485 | _T_10340; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20]
|
|
wire _T_10342 = _T_5009 & ic_tag_valid_out_1_109; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10487 = _T_10486 | _T_10342; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20]
|
|
wire _T_10344 = _T_5010 & ic_tag_valid_out_1_110; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10488 = _T_10487 | _T_10344; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20]
|
|
wire _T_10346 = _T_5011 & ic_tag_valid_out_1_111; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10489 = _T_10488 | _T_10346; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20]
|
|
wire _T_10348 = _T_5012 & ic_tag_valid_out_1_112; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10490 = _T_10489 | _T_10348; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20]
|
|
wire _T_10350 = _T_5013 & ic_tag_valid_out_1_113; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10491 = _T_10490 | _T_10350; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20]
|
|
wire _T_10352 = _T_5014 & ic_tag_valid_out_1_114; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10492 = _T_10491 | _T_10352; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20]
|
|
wire _T_10354 = _T_5015 & ic_tag_valid_out_1_115; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10493 = _T_10492 | _T_10354; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20]
|
|
wire _T_10356 = _T_5016 & ic_tag_valid_out_1_116; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10494 = _T_10493 | _T_10356; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20]
|
|
wire _T_10358 = _T_5017 & ic_tag_valid_out_1_117; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10495 = _T_10494 | _T_10358; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20]
|
|
wire _T_10360 = _T_5018 & ic_tag_valid_out_1_118; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10496 = _T_10495 | _T_10360; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20]
|
|
wire _T_10362 = _T_5019 & ic_tag_valid_out_1_119; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10497 = _T_10496 | _T_10362; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20]
|
|
wire _T_10364 = _T_5020 & ic_tag_valid_out_1_120; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10498 = _T_10497 | _T_10364; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20]
|
|
wire _T_10366 = _T_5021 & ic_tag_valid_out_1_121; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10499 = _T_10498 | _T_10366; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20]
|
|
wire _T_10368 = _T_5022 & ic_tag_valid_out_1_122; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10500 = _T_10499 | _T_10368; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20]
|
|
wire _T_10370 = _T_5023 & ic_tag_valid_out_1_123; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10501 = _T_10500 | _T_10370; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20]
|
|
wire _T_10372 = _T_5024 & ic_tag_valid_out_1_124; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10502 = _T_10501 | _T_10372; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20]
|
|
wire _T_10374 = _T_5025 & ic_tag_valid_out_1_125; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10503 = _T_10502 | _T_10374; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20]
|
|
wire _T_10376 = _T_5026 & ic_tag_valid_out_1_126; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10504 = _T_10503 | _T_10376; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20]
|
|
wire _T_10378 = _T_5027 & ic_tag_valid_out_1_127; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10505 = _T_10504 | _T_10378; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20]
|
|
wire _T_9741 = _T_4900 & ic_tag_valid_out_0_0; // @[ifu_mem_ctl.scala 656:8]
|
|
reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20]
|
|
wire _T_9743 = _T_4901 & ic_tag_valid_out_0_1; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_9996 = _T_9741 | _T_9743; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20]
|
|
wire _T_9745 = _T_4902 & ic_tag_valid_out_0_2; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_9997 = _T_9996 | _T_9745; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20]
|
|
wire _T_9747 = _T_4903 & ic_tag_valid_out_0_3; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_9998 = _T_9997 | _T_9747; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20]
|
|
wire _T_9749 = _T_4904 & ic_tag_valid_out_0_4; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_9999 = _T_9998 | _T_9749; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20]
|
|
wire _T_9751 = _T_4905 & ic_tag_valid_out_0_5; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10000 = _T_9999 | _T_9751; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20]
|
|
wire _T_9753 = _T_4906 & ic_tag_valid_out_0_6; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10001 = _T_10000 | _T_9753; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20]
|
|
wire _T_9755 = _T_4907 & ic_tag_valid_out_0_7; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10002 = _T_10001 | _T_9755; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20]
|
|
wire _T_9757 = _T_4908 & ic_tag_valid_out_0_8; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10003 = _T_10002 | _T_9757; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20]
|
|
wire _T_9759 = _T_4909 & ic_tag_valid_out_0_9; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10004 = _T_10003 | _T_9759; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20]
|
|
wire _T_9761 = _T_4910 & ic_tag_valid_out_0_10; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10005 = _T_10004 | _T_9761; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20]
|
|
wire _T_9763 = _T_4911 & ic_tag_valid_out_0_11; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10006 = _T_10005 | _T_9763; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20]
|
|
wire _T_9765 = _T_4912 & ic_tag_valid_out_0_12; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10007 = _T_10006 | _T_9765; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20]
|
|
wire _T_9767 = _T_4913 & ic_tag_valid_out_0_13; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10008 = _T_10007 | _T_9767; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20]
|
|
wire _T_9769 = _T_4914 & ic_tag_valid_out_0_14; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10009 = _T_10008 | _T_9769; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20]
|
|
wire _T_9771 = _T_4915 & ic_tag_valid_out_0_15; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10010 = _T_10009 | _T_9771; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20]
|
|
wire _T_9773 = _T_4916 & ic_tag_valid_out_0_16; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10011 = _T_10010 | _T_9773; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20]
|
|
wire _T_9775 = _T_4917 & ic_tag_valid_out_0_17; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10012 = _T_10011 | _T_9775; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20]
|
|
wire _T_9777 = _T_4918 & ic_tag_valid_out_0_18; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10013 = _T_10012 | _T_9777; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20]
|
|
wire _T_9779 = _T_4919 & ic_tag_valid_out_0_19; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10014 = _T_10013 | _T_9779; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20]
|
|
wire _T_9781 = _T_4920 & ic_tag_valid_out_0_20; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10015 = _T_10014 | _T_9781; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20]
|
|
wire _T_9783 = _T_4921 & ic_tag_valid_out_0_21; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10016 = _T_10015 | _T_9783; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20]
|
|
wire _T_9785 = _T_4922 & ic_tag_valid_out_0_22; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10017 = _T_10016 | _T_9785; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20]
|
|
wire _T_9787 = _T_4923 & ic_tag_valid_out_0_23; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10018 = _T_10017 | _T_9787; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20]
|
|
wire _T_9789 = _T_4924 & ic_tag_valid_out_0_24; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10019 = _T_10018 | _T_9789; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20]
|
|
wire _T_9791 = _T_4925 & ic_tag_valid_out_0_25; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10020 = _T_10019 | _T_9791; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20]
|
|
wire _T_9793 = _T_4926 & ic_tag_valid_out_0_26; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10021 = _T_10020 | _T_9793; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20]
|
|
wire _T_9795 = _T_4927 & ic_tag_valid_out_0_27; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10022 = _T_10021 | _T_9795; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20]
|
|
wire _T_9797 = _T_4928 & ic_tag_valid_out_0_28; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10023 = _T_10022 | _T_9797; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20]
|
|
wire _T_9799 = _T_4929 & ic_tag_valid_out_0_29; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10024 = _T_10023 | _T_9799; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20]
|
|
wire _T_9801 = _T_4930 & ic_tag_valid_out_0_30; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10025 = _T_10024 | _T_9801; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20]
|
|
wire _T_9803 = _T_4931 & ic_tag_valid_out_0_31; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10026 = _T_10025 | _T_9803; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20]
|
|
wire _T_9805 = _T_4932 & ic_tag_valid_out_0_32; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10027 = _T_10026 | _T_9805; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20]
|
|
wire _T_9807 = _T_4933 & ic_tag_valid_out_0_33; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10028 = _T_10027 | _T_9807; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20]
|
|
wire _T_9809 = _T_4934 & ic_tag_valid_out_0_34; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10029 = _T_10028 | _T_9809; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20]
|
|
wire _T_9811 = _T_4935 & ic_tag_valid_out_0_35; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10030 = _T_10029 | _T_9811; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20]
|
|
wire _T_9813 = _T_4936 & ic_tag_valid_out_0_36; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10031 = _T_10030 | _T_9813; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20]
|
|
wire _T_9815 = _T_4937 & ic_tag_valid_out_0_37; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10032 = _T_10031 | _T_9815; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20]
|
|
wire _T_9817 = _T_4938 & ic_tag_valid_out_0_38; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10033 = _T_10032 | _T_9817; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20]
|
|
wire _T_9819 = _T_4939 & ic_tag_valid_out_0_39; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10034 = _T_10033 | _T_9819; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20]
|
|
wire _T_9821 = _T_4940 & ic_tag_valid_out_0_40; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10035 = _T_10034 | _T_9821; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20]
|
|
wire _T_9823 = _T_4941 & ic_tag_valid_out_0_41; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10036 = _T_10035 | _T_9823; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20]
|
|
wire _T_9825 = _T_4942 & ic_tag_valid_out_0_42; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10037 = _T_10036 | _T_9825; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20]
|
|
wire _T_9827 = _T_4943 & ic_tag_valid_out_0_43; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10038 = _T_10037 | _T_9827; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20]
|
|
wire _T_9829 = _T_4944 & ic_tag_valid_out_0_44; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10039 = _T_10038 | _T_9829; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20]
|
|
wire _T_9831 = _T_4945 & ic_tag_valid_out_0_45; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10040 = _T_10039 | _T_9831; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20]
|
|
wire _T_9833 = _T_4946 & ic_tag_valid_out_0_46; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10041 = _T_10040 | _T_9833; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20]
|
|
wire _T_9835 = _T_4947 & ic_tag_valid_out_0_47; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10042 = _T_10041 | _T_9835; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20]
|
|
wire _T_9837 = _T_4948 & ic_tag_valid_out_0_48; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10043 = _T_10042 | _T_9837; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20]
|
|
wire _T_9839 = _T_4949 & ic_tag_valid_out_0_49; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10044 = _T_10043 | _T_9839; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20]
|
|
wire _T_9841 = _T_4950 & ic_tag_valid_out_0_50; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10045 = _T_10044 | _T_9841; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20]
|
|
wire _T_9843 = _T_4951 & ic_tag_valid_out_0_51; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10046 = _T_10045 | _T_9843; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20]
|
|
wire _T_9845 = _T_4952 & ic_tag_valid_out_0_52; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10047 = _T_10046 | _T_9845; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20]
|
|
wire _T_9847 = _T_4953 & ic_tag_valid_out_0_53; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10048 = _T_10047 | _T_9847; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20]
|
|
wire _T_9849 = _T_4954 & ic_tag_valid_out_0_54; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10049 = _T_10048 | _T_9849; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20]
|
|
wire _T_9851 = _T_4955 & ic_tag_valid_out_0_55; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10050 = _T_10049 | _T_9851; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20]
|
|
wire _T_9853 = _T_4956 & ic_tag_valid_out_0_56; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10051 = _T_10050 | _T_9853; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20]
|
|
wire _T_9855 = _T_4957 & ic_tag_valid_out_0_57; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10052 = _T_10051 | _T_9855; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20]
|
|
wire _T_9857 = _T_4958 & ic_tag_valid_out_0_58; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10053 = _T_10052 | _T_9857; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20]
|
|
wire _T_9859 = _T_4959 & ic_tag_valid_out_0_59; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10054 = _T_10053 | _T_9859; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20]
|
|
wire _T_9861 = _T_4960 & ic_tag_valid_out_0_60; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10055 = _T_10054 | _T_9861; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20]
|
|
wire _T_9863 = _T_4961 & ic_tag_valid_out_0_61; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10056 = _T_10055 | _T_9863; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20]
|
|
wire _T_9865 = _T_4962 & ic_tag_valid_out_0_62; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10057 = _T_10056 | _T_9865; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20]
|
|
wire _T_9867 = _T_4963 & ic_tag_valid_out_0_63; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10058 = _T_10057 | _T_9867; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20]
|
|
wire _T_9869 = _T_4964 & ic_tag_valid_out_0_64; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10059 = _T_10058 | _T_9869; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20]
|
|
wire _T_9871 = _T_4965 & ic_tag_valid_out_0_65; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10060 = _T_10059 | _T_9871; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20]
|
|
wire _T_9873 = _T_4966 & ic_tag_valid_out_0_66; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10061 = _T_10060 | _T_9873; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20]
|
|
wire _T_9875 = _T_4967 & ic_tag_valid_out_0_67; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10062 = _T_10061 | _T_9875; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20]
|
|
wire _T_9877 = _T_4968 & ic_tag_valid_out_0_68; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10063 = _T_10062 | _T_9877; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20]
|
|
wire _T_9879 = _T_4969 & ic_tag_valid_out_0_69; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10064 = _T_10063 | _T_9879; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20]
|
|
wire _T_9881 = _T_4970 & ic_tag_valid_out_0_70; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10065 = _T_10064 | _T_9881; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20]
|
|
wire _T_9883 = _T_4971 & ic_tag_valid_out_0_71; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10066 = _T_10065 | _T_9883; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20]
|
|
wire _T_9885 = _T_4972 & ic_tag_valid_out_0_72; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10067 = _T_10066 | _T_9885; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20]
|
|
wire _T_9887 = _T_4973 & ic_tag_valid_out_0_73; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10068 = _T_10067 | _T_9887; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20]
|
|
wire _T_9889 = _T_4974 & ic_tag_valid_out_0_74; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10069 = _T_10068 | _T_9889; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20]
|
|
wire _T_9891 = _T_4975 & ic_tag_valid_out_0_75; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10070 = _T_10069 | _T_9891; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20]
|
|
wire _T_9893 = _T_4976 & ic_tag_valid_out_0_76; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10071 = _T_10070 | _T_9893; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20]
|
|
wire _T_9895 = _T_4977 & ic_tag_valid_out_0_77; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10072 = _T_10071 | _T_9895; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20]
|
|
wire _T_9897 = _T_4978 & ic_tag_valid_out_0_78; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10073 = _T_10072 | _T_9897; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20]
|
|
wire _T_9899 = _T_4979 & ic_tag_valid_out_0_79; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10074 = _T_10073 | _T_9899; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20]
|
|
wire _T_9901 = _T_4980 & ic_tag_valid_out_0_80; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10075 = _T_10074 | _T_9901; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20]
|
|
wire _T_9903 = _T_4981 & ic_tag_valid_out_0_81; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10076 = _T_10075 | _T_9903; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20]
|
|
wire _T_9905 = _T_4982 & ic_tag_valid_out_0_82; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10077 = _T_10076 | _T_9905; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20]
|
|
wire _T_9907 = _T_4983 & ic_tag_valid_out_0_83; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10078 = _T_10077 | _T_9907; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20]
|
|
wire _T_9909 = _T_4984 & ic_tag_valid_out_0_84; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10079 = _T_10078 | _T_9909; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20]
|
|
wire _T_9911 = _T_4985 & ic_tag_valid_out_0_85; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10080 = _T_10079 | _T_9911; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20]
|
|
wire _T_9913 = _T_4986 & ic_tag_valid_out_0_86; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10081 = _T_10080 | _T_9913; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20]
|
|
wire _T_9915 = _T_4987 & ic_tag_valid_out_0_87; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10082 = _T_10081 | _T_9915; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20]
|
|
wire _T_9917 = _T_4988 & ic_tag_valid_out_0_88; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10083 = _T_10082 | _T_9917; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20]
|
|
wire _T_9919 = _T_4989 & ic_tag_valid_out_0_89; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10084 = _T_10083 | _T_9919; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20]
|
|
wire _T_9921 = _T_4990 & ic_tag_valid_out_0_90; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10085 = _T_10084 | _T_9921; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20]
|
|
wire _T_9923 = _T_4991 & ic_tag_valid_out_0_91; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10086 = _T_10085 | _T_9923; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20]
|
|
wire _T_9925 = _T_4992 & ic_tag_valid_out_0_92; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10087 = _T_10086 | _T_9925; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20]
|
|
wire _T_9927 = _T_4993 & ic_tag_valid_out_0_93; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10088 = _T_10087 | _T_9927; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20]
|
|
wire _T_9929 = _T_4994 & ic_tag_valid_out_0_94; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10089 = _T_10088 | _T_9929; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20]
|
|
wire _T_9931 = _T_4995 & ic_tag_valid_out_0_95; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10090 = _T_10089 | _T_9931; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20]
|
|
wire _T_9933 = _T_4996 & ic_tag_valid_out_0_96; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10091 = _T_10090 | _T_9933; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20]
|
|
wire _T_9935 = _T_4997 & ic_tag_valid_out_0_97; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10092 = _T_10091 | _T_9935; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20]
|
|
wire _T_9937 = _T_4998 & ic_tag_valid_out_0_98; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10093 = _T_10092 | _T_9937; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20]
|
|
wire _T_9939 = _T_4999 & ic_tag_valid_out_0_99; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10094 = _T_10093 | _T_9939; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20]
|
|
wire _T_9941 = _T_5000 & ic_tag_valid_out_0_100; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10095 = _T_10094 | _T_9941; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20]
|
|
wire _T_9943 = _T_5001 & ic_tag_valid_out_0_101; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10096 = _T_10095 | _T_9943; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20]
|
|
wire _T_9945 = _T_5002 & ic_tag_valid_out_0_102; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10097 = _T_10096 | _T_9945; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20]
|
|
wire _T_9947 = _T_5003 & ic_tag_valid_out_0_103; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10098 = _T_10097 | _T_9947; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20]
|
|
wire _T_9949 = _T_5004 & ic_tag_valid_out_0_104; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10099 = _T_10098 | _T_9949; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20]
|
|
wire _T_9951 = _T_5005 & ic_tag_valid_out_0_105; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10100 = _T_10099 | _T_9951; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20]
|
|
wire _T_9953 = _T_5006 & ic_tag_valid_out_0_106; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10101 = _T_10100 | _T_9953; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20]
|
|
wire _T_9955 = _T_5007 & ic_tag_valid_out_0_107; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10102 = _T_10101 | _T_9955; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20]
|
|
wire _T_9957 = _T_5008 & ic_tag_valid_out_0_108; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10103 = _T_10102 | _T_9957; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20]
|
|
wire _T_9959 = _T_5009 & ic_tag_valid_out_0_109; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10104 = _T_10103 | _T_9959; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20]
|
|
wire _T_9961 = _T_5010 & ic_tag_valid_out_0_110; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10105 = _T_10104 | _T_9961; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20]
|
|
wire _T_9963 = _T_5011 & ic_tag_valid_out_0_111; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10106 = _T_10105 | _T_9963; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20]
|
|
wire _T_9965 = _T_5012 & ic_tag_valid_out_0_112; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10107 = _T_10106 | _T_9965; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20]
|
|
wire _T_9967 = _T_5013 & ic_tag_valid_out_0_113; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10108 = _T_10107 | _T_9967; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20]
|
|
wire _T_9969 = _T_5014 & ic_tag_valid_out_0_114; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10109 = _T_10108 | _T_9969; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20]
|
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wire _T_9971 = _T_5015 & ic_tag_valid_out_0_115; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10110 = _T_10109 | _T_9971; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20]
|
|
wire _T_9973 = _T_5016 & ic_tag_valid_out_0_116; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10111 = _T_10110 | _T_9973; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20]
|
|
wire _T_9975 = _T_5017 & ic_tag_valid_out_0_117; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10112 = _T_10111 | _T_9975; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20]
|
|
wire _T_9977 = _T_5018 & ic_tag_valid_out_0_118; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10113 = _T_10112 | _T_9977; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20]
|
|
wire _T_9979 = _T_5019 & ic_tag_valid_out_0_119; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10114 = _T_10113 | _T_9979; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20]
|
|
wire _T_9981 = _T_5020 & ic_tag_valid_out_0_120; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10115 = _T_10114 | _T_9981; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20]
|
|
wire _T_9983 = _T_5021 & ic_tag_valid_out_0_121; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10116 = _T_10115 | _T_9983; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20]
|
|
wire _T_9985 = _T_5022 & ic_tag_valid_out_0_122; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10117 = _T_10116 | _T_9985; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20]
|
|
wire _T_9987 = _T_5023 & ic_tag_valid_out_0_123; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10118 = _T_10117 | _T_9987; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20]
|
|
wire _T_9989 = _T_5024 & ic_tag_valid_out_0_124; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10119 = _T_10118 | _T_9989; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20]
|
|
wire _T_9991 = _T_5025 & ic_tag_valid_out_0_125; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10120 = _T_10119 | _T_9991; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20]
|
|
wire _T_9993 = _T_5026 & ic_tag_valid_out_0_126; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10121 = _T_10120 | _T_9993; // @[ifu_mem_ctl.scala 656:85]
|
|
reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20]
|
|
wire _T_9995 = _T_5027 & ic_tag_valid_out_0_127; // @[ifu_mem_ctl.scala 656:8]
|
|
wire _T_10122 = _T_10121 | _T_9995; // @[ifu_mem_ctl.scala 656:85]
|
|
wire [1:0] ic_tag_valid_unq = {_T_10505,_T_10122}; // @[Cat.scala 29:58]
|
|
reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20]
|
|
reg ic_debug_rd_en_ff; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_10545 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10546 = ic_debug_way_ff & _T_10545; // @[ifu_mem_ctl.scala 705:67]
|
|
wire [1:0] _T_10547 = ic_tag_valid_unq & _T_10546; // @[ifu_mem_ctl.scala 705:48]
|
|
wire ic_debug_tag_val_rd_out = |_T_10547; // @[ifu_mem_ctl.scala 705:115]
|
|
wire [70:0] _T_1236 = {2'h0,io_ic_tag_debug_rd_data[25:21],32'h0,io_ic_tag_debug_rd_data[20:0],6'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58]
|
|
reg [70:0] _T_1237; // @[Reg.scala 27:20]
|
|
wire ifu_wr_cumulative_err = ifu_wr_cumulative_err_data & _T_2657; // @[ifu_mem_ctl.scala 270:84]
|
|
wire _T_1271 = ifu_wr_cumulative_err ^ ifu_wr_data_comb_err_ff; // @[lib.scala 466:21]
|
|
wire _T_1272 = |_T_1271; // @[lib.scala 466:29]
|
|
wire _T_1287 = _T_1280 | fetch_req_iccm_f; // @[ifu_mem_ctl.scala 280:61]
|
|
wire _T_1288 = _T_1287 | sel_ic_data; // @[ifu_mem_ctl.scala 280:80]
|
|
wire [63:0] _T_1290 = _T_1288 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] ic_final_data = _T_1290 & io_ic_rd_data; // @[ifu_mem_ctl.scala 280:95]
|
|
wire [63:0] _T_1292 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_1293 = _T_1292 & io_iccm_rd_data; // @[ifu_mem_ctl.scala 284:72]
|
|
wire [63:0] _T_1295 = _T_1280 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_2153 = ~ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 350:31]
|
|
wire _T_1666 = ~ifu_fetch_addr_int_f[1]; // @[ifu_mem_ctl.scala 346:38]
|
|
wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_1667 = byp_fetch_index_inc_0 == 4'h0; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1715 = _T_1667 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire _T_1670 = byp_fetch_index_inc_0 == 4'h1; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1716 = _T_1670 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1731 = _T_1715 | _T_1716; // @[Mux.scala 27:72]
|
|
wire _T_1673 = byp_fetch_index_inc_0 == 4'h2; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1717 = _T_1673 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1732 = _T_1731 | _T_1717; // @[Mux.scala 27:72]
|
|
wire _T_1676 = byp_fetch_index_inc_0 == 4'h3; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1718 = _T_1676 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1733 = _T_1732 | _T_1718; // @[Mux.scala 27:72]
|
|
wire _T_1679 = byp_fetch_index_inc_0 == 4'h4; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1719 = _T_1679 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1734 = _T_1733 | _T_1719; // @[Mux.scala 27:72]
|
|
wire _T_1682 = byp_fetch_index_inc_0 == 4'h5; // @[ifu_mem_ctl.scala 347:73]
|
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wire [15:0] _T_1720 = _T_1682 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1735 = _T_1734 | _T_1720; // @[Mux.scala 27:72]
|
|
wire _T_1685 = byp_fetch_index_inc_0 == 4'h6; // @[ifu_mem_ctl.scala 347:73]
|
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wire [15:0] _T_1721 = _T_1685 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1736 = _T_1735 | _T_1721; // @[Mux.scala 27:72]
|
|
wire _T_1688 = byp_fetch_index_inc_0 == 4'h7; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1722 = _T_1688 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1737 = _T_1736 | _T_1722; // @[Mux.scala 27:72]
|
|
wire _T_1691 = byp_fetch_index_inc_0 == 4'h8; // @[ifu_mem_ctl.scala 347:73]
|
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wire [15:0] _T_1723 = _T_1691 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1738 = _T_1737 | _T_1723; // @[Mux.scala 27:72]
|
|
wire _T_1694 = byp_fetch_index_inc_0 == 4'h9; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1724 = _T_1694 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1739 = _T_1738 | _T_1724; // @[Mux.scala 27:72]
|
|
wire _T_1697 = byp_fetch_index_inc_0 == 4'ha; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1725 = _T_1697 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1740 = _T_1739 | _T_1725; // @[Mux.scala 27:72]
|
|
wire _T_1700 = byp_fetch_index_inc_0 == 4'hb; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1726 = _T_1700 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1741 = _T_1740 | _T_1726; // @[Mux.scala 27:72]
|
|
wire _T_1703 = byp_fetch_index_inc_0 == 4'hc; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1727 = _T_1703 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1742 = _T_1741 | _T_1727; // @[Mux.scala 27:72]
|
|
wire _T_1706 = byp_fetch_index_inc_0 == 4'hd; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1728 = _T_1706 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1743 = _T_1742 | _T_1728; // @[Mux.scala 27:72]
|
|
wire _T_1709 = byp_fetch_index_inc_0 == 4'he; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1729 = _T_1709 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1744 = _T_1743 | _T_1729; // @[Mux.scala 27:72]
|
|
wire _T_1712 = byp_fetch_index_inc_0 == 4'hf; // @[ifu_mem_ctl.scala 347:73]
|
|
wire [15:0] _T_1730 = _T_1712 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1745 = _T_1744 | _T_1730; // @[Mux.scala 27:72]
|
|
wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_1747 = byp_fetch_index_1 == 4'h0; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1795 = _T_1747 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_1750 = byp_fetch_index_1 == 4'h1; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1796 = _T_1750 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1811 = _T_1795 | _T_1796; // @[Mux.scala 27:72]
|
|
wire _T_1753 = byp_fetch_index_1 == 4'h2; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1797 = _T_1753 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1812 = _T_1811 | _T_1797; // @[Mux.scala 27:72]
|
|
wire _T_1756 = byp_fetch_index_1 == 4'h3; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1798 = _T_1756 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1813 = _T_1812 | _T_1798; // @[Mux.scala 27:72]
|
|
wire _T_1759 = byp_fetch_index_1 == 4'h4; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1799 = _T_1759 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1814 = _T_1813 | _T_1799; // @[Mux.scala 27:72]
|
|
wire _T_1762 = byp_fetch_index_1 == 4'h5; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1800 = _T_1762 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1815 = _T_1814 | _T_1800; // @[Mux.scala 27:72]
|
|
wire _T_1765 = byp_fetch_index_1 == 4'h6; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1801 = _T_1765 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1816 = _T_1815 | _T_1801; // @[Mux.scala 27:72]
|
|
wire _T_1768 = byp_fetch_index_1 == 4'h7; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1802 = _T_1768 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1817 = _T_1816 | _T_1802; // @[Mux.scala 27:72]
|
|
wire _T_1771 = byp_fetch_index_1 == 4'h8; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1803 = _T_1771 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1818 = _T_1817 | _T_1803; // @[Mux.scala 27:72]
|
|
wire _T_1774 = byp_fetch_index_1 == 4'h9; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1804 = _T_1774 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1819 = _T_1818 | _T_1804; // @[Mux.scala 27:72]
|
|
wire _T_1777 = byp_fetch_index_1 == 4'ha; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1805 = _T_1777 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1820 = _T_1819 | _T_1805; // @[Mux.scala 27:72]
|
|
wire _T_1780 = byp_fetch_index_1 == 4'hb; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1806 = _T_1780 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1821 = _T_1820 | _T_1806; // @[Mux.scala 27:72]
|
|
wire _T_1783 = byp_fetch_index_1 == 4'hc; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1807 = _T_1783 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1822 = _T_1821 | _T_1807; // @[Mux.scala 27:72]
|
|
wire _T_1786 = byp_fetch_index_1 == 4'hd; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1808 = _T_1786 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1823 = _T_1822 | _T_1808; // @[Mux.scala 27:72]
|
|
wire _T_1789 = byp_fetch_index_1 == 4'he; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1809 = _T_1789 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1824 = _T_1823 | _T_1809; // @[Mux.scala 27:72]
|
|
wire _T_1792 = byp_fetch_index_1 == 4'hf; // @[ifu_mem_ctl.scala 347:179]
|
|
wire [31:0] _T_1810 = _T_1792 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1825 = _T_1824 | _T_1810; // @[Mux.scala 27:72]
|
|
wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_1827 = byp_fetch_index_0 == 4'h0; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1875 = _T_1827 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_1830 = byp_fetch_index_0 == 4'h1; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1876 = _T_1830 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1891 = _T_1875 | _T_1876; // @[Mux.scala 27:72]
|
|
wire _T_1833 = byp_fetch_index_0 == 4'h2; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1877 = _T_1833 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1892 = _T_1891 | _T_1877; // @[Mux.scala 27:72]
|
|
wire _T_1836 = byp_fetch_index_0 == 4'h3; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1878 = _T_1836 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1893 = _T_1892 | _T_1878; // @[Mux.scala 27:72]
|
|
wire _T_1839 = byp_fetch_index_0 == 4'h4; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1879 = _T_1839 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1894 = _T_1893 | _T_1879; // @[Mux.scala 27:72]
|
|
wire _T_1842 = byp_fetch_index_0 == 4'h5; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1880 = _T_1842 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1895 = _T_1894 | _T_1880; // @[Mux.scala 27:72]
|
|
wire _T_1845 = byp_fetch_index_0 == 4'h6; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1881 = _T_1845 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1896 = _T_1895 | _T_1881; // @[Mux.scala 27:72]
|
|
wire _T_1848 = byp_fetch_index_0 == 4'h7; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1882 = _T_1848 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1897 = _T_1896 | _T_1882; // @[Mux.scala 27:72]
|
|
wire _T_1851 = byp_fetch_index_0 == 4'h8; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1883 = _T_1851 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1898 = _T_1897 | _T_1883; // @[Mux.scala 27:72]
|
|
wire _T_1854 = byp_fetch_index_0 == 4'h9; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1884 = _T_1854 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1899 = _T_1898 | _T_1884; // @[Mux.scala 27:72]
|
|
wire _T_1857 = byp_fetch_index_0 == 4'ha; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1885 = _T_1857 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1900 = _T_1899 | _T_1885; // @[Mux.scala 27:72]
|
|
wire _T_1860 = byp_fetch_index_0 == 4'hb; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1886 = _T_1860 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1901 = _T_1900 | _T_1886; // @[Mux.scala 27:72]
|
|
wire _T_1863 = byp_fetch_index_0 == 4'hc; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1887 = _T_1863 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1902 = _T_1901 | _T_1887; // @[Mux.scala 27:72]
|
|
wire _T_1866 = byp_fetch_index_0 == 4'hd; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1888 = _T_1866 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1903 = _T_1902 | _T_1888; // @[Mux.scala 27:72]
|
|
wire _T_1869 = byp_fetch_index_0 == 4'he; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1889 = _T_1869 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1904 = _T_1903 | _T_1889; // @[Mux.scala 27:72]
|
|
wire _T_1872 = byp_fetch_index_0 == 4'hf; // @[ifu_mem_ctl.scala 347:285]
|
|
wire [31:0] _T_1890 = _T_1872 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1905 = _T_1904 | _T_1890; // @[Mux.scala 27:72]
|
|
wire [79:0] _T_1908 = {_T_1745,_T_1825,_T_1905}; // @[Cat.scala 29:58]
|
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wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58]
|
|
wire _T_1909 = byp_fetch_index_inc_1 == 4'h0; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1957 = _T_1909 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire _T_1912 = byp_fetch_index_inc_1 == 4'h1; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1958 = _T_1912 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1973 = _T_1957 | _T_1958; // @[Mux.scala 27:72]
|
|
wire _T_1915 = byp_fetch_index_inc_1 == 4'h2; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1959 = _T_1915 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1974 = _T_1973 | _T_1959; // @[Mux.scala 27:72]
|
|
wire _T_1918 = byp_fetch_index_inc_1 == 4'h3; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1960 = _T_1918 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1975 = _T_1974 | _T_1960; // @[Mux.scala 27:72]
|
|
wire _T_1921 = byp_fetch_index_inc_1 == 4'h4; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1961 = _T_1921 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1976 = _T_1975 | _T_1961; // @[Mux.scala 27:72]
|
|
wire _T_1924 = byp_fetch_index_inc_1 == 4'h5; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1962 = _T_1924 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1977 = _T_1976 | _T_1962; // @[Mux.scala 27:72]
|
|
wire _T_1927 = byp_fetch_index_inc_1 == 4'h6; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1963 = _T_1927 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1978 = _T_1977 | _T_1963; // @[Mux.scala 27:72]
|
|
wire _T_1930 = byp_fetch_index_inc_1 == 4'h7; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1964 = _T_1930 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1979 = _T_1978 | _T_1964; // @[Mux.scala 27:72]
|
|
wire _T_1933 = byp_fetch_index_inc_1 == 4'h8; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1965 = _T_1933 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1980 = _T_1979 | _T_1965; // @[Mux.scala 27:72]
|
|
wire _T_1936 = byp_fetch_index_inc_1 == 4'h9; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1966 = _T_1936 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_1981 = _T_1980 | _T_1966; // @[Mux.scala 27:72]
|
|
wire _T_1939 = byp_fetch_index_inc_1 == 4'ha; // @[ifu_mem_ctl.scala 348:73]
|
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wire [15:0] _T_1967 = _T_1939 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1982 = _T_1981 | _T_1967; // @[Mux.scala 27:72]
|
|
wire _T_1942 = byp_fetch_index_inc_1 == 4'hb; // @[ifu_mem_ctl.scala 348:73]
|
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wire [15:0] _T_1968 = _T_1942 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1983 = _T_1982 | _T_1968; // @[Mux.scala 27:72]
|
|
wire _T_1945 = byp_fetch_index_inc_1 == 4'hc; // @[ifu_mem_ctl.scala 348:73]
|
|
wire [15:0] _T_1969 = _T_1945 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1984 = _T_1983 | _T_1969; // @[Mux.scala 27:72]
|
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wire _T_1948 = byp_fetch_index_inc_1 == 4'hd; // @[ifu_mem_ctl.scala 348:73]
|
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wire [15:0] _T_1970 = _T_1948 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1985 = _T_1984 | _T_1970; // @[Mux.scala 27:72]
|
|
wire _T_1951 = byp_fetch_index_inc_1 == 4'he; // @[ifu_mem_ctl.scala 348:73]
|
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wire [15:0] _T_1971 = _T_1951 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1986 = _T_1985 | _T_1971; // @[Mux.scala 27:72]
|
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wire _T_1954 = byp_fetch_index_inc_1 == 4'hf; // @[ifu_mem_ctl.scala 348:73]
|
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wire [15:0] _T_1972 = _T_1954 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_1987 = _T_1986 | _T_1972; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2037 = _T_1667 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2038 = _T_1670 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2053 = _T_2037 | _T_2038; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2039 = _T_1673 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2054 = _T_2053 | _T_2039; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2040 = _T_1676 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2055 = _T_2054 | _T_2040; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2041 = _T_1679 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2056 = _T_2055 | _T_2041; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2042 = _T_1682 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2057 = _T_2056 | _T_2042; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2043 = _T_1685 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2058 = _T_2057 | _T_2043; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2044 = _T_1688 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2045 = _T_1691 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2046 = _T_1694 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2047 = _T_1697 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2048 = _T_1700 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2049 = _T_1703 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2050 = _T_1706 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2051 = _T_1709 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72]
|
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wire [31:0] _T_2052 = _T_1712 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72]
|
|
wire [79:0] _T_2150 = {_T_1987,_T_2067,_T_1825}; // @[Cat.scala 29:58]
|
|
wire [79:0] ic_byp_data_only_pre_new = _T_1666 ? _T_1908 : _T_2150; // @[ifu_mem_ctl.scala 346:37]
|
|
wire [79:0] _T_2155 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
|
|
wire [79:0] ic_byp_data_only_new = _T_2153 ? ic_byp_data_only_pre_new : _T_2155; // @[ifu_mem_ctl.scala 350:30]
|
|
wire [79:0] _GEN_517 = {{16'd0}, _T_1295}; // @[ifu_mem_ctl.scala 284:117]
|
|
wire [79:0] _T_1296 = _GEN_517 & ic_byp_data_only_new; // @[ifu_mem_ctl.scala 284:117]
|
|
wire [79:0] _GEN_518 = {{16'd0}, _T_1293}; // @[ifu_mem_ctl.scala 284:91]
|
|
wire [79:0] ic_premux_data_temp = _GEN_518 | _T_1296; // @[ifu_mem_ctl.scala 284:91]
|
|
wire fetch_req_f_qual = io_ic_hit_f & _T_339; // @[ifu_mem_ctl.scala 291:38]
|
|
wire [1:0] _T_1301 = ifc_region_acc_fault_final_f ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_1302 = _T_1301 | ifc_bus_acc_fault_f; // @[ifu_mem_ctl.scala 293:65]
|
|
wire [1:0] _T_1305 = _T_339 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_1307 = |io_iccm_rd_ecc_double_err; // @[ifu_mem_ctl.scala 294:62]
|
|
reg ifc_region_acc_fault_memory_f; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1309 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 294:108]
|
|
wire [1:0] _T_1310 = ifc_region_acc_fault_f ? 2'h2 : _T_1309; // @[ifu_mem_ctl.scala 294:75]
|
|
wire _T_1312 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[ifu_mem_ctl.scala 296:45]
|
|
wire _T_1314 = byp_fetch_index == 5'h1f; // @[ifu_mem_ctl.scala 296:80]
|
|
wire _T_1315 = ~_T_1314; // @[ifu_mem_ctl.scala 296:71]
|
|
wire _T_1316 = _T_1312 & _T_1315; // @[ifu_mem_ctl.scala 296:69]
|
|
wire _T_1317 = err_stop_state != 2'h2; // @[ifu_mem_ctl.scala 296:131]
|
|
wire _T_1318 = _T_1316 & _T_1317; // @[ifu_mem_ctl.scala 296:114]
|
|
wire [6:0] _T_1390 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58]
|
|
wire _T_1396 = ic_miss_buff_data_error[0] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire _T_2734 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 521:54]
|
|
wire _T_2735 = _T_2734 & _T_16; // @[ifu_mem_ctl.scala 521:57]
|
|
wire bus_ifu_wr_data_error = _T_2735 & miss_pending; // @[ifu_mem_ctl.scala 521:75]
|
|
wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1396; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1400 = ic_miss_buff_data_error[1] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1400; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1404 = ic_miss_buff_data_error[2] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1404; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1408 = ic_miss_buff_data_error[3] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1408; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1412 = ic_miss_buff_data_error[4] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1412; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1416 = ic_miss_buff_data_error[5] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1416; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1420 = ic_miss_buff_data_error[6] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1420; // @[ifu_mem_ctl.scala 313:72]
|
|
wire _T_1424 = ic_miss_buff_data_error[7] & _T_1362; // @[ifu_mem_ctl.scala 314:32]
|
|
wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1424; // @[ifu_mem_ctl.scala 313:72]
|
|
wire [6:0] _T_1430 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58]
|
|
wire _T_1553 = ic_crit_wd_rdy_new_in ^ ic_crit_wd_rdy_new_ff; // @[lib.scala 466:21]
|
|
wire _T_1554 = |_T_1553; // @[lib.scala 466:29]
|
|
reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20]
|
|
wire _T_2521 = 3'h0 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2529 = _T_9 & _T_339; // @[ifu_mem_ctl.scala 394:82]
|
|
wire _T_2530 = _T_2529 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 394:105]
|
|
wire _T_2532 = _T_2530 & _T_2653; // @[ifu_mem_ctl.scala 394:129]
|
|
wire _T_2533 = 3'h1 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2534 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 399:50]
|
|
wire _T_2536 = 3'h2 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2543 = 3'h4 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _T_2545 = 3'h3 == perr_state; // @[Conditional.scala 37:30]
|
|
wire _GEN_60 = _T_2543 | _T_2545; // @[Conditional.scala 39:67]
|
|
wire _GEN_62 = _T_2536 ? _T_2534 : _GEN_60; // @[Conditional.scala 39:67]
|
|
wire _GEN_64 = _T_2533 ? _T_2534 : _GEN_62; // @[Conditional.scala 39:67]
|
|
wire perr_state_en = _T_2521 ? _T_2532 : _GEN_64; // @[Conditional.scala 40:58]
|
|
wire perr_sb_write_status = _T_2521 & perr_state_en; // @[Conditional.scala 40:58]
|
|
wire _T_2535 = io_dec_tlu_flush_lower_wb & io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 400:56]
|
|
wire _GEN_65 = _T_2533 & _T_2535; // @[Conditional.scala 39:67]
|
|
wire perr_sel_invalidate = _T_2521 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58]
|
|
wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg dma_sb_err_state_ff; // @[Reg.scala 27:20]
|
|
wire _T_2516 = _T_10 ^ dma_sb_err_state_ff; // @[lib.scala 488:21]
|
|
wire _T_2517 = |_T_2516; // @[lib.scala 488:29]
|
|
wire _T_2519 = ~dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 385:49]
|
|
wire _T_2523 = io_dec_mem_ctrl_ifu_ic_error_start & _T_339; // @[ifu_mem_ctl.scala 393:104]
|
|
wire _T_2537 = ~io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 403:30]
|
|
wire _T_2538 = _T_2537 & io_dec_tlu_flush_lower_wb; // @[ifu_mem_ctl.scala 403:68]
|
|
wire _T_2539 = _T_2538 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 403:98]
|
|
wire _T_2548 = perr_state == 3'h2; // @[ifu_mem_ctl.scala 423:79]
|
|
wire _T_2549 = io_dec_mem_ctrl_dec_tlu_flush_err_wb & _T_2548; // @[ifu_mem_ctl.scala 423:65]
|
|
wire _T_2551 = _T_2549 & _T_2653; // @[ifu_mem_ctl.scala 423:94]
|
|
wire _T_2553 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 426:59]
|
|
wire _T_2554 = _T_2553 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 426:99]
|
|
wire _T_2568 = _T_2553 | io_ifu_fetch_val[0]; // @[ifu_mem_ctl.scala 429:94]
|
|
wire _T_2569 = _T_2568 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 429:116]
|
|
wire _T_2570 = _T_2569 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 429:139]
|
|
wire _T_2590 = _T_2568 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 436:116]
|
|
wire _T_2598 = io_dec_tlu_flush_lower_wb & _T_2537; // @[ifu_mem_ctl.scala 441:60]
|
|
wire _T_2599 = _T_2598 | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 441:101]
|
|
wire _T_2600 = _T_2599 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 441:141]
|
|
wire _GEN_72 = _T_2596 & _T_2554; // @[Conditional.scala 39:67]
|
|
wire _GEN_75 = _T_2579 ? _T_2590 : _GEN_72; // @[Conditional.scala 39:67]
|
|
wire _GEN_77 = _T_2579 | _T_2596; // @[Conditional.scala 39:67]
|
|
wire _GEN_79 = _T_2552 ? _T_2570 : _GEN_75; // @[Conditional.scala 39:67]
|
|
wire _GEN_81 = _T_2552 | _GEN_77; // @[Conditional.scala 39:67]
|
|
wire err_stop_state_en = _T_2547 ? _T_2551 : _GEN_79; // @[Conditional.scala 40:58]
|
|
wire _T_2608 = io_ifu_bus_clk_en ^ bus_ifu_bus_clk_en_ff; // @[lib.scala 488:21]
|
|
wire _T_2609 = |_T_2608; // @[lib.scala 488:29]
|
|
wire _T_2612 = scnd_miss_req_in ^ scnd_miss_req_q; // @[lib.scala 488:21]
|
|
wire _T_2613 = |_T_2612; // @[lib.scala 488:29]
|
|
reg bus_cmd_req_hold; // @[Reg.scala 27:20]
|
|
wire _T_2617 = ic_act_miss_f | bus_cmd_req_hold; // @[ifu_mem_ctl.scala 462:45]
|
|
reg ifu_bus_cmd_valid; // @[Reg.scala 27:20]
|
|
wire _T_2618 = _T_2617 | ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 462:64]
|
|
wire _T_2620 = _T_2618 & _T_2653; // @[ifu_mem_ctl.scala 462:85]
|
|
reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20]
|
|
wire _T_2622 = bus_cmd_beat_count == 3'h7; // @[ifu_mem_ctl.scala 462:146]
|
|
wire _T_2623 = _T_2622 & ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 462:177]
|
|
wire _T_2624 = _T_2623 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 462:197]
|
|
wire _T_2625 = _T_2624 & miss_pending; // @[ifu_mem_ctl.scala 462:219]
|
|
wire _T_2626 = ~_T_2625; // @[ifu_mem_ctl.scala 462:125]
|
|
wire ifc_bus_ic_req_ff_in = _T_2620 & _T_2626; // @[ifu_mem_ctl.scala 462:123]
|
|
wire _T_2627 = io_ifu_bus_clk_en | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 463:88]
|
|
wire ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 486:45]
|
|
wire _T_2647 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 490:39]
|
|
wire _T_2648 = _T_2647 & miss_pending; // @[ifu_mem_ctl.scala 490:57]
|
|
wire bus_cmd_sent = _T_2648 & _T_2653; // @[ifu_mem_ctl.scala 490:72]
|
|
wire _T_2630 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 465:61]
|
|
wire _T_2631 = _T_2617 & _T_2630; // @[ifu_mem_ctl.scala 465:59]
|
|
wire bus_cmd_req_in = _T_2631 & _T_2653; // @[ifu_mem_ctl.scala 465:75]
|
|
wire _T_2634 = bus_cmd_req_in ^ bus_cmd_req_hold; // @[lib.scala 488:21]
|
|
wire _T_2635 = |_T_2634; // @[lib.scala 488:29]
|
|
wire [2:0] _T_2639 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_2641 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2643 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
reg ifu_bus_arready_unq_ff; // @[Reg.scala 27:20]
|
|
reg ifu_bus_arvalid_ff; // @[Reg.scala 27:20]
|
|
wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 487:51]
|
|
wire [2:0] _T_2667 = bus_new_data_beat_count ^ bus_data_beat_count; // @[lib.scala 466:21]
|
|
wire _T_2668 = |_T_2667; // @[lib.scala 466:29]
|
|
wire _T_2671 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 498:73]
|
|
wire _T_2672 = _T_2654 & _T_2671; // @[ifu_mem_ctl.scala 498:71]
|
|
wire _T_2674 = last_data_recieved_ff & _T_1362; // @[ifu_mem_ctl.scala 498:114]
|
|
wire last_data_recieved_in = _T_2672 | _T_2674; // @[ifu_mem_ctl.scala 498:89]
|
|
wire _T_2676 = last_data_recieved_in ^ last_data_recieved_ff; // @[lib.scala 488:21]
|
|
wire _T_2677 = |_T_2676; // @[lib.scala 488:29]
|
|
wire [2:0] _T_2683 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 503:43]
|
|
wire _T_2689 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 506:48]
|
|
wire _T_2690 = _T_2689 & miss_pending; // @[ifu_mem_ctl.scala 506:70]
|
|
wire bus_inc_cmd_beat_cnt = _T_2690 & _T_2653; // @[ifu_mem_ctl.scala 506:85]
|
|
wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 508:57]
|
|
wire _T_2694 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 509:31]
|
|
wire _T_2695 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 509:71]
|
|
wire _T_2696 = _T_2695 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 509:87]
|
|
wire _T_2697 = ~_T_2696; // @[ifu_mem_ctl.scala 509:55]
|
|
wire bus_hold_cmd_beat_cnt = _T_2694 & _T_2697; // @[ifu_mem_ctl.scala 509:53]
|
|
wire _T_2698 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 510:46]
|
|
wire bus_cmd_beat_en = _T_2698 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 510:62]
|
|
wire [2:0] _T_2701 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 512:46]
|
|
wire [2:0] _T_2703 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2704 = bus_inc_cmd_beat_cnt ? _T_2701 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2705 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_2707 = _T_2703 | _T_2704; // @[Mux.scala 27:72]
|
|
wire [2:0] bus_new_cmd_beat_count = _T_2707 | _T_2705; // @[Mux.scala 27:72]
|
|
wire _T_2711 = _T_326 & bus_cmd_beat_en; // @[lib.scala 399:57]
|
|
wire _T_2727 = ic_act_miss_f ^ ic_act_miss_f_delayed; // @[lib.scala 488:21]
|
|
wire _T_2728 = |_T_2727; // @[lib.scala 488:29]
|
|
wire _T_2740 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 523:53]
|
|
wire _T_2741 = io_ifc_dma_access_ok & _T_2740; // @[ifu_mem_ctl.scala 523:50]
|
|
wire _T_2742 = ~io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 523:73]
|
|
wire ifc_dma_access_ok_d = _T_2741 & _T_2742; // @[ifu_mem_ctl.scala 523:71]
|
|
reg ifc_dma_access_ok_prev; // @[Reg.scala 27:20]
|
|
wire _T_2743 = ifc_dma_access_ok_d ^ ifc_dma_access_ok_prev; // @[lib.scala 488:21]
|
|
wire _T_2744 = |_T_2743; // @[lib.scala 488:29]
|
|
wire _T_2750 = _T_2741 & ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 530:63]
|
|
wire _T_2751 = perr_state == 3'h0; // @[ifu_mem_ctl.scala 530:102]
|
|
wire _T_2752 = _T_2750 & _T_2751; // @[ifu_mem_ctl.scala 530:88]
|
|
wire _T_2756 = io_dma_mem_ctl_dma_iccm_req ^ dma_iccm_req_f; // @[lib.scala 488:21]
|
|
wire _T_2757 = |_T_2756; // @[lib.scala 488:29]
|
|
wire _T_2759 = io_iccm_ready & io_dma_mem_ctl_dma_iccm_req; // @[ifu_mem_ctl.scala 532:34]
|
|
wire _T_2760 = _T_2759 & io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 532:64]
|
|
wire _T_2763 = ~io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 533:66]
|
|
wire _T_2764 = _T_2759 & _T_2763; // @[ifu_mem_ctl.scala 533:64]
|
|
wire _T_2765 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 533:122]
|
|
wire [2:0] _T_2770 = io_dma_mem_ctl_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_2791 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[33]; // @[lib.scala 125:74]
|
|
wire _T_2792 = _T_2791 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 125:74]
|
|
wire _T_2793 = _T_2792 ^ io_dma_mem_ctl_dma_mem_wdata[36]; // @[lib.scala 125:74]
|
|
wire _T_2794 = _T_2793 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 125:74]
|
|
wire _T_2795 = _T_2794 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 125:74]
|
|
wire _T_2796 = _T_2795 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 125:74]
|
|
wire _T_2797 = _T_2796 ^ io_dma_mem_ctl_dma_mem_wdata[43]; // @[lib.scala 125:74]
|
|
wire _T_2798 = _T_2797 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 125:74]
|
|
wire _T_2799 = _T_2798 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 125:74]
|
|
wire _T_2800 = _T_2799 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 125:74]
|
|
wire _T_2801 = _T_2800 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 125:74]
|
|
wire _T_2802 = _T_2801 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 125:74]
|
|
wire _T_2803 = _T_2802 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 125:74]
|
|
wire _T_2804 = _T_2803 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 125:74]
|
|
wire _T_2805 = _T_2804 ^ io_dma_mem_ctl_dma_mem_wdata[58]; // @[lib.scala 125:74]
|
|
wire _T_2806 = _T_2805 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 125:74]
|
|
wire _T_2807 = _T_2806 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 125:74]
|
|
wire _T_2826 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[lib.scala 125:74]
|
|
wire _T_2827 = _T_2826 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 125:74]
|
|
wire _T_2828 = _T_2827 ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[lib.scala 125:74]
|
|
wire _T_2829 = _T_2828 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 125:74]
|
|
wire _T_2830 = _T_2829 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 125:74]
|
|
wire _T_2831 = _T_2830 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 125:74]
|
|
wire _T_2832 = _T_2831 ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[lib.scala 125:74]
|
|
wire _T_2833 = _T_2832 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 125:74]
|
|
wire _T_2834 = _T_2833 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 125:74]
|
|
wire _T_2835 = _T_2834 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 125:74]
|
|
wire _T_2836 = _T_2835 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 125:74]
|
|
wire _T_2837 = _T_2836 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 125:74]
|
|
wire _T_2838 = _T_2837 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 125:74]
|
|
wire _T_2839 = _T_2838 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 125:74]
|
|
wire _T_2840 = _T_2839 ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[lib.scala 125:74]
|
|
wire _T_2841 = _T_2840 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 125:74]
|
|
wire _T_2842 = _T_2841 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 125:74]
|
|
wire _T_2861 = io_dma_mem_ctl_dma_mem_wdata[33] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[lib.scala 125:74]
|
|
wire _T_2862 = _T_2861 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 125:74]
|
|
wire _T_2863 = _T_2862 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[lib.scala 125:74]
|
|
wire _T_2864 = _T_2863 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 125:74]
|
|
wire _T_2865 = _T_2864 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 125:74]
|
|
wire _T_2866 = _T_2865 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 125:74]
|
|
wire _T_2867 = _T_2866 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[lib.scala 125:74]
|
|
wire _T_2868 = _T_2867 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 125:74]
|
|
wire _T_2869 = _T_2868 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 125:74]
|
|
wire _T_2870 = _T_2869 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 125:74]
|
|
wire _T_2871 = _T_2870 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 125:74]
|
|
wire _T_2872 = _T_2871 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 125:74]
|
|
wire _T_2873 = _T_2872 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 125:74]
|
|
wire _T_2874 = _T_2873 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 125:74]
|
|
wire _T_2875 = _T_2874 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[lib.scala 125:74]
|
|
wire _T_2876 = _T_2875 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 125:74]
|
|
wire _T_2877 = _T_2876 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 125:74]
|
|
wire _T_2893 = io_dma_mem_ctl_dma_mem_wdata[36] ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[lib.scala 125:74]
|
|
wire _T_2894 = _T_2893 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 125:74]
|
|
wire _T_2895 = _T_2894 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[lib.scala 125:74]
|
|
wire _T_2896 = _T_2895 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 125:74]
|
|
wire _T_2897 = _T_2896 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 125:74]
|
|
wire _T_2898 = _T_2897 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 125:74]
|
|
wire _T_2899 = _T_2898 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[lib.scala 125:74]
|
|
wire _T_2900 = _T_2899 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 125:74]
|
|
wire _T_2901 = _T_2900 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 125:74]
|
|
wire _T_2902 = _T_2901 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 125:74]
|
|
wire _T_2903 = _T_2902 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 125:74]
|
|
wire _T_2904 = _T_2903 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 125:74]
|
|
wire _T_2905 = _T_2904 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 125:74]
|
|
wire _T_2906 = _T_2905 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 125:74]
|
|
wire _T_2922 = io_dma_mem_ctl_dma_mem_wdata[43] ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[lib.scala 125:74]
|
|
wire _T_2923 = _T_2922 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 125:74]
|
|
wire _T_2924 = _T_2923 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[lib.scala 125:74]
|
|
wire _T_2925 = _T_2924 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 125:74]
|
|
wire _T_2926 = _T_2925 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 125:74]
|
|
wire _T_2927 = _T_2926 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 125:74]
|
|
wire _T_2928 = _T_2927 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[lib.scala 125:74]
|
|
wire _T_2929 = _T_2928 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 125:74]
|
|
wire _T_2930 = _T_2929 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 125:74]
|
|
wire _T_2931 = _T_2930 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 125:74]
|
|
wire _T_2932 = _T_2931 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 125:74]
|
|
wire _T_2933 = _T_2932 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 125:74]
|
|
wire _T_2934 = _T_2933 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 125:74]
|
|
wire _T_2935 = _T_2934 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 125:74]
|
|
wire _T_2942 = io_dma_mem_ctl_dma_mem_wdata[58] ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[lib.scala 125:74]
|
|
wire _T_2943 = _T_2942 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 125:74]
|
|
wire _T_2944 = _T_2943 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[lib.scala 125:74]
|
|
wire _T_2945 = _T_2944 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 125:74]
|
|
wire _T_2946 = _T_2945 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 125:74]
|
|
wire [5:0] _T_2951 = {_T_2946,_T_2935,_T_2906,_T_2877,_T_2842,_T_2807}; // @[Cat.scala 29:58]
|
|
wire _T_2952 = ^io_dma_mem_ctl_dma_mem_wdata[63:32]; // @[lib.scala 133:13]
|
|
wire _T_2953 = ^_T_2951; // @[lib.scala 133:23]
|
|
wire _T_2954 = _T_2952 ^ _T_2953; // @[lib.scala 133:18]
|
|
wire _T_2975 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[1]; // @[lib.scala 125:74]
|
|
wire _T_2976 = _T_2975 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 125:74]
|
|
wire _T_2977 = _T_2976 ^ io_dma_mem_ctl_dma_mem_wdata[4]; // @[lib.scala 125:74]
|
|
wire _T_2978 = _T_2977 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 125:74]
|
|
wire _T_2979 = _T_2978 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 125:74]
|
|
wire _T_2980 = _T_2979 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 125:74]
|
|
wire _T_2981 = _T_2980 ^ io_dma_mem_ctl_dma_mem_wdata[11]; // @[lib.scala 125:74]
|
|
wire _T_2982 = _T_2981 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 125:74]
|
|
wire _T_2983 = _T_2982 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 125:74]
|
|
wire _T_2984 = _T_2983 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 125:74]
|
|
wire _T_2985 = _T_2984 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 125:74]
|
|
wire _T_2986 = _T_2985 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 125:74]
|
|
wire _T_2987 = _T_2986 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 125:74]
|
|
wire _T_2988 = _T_2987 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 125:74]
|
|
wire _T_2989 = _T_2988 ^ io_dma_mem_ctl_dma_mem_wdata[26]; // @[lib.scala 125:74]
|
|
wire _T_2990 = _T_2989 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 125:74]
|
|
wire _T_2991 = _T_2990 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 125:74]
|
|
wire _T_3010 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[lib.scala 125:74]
|
|
wire _T_3011 = _T_3010 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 125:74]
|
|
wire _T_3012 = _T_3011 ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[lib.scala 125:74]
|
|
wire _T_3013 = _T_3012 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 125:74]
|
|
wire _T_3014 = _T_3013 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 125:74]
|
|
wire _T_3015 = _T_3014 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 125:74]
|
|
wire _T_3016 = _T_3015 ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[lib.scala 125:74]
|
|
wire _T_3017 = _T_3016 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 125:74]
|
|
wire _T_3018 = _T_3017 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 125:74]
|
|
wire _T_3019 = _T_3018 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 125:74]
|
|
wire _T_3020 = _T_3019 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 125:74]
|
|
wire _T_3021 = _T_3020 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 125:74]
|
|
wire _T_3022 = _T_3021 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 125:74]
|
|
wire _T_3023 = _T_3022 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 125:74]
|
|
wire _T_3024 = _T_3023 ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[lib.scala 125:74]
|
|
wire _T_3025 = _T_3024 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 125:74]
|
|
wire _T_3026 = _T_3025 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 125:74]
|
|
wire _T_3045 = io_dma_mem_ctl_dma_mem_wdata[1] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[lib.scala 125:74]
|
|
wire _T_3046 = _T_3045 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 125:74]
|
|
wire _T_3047 = _T_3046 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[lib.scala 125:74]
|
|
wire _T_3048 = _T_3047 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 125:74]
|
|
wire _T_3049 = _T_3048 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 125:74]
|
|
wire _T_3050 = _T_3049 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 125:74]
|
|
wire _T_3051 = _T_3050 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[lib.scala 125:74]
|
|
wire _T_3052 = _T_3051 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 125:74]
|
|
wire _T_3053 = _T_3052 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 125:74]
|
|
wire _T_3054 = _T_3053 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 125:74]
|
|
wire _T_3055 = _T_3054 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 125:74]
|
|
wire _T_3056 = _T_3055 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 125:74]
|
|
wire _T_3057 = _T_3056 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 125:74]
|
|
wire _T_3058 = _T_3057 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 125:74]
|
|
wire _T_3059 = _T_3058 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[lib.scala 125:74]
|
|
wire _T_3060 = _T_3059 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 125:74]
|
|
wire _T_3061 = _T_3060 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 125:74]
|
|
wire _T_3077 = io_dma_mem_ctl_dma_mem_wdata[4] ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[lib.scala 125:74]
|
|
wire _T_3078 = _T_3077 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 125:74]
|
|
wire _T_3079 = _T_3078 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[lib.scala 125:74]
|
|
wire _T_3080 = _T_3079 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 125:74]
|
|
wire _T_3081 = _T_3080 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 125:74]
|
|
wire _T_3082 = _T_3081 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 125:74]
|
|
wire _T_3083 = _T_3082 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[lib.scala 125:74]
|
|
wire _T_3084 = _T_3083 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 125:74]
|
|
wire _T_3085 = _T_3084 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 125:74]
|
|
wire _T_3086 = _T_3085 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 125:74]
|
|
wire _T_3087 = _T_3086 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 125:74]
|
|
wire _T_3088 = _T_3087 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 125:74]
|
|
wire _T_3089 = _T_3088 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 125:74]
|
|
wire _T_3090 = _T_3089 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 125:74]
|
|
wire _T_3106 = io_dma_mem_ctl_dma_mem_wdata[11] ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[lib.scala 125:74]
|
|
wire _T_3107 = _T_3106 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 125:74]
|
|
wire _T_3108 = _T_3107 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[lib.scala 125:74]
|
|
wire _T_3109 = _T_3108 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 125:74]
|
|
wire _T_3110 = _T_3109 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 125:74]
|
|
wire _T_3111 = _T_3110 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 125:74]
|
|
wire _T_3112 = _T_3111 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[lib.scala 125:74]
|
|
wire _T_3113 = _T_3112 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 125:74]
|
|
wire _T_3114 = _T_3113 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 125:74]
|
|
wire _T_3115 = _T_3114 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 125:74]
|
|
wire _T_3116 = _T_3115 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 125:74]
|
|
wire _T_3117 = _T_3116 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 125:74]
|
|
wire _T_3118 = _T_3117 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 125:74]
|
|
wire _T_3119 = _T_3118 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 125:74]
|
|
wire _T_3126 = io_dma_mem_ctl_dma_mem_wdata[26] ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[lib.scala 125:74]
|
|
wire _T_3127 = _T_3126 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 125:74]
|
|
wire _T_3128 = _T_3127 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[lib.scala 125:74]
|
|
wire _T_3129 = _T_3128 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 125:74]
|
|
wire _T_3130 = _T_3129 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 125:74]
|
|
wire [5:0] _T_3135 = {_T_3130,_T_3119,_T_3090,_T_3061,_T_3026,_T_2991}; // @[Cat.scala 29:58]
|
|
wire _T_3136 = ^io_dma_mem_ctl_dma_mem_wdata[31:0]; // @[lib.scala 133:13]
|
|
wire _T_3137 = ^_T_3135; // @[lib.scala 133:23]
|
|
wire _T_3138 = _T_3136 ^ _T_3137; // @[lib.scala 133:18]
|
|
wire [6:0] _T_3139 = {_T_3138,_T_3130,_T_3119,_T_3090,_T_3061,_T_3026,_T_2991}; // @[Cat.scala 29:58]
|
|
wire [13:0] dma_mem_ecc = {_T_2954,_T_2946,_T_2935,_T_2906,_T_2877,_T_2842,_T_2807,_T_3139}; // @[Cat.scala 29:58]
|
|
wire _T_3141 = ~_T_2759; // @[ifu_mem_ctl.scala 539:45]
|
|
wire _T_3142 = iccm_correct_ecc & _T_3141; // @[ifu_mem_ctl.scala 539:43]
|
|
reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20]
|
|
wire [77:0] _T_3143 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58]
|
|
wire [77:0] _T_3150 = {dma_mem_ecc[13:7],io_dma_mem_ctl_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_ctl_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58]
|
|
reg [1:0] dma_mem_addr_ff; // @[Reg.scala 27:20]
|
|
wire _T_3505 = _T_3417[5:0] == 6'h27; // @[lib.scala 205:41]
|
|
wire _T_3503 = _T_3417[5:0] == 6'h26; // @[lib.scala 205:41]
|
|
wire _T_3501 = _T_3417[5:0] == 6'h25; // @[lib.scala 205:41]
|
|
wire _T_3499 = _T_3417[5:0] == 6'h24; // @[lib.scala 205:41]
|
|
wire _T_3497 = _T_3417[5:0] == 6'h23; // @[lib.scala 205:41]
|
|
wire _T_3495 = _T_3417[5:0] == 6'h22; // @[lib.scala 205:41]
|
|
wire _T_3493 = _T_3417[5:0] == 6'h21; // @[lib.scala 205:41]
|
|
wire _T_3491 = _T_3417[5:0] == 6'h20; // @[lib.scala 205:41]
|
|
wire _T_3489 = _T_3417[5:0] == 6'h1f; // @[lib.scala 205:41]
|
|
wire _T_3487 = _T_3417[5:0] == 6'h1e; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3563 = {_T_3505,_T_3503,_T_3501,_T_3499,_T_3497,_T_3495,_T_3493,_T_3491,_T_3489,_T_3487}; // @[lib.scala 208:69]
|
|
wire _T_3485 = _T_3417[5:0] == 6'h1d; // @[lib.scala 205:41]
|
|
wire _T_3483 = _T_3417[5:0] == 6'h1c; // @[lib.scala 205:41]
|
|
wire _T_3481 = _T_3417[5:0] == 6'h1b; // @[lib.scala 205:41]
|
|
wire _T_3479 = _T_3417[5:0] == 6'h1a; // @[lib.scala 205:41]
|
|
wire _T_3477 = _T_3417[5:0] == 6'h19; // @[lib.scala 205:41]
|
|
wire _T_3475 = _T_3417[5:0] == 6'h18; // @[lib.scala 205:41]
|
|
wire _T_3473 = _T_3417[5:0] == 6'h17; // @[lib.scala 205:41]
|
|
wire _T_3471 = _T_3417[5:0] == 6'h16; // @[lib.scala 205:41]
|
|
wire _T_3469 = _T_3417[5:0] == 6'h15; // @[lib.scala 205:41]
|
|
wire _T_3467 = _T_3417[5:0] == 6'h14; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3554 = {_T_3485,_T_3483,_T_3481,_T_3479,_T_3477,_T_3475,_T_3473,_T_3471,_T_3469,_T_3467}; // @[lib.scala 208:69]
|
|
wire _T_3465 = _T_3417[5:0] == 6'h13; // @[lib.scala 205:41]
|
|
wire _T_3463 = _T_3417[5:0] == 6'h12; // @[lib.scala 205:41]
|
|
wire _T_3461 = _T_3417[5:0] == 6'h11; // @[lib.scala 205:41]
|
|
wire _T_3459 = _T_3417[5:0] == 6'h10; // @[lib.scala 205:41]
|
|
wire _T_3457 = _T_3417[5:0] == 6'hf; // @[lib.scala 205:41]
|
|
wire _T_3455 = _T_3417[5:0] == 6'he; // @[lib.scala 205:41]
|
|
wire _T_3453 = _T_3417[5:0] == 6'hd; // @[lib.scala 205:41]
|
|
wire _T_3451 = _T_3417[5:0] == 6'hc; // @[lib.scala 205:41]
|
|
wire _T_3449 = _T_3417[5:0] == 6'hb; // @[lib.scala 205:41]
|
|
wire _T_3447 = _T_3417[5:0] == 6'ha; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3544 = {_T_3465,_T_3463,_T_3461,_T_3459,_T_3457,_T_3455,_T_3453,_T_3451,_T_3449,_T_3447}; // @[lib.scala 208:69]
|
|
wire _T_3445 = _T_3417[5:0] == 6'h9; // @[lib.scala 205:41]
|
|
wire _T_3443 = _T_3417[5:0] == 6'h8; // @[lib.scala 205:41]
|
|
wire _T_3441 = _T_3417[5:0] == 6'h7; // @[lib.scala 205:41]
|
|
wire _T_3439 = _T_3417[5:0] == 6'h6; // @[lib.scala 205:41]
|
|
wire _T_3437 = _T_3417[5:0] == 6'h5; // @[lib.scala 205:41]
|
|
wire _T_3435 = _T_3417[5:0] == 6'h4; // @[lib.scala 205:41]
|
|
wire _T_3433 = _T_3417[5:0] == 6'h3; // @[lib.scala 205:41]
|
|
wire _T_3431 = _T_3417[5:0] == 6'h2; // @[lib.scala 205:41]
|
|
wire _T_3429 = _T_3417[5:0] == 6'h1; // @[lib.scala 205:41]
|
|
wire [18:0] _T_3545 = {_T_3544,_T_3445,_T_3443,_T_3441,_T_3439,_T_3437,_T_3435,_T_3433,_T_3431,_T_3429}; // @[lib.scala 208:69]
|
|
wire [38:0] _T_3565 = {_T_3563,_T_3554,_T_3545}; // @[lib.scala 208:69]
|
|
wire [7:0] _T_3520 = {io_iccm_rd_data_ecc[35],io_iccm_rd_data_ecc[3:1],io_iccm_rd_data_ecc[34],io_iccm_rd_data_ecc[0],io_iccm_rd_data_ecc[33:32]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3526 = {io_iccm_rd_data_ecc[38],io_iccm_rd_data_ecc[31:26],io_iccm_rd_data_ecc[37],io_iccm_rd_data_ecc[25:11],io_iccm_rd_data_ecc[36],io_iccm_rd_data_ecc[10:4],_T_3520}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3566 = _T_3565 ^ _T_3526; // @[lib.scala 208:76]
|
|
wire [38:0] _T_3567 = _T_3421 ? _T_3566 : _T_3526; // @[lib.scala 208:31]
|
|
wire [31:0] iccm_corrected_data_0 = {_T_3567[37:32],_T_3567[30:16],_T_3567[14:8],_T_3567[6:4],_T_3567[2]}; // @[Cat.scala 29:58]
|
|
wire _T_3890 = _T_3802[5:0] == 6'h27; // @[lib.scala 205:41]
|
|
wire _T_3888 = _T_3802[5:0] == 6'h26; // @[lib.scala 205:41]
|
|
wire _T_3886 = _T_3802[5:0] == 6'h25; // @[lib.scala 205:41]
|
|
wire _T_3884 = _T_3802[5:0] == 6'h24; // @[lib.scala 205:41]
|
|
wire _T_3882 = _T_3802[5:0] == 6'h23; // @[lib.scala 205:41]
|
|
wire _T_3880 = _T_3802[5:0] == 6'h22; // @[lib.scala 205:41]
|
|
wire _T_3878 = _T_3802[5:0] == 6'h21; // @[lib.scala 205:41]
|
|
wire _T_3876 = _T_3802[5:0] == 6'h20; // @[lib.scala 205:41]
|
|
wire _T_3874 = _T_3802[5:0] == 6'h1f; // @[lib.scala 205:41]
|
|
wire _T_3872 = _T_3802[5:0] == 6'h1e; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3948 = {_T_3890,_T_3888,_T_3886,_T_3884,_T_3882,_T_3880,_T_3878,_T_3876,_T_3874,_T_3872}; // @[lib.scala 208:69]
|
|
wire _T_3870 = _T_3802[5:0] == 6'h1d; // @[lib.scala 205:41]
|
|
wire _T_3868 = _T_3802[5:0] == 6'h1c; // @[lib.scala 205:41]
|
|
wire _T_3866 = _T_3802[5:0] == 6'h1b; // @[lib.scala 205:41]
|
|
wire _T_3864 = _T_3802[5:0] == 6'h1a; // @[lib.scala 205:41]
|
|
wire _T_3862 = _T_3802[5:0] == 6'h19; // @[lib.scala 205:41]
|
|
wire _T_3860 = _T_3802[5:0] == 6'h18; // @[lib.scala 205:41]
|
|
wire _T_3858 = _T_3802[5:0] == 6'h17; // @[lib.scala 205:41]
|
|
wire _T_3856 = _T_3802[5:0] == 6'h16; // @[lib.scala 205:41]
|
|
wire _T_3854 = _T_3802[5:0] == 6'h15; // @[lib.scala 205:41]
|
|
wire _T_3852 = _T_3802[5:0] == 6'h14; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3939 = {_T_3870,_T_3868,_T_3866,_T_3864,_T_3862,_T_3860,_T_3858,_T_3856,_T_3854,_T_3852}; // @[lib.scala 208:69]
|
|
wire _T_3850 = _T_3802[5:0] == 6'h13; // @[lib.scala 205:41]
|
|
wire _T_3848 = _T_3802[5:0] == 6'h12; // @[lib.scala 205:41]
|
|
wire _T_3846 = _T_3802[5:0] == 6'h11; // @[lib.scala 205:41]
|
|
wire _T_3844 = _T_3802[5:0] == 6'h10; // @[lib.scala 205:41]
|
|
wire _T_3842 = _T_3802[5:0] == 6'hf; // @[lib.scala 205:41]
|
|
wire _T_3840 = _T_3802[5:0] == 6'he; // @[lib.scala 205:41]
|
|
wire _T_3838 = _T_3802[5:0] == 6'hd; // @[lib.scala 205:41]
|
|
wire _T_3836 = _T_3802[5:0] == 6'hc; // @[lib.scala 205:41]
|
|
wire _T_3834 = _T_3802[5:0] == 6'hb; // @[lib.scala 205:41]
|
|
wire _T_3832 = _T_3802[5:0] == 6'ha; // @[lib.scala 205:41]
|
|
wire [9:0] _T_3929 = {_T_3850,_T_3848,_T_3846,_T_3844,_T_3842,_T_3840,_T_3838,_T_3836,_T_3834,_T_3832}; // @[lib.scala 208:69]
|
|
wire _T_3830 = _T_3802[5:0] == 6'h9; // @[lib.scala 205:41]
|
|
wire _T_3828 = _T_3802[5:0] == 6'h8; // @[lib.scala 205:41]
|
|
wire _T_3826 = _T_3802[5:0] == 6'h7; // @[lib.scala 205:41]
|
|
wire _T_3824 = _T_3802[5:0] == 6'h6; // @[lib.scala 205:41]
|
|
wire _T_3822 = _T_3802[5:0] == 6'h5; // @[lib.scala 205:41]
|
|
wire _T_3820 = _T_3802[5:0] == 6'h4; // @[lib.scala 205:41]
|
|
wire _T_3818 = _T_3802[5:0] == 6'h3; // @[lib.scala 205:41]
|
|
wire _T_3816 = _T_3802[5:0] == 6'h2; // @[lib.scala 205:41]
|
|
wire _T_3814 = _T_3802[5:0] == 6'h1; // @[lib.scala 205:41]
|
|
wire [18:0] _T_3930 = {_T_3929,_T_3830,_T_3828,_T_3826,_T_3824,_T_3822,_T_3820,_T_3818,_T_3816,_T_3814}; // @[lib.scala 208:69]
|
|
wire [38:0] _T_3950 = {_T_3948,_T_3939,_T_3930}; // @[lib.scala 208:69]
|
|
wire [7:0] _T_3905 = {io_iccm_rd_data_ecc[74],io_iccm_rd_data_ecc[42:40],io_iccm_rd_data_ecc[73],io_iccm_rd_data_ecc[39],io_iccm_rd_data_ecc[72:71]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3911 = {io_iccm_rd_data_ecc[77],io_iccm_rd_data_ecc[70:65],io_iccm_rd_data_ecc[76],io_iccm_rd_data_ecc[64:50],io_iccm_rd_data_ecc[75],io_iccm_rd_data_ecc[49:43],_T_3905}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_3951 = _T_3950 ^ _T_3911; // @[lib.scala 208:76]
|
|
wire [38:0] _T_3952 = _T_3806 ? _T_3951 : _T_3911; // @[lib.scala 208:31]
|
|
wire [31:0] iccm_corrected_data_1 = {_T_3952[37:32],_T_3952[30:16],_T_3952[14:8],_T_3952[6:4],_T_3952[2]}; // @[Cat.scala 29:58]
|
|
wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 543:35]
|
|
wire _T_3810 = ~_T_3802[6]; // @[lib.scala 201:55]
|
|
wire _T_3811 = _T_3804 & _T_3810; // @[lib.scala 201:53]
|
|
wire _T_3425 = ~_T_3417[6]; // @[lib.scala 201:55]
|
|
wire _T_3426 = _T_3419 & _T_3425; // @[lib.scala 201:53]
|
|
wire [1:0] iccm_double_ecc_error = {_T_3811,_T_3426}; // @[Cat.scala 29:58]
|
|
wire _T_3154 = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 545:53]
|
|
wire [63:0] _T_3155 = {io_dma_mem_ctl_dma_mem_addr,io_dma_mem_ctl_dma_mem_addr}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_3156 = {iccm_dma_rdata_1_muxed,_T_3567[37:32],_T_3567[30:16],_T_3567[14:8],_T_3567[6:4],_T_3567[2]}; // @[Cat.scala 29:58]
|
|
reg [2:0] dma_mem_tag_ff; // @[Reg.scala 27:20]
|
|
wire [2:0] _T_3157 = io_dma_mem_ctl_dma_mem_tag ^ dma_mem_tag_ff; // @[lib.scala 466:21]
|
|
wire _T_3158 = |_T_3157; // @[lib.scala 466:29]
|
|
reg [2:0] iccm_dma_rtag_temp; // @[Reg.scala 27:20]
|
|
wire [2:0] _T_3160 = dma_mem_tag_ff ^ iccm_dma_rtag_temp; // @[lib.scala 466:21]
|
|
wire _T_3161 = |_T_3160; // @[lib.scala 466:29]
|
|
wire [1:0] _T_3165 = io_dma_mem_ctl_dma_mem_addr[3:2] ^ dma_mem_addr_ff; // @[lib.scala 466:21]
|
|
wire _T_3166 = |_T_3165; // @[lib.scala 466:29]
|
|
wire _T_3168 = _T_2764 ^ iccm_dma_rvalid_in; // @[lib.scala 488:21]
|
|
wire _T_3169 = |_T_3168; // @[lib.scala 488:29]
|
|
reg iccm_dma_rvalid_temp; // @[Reg.scala 27:20]
|
|
wire _T_3171 = iccm_dma_rvalid_in ^ iccm_dma_rvalid_temp; // @[lib.scala 488:21]
|
|
wire _T_3172 = |_T_3171; // @[lib.scala 488:29]
|
|
reg iccm_dma_ecc_error; // @[Reg.scala 27:20]
|
|
wire _T_3175 = _T_3154 ^ iccm_dma_ecc_error; // @[lib.scala 488:21]
|
|
wire _T_3176 = |_T_3175; // @[lib.scala 488:29]
|
|
reg [63:0] iccm_dma_rdata_temp; // @[Reg.scala 27:20]
|
|
wire _T_3180 = _T_2759 & _T_2740; // @[ifu_mem_ctl.scala 558:71]
|
|
wire _T_3184 = _T_3141 & iccm_correct_ecc; // @[ifu_mem_ctl.scala 559:56]
|
|
reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20]
|
|
wire [14:0] _T_3185 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_3187 = _T_3184 ? _T_3185 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 559:8]
|
|
wire _T_3579 = _T_3417 == 7'h40; // @[lib.scala 211:62]
|
|
wire _T_3580 = _T_3567[38] ^ _T_3579; // @[lib.scala 211:44]
|
|
wire [6:0] iccm_corrected_ecc_0 = {_T_3580,_T_3567[31],_T_3567[15],_T_3567[7],_T_3567[3],_T_3567[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_3964 = _T_3802 == 7'h40; // @[lib.scala 211:62]
|
|
wire _T_3965 = _T_3952[38] ^ _T_3964; // @[lib.scala 211:44]
|
|
wire [6:0] iccm_corrected_ecc_1 = {_T_3965,_T_3952[31],_T_3952[15],_T_3952[7],_T_3952[3],_T_3952[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_3981 = _T_6 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 571:77]
|
|
wire [1:0] _T_3987 = {iccm_double_ecc_error[0],iccm_double_ecc_error[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_3989 = ifc_iccm_access_f ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_3990 = _T_3987 & _T_3989; // @[ifu_mem_ctl.scala 572:124]
|
|
wire [1:0] _T_3993 = {iccm_double_ecc_error[1],iccm_double_ecc_error[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_3996 = _T_3993 & _T_3989; // @[ifu_mem_ctl.scala 573:66]
|
|
wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 580:38]
|
|
wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[ifu_mem_ctl.scala 581:37]
|
|
reg iccm_rd_ecc_single_err_ff; // @[Reg.scala 27:20]
|
|
wire _T_4009 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 585:81]
|
|
wire iccm_rd_ecc_single_err_hold_in = _T_4009 & _T_339; // @[ifu_mem_ctl.scala 585:110]
|
|
wire _T_4002 = iccm_rd_ecc_single_err_hold_in ^ iccm_rd_ecc_single_err_ff; // @[lib.scala 488:21]
|
|
wire _T_4003 = |_T_4002; // @[lib.scala 488:29]
|
|
wire _T_4005 = ~iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 584:93]
|
|
wire _T_4006 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err & _T_4005; // @[ifu_mem_ctl.scala 584:91]
|
|
wire _T_4008 = _T_4006 & _T_339; // @[ifu_mem_ctl.scala 584:121]
|
|
wire iccm_ecc_write_status = _T_4008 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 584:144]
|
|
reg [13:0] iccm_rw_addr_f; // @[Reg.scala 27:20]
|
|
wire [13:0] _T_4015 = iccm_rw_addr_f + 14'h1; // @[ifu_mem_ctl.scala 588:102]
|
|
wire [13:0] _T_4018 = io_iccm_rw_addr[14:1] ^ iccm_rw_addr_f; // @[lib.scala 466:21]
|
|
wire _T_4019 = |_T_4018; // @[lib.scala 466:29]
|
|
wire [38:0] _T_4021 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58]
|
|
wire _T_4026 = ~io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 592:41]
|
|
wire _T_4027 = io_ifc_fetch_req_bf & _T_4026; // @[ifu_mem_ctl.scala 592:39]
|
|
wire _T_4029 = _T_4027 & _T_10655; // @[ifu_mem_ctl.scala 592:70]
|
|
wire _T_4031 = ~miss_state_en; // @[ifu_mem_ctl.scala 593:34]
|
|
wire _T_4032 = _T_2274 & _T_4031; // @[ifu_mem_ctl.scala 593:32]
|
|
wire _T_4035 = _T_2290 & _T_4031; // @[ifu_mem_ctl.scala 594:37]
|
|
wire _T_4036 = _T_4032 | _T_4035; // @[ifu_mem_ctl.scala 593:88]
|
|
wire _T_4037 = miss_state == 3'h7; // @[ifu_mem_ctl.scala 595:19]
|
|
wire _T_4039 = _T_4037 & _T_4031; // @[ifu_mem_ctl.scala 595:41]
|
|
wire _T_4040 = _T_4036 | _T_4039; // @[ifu_mem_ctl.scala 594:88]
|
|
wire _T_4043 = _T_1281 & _T_4031; // @[ifu_mem_ctl.scala 596:35]
|
|
wire _T_4044 = _T_4040 | _T_4043; // @[ifu_mem_ctl.scala 595:88]
|
|
wire _T_4047 = _T_2289 & _T_4031; // @[ifu_mem_ctl.scala 597:38]
|
|
wire _T_4048 = _T_4044 | _T_4047; // @[ifu_mem_ctl.scala 596:88]
|
|
wire _T_4050 = _T_2290 & miss_state_en; // @[ifu_mem_ctl.scala 598:37]
|
|
wire _T_4051 = miss_nxtstate == 3'h3; // @[ifu_mem_ctl.scala 598:71]
|
|
wire _T_4052 = _T_4050 & _T_4051; // @[ifu_mem_ctl.scala 598:54]
|
|
wire _T_4053 = _T_4048 | _T_4052; // @[ifu_mem_ctl.scala 597:57]
|
|
wire _T_4054 = ~_T_4053; // @[ifu_mem_ctl.scala 593:5]
|
|
wire _T_4055 = _T_4029 & _T_4054; // @[ifu_mem_ctl.scala 592:96]
|
|
wire _T_4056 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 599:26]
|
|
wire _T_4058 = _T_4056 & _T_4026; // @[ifu_mem_ctl.scala 599:48]
|
|
wire _T_4060 = _T_4058 & _T_10655; // @[ifu_mem_ctl.scala 599:79]
|
|
wire [1:0] _T_4063 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_10530 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 687:89]
|
|
wire bus_wren_1 = _T_10530 & miss_pending; // @[ifu_mem_ctl.scala 687:113]
|
|
wire _T_10529 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 687:89]
|
|
wire bus_wren_0 = _T_10529 & miss_pending; // @[ifu_mem_ctl.scala 687:113]
|
|
wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58]
|
|
wire _T_4069 = ~_T_111; // @[ifu_mem_ctl.scala 602:106]
|
|
wire _T_4070 = _T_2274 & _T_4069; // @[ifu_mem_ctl.scala 602:104]
|
|
wire _T_4071 = _T_2290 | _T_4070; // @[ifu_mem_ctl.scala 602:77]
|
|
wire _T_4075 = ~_T_54; // @[ifu_mem_ctl.scala 602:172]
|
|
wire _T_4076 = _T_4071 & _T_4075; // @[ifu_mem_ctl.scala 602:170]
|
|
wire _T_4077 = ~_T_4076; // @[ifu_mem_ctl.scala 602:44]
|
|
wire _T_4080 = io_dec_mem_ctrl_dec_tlu_fence_i_wb ^ reset_all_tags; // @[lib.scala 488:21]
|
|
wire _T_4081 = |_T_4080; // @[lib.scala 488:29]
|
|
wire _T_4084 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 605:62]
|
|
wire _T_4085 = ~_T_4084; // @[ifu_mem_ctl.scala 605:48]
|
|
wire _T_4086 = _T_282 & _T_4085; // @[ifu_mem_ctl.scala 605:46]
|
|
wire _T_4087 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 605:79]
|
|
wire ic_valid = _T_4086 & _T_4087; // @[ifu_mem_ctl.scala 605:77]
|
|
wire _T_4089 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 606:80]
|
|
wire [6:0] ifu_status_wr_addr_w_debug = _T_4089 ? io_ic_debug_addr[9:3] : ifu_status_wr_addr[11:5]; // @[ifu_mem_ctl.scala 606:39]
|
|
reg [6:0] ifu_status_wr_addr_ff; // @[Reg.scala 27:20]
|
|
wire [6:0] _T_4092 = ifu_status_wr_addr_w_debug ^ ifu_status_wr_addr_ff; // @[lib.scala 466:21]
|
|
wire _T_4093 = |_T_4092; // @[lib.scala 466:29]
|
|
wire _T_4095 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 611:72]
|
|
wire _T_10527 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 686:43]
|
|
wire way_status_wr_en = _T_10527 | ic_act_hit_f; // @[ifu_mem_ctl.scala 686:56]
|
|
wire way_status_wr_en_w_debug = way_status_wr_en | _T_4095; // @[ifu_mem_ctl.scala 611:51]
|
|
reg way_status_wr_en_ff; // @[Reg.scala 27:20]
|
|
wire _T_4096 = way_status_wr_en_w_debug ^ way_status_wr_en_ff; // @[lib.scala 488:21]
|
|
wire _T_4097 = |_T_4096; // @[lib.scala 488:29]
|
|
wire way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 682:39]
|
|
wire way_status_new = _T_10527 ? replace_way_mb_any_0 : way_status_hit_new; // @[ifu_mem_ctl.scala 685:24]
|
|
wire way_status_new_w_debug = _T_4095 ? io_ic_debug_wr_data[4] : way_status_new; // @[ifu_mem_ctl.scala 615:35]
|
|
reg way_status_new_ff; // @[Reg.scala 27:20]
|
|
wire _T_4101 = way_status_new_w_debug ^ way_status_new_ff; // @[lib.scala 466:21]
|
|
wire _T_4102 = |_T_4101; // @[lib.scala 466:29]
|
|
wire way_status_clken_0 = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_1 = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_2 = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_3 = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_4 = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_5 = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_6 = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_7 = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_8 = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_9 = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_10 = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_11 = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_12 = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_13 = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_14 = ifu_status_wr_addr_ff[6:3] == 4'he; // @[ifu_mem_ctl.scala 619:130]
|
|
wire way_status_clken_15 = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[ifu_mem_ctl.scala 619:130]
|
|
wire _T_4121 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4122 = _T_4121 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4123 = way_status_clken_0 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4126 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4127 = _T_4126 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4128 = way_status_clken_0 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4131 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4132 = _T_4131 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4133 = way_status_clken_0 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4136 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4137 = _T_4136 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4138 = way_status_clken_0 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4141 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4142 = _T_4141 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4143 = way_status_clken_0 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4146 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4147 = _T_4146 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4148 = way_status_clken_0 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4151 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4152 = _T_4151 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4153 = way_status_clken_0 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4156 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 623:93]
|
|
wire _T_4157 = _T_4156 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 623:101]
|
|
wire _T_4158 = way_status_clken_0 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4163 = way_status_clken_1 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4168 = way_status_clken_1 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4173 = way_status_clken_1 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4178 = way_status_clken_1 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4183 = way_status_clken_1 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4188 = way_status_clken_1 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4193 = way_status_clken_1 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4198 = way_status_clken_1 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4203 = way_status_clken_2 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4208 = way_status_clken_2 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4213 = way_status_clken_2 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4218 = way_status_clken_2 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4223 = way_status_clken_2 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4228 = way_status_clken_2 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4233 = way_status_clken_2 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4238 = way_status_clken_2 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4243 = way_status_clken_3 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4248 = way_status_clken_3 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4253 = way_status_clken_3 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4258 = way_status_clken_3 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4263 = way_status_clken_3 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4268 = way_status_clken_3 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4273 = way_status_clken_3 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4278 = way_status_clken_3 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4283 = way_status_clken_4 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4288 = way_status_clken_4 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4293 = way_status_clken_4 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4298 = way_status_clken_4 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4303 = way_status_clken_4 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4308 = way_status_clken_4 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4313 = way_status_clken_4 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4318 = way_status_clken_4 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4323 = way_status_clken_5 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4328 = way_status_clken_5 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4333 = way_status_clken_5 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4338 = way_status_clken_5 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4343 = way_status_clken_5 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4348 = way_status_clken_5 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4353 = way_status_clken_5 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4358 = way_status_clken_5 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4363 = way_status_clken_6 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4368 = way_status_clken_6 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4373 = way_status_clken_6 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4378 = way_status_clken_6 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4383 = way_status_clken_6 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4388 = way_status_clken_6 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4393 = way_status_clken_6 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4398 = way_status_clken_6 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4403 = way_status_clken_7 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4408 = way_status_clken_7 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4413 = way_status_clken_7 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4418 = way_status_clken_7 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4423 = way_status_clken_7 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4428 = way_status_clken_7 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4433 = way_status_clken_7 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4438 = way_status_clken_7 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4443 = way_status_clken_8 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4448 = way_status_clken_8 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4453 = way_status_clken_8 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4458 = way_status_clken_8 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4463 = way_status_clken_8 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4468 = way_status_clken_8 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4473 = way_status_clken_8 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4478 = way_status_clken_8 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4483 = way_status_clken_9 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4488 = way_status_clken_9 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4493 = way_status_clken_9 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4498 = way_status_clken_9 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4503 = way_status_clken_9 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4508 = way_status_clken_9 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4513 = way_status_clken_9 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4518 = way_status_clken_9 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4523 = way_status_clken_10 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4528 = way_status_clken_10 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4533 = way_status_clken_10 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4538 = way_status_clken_10 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4543 = way_status_clken_10 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4548 = way_status_clken_10 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4553 = way_status_clken_10 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4558 = way_status_clken_10 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4563 = way_status_clken_11 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4568 = way_status_clken_11 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4573 = way_status_clken_11 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4578 = way_status_clken_11 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4583 = way_status_clken_11 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4588 = way_status_clken_11 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4593 = way_status_clken_11 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4598 = way_status_clken_11 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4603 = way_status_clken_12 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4608 = way_status_clken_12 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4613 = way_status_clken_12 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4618 = way_status_clken_12 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4623 = way_status_clken_12 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4628 = way_status_clken_12 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4633 = way_status_clken_12 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4638 = way_status_clken_12 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4643 = way_status_clken_13 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4648 = way_status_clken_13 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4653 = way_status_clken_13 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4658 = way_status_clken_13 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4663 = way_status_clken_13 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4668 = way_status_clken_13 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4673 = way_status_clken_13 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4678 = way_status_clken_13 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4683 = way_status_clken_14 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4688 = way_status_clken_14 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4693 = way_status_clken_14 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4698 = way_status_clken_14 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4703 = way_status_clken_14 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4708 = way_status_clken_14 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4713 = way_status_clken_14 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4718 = way_status_clken_14 & _T_4157; // @[lib.scala 399:57]
|
|
wire _T_4723 = way_status_clken_15 & _T_4122; // @[lib.scala 399:57]
|
|
wire _T_4728 = way_status_clken_15 & _T_4127; // @[lib.scala 399:57]
|
|
wire _T_4733 = way_status_clken_15 & _T_4132; // @[lib.scala 399:57]
|
|
wire _T_4738 = way_status_clken_15 & _T_4137; // @[lib.scala 399:57]
|
|
wire _T_4743 = way_status_clken_15 & _T_4142; // @[lib.scala 399:57]
|
|
wire _T_4748 = way_status_clken_15 & _T_4147; // @[lib.scala 399:57]
|
|
wire _T_4753 = way_status_clken_15 & _T_4152; // @[lib.scala 399:57]
|
|
wire _T_4758 = way_status_clken_15 & _T_4157; // @[lib.scala 399:57]
|
|
wire [6:0] ifu_ic_rw_int_addr_w_debug = _T_4089 ? io_ic_debug_addr[9:3] : io_ic_rw_addr[11:5]; // @[ifu_mem_ctl.scala 629:39]
|
|
wire [6:0] _T_5289 = ifu_ic_rw_int_addr_w_debug ^ ifu_ic_rw_int_addr_ff; // @[lib.scala 466:21]
|
|
wire _T_5290 = |_T_5289; // @[lib.scala 466:29]
|
|
wire _T_10533 = _T_103 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 689:82]
|
|
wire _T_10534 = _T_10533 & miss_pending; // @[ifu_mem_ctl.scala 689:106]
|
|
wire bus_wren_last_1 = _T_10534 & bus_last_data_beat; // @[ifu_mem_ctl.scala 689:121]
|
|
wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 690:82]
|
|
wire _T_10536 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 691:71]
|
|
wire _T_10531 = _T_103 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 689:82]
|
|
wire _T_10532 = _T_10531 & miss_pending; // @[ifu_mem_ctl.scala 689:106]
|
|
wire bus_wren_last_0 = _T_10532 & bus_last_data_beat; // @[ifu_mem_ctl.scala 689:121]
|
|
wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 690:82]
|
|
wire _T_10535 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 691:71]
|
|
wire [1:0] ifu_tag_wren = {_T_10536,_T_10535}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_10587 = _T_4095 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] ic_debug_tag_wr_en = _T_10587 & io_ic_debug_way; // @[ifu_mem_ctl.scala 720:90]
|
|
wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[ifu_mem_ctl.scala 637:43]
|
|
reg [1:0] ifu_tag_wren_ff; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_5292 = ifu_tag_wren_w_debug ^ ifu_tag_wren_ff; // @[lib.scala 466:21]
|
|
wire _T_5293 = |_T_5292; // @[lib.scala 466:29]
|
|
wire ic_valid_w_debug = _T_4095 ? io_ic_debug_wr_data[0] : ic_valid; // @[ifu_mem_ctl.scala 640:29]
|
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reg ic_valid_ff; // @[Reg.scala 27:20]
|
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wire _T_5297 = ic_valid_w_debug ^ ic_valid_ff; // @[lib.scala 488:21]
|
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wire _T_5298 = |_T_5297; // @[lib.scala 488:29]
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wire _T_5301 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 645:76]
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wire _T_5303 = _T_5301 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5305 = perr_ic_index_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 646:68]
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wire _T_5307 = _T_5305 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5308 = _T_5303 | _T_5307; // @[ifu_mem_ctl.scala 645:107]
|
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wire _T_5309 = _T_5308 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
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wire _T_5313 = _T_5301 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5317 = _T_5305 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 646:77]
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wire _T_5318 = _T_5313 | _T_5317; // @[ifu_mem_ctl.scala 645:107]
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wire _T_5319 = _T_5318 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
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wire [1:0] tag_valid_clken_0 = {_T_5319,_T_5309}; // @[Cat.scala 29:58]
|
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wire _T_5321 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 645:76]
|
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wire _T_5323 = _T_5321 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5325 = perr_ic_index_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 646:68]
|
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wire _T_5327 = _T_5325 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5328 = _T_5323 | _T_5327; // @[ifu_mem_ctl.scala 645:107]
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wire _T_5329 = _T_5328 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
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wire _T_5333 = _T_5321 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5337 = _T_5325 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5338 = _T_5333 | _T_5337; // @[ifu_mem_ctl.scala 645:107]
|
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wire _T_5339 = _T_5338 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
|
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wire [1:0] tag_valid_clken_1 = {_T_5339,_T_5329}; // @[Cat.scala 29:58]
|
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wire _T_5341 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 645:76]
|
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wire _T_5343 = _T_5341 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5345 = perr_ic_index_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 646:68]
|
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wire _T_5347 = _T_5345 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 646:77]
|
|
wire _T_5348 = _T_5343 | _T_5347; // @[ifu_mem_ctl.scala 645:107]
|
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wire _T_5349 = _T_5348 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
|
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wire _T_5353 = _T_5341 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5357 = _T_5345 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5358 = _T_5353 | _T_5357; // @[ifu_mem_ctl.scala 645:107]
|
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wire _T_5359 = _T_5358 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
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wire [1:0] tag_valid_clken_2 = {_T_5359,_T_5349}; // @[Cat.scala 29:58]
|
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wire _T_5361 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 645:76]
|
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wire _T_5363 = _T_5361 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5365 = perr_ic_index_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 646:68]
|
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wire _T_5367 = _T_5365 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5368 = _T_5363 | _T_5367; // @[ifu_mem_ctl.scala 645:107]
|
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wire _T_5369 = _T_5368 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
|
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wire _T_5373 = _T_5361 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 645:85]
|
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wire _T_5377 = _T_5365 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 646:77]
|
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wire _T_5378 = _T_5373 | _T_5377; // @[ifu_mem_ctl.scala 645:107]
|
|
wire _T_5379 = _T_5378 | reset_all_tags; // @[ifu_mem_ctl.scala 646:100]
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|
wire [1:0] tag_valid_clken_3 = {_T_5379,_T_5369}; // @[Cat.scala 29:58]
|
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wire _T_5390 = ic_valid_ff & _T_198; // @[ifu_mem_ctl.scala 654:66]
|
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wire _T_5391 = ~perr_sel_invalidate; // @[ifu_mem_ctl.scala 654:93]
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wire _T_5392 = _T_5390 & _T_5391; // @[ifu_mem_ctl.scala 654:91]
|
|
wire _T_5395 = _T_4900 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5396 = perr_ic_index_ff == 7'h0; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5398 = _T_5396 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_5399 = _T_5395 | _T_5398; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5400 = _T_5399 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5403 = tag_valid_clken_0[0] & _T_5400; // @[lib.scala 399:57]
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wire _T_5412 = _T_4901 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5413 = perr_ic_index_ff == 7'h1; // @[ifu_mem_ctl.scala 654:204]
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wire _T_5415 = _T_5413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_5416 = _T_5412 | _T_5415; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5417 = _T_5416 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
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wire _T_5420 = tag_valid_clken_0[0] & _T_5417; // @[lib.scala 399:57]
|
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wire _T_5429 = _T_4902 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5430 = perr_ic_index_ff == 7'h2; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5432 = _T_5430 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5433 = _T_5429 | _T_5432; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5434 = _T_5433 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5437 = tag_valid_clken_0[0] & _T_5434; // @[lib.scala 399:57]
|
|
wire _T_5446 = _T_4903 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5447 = perr_ic_index_ff == 7'h3; // @[ifu_mem_ctl.scala 654:204]
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wire _T_5449 = _T_5447 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5450 = _T_5446 | _T_5449; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5451 = _T_5450 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
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wire _T_5454 = tag_valid_clken_0[0] & _T_5451; // @[lib.scala 399:57]
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wire _T_5463 = _T_4904 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5464 = perr_ic_index_ff == 7'h4; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5466 = _T_5464 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_5467 = _T_5463 | _T_5466; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5468 = _T_5467 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_5471 = tag_valid_clken_0[0] & _T_5468; // @[lib.scala 399:57]
|
|
wire _T_5480 = _T_4905 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5481 = perr_ic_index_ff == 7'h5; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5483 = _T_5481 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_5484 = _T_5480 | _T_5483; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5485 = _T_5484 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5488 = tag_valid_clken_0[0] & _T_5485; // @[lib.scala 399:57]
|
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wire _T_5497 = _T_4906 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5498 = perr_ic_index_ff == 7'h6; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5500 = _T_5498 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_5501 = _T_5497 | _T_5500; // @[ifu_mem_ctl.scala 654:183]
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wire _T_5502 = _T_5501 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_5505 = tag_valid_clken_0[0] & _T_5502; // @[lib.scala 399:57]
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wire _T_5514 = _T_4907 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5515 = perr_ic_index_ff == 7'h7; // @[ifu_mem_ctl.scala 654:204]
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wire _T_5517 = _T_5515 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_5518 = _T_5514 | _T_5517; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5519 = _T_5518 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_5522 = tag_valid_clken_0[0] & _T_5519; // @[lib.scala 399:57]
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wire _T_5531 = _T_4908 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_5532 = perr_ic_index_ff == 7'h8; // @[ifu_mem_ctl.scala 654:204]
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wire _T_5534 = _T_5532 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_5535 = _T_5531 | _T_5534; // @[ifu_mem_ctl.scala 654:183]
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wire _T_5536 = _T_5535 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
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wire _T_5539 = tag_valid_clken_0[0] & _T_5536; // @[lib.scala 399:57]
|
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wire _T_5548 = _T_4909 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5549 = perr_ic_index_ff == 7'h9; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5551 = _T_5549 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_5552 = _T_5548 | _T_5551; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5553 = _T_5552 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
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wire _T_5556 = tag_valid_clken_0[0] & _T_5553; // @[lib.scala 399:57]
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wire _T_5565 = _T_4910 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
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wire _T_5566 = perr_ic_index_ff == 7'ha; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_5568 = _T_5566 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5569 = _T_5565 | _T_5568; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_5570 = _T_5569 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
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wire _T_5573 = tag_valid_clken_0[0] & _T_5570; // @[lib.scala 399:57]
|
|
wire _T_5582 = _T_4911 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5583 = perr_ic_index_ff == 7'hb; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5585 = _T_5583 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_5586 = _T_5582 | _T_5585; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5587 = _T_5586 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5590 = tag_valid_clken_0[0] & _T_5587; // @[lib.scala 399:57]
|
|
wire _T_5599 = _T_4912 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5600 = perr_ic_index_ff == 7'hc; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5602 = _T_5600 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5603 = _T_5599 | _T_5602; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5604 = _T_5603 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5607 = tag_valid_clken_0[0] & _T_5604; // @[lib.scala 399:57]
|
|
wire _T_5616 = _T_4913 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5617 = perr_ic_index_ff == 7'hd; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5619 = _T_5617 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5620 = _T_5616 | _T_5619; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5621 = _T_5620 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5624 = tag_valid_clken_0[0] & _T_5621; // @[lib.scala 399:57]
|
|
wire _T_5633 = _T_4914 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5634 = perr_ic_index_ff == 7'he; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5636 = _T_5634 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5637 = _T_5633 | _T_5636; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5638 = _T_5637 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5641 = tag_valid_clken_0[0] & _T_5638; // @[lib.scala 399:57]
|
|
wire _T_5650 = _T_4915 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5651 = perr_ic_index_ff == 7'hf; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5653 = _T_5651 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5654 = _T_5650 | _T_5653; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5655 = _T_5654 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5658 = tag_valid_clken_0[0] & _T_5655; // @[lib.scala 399:57]
|
|
wire _T_5667 = _T_4916 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5668 = perr_ic_index_ff == 7'h10; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5670 = _T_5668 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5671 = _T_5667 | _T_5670; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5672 = _T_5671 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5675 = tag_valid_clken_0[0] & _T_5672; // @[lib.scala 399:57]
|
|
wire _T_5684 = _T_4917 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5685 = perr_ic_index_ff == 7'h11; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5687 = _T_5685 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5688 = _T_5684 | _T_5687; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5689 = _T_5688 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5692 = tag_valid_clken_0[0] & _T_5689; // @[lib.scala 399:57]
|
|
wire _T_5701 = _T_4918 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5702 = perr_ic_index_ff == 7'h12; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5704 = _T_5702 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5705 = _T_5701 | _T_5704; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5706 = _T_5705 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5709 = tag_valid_clken_0[0] & _T_5706; // @[lib.scala 399:57]
|
|
wire _T_5718 = _T_4919 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5719 = perr_ic_index_ff == 7'h13; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5721 = _T_5719 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5722 = _T_5718 | _T_5721; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5723 = _T_5722 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5726 = tag_valid_clken_0[0] & _T_5723; // @[lib.scala 399:57]
|
|
wire _T_5735 = _T_4920 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5736 = perr_ic_index_ff == 7'h14; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5738 = _T_5736 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5739 = _T_5735 | _T_5738; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5740 = _T_5739 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5743 = tag_valid_clken_0[0] & _T_5740; // @[lib.scala 399:57]
|
|
wire _T_5752 = _T_4921 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5753 = perr_ic_index_ff == 7'h15; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5755 = _T_5753 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5756 = _T_5752 | _T_5755; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5757 = _T_5756 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5760 = tag_valid_clken_0[0] & _T_5757; // @[lib.scala 399:57]
|
|
wire _T_5769 = _T_4922 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5770 = perr_ic_index_ff == 7'h16; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5772 = _T_5770 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5773 = _T_5769 | _T_5772; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5774 = _T_5773 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5777 = tag_valid_clken_0[0] & _T_5774; // @[lib.scala 399:57]
|
|
wire _T_5786 = _T_4923 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5787 = perr_ic_index_ff == 7'h17; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5789 = _T_5787 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5790 = _T_5786 | _T_5789; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5791 = _T_5790 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5794 = tag_valid_clken_0[0] & _T_5791; // @[lib.scala 399:57]
|
|
wire _T_5803 = _T_4924 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5804 = perr_ic_index_ff == 7'h18; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5806 = _T_5804 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5807 = _T_5803 | _T_5806; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5808 = _T_5807 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5811 = tag_valid_clken_0[0] & _T_5808; // @[lib.scala 399:57]
|
|
wire _T_5820 = _T_4925 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5821 = perr_ic_index_ff == 7'h19; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5823 = _T_5821 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5824 = _T_5820 | _T_5823; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5825 = _T_5824 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5828 = tag_valid_clken_0[0] & _T_5825; // @[lib.scala 399:57]
|
|
wire _T_5837 = _T_4926 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5838 = perr_ic_index_ff == 7'h1a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5840 = _T_5838 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5841 = _T_5837 | _T_5840; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5842 = _T_5841 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5845 = tag_valid_clken_0[0] & _T_5842; // @[lib.scala 399:57]
|
|
wire _T_5854 = _T_4927 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5855 = perr_ic_index_ff == 7'h1b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5857 = _T_5855 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5858 = _T_5854 | _T_5857; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5859 = _T_5858 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5862 = tag_valid_clken_0[0] & _T_5859; // @[lib.scala 399:57]
|
|
wire _T_5871 = _T_4928 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5872 = perr_ic_index_ff == 7'h1c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5874 = _T_5872 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5875 = _T_5871 | _T_5874; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5876 = _T_5875 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5879 = tag_valid_clken_0[0] & _T_5876; // @[lib.scala 399:57]
|
|
wire _T_5888 = _T_4929 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5889 = perr_ic_index_ff == 7'h1d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5891 = _T_5889 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5892 = _T_5888 | _T_5891; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5893 = _T_5892 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5896 = tag_valid_clken_0[0] & _T_5893; // @[lib.scala 399:57]
|
|
wire _T_5905 = _T_4930 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5906 = perr_ic_index_ff == 7'h1e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5908 = _T_5906 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5909 = _T_5905 | _T_5908; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5910 = _T_5909 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5913 = tag_valid_clken_0[0] & _T_5910; // @[lib.scala 399:57]
|
|
wire _T_5922 = _T_4931 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5923 = perr_ic_index_ff == 7'h1f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_5925 = _T_5923 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5926 = _T_5922 | _T_5925; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5927 = _T_5926 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5930 = tag_valid_clken_0[0] & _T_5927; // @[lib.scala 399:57]
|
|
wire _T_5939 = _T_4900 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5942 = _T_5396 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5943 = _T_5939 | _T_5942; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5944 = _T_5943 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5947 = tag_valid_clken_0[1] & _T_5944; // @[lib.scala 399:57]
|
|
wire _T_5956 = _T_4901 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5959 = _T_5413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5960 = _T_5956 | _T_5959; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5961 = _T_5960 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5964 = tag_valid_clken_0[1] & _T_5961; // @[lib.scala 399:57]
|
|
wire _T_5973 = _T_4902 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5976 = _T_5430 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5977 = _T_5973 | _T_5976; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5978 = _T_5977 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5981 = tag_valid_clken_0[1] & _T_5978; // @[lib.scala 399:57]
|
|
wire _T_5990 = _T_4903 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_5993 = _T_5447 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_5994 = _T_5990 | _T_5993; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_5995 = _T_5994 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_5998 = tag_valid_clken_0[1] & _T_5995; // @[lib.scala 399:57]
|
|
wire _T_6007 = _T_4904 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6010 = _T_5464 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6011 = _T_6007 | _T_6010; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6012 = _T_6011 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6015 = tag_valid_clken_0[1] & _T_6012; // @[lib.scala 399:57]
|
|
wire _T_6024 = _T_4905 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6027 = _T_5481 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6028 = _T_6024 | _T_6027; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6029 = _T_6028 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6032 = tag_valid_clken_0[1] & _T_6029; // @[lib.scala 399:57]
|
|
wire _T_6041 = _T_4906 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6044 = _T_5498 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6045 = _T_6041 | _T_6044; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6046 = _T_6045 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6049 = tag_valid_clken_0[1] & _T_6046; // @[lib.scala 399:57]
|
|
wire _T_6058 = _T_4907 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6061 = _T_5515 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6062 = _T_6058 | _T_6061; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6063 = _T_6062 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6066 = tag_valid_clken_0[1] & _T_6063; // @[lib.scala 399:57]
|
|
wire _T_6075 = _T_4908 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6078 = _T_5532 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6079 = _T_6075 | _T_6078; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6080 = _T_6079 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6083 = tag_valid_clken_0[1] & _T_6080; // @[lib.scala 399:57]
|
|
wire _T_6092 = _T_4909 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6095 = _T_5549 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6096 = _T_6092 | _T_6095; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6097 = _T_6096 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6100 = tag_valid_clken_0[1] & _T_6097; // @[lib.scala 399:57]
|
|
wire _T_6109 = _T_4910 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6112 = _T_5566 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6113 = _T_6109 | _T_6112; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6114 = _T_6113 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6117 = tag_valid_clken_0[1] & _T_6114; // @[lib.scala 399:57]
|
|
wire _T_6126 = _T_4911 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6129 = _T_5583 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6130 = _T_6126 | _T_6129; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6131 = _T_6130 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6134 = tag_valid_clken_0[1] & _T_6131; // @[lib.scala 399:57]
|
|
wire _T_6143 = _T_4912 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6146 = _T_5600 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6147 = _T_6143 | _T_6146; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6148 = _T_6147 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6151 = tag_valid_clken_0[1] & _T_6148; // @[lib.scala 399:57]
|
|
wire _T_6160 = _T_4913 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6163 = _T_5617 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6164 = _T_6160 | _T_6163; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6165 = _T_6164 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6168 = tag_valid_clken_0[1] & _T_6165; // @[lib.scala 399:57]
|
|
wire _T_6177 = _T_4914 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6180 = _T_5634 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6181 = _T_6177 | _T_6180; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6182 = _T_6181 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6185 = tag_valid_clken_0[1] & _T_6182; // @[lib.scala 399:57]
|
|
wire _T_6194 = _T_4915 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6197 = _T_5651 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6198 = _T_6194 | _T_6197; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6199 = _T_6198 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6202 = tag_valid_clken_0[1] & _T_6199; // @[lib.scala 399:57]
|
|
wire _T_6211 = _T_4916 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6214 = _T_5668 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6215 = _T_6211 | _T_6214; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6216 = _T_6215 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6219 = tag_valid_clken_0[1] & _T_6216; // @[lib.scala 399:57]
|
|
wire _T_6228 = _T_4917 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6231 = _T_5685 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6232 = _T_6228 | _T_6231; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6233 = _T_6232 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6236 = tag_valid_clken_0[1] & _T_6233; // @[lib.scala 399:57]
|
|
wire _T_6245 = _T_4918 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6248 = _T_5702 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6249 = _T_6245 | _T_6248; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6250 = _T_6249 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6253 = tag_valid_clken_0[1] & _T_6250; // @[lib.scala 399:57]
|
|
wire _T_6262 = _T_4919 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6265 = _T_5719 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6266 = _T_6262 | _T_6265; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6267 = _T_6266 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6270 = tag_valid_clken_0[1] & _T_6267; // @[lib.scala 399:57]
|
|
wire _T_6279 = _T_4920 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6282 = _T_5736 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6283 = _T_6279 | _T_6282; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6284 = _T_6283 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6287 = tag_valid_clken_0[1] & _T_6284; // @[lib.scala 399:57]
|
|
wire _T_6296 = _T_4921 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6299 = _T_5753 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6300 = _T_6296 | _T_6299; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6301 = _T_6300 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6304 = tag_valid_clken_0[1] & _T_6301; // @[lib.scala 399:57]
|
|
wire _T_6313 = _T_4922 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6316 = _T_5770 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6317 = _T_6313 | _T_6316; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6318 = _T_6317 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6321 = tag_valid_clken_0[1] & _T_6318; // @[lib.scala 399:57]
|
|
wire _T_6330 = _T_4923 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6333 = _T_5787 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6334 = _T_6330 | _T_6333; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6335 = _T_6334 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6338 = tag_valid_clken_0[1] & _T_6335; // @[lib.scala 399:57]
|
|
wire _T_6347 = _T_4924 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6350 = _T_5804 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6351 = _T_6347 | _T_6350; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6352 = _T_6351 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6355 = tag_valid_clken_0[1] & _T_6352; // @[lib.scala 399:57]
|
|
wire _T_6364 = _T_4925 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6367 = _T_5821 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6368 = _T_6364 | _T_6367; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6369 = _T_6368 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6372 = tag_valid_clken_0[1] & _T_6369; // @[lib.scala 399:57]
|
|
wire _T_6381 = _T_4926 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6384 = _T_5838 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6385 = _T_6381 | _T_6384; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6386 = _T_6385 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6389 = tag_valid_clken_0[1] & _T_6386; // @[lib.scala 399:57]
|
|
wire _T_6398 = _T_4927 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6401 = _T_5855 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6402 = _T_6398 | _T_6401; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6403 = _T_6402 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6406 = tag_valid_clken_0[1] & _T_6403; // @[lib.scala 399:57]
|
|
wire _T_6415 = _T_4928 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6418 = _T_5872 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6419 = _T_6415 | _T_6418; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6420 = _T_6419 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6423 = tag_valid_clken_0[1] & _T_6420; // @[lib.scala 399:57]
|
|
wire _T_6432 = _T_4929 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6435 = _T_5889 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6436 = _T_6432 | _T_6435; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6437 = _T_6436 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6440 = tag_valid_clken_0[1] & _T_6437; // @[lib.scala 399:57]
|
|
wire _T_6449 = _T_4930 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6452 = _T_5906 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6453 = _T_6449 | _T_6452; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6454 = _T_6453 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6457 = tag_valid_clken_0[1] & _T_6454; // @[lib.scala 399:57]
|
|
wire _T_6466 = _T_4931 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6469 = _T_5923 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6470 = _T_6466 | _T_6469; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6471 = _T_6470 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6474 = tag_valid_clken_0[1] & _T_6471; // @[lib.scala 399:57]
|
|
wire _T_6483 = _T_4932 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6484 = perr_ic_index_ff == 7'h20; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6486 = _T_6484 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6487 = _T_6483 | _T_6486; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6488 = _T_6487 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6491 = tag_valid_clken_1[0] & _T_6488; // @[lib.scala 399:57]
|
|
wire _T_6500 = _T_4933 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6501 = perr_ic_index_ff == 7'h21; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6503 = _T_6501 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6504 = _T_6500 | _T_6503; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6505 = _T_6504 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6508 = tag_valid_clken_1[0] & _T_6505; // @[lib.scala 399:57]
|
|
wire _T_6517 = _T_4934 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6518 = perr_ic_index_ff == 7'h22; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6520 = _T_6518 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6521 = _T_6517 | _T_6520; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6522 = _T_6521 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6525 = tag_valid_clken_1[0] & _T_6522; // @[lib.scala 399:57]
|
|
wire _T_6534 = _T_4935 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6535 = perr_ic_index_ff == 7'h23; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6537 = _T_6535 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6538 = _T_6534 | _T_6537; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6539 = _T_6538 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6542 = tag_valid_clken_1[0] & _T_6539; // @[lib.scala 399:57]
|
|
wire _T_6551 = _T_4936 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6552 = perr_ic_index_ff == 7'h24; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6554 = _T_6552 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6555 = _T_6551 | _T_6554; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6556 = _T_6555 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6559 = tag_valid_clken_1[0] & _T_6556; // @[lib.scala 399:57]
|
|
wire _T_6568 = _T_4937 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6569 = perr_ic_index_ff == 7'h25; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6571 = _T_6569 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6572 = _T_6568 | _T_6571; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6573 = _T_6572 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6576 = tag_valid_clken_1[0] & _T_6573; // @[lib.scala 399:57]
|
|
wire _T_6585 = _T_4938 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6586 = perr_ic_index_ff == 7'h26; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6588 = _T_6586 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6589 = _T_6585 | _T_6588; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6590 = _T_6589 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6593 = tag_valid_clken_1[0] & _T_6590; // @[lib.scala 399:57]
|
|
wire _T_6602 = _T_4939 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6603 = perr_ic_index_ff == 7'h27; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6605 = _T_6603 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6606 = _T_6602 | _T_6605; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6607 = _T_6606 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6610 = tag_valid_clken_1[0] & _T_6607; // @[lib.scala 399:57]
|
|
wire _T_6619 = _T_4940 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6620 = perr_ic_index_ff == 7'h28; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6622 = _T_6620 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6623 = _T_6619 | _T_6622; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6624 = _T_6623 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6627 = tag_valid_clken_1[0] & _T_6624; // @[lib.scala 399:57]
|
|
wire _T_6636 = _T_4941 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6637 = perr_ic_index_ff == 7'h29; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6639 = _T_6637 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6640 = _T_6636 | _T_6639; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6641 = _T_6640 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6644 = tag_valid_clken_1[0] & _T_6641; // @[lib.scala 399:57]
|
|
wire _T_6653 = _T_4942 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6654 = perr_ic_index_ff == 7'h2a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6656 = _T_6654 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6657 = _T_6653 | _T_6656; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6658 = _T_6657 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6661 = tag_valid_clken_1[0] & _T_6658; // @[lib.scala 399:57]
|
|
wire _T_6670 = _T_4943 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6671 = perr_ic_index_ff == 7'h2b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6673 = _T_6671 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6674 = _T_6670 | _T_6673; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6675 = _T_6674 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6678 = tag_valid_clken_1[0] & _T_6675; // @[lib.scala 399:57]
|
|
wire _T_6687 = _T_4944 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6688 = perr_ic_index_ff == 7'h2c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6690 = _T_6688 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6691 = _T_6687 | _T_6690; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6692 = _T_6691 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6695 = tag_valid_clken_1[0] & _T_6692; // @[lib.scala 399:57]
|
|
wire _T_6704 = _T_4945 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6705 = perr_ic_index_ff == 7'h2d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6707 = _T_6705 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6708 = _T_6704 | _T_6707; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6709 = _T_6708 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6712 = tag_valid_clken_1[0] & _T_6709; // @[lib.scala 399:57]
|
|
wire _T_6721 = _T_4946 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6722 = perr_ic_index_ff == 7'h2e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6724 = _T_6722 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6725 = _T_6721 | _T_6724; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6726 = _T_6725 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6729 = tag_valid_clken_1[0] & _T_6726; // @[lib.scala 399:57]
|
|
wire _T_6738 = _T_4947 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6739 = perr_ic_index_ff == 7'h2f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6741 = _T_6739 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6742 = _T_6738 | _T_6741; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6743 = _T_6742 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6746 = tag_valid_clken_1[0] & _T_6743; // @[lib.scala 399:57]
|
|
wire _T_6755 = _T_4948 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6756 = perr_ic_index_ff == 7'h30; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6758 = _T_6756 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6759 = _T_6755 | _T_6758; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6760 = _T_6759 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6763 = tag_valid_clken_1[0] & _T_6760; // @[lib.scala 399:57]
|
|
wire _T_6772 = _T_4949 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6773 = perr_ic_index_ff == 7'h31; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6775 = _T_6773 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6776 = _T_6772 | _T_6775; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6777 = _T_6776 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6780 = tag_valid_clken_1[0] & _T_6777; // @[lib.scala 399:57]
|
|
wire _T_6789 = _T_4950 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6790 = perr_ic_index_ff == 7'h32; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6792 = _T_6790 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6793 = _T_6789 | _T_6792; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6794 = _T_6793 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6797 = tag_valid_clken_1[0] & _T_6794; // @[lib.scala 399:57]
|
|
wire _T_6806 = _T_4951 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6807 = perr_ic_index_ff == 7'h33; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6809 = _T_6807 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6810 = _T_6806 | _T_6809; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6811 = _T_6810 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6814 = tag_valid_clken_1[0] & _T_6811; // @[lib.scala 399:57]
|
|
wire _T_6823 = _T_4952 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6824 = perr_ic_index_ff == 7'h34; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6826 = _T_6824 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6827 = _T_6823 | _T_6826; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6828 = _T_6827 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6831 = tag_valid_clken_1[0] & _T_6828; // @[lib.scala 399:57]
|
|
wire _T_6840 = _T_4953 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6841 = perr_ic_index_ff == 7'h35; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6843 = _T_6841 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6844 = _T_6840 | _T_6843; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6845 = _T_6844 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6848 = tag_valid_clken_1[0] & _T_6845; // @[lib.scala 399:57]
|
|
wire _T_6857 = _T_4954 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6858 = perr_ic_index_ff == 7'h36; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6860 = _T_6858 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6861 = _T_6857 | _T_6860; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6862 = _T_6861 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6865 = tag_valid_clken_1[0] & _T_6862; // @[lib.scala 399:57]
|
|
wire _T_6874 = _T_4955 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6875 = perr_ic_index_ff == 7'h37; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6877 = _T_6875 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6878 = _T_6874 | _T_6877; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6879 = _T_6878 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6882 = tag_valid_clken_1[0] & _T_6879; // @[lib.scala 399:57]
|
|
wire _T_6891 = _T_4956 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6892 = perr_ic_index_ff == 7'h38; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6894 = _T_6892 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6895 = _T_6891 | _T_6894; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6896 = _T_6895 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6899 = tag_valid_clken_1[0] & _T_6896; // @[lib.scala 399:57]
|
|
wire _T_6908 = _T_4957 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6909 = perr_ic_index_ff == 7'h39; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6911 = _T_6909 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6912 = _T_6908 | _T_6911; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6913 = _T_6912 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6916 = tag_valid_clken_1[0] & _T_6913; // @[lib.scala 399:57]
|
|
wire _T_6925 = _T_4958 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6926 = perr_ic_index_ff == 7'h3a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6928 = _T_6926 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6929 = _T_6925 | _T_6928; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6930 = _T_6929 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6933 = tag_valid_clken_1[0] & _T_6930; // @[lib.scala 399:57]
|
|
wire _T_6942 = _T_4959 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6943 = perr_ic_index_ff == 7'h3b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6945 = _T_6943 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6946 = _T_6942 | _T_6945; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6947 = _T_6946 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6950 = tag_valid_clken_1[0] & _T_6947; // @[lib.scala 399:57]
|
|
wire _T_6959 = _T_4960 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6960 = perr_ic_index_ff == 7'h3c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6962 = _T_6960 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6963 = _T_6959 | _T_6962; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6964 = _T_6963 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6967 = tag_valid_clken_1[0] & _T_6964; // @[lib.scala 399:57]
|
|
wire _T_6976 = _T_4961 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6977 = perr_ic_index_ff == 7'h3d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6979 = _T_6977 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6980 = _T_6976 | _T_6979; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6981 = _T_6980 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_6984 = tag_valid_clken_1[0] & _T_6981; // @[lib.scala 399:57]
|
|
wire _T_6993 = _T_4962 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_6994 = perr_ic_index_ff == 7'h3e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_6996 = _T_6994 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_6997 = _T_6993 | _T_6996; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_6998 = _T_6997 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7001 = tag_valid_clken_1[0] & _T_6998; // @[lib.scala 399:57]
|
|
wire _T_7010 = _T_4963 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7011 = perr_ic_index_ff == 7'h3f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7013 = _T_7011 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7014 = _T_7010 | _T_7013; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7015 = _T_7014 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7018 = tag_valid_clken_1[0] & _T_7015; // @[lib.scala 399:57]
|
|
wire _T_7027 = _T_4932 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7030 = _T_6484 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7031 = _T_7027 | _T_7030; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7032 = _T_7031 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7035 = tag_valid_clken_1[1] & _T_7032; // @[lib.scala 399:57]
|
|
wire _T_7044 = _T_4933 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7047 = _T_6501 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7048 = _T_7044 | _T_7047; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7049 = _T_7048 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7052 = tag_valid_clken_1[1] & _T_7049; // @[lib.scala 399:57]
|
|
wire _T_7061 = _T_4934 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7064 = _T_6518 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7065 = _T_7061 | _T_7064; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7066 = _T_7065 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7069 = tag_valid_clken_1[1] & _T_7066; // @[lib.scala 399:57]
|
|
wire _T_7078 = _T_4935 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7081 = _T_6535 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7082 = _T_7078 | _T_7081; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7083 = _T_7082 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7086 = tag_valid_clken_1[1] & _T_7083; // @[lib.scala 399:57]
|
|
wire _T_7095 = _T_4936 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7098 = _T_6552 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7099 = _T_7095 | _T_7098; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7100 = _T_7099 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7103 = tag_valid_clken_1[1] & _T_7100; // @[lib.scala 399:57]
|
|
wire _T_7112 = _T_4937 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7115 = _T_6569 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7116 = _T_7112 | _T_7115; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7117 = _T_7116 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7120 = tag_valid_clken_1[1] & _T_7117; // @[lib.scala 399:57]
|
|
wire _T_7129 = _T_4938 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7132 = _T_6586 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7133 = _T_7129 | _T_7132; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7134 = _T_7133 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7137 = tag_valid_clken_1[1] & _T_7134; // @[lib.scala 399:57]
|
|
wire _T_7146 = _T_4939 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7149 = _T_6603 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7150 = _T_7146 | _T_7149; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7151 = _T_7150 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7154 = tag_valid_clken_1[1] & _T_7151; // @[lib.scala 399:57]
|
|
wire _T_7163 = _T_4940 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7166 = _T_6620 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7167 = _T_7163 | _T_7166; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7168 = _T_7167 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7171 = tag_valid_clken_1[1] & _T_7168; // @[lib.scala 399:57]
|
|
wire _T_7180 = _T_4941 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7183 = _T_6637 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7184 = _T_7180 | _T_7183; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7185 = _T_7184 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7188 = tag_valid_clken_1[1] & _T_7185; // @[lib.scala 399:57]
|
|
wire _T_7197 = _T_4942 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7200 = _T_6654 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7201 = _T_7197 | _T_7200; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7202 = _T_7201 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7205 = tag_valid_clken_1[1] & _T_7202; // @[lib.scala 399:57]
|
|
wire _T_7214 = _T_4943 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7217 = _T_6671 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7218 = _T_7214 | _T_7217; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7219 = _T_7218 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7222 = tag_valid_clken_1[1] & _T_7219; // @[lib.scala 399:57]
|
|
wire _T_7231 = _T_4944 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7234 = _T_6688 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7235 = _T_7231 | _T_7234; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7236 = _T_7235 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7239 = tag_valid_clken_1[1] & _T_7236; // @[lib.scala 399:57]
|
|
wire _T_7248 = _T_4945 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7251 = _T_6705 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7252 = _T_7248 | _T_7251; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7253 = _T_7252 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7256 = tag_valid_clken_1[1] & _T_7253; // @[lib.scala 399:57]
|
|
wire _T_7265 = _T_4946 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7268 = _T_6722 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7269 = _T_7265 | _T_7268; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7270 = _T_7269 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7273 = tag_valid_clken_1[1] & _T_7270; // @[lib.scala 399:57]
|
|
wire _T_7282 = _T_4947 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7285 = _T_6739 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7286 = _T_7282 | _T_7285; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7287 = _T_7286 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7290 = tag_valid_clken_1[1] & _T_7287; // @[lib.scala 399:57]
|
|
wire _T_7299 = _T_4948 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7302 = _T_6756 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7303 = _T_7299 | _T_7302; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7304 = _T_7303 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7307 = tag_valid_clken_1[1] & _T_7304; // @[lib.scala 399:57]
|
|
wire _T_7316 = _T_4949 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7319 = _T_6773 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7320 = _T_7316 | _T_7319; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7321 = _T_7320 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7324 = tag_valid_clken_1[1] & _T_7321; // @[lib.scala 399:57]
|
|
wire _T_7333 = _T_4950 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7336 = _T_6790 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7337 = _T_7333 | _T_7336; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7338 = _T_7337 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7341 = tag_valid_clken_1[1] & _T_7338; // @[lib.scala 399:57]
|
|
wire _T_7350 = _T_4951 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7353 = _T_6807 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7354 = _T_7350 | _T_7353; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7355 = _T_7354 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7358 = tag_valid_clken_1[1] & _T_7355; // @[lib.scala 399:57]
|
|
wire _T_7367 = _T_4952 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7370 = _T_6824 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7371 = _T_7367 | _T_7370; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7372 = _T_7371 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7375 = tag_valid_clken_1[1] & _T_7372; // @[lib.scala 399:57]
|
|
wire _T_7384 = _T_4953 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7387 = _T_6841 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7388 = _T_7384 | _T_7387; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7389 = _T_7388 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7392 = tag_valid_clken_1[1] & _T_7389; // @[lib.scala 399:57]
|
|
wire _T_7401 = _T_4954 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7404 = _T_6858 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7405 = _T_7401 | _T_7404; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7406 = _T_7405 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7409 = tag_valid_clken_1[1] & _T_7406; // @[lib.scala 399:57]
|
|
wire _T_7418 = _T_4955 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7421 = _T_6875 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7422 = _T_7418 | _T_7421; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7423 = _T_7422 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7426 = tag_valid_clken_1[1] & _T_7423; // @[lib.scala 399:57]
|
|
wire _T_7435 = _T_4956 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7438 = _T_6892 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7439 = _T_7435 | _T_7438; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7440 = _T_7439 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7443 = tag_valid_clken_1[1] & _T_7440; // @[lib.scala 399:57]
|
|
wire _T_7452 = _T_4957 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7455 = _T_6909 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7456 = _T_7452 | _T_7455; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_7457 = _T_7456 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_7460 = tag_valid_clken_1[1] & _T_7457; // @[lib.scala 399:57]
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wire _T_7469 = _T_4958 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_7472 = _T_6926 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
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wire _T_7473 = _T_7469 | _T_7472; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7474 = _T_7473 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_7477 = tag_valid_clken_1[1] & _T_7474; // @[lib.scala 399:57]
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wire _T_7486 = _T_4959 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7489 = _T_6943 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7490 = _T_7486 | _T_7489; // @[ifu_mem_ctl.scala 654:183]
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|
wire _T_7491 = _T_7490 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_7494 = tag_valid_clken_1[1] & _T_7491; // @[lib.scala 399:57]
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wire _T_7503 = _T_4960 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_7506 = _T_6960 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_7507 = _T_7503 | _T_7506; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7508 = _T_7507 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_7511 = tag_valid_clken_1[1] & _T_7508; // @[lib.scala 399:57]
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wire _T_7520 = _T_4961 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_7523 = _T_6977 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
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wire _T_7524 = _T_7520 | _T_7523; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7525 = _T_7524 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7528 = tag_valid_clken_1[1] & _T_7525; // @[lib.scala 399:57]
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|
wire _T_7537 = _T_4962 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_7540 = _T_6994 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7541 = _T_7537 | _T_7540; // @[ifu_mem_ctl.scala 654:183]
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|
wire _T_7542 = _T_7541 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7545 = tag_valid_clken_1[1] & _T_7542; // @[lib.scala 399:57]
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|
wire _T_7554 = _T_4963 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
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|
wire _T_7557 = _T_7011 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7558 = _T_7554 | _T_7557; // @[ifu_mem_ctl.scala 654:183]
|
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wire _T_7559 = _T_7558 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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wire _T_7562 = tag_valid_clken_1[1] & _T_7559; // @[lib.scala 399:57]
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wire _T_7571 = _T_4964 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
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|
wire _T_7572 = perr_ic_index_ff == 7'h40; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7574 = _T_7572 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7575 = _T_7571 | _T_7574; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7576 = _T_7575 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7579 = tag_valid_clken_2[0] & _T_7576; // @[lib.scala 399:57]
|
|
wire _T_7588 = _T_4965 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7589 = perr_ic_index_ff == 7'h41; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7591 = _T_7589 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7592 = _T_7588 | _T_7591; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7593 = _T_7592 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7596 = tag_valid_clken_2[0] & _T_7593; // @[lib.scala 399:57]
|
|
wire _T_7605 = _T_4966 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7606 = perr_ic_index_ff == 7'h42; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7608 = _T_7606 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7609 = _T_7605 | _T_7608; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7610 = _T_7609 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7613 = tag_valid_clken_2[0] & _T_7610; // @[lib.scala 399:57]
|
|
wire _T_7622 = _T_4967 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7623 = perr_ic_index_ff == 7'h43; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7625 = _T_7623 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7626 = _T_7622 | _T_7625; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7627 = _T_7626 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7630 = tag_valid_clken_2[0] & _T_7627; // @[lib.scala 399:57]
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|
wire _T_7639 = _T_4968 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7640 = perr_ic_index_ff == 7'h44; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7642 = _T_7640 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7643 = _T_7639 | _T_7642; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7644 = _T_7643 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7647 = tag_valid_clken_2[0] & _T_7644; // @[lib.scala 399:57]
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|
wire _T_7656 = _T_4969 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7657 = perr_ic_index_ff == 7'h45; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7659 = _T_7657 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7660 = _T_7656 | _T_7659; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7661 = _T_7660 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7664 = tag_valid_clken_2[0] & _T_7661; // @[lib.scala 399:57]
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wire _T_7673 = _T_4970 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
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wire _T_7674 = perr_ic_index_ff == 7'h46; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7676 = _T_7674 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7677 = _T_7673 | _T_7676; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7678 = _T_7677 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7681 = tag_valid_clken_2[0] & _T_7678; // @[lib.scala 399:57]
|
|
wire _T_7690 = _T_4971 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7691 = perr_ic_index_ff == 7'h47; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7693 = _T_7691 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
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|
wire _T_7694 = _T_7690 | _T_7693; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7695 = _T_7694 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7698 = tag_valid_clken_2[0] & _T_7695; // @[lib.scala 399:57]
|
|
wire _T_7707 = _T_4972 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7708 = perr_ic_index_ff == 7'h48; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7710 = _T_7708 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7711 = _T_7707 | _T_7710; // @[ifu_mem_ctl.scala 654:183]
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|
wire _T_7712 = _T_7711 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7715 = tag_valid_clken_2[0] & _T_7712; // @[lib.scala 399:57]
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wire _T_7724 = _T_4973 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7725 = perr_ic_index_ff == 7'h49; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7727 = _T_7725 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7728 = _T_7724 | _T_7727; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7729 = _T_7728 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
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|
wire _T_7732 = tag_valid_clken_2[0] & _T_7729; // @[lib.scala 399:57]
|
|
wire _T_7741 = _T_4974 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7742 = perr_ic_index_ff == 7'h4a; // @[ifu_mem_ctl.scala 654:204]
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wire _T_7744 = _T_7742 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7745 = _T_7741 | _T_7744; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7746 = _T_7745 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7749 = tag_valid_clken_2[0] & _T_7746; // @[lib.scala 399:57]
|
|
wire _T_7758 = _T_4975 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7759 = perr_ic_index_ff == 7'h4b; // @[ifu_mem_ctl.scala 654:204]
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|
wire _T_7761 = _T_7759 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7762 = _T_7758 | _T_7761; // @[ifu_mem_ctl.scala 654:183]
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wire _T_7763 = _T_7762 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7766 = tag_valid_clken_2[0] & _T_7763; // @[lib.scala 399:57]
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|
wire _T_7775 = _T_4976 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7776 = perr_ic_index_ff == 7'h4c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7778 = _T_7776 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7779 = _T_7775 | _T_7778; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7780 = _T_7779 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7783 = tag_valid_clken_2[0] & _T_7780; // @[lib.scala 399:57]
|
|
wire _T_7792 = _T_4977 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7793 = perr_ic_index_ff == 7'h4d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7795 = _T_7793 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7796 = _T_7792 | _T_7795; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7797 = _T_7796 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7800 = tag_valid_clken_2[0] & _T_7797; // @[lib.scala 399:57]
|
|
wire _T_7809 = _T_4978 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7810 = perr_ic_index_ff == 7'h4e; // @[ifu_mem_ctl.scala 654:204]
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wire _T_7812 = _T_7810 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7813 = _T_7809 | _T_7812; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7814 = _T_7813 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7817 = tag_valid_clken_2[0] & _T_7814; // @[lib.scala 399:57]
|
|
wire _T_7826 = _T_4979 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7827 = perr_ic_index_ff == 7'h4f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7829 = _T_7827 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7830 = _T_7826 | _T_7829; // @[ifu_mem_ctl.scala 654:183]
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|
wire _T_7831 = _T_7830 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7834 = tag_valid_clken_2[0] & _T_7831; // @[lib.scala 399:57]
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|
wire _T_7843 = _T_4980 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7844 = perr_ic_index_ff == 7'h50; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7846 = _T_7844 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7847 = _T_7843 | _T_7846; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7848 = _T_7847 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7851 = tag_valid_clken_2[0] & _T_7848; // @[lib.scala 399:57]
|
|
wire _T_7860 = _T_4981 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7861 = perr_ic_index_ff == 7'h51; // @[ifu_mem_ctl.scala 654:204]
|
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wire _T_7863 = _T_7861 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7864 = _T_7860 | _T_7863; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7865 = _T_7864 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7868 = tag_valid_clken_2[0] & _T_7865; // @[lib.scala 399:57]
|
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wire _T_7877 = _T_4982 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7878 = perr_ic_index_ff == 7'h52; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7880 = _T_7878 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7881 = _T_7877 | _T_7880; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7882 = _T_7881 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7885 = tag_valid_clken_2[0] & _T_7882; // @[lib.scala 399:57]
|
|
wire _T_7894 = _T_4983 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7895 = perr_ic_index_ff == 7'h53; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7897 = _T_7895 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7898 = _T_7894 | _T_7897; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7899 = _T_7898 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7902 = tag_valid_clken_2[0] & _T_7899; // @[lib.scala 399:57]
|
|
wire _T_7911 = _T_4984 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7912 = perr_ic_index_ff == 7'h54; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7914 = _T_7912 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7915 = _T_7911 | _T_7914; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7916 = _T_7915 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7919 = tag_valid_clken_2[0] & _T_7916; // @[lib.scala 399:57]
|
|
wire _T_7928 = _T_4985 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7929 = perr_ic_index_ff == 7'h55; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7931 = _T_7929 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7932 = _T_7928 | _T_7931; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7933 = _T_7932 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7936 = tag_valid_clken_2[0] & _T_7933; // @[lib.scala 399:57]
|
|
wire _T_7945 = _T_4986 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7946 = perr_ic_index_ff == 7'h56; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7948 = _T_7946 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7949 = _T_7945 | _T_7948; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7950 = _T_7949 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7953 = tag_valid_clken_2[0] & _T_7950; // @[lib.scala 399:57]
|
|
wire _T_7962 = _T_4987 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7963 = perr_ic_index_ff == 7'h57; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7965 = _T_7963 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7966 = _T_7962 | _T_7965; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7967 = _T_7966 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7970 = tag_valid_clken_2[0] & _T_7967; // @[lib.scala 399:57]
|
|
wire _T_7979 = _T_4988 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7980 = perr_ic_index_ff == 7'h58; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7982 = _T_7980 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_7983 = _T_7979 | _T_7982; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_7984 = _T_7983 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_7987 = tag_valid_clken_2[0] & _T_7984; // @[lib.scala 399:57]
|
|
wire _T_7996 = _T_4989 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_7997 = perr_ic_index_ff == 7'h59; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_7999 = _T_7997 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8000 = _T_7996 | _T_7999; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8001 = _T_8000 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8004 = tag_valid_clken_2[0] & _T_8001; // @[lib.scala 399:57]
|
|
wire _T_8013 = _T_4990 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8014 = perr_ic_index_ff == 7'h5a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8016 = _T_8014 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8017 = _T_8013 | _T_8016; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8018 = _T_8017 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8021 = tag_valid_clken_2[0] & _T_8018; // @[lib.scala 399:57]
|
|
wire _T_8030 = _T_4991 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8031 = perr_ic_index_ff == 7'h5b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8033 = _T_8031 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8034 = _T_8030 | _T_8033; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8035 = _T_8034 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8038 = tag_valid_clken_2[0] & _T_8035; // @[lib.scala 399:57]
|
|
wire _T_8047 = _T_4992 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8048 = perr_ic_index_ff == 7'h5c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8050 = _T_8048 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8051 = _T_8047 | _T_8050; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8052 = _T_8051 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8055 = tag_valid_clken_2[0] & _T_8052; // @[lib.scala 399:57]
|
|
wire _T_8064 = _T_4993 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8065 = perr_ic_index_ff == 7'h5d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8067 = _T_8065 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8068 = _T_8064 | _T_8067; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8069 = _T_8068 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8072 = tag_valid_clken_2[0] & _T_8069; // @[lib.scala 399:57]
|
|
wire _T_8081 = _T_4994 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8082 = perr_ic_index_ff == 7'h5e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8084 = _T_8082 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8085 = _T_8081 | _T_8084; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8086 = _T_8085 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8089 = tag_valid_clken_2[0] & _T_8086; // @[lib.scala 399:57]
|
|
wire _T_8098 = _T_4995 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8099 = perr_ic_index_ff == 7'h5f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8101 = _T_8099 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8102 = _T_8098 | _T_8101; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8103 = _T_8102 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8106 = tag_valid_clken_2[0] & _T_8103; // @[lib.scala 399:57]
|
|
wire _T_8115 = _T_4964 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8118 = _T_7572 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8119 = _T_8115 | _T_8118; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8120 = _T_8119 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8123 = tag_valid_clken_2[1] & _T_8120; // @[lib.scala 399:57]
|
|
wire _T_8132 = _T_4965 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8135 = _T_7589 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8136 = _T_8132 | _T_8135; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8137 = _T_8136 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8140 = tag_valid_clken_2[1] & _T_8137; // @[lib.scala 399:57]
|
|
wire _T_8149 = _T_4966 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8152 = _T_7606 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8153 = _T_8149 | _T_8152; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8154 = _T_8153 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8157 = tag_valid_clken_2[1] & _T_8154; // @[lib.scala 399:57]
|
|
wire _T_8166 = _T_4967 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8169 = _T_7623 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8170 = _T_8166 | _T_8169; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8171 = _T_8170 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8174 = tag_valid_clken_2[1] & _T_8171; // @[lib.scala 399:57]
|
|
wire _T_8183 = _T_4968 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8186 = _T_7640 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8187 = _T_8183 | _T_8186; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8188 = _T_8187 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8191 = tag_valid_clken_2[1] & _T_8188; // @[lib.scala 399:57]
|
|
wire _T_8200 = _T_4969 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8203 = _T_7657 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8204 = _T_8200 | _T_8203; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8205 = _T_8204 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8208 = tag_valid_clken_2[1] & _T_8205; // @[lib.scala 399:57]
|
|
wire _T_8217 = _T_4970 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8220 = _T_7674 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8221 = _T_8217 | _T_8220; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8222 = _T_8221 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8225 = tag_valid_clken_2[1] & _T_8222; // @[lib.scala 399:57]
|
|
wire _T_8234 = _T_4971 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8237 = _T_7691 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8238 = _T_8234 | _T_8237; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8239 = _T_8238 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8242 = tag_valid_clken_2[1] & _T_8239; // @[lib.scala 399:57]
|
|
wire _T_8251 = _T_4972 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8254 = _T_7708 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8255 = _T_8251 | _T_8254; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8256 = _T_8255 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8259 = tag_valid_clken_2[1] & _T_8256; // @[lib.scala 399:57]
|
|
wire _T_8268 = _T_4973 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8271 = _T_7725 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8272 = _T_8268 | _T_8271; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8273 = _T_8272 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8276 = tag_valid_clken_2[1] & _T_8273; // @[lib.scala 399:57]
|
|
wire _T_8285 = _T_4974 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8288 = _T_7742 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8289 = _T_8285 | _T_8288; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8290 = _T_8289 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8293 = tag_valid_clken_2[1] & _T_8290; // @[lib.scala 399:57]
|
|
wire _T_8302 = _T_4975 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8305 = _T_7759 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8306 = _T_8302 | _T_8305; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8307 = _T_8306 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8310 = tag_valid_clken_2[1] & _T_8307; // @[lib.scala 399:57]
|
|
wire _T_8319 = _T_4976 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8322 = _T_7776 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8323 = _T_8319 | _T_8322; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8324 = _T_8323 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8327 = tag_valid_clken_2[1] & _T_8324; // @[lib.scala 399:57]
|
|
wire _T_8336 = _T_4977 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8339 = _T_7793 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8340 = _T_8336 | _T_8339; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8341 = _T_8340 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8344 = tag_valid_clken_2[1] & _T_8341; // @[lib.scala 399:57]
|
|
wire _T_8353 = _T_4978 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8356 = _T_7810 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8357 = _T_8353 | _T_8356; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8358 = _T_8357 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8361 = tag_valid_clken_2[1] & _T_8358; // @[lib.scala 399:57]
|
|
wire _T_8370 = _T_4979 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8373 = _T_7827 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8374 = _T_8370 | _T_8373; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8375 = _T_8374 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8378 = tag_valid_clken_2[1] & _T_8375; // @[lib.scala 399:57]
|
|
wire _T_8387 = _T_4980 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8390 = _T_7844 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8391 = _T_8387 | _T_8390; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8392 = _T_8391 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8395 = tag_valid_clken_2[1] & _T_8392; // @[lib.scala 399:57]
|
|
wire _T_8404 = _T_4981 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8407 = _T_7861 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8408 = _T_8404 | _T_8407; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8409 = _T_8408 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8412 = tag_valid_clken_2[1] & _T_8409; // @[lib.scala 399:57]
|
|
wire _T_8421 = _T_4982 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8424 = _T_7878 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8425 = _T_8421 | _T_8424; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8426 = _T_8425 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8429 = tag_valid_clken_2[1] & _T_8426; // @[lib.scala 399:57]
|
|
wire _T_8438 = _T_4983 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8441 = _T_7895 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8442 = _T_8438 | _T_8441; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8443 = _T_8442 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8446 = tag_valid_clken_2[1] & _T_8443; // @[lib.scala 399:57]
|
|
wire _T_8455 = _T_4984 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8458 = _T_7912 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8459 = _T_8455 | _T_8458; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8460 = _T_8459 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8463 = tag_valid_clken_2[1] & _T_8460; // @[lib.scala 399:57]
|
|
wire _T_8472 = _T_4985 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8475 = _T_7929 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8476 = _T_8472 | _T_8475; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8477 = _T_8476 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8480 = tag_valid_clken_2[1] & _T_8477; // @[lib.scala 399:57]
|
|
wire _T_8489 = _T_4986 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8492 = _T_7946 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8493 = _T_8489 | _T_8492; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8494 = _T_8493 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8497 = tag_valid_clken_2[1] & _T_8494; // @[lib.scala 399:57]
|
|
wire _T_8506 = _T_4987 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8509 = _T_7963 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8510 = _T_8506 | _T_8509; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8511 = _T_8510 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8514 = tag_valid_clken_2[1] & _T_8511; // @[lib.scala 399:57]
|
|
wire _T_8523 = _T_4988 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8526 = _T_7980 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8527 = _T_8523 | _T_8526; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8528 = _T_8527 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8531 = tag_valid_clken_2[1] & _T_8528; // @[lib.scala 399:57]
|
|
wire _T_8540 = _T_4989 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8543 = _T_7997 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8544 = _T_8540 | _T_8543; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8545 = _T_8544 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8548 = tag_valid_clken_2[1] & _T_8545; // @[lib.scala 399:57]
|
|
wire _T_8557 = _T_4990 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8560 = _T_8014 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8561 = _T_8557 | _T_8560; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8562 = _T_8561 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8565 = tag_valid_clken_2[1] & _T_8562; // @[lib.scala 399:57]
|
|
wire _T_8574 = _T_4991 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8577 = _T_8031 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8578 = _T_8574 | _T_8577; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8579 = _T_8578 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8582 = tag_valid_clken_2[1] & _T_8579; // @[lib.scala 399:57]
|
|
wire _T_8591 = _T_4992 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8594 = _T_8048 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8595 = _T_8591 | _T_8594; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8596 = _T_8595 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8599 = tag_valid_clken_2[1] & _T_8596; // @[lib.scala 399:57]
|
|
wire _T_8608 = _T_4993 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8611 = _T_8065 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8612 = _T_8608 | _T_8611; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8613 = _T_8612 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8616 = tag_valid_clken_2[1] & _T_8613; // @[lib.scala 399:57]
|
|
wire _T_8625 = _T_4994 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8628 = _T_8082 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8629 = _T_8625 | _T_8628; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8630 = _T_8629 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8633 = tag_valid_clken_2[1] & _T_8630; // @[lib.scala 399:57]
|
|
wire _T_8642 = _T_4995 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8645 = _T_8099 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8646 = _T_8642 | _T_8645; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8647 = _T_8646 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8650 = tag_valid_clken_2[1] & _T_8647; // @[lib.scala 399:57]
|
|
wire _T_8659 = _T_4996 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8660 = perr_ic_index_ff == 7'h60; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8662 = _T_8660 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8663 = _T_8659 | _T_8662; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8664 = _T_8663 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8667 = tag_valid_clken_3[0] & _T_8664; // @[lib.scala 399:57]
|
|
wire _T_8676 = _T_4997 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8677 = perr_ic_index_ff == 7'h61; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8679 = _T_8677 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8680 = _T_8676 | _T_8679; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8681 = _T_8680 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8684 = tag_valid_clken_3[0] & _T_8681; // @[lib.scala 399:57]
|
|
wire _T_8693 = _T_4998 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8694 = perr_ic_index_ff == 7'h62; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8696 = _T_8694 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8697 = _T_8693 | _T_8696; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8698 = _T_8697 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8701 = tag_valid_clken_3[0] & _T_8698; // @[lib.scala 399:57]
|
|
wire _T_8710 = _T_4999 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8711 = perr_ic_index_ff == 7'h63; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8713 = _T_8711 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8714 = _T_8710 | _T_8713; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8715 = _T_8714 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8718 = tag_valid_clken_3[0] & _T_8715; // @[lib.scala 399:57]
|
|
wire _T_8727 = _T_5000 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8728 = perr_ic_index_ff == 7'h64; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8730 = _T_8728 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8731 = _T_8727 | _T_8730; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8732 = _T_8731 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8735 = tag_valid_clken_3[0] & _T_8732; // @[lib.scala 399:57]
|
|
wire _T_8744 = _T_5001 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8745 = perr_ic_index_ff == 7'h65; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8747 = _T_8745 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8748 = _T_8744 | _T_8747; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8749 = _T_8748 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8752 = tag_valid_clken_3[0] & _T_8749; // @[lib.scala 399:57]
|
|
wire _T_8761 = _T_5002 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8762 = perr_ic_index_ff == 7'h66; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8764 = _T_8762 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8765 = _T_8761 | _T_8764; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8766 = _T_8765 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8769 = tag_valid_clken_3[0] & _T_8766; // @[lib.scala 399:57]
|
|
wire _T_8778 = _T_5003 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8779 = perr_ic_index_ff == 7'h67; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8781 = _T_8779 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8782 = _T_8778 | _T_8781; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8783 = _T_8782 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8786 = tag_valid_clken_3[0] & _T_8783; // @[lib.scala 399:57]
|
|
wire _T_8795 = _T_5004 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8796 = perr_ic_index_ff == 7'h68; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8798 = _T_8796 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8799 = _T_8795 | _T_8798; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8800 = _T_8799 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8803 = tag_valid_clken_3[0] & _T_8800; // @[lib.scala 399:57]
|
|
wire _T_8812 = _T_5005 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8813 = perr_ic_index_ff == 7'h69; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8815 = _T_8813 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8816 = _T_8812 | _T_8815; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8817 = _T_8816 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8820 = tag_valid_clken_3[0] & _T_8817; // @[lib.scala 399:57]
|
|
wire _T_8829 = _T_5006 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8830 = perr_ic_index_ff == 7'h6a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8832 = _T_8830 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8833 = _T_8829 | _T_8832; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8834 = _T_8833 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8837 = tag_valid_clken_3[0] & _T_8834; // @[lib.scala 399:57]
|
|
wire _T_8846 = _T_5007 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8847 = perr_ic_index_ff == 7'h6b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8849 = _T_8847 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8850 = _T_8846 | _T_8849; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8851 = _T_8850 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8854 = tag_valid_clken_3[0] & _T_8851; // @[lib.scala 399:57]
|
|
wire _T_8863 = _T_5008 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8864 = perr_ic_index_ff == 7'h6c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8866 = _T_8864 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8867 = _T_8863 | _T_8866; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8868 = _T_8867 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8871 = tag_valid_clken_3[0] & _T_8868; // @[lib.scala 399:57]
|
|
wire _T_8880 = _T_5009 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8881 = perr_ic_index_ff == 7'h6d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8883 = _T_8881 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8884 = _T_8880 | _T_8883; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8885 = _T_8884 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8888 = tag_valid_clken_3[0] & _T_8885; // @[lib.scala 399:57]
|
|
wire _T_8897 = _T_5010 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8898 = perr_ic_index_ff == 7'h6e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8900 = _T_8898 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8901 = _T_8897 | _T_8900; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8902 = _T_8901 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8905 = tag_valid_clken_3[0] & _T_8902; // @[lib.scala 399:57]
|
|
wire _T_8914 = _T_5011 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8915 = perr_ic_index_ff == 7'h6f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8917 = _T_8915 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8918 = _T_8914 | _T_8917; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8919 = _T_8918 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8922 = tag_valid_clken_3[0] & _T_8919; // @[lib.scala 399:57]
|
|
wire _T_8931 = _T_5012 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8932 = perr_ic_index_ff == 7'h70; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8934 = _T_8932 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8935 = _T_8931 | _T_8934; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8936 = _T_8935 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8939 = tag_valid_clken_3[0] & _T_8936; // @[lib.scala 399:57]
|
|
wire _T_8948 = _T_5013 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8949 = perr_ic_index_ff == 7'h71; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8951 = _T_8949 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8952 = _T_8948 | _T_8951; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8953 = _T_8952 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8956 = tag_valid_clken_3[0] & _T_8953; // @[lib.scala 399:57]
|
|
wire _T_8965 = _T_5014 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8966 = perr_ic_index_ff == 7'h72; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8968 = _T_8966 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8969 = _T_8965 | _T_8968; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8970 = _T_8969 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8973 = tag_valid_clken_3[0] & _T_8970; // @[lib.scala 399:57]
|
|
wire _T_8982 = _T_5015 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_8983 = perr_ic_index_ff == 7'h73; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_8985 = _T_8983 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_8986 = _T_8982 | _T_8985; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_8987 = _T_8986 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_8990 = tag_valid_clken_3[0] & _T_8987; // @[lib.scala 399:57]
|
|
wire _T_8999 = _T_5016 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9000 = perr_ic_index_ff == 7'h74; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9002 = _T_9000 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9003 = _T_8999 | _T_9002; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9004 = _T_9003 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9007 = tag_valid_clken_3[0] & _T_9004; // @[lib.scala 399:57]
|
|
wire _T_9016 = _T_5017 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9017 = perr_ic_index_ff == 7'h75; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9019 = _T_9017 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9020 = _T_9016 | _T_9019; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9021 = _T_9020 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9024 = tag_valid_clken_3[0] & _T_9021; // @[lib.scala 399:57]
|
|
wire _T_9033 = _T_5018 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9034 = perr_ic_index_ff == 7'h76; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9036 = _T_9034 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9037 = _T_9033 | _T_9036; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9038 = _T_9037 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9041 = tag_valid_clken_3[0] & _T_9038; // @[lib.scala 399:57]
|
|
wire _T_9050 = _T_5019 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9051 = perr_ic_index_ff == 7'h77; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9053 = _T_9051 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9054 = _T_9050 | _T_9053; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9055 = _T_9054 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9058 = tag_valid_clken_3[0] & _T_9055; // @[lib.scala 399:57]
|
|
wire _T_9067 = _T_5020 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9068 = perr_ic_index_ff == 7'h78; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9070 = _T_9068 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9071 = _T_9067 | _T_9070; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9072 = _T_9071 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9075 = tag_valid_clken_3[0] & _T_9072; // @[lib.scala 399:57]
|
|
wire _T_9084 = _T_5021 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9085 = perr_ic_index_ff == 7'h79; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9087 = _T_9085 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9088 = _T_9084 | _T_9087; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9089 = _T_9088 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9092 = tag_valid_clken_3[0] & _T_9089; // @[lib.scala 399:57]
|
|
wire _T_9101 = _T_5022 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9102 = perr_ic_index_ff == 7'h7a; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9104 = _T_9102 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9105 = _T_9101 | _T_9104; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9106 = _T_9105 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9109 = tag_valid_clken_3[0] & _T_9106; // @[lib.scala 399:57]
|
|
wire _T_9118 = _T_5023 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9119 = perr_ic_index_ff == 7'h7b; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9121 = _T_9119 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9122 = _T_9118 | _T_9121; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9123 = _T_9122 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9126 = tag_valid_clken_3[0] & _T_9123; // @[lib.scala 399:57]
|
|
wire _T_9135 = _T_5024 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9136 = perr_ic_index_ff == 7'h7c; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9138 = _T_9136 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9139 = _T_9135 | _T_9138; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9140 = _T_9139 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9143 = tag_valid_clken_3[0] & _T_9140; // @[lib.scala 399:57]
|
|
wire _T_9152 = _T_5025 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9153 = perr_ic_index_ff == 7'h7d; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9155 = _T_9153 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9156 = _T_9152 | _T_9155; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9157 = _T_9156 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9160 = tag_valid_clken_3[0] & _T_9157; // @[lib.scala 399:57]
|
|
wire _T_9169 = _T_5026 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9170 = perr_ic_index_ff == 7'h7e; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9172 = _T_9170 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9173 = _T_9169 | _T_9172; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9174 = _T_9173 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9177 = tag_valid_clken_3[0] & _T_9174; // @[lib.scala 399:57]
|
|
wire _T_9186 = _T_5027 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9187 = perr_ic_index_ff == 7'h7f; // @[ifu_mem_ctl.scala 654:204]
|
|
wire _T_9189 = _T_9187 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9190 = _T_9186 | _T_9189; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9191 = _T_9190 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9194 = tag_valid_clken_3[0] & _T_9191; // @[lib.scala 399:57]
|
|
wire _T_9203 = _T_4996 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9206 = _T_8660 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9207 = _T_9203 | _T_9206; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9208 = _T_9207 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9211 = tag_valid_clken_3[1] & _T_9208; // @[lib.scala 399:57]
|
|
wire _T_9220 = _T_4997 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9223 = _T_8677 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9224 = _T_9220 | _T_9223; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9225 = _T_9224 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9228 = tag_valid_clken_3[1] & _T_9225; // @[lib.scala 399:57]
|
|
wire _T_9237 = _T_4998 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9240 = _T_8694 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9241 = _T_9237 | _T_9240; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9242 = _T_9241 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9245 = tag_valid_clken_3[1] & _T_9242; // @[lib.scala 399:57]
|
|
wire _T_9254 = _T_4999 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9257 = _T_8711 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9258 = _T_9254 | _T_9257; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9259 = _T_9258 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9262 = tag_valid_clken_3[1] & _T_9259; // @[lib.scala 399:57]
|
|
wire _T_9271 = _T_5000 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9274 = _T_8728 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9275 = _T_9271 | _T_9274; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9276 = _T_9275 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9279 = tag_valid_clken_3[1] & _T_9276; // @[lib.scala 399:57]
|
|
wire _T_9288 = _T_5001 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9291 = _T_8745 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9292 = _T_9288 | _T_9291; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9293 = _T_9292 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9296 = tag_valid_clken_3[1] & _T_9293; // @[lib.scala 399:57]
|
|
wire _T_9305 = _T_5002 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9308 = _T_8762 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9309 = _T_9305 | _T_9308; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9310 = _T_9309 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9313 = tag_valid_clken_3[1] & _T_9310; // @[lib.scala 399:57]
|
|
wire _T_9322 = _T_5003 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9325 = _T_8779 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9326 = _T_9322 | _T_9325; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9327 = _T_9326 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9330 = tag_valid_clken_3[1] & _T_9327; // @[lib.scala 399:57]
|
|
wire _T_9339 = _T_5004 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9342 = _T_8796 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9343 = _T_9339 | _T_9342; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9344 = _T_9343 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9347 = tag_valid_clken_3[1] & _T_9344; // @[lib.scala 399:57]
|
|
wire _T_9356 = _T_5005 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9359 = _T_8813 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9360 = _T_9356 | _T_9359; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9361 = _T_9360 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9364 = tag_valid_clken_3[1] & _T_9361; // @[lib.scala 399:57]
|
|
wire _T_9373 = _T_5006 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9376 = _T_8830 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9377 = _T_9373 | _T_9376; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9378 = _T_9377 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9381 = tag_valid_clken_3[1] & _T_9378; // @[lib.scala 399:57]
|
|
wire _T_9390 = _T_5007 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9393 = _T_8847 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9394 = _T_9390 | _T_9393; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9395 = _T_9394 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9398 = tag_valid_clken_3[1] & _T_9395; // @[lib.scala 399:57]
|
|
wire _T_9407 = _T_5008 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9410 = _T_8864 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9411 = _T_9407 | _T_9410; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9412 = _T_9411 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9415 = tag_valid_clken_3[1] & _T_9412; // @[lib.scala 399:57]
|
|
wire _T_9424 = _T_5009 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9427 = _T_8881 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9428 = _T_9424 | _T_9427; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9429 = _T_9428 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9432 = tag_valid_clken_3[1] & _T_9429; // @[lib.scala 399:57]
|
|
wire _T_9441 = _T_5010 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9444 = _T_8898 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9445 = _T_9441 | _T_9444; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9446 = _T_9445 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9449 = tag_valid_clken_3[1] & _T_9446; // @[lib.scala 399:57]
|
|
wire _T_9458 = _T_5011 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9461 = _T_8915 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9462 = _T_9458 | _T_9461; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9463 = _T_9462 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9466 = tag_valid_clken_3[1] & _T_9463; // @[lib.scala 399:57]
|
|
wire _T_9475 = _T_5012 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9478 = _T_8932 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9479 = _T_9475 | _T_9478; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9480 = _T_9479 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9483 = tag_valid_clken_3[1] & _T_9480; // @[lib.scala 399:57]
|
|
wire _T_9492 = _T_5013 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9495 = _T_8949 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9496 = _T_9492 | _T_9495; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9497 = _T_9496 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9500 = tag_valid_clken_3[1] & _T_9497; // @[lib.scala 399:57]
|
|
wire _T_9509 = _T_5014 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9512 = _T_8966 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9513 = _T_9509 | _T_9512; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9514 = _T_9513 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9517 = tag_valid_clken_3[1] & _T_9514; // @[lib.scala 399:57]
|
|
wire _T_9526 = _T_5015 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9529 = _T_8983 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9530 = _T_9526 | _T_9529; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9531 = _T_9530 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9534 = tag_valid_clken_3[1] & _T_9531; // @[lib.scala 399:57]
|
|
wire _T_9543 = _T_5016 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9546 = _T_9000 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9547 = _T_9543 | _T_9546; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9548 = _T_9547 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9551 = tag_valid_clken_3[1] & _T_9548; // @[lib.scala 399:57]
|
|
wire _T_9560 = _T_5017 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9563 = _T_9017 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9564 = _T_9560 | _T_9563; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9565 = _T_9564 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9568 = tag_valid_clken_3[1] & _T_9565; // @[lib.scala 399:57]
|
|
wire _T_9577 = _T_5018 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9580 = _T_9034 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9581 = _T_9577 | _T_9580; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9582 = _T_9581 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9585 = tag_valid_clken_3[1] & _T_9582; // @[lib.scala 399:57]
|
|
wire _T_9594 = _T_5019 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9597 = _T_9051 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9598 = _T_9594 | _T_9597; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9599 = _T_9598 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9602 = tag_valid_clken_3[1] & _T_9599; // @[lib.scala 399:57]
|
|
wire _T_9611 = _T_5020 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9614 = _T_9068 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9615 = _T_9611 | _T_9614; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9616 = _T_9615 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9619 = tag_valid_clken_3[1] & _T_9616; // @[lib.scala 399:57]
|
|
wire _T_9628 = _T_5021 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9631 = _T_9085 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9632 = _T_9628 | _T_9631; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9633 = _T_9632 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9636 = tag_valid_clken_3[1] & _T_9633; // @[lib.scala 399:57]
|
|
wire _T_9645 = _T_5022 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9648 = _T_9102 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9649 = _T_9645 | _T_9648; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9650 = _T_9649 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9653 = tag_valid_clken_3[1] & _T_9650; // @[lib.scala 399:57]
|
|
wire _T_9662 = _T_5023 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9665 = _T_9119 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9666 = _T_9662 | _T_9665; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9667 = _T_9666 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9670 = tag_valid_clken_3[1] & _T_9667; // @[lib.scala 399:57]
|
|
wire _T_9679 = _T_5024 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9682 = _T_9136 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9683 = _T_9679 | _T_9682; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9684 = _T_9683 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9687 = tag_valid_clken_3[1] & _T_9684; // @[lib.scala 399:57]
|
|
wire _T_9696 = _T_5025 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9699 = _T_9153 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9700 = _T_9696 | _T_9699; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9701 = _T_9700 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9704 = tag_valid_clken_3[1] & _T_9701; // @[lib.scala 399:57]
|
|
wire _T_9713 = _T_5026 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9716 = _T_9170 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9717 = _T_9713 | _T_9716; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9718 = _T_9717 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9721 = tag_valid_clken_3[1] & _T_9718; // @[lib.scala 399:57]
|
|
wire _T_9730 = _T_5027 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 654:161]
|
|
wire _T_9733 = _T_9187 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 654:226]
|
|
wire _T_9734 = _T_9730 | _T_9733; // @[ifu_mem_ctl.scala 654:183]
|
|
wire _T_9735 = _T_9734 | reset_all_tags; // @[ifu_mem_ctl.scala 654:249]
|
|
wire _T_9738 = tag_valid_clken_3[1] & _T_9735; // @[lib.scala 399:57]
|
|
wire _T_10539 = ~fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 702:63]
|
|
wire _T_10540 = _T_10539 & ifc_fetch_req_f_raw; // @[ifu_mem_ctl.scala 702:85]
|
|
wire [1:0] _T_10542 = _T_10540 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg _T_10552; // @[Reg.scala 27:20]
|
|
wire _T_10550 = ic_act_miss_f ^ _T_10552; // @[lib.scala 488:21]
|
|
wire _T_10551 = |_T_10550; // @[lib.scala 488:29]
|
|
reg _T_10556; // @[Reg.scala 27:20]
|
|
wire _T_10554 = ic_act_hit_f ^ _T_10556; // @[lib.scala 488:21]
|
|
wire _T_10555 = |_T_10554; // @[lib.scala 488:29]
|
|
reg _T_10561; // @[Reg.scala 27:20]
|
|
wire _T_10559 = _T_2500 ^ _T_10561; // @[lib.scala 488:21]
|
|
wire _T_10560 = |_T_10559; // @[lib.scala 488:29]
|
|
wire _T_10562 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 710:69]
|
|
wire _T_10563 = ifu_bus_arvalid_ff & _T_10562; // @[ifu_mem_ctl.scala 710:67]
|
|
wire _T_10564 = _T_10563 & miss_pending; // @[ifu_mem_ctl.scala 710:89]
|
|
reg _T_10568; // @[Reg.scala 27:20]
|
|
wire _T_10566 = _T_10564 ^ _T_10568; // @[lib.scala 488:21]
|
|
wire _T_10567 = |_T_10566; // @[lib.scala 488:29]
|
|
reg _T_10572; // @[Reg.scala 27:20]
|
|
wire _T_10570 = bus_cmd_sent ^ _T_10572; // @[lib.scala 488:21]
|
|
wire _T_10571 = |_T_10570; // @[lib.scala 488:29]
|
|
wire _T_10575 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 718:84]
|
|
wire _T_10577 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 718:150]
|
|
wire _T_10579 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 719:63]
|
|
wire _T_10581 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[ifu_mem_ctl.scala 719:129]
|
|
wire [3:0] _T_10584 = {_T_10575,_T_10577,_T_10579,_T_10581}; // @[Cat.scala 29:58]
|
|
wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 721:53]
|
|
wire _T_10592 = io_ic_debug_rd_en ^ ic_debug_rd_en_ff; // @[lib.scala 488:21]
|
|
wire _T_10593 = |_T_10592; // @[lib.scala 488:29]
|
|
reg _T_10598; // @[Reg.scala 27:20]
|
|
wire _T_10596 = ic_debug_rd_en_ff ^ _T_10598; // @[lib.scala 488:21]
|
|
wire _T_10597 = |_T_10596; // @[lib.scala 488:29]
|
|
wire _T_10660 = ifc_region_acc_fault_memory_bf ^ ifc_region_acc_fault_memory_f; // @[lib.scala 488:21]
|
|
wire _T_10661 = |_T_10660; // @[lib.scala 488:29]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_35 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_35_io_clk),
|
|
.io_en(rvclkhdr_35_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_36 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_36_io_clk),
|
|
.io_en(rvclkhdr_36_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_37 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_37_io_clk),
|
|
.io_en(rvclkhdr_37_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_38 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_38_io_clk),
|
|
.io_en(rvclkhdr_38_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_39 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_39_io_clk),
|
|
.io_en(rvclkhdr_39_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_40 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_40_io_clk),
|
|
.io_en(rvclkhdr_40_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_41 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_41_io_clk),
|
|
.io_en(rvclkhdr_41_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_42 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_42_io_clk),
|
|
.io_en(rvclkhdr_42_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_43 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_43_io_clk),
|
|
.io_en(rvclkhdr_43_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_44 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_44_io_clk),
|
|
.io_en(rvclkhdr_44_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_45 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_45_io_clk),
|
|
.io_en(rvclkhdr_45_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_46 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_46_io_clk),
|
|
.io_en(rvclkhdr_46_io_en)
|
|
);
|
|
assign io_dec_mem_ctrl_ifu_pmu_ic_miss = _T_10552; // @[ifu_mem_ctl.scala 707:37]
|
|
assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_10556; // @[ifu_mem_ctl.scala 708:37]
|
|
assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_10561; // @[ifu_mem_ctl.scala 709:37]
|
|
assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_10568; // @[ifu_mem_ctl.scala 710:37]
|
|
assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_10572; // @[ifu_mem_ctl.scala 711:37]
|
|
assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1225 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 252:38]
|
|
assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3981 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 571:48]
|
|
assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1237; // @[ifu_mem_ctl.scala 260:40]
|
|
assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_10598; // @[ifu_mem_ctl.scala 725:46]
|
|
assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 232:39]
|
|
assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 468:14 ifu_mem_ctl.scala 470:23]
|
|
assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2639; // @[ifu_mem_ctl.scala 468:14 ifu_mem_ctl.scala 471:25]
|
|
assign io_ifu_axi_ar_bits_addr = _T_2641 & _T_2643; // @[ifu_mem_ctl.scala 468:14 ifu_mem_ctl.scala 472:27]
|
|
assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 468:14 ifu_mem_ctl.scala 475:29]
|
|
assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 468:14 ifu_mem_ctl.scala 477:22]
|
|
assign io_iccm_rw_addr = _T_3180 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3187; // @[ifu_mem_ctl.scala 558:19]
|
|
assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2519; // @[ifu_mem_ctl.scala 385:27]
|
|
assign io_iccm_correction_state = _T_2547 ? 1'h0 : _GEN_81; // @[ifu_mem_ctl.scala 419:28 ifu_mem_ctl.scala 431:32 ifu_mem_ctl.scala 438:32 ifu_mem_ctl.scala 445:32]
|
|
assign io_iccm_wren = _T_2760 | iccm_correct_ecc; // @[ifu_mem_ctl.scala 532:16]
|
|
assign io_iccm_rden = _T_2764 | _T_2765; // @[ifu_mem_ctl.scala 533:16]
|
|
assign io_iccm_wr_size = _T_2770 & io_dma_mem_ctl_dma_mem_sz; // @[ifu_mem_ctl.scala 535:19]
|
|
assign io_iccm_wr_data = _T_3142 ? _T_3143 : _T_3150; // @[ifu_mem_ctl.scala 539:19]
|
|
assign io_ic_rw_addr = _T_360 | _T_361; // @[ifu_mem_ctl.scala 236:17]
|
|
assign io_ic_tag_valid = ic_tag_valid_unq & _T_10542; // @[ifu_mem_ctl.scala 702:19]
|
|
assign io_ic_wr_en = bus_ic_wr_en & _T_4063; // @[ifu_mem_ctl.scala 601:15]
|
|
assign io_ic_rd_en = _T_4055 | _T_4060; // @[ifu_mem_ctl.scala 592:15]
|
|
assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 249:17]
|
|
assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 249:17]
|
|
assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 250:23]
|
|
assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 714:20]
|
|
assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 716:21]
|
|
assign io_ic_debug_wr_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu_mem_ctl.scala 717:21]
|
|
assign io_ic_debug_tag_array = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[ifu_mem_ctl.scala 715:25]
|
|
assign io_ic_debug_way = _T_10584[1:0]; // @[ifu_mem_ctl.scala 718:19]
|
|
assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 287:21]
|
|
assign io_ic_sel_premux_data = fetch_req_iccm_f | _T_1280; // @[ifu_mem_ctl.scala 288:25]
|
|
assign io_ifu_ic_mb_empty = _T_348 | _T_237; // @[ifu_mem_ctl.scala 231:22]
|
|
assign io_ic_dma_active = _T_14 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 93:20]
|
|
assign io_ic_write_stall = write_ic_16_bytes & _T_4077; // @[ifu_mem_ctl.scala 602:21]
|
|
assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 554:25]
|
|
assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 552:22]
|
|
assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 556:21]
|
|
assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 548:20]
|
|
assign io_iccm_ready = _T_2752 & _T_2742; // @[ifu_mem_ctl.scala 530:18]
|
|
assign io_iccm_rd_ecc_double_err = _T_2153 ? _T_3990 : _T_3996; // @[ifu_mem_ctl.scala 572:31]
|
|
assign io_iccm_dma_sb_error = _T_6 & dma_iccm_req_f; // @[ifu_mem_ctl.scala 91:24]
|
|
assign io_ic_hit_f = _T_269 | _T_270; // @[ifu_mem_ctl.scala 191:15]
|
|
assign io_ic_access_fault_f = _T_1302 & _T_1305; // @[ifu_mem_ctl.scala 293:24]
|
|
assign io_ic_access_fault_type_f = _T_1307 ? 2'h1 : _T_1310; // @[ifu_mem_ctl.scala 294:29]
|
|
assign io_ifu_async_error_start = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 92:28]
|
|
assign io_ic_fetch_val_f = {_T_1318,fetch_req_f_qual}; // @[ifu_mem_ctl.scala 296:21]
|
|
assign io_ic_data_f = ic_final_data[31:0]; // @[ifu_mem_ctl.scala 290:16]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[lib.scala 351:16]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = io_ifu_bus_clk_en & io_ifu_axi_r_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = ic_debug_rd_en_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = bus_ifu_wr_en & _T_1321; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1321; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1322; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1322; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1323; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1323; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1324; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1324; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1325; // @[lib.scala 425:17]
|
|
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1325; // @[lib.scala 425:17]
|
|
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1326; // @[lib.scala 425:17]
|
|
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1326; // @[lib.scala 425:17]
|
|
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1327; // @[lib.scala 425:17]
|
|
assign rvclkhdr_16_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1327; // @[lib.scala 425:17]
|
|
assign rvclkhdr_17_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1328; // @[lib.scala 425:17]
|
|
assign rvclkhdr_18_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1328; // @[lib.scala 425:17]
|
|
assign rvclkhdr_19_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_19_io_en = _T_2521 & perr_state_en; // @[lib.scala 425:17]
|
|
assign rvclkhdr_20_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_20_io_en = iccm_dma_rvalid_in; // @[lib.scala 425:17]
|
|
assign rvclkhdr_21_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_21_io_en = _T_4008 | io_iccm_dma_sb_error; // @[lib.scala 425:17]
|
|
assign rvclkhdr_22_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_22_io_en = _T_4008 | io_iccm_dma_sb_error; // @[lib.scala 425:17]
|
|
assign rvclkhdr_23_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_23_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[lib.scala 351:16]
|
|
assign rvclkhdr_24_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_24_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[lib.scala 351:16]
|
|
assign rvclkhdr_25_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_25_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[lib.scala 351:16]
|
|
assign rvclkhdr_26_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_26_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[lib.scala 351:16]
|
|
assign rvclkhdr_27_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_27_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[lib.scala 351:16]
|
|
assign rvclkhdr_28_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_28_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[lib.scala 351:16]
|
|
assign rvclkhdr_29_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_29_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[lib.scala 351:16]
|
|
assign rvclkhdr_30_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_30_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[lib.scala 351:16]
|
|
assign rvclkhdr_31_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_31_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[lib.scala 351:16]
|
|
assign rvclkhdr_32_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_32_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[lib.scala 351:16]
|
|
assign rvclkhdr_33_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_33_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[lib.scala 351:16]
|
|
assign rvclkhdr_34_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_34_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[lib.scala 351:16]
|
|
assign rvclkhdr_35_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_35_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[lib.scala 351:16]
|
|
assign rvclkhdr_36_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_36_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[lib.scala 351:16]
|
|
assign rvclkhdr_37_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_37_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[lib.scala 351:16]
|
|
assign rvclkhdr_38_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_38_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[lib.scala 351:16]
|
|
assign rvclkhdr_39_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_39_io_en = tag_valid_clken_0[0]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_40_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_40_io_en = tag_valid_clken_0[1]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_41_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_41_io_en = tag_valid_clken_1[0]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_42_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_42_io_en = tag_valid_clken_1[1]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_43_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_43_io_en = tag_valid_clken_2[0]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_44_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_44_io_en = tag_valid_clken_2[1]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_45_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_45_io_en = tag_valid_clken_3[0]; // @[lib.scala 351:16]
|
|
assign rvclkhdr_46_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_46_io_en = tag_valid_clken_3[1]; // @[lib.scala 351:16]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
flush_final_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
ifc_fetch_req_f_raw = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
miss_state = _RAND_2[2:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
scnd_miss_req_q = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
ifu_fetch_addr_int_f = _RAND_4[30:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
ifc_iccm_access_f = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
iccm_dma_rvalid_in = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
dma_iccm_req_f = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
perr_state = _RAND_8[2:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
err_stop_state = _RAND_9[1:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
reset_all_tags = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
ifc_region_acc_fault_final_f = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
ifu_bus_rvalid_unq_ff = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
bus_ifu_bus_clk_en_ff = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
uncacheable_miss_ff = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
bus_data_beat_count = _RAND_15[2:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
ic_miss_buff_data_valid = _RAND_16[7:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
imb_ff = _RAND_17[30:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
last_data_recieved_ff = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
sel_mb_addr_ff = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
way_status_mb_scnd_ff = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
ifu_ic_rw_int_addr_ff = _RAND_21[6:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
way_status_out_0 = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
way_status_out_1 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
way_status_out_2 = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
way_status_out_3 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
way_status_out_4 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
way_status_out_5 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
way_status_out_6 = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
way_status_out_7 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
way_status_out_8 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
way_status_out_9 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
way_status_out_10 = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
way_status_out_11 = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
way_status_out_12 = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
way_status_out_13 = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
way_status_out_14 = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
way_status_out_15 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
way_status_out_16 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
way_status_out_17 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
way_status_out_18 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
way_status_out_19 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
way_status_out_20 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
way_status_out_21 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
way_status_out_22 = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
way_status_out_23 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
way_status_out_24 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
way_status_out_25 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
way_status_out_26 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
way_status_out_27 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
way_status_out_28 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
way_status_out_29 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
way_status_out_30 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
way_status_out_31 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
way_status_out_32 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
way_status_out_33 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
way_status_out_34 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
way_status_out_35 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
way_status_out_36 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
way_status_out_37 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
way_status_out_38 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
way_status_out_39 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
way_status_out_40 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
way_status_out_41 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
way_status_out_42 = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
way_status_out_43 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
way_status_out_44 = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
way_status_out_45 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
way_status_out_46 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
way_status_out_47 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
way_status_out_48 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
way_status_out_49 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
way_status_out_50 = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
way_status_out_51 = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
way_status_out_52 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
way_status_out_53 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
way_status_out_54 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
way_status_out_55 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
way_status_out_56 = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
way_status_out_57 = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
way_status_out_58 = _RAND_80[0:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
way_status_out_59 = _RAND_81[0:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
way_status_out_60 = _RAND_82[0:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
way_status_out_61 = _RAND_83[0:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
way_status_out_62 = _RAND_84[0:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
way_status_out_63 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
way_status_out_64 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
way_status_out_65 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
way_status_out_66 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
way_status_out_67 = _RAND_89[0:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
way_status_out_68 = _RAND_90[0:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
way_status_out_69 = _RAND_91[0:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
way_status_out_70 = _RAND_92[0:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
way_status_out_71 = _RAND_93[0:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
way_status_out_72 = _RAND_94[0:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
way_status_out_73 = _RAND_95[0:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
way_status_out_74 = _RAND_96[0:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
way_status_out_75 = _RAND_97[0:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
way_status_out_76 = _RAND_98[0:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
way_status_out_77 = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
way_status_out_78 = _RAND_100[0:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
way_status_out_79 = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
way_status_out_80 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
way_status_out_81 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
way_status_out_82 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
way_status_out_83 = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
way_status_out_84 = _RAND_106[0:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
way_status_out_85 = _RAND_107[0:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
way_status_out_86 = _RAND_108[0:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
way_status_out_87 = _RAND_109[0:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
way_status_out_88 = _RAND_110[0:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
way_status_out_89 = _RAND_111[0:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
way_status_out_90 = _RAND_112[0:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
way_status_out_91 = _RAND_113[0:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
way_status_out_92 = _RAND_114[0:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
way_status_out_93 = _RAND_115[0:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
way_status_out_94 = _RAND_116[0:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
way_status_out_95 = _RAND_117[0:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
way_status_out_96 = _RAND_118[0:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
way_status_out_97 = _RAND_119[0:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
way_status_out_98 = _RAND_120[0:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
way_status_out_99 = _RAND_121[0:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
way_status_out_100 = _RAND_122[0:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
way_status_out_101 = _RAND_123[0:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
way_status_out_102 = _RAND_124[0:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
way_status_out_103 = _RAND_125[0:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
way_status_out_104 = _RAND_126[0:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
way_status_out_105 = _RAND_127[0:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
way_status_out_106 = _RAND_128[0:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
way_status_out_107 = _RAND_129[0:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
way_status_out_108 = _RAND_130[0:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
way_status_out_109 = _RAND_131[0:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
way_status_out_110 = _RAND_132[0:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
way_status_out_111 = _RAND_133[0:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
way_status_out_112 = _RAND_134[0:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
way_status_out_113 = _RAND_135[0:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
way_status_out_114 = _RAND_136[0:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
way_status_out_115 = _RAND_137[0:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
way_status_out_116 = _RAND_138[0:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
way_status_out_117 = _RAND_139[0:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
way_status_out_118 = _RAND_140[0:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
way_status_out_119 = _RAND_141[0:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
way_status_out_120 = _RAND_142[0:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
way_status_out_121 = _RAND_143[0:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
way_status_out_122 = _RAND_144[0:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
way_status_out_123 = _RAND_145[0:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
way_status_out_124 = _RAND_146[0:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
way_status_out_125 = _RAND_147[0:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
way_status_out_126 = _RAND_148[0:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
way_status_out_127 = _RAND_149[0:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
tagv_mb_scnd_ff = _RAND_150[1:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
uncacheable_miss_scnd_ff = _RAND_151[0:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
imb_scnd_ff = _RAND_152[30:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
ifu_bus_rid_ff = _RAND_153[2:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
ifu_bus_rresp_ff = _RAND_154[1:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
ifu_wr_data_comb_err_ff = _RAND_155[0:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
way_status_mb_ff = _RAND_156[0:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
tagv_mb_ff = _RAND_157[1:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
reset_ic_ff = _RAND_158[0:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
fetch_uncacheable_ff = _RAND_159[0:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
miss_addr = _RAND_160[25:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
ifc_region_acc_fault_f = _RAND_161[0:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
bus_rd_addr_count = _RAND_162[2:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
ic_act_miss_f_delayed = _RAND_163[0:0];
|
|
_RAND_164 = {2{`RANDOM}};
|
|
ifu_bus_rdata_ff = _RAND_164[63:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
ic_miss_buff_data_0 = _RAND_165[31:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
ic_miss_buff_data_1 = _RAND_166[31:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
ic_miss_buff_data_2 = _RAND_167[31:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
ic_miss_buff_data_3 = _RAND_168[31:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
ic_miss_buff_data_4 = _RAND_169[31:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
ic_miss_buff_data_5 = _RAND_170[31:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
ic_miss_buff_data_6 = _RAND_171[31:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
ic_miss_buff_data_7 = _RAND_172[31:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
ic_miss_buff_data_8 = _RAND_173[31:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
ic_miss_buff_data_9 = _RAND_174[31:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
ic_miss_buff_data_10 = _RAND_175[31:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
ic_miss_buff_data_11 = _RAND_176[31:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
ic_miss_buff_data_12 = _RAND_177[31:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
ic_miss_buff_data_13 = _RAND_178[31:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
ic_miss_buff_data_14 = _RAND_179[31:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
ic_miss_buff_data_15 = _RAND_180[31:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
ic_crit_wd_rdy_new_ff = _RAND_181[0:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
ic_miss_buff_data_error = _RAND_182[7:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
ic_debug_ict_array_sel_ff = _RAND_183[0:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_0 = _RAND_184[0:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_1 = _RAND_185[0:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_2 = _RAND_186[0:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_3 = _RAND_187[0:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_4 = _RAND_188[0:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_5 = _RAND_189[0:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_6 = _RAND_190[0:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_7 = _RAND_191[0:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_8 = _RAND_192[0:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_9 = _RAND_193[0:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_10 = _RAND_194[0:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_11 = _RAND_195[0:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_12 = _RAND_196[0:0];
|
|
_RAND_197 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_13 = _RAND_197[0:0];
|
|
_RAND_198 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_14 = _RAND_198[0:0];
|
|
_RAND_199 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_15 = _RAND_199[0:0];
|
|
_RAND_200 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_16 = _RAND_200[0:0];
|
|
_RAND_201 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_17 = _RAND_201[0:0];
|
|
_RAND_202 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_18 = _RAND_202[0:0];
|
|
_RAND_203 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_19 = _RAND_203[0:0];
|
|
_RAND_204 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_20 = _RAND_204[0:0];
|
|
_RAND_205 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_21 = _RAND_205[0:0];
|
|
_RAND_206 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_22 = _RAND_206[0:0];
|
|
_RAND_207 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_23 = _RAND_207[0:0];
|
|
_RAND_208 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_24 = _RAND_208[0:0];
|
|
_RAND_209 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_25 = _RAND_209[0:0];
|
|
_RAND_210 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_26 = _RAND_210[0:0];
|
|
_RAND_211 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_27 = _RAND_211[0:0];
|
|
_RAND_212 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_28 = _RAND_212[0:0];
|
|
_RAND_213 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_29 = _RAND_213[0:0];
|
|
_RAND_214 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_30 = _RAND_214[0:0];
|
|
_RAND_215 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_31 = _RAND_215[0:0];
|
|
_RAND_216 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_32 = _RAND_216[0:0];
|
|
_RAND_217 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_33 = _RAND_217[0:0];
|
|
_RAND_218 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_34 = _RAND_218[0:0];
|
|
_RAND_219 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_35 = _RAND_219[0:0];
|
|
_RAND_220 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_36 = _RAND_220[0:0];
|
|
_RAND_221 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_37 = _RAND_221[0:0];
|
|
_RAND_222 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_38 = _RAND_222[0:0];
|
|
_RAND_223 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_39 = _RAND_223[0:0];
|
|
_RAND_224 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_40 = _RAND_224[0:0];
|
|
_RAND_225 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_41 = _RAND_225[0:0];
|
|
_RAND_226 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_42 = _RAND_226[0:0];
|
|
_RAND_227 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_43 = _RAND_227[0:0];
|
|
_RAND_228 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_44 = _RAND_228[0:0];
|
|
_RAND_229 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_45 = _RAND_229[0:0];
|
|
_RAND_230 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_46 = _RAND_230[0:0];
|
|
_RAND_231 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_47 = _RAND_231[0:0];
|
|
_RAND_232 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_48 = _RAND_232[0:0];
|
|
_RAND_233 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_49 = _RAND_233[0:0];
|
|
_RAND_234 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_50 = _RAND_234[0:0];
|
|
_RAND_235 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_51 = _RAND_235[0:0];
|
|
_RAND_236 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_52 = _RAND_236[0:0];
|
|
_RAND_237 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_53 = _RAND_237[0:0];
|
|
_RAND_238 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_54 = _RAND_238[0:0];
|
|
_RAND_239 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_55 = _RAND_239[0:0];
|
|
_RAND_240 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_56 = _RAND_240[0:0];
|
|
_RAND_241 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_57 = _RAND_241[0:0];
|
|
_RAND_242 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_58 = _RAND_242[0:0];
|
|
_RAND_243 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_59 = _RAND_243[0:0];
|
|
_RAND_244 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_60 = _RAND_244[0:0];
|
|
_RAND_245 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_61 = _RAND_245[0:0];
|
|
_RAND_246 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_62 = _RAND_246[0:0];
|
|
_RAND_247 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_63 = _RAND_247[0:0];
|
|
_RAND_248 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_64 = _RAND_248[0:0];
|
|
_RAND_249 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_65 = _RAND_249[0:0];
|
|
_RAND_250 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_66 = _RAND_250[0:0];
|
|
_RAND_251 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_67 = _RAND_251[0:0];
|
|
_RAND_252 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_68 = _RAND_252[0:0];
|
|
_RAND_253 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_69 = _RAND_253[0:0];
|
|
_RAND_254 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_70 = _RAND_254[0:0];
|
|
_RAND_255 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_71 = _RAND_255[0:0];
|
|
_RAND_256 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_72 = _RAND_256[0:0];
|
|
_RAND_257 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_73 = _RAND_257[0:0];
|
|
_RAND_258 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_74 = _RAND_258[0:0];
|
|
_RAND_259 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_75 = _RAND_259[0:0];
|
|
_RAND_260 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_76 = _RAND_260[0:0];
|
|
_RAND_261 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_77 = _RAND_261[0:0];
|
|
_RAND_262 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_78 = _RAND_262[0:0];
|
|
_RAND_263 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_79 = _RAND_263[0:0];
|
|
_RAND_264 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_80 = _RAND_264[0:0];
|
|
_RAND_265 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_81 = _RAND_265[0:0];
|
|
_RAND_266 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_82 = _RAND_266[0:0];
|
|
_RAND_267 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_83 = _RAND_267[0:0];
|
|
_RAND_268 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_84 = _RAND_268[0:0];
|
|
_RAND_269 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_85 = _RAND_269[0:0];
|
|
_RAND_270 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_86 = _RAND_270[0:0];
|
|
_RAND_271 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_87 = _RAND_271[0:0];
|
|
_RAND_272 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_88 = _RAND_272[0:0];
|
|
_RAND_273 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_89 = _RAND_273[0:0];
|
|
_RAND_274 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_90 = _RAND_274[0:0];
|
|
_RAND_275 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_91 = _RAND_275[0:0];
|
|
_RAND_276 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_92 = _RAND_276[0:0];
|
|
_RAND_277 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_93 = _RAND_277[0:0];
|
|
_RAND_278 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_94 = _RAND_278[0:0];
|
|
_RAND_279 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_95 = _RAND_279[0:0];
|
|
_RAND_280 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_96 = _RAND_280[0:0];
|
|
_RAND_281 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_97 = _RAND_281[0:0];
|
|
_RAND_282 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_98 = _RAND_282[0:0];
|
|
_RAND_283 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_99 = _RAND_283[0:0];
|
|
_RAND_284 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_100 = _RAND_284[0:0];
|
|
_RAND_285 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_101 = _RAND_285[0:0];
|
|
_RAND_286 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_102 = _RAND_286[0:0];
|
|
_RAND_287 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_103 = _RAND_287[0:0];
|
|
_RAND_288 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_104 = _RAND_288[0:0];
|
|
_RAND_289 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_105 = _RAND_289[0:0];
|
|
_RAND_290 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_106 = _RAND_290[0:0];
|
|
_RAND_291 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_107 = _RAND_291[0:0];
|
|
_RAND_292 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_108 = _RAND_292[0:0];
|
|
_RAND_293 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_109 = _RAND_293[0:0];
|
|
_RAND_294 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_110 = _RAND_294[0:0];
|
|
_RAND_295 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_111 = _RAND_295[0:0];
|
|
_RAND_296 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_112 = _RAND_296[0:0];
|
|
_RAND_297 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_113 = _RAND_297[0:0];
|
|
_RAND_298 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_114 = _RAND_298[0:0];
|
|
_RAND_299 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_115 = _RAND_299[0:0];
|
|
_RAND_300 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_116 = _RAND_300[0:0];
|
|
_RAND_301 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_117 = _RAND_301[0:0];
|
|
_RAND_302 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_118 = _RAND_302[0:0];
|
|
_RAND_303 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_119 = _RAND_303[0:0];
|
|
_RAND_304 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_120 = _RAND_304[0:0];
|
|
_RAND_305 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_121 = _RAND_305[0:0];
|
|
_RAND_306 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_122 = _RAND_306[0:0];
|
|
_RAND_307 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_123 = _RAND_307[0:0];
|
|
_RAND_308 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_124 = _RAND_308[0:0];
|
|
_RAND_309 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_125 = _RAND_309[0:0];
|
|
_RAND_310 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_126 = _RAND_310[0:0];
|
|
_RAND_311 = {1{`RANDOM}};
|
|
ic_tag_valid_out_1_127 = _RAND_311[0:0];
|
|
_RAND_312 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_0 = _RAND_312[0:0];
|
|
_RAND_313 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_1 = _RAND_313[0:0];
|
|
_RAND_314 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_2 = _RAND_314[0:0];
|
|
_RAND_315 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_3 = _RAND_315[0:0];
|
|
_RAND_316 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_4 = _RAND_316[0:0];
|
|
_RAND_317 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_5 = _RAND_317[0:0];
|
|
_RAND_318 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_6 = _RAND_318[0:0];
|
|
_RAND_319 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_7 = _RAND_319[0:0];
|
|
_RAND_320 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_8 = _RAND_320[0:0];
|
|
_RAND_321 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_9 = _RAND_321[0:0];
|
|
_RAND_322 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_10 = _RAND_322[0:0];
|
|
_RAND_323 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_11 = _RAND_323[0:0];
|
|
_RAND_324 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_12 = _RAND_324[0:0];
|
|
_RAND_325 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_13 = _RAND_325[0:0];
|
|
_RAND_326 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_14 = _RAND_326[0:0];
|
|
_RAND_327 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_15 = _RAND_327[0:0];
|
|
_RAND_328 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_16 = _RAND_328[0:0];
|
|
_RAND_329 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_17 = _RAND_329[0:0];
|
|
_RAND_330 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_18 = _RAND_330[0:0];
|
|
_RAND_331 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_19 = _RAND_331[0:0];
|
|
_RAND_332 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_20 = _RAND_332[0:0];
|
|
_RAND_333 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_21 = _RAND_333[0:0];
|
|
_RAND_334 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_22 = _RAND_334[0:0];
|
|
_RAND_335 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_23 = _RAND_335[0:0];
|
|
_RAND_336 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_24 = _RAND_336[0:0];
|
|
_RAND_337 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_25 = _RAND_337[0:0];
|
|
_RAND_338 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_26 = _RAND_338[0:0];
|
|
_RAND_339 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_27 = _RAND_339[0:0];
|
|
_RAND_340 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_28 = _RAND_340[0:0];
|
|
_RAND_341 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_29 = _RAND_341[0:0];
|
|
_RAND_342 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_30 = _RAND_342[0:0];
|
|
_RAND_343 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_31 = _RAND_343[0:0];
|
|
_RAND_344 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_32 = _RAND_344[0:0];
|
|
_RAND_345 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_33 = _RAND_345[0:0];
|
|
_RAND_346 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_34 = _RAND_346[0:0];
|
|
_RAND_347 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_35 = _RAND_347[0:0];
|
|
_RAND_348 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_36 = _RAND_348[0:0];
|
|
_RAND_349 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_37 = _RAND_349[0:0];
|
|
_RAND_350 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_38 = _RAND_350[0:0];
|
|
_RAND_351 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_39 = _RAND_351[0:0];
|
|
_RAND_352 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_40 = _RAND_352[0:0];
|
|
_RAND_353 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_41 = _RAND_353[0:0];
|
|
_RAND_354 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_42 = _RAND_354[0:0];
|
|
_RAND_355 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_43 = _RAND_355[0:0];
|
|
_RAND_356 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_44 = _RAND_356[0:0];
|
|
_RAND_357 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_45 = _RAND_357[0:0];
|
|
_RAND_358 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_46 = _RAND_358[0:0];
|
|
_RAND_359 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_47 = _RAND_359[0:0];
|
|
_RAND_360 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_48 = _RAND_360[0:0];
|
|
_RAND_361 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_49 = _RAND_361[0:0];
|
|
_RAND_362 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_50 = _RAND_362[0:0];
|
|
_RAND_363 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_51 = _RAND_363[0:0];
|
|
_RAND_364 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_52 = _RAND_364[0:0];
|
|
_RAND_365 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_53 = _RAND_365[0:0];
|
|
_RAND_366 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_54 = _RAND_366[0:0];
|
|
_RAND_367 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_55 = _RAND_367[0:0];
|
|
_RAND_368 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_56 = _RAND_368[0:0];
|
|
_RAND_369 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_57 = _RAND_369[0:0];
|
|
_RAND_370 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_58 = _RAND_370[0:0];
|
|
_RAND_371 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_59 = _RAND_371[0:0];
|
|
_RAND_372 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_60 = _RAND_372[0:0];
|
|
_RAND_373 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_61 = _RAND_373[0:0];
|
|
_RAND_374 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_62 = _RAND_374[0:0];
|
|
_RAND_375 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_63 = _RAND_375[0:0];
|
|
_RAND_376 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_64 = _RAND_376[0:0];
|
|
_RAND_377 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_65 = _RAND_377[0:0];
|
|
_RAND_378 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_66 = _RAND_378[0:0];
|
|
_RAND_379 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_67 = _RAND_379[0:0];
|
|
_RAND_380 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_68 = _RAND_380[0:0];
|
|
_RAND_381 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_69 = _RAND_381[0:0];
|
|
_RAND_382 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_70 = _RAND_382[0:0];
|
|
_RAND_383 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_71 = _RAND_383[0:0];
|
|
_RAND_384 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_72 = _RAND_384[0:0];
|
|
_RAND_385 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_73 = _RAND_385[0:0];
|
|
_RAND_386 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_74 = _RAND_386[0:0];
|
|
_RAND_387 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_75 = _RAND_387[0:0];
|
|
_RAND_388 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_76 = _RAND_388[0:0];
|
|
_RAND_389 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_77 = _RAND_389[0:0];
|
|
_RAND_390 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_78 = _RAND_390[0:0];
|
|
_RAND_391 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_79 = _RAND_391[0:0];
|
|
_RAND_392 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_80 = _RAND_392[0:0];
|
|
_RAND_393 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_81 = _RAND_393[0:0];
|
|
_RAND_394 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_82 = _RAND_394[0:0];
|
|
_RAND_395 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_83 = _RAND_395[0:0];
|
|
_RAND_396 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_84 = _RAND_396[0:0];
|
|
_RAND_397 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_85 = _RAND_397[0:0];
|
|
_RAND_398 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_86 = _RAND_398[0:0];
|
|
_RAND_399 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_87 = _RAND_399[0:0];
|
|
_RAND_400 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_88 = _RAND_400[0:0];
|
|
_RAND_401 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_89 = _RAND_401[0:0];
|
|
_RAND_402 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_90 = _RAND_402[0:0];
|
|
_RAND_403 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_91 = _RAND_403[0:0];
|
|
_RAND_404 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_92 = _RAND_404[0:0];
|
|
_RAND_405 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_93 = _RAND_405[0:0];
|
|
_RAND_406 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_94 = _RAND_406[0:0];
|
|
_RAND_407 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_95 = _RAND_407[0:0];
|
|
_RAND_408 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_96 = _RAND_408[0:0];
|
|
_RAND_409 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_97 = _RAND_409[0:0];
|
|
_RAND_410 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_98 = _RAND_410[0:0];
|
|
_RAND_411 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_99 = _RAND_411[0:0];
|
|
_RAND_412 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_100 = _RAND_412[0:0];
|
|
_RAND_413 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_101 = _RAND_413[0:0];
|
|
_RAND_414 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_102 = _RAND_414[0:0];
|
|
_RAND_415 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_103 = _RAND_415[0:0];
|
|
_RAND_416 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_104 = _RAND_416[0:0];
|
|
_RAND_417 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_105 = _RAND_417[0:0];
|
|
_RAND_418 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_106 = _RAND_418[0:0];
|
|
_RAND_419 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_107 = _RAND_419[0:0];
|
|
_RAND_420 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_108 = _RAND_420[0:0];
|
|
_RAND_421 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_109 = _RAND_421[0:0];
|
|
_RAND_422 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_110 = _RAND_422[0:0];
|
|
_RAND_423 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_111 = _RAND_423[0:0];
|
|
_RAND_424 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_112 = _RAND_424[0:0];
|
|
_RAND_425 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_113 = _RAND_425[0:0];
|
|
_RAND_426 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_114 = _RAND_426[0:0];
|
|
_RAND_427 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_115 = _RAND_427[0:0];
|
|
_RAND_428 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_116 = _RAND_428[0:0];
|
|
_RAND_429 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_117 = _RAND_429[0:0];
|
|
_RAND_430 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_118 = _RAND_430[0:0];
|
|
_RAND_431 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_119 = _RAND_431[0:0];
|
|
_RAND_432 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_120 = _RAND_432[0:0];
|
|
_RAND_433 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_121 = _RAND_433[0:0];
|
|
_RAND_434 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_122 = _RAND_434[0:0];
|
|
_RAND_435 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_123 = _RAND_435[0:0];
|
|
_RAND_436 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_124 = _RAND_436[0:0];
|
|
_RAND_437 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_125 = _RAND_437[0:0];
|
|
_RAND_438 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_126 = _RAND_438[0:0];
|
|
_RAND_439 = {1{`RANDOM}};
|
|
ic_tag_valid_out_0_127 = _RAND_439[0:0];
|
|
_RAND_440 = {1{`RANDOM}};
|
|
ic_debug_way_ff = _RAND_440[1:0];
|
|
_RAND_441 = {1{`RANDOM}};
|
|
ic_debug_rd_en_ff = _RAND_441[0:0];
|
|
_RAND_442 = {3{`RANDOM}};
|
|
_T_1237 = _RAND_442[70:0];
|
|
_RAND_443 = {1{`RANDOM}};
|
|
ifc_region_acc_fault_memory_f = _RAND_443[0:0];
|
|
_RAND_444 = {1{`RANDOM}};
|
|
perr_ic_index_ff = _RAND_444[6:0];
|
|
_RAND_445 = {1{`RANDOM}};
|
|
dma_sb_err_state_ff = _RAND_445[0:0];
|
|
_RAND_446 = {1{`RANDOM}};
|
|
bus_cmd_req_hold = _RAND_446[0:0];
|
|
_RAND_447 = {1{`RANDOM}};
|
|
ifu_bus_cmd_valid = _RAND_447[0:0];
|
|
_RAND_448 = {1{`RANDOM}};
|
|
bus_cmd_beat_count = _RAND_448[2:0];
|
|
_RAND_449 = {1{`RANDOM}};
|
|
ifu_bus_arready_unq_ff = _RAND_449[0:0];
|
|
_RAND_450 = {1{`RANDOM}};
|
|
ifu_bus_arvalid_ff = _RAND_450[0:0];
|
|
_RAND_451 = {1{`RANDOM}};
|
|
ifc_dma_access_ok_prev = _RAND_451[0:0];
|
|
_RAND_452 = {2{`RANDOM}};
|
|
iccm_ecc_corr_data_ff = _RAND_452[38:0];
|
|
_RAND_453 = {1{`RANDOM}};
|
|
dma_mem_addr_ff = _RAND_453[1:0];
|
|
_RAND_454 = {1{`RANDOM}};
|
|
dma_mem_tag_ff = _RAND_454[2:0];
|
|
_RAND_455 = {1{`RANDOM}};
|
|
iccm_dma_rtag_temp = _RAND_455[2:0];
|
|
_RAND_456 = {1{`RANDOM}};
|
|
iccm_dma_rvalid_temp = _RAND_456[0:0];
|
|
_RAND_457 = {1{`RANDOM}};
|
|
iccm_dma_ecc_error = _RAND_457[0:0];
|
|
_RAND_458 = {2{`RANDOM}};
|
|
iccm_dma_rdata_temp = _RAND_458[63:0];
|
|
_RAND_459 = {1{`RANDOM}};
|
|
iccm_ecc_corr_index_ff = _RAND_459[13:0];
|
|
_RAND_460 = {1{`RANDOM}};
|
|
iccm_rd_ecc_single_err_ff = _RAND_460[0:0];
|
|
_RAND_461 = {1{`RANDOM}};
|
|
iccm_rw_addr_f = _RAND_461[13:0];
|
|
_RAND_462 = {1{`RANDOM}};
|
|
ifu_status_wr_addr_ff = _RAND_462[6:0];
|
|
_RAND_463 = {1{`RANDOM}};
|
|
way_status_wr_en_ff = _RAND_463[0:0];
|
|
_RAND_464 = {1{`RANDOM}};
|
|
way_status_new_ff = _RAND_464[0:0];
|
|
_RAND_465 = {1{`RANDOM}};
|
|
ifu_tag_wren_ff = _RAND_465[1:0];
|
|
_RAND_466 = {1{`RANDOM}};
|
|
ic_valid_ff = _RAND_466[0:0];
|
|
_RAND_467 = {1{`RANDOM}};
|
|
_T_10552 = _RAND_467[0:0];
|
|
_RAND_468 = {1{`RANDOM}};
|
|
_T_10556 = _RAND_468[0:0];
|
|
_RAND_469 = {1{`RANDOM}};
|
|
_T_10561 = _RAND_469[0:0];
|
|
_RAND_470 = {1{`RANDOM}};
|
|
_T_10568 = _RAND_470[0:0];
|
|
_RAND_471 = {1{`RANDOM}};
|
|
_T_10572 = _RAND_471[0:0];
|
|
_RAND_472 = {1{`RANDOM}};
|
|
_T_10598 = _RAND_472[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
flush_final_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_fetch_req_f_raw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_state = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
scnd_miss_req_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_fetch_addr_int_f = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_iccm_access_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rvalid_in = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_iccm_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
perr_state = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
err_stop_state = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_all_tags = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_region_acc_fault_final_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rvalid_unq_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_ifu_bus_clk_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
uncacheable_miss_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_data_beat_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_valid = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
imb_ff = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
last_data_recieved_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
sel_mb_addr_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_mb_scnd_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_ic_rw_int_addr_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_out_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tagv_mb_scnd_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
uncacheable_miss_scnd_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
imb_scnd_ff = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rid_ff = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rresp_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_wr_data_comb_err_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_mb_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tagv_mb_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_ic_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fetch_uncacheable_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_addr = 26'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_region_acc_fault_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_rd_addr_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_act_miss_f_delayed = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_rdata_ff = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_7 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_8 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_9 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_10 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_11 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_12 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_13 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_14 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_15 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_crit_wd_rdy_new_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_miss_buff_data_error = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_ict_array_sel_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_91 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_92 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_93 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_95 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_96 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_97 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_99 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_100 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_120 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_way_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_debug_rd_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1237 = 71'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_region_acc_fault_memory_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
perr_ic_index_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_sb_err_state_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_cmd_req_hold = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_cmd_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_cmd_beat_count = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_arready_unq_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_bus_arvalid_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_dma_access_ok_prev = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_ecc_corr_data_ff = 39'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_mem_addr_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_mem_tag_ff = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rtag_temp = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rvalid_temp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_ecc_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_dma_rdata_temp = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_ecc_corr_index_ff = 14'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_rd_ecc_single_err_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_rw_addr_f = 14'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_status_wr_addr_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_wr_en_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
way_status_new_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_tag_wren_ff = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ic_valid_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10552 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10556 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10561 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10568 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10572 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10598 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
flush_final_f <= 1'h0;
|
|
end else if (_T_1) begin
|
|
flush_final_f <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_fetch_req_f_raw <= 1'h0;
|
|
end else if (_T_337) begin
|
|
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
miss_state <= 3'h0;
|
|
end else if (miss_state_en) begin
|
|
if (_T_27) begin
|
|
if (_T_29) begin
|
|
miss_state <= 3'h1;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else if (_T_34) begin
|
|
if (_T_39) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_43) begin
|
|
miss_state <= 3'h3;
|
|
end else if (_T_50) begin
|
|
miss_state <= 3'h4;
|
|
end else if (_T_54) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_64) begin
|
|
miss_state <= 3'h6;
|
|
end else if (_T_74) begin
|
|
miss_state <= 3'h6;
|
|
end else if (_T_82) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_87) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_105) begin
|
|
miss_state <= 3'h0;
|
|
end else if (_T_109) begin
|
|
if (_T_116) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_124) begin
|
|
if (_T_129) begin
|
|
miss_state <= 3'h2;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_135) begin
|
|
if (_T_140) begin
|
|
miss_state <= 3'h5;
|
|
end else if (_T_146) begin
|
|
miss_state <= 3'h7;
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else if (_T_154) begin
|
|
if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
|
|
miss_state <= 3'h0;
|
|
end else if (io_exu_flush_final) begin
|
|
if (_T_35) begin
|
|
miss_state <= 3'h0;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h1;
|
|
end
|
|
end else if (_T_163) begin
|
|
if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
|
|
miss_state <= 3'h0;
|
|
end else if (io_exu_flush_final) begin
|
|
if (_T_35) begin
|
|
miss_state <= 3'h0;
|
|
end else begin
|
|
miss_state <= 3'h2;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end else begin
|
|
miss_state <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
scnd_miss_req_q <= 1'h0;
|
|
end else if (_T_2613) begin
|
|
scnd_miss_req_q <= scnd_miss_req_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_fetch_addr_int_f <= 31'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
ifu_fetch_addr_int_f <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_iccm_access_f <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
ifc_iccm_access_f <= io_ifc_iccm_access_bf;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rvalid_in <= 1'h0;
|
|
end else if (_T_3169) begin
|
|
iccm_dma_rvalid_in <= _T_2764;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_iccm_req_f <= 1'h0;
|
|
end else if (_T_2757) begin
|
|
dma_iccm_req_f <= io_dma_mem_ctl_dma_iccm_req;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
perr_state <= 3'h0;
|
|
end else if (perr_state_en) begin
|
|
if (_T_2521) begin
|
|
if (io_iccm_dma_sb_error) begin
|
|
perr_state <= 3'h4;
|
|
end else if (_T_2523) begin
|
|
perr_state <= 3'h1;
|
|
end else begin
|
|
perr_state <= 3'h2;
|
|
end
|
|
end else if (_T_2533) begin
|
|
perr_state <= 3'h0;
|
|
end else if (_T_2536) begin
|
|
if (_T_2539) begin
|
|
perr_state <= 3'h0;
|
|
end else begin
|
|
perr_state <= 3'h3;
|
|
end
|
|
end else if (_T_2543) begin
|
|
if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
|
|
perr_state <= 3'h0;
|
|
end else begin
|
|
perr_state <= 3'h3;
|
|
end
|
|
end else begin
|
|
perr_state <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (err_stop_state_en) begin
|
|
if (_T_2547) begin
|
|
err_stop_state <= 2'h1;
|
|
end else if (_T_2552) begin
|
|
if (_T_2554) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (_T_2575) begin
|
|
err_stop_state <= 2'h3;
|
|
end else if (io_ifu_fetch_val[0]) begin
|
|
err_stop_state <= 2'h2;
|
|
end else begin
|
|
err_stop_state <= 2'h1;
|
|
end
|
|
end else if (_T_2579) begin
|
|
if (_T_2554) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (io_ifu_fetch_val[0]) begin
|
|
err_stop_state <= 2'h3;
|
|
end else begin
|
|
err_stop_state <= 2'h2;
|
|
end
|
|
end else if (_T_2596) begin
|
|
if (_T_2600) begin
|
|
err_stop_state <= 2'h0;
|
|
end else if (io_dec_mem_ctrl_dec_tlu_flush_err_wb) begin
|
|
err_stop_state <= 2'h1;
|
|
end else begin
|
|
err_stop_state <= 2'h3;
|
|
end
|
|
end else begin
|
|
err_stop_state <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_all_tags <= 1'h0;
|
|
end else if (_T_4081) begin
|
|
reset_all_tags <= io_dec_mem_ctrl_dec_tlu_fence_i_wb;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_region_acc_fault_final_f <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
ifc_region_acc_fault_final_f <= ifc_region_acc_fault_final_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rvalid_unq_ff <= 1'h0;
|
|
end else if (io_ifu_bus_clk_en) begin
|
|
ifu_bus_rvalid_unq_ff <= io_ifu_axi_r_valid;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_ifu_bus_clk_en_ff <= 1'h0;
|
|
end else if (_T_2609) begin
|
|
bus_ifu_bus_clk_en_ff <= io_ifu_bus_clk_en;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
uncacheable_miss_ff <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (scnd_miss_req) begin
|
|
uncacheable_miss_ff <= uncacheable_miss_scnd_ff;
|
|
end else if (!(sel_hold_imb)) begin
|
|
uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_data_beat_count <= 3'h0;
|
|
end else if (_T_2668) begin
|
|
bus_data_beat_count <= bus_new_data_beat_count;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_valid <= 8'h0;
|
|
end else begin
|
|
ic_miss_buff_data_valid <= {_T_1390,ic_miss_buff_data_valid_in_0};
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
imb_ff <= 31'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (scnd_miss_req) begin
|
|
imb_ff <= imb_scnd_ff;
|
|
end else if (!(sel_hold_imb)) begin
|
|
imb_ff <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
last_data_recieved_ff <= 1'h0;
|
|
end else if (_T_2677) begin
|
|
last_data_recieved_ff <= last_data_recieved_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
sel_mb_addr_ff <= 1'h0;
|
|
end else if (_T_375) begin
|
|
sel_mb_addr_ff <= sel_mb_addr;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_mb_scnd_ff <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (!(_T_22)) begin
|
|
way_status_mb_scnd_ff <= way_status;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_ic_rw_int_addr_ff <= 7'h0;
|
|
end else if (_T_5290) begin
|
|
if (_T_4089) begin
|
|
ifu_ic_rw_int_addr_ff <= io_ic_debug_addr[9:3];
|
|
end else begin
|
|
ifu_ic_rw_int_addr_ff <= io_ic_rw_addr[11:5];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_0 <= 1'h0;
|
|
end else if (_T_4123) begin
|
|
way_status_out_0 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_1 <= 1'h0;
|
|
end else if (_T_4128) begin
|
|
way_status_out_1 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_2 <= 1'h0;
|
|
end else if (_T_4133) begin
|
|
way_status_out_2 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_3 <= 1'h0;
|
|
end else if (_T_4138) begin
|
|
way_status_out_3 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_4 <= 1'h0;
|
|
end else if (_T_4143) begin
|
|
way_status_out_4 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_5 <= 1'h0;
|
|
end else if (_T_4148) begin
|
|
way_status_out_5 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_6 <= 1'h0;
|
|
end else if (_T_4153) begin
|
|
way_status_out_6 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_7 <= 1'h0;
|
|
end else if (_T_4158) begin
|
|
way_status_out_7 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_8 <= 1'h0;
|
|
end else if (_T_4163) begin
|
|
way_status_out_8 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_9 <= 1'h0;
|
|
end else if (_T_4168) begin
|
|
way_status_out_9 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_10 <= 1'h0;
|
|
end else if (_T_4173) begin
|
|
way_status_out_10 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_11 <= 1'h0;
|
|
end else if (_T_4178) begin
|
|
way_status_out_11 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_12 <= 1'h0;
|
|
end else if (_T_4183) begin
|
|
way_status_out_12 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_13 <= 1'h0;
|
|
end else if (_T_4188) begin
|
|
way_status_out_13 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_14 <= 1'h0;
|
|
end else if (_T_4193) begin
|
|
way_status_out_14 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_15 <= 1'h0;
|
|
end else if (_T_4198) begin
|
|
way_status_out_15 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_16 <= 1'h0;
|
|
end else if (_T_4203) begin
|
|
way_status_out_16 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_17 <= 1'h0;
|
|
end else if (_T_4208) begin
|
|
way_status_out_17 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_18 <= 1'h0;
|
|
end else if (_T_4213) begin
|
|
way_status_out_18 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_19 <= 1'h0;
|
|
end else if (_T_4218) begin
|
|
way_status_out_19 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_20 <= 1'h0;
|
|
end else if (_T_4223) begin
|
|
way_status_out_20 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_21 <= 1'h0;
|
|
end else if (_T_4228) begin
|
|
way_status_out_21 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_22 <= 1'h0;
|
|
end else if (_T_4233) begin
|
|
way_status_out_22 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_23 <= 1'h0;
|
|
end else if (_T_4238) begin
|
|
way_status_out_23 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_24 <= 1'h0;
|
|
end else if (_T_4243) begin
|
|
way_status_out_24 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_25 <= 1'h0;
|
|
end else if (_T_4248) begin
|
|
way_status_out_25 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_26 <= 1'h0;
|
|
end else if (_T_4253) begin
|
|
way_status_out_26 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_27 <= 1'h0;
|
|
end else if (_T_4258) begin
|
|
way_status_out_27 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_28 <= 1'h0;
|
|
end else if (_T_4263) begin
|
|
way_status_out_28 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_29 <= 1'h0;
|
|
end else if (_T_4268) begin
|
|
way_status_out_29 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_30 <= 1'h0;
|
|
end else if (_T_4273) begin
|
|
way_status_out_30 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_31 <= 1'h0;
|
|
end else if (_T_4278) begin
|
|
way_status_out_31 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_32 <= 1'h0;
|
|
end else if (_T_4283) begin
|
|
way_status_out_32 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_33 <= 1'h0;
|
|
end else if (_T_4288) begin
|
|
way_status_out_33 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_34 <= 1'h0;
|
|
end else if (_T_4293) begin
|
|
way_status_out_34 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_35 <= 1'h0;
|
|
end else if (_T_4298) begin
|
|
way_status_out_35 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_36 <= 1'h0;
|
|
end else if (_T_4303) begin
|
|
way_status_out_36 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_37 <= 1'h0;
|
|
end else if (_T_4308) begin
|
|
way_status_out_37 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_38 <= 1'h0;
|
|
end else if (_T_4313) begin
|
|
way_status_out_38 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_39 <= 1'h0;
|
|
end else if (_T_4318) begin
|
|
way_status_out_39 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_40 <= 1'h0;
|
|
end else if (_T_4323) begin
|
|
way_status_out_40 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_41 <= 1'h0;
|
|
end else if (_T_4328) begin
|
|
way_status_out_41 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_42 <= 1'h0;
|
|
end else if (_T_4333) begin
|
|
way_status_out_42 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_43 <= 1'h0;
|
|
end else if (_T_4338) begin
|
|
way_status_out_43 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_44 <= 1'h0;
|
|
end else if (_T_4343) begin
|
|
way_status_out_44 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_45 <= 1'h0;
|
|
end else if (_T_4348) begin
|
|
way_status_out_45 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_46 <= 1'h0;
|
|
end else if (_T_4353) begin
|
|
way_status_out_46 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_47 <= 1'h0;
|
|
end else if (_T_4358) begin
|
|
way_status_out_47 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_48 <= 1'h0;
|
|
end else if (_T_4363) begin
|
|
way_status_out_48 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_49 <= 1'h0;
|
|
end else if (_T_4368) begin
|
|
way_status_out_49 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_50 <= 1'h0;
|
|
end else if (_T_4373) begin
|
|
way_status_out_50 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_51 <= 1'h0;
|
|
end else if (_T_4378) begin
|
|
way_status_out_51 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_52 <= 1'h0;
|
|
end else if (_T_4383) begin
|
|
way_status_out_52 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_53 <= 1'h0;
|
|
end else if (_T_4388) begin
|
|
way_status_out_53 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_54 <= 1'h0;
|
|
end else if (_T_4393) begin
|
|
way_status_out_54 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_55 <= 1'h0;
|
|
end else if (_T_4398) begin
|
|
way_status_out_55 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_56 <= 1'h0;
|
|
end else if (_T_4403) begin
|
|
way_status_out_56 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_57 <= 1'h0;
|
|
end else if (_T_4408) begin
|
|
way_status_out_57 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_58 <= 1'h0;
|
|
end else if (_T_4413) begin
|
|
way_status_out_58 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_59 <= 1'h0;
|
|
end else if (_T_4418) begin
|
|
way_status_out_59 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_60 <= 1'h0;
|
|
end else if (_T_4423) begin
|
|
way_status_out_60 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_61 <= 1'h0;
|
|
end else if (_T_4428) begin
|
|
way_status_out_61 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_62 <= 1'h0;
|
|
end else if (_T_4433) begin
|
|
way_status_out_62 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_63 <= 1'h0;
|
|
end else if (_T_4438) begin
|
|
way_status_out_63 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_64 <= 1'h0;
|
|
end else if (_T_4443) begin
|
|
way_status_out_64 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_65 <= 1'h0;
|
|
end else if (_T_4448) begin
|
|
way_status_out_65 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_66 <= 1'h0;
|
|
end else if (_T_4453) begin
|
|
way_status_out_66 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_67 <= 1'h0;
|
|
end else if (_T_4458) begin
|
|
way_status_out_67 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_68 <= 1'h0;
|
|
end else if (_T_4463) begin
|
|
way_status_out_68 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_69 <= 1'h0;
|
|
end else if (_T_4468) begin
|
|
way_status_out_69 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_70 <= 1'h0;
|
|
end else if (_T_4473) begin
|
|
way_status_out_70 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_71 <= 1'h0;
|
|
end else if (_T_4478) begin
|
|
way_status_out_71 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_72 <= 1'h0;
|
|
end else if (_T_4483) begin
|
|
way_status_out_72 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_73 <= 1'h0;
|
|
end else if (_T_4488) begin
|
|
way_status_out_73 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_74 <= 1'h0;
|
|
end else if (_T_4493) begin
|
|
way_status_out_74 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_75 <= 1'h0;
|
|
end else if (_T_4498) begin
|
|
way_status_out_75 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_76 <= 1'h0;
|
|
end else if (_T_4503) begin
|
|
way_status_out_76 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_77 <= 1'h0;
|
|
end else if (_T_4508) begin
|
|
way_status_out_77 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_78 <= 1'h0;
|
|
end else if (_T_4513) begin
|
|
way_status_out_78 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_79 <= 1'h0;
|
|
end else if (_T_4518) begin
|
|
way_status_out_79 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_80 <= 1'h0;
|
|
end else if (_T_4523) begin
|
|
way_status_out_80 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_81 <= 1'h0;
|
|
end else if (_T_4528) begin
|
|
way_status_out_81 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_82 <= 1'h0;
|
|
end else if (_T_4533) begin
|
|
way_status_out_82 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_83 <= 1'h0;
|
|
end else if (_T_4538) begin
|
|
way_status_out_83 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_84 <= 1'h0;
|
|
end else if (_T_4543) begin
|
|
way_status_out_84 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_85 <= 1'h0;
|
|
end else if (_T_4548) begin
|
|
way_status_out_85 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_86 <= 1'h0;
|
|
end else if (_T_4553) begin
|
|
way_status_out_86 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_87 <= 1'h0;
|
|
end else if (_T_4558) begin
|
|
way_status_out_87 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_88 <= 1'h0;
|
|
end else if (_T_4563) begin
|
|
way_status_out_88 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_89 <= 1'h0;
|
|
end else if (_T_4568) begin
|
|
way_status_out_89 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_90 <= 1'h0;
|
|
end else if (_T_4573) begin
|
|
way_status_out_90 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_91 <= 1'h0;
|
|
end else if (_T_4578) begin
|
|
way_status_out_91 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_92 <= 1'h0;
|
|
end else if (_T_4583) begin
|
|
way_status_out_92 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_93 <= 1'h0;
|
|
end else if (_T_4588) begin
|
|
way_status_out_93 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_94 <= 1'h0;
|
|
end else if (_T_4593) begin
|
|
way_status_out_94 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_95 <= 1'h0;
|
|
end else if (_T_4598) begin
|
|
way_status_out_95 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_96 <= 1'h0;
|
|
end else if (_T_4603) begin
|
|
way_status_out_96 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_97 <= 1'h0;
|
|
end else if (_T_4608) begin
|
|
way_status_out_97 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_98 <= 1'h0;
|
|
end else if (_T_4613) begin
|
|
way_status_out_98 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_99 <= 1'h0;
|
|
end else if (_T_4618) begin
|
|
way_status_out_99 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_100 <= 1'h0;
|
|
end else if (_T_4623) begin
|
|
way_status_out_100 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_101 <= 1'h0;
|
|
end else if (_T_4628) begin
|
|
way_status_out_101 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_102 <= 1'h0;
|
|
end else if (_T_4633) begin
|
|
way_status_out_102 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_103 <= 1'h0;
|
|
end else if (_T_4638) begin
|
|
way_status_out_103 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_104 <= 1'h0;
|
|
end else if (_T_4643) begin
|
|
way_status_out_104 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_105 <= 1'h0;
|
|
end else if (_T_4648) begin
|
|
way_status_out_105 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_106 <= 1'h0;
|
|
end else if (_T_4653) begin
|
|
way_status_out_106 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_107 <= 1'h0;
|
|
end else if (_T_4658) begin
|
|
way_status_out_107 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_108 <= 1'h0;
|
|
end else if (_T_4663) begin
|
|
way_status_out_108 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_109 <= 1'h0;
|
|
end else if (_T_4668) begin
|
|
way_status_out_109 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_110 <= 1'h0;
|
|
end else if (_T_4673) begin
|
|
way_status_out_110 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_111 <= 1'h0;
|
|
end else if (_T_4678) begin
|
|
way_status_out_111 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_112 <= 1'h0;
|
|
end else if (_T_4683) begin
|
|
way_status_out_112 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_113 <= 1'h0;
|
|
end else if (_T_4688) begin
|
|
way_status_out_113 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_114 <= 1'h0;
|
|
end else if (_T_4693) begin
|
|
way_status_out_114 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_115 <= 1'h0;
|
|
end else if (_T_4698) begin
|
|
way_status_out_115 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_116 <= 1'h0;
|
|
end else if (_T_4703) begin
|
|
way_status_out_116 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_117 <= 1'h0;
|
|
end else if (_T_4708) begin
|
|
way_status_out_117 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_118 <= 1'h0;
|
|
end else if (_T_4713) begin
|
|
way_status_out_118 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_119 <= 1'h0;
|
|
end else if (_T_4718) begin
|
|
way_status_out_119 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_120 <= 1'h0;
|
|
end else if (_T_4723) begin
|
|
way_status_out_120 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_121 <= 1'h0;
|
|
end else if (_T_4728) begin
|
|
way_status_out_121 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_122 <= 1'h0;
|
|
end else if (_T_4733) begin
|
|
way_status_out_122 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_123 <= 1'h0;
|
|
end else if (_T_4738) begin
|
|
way_status_out_123 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_124 <= 1'h0;
|
|
end else if (_T_4743) begin
|
|
way_status_out_124 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_125 <= 1'h0;
|
|
end else if (_T_4748) begin
|
|
way_status_out_125 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_126 <= 1'h0;
|
|
end else if (_T_4753) begin
|
|
way_status_out_126 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_out_127 <= 1'h0;
|
|
end else if (_T_4758) begin
|
|
way_status_out_127 <= way_status_new_ff;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
tagv_mb_scnd_ff <= 2'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (!(_T_22)) begin
|
|
tagv_mb_scnd_ff <= _T_203;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
uncacheable_miss_scnd_ff <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (!(sel_hold_imb_scnd)) begin
|
|
uncacheable_miss_scnd_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
imb_scnd_ff <= 31'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (!(sel_hold_imb_scnd)) begin
|
|
imb_scnd_ff <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rid_ff <= 3'h0;
|
|
end else if (io_ifu_bus_clk_en) begin
|
|
ifu_bus_rid_ff <= io_ifu_axi_r_bits_id;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rresp_ff <= 2'h0;
|
|
end else if (io_ifu_bus_clk_en) begin
|
|
ifu_bus_rresp_ff <= io_ifu_axi_r_bits_resp;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_wr_data_comb_err_ff <= 1'h0;
|
|
end else if (_T_1272) begin
|
|
ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_mb_ff <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (_T_284) begin
|
|
way_status_mb_ff <= way_status_mb_scnd_ff;
|
|
end else if (_T_286) begin
|
|
way_status_mb_ff <= replace_way_mb_any_0;
|
|
end else if (!(miss_pending)) begin
|
|
way_status_mb_ff <= way_status;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
tagv_mb_ff <= 2'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
if (scnd_miss_req) begin
|
|
tagv_mb_ff <= _T_296;
|
|
end else if (!(miss_pending)) begin
|
|
tagv_mb_ff <= _T_303;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_ic_ff <= 1'h0;
|
|
end else if (_T_310) begin
|
|
reset_ic_ff <= reset_ic_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
fetch_uncacheable_ff <= 1'h0;
|
|
end else if (_T_313) begin
|
|
fetch_uncacheable_ff <= io_ifc_fetch_uncacheable_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
miss_addr <= 26'h0;
|
|
end else if (_T_326) begin
|
|
if (_T_237) begin
|
|
miss_addr <= imb_ff[30:5];
|
|
end else if (scnd_miss_req_q) begin
|
|
miss_addr <= imb_scnd_ff[30:5];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_region_acc_fault_f <= 1'h0;
|
|
end else if (fetch_bf_f_c1_clken) begin
|
|
ifc_region_acc_fault_f <= io_ifc_region_acc_fault_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bus_rd_addr_count <= 3'h0;
|
|
end else if (_T_326) begin
|
|
if (_T_237) begin
|
|
bus_rd_addr_count <= imb_ff[4:2];
|
|
end else if (scnd_miss_req_q) begin
|
|
bus_rd_addr_count <= imb_scnd_ff[4:2];
|
|
end else if (bus_cmd_sent) begin
|
|
bus_rd_addr_count <= _T_2683;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_act_miss_f_delayed <= 1'h0;
|
|
end else if (_T_2728) begin
|
|
ic_act_miss_f_delayed <= ic_act_miss_f;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_rdata_ff <= 64'h0;
|
|
end else if (_T_377) begin
|
|
ifu_bus_rdata_ff <= io_ifu_axi_r_bits_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_0 <= 32'h0;
|
|
end else if (write_fill_data_0) begin
|
|
ic_miss_buff_data_0 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_1 <= 32'h0;
|
|
end else if (write_fill_data_0) begin
|
|
ic_miss_buff_data_1 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_2 <= 32'h0;
|
|
end else if (write_fill_data_1) begin
|
|
ic_miss_buff_data_2 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_3 <= 32'h0;
|
|
end else if (write_fill_data_1) begin
|
|
ic_miss_buff_data_3 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_4 <= 32'h0;
|
|
end else if (write_fill_data_2) begin
|
|
ic_miss_buff_data_4 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_5 <= 32'h0;
|
|
end else if (write_fill_data_2) begin
|
|
ic_miss_buff_data_5 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_6 <= 32'h0;
|
|
end else if (write_fill_data_3) begin
|
|
ic_miss_buff_data_6 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_7 <= 32'h0;
|
|
end else if (write_fill_data_3) begin
|
|
ic_miss_buff_data_7 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_8 <= 32'h0;
|
|
end else if (write_fill_data_4) begin
|
|
ic_miss_buff_data_8 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_9 <= 32'h0;
|
|
end else if (write_fill_data_4) begin
|
|
ic_miss_buff_data_9 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_10 <= 32'h0;
|
|
end else if (write_fill_data_5) begin
|
|
ic_miss_buff_data_10 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_11 <= 32'h0;
|
|
end else if (write_fill_data_5) begin
|
|
ic_miss_buff_data_11 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_12 <= 32'h0;
|
|
end else if (write_fill_data_6) begin
|
|
ic_miss_buff_data_12 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_13 <= 32'h0;
|
|
end else if (write_fill_data_6) begin
|
|
ic_miss_buff_data_13 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_14 <= 32'h0;
|
|
end else if (write_fill_data_7) begin
|
|
ic_miss_buff_data_14 <= io_ifu_axi_r_bits_data[31:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_15 <= 32'h0;
|
|
end else if (write_fill_data_7) begin
|
|
ic_miss_buff_data_15 <= io_ifu_axi_r_bits_data[63:32];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_crit_wd_rdy_new_ff <= 1'h0;
|
|
end else if (_T_1554) begin
|
|
ic_crit_wd_rdy_new_ff <= ic_crit_wd_rdy_new_in;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_miss_buff_data_error <= 8'h0;
|
|
end else begin
|
|
ic_miss_buff_data_error <= {_T_1430,ic_miss_buff_data_error_in_0};
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_ict_array_sel_ff <= 1'h0;
|
|
end else if (debug_c1_clken) begin
|
|
ic_debug_ict_array_sel_ff <= ic_debug_ict_array_sel_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_0 <= 1'h0;
|
|
end else if (_T_5947) begin
|
|
ic_tag_valid_out_1_0 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_1 <= 1'h0;
|
|
end else if (_T_5964) begin
|
|
ic_tag_valid_out_1_1 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_2 <= 1'h0;
|
|
end else if (_T_5981) begin
|
|
ic_tag_valid_out_1_2 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_3 <= 1'h0;
|
|
end else if (_T_5998) begin
|
|
ic_tag_valid_out_1_3 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_4 <= 1'h0;
|
|
end else if (_T_6015) begin
|
|
ic_tag_valid_out_1_4 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_5 <= 1'h0;
|
|
end else if (_T_6032) begin
|
|
ic_tag_valid_out_1_5 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_6 <= 1'h0;
|
|
end else if (_T_6049) begin
|
|
ic_tag_valid_out_1_6 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_7 <= 1'h0;
|
|
end else if (_T_6066) begin
|
|
ic_tag_valid_out_1_7 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_8 <= 1'h0;
|
|
end else if (_T_6083) begin
|
|
ic_tag_valid_out_1_8 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_9 <= 1'h0;
|
|
end else if (_T_6100) begin
|
|
ic_tag_valid_out_1_9 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_10 <= 1'h0;
|
|
end else if (_T_6117) begin
|
|
ic_tag_valid_out_1_10 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_11 <= 1'h0;
|
|
end else if (_T_6134) begin
|
|
ic_tag_valid_out_1_11 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_12 <= 1'h0;
|
|
end else if (_T_6151) begin
|
|
ic_tag_valid_out_1_12 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_13 <= 1'h0;
|
|
end else if (_T_6168) begin
|
|
ic_tag_valid_out_1_13 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_14 <= 1'h0;
|
|
end else if (_T_6185) begin
|
|
ic_tag_valid_out_1_14 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_15 <= 1'h0;
|
|
end else if (_T_6202) begin
|
|
ic_tag_valid_out_1_15 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_16 <= 1'h0;
|
|
end else if (_T_6219) begin
|
|
ic_tag_valid_out_1_16 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_17 <= 1'h0;
|
|
end else if (_T_6236) begin
|
|
ic_tag_valid_out_1_17 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_18 <= 1'h0;
|
|
end else if (_T_6253) begin
|
|
ic_tag_valid_out_1_18 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_19 <= 1'h0;
|
|
end else if (_T_6270) begin
|
|
ic_tag_valid_out_1_19 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_20 <= 1'h0;
|
|
end else if (_T_6287) begin
|
|
ic_tag_valid_out_1_20 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_21 <= 1'h0;
|
|
end else if (_T_6304) begin
|
|
ic_tag_valid_out_1_21 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_22 <= 1'h0;
|
|
end else if (_T_6321) begin
|
|
ic_tag_valid_out_1_22 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_23 <= 1'h0;
|
|
end else if (_T_6338) begin
|
|
ic_tag_valid_out_1_23 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_24 <= 1'h0;
|
|
end else if (_T_6355) begin
|
|
ic_tag_valid_out_1_24 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_25 <= 1'h0;
|
|
end else if (_T_6372) begin
|
|
ic_tag_valid_out_1_25 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_26 <= 1'h0;
|
|
end else if (_T_6389) begin
|
|
ic_tag_valid_out_1_26 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_27 <= 1'h0;
|
|
end else if (_T_6406) begin
|
|
ic_tag_valid_out_1_27 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_28 <= 1'h0;
|
|
end else if (_T_6423) begin
|
|
ic_tag_valid_out_1_28 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_29 <= 1'h0;
|
|
end else if (_T_6440) begin
|
|
ic_tag_valid_out_1_29 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_30 <= 1'h0;
|
|
end else if (_T_6457) begin
|
|
ic_tag_valid_out_1_30 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_31 <= 1'h0;
|
|
end else if (_T_6474) begin
|
|
ic_tag_valid_out_1_31 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_32 <= 1'h0;
|
|
end else if (_T_7035) begin
|
|
ic_tag_valid_out_1_32 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_33 <= 1'h0;
|
|
end else if (_T_7052) begin
|
|
ic_tag_valid_out_1_33 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_34 <= 1'h0;
|
|
end else if (_T_7069) begin
|
|
ic_tag_valid_out_1_34 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_35 <= 1'h0;
|
|
end else if (_T_7086) begin
|
|
ic_tag_valid_out_1_35 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_36 <= 1'h0;
|
|
end else if (_T_7103) begin
|
|
ic_tag_valid_out_1_36 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_37 <= 1'h0;
|
|
end else if (_T_7120) begin
|
|
ic_tag_valid_out_1_37 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_38 <= 1'h0;
|
|
end else if (_T_7137) begin
|
|
ic_tag_valid_out_1_38 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_39 <= 1'h0;
|
|
end else if (_T_7154) begin
|
|
ic_tag_valid_out_1_39 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_40 <= 1'h0;
|
|
end else if (_T_7171) begin
|
|
ic_tag_valid_out_1_40 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_41 <= 1'h0;
|
|
end else if (_T_7188) begin
|
|
ic_tag_valid_out_1_41 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_42 <= 1'h0;
|
|
end else if (_T_7205) begin
|
|
ic_tag_valid_out_1_42 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_43 <= 1'h0;
|
|
end else if (_T_7222) begin
|
|
ic_tag_valid_out_1_43 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_44 <= 1'h0;
|
|
end else if (_T_7239) begin
|
|
ic_tag_valid_out_1_44 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_45 <= 1'h0;
|
|
end else if (_T_7256) begin
|
|
ic_tag_valid_out_1_45 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_46 <= 1'h0;
|
|
end else if (_T_7273) begin
|
|
ic_tag_valid_out_1_46 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_47 <= 1'h0;
|
|
end else if (_T_7290) begin
|
|
ic_tag_valid_out_1_47 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_48 <= 1'h0;
|
|
end else if (_T_7307) begin
|
|
ic_tag_valid_out_1_48 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_49 <= 1'h0;
|
|
end else if (_T_7324) begin
|
|
ic_tag_valid_out_1_49 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_50 <= 1'h0;
|
|
end else if (_T_7341) begin
|
|
ic_tag_valid_out_1_50 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_51 <= 1'h0;
|
|
end else if (_T_7358) begin
|
|
ic_tag_valid_out_1_51 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_52 <= 1'h0;
|
|
end else if (_T_7375) begin
|
|
ic_tag_valid_out_1_52 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_53 <= 1'h0;
|
|
end else if (_T_7392) begin
|
|
ic_tag_valid_out_1_53 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_54 <= 1'h0;
|
|
end else if (_T_7409) begin
|
|
ic_tag_valid_out_1_54 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_55 <= 1'h0;
|
|
end else if (_T_7426) begin
|
|
ic_tag_valid_out_1_55 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_56 <= 1'h0;
|
|
end else if (_T_7443) begin
|
|
ic_tag_valid_out_1_56 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_57 <= 1'h0;
|
|
end else if (_T_7460) begin
|
|
ic_tag_valid_out_1_57 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_58 <= 1'h0;
|
|
end else if (_T_7477) begin
|
|
ic_tag_valid_out_1_58 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_59 <= 1'h0;
|
|
end else if (_T_7494) begin
|
|
ic_tag_valid_out_1_59 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_60 <= 1'h0;
|
|
end else if (_T_7511) begin
|
|
ic_tag_valid_out_1_60 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_61 <= 1'h0;
|
|
end else if (_T_7528) begin
|
|
ic_tag_valid_out_1_61 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_62 <= 1'h0;
|
|
end else if (_T_7545) begin
|
|
ic_tag_valid_out_1_62 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_63 <= 1'h0;
|
|
end else if (_T_7562) begin
|
|
ic_tag_valid_out_1_63 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_64 <= 1'h0;
|
|
end else if (_T_8123) begin
|
|
ic_tag_valid_out_1_64 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_65 <= 1'h0;
|
|
end else if (_T_8140) begin
|
|
ic_tag_valid_out_1_65 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_66 <= 1'h0;
|
|
end else if (_T_8157) begin
|
|
ic_tag_valid_out_1_66 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_67 <= 1'h0;
|
|
end else if (_T_8174) begin
|
|
ic_tag_valid_out_1_67 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_68 <= 1'h0;
|
|
end else if (_T_8191) begin
|
|
ic_tag_valid_out_1_68 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_69 <= 1'h0;
|
|
end else if (_T_8208) begin
|
|
ic_tag_valid_out_1_69 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_70 <= 1'h0;
|
|
end else if (_T_8225) begin
|
|
ic_tag_valid_out_1_70 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_71 <= 1'h0;
|
|
end else if (_T_8242) begin
|
|
ic_tag_valid_out_1_71 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_72 <= 1'h0;
|
|
end else if (_T_8259) begin
|
|
ic_tag_valid_out_1_72 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_73 <= 1'h0;
|
|
end else if (_T_8276) begin
|
|
ic_tag_valid_out_1_73 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_74 <= 1'h0;
|
|
end else if (_T_8293) begin
|
|
ic_tag_valid_out_1_74 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_75 <= 1'h0;
|
|
end else if (_T_8310) begin
|
|
ic_tag_valid_out_1_75 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_76 <= 1'h0;
|
|
end else if (_T_8327) begin
|
|
ic_tag_valid_out_1_76 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_77 <= 1'h0;
|
|
end else if (_T_8344) begin
|
|
ic_tag_valid_out_1_77 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_78 <= 1'h0;
|
|
end else if (_T_8361) begin
|
|
ic_tag_valid_out_1_78 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_79 <= 1'h0;
|
|
end else if (_T_8378) begin
|
|
ic_tag_valid_out_1_79 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_80 <= 1'h0;
|
|
end else if (_T_8395) begin
|
|
ic_tag_valid_out_1_80 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_81 <= 1'h0;
|
|
end else if (_T_8412) begin
|
|
ic_tag_valid_out_1_81 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_82 <= 1'h0;
|
|
end else if (_T_8429) begin
|
|
ic_tag_valid_out_1_82 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_83 <= 1'h0;
|
|
end else if (_T_8446) begin
|
|
ic_tag_valid_out_1_83 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_84 <= 1'h0;
|
|
end else if (_T_8463) begin
|
|
ic_tag_valid_out_1_84 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_85 <= 1'h0;
|
|
end else if (_T_8480) begin
|
|
ic_tag_valid_out_1_85 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_86 <= 1'h0;
|
|
end else if (_T_8497) begin
|
|
ic_tag_valid_out_1_86 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_87 <= 1'h0;
|
|
end else if (_T_8514) begin
|
|
ic_tag_valid_out_1_87 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_88 <= 1'h0;
|
|
end else if (_T_8531) begin
|
|
ic_tag_valid_out_1_88 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_89 <= 1'h0;
|
|
end else if (_T_8548) begin
|
|
ic_tag_valid_out_1_89 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_90 <= 1'h0;
|
|
end else if (_T_8565) begin
|
|
ic_tag_valid_out_1_90 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_91 <= 1'h0;
|
|
end else if (_T_8582) begin
|
|
ic_tag_valid_out_1_91 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_92 <= 1'h0;
|
|
end else if (_T_8599) begin
|
|
ic_tag_valid_out_1_92 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_93 <= 1'h0;
|
|
end else if (_T_8616) begin
|
|
ic_tag_valid_out_1_93 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_94 <= 1'h0;
|
|
end else if (_T_8633) begin
|
|
ic_tag_valid_out_1_94 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_95 <= 1'h0;
|
|
end else if (_T_8650) begin
|
|
ic_tag_valid_out_1_95 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_96 <= 1'h0;
|
|
end else if (_T_9211) begin
|
|
ic_tag_valid_out_1_96 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_97 <= 1'h0;
|
|
end else if (_T_9228) begin
|
|
ic_tag_valid_out_1_97 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_98 <= 1'h0;
|
|
end else if (_T_9245) begin
|
|
ic_tag_valid_out_1_98 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_99 <= 1'h0;
|
|
end else if (_T_9262) begin
|
|
ic_tag_valid_out_1_99 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_100 <= 1'h0;
|
|
end else if (_T_9279) begin
|
|
ic_tag_valid_out_1_100 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_101 <= 1'h0;
|
|
end else if (_T_9296) begin
|
|
ic_tag_valid_out_1_101 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_102 <= 1'h0;
|
|
end else if (_T_9313) begin
|
|
ic_tag_valid_out_1_102 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_103 <= 1'h0;
|
|
end else if (_T_9330) begin
|
|
ic_tag_valid_out_1_103 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_104 <= 1'h0;
|
|
end else if (_T_9347) begin
|
|
ic_tag_valid_out_1_104 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_105 <= 1'h0;
|
|
end else if (_T_9364) begin
|
|
ic_tag_valid_out_1_105 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_106 <= 1'h0;
|
|
end else if (_T_9381) begin
|
|
ic_tag_valid_out_1_106 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_107 <= 1'h0;
|
|
end else if (_T_9398) begin
|
|
ic_tag_valid_out_1_107 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_108 <= 1'h0;
|
|
end else if (_T_9415) begin
|
|
ic_tag_valid_out_1_108 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_109 <= 1'h0;
|
|
end else if (_T_9432) begin
|
|
ic_tag_valid_out_1_109 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_110 <= 1'h0;
|
|
end else if (_T_9449) begin
|
|
ic_tag_valid_out_1_110 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_111 <= 1'h0;
|
|
end else if (_T_9466) begin
|
|
ic_tag_valid_out_1_111 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_112 <= 1'h0;
|
|
end else if (_T_9483) begin
|
|
ic_tag_valid_out_1_112 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_113 <= 1'h0;
|
|
end else if (_T_9500) begin
|
|
ic_tag_valid_out_1_113 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_114 <= 1'h0;
|
|
end else if (_T_9517) begin
|
|
ic_tag_valid_out_1_114 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_115 <= 1'h0;
|
|
end else if (_T_9534) begin
|
|
ic_tag_valid_out_1_115 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_116 <= 1'h0;
|
|
end else if (_T_9551) begin
|
|
ic_tag_valid_out_1_116 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_117 <= 1'h0;
|
|
end else if (_T_9568) begin
|
|
ic_tag_valid_out_1_117 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_118 <= 1'h0;
|
|
end else if (_T_9585) begin
|
|
ic_tag_valid_out_1_118 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_119 <= 1'h0;
|
|
end else if (_T_9602) begin
|
|
ic_tag_valid_out_1_119 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_120 <= 1'h0;
|
|
end else if (_T_9619) begin
|
|
ic_tag_valid_out_1_120 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_121 <= 1'h0;
|
|
end else if (_T_9636) begin
|
|
ic_tag_valid_out_1_121 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_122 <= 1'h0;
|
|
end else if (_T_9653) begin
|
|
ic_tag_valid_out_1_122 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_123 <= 1'h0;
|
|
end else if (_T_9670) begin
|
|
ic_tag_valid_out_1_123 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_124 <= 1'h0;
|
|
end else if (_T_9687) begin
|
|
ic_tag_valid_out_1_124 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_125 <= 1'h0;
|
|
end else if (_T_9704) begin
|
|
ic_tag_valid_out_1_125 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_126 <= 1'h0;
|
|
end else if (_T_9721) begin
|
|
ic_tag_valid_out_1_126 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_1_127 <= 1'h0;
|
|
end else if (_T_9738) begin
|
|
ic_tag_valid_out_1_127 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_0 <= 1'h0;
|
|
end else if (_T_5403) begin
|
|
ic_tag_valid_out_0_0 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_1 <= 1'h0;
|
|
end else if (_T_5420) begin
|
|
ic_tag_valid_out_0_1 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_2 <= 1'h0;
|
|
end else if (_T_5437) begin
|
|
ic_tag_valid_out_0_2 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_3 <= 1'h0;
|
|
end else if (_T_5454) begin
|
|
ic_tag_valid_out_0_3 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_4 <= 1'h0;
|
|
end else if (_T_5471) begin
|
|
ic_tag_valid_out_0_4 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_5 <= 1'h0;
|
|
end else if (_T_5488) begin
|
|
ic_tag_valid_out_0_5 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_6 <= 1'h0;
|
|
end else if (_T_5505) begin
|
|
ic_tag_valid_out_0_6 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_7 <= 1'h0;
|
|
end else if (_T_5522) begin
|
|
ic_tag_valid_out_0_7 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_8 <= 1'h0;
|
|
end else if (_T_5539) begin
|
|
ic_tag_valid_out_0_8 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_9 <= 1'h0;
|
|
end else if (_T_5556) begin
|
|
ic_tag_valid_out_0_9 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_10 <= 1'h0;
|
|
end else if (_T_5573) begin
|
|
ic_tag_valid_out_0_10 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_11 <= 1'h0;
|
|
end else if (_T_5590) begin
|
|
ic_tag_valid_out_0_11 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_12 <= 1'h0;
|
|
end else if (_T_5607) begin
|
|
ic_tag_valid_out_0_12 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_13 <= 1'h0;
|
|
end else if (_T_5624) begin
|
|
ic_tag_valid_out_0_13 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_14 <= 1'h0;
|
|
end else if (_T_5641) begin
|
|
ic_tag_valid_out_0_14 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_15 <= 1'h0;
|
|
end else if (_T_5658) begin
|
|
ic_tag_valid_out_0_15 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_16 <= 1'h0;
|
|
end else if (_T_5675) begin
|
|
ic_tag_valid_out_0_16 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_17 <= 1'h0;
|
|
end else if (_T_5692) begin
|
|
ic_tag_valid_out_0_17 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_18 <= 1'h0;
|
|
end else if (_T_5709) begin
|
|
ic_tag_valid_out_0_18 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_19 <= 1'h0;
|
|
end else if (_T_5726) begin
|
|
ic_tag_valid_out_0_19 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_20 <= 1'h0;
|
|
end else if (_T_5743) begin
|
|
ic_tag_valid_out_0_20 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_21 <= 1'h0;
|
|
end else if (_T_5760) begin
|
|
ic_tag_valid_out_0_21 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_22 <= 1'h0;
|
|
end else if (_T_5777) begin
|
|
ic_tag_valid_out_0_22 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_23 <= 1'h0;
|
|
end else if (_T_5794) begin
|
|
ic_tag_valid_out_0_23 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_24 <= 1'h0;
|
|
end else if (_T_5811) begin
|
|
ic_tag_valid_out_0_24 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_25 <= 1'h0;
|
|
end else if (_T_5828) begin
|
|
ic_tag_valid_out_0_25 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_26 <= 1'h0;
|
|
end else if (_T_5845) begin
|
|
ic_tag_valid_out_0_26 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_27 <= 1'h0;
|
|
end else if (_T_5862) begin
|
|
ic_tag_valid_out_0_27 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_28 <= 1'h0;
|
|
end else if (_T_5879) begin
|
|
ic_tag_valid_out_0_28 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_29 <= 1'h0;
|
|
end else if (_T_5896) begin
|
|
ic_tag_valid_out_0_29 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_30 <= 1'h0;
|
|
end else if (_T_5913) begin
|
|
ic_tag_valid_out_0_30 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_31 <= 1'h0;
|
|
end else if (_T_5930) begin
|
|
ic_tag_valid_out_0_31 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_32 <= 1'h0;
|
|
end else if (_T_6491) begin
|
|
ic_tag_valid_out_0_32 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_33 <= 1'h0;
|
|
end else if (_T_6508) begin
|
|
ic_tag_valid_out_0_33 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_34 <= 1'h0;
|
|
end else if (_T_6525) begin
|
|
ic_tag_valid_out_0_34 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_35 <= 1'h0;
|
|
end else if (_T_6542) begin
|
|
ic_tag_valid_out_0_35 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_36 <= 1'h0;
|
|
end else if (_T_6559) begin
|
|
ic_tag_valid_out_0_36 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_37 <= 1'h0;
|
|
end else if (_T_6576) begin
|
|
ic_tag_valid_out_0_37 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_38 <= 1'h0;
|
|
end else if (_T_6593) begin
|
|
ic_tag_valid_out_0_38 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_39 <= 1'h0;
|
|
end else if (_T_6610) begin
|
|
ic_tag_valid_out_0_39 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_40 <= 1'h0;
|
|
end else if (_T_6627) begin
|
|
ic_tag_valid_out_0_40 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_41 <= 1'h0;
|
|
end else if (_T_6644) begin
|
|
ic_tag_valid_out_0_41 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_42 <= 1'h0;
|
|
end else if (_T_6661) begin
|
|
ic_tag_valid_out_0_42 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_43 <= 1'h0;
|
|
end else if (_T_6678) begin
|
|
ic_tag_valid_out_0_43 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_44 <= 1'h0;
|
|
end else if (_T_6695) begin
|
|
ic_tag_valid_out_0_44 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_45 <= 1'h0;
|
|
end else if (_T_6712) begin
|
|
ic_tag_valid_out_0_45 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_46 <= 1'h0;
|
|
end else if (_T_6729) begin
|
|
ic_tag_valid_out_0_46 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_47 <= 1'h0;
|
|
end else if (_T_6746) begin
|
|
ic_tag_valid_out_0_47 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_48 <= 1'h0;
|
|
end else if (_T_6763) begin
|
|
ic_tag_valid_out_0_48 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_49 <= 1'h0;
|
|
end else if (_T_6780) begin
|
|
ic_tag_valid_out_0_49 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_50 <= 1'h0;
|
|
end else if (_T_6797) begin
|
|
ic_tag_valid_out_0_50 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_51 <= 1'h0;
|
|
end else if (_T_6814) begin
|
|
ic_tag_valid_out_0_51 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_52 <= 1'h0;
|
|
end else if (_T_6831) begin
|
|
ic_tag_valid_out_0_52 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_53 <= 1'h0;
|
|
end else if (_T_6848) begin
|
|
ic_tag_valid_out_0_53 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_54 <= 1'h0;
|
|
end else if (_T_6865) begin
|
|
ic_tag_valid_out_0_54 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_55 <= 1'h0;
|
|
end else if (_T_6882) begin
|
|
ic_tag_valid_out_0_55 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_56 <= 1'h0;
|
|
end else if (_T_6899) begin
|
|
ic_tag_valid_out_0_56 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_57 <= 1'h0;
|
|
end else if (_T_6916) begin
|
|
ic_tag_valid_out_0_57 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_58 <= 1'h0;
|
|
end else if (_T_6933) begin
|
|
ic_tag_valid_out_0_58 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_59 <= 1'h0;
|
|
end else if (_T_6950) begin
|
|
ic_tag_valid_out_0_59 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_60 <= 1'h0;
|
|
end else if (_T_6967) begin
|
|
ic_tag_valid_out_0_60 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_61 <= 1'h0;
|
|
end else if (_T_6984) begin
|
|
ic_tag_valid_out_0_61 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_62 <= 1'h0;
|
|
end else if (_T_7001) begin
|
|
ic_tag_valid_out_0_62 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_63 <= 1'h0;
|
|
end else if (_T_7018) begin
|
|
ic_tag_valid_out_0_63 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_64 <= 1'h0;
|
|
end else if (_T_7579) begin
|
|
ic_tag_valid_out_0_64 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_65 <= 1'h0;
|
|
end else if (_T_7596) begin
|
|
ic_tag_valid_out_0_65 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_66 <= 1'h0;
|
|
end else if (_T_7613) begin
|
|
ic_tag_valid_out_0_66 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_67 <= 1'h0;
|
|
end else if (_T_7630) begin
|
|
ic_tag_valid_out_0_67 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_68 <= 1'h0;
|
|
end else if (_T_7647) begin
|
|
ic_tag_valid_out_0_68 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_69 <= 1'h0;
|
|
end else if (_T_7664) begin
|
|
ic_tag_valid_out_0_69 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_70 <= 1'h0;
|
|
end else if (_T_7681) begin
|
|
ic_tag_valid_out_0_70 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_71 <= 1'h0;
|
|
end else if (_T_7698) begin
|
|
ic_tag_valid_out_0_71 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_72 <= 1'h0;
|
|
end else if (_T_7715) begin
|
|
ic_tag_valid_out_0_72 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_73 <= 1'h0;
|
|
end else if (_T_7732) begin
|
|
ic_tag_valid_out_0_73 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_74 <= 1'h0;
|
|
end else if (_T_7749) begin
|
|
ic_tag_valid_out_0_74 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_75 <= 1'h0;
|
|
end else if (_T_7766) begin
|
|
ic_tag_valid_out_0_75 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_76 <= 1'h0;
|
|
end else if (_T_7783) begin
|
|
ic_tag_valid_out_0_76 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_77 <= 1'h0;
|
|
end else if (_T_7800) begin
|
|
ic_tag_valid_out_0_77 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_78 <= 1'h0;
|
|
end else if (_T_7817) begin
|
|
ic_tag_valid_out_0_78 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_79 <= 1'h0;
|
|
end else if (_T_7834) begin
|
|
ic_tag_valid_out_0_79 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_80 <= 1'h0;
|
|
end else if (_T_7851) begin
|
|
ic_tag_valid_out_0_80 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_81 <= 1'h0;
|
|
end else if (_T_7868) begin
|
|
ic_tag_valid_out_0_81 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_82 <= 1'h0;
|
|
end else if (_T_7885) begin
|
|
ic_tag_valid_out_0_82 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_83 <= 1'h0;
|
|
end else if (_T_7902) begin
|
|
ic_tag_valid_out_0_83 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_84 <= 1'h0;
|
|
end else if (_T_7919) begin
|
|
ic_tag_valid_out_0_84 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_85 <= 1'h0;
|
|
end else if (_T_7936) begin
|
|
ic_tag_valid_out_0_85 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_86 <= 1'h0;
|
|
end else if (_T_7953) begin
|
|
ic_tag_valid_out_0_86 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_87 <= 1'h0;
|
|
end else if (_T_7970) begin
|
|
ic_tag_valid_out_0_87 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_88 <= 1'h0;
|
|
end else if (_T_7987) begin
|
|
ic_tag_valid_out_0_88 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_89 <= 1'h0;
|
|
end else if (_T_8004) begin
|
|
ic_tag_valid_out_0_89 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_90 <= 1'h0;
|
|
end else if (_T_8021) begin
|
|
ic_tag_valid_out_0_90 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_91 <= 1'h0;
|
|
end else if (_T_8038) begin
|
|
ic_tag_valid_out_0_91 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_92 <= 1'h0;
|
|
end else if (_T_8055) begin
|
|
ic_tag_valid_out_0_92 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_93 <= 1'h0;
|
|
end else if (_T_8072) begin
|
|
ic_tag_valid_out_0_93 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_94 <= 1'h0;
|
|
end else if (_T_8089) begin
|
|
ic_tag_valid_out_0_94 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_95 <= 1'h0;
|
|
end else if (_T_8106) begin
|
|
ic_tag_valid_out_0_95 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_96 <= 1'h0;
|
|
end else if (_T_8667) begin
|
|
ic_tag_valid_out_0_96 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_97 <= 1'h0;
|
|
end else if (_T_8684) begin
|
|
ic_tag_valid_out_0_97 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_98 <= 1'h0;
|
|
end else if (_T_8701) begin
|
|
ic_tag_valid_out_0_98 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_99 <= 1'h0;
|
|
end else if (_T_8718) begin
|
|
ic_tag_valid_out_0_99 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_100 <= 1'h0;
|
|
end else if (_T_8735) begin
|
|
ic_tag_valid_out_0_100 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_101 <= 1'h0;
|
|
end else if (_T_8752) begin
|
|
ic_tag_valid_out_0_101 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_102 <= 1'h0;
|
|
end else if (_T_8769) begin
|
|
ic_tag_valid_out_0_102 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_103 <= 1'h0;
|
|
end else if (_T_8786) begin
|
|
ic_tag_valid_out_0_103 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_104 <= 1'h0;
|
|
end else if (_T_8803) begin
|
|
ic_tag_valid_out_0_104 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_105 <= 1'h0;
|
|
end else if (_T_8820) begin
|
|
ic_tag_valid_out_0_105 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_106 <= 1'h0;
|
|
end else if (_T_8837) begin
|
|
ic_tag_valid_out_0_106 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_107 <= 1'h0;
|
|
end else if (_T_8854) begin
|
|
ic_tag_valid_out_0_107 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_108 <= 1'h0;
|
|
end else if (_T_8871) begin
|
|
ic_tag_valid_out_0_108 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_109 <= 1'h0;
|
|
end else if (_T_8888) begin
|
|
ic_tag_valid_out_0_109 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_110 <= 1'h0;
|
|
end else if (_T_8905) begin
|
|
ic_tag_valid_out_0_110 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_111 <= 1'h0;
|
|
end else if (_T_8922) begin
|
|
ic_tag_valid_out_0_111 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_112 <= 1'h0;
|
|
end else if (_T_8939) begin
|
|
ic_tag_valid_out_0_112 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_113 <= 1'h0;
|
|
end else if (_T_8956) begin
|
|
ic_tag_valid_out_0_113 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_114 <= 1'h0;
|
|
end else if (_T_8973) begin
|
|
ic_tag_valid_out_0_114 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_115 <= 1'h0;
|
|
end else if (_T_8990) begin
|
|
ic_tag_valid_out_0_115 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_116 <= 1'h0;
|
|
end else if (_T_9007) begin
|
|
ic_tag_valid_out_0_116 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_117 <= 1'h0;
|
|
end else if (_T_9024) begin
|
|
ic_tag_valid_out_0_117 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_118 <= 1'h0;
|
|
end else if (_T_9041) begin
|
|
ic_tag_valid_out_0_118 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_119 <= 1'h0;
|
|
end else if (_T_9058) begin
|
|
ic_tag_valid_out_0_119 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_120 <= 1'h0;
|
|
end else if (_T_9075) begin
|
|
ic_tag_valid_out_0_120 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_121 <= 1'h0;
|
|
end else if (_T_9092) begin
|
|
ic_tag_valid_out_0_121 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_122 <= 1'h0;
|
|
end else if (_T_9109) begin
|
|
ic_tag_valid_out_0_122 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_123 <= 1'h0;
|
|
end else if (_T_9126) begin
|
|
ic_tag_valid_out_0_123 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_124 <= 1'h0;
|
|
end else if (_T_9143) begin
|
|
ic_tag_valid_out_0_124 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_125 <= 1'h0;
|
|
end else if (_T_9160) begin
|
|
ic_tag_valid_out_0_125 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_126 <= 1'h0;
|
|
end else if (_T_9177) begin
|
|
ic_tag_valid_out_0_126 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_tag_valid_out_0_127 <= 1'h0;
|
|
end else if (_T_9194) begin
|
|
ic_tag_valid_out_0_127 <= _T_5392;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_way_ff <= 2'h0;
|
|
end else if (debug_c1_clken) begin
|
|
ic_debug_way_ff <= io_ic_debug_way;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_debug_rd_en_ff <= 1'h0;
|
|
end else if (_T_10593) begin
|
|
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1237 <= 71'h0;
|
|
end else if (ic_debug_rd_en_ff) begin
|
|
if (ic_debug_ict_array_sel_ff) begin
|
|
_T_1237 <= _T_1236;
|
|
end else begin
|
|
_T_1237 <= io_ic_debug_rd_data;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_region_acc_fault_memory_f <= 1'h0;
|
|
end else if (_T_10661) begin
|
|
ifc_region_acc_fault_memory_f <= ifc_region_acc_fault_memory_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
perr_ic_index_ff <= 7'h0;
|
|
end else if (perr_sb_write_status) begin
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_sb_err_state_ff <= 1'h0;
|
|
end else if (_T_2517) begin
|
|
dma_sb_err_state_ff <= _T_10;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
bus_cmd_req_hold <= 1'h0;
|
|
end else if (_T_2635) begin
|
|
bus_cmd_req_hold <= bus_cmd_req_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_cmd_valid <= 1'h0;
|
|
end else if (_T_2627) begin
|
|
ifu_bus_cmd_valid <= ifc_bus_ic_req_ff_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bus_cmd_beat_count <= 3'h0;
|
|
end else if (_T_2711) begin
|
|
bus_cmd_beat_count <= bus_new_cmd_beat_count;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_arready_unq_ff <= 1'h0;
|
|
end else if (io_ifu_bus_clk_en) begin
|
|
ifu_bus_arready_unq_ff <= io_ifu_axi_ar_ready;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_bus_arvalid_ff <= 1'h0;
|
|
end else if (io_ifu_bus_clk_en) begin
|
|
ifu_bus_arvalid_ff <= io_ifu_axi_ar_valid;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_dma_access_ok_prev <= 1'h0;
|
|
end else if (_T_2744) begin
|
|
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_ecc_corr_data_ff <= 39'h0;
|
|
end else if (iccm_ecc_write_status) begin
|
|
iccm_ecc_corr_data_ff <= _T_4021;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_addr_ff <= 2'h0;
|
|
end else if (_T_3166) begin
|
|
dma_mem_addr_ff <= io_dma_mem_ctl_dma_mem_addr[3:2];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_tag_ff <= 3'h0;
|
|
end else if (_T_3158) begin
|
|
dma_mem_tag_ff <= io_dma_mem_ctl_dma_mem_tag;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rtag_temp <= 3'h0;
|
|
end else if (_T_3161) begin
|
|
iccm_dma_rtag_temp <= dma_mem_tag_ff;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rvalid_temp <= 1'h0;
|
|
end else if (_T_3172) begin
|
|
iccm_dma_rvalid_temp <= iccm_dma_rvalid_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_ecc_error <= 1'h0;
|
|
end else if (_T_3176) begin
|
|
iccm_dma_ecc_error <= _T_3154;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_dma_rdata_temp <= 64'h0;
|
|
end else if (iccm_dma_rvalid_in) begin
|
|
if (_T_3154) begin
|
|
iccm_dma_rdata_temp <= _T_3155;
|
|
end else begin
|
|
iccm_dma_rdata_temp <= _T_3156;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_ecc_corr_index_ff <= 14'h0;
|
|
end else if (iccm_ecc_write_status) begin
|
|
if (iccm_single_ecc_error[0]) begin
|
|
iccm_ecc_corr_index_ff <= iccm_rw_addr_f;
|
|
end else begin
|
|
iccm_ecc_corr_index_ff <= _T_4015;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_rd_ecc_single_err_ff <= 1'h0;
|
|
end else if (_T_4003) begin
|
|
iccm_rd_ecc_single_err_ff <= iccm_rd_ecc_single_err_hold_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_rw_addr_f <= 14'h0;
|
|
end else if (_T_4019) begin
|
|
iccm_rw_addr_f <= io_iccm_rw_addr[14:1];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_status_wr_addr_ff <= 7'h0;
|
|
end else if (_T_4093) begin
|
|
if (_T_4089) begin
|
|
ifu_status_wr_addr_ff <= io_ic_debug_addr[9:3];
|
|
end else begin
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr[11:5];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_wr_en_ff <= 1'h0;
|
|
end else if (_T_4097) begin
|
|
way_status_wr_en_ff <= way_status_wr_en_w_debug;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
way_status_new_ff <= 1'h0;
|
|
end else if (_T_4102) begin
|
|
if (_T_4095) begin
|
|
way_status_new_ff <= io_ic_debug_wr_data[4];
|
|
end else if (_T_10527) begin
|
|
way_status_new_ff <= replace_way_mb_any_0;
|
|
end else begin
|
|
way_status_new_ff <= way_status_hit_new;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_tag_wren_ff <= 2'h0;
|
|
end else if (_T_5293) begin
|
|
ifu_tag_wren_ff <= ifu_tag_wren_w_debug;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ic_valid_ff <= 1'h0;
|
|
end else if (_T_5298) begin
|
|
if (_T_4095) begin
|
|
ic_valid_ff <= io_ic_debug_wr_data[0];
|
|
end else begin
|
|
ic_valid_ff <= ic_valid;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10552 <= 1'h0;
|
|
end else if (_T_10551) begin
|
|
_T_10552 <= ic_act_miss_f;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10556 <= 1'h0;
|
|
end else if (_T_10555) begin
|
|
_T_10556 <= ic_act_hit_f;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10561 <= 1'h0;
|
|
end else if (_T_10560) begin
|
|
_T_10561 <= _T_2500;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10568 <= 1'h0;
|
|
end else if (_T_10567) begin
|
|
_T_10568 <= _T_10564;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10572 <= 1'h0;
|
|
end else if (_T_10571) begin
|
|
_T_10572 <= bus_cmd_sent;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10598 <= 1'h0;
|
|
end else if (_T_10597) begin
|
|
_T_10598 <= ic_debug_rd_en_ff;
|
|
end
|
|
end
|
|
endmodule
|
|
module ifu_bp_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_ic_hit_f,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_ifc_fetch_addr_f,
|
|
input io_ifc_fetch_req_f,
|
|
input io_dec_bp_dec_tlu_br0_r_pkt_valid,
|
|
input [1:0] io_dec_bp_dec_tlu_br0_r_pkt_bits_hist,
|
|
input io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error,
|
|
input io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error,
|
|
input io_dec_bp_dec_tlu_br0_r_pkt_bits_way,
|
|
input io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,
|
|
input io_dec_bp_dec_tlu_flush_leak_one_wb,
|
|
input io_dec_bp_dec_tlu_bpred_disable,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
input [7:0] io_exu_bp_exu_i0_br_index_r,
|
|
input [7:0] io_exu_bp_exu_i0_br_fghr_r,
|
|
input io_exu_bp_exu_mp_pkt_valid,
|
|
input io_exu_bp_exu_mp_pkt_bits_misp,
|
|
input io_exu_bp_exu_mp_pkt_bits_ataken,
|
|
input io_exu_bp_exu_mp_pkt_bits_boffset,
|
|
input io_exu_bp_exu_mp_pkt_bits_pc4,
|
|
input [1:0] io_exu_bp_exu_mp_pkt_bits_hist,
|
|
input [11:0] io_exu_bp_exu_mp_pkt_bits_toffset,
|
|
input io_exu_bp_exu_mp_pkt_bits_pcall,
|
|
input io_exu_bp_exu_mp_pkt_bits_pja,
|
|
input io_exu_bp_exu_mp_pkt_bits_way,
|
|
input io_exu_bp_exu_mp_pkt_bits_pret,
|
|
input [7:0] io_exu_bp_exu_mp_eghr,
|
|
input [7:0] io_exu_bp_exu_mp_fghr,
|
|
input [7:0] io_exu_bp_exu_mp_index,
|
|
input [4:0] io_exu_bp_exu_mp_btag,
|
|
output io_ifu_bp_hit_taken_f,
|
|
output [30:0] io_ifu_bp_btb_target_f,
|
|
output io_ifu_bp_inst_mask_f,
|
|
output [7:0] io_ifu_bp_fghr_f,
|
|
output [1:0] io_ifu_bp_way_f,
|
|
output [1:0] io_ifu_bp_ret_f,
|
|
output [1:0] io_ifu_bp_hist1_f,
|
|
output [1:0] io_ifu_bp_hist0_f,
|
|
output [1:0] io_ifu_bp_pc4_f,
|
|
output [1:0] io_ifu_bp_valid_f,
|
|
output [11:0] io_ifu_bp_poffset_f
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
reg [31:0] _RAND_137;
|
|
reg [31:0] _RAND_138;
|
|
reg [31:0] _RAND_139;
|
|
reg [31:0] _RAND_140;
|
|
reg [31:0] _RAND_141;
|
|
reg [31:0] _RAND_142;
|
|
reg [31:0] _RAND_143;
|
|
reg [31:0] _RAND_144;
|
|
reg [31:0] _RAND_145;
|
|
reg [31:0] _RAND_146;
|
|
reg [31:0] _RAND_147;
|
|
reg [31:0] _RAND_148;
|
|
reg [31:0] _RAND_149;
|
|
reg [31:0] _RAND_150;
|
|
reg [31:0] _RAND_151;
|
|
reg [31:0] _RAND_152;
|
|
reg [31:0] _RAND_153;
|
|
reg [31:0] _RAND_154;
|
|
reg [31:0] _RAND_155;
|
|
reg [31:0] _RAND_156;
|
|
reg [31:0] _RAND_157;
|
|
reg [31:0] _RAND_158;
|
|
reg [31:0] _RAND_159;
|
|
reg [31:0] _RAND_160;
|
|
reg [31:0] _RAND_161;
|
|
reg [31:0] _RAND_162;
|
|
reg [31:0] _RAND_163;
|
|
reg [31:0] _RAND_164;
|
|
reg [31:0] _RAND_165;
|
|
reg [31:0] _RAND_166;
|
|
reg [31:0] _RAND_167;
|
|
reg [31:0] _RAND_168;
|
|
reg [31:0] _RAND_169;
|
|
reg [31:0] _RAND_170;
|
|
reg [31:0] _RAND_171;
|
|
reg [31:0] _RAND_172;
|
|
reg [31:0] _RAND_173;
|
|
reg [31:0] _RAND_174;
|
|
reg [31:0] _RAND_175;
|
|
reg [31:0] _RAND_176;
|
|
reg [31:0] _RAND_177;
|
|
reg [31:0] _RAND_178;
|
|
reg [31:0] _RAND_179;
|
|
reg [31:0] _RAND_180;
|
|
reg [31:0] _RAND_181;
|
|
reg [31:0] _RAND_182;
|
|
reg [31:0] _RAND_183;
|
|
reg [31:0] _RAND_184;
|
|
reg [31:0] _RAND_185;
|
|
reg [31:0] _RAND_186;
|
|
reg [31:0] _RAND_187;
|
|
reg [31:0] _RAND_188;
|
|
reg [31:0] _RAND_189;
|
|
reg [31:0] _RAND_190;
|
|
reg [31:0] _RAND_191;
|
|
reg [31:0] _RAND_192;
|
|
reg [31:0] _RAND_193;
|
|
reg [31:0] _RAND_194;
|
|
reg [31:0] _RAND_195;
|
|
reg [31:0] _RAND_196;
|
|
reg [31:0] _RAND_197;
|
|
reg [31:0] _RAND_198;
|
|
reg [31:0] _RAND_199;
|
|
reg [31:0] _RAND_200;
|
|
reg [31:0] _RAND_201;
|
|
reg [31:0] _RAND_202;
|
|
reg [31:0] _RAND_203;
|
|
reg [31:0] _RAND_204;
|
|
reg [31:0] _RAND_205;
|
|
reg [31:0] _RAND_206;
|
|
reg [31:0] _RAND_207;
|
|
reg [31:0] _RAND_208;
|
|
reg [31:0] _RAND_209;
|
|
reg [31:0] _RAND_210;
|
|
reg [31:0] _RAND_211;
|
|
reg [31:0] _RAND_212;
|
|
reg [31:0] _RAND_213;
|
|
reg [31:0] _RAND_214;
|
|
reg [31:0] _RAND_215;
|
|
reg [31:0] _RAND_216;
|
|
reg [31:0] _RAND_217;
|
|
reg [31:0] _RAND_218;
|
|
reg [31:0] _RAND_219;
|
|
reg [31:0] _RAND_220;
|
|
reg [31:0] _RAND_221;
|
|
reg [31:0] _RAND_222;
|
|
reg [31:0] _RAND_223;
|
|
reg [31:0] _RAND_224;
|
|
reg [31:0] _RAND_225;
|
|
reg [31:0] _RAND_226;
|
|
reg [31:0] _RAND_227;
|
|
reg [31:0] _RAND_228;
|
|
reg [31:0] _RAND_229;
|
|
reg [31:0] _RAND_230;
|
|
reg [31:0] _RAND_231;
|
|
reg [31:0] _RAND_232;
|
|
reg [31:0] _RAND_233;
|
|
reg [31:0] _RAND_234;
|
|
reg [31:0] _RAND_235;
|
|
reg [31:0] _RAND_236;
|
|
reg [31:0] _RAND_237;
|
|
reg [31:0] _RAND_238;
|
|
reg [31:0] _RAND_239;
|
|
reg [31:0] _RAND_240;
|
|
reg [31:0] _RAND_241;
|
|
reg [31:0] _RAND_242;
|
|
reg [31:0] _RAND_243;
|
|
reg [31:0] _RAND_244;
|
|
reg [31:0] _RAND_245;
|
|
reg [31:0] _RAND_246;
|
|
reg [31:0] _RAND_247;
|
|
reg [31:0] _RAND_248;
|
|
reg [31:0] _RAND_249;
|
|
reg [31:0] _RAND_250;
|
|
reg [31:0] _RAND_251;
|
|
reg [31:0] _RAND_252;
|
|
reg [31:0] _RAND_253;
|
|
reg [31:0] _RAND_254;
|
|
reg [31:0] _RAND_255;
|
|
reg [31:0] _RAND_256;
|
|
reg [31:0] _RAND_257;
|
|
reg [31:0] _RAND_258;
|
|
reg [31:0] _RAND_259;
|
|
reg [31:0] _RAND_260;
|
|
reg [31:0] _RAND_261;
|
|
reg [31:0] _RAND_262;
|
|
reg [31:0] _RAND_263;
|
|
reg [31:0] _RAND_264;
|
|
reg [31:0] _RAND_265;
|
|
reg [31:0] _RAND_266;
|
|
reg [31:0] _RAND_267;
|
|
reg [31:0] _RAND_268;
|
|
reg [31:0] _RAND_269;
|
|
reg [31:0] _RAND_270;
|
|
reg [31:0] _RAND_271;
|
|
reg [31:0] _RAND_272;
|
|
reg [31:0] _RAND_273;
|
|
reg [31:0] _RAND_274;
|
|
reg [31:0] _RAND_275;
|
|
reg [31:0] _RAND_276;
|
|
reg [31:0] _RAND_277;
|
|
reg [31:0] _RAND_278;
|
|
reg [31:0] _RAND_279;
|
|
reg [31:0] _RAND_280;
|
|
reg [31:0] _RAND_281;
|
|
reg [31:0] _RAND_282;
|
|
reg [31:0] _RAND_283;
|
|
reg [31:0] _RAND_284;
|
|
reg [31:0] _RAND_285;
|
|
reg [31:0] _RAND_286;
|
|
reg [31:0] _RAND_287;
|
|
reg [31:0] _RAND_288;
|
|
reg [31:0] _RAND_289;
|
|
reg [31:0] _RAND_290;
|
|
reg [31:0] _RAND_291;
|
|
reg [31:0] _RAND_292;
|
|
reg [31:0] _RAND_293;
|
|
reg [31:0] _RAND_294;
|
|
reg [31:0] _RAND_295;
|
|
reg [31:0] _RAND_296;
|
|
reg [31:0] _RAND_297;
|
|
reg [31:0] _RAND_298;
|
|
reg [31:0] _RAND_299;
|
|
reg [31:0] _RAND_300;
|
|
reg [31:0] _RAND_301;
|
|
reg [31:0] _RAND_302;
|
|
reg [31:0] _RAND_303;
|
|
reg [31:0] _RAND_304;
|
|
reg [31:0] _RAND_305;
|
|
reg [31:0] _RAND_306;
|
|
reg [31:0] _RAND_307;
|
|
reg [31:0] _RAND_308;
|
|
reg [31:0] _RAND_309;
|
|
reg [31:0] _RAND_310;
|
|
reg [31:0] _RAND_311;
|
|
reg [31:0] _RAND_312;
|
|
reg [31:0] _RAND_313;
|
|
reg [31:0] _RAND_314;
|
|
reg [31:0] _RAND_315;
|
|
reg [31:0] _RAND_316;
|
|
reg [31:0] _RAND_317;
|
|
reg [31:0] _RAND_318;
|
|
reg [31:0] _RAND_319;
|
|
reg [31:0] _RAND_320;
|
|
reg [31:0] _RAND_321;
|
|
reg [31:0] _RAND_322;
|
|
reg [31:0] _RAND_323;
|
|
reg [31:0] _RAND_324;
|
|
reg [31:0] _RAND_325;
|
|
reg [31:0] _RAND_326;
|
|
reg [31:0] _RAND_327;
|
|
reg [31:0] _RAND_328;
|
|
reg [31:0] _RAND_329;
|
|
reg [31:0] _RAND_330;
|
|
reg [31:0] _RAND_331;
|
|
reg [31:0] _RAND_332;
|
|
reg [31:0] _RAND_333;
|
|
reg [31:0] _RAND_334;
|
|
reg [31:0] _RAND_335;
|
|
reg [31:0] _RAND_336;
|
|
reg [31:0] _RAND_337;
|
|
reg [31:0] _RAND_338;
|
|
reg [31:0] _RAND_339;
|
|
reg [31:0] _RAND_340;
|
|
reg [31:0] _RAND_341;
|
|
reg [31:0] _RAND_342;
|
|
reg [31:0] _RAND_343;
|
|
reg [31:0] _RAND_344;
|
|
reg [31:0] _RAND_345;
|
|
reg [31:0] _RAND_346;
|
|
reg [31:0] _RAND_347;
|
|
reg [31:0] _RAND_348;
|
|
reg [31:0] _RAND_349;
|
|
reg [31:0] _RAND_350;
|
|
reg [31:0] _RAND_351;
|
|
reg [31:0] _RAND_352;
|
|
reg [31:0] _RAND_353;
|
|
reg [31:0] _RAND_354;
|
|
reg [31:0] _RAND_355;
|
|
reg [31:0] _RAND_356;
|
|
reg [31:0] _RAND_357;
|
|
reg [31:0] _RAND_358;
|
|
reg [31:0] _RAND_359;
|
|
reg [31:0] _RAND_360;
|
|
reg [31:0] _RAND_361;
|
|
reg [31:0] _RAND_362;
|
|
reg [31:0] _RAND_363;
|
|
reg [31:0] _RAND_364;
|
|
reg [31:0] _RAND_365;
|
|
reg [31:0] _RAND_366;
|
|
reg [31:0] _RAND_367;
|
|
reg [31:0] _RAND_368;
|
|
reg [31:0] _RAND_369;
|
|
reg [31:0] _RAND_370;
|
|
reg [31:0] _RAND_371;
|
|
reg [31:0] _RAND_372;
|
|
reg [31:0] _RAND_373;
|
|
reg [31:0] _RAND_374;
|
|
reg [31:0] _RAND_375;
|
|
reg [31:0] _RAND_376;
|
|
reg [31:0] _RAND_377;
|
|
reg [31:0] _RAND_378;
|
|
reg [31:0] _RAND_379;
|
|
reg [31:0] _RAND_380;
|
|
reg [31:0] _RAND_381;
|
|
reg [31:0] _RAND_382;
|
|
reg [31:0] _RAND_383;
|
|
reg [31:0] _RAND_384;
|
|
reg [31:0] _RAND_385;
|
|
reg [31:0] _RAND_386;
|
|
reg [31:0] _RAND_387;
|
|
reg [31:0] _RAND_388;
|
|
reg [31:0] _RAND_389;
|
|
reg [31:0] _RAND_390;
|
|
reg [31:0] _RAND_391;
|
|
reg [31:0] _RAND_392;
|
|
reg [31:0] _RAND_393;
|
|
reg [31:0] _RAND_394;
|
|
reg [31:0] _RAND_395;
|
|
reg [31:0] _RAND_396;
|
|
reg [31:0] _RAND_397;
|
|
reg [31:0] _RAND_398;
|
|
reg [31:0] _RAND_399;
|
|
reg [31:0] _RAND_400;
|
|
reg [31:0] _RAND_401;
|
|
reg [31:0] _RAND_402;
|
|
reg [31:0] _RAND_403;
|
|
reg [31:0] _RAND_404;
|
|
reg [31:0] _RAND_405;
|
|
reg [31:0] _RAND_406;
|
|
reg [31:0] _RAND_407;
|
|
reg [31:0] _RAND_408;
|
|
reg [31:0] _RAND_409;
|
|
reg [31:0] _RAND_410;
|
|
reg [31:0] _RAND_411;
|
|
reg [31:0] _RAND_412;
|
|
reg [31:0] _RAND_413;
|
|
reg [31:0] _RAND_414;
|
|
reg [31:0] _RAND_415;
|
|
reg [31:0] _RAND_416;
|
|
reg [31:0] _RAND_417;
|
|
reg [31:0] _RAND_418;
|
|
reg [31:0] _RAND_419;
|
|
reg [31:0] _RAND_420;
|
|
reg [31:0] _RAND_421;
|
|
reg [31:0] _RAND_422;
|
|
reg [31:0] _RAND_423;
|
|
reg [31:0] _RAND_424;
|
|
reg [31:0] _RAND_425;
|
|
reg [31:0] _RAND_426;
|
|
reg [31:0] _RAND_427;
|
|
reg [31:0] _RAND_428;
|
|
reg [31:0] _RAND_429;
|
|
reg [31:0] _RAND_430;
|
|
reg [31:0] _RAND_431;
|
|
reg [31:0] _RAND_432;
|
|
reg [31:0] _RAND_433;
|
|
reg [31:0] _RAND_434;
|
|
reg [31:0] _RAND_435;
|
|
reg [31:0] _RAND_436;
|
|
reg [31:0] _RAND_437;
|
|
reg [31:0] _RAND_438;
|
|
reg [31:0] _RAND_439;
|
|
reg [31:0] _RAND_440;
|
|
reg [31:0] _RAND_441;
|
|
reg [31:0] _RAND_442;
|
|
reg [31:0] _RAND_443;
|
|
reg [31:0] _RAND_444;
|
|
reg [31:0] _RAND_445;
|
|
reg [31:0] _RAND_446;
|
|
reg [31:0] _RAND_447;
|
|
reg [31:0] _RAND_448;
|
|
reg [31:0] _RAND_449;
|
|
reg [31:0] _RAND_450;
|
|
reg [31:0] _RAND_451;
|
|
reg [31:0] _RAND_452;
|
|
reg [31:0] _RAND_453;
|
|
reg [31:0] _RAND_454;
|
|
reg [31:0] _RAND_455;
|
|
reg [31:0] _RAND_456;
|
|
reg [31:0] _RAND_457;
|
|
reg [31:0] _RAND_458;
|
|
reg [31:0] _RAND_459;
|
|
reg [31:0] _RAND_460;
|
|
reg [31:0] _RAND_461;
|
|
reg [31:0] _RAND_462;
|
|
reg [31:0] _RAND_463;
|
|
reg [31:0] _RAND_464;
|
|
reg [31:0] _RAND_465;
|
|
reg [31:0] _RAND_466;
|
|
reg [31:0] _RAND_467;
|
|
reg [31:0] _RAND_468;
|
|
reg [31:0] _RAND_469;
|
|
reg [31:0] _RAND_470;
|
|
reg [31:0] _RAND_471;
|
|
reg [31:0] _RAND_472;
|
|
reg [31:0] _RAND_473;
|
|
reg [31:0] _RAND_474;
|
|
reg [31:0] _RAND_475;
|
|
reg [31:0] _RAND_476;
|
|
reg [31:0] _RAND_477;
|
|
reg [31:0] _RAND_478;
|
|
reg [31:0] _RAND_479;
|
|
reg [31:0] _RAND_480;
|
|
reg [31:0] _RAND_481;
|
|
reg [31:0] _RAND_482;
|
|
reg [31:0] _RAND_483;
|
|
reg [31:0] _RAND_484;
|
|
reg [31:0] _RAND_485;
|
|
reg [31:0] _RAND_486;
|
|
reg [31:0] _RAND_487;
|
|
reg [31:0] _RAND_488;
|
|
reg [31:0] _RAND_489;
|
|
reg [31:0] _RAND_490;
|
|
reg [31:0] _RAND_491;
|
|
reg [31:0] _RAND_492;
|
|
reg [31:0] _RAND_493;
|
|
reg [31:0] _RAND_494;
|
|
reg [31:0] _RAND_495;
|
|
reg [31:0] _RAND_496;
|
|
reg [31:0] _RAND_497;
|
|
reg [31:0] _RAND_498;
|
|
reg [31:0] _RAND_499;
|
|
reg [31:0] _RAND_500;
|
|
reg [31:0] _RAND_501;
|
|
reg [31:0] _RAND_502;
|
|
reg [31:0] _RAND_503;
|
|
reg [31:0] _RAND_504;
|
|
reg [31:0] _RAND_505;
|
|
reg [31:0] _RAND_506;
|
|
reg [31:0] _RAND_507;
|
|
reg [31:0] _RAND_508;
|
|
reg [31:0] _RAND_509;
|
|
reg [31:0] _RAND_510;
|
|
reg [31:0] _RAND_511;
|
|
reg [31:0] _RAND_512;
|
|
reg [31:0] _RAND_513;
|
|
reg [31:0] _RAND_514;
|
|
reg [31:0] _RAND_515;
|
|
reg [31:0] _RAND_516;
|
|
reg [31:0] _RAND_517;
|
|
reg [31:0] _RAND_518;
|
|
reg [31:0] _RAND_519;
|
|
reg [31:0] _RAND_520;
|
|
reg [31:0] _RAND_521;
|
|
reg [31:0] _RAND_522;
|
|
reg [31:0] _RAND_523;
|
|
reg [31:0] _RAND_524;
|
|
reg [31:0] _RAND_525;
|
|
reg [31:0] _RAND_526;
|
|
reg [31:0] _RAND_527;
|
|
reg [31:0] _RAND_528;
|
|
reg [31:0] _RAND_529;
|
|
reg [31:0] _RAND_530;
|
|
reg [31:0] _RAND_531;
|
|
reg [31:0] _RAND_532;
|
|
reg [31:0] _RAND_533;
|
|
reg [31:0] _RAND_534;
|
|
reg [31:0] _RAND_535;
|
|
reg [31:0] _RAND_536;
|
|
reg [31:0] _RAND_537;
|
|
reg [31:0] _RAND_538;
|
|
reg [31:0] _RAND_539;
|
|
reg [31:0] _RAND_540;
|
|
reg [31:0] _RAND_541;
|
|
reg [31:0] _RAND_542;
|
|
reg [31:0] _RAND_543;
|
|
reg [31:0] _RAND_544;
|
|
reg [31:0] _RAND_545;
|
|
reg [31:0] _RAND_546;
|
|
reg [31:0] _RAND_547;
|
|
reg [31:0] _RAND_548;
|
|
reg [31:0] _RAND_549;
|
|
reg [31:0] _RAND_550;
|
|
reg [31:0] _RAND_551;
|
|
reg [31:0] _RAND_552;
|
|
reg [31:0] _RAND_553;
|
|
reg [31:0] _RAND_554;
|
|
reg [31:0] _RAND_555;
|
|
reg [31:0] _RAND_556;
|
|
reg [31:0] _RAND_557;
|
|
reg [31:0] _RAND_558;
|
|
reg [31:0] _RAND_559;
|
|
reg [31:0] _RAND_560;
|
|
reg [31:0] _RAND_561;
|
|
reg [31:0] _RAND_562;
|
|
reg [31:0] _RAND_563;
|
|
reg [31:0] _RAND_564;
|
|
reg [31:0] _RAND_565;
|
|
reg [31:0] _RAND_566;
|
|
reg [31:0] _RAND_567;
|
|
reg [31:0] _RAND_568;
|
|
reg [31:0] _RAND_569;
|
|
reg [31:0] _RAND_570;
|
|
reg [31:0] _RAND_571;
|
|
reg [31:0] _RAND_572;
|
|
reg [31:0] _RAND_573;
|
|
reg [31:0] _RAND_574;
|
|
reg [31:0] _RAND_575;
|
|
reg [31:0] _RAND_576;
|
|
reg [31:0] _RAND_577;
|
|
reg [31:0] _RAND_578;
|
|
reg [31:0] _RAND_579;
|
|
reg [31:0] _RAND_580;
|
|
reg [31:0] _RAND_581;
|
|
reg [31:0] _RAND_582;
|
|
reg [31:0] _RAND_583;
|
|
reg [31:0] _RAND_584;
|
|
reg [31:0] _RAND_585;
|
|
reg [31:0] _RAND_586;
|
|
reg [31:0] _RAND_587;
|
|
reg [31:0] _RAND_588;
|
|
reg [31:0] _RAND_589;
|
|
reg [31:0] _RAND_590;
|
|
reg [31:0] _RAND_591;
|
|
reg [31:0] _RAND_592;
|
|
reg [31:0] _RAND_593;
|
|
reg [31:0] _RAND_594;
|
|
reg [31:0] _RAND_595;
|
|
reg [31:0] _RAND_596;
|
|
reg [31:0] _RAND_597;
|
|
reg [31:0] _RAND_598;
|
|
reg [31:0] _RAND_599;
|
|
reg [31:0] _RAND_600;
|
|
reg [31:0] _RAND_601;
|
|
reg [31:0] _RAND_602;
|
|
reg [31:0] _RAND_603;
|
|
reg [31:0] _RAND_604;
|
|
reg [31:0] _RAND_605;
|
|
reg [31:0] _RAND_606;
|
|
reg [31:0] _RAND_607;
|
|
reg [31:0] _RAND_608;
|
|
reg [31:0] _RAND_609;
|
|
reg [31:0] _RAND_610;
|
|
reg [31:0] _RAND_611;
|
|
reg [31:0] _RAND_612;
|
|
reg [31:0] _RAND_613;
|
|
reg [31:0] _RAND_614;
|
|
reg [31:0] _RAND_615;
|
|
reg [31:0] _RAND_616;
|
|
reg [31:0] _RAND_617;
|
|
reg [31:0] _RAND_618;
|
|
reg [31:0] _RAND_619;
|
|
reg [31:0] _RAND_620;
|
|
reg [31:0] _RAND_621;
|
|
reg [31:0] _RAND_622;
|
|
reg [31:0] _RAND_623;
|
|
reg [31:0] _RAND_624;
|
|
reg [31:0] _RAND_625;
|
|
reg [31:0] _RAND_626;
|
|
reg [31:0] _RAND_627;
|
|
reg [31:0] _RAND_628;
|
|
reg [31:0] _RAND_629;
|
|
reg [31:0] _RAND_630;
|
|
reg [31:0] _RAND_631;
|
|
reg [31:0] _RAND_632;
|
|
reg [31:0] _RAND_633;
|
|
reg [31:0] _RAND_634;
|
|
reg [31:0] _RAND_635;
|
|
reg [31:0] _RAND_636;
|
|
reg [31:0] _RAND_637;
|
|
reg [31:0] _RAND_638;
|
|
reg [31:0] _RAND_639;
|
|
reg [31:0] _RAND_640;
|
|
reg [31:0] _RAND_641;
|
|
reg [31:0] _RAND_642;
|
|
reg [31:0] _RAND_643;
|
|
reg [31:0] _RAND_644;
|
|
reg [31:0] _RAND_645;
|
|
reg [31:0] _RAND_646;
|
|
reg [31:0] _RAND_647;
|
|
reg [31:0] _RAND_648;
|
|
reg [31:0] _RAND_649;
|
|
reg [31:0] _RAND_650;
|
|
reg [31:0] _RAND_651;
|
|
reg [31:0] _RAND_652;
|
|
reg [31:0] _RAND_653;
|
|
reg [31:0] _RAND_654;
|
|
reg [31:0] _RAND_655;
|
|
reg [31:0] _RAND_656;
|
|
reg [31:0] _RAND_657;
|
|
reg [31:0] _RAND_658;
|
|
reg [31:0] _RAND_659;
|
|
reg [31:0] _RAND_660;
|
|
reg [31:0] _RAND_661;
|
|
reg [31:0] _RAND_662;
|
|
reg [31:0] _RAND_663;
|
|
reg [31:0] _RAND_664;
|
|
reg [31:0] _RAND_665;
|
|
reg [31:0] _RAND_666;
|
|
reg [31:0] _RAND_667;
|
|
reg [31:0] _RAND_668;
|
|
reg [31:0] _RAND_669;
|
|
reg [31:0] _RAND_670;
|
|
reg [31:0] _RAND_671;
|
|
reg [31:0] _RAND_672;
|
|
reg [31:0] _RAND_673;
|
|
reg [31:0] _RAND_674;
|
|
reg [31:0] _RAND_675;
|
|
reg [31:0] _RAND_676;
|
|
reg [31:0] _RAND_677;
|
|
reg [31:0] _RAND_678;
|
|
reg [31:0] _RAND_679;
|
|
reg [31:0] _RAND_680;
|
|
reg [31:0] _RAND_681;
|
|
reg [31:0] _RAND_682;
|
|
reg [31:0] _RAND_683;
|
|
reg [31:0] _RAND_684;
|
|
reg [31:0] _RAND_685;
|
|
reg [31:0] _RAND_686;
|
|
reg [31:0] _RAND_687;
|
|
reg [31:0] _RAND_688;
|
|
reg [31:0] _RAND_689;
|
|
reg [31:0] _RAND_690;
|
|
reg [31:0] _RAND_691;
|
|
reg [31:0] _RAND_692;
|
|
reg [31:0] _RAND_693;
|
|
reg [31:0] _RAND_694;
|
|
reg [31:0] _RAND_695;
|
|
reg [31:0] _RAND_696;
|
|
reg [31:0] _RAND_697;
|
|
reg [31:0] _RAND_698;
|
|
reg [31:0] _RAND_699;
|
|
reg [31:0] _RAND_700;
|
|
reg [31:0] _RAND_701;
|
|
reg [31:0] _RAND_702;
|
|
reg [31:0] _RAND_703;
|
|
reg [31:0] _RAND_704;
|
|
reg [31:0] _RAND_705;
|
|
reg [31:0] _RAND_706;
|
|
reg [31:0] _RAND_707;
|
|
reg [31:0] _RAND_708;
|
|
reg [31:0] _RAND_709;
|
|
reg [31:0] _RAND_710;
|
|
reg [31:0] _RAND_711;
|
|
reg [31:0] _RAND_712;
|
|
reg [31:0] _RAND_713;
|
|
reg [31:0] _RAND_714;
|
|
reg [31:0] _RAND_715;
|
|
reg [31:0] _RAND_716;
|
|
reg [31:0] _RAND_717;
|
|
reg [31:0] _RAND_718;
|
|
reg [31:0] _RAND_719;
|
|
reg [31:0] _RAND_720;
|
|
reg [31:0] _RAND_721;
|
|
reg [31:0] _RAND_722;
|
|
reg [31:0] _RAND_723;
|
|
reg [31:0] _RAND_724;
|
|
reg [31:0] _RAND_725;
|
|
reg [31:0] _RAND_726;
|
|
reg [31:0] _RAND_727;
|
|
reg [31:0] _RAND_728;
|
|
reg [31:0] _RAND_729;
|
|
reg [31:0] _RAND_730;
|
|
reg [31:0] _RAND_731;
|
|
reg [31:0] _RAND_732;
|
|
reg [31:0] _RAND_733;
|
|
reg [31:0] _RAND_734;
|
|
reg [31:0] _RAND_735;
|
|
reg [31:0] _RAND_736;
|
|
reg [31:0] _RAND_737;
|
|
reg [31:0] _RAND_738;
|
|
reg [31:0] _RAND_739;
|
|
reg [31:0] _RAND_740;
|
|
reg [31:0] _RAND_741;
|
|
reg [31:0] _RAND_742;
|
|
reg [31:0] _RAND_743;
|
|
reg [31:0] _RAND_744;
|
|
reg [31:0] _RAND_745;
|
|
reg [31:0] _RAND_746;
|
|
reg [31:0] _RAND_747;
|
|
reg [31:0] _RAND_748;
|
|
reg [31:0] _RAND_749;
|
|
reg [31:0] _RAND_750;
|
|
reg [31:0] _RAND_751;
|
|
reg [31:0] _RAND_752;
|
|
reg [31:0] _RAND_753;
|
|
reg [31:0] _RAND_754;
|
|
reg [31:0] _RAND_755;
|
|
reg [31:0] _RAND_756;
|
|
reg [31:0] _RAND_757;
|
|
reg [31:0] _RAND_758;
|
|
reg [31:0] _RAND_759;
|
|
reg [31:0] _RAND_760;
|
|
reg [31:0] _RAND_761;
|
|
reg [31:0] _RAND_762;
|
|
reg [31:0] _RAND_763;
|
|
reg [31:0] _RAND_764;
|
|
reg [31:0] _RAND_765;
|
|
reg [31:0] _RAND_766;
|
|
reg [31:0] _RAND_767;
|
|
reg [31:0] _RAND_768;
|
|
reg [31:0] _RAND_769;
|
|
reg [31:0] _RAND_770;
|
|
reg [31:0] _RAND_771;
|
|
reg [31:0] _RAND_772;
|
|
reg [31:0] _RAND_773;
|
|
reg [31:0] _RAND_774;
|
|
reg [31:0] _RAND_775;
|
|
reg [31:0] _RAND_776;
|
|
reg [31:0] _RAND_777;
|
|
reg [31:0] _RAND_778;
|
|
reg [31:0] _RAND_779;
|
|
reg [31:0] _RAND_780;
|
|
reg [31:0] _RAND_781;
|
|
reg [31:0] _RAND_782;
|
|
reg [31:0] _RAND_783;
|
|
reg [31:0] _RAND_784;
|
|
reg [31:0] _RAND_785;
|
|
reg [31:0] _RAND_786;
|
|
reg [31:0] _RAND_787;
|
|
reg [31:0] _RAND_788;
|
|
reg [31:0] _RAND_789;
|
|
reg [31:0] _RAND_790;
|
|
reg [31:0] _RAND_791;
|
|
reg [31:0] _RAND_792;
|
|
reg [31:0] _RAND_793;
|
|
reg [31:0] _RAND_794;
|
|
reg [31:0] _RAND_795;
|
|
reg [31:0] _RAND_796;
|
|
reg [31:0] _RAND_797;
|
|
reg [31:0] _RAND_798;
|
|
reg [31:0] _RAND_799;
|
|
reg [31:0] _RAND_800;
|
|
reg [31:0] _RAND_801;
|
|
reg [31:0] _RAND_802;
|
|
reg [31:0] _RAND_803;
|
|
reg [31:0] _RAND_804;
|
|
reg [31:0] _RAND_805;
|
|
reg [31:0] _RAND_806;
|
|
reg [31:0] _RAND_807;
|
|
reg [31:0] _RAND_808;
|
|
reg [31:0] _RAND_809;
|
|
reg [31:0] _RAND_810;
|
|
reg [31:0] _RAND_811;
|
|
reg [31:0] _RAND_812;
|
|
reg [31:0] _RAND_813;
|
|
reg [31:0] _RAND_814;
|
|
reg [31:0] _RAND_815;
|
|
reg [31:0] _RAND_816;
|
|
reg [31:0] _RAND_817;
|
|
reg [31:0] _RAND_818;
|
|
reg [31:0] _RAND_819;
|
|
reg [31:0] _RAND_820;
|
|
reg [31:0] _RAND_821;
|
|
reg [31:0] _RAND_822;
|
|
reg [31:0] _RAND_823;
|
|
reg [31:0] _RAND_824;
|
|
reg [31:0] _RAND_825;
|
|
reg [31:0] _RAND_826;
|
|
reg [31:0] _RAND_827;
|
|
reg [31:0] _RAND_828;
|
|
reg [31:0] _RAND_829;
|
|
reg [31:0] _RAND_830;
|
|
reg [31:0] _RAND_831;
|
|
reg [31:0] _RAND_832;
|
|
reg [31:0] _RAND_833;
|
|
reg [31:0] _RAND_834;
|
|
reg [31:0] _RAND_835;
|
|
reg [31:0] _RAND_836;
|
|
reg [31:0] _RAND_837;
|
|
reg [31:0] _RAND_838;
|
|
reg [31:0] _RAND_839;
|
|
reg [31:0] _RAND_840;
|
|
reg [31:0] _RAND_841;
|
|
reg [31:0] _RAND_842;
|
|
reg [31:0] _RAND_843;
|
|
reg [31:0] _RAND_844;
|
|
reg [31:0] _RAND_845;
|
|
reg [31:0] _RAND_846;
|
|
reg [31:0] _RAND_847;
|
|
reg [31:0] _RAND_848;
|
|
reg [31:0] _RAND_849;
|
|
reg [31:0] _RAND_850;
|
|
reg [31:0] _RAND_851;
|
|
reg [31:0] _RAND_852;
|
|
reg [31:0] _RAND_853;
|
|
reg [31:0] _RAND_854;
|
|
reg [31:0] _RAND_855;
|
|
reg [31:0] _RAND_856;
|
|
reg [31:0] _RAND_857;
|
|
reg [31:0] _RAND_858;
|
|
reg [31:0] _RAND_859;
|
|
reg [31:0] _RAND_860;
|
|
reg [31:0] _RAND_861;
|
|
reg [31:0] _RAND_862;
|
|
reg [31:0] _RAND_863;
|
|
reg [31:0] _RAND_864;
|
|
reg [31:0] _RAND_865;
|
|
reg [31:0] _RAND_866;
|
|
reg [31:0] _RAND_867;
|
|
reg [31:0] _RAND_868;
|
|
reg [31:0] _RAND_869;
|
|
reg [31:0] _RAND_870;
|
|
reg [31:0] _RAND_871;
|
|
reg [31:0] _RAND_872;
|
|
reg [31:0] _RAND_873;
|
|
reg [31:0] _RAND_874;
|
|
reg [31:0] _RAND_875;
|
|
reg [31:0] _RAND_876;
|
|
reg [31:0] _RAND_877;
|
|
reg [31:0] _RAND_878;
|
|
reg [31:0] _RAND_879;
|
|
reg [31:0] _RAND_880;
|
|
reg [31:0] _RAND_881;
|
|
reg [31:0] _RAND_882;
|
|
reg [31:0] _RAND_883;
|
|
reg [31:0] _RAND_884;
|
|
reg [31:0] _RAND_885;
|
|
reg [31:0] _RAND_886;
|
|
reg [31:0] _RAND_887;
|
|
reg [31:0] _RAND_888;
|
|
reg [31:0] _RAND_889;
|
|
reg [31:0] _RAND_890;
|
|
reg [31:0] _RAND_891;
|
|
reg [31:0] _RAND_892;
|
|
reg [31:0] _RAND_893;
|
|
reg [31:0] _RAND_894;
|
|
reg [31:0] _RAND_895;
|
|
reg [31:0] _RAND_896;
|
|
reg [31:0] _RAND_897;
|
|
reg [31:0] _RAND_898;
|
|
reg [31:0] _RAND_899;
|
|
reg [31:0] _RAND_900;
|
|
reg [31:0] _RAND_901;
|
|
reg [31:0] _RAND_902;
|
|
reg [31:0] _RAND_903;
|
|
reg [31:0] _RAND_904;
|
|
reg [31:0] _RAND_905;
|
|
reg [31:0] _RAND_906;
|
|
reg [31:0] _RAND_907;
|
|
reg [31:0] _RAND_908;
|
|
reg [31:0] _RAND_909;
|
|
reg [31:0] _RAND_910;
|
|
reg [31:0] _RAND_911;
|
|
reg [31:0] _RAND_912;
|
|
reg [31:0] _RAND_913;
|
|
reg [31:0] _RAND_914;
|
|
reg [31:0] _RAND_915;
|
|
reg [31:0] _RAND_916;
|
|
reg [31:0] _RAND_917;
|
|
reg [31:0] _RAND_918;
|
|
reg [31:0] _RAND_919;
|
|
reg [31:0] _RAND_920;
|
|
reg [31:0] _RAND_921;
|
|
reg [31:0] _RAND_922;
|
|
reg [31:0] _RAND_923;
|
|
reg [31:0] _RAND_924;
|
|
reg [31:0] _RAND_925;
|
|
reg [31:0] _RAND_926;
|
|
reg [31:0] _RAND_927;
|
|
reg [31:0] _RAND_928;
|
|
reg [31:0] _RAND_929;
|
|
reg [31:0] _RAND_930;
|
|
reg [31:0] _RAND_931;
|
|
reg [31:0] _RAND_932;
|
|
reg [31:0] _RAND_933;
|
|
reg [31:0] _RAND_934;
|
|
reg [31:0] _RAND_935;
|
|
reg [31:0] _RAND_936;
|
|
reg [31:0] _RAND_937;
|
|
reg [31:0] _RAND_938;
|
|
reg [31:0] _RAND_939;
|
|
reg [31:0] _RAND_940;
|
|
reg [31:0] _RAND_941;
|
|
reg [31:0] _RAND_942;
|
|
reg [31:0] _RAND_943;
|
|
reg [31:0] _RAND_944;
|
|
reg [31:0] _RAND_945;
|
|
reg [31:0] _RAND_946;
|
|
reg [31:0] _RAND_947;
|
|
reg [31:0] _RAND_948;
|
|
reg [31:0] _RAND_949;
|
|
reg [31:0] _RAND_950;
|
|
reg [31:0] _RAND_951;
|
|
reg [31:0] _RAND_952;
|
|
reg [31:0] _RAND_953;
|
|
reg [31:0] _RAND_954;
|
|
reg [31:0] _RAND_955;
|
|
reg [31:0] _RAND_956;
|
|
reg [31:0] _RAND_957;
|
|
reg [31:0] _RAND_958;
|
|
reg [31:0] _RAND_959;
|
|
reg [31:0] _RAND_960;
|
|
reg [31:0] _RAND_961;
|
|
reg [31:0] _RAND_962;
|
|
reg [31:0] _RAND_963;
|
|
reg [31:0] _RAND_964;
|
|
reg [31:0] _RAND_965;
|
|
reg [31:0] _RAND_966;
|
|
reg [31:0] _RAND_967;
|
|
reg [31:0] _RAND_968;
|
|
reg [31:0] _RAND_969;
|
|
reg [31:0] _RAND_970;
|
|
reg [31:0] _RAND_971;
|
|
reg [31:0] _RAND_972;
|
|
reg [31:0] _RAND_973;
|
|
reg [31:0] _RAND_974;
|
|
reg [31:0] _RAND_975;
|
|
reg [31:0] _RAND_976;
|
|
reg [31:0] _RAND_977;
|
|
reg [31:0] _RAND_978;
|
|
reg [31:0] _RAND_979;
|
|
reg [31:0] _RAND_980;
|
|
reg [31:0] _RAND_981;
|
|
reg [31:0] _RAND_982;
|
|
reg [31:0] _RAND_983;
|
|
reg [31:0] _RAND_984;
|
|
reg [31:0] _RAND_985;
|
|
reg [31:0] _RAND_986;
|
|
reg [31:0] _RAND_987;
|
|
reg [31:0] _RAND_988;
|
|
reg [31:0] _RAND_989;
|
|
reg [31:0] _RAND_990;
|
|
reg [31:0] _RAND_991;
|
|
reg [31:0] _RAND_992;
|
|
reg [31:0] _RAND_993;
|
|
reg [31:0] _RAND_994;
|
|
reg [31:0] _RAND_995;
|
|
reg [31:0] _RAND_996;
|
|
reg [31:0] _RAND_997;
|
|
reg [31:0] _RAND_998;
|
|
reg [31:0] _RAND_999;
|
|
reg [31:0] _RAND_1000;
|
|
reg [31:0] _RAND_1001;
|
|
reg [31:0] _RAND_1002;
|
|
reg [31:0] _RAND_1003;
|
|
reg [31:0] _RAND_1004;
|
|
reg [31:0] _RAND_1005;
|
|
reg [31:0] _RAND_1006;
|
|
reg [31:0] _RAND_1007;
|
|
reg [31:0] _RAND_1008;
|
|
reg [31:0] _RAND_1009;
|
|
reg [31:0] _RAND_1010;
|
|
reg [31:0] _RAND_1011;
|
|
reg [31:0] _RAND_1012;
|
|
reg [31:0] _RAND_1013;
|
|
reg [31:0] _RAND_1014;
|
|
reg [31:0] _RAND_1015;
|
|
reg [31:0] _RAND_1016;
|
|
reg [31:0] _RAND_1017;
|
|
reg [31:0] _RAND_1018;
|
|
reg [31:0] _RAND_1019;
|
|
reg [31:0] _RAND_1020;
|
|
reg [31:0] _RAND_1021;
|
|
reg [31:0] _RAND_1022;
|
|
reg [31:0] _RAND_1023;
|
|
reg [31:0] _RAND_1024;
|
|
reg [31:0] _RAND_1025;
|
|
reg [31:0] _RAND_1026;
|
|
reg [255:0] _RAND_1027;
|
|
reg [31:0] _RAND_1028;
|
|
reg [31:0] _RAND_1029;
|
|
reg [31:0] _RAND_1030;
|
|
reg [31:0] _RAND_1031;
|
|
reg [31:0] _RAND_1032;
|
|
reg [31:0] _RAND_1033;
|
|
reg [31:0] _RAND_1034;
|
|
reg [31:0] _RAND_1035;
|
|
reg [31:0] _RAND_1036;
|
|
reg [31:0] _RAND_1037;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_35_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_35_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_36_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_36_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_37_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_37_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_38_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_38_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_39_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_39_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_40_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_40_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_41_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_41_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_42_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_42_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_43_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_43_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_44_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_44_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_45_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_45_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_46_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_46_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_47_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_47_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_48_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_48_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_49_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_49_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_50_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_50_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_51_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_51_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_52_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_52_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_53_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_53_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_54_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_54_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_55_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_55_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_56_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_56_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_57_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_57_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_58_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_58_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_59_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_59_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_60_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_60_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_61_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_61_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_62_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_62_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_63_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_63_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_64_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_64_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_65_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_65_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_66_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_66_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_67_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_67_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_68_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_68_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_69_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_69_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_70_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_70_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_71_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_71_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_72_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_72_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_73_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_73_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_74_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_74_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_75_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_75_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_76_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_76_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_77_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_77_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_78_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_78_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_79_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_79_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_80_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_80_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_81_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_81_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_82_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_82_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_83_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_83_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_84_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_84_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_85_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_85_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_86_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_86_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_87_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_87_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_88_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_88_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_89_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_89_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_90_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_90_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_91_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_91_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_92_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_92_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_93_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_93_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_94_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_94_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_95_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_95_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_96_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_96_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_97_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_97_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_98_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_98_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_99_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_99_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_100_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_100_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_101_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_101_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_102_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_102_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_103_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_103_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_104_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_104_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_105_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_105_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_106_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_106_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_107_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_107_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_108_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_108_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_109_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_109_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_110_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_110_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_111_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_111_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_112_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_112_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_113_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_113_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_114_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_114_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_115_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_115_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_116_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_116_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_117_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_117_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_118_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_118_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_119_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_119_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_120_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_120_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_121_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_121_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_122_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_122_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_123_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_123_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_124_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_124_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_125_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_125_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_126_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_126_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_127_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_127_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_128_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_128_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_129_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_129_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_130_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_130_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_131_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_131_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_132_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_132_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_133_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_133_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_134_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_134_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_135_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_135_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_136_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_136_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_137_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_137_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_138_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_138_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_139_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_139_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_140_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_140_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_141_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_141_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_142_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_142_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_143_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_143_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_144_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_144_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_145_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_145_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_146_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_146_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_147_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_147_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_148_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_148_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_149_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_149_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_150_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_150_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_151_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_151_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_152_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_152_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_153_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_153_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_154_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_154_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_155_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_155_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_156_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_156_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_157_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_157_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_158_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_158_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_159_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_159_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_160_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_160_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_161_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_161_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_162_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_162_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_163_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_163_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_164_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_164_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_165_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_165_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_166_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_166_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_167_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_167_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_168_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_168_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_169_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_169_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_170_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_170_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_171_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_171_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_172_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_172_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_173_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_173_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_174_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_174_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_175_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_175_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_176_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_176_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_177_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_177_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_178_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_178_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_179_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_179_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_180_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_180_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_181_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_181_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_182_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_182_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_183_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_183_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_184_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_184_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_185_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_185_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_186_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_186_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_187_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_187_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_188_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_188_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_189_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_189_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_190_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_190_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_191_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_191_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_192_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_192_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_193_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_193_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_194_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_194_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_195_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_195_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_196_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_196_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_197_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_197_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_198_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_198_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_199_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_199_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_200_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_200_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_201_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_201_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_202_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_202_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_203_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_203_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_204_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_204_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_205_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_205_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_206_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_206_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_207_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_207_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_208_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_208_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_209_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_209_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_210_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_210_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_211_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_211_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_212_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_212_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_213_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_213_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_214_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_214_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_215_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_215_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_216_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_216_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_217_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_217_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_218_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_218_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_219_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_219_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_220_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_220_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_221_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_221_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_222_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_222_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_223_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_223_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_224_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_224_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_225_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_225_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_226_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_226_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_227_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_227_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_228_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_228_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_229_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_229_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_230_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_230_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_231_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_231_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_232_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_232_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_233_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_233_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_234_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_234_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_235_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_235_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_236_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_236_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_237_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_237_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_238_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_238_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_239_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_239_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_240_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_240_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_241_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_241_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_242_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_242_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_243_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_243_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_244_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_244_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_245_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_245_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_246_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_246_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_247_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_247_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_248_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_248_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_249_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_249_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_250_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_250_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_251_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_251_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_252_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_252_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_253_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_253_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_254_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_254_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_255_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_255_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_256_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_256_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_257_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_257_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_258_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_258_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_259_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_259_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_260_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_260_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_261_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_261_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_262_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_262_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_263_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_263_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_264_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_264_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_265_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_265_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_266_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_266_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_267_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_267_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_268_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_268_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_269_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_269_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_270_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_270_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_271_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_271_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_272_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_272_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_273_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_273_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_274_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_274_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_275_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_275_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_276_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_276_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_277_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_277_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_278_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_278_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_279_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_279_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_280_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_280_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_281_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_281_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_282_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_282_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_283_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_283_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_284_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_284_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_285_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_285_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_286_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_286_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_287_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_287_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_288_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_288_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_289_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_289_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_290_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_290_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_291_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_291_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_292_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_292_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_293_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_293_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_294_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_294_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_295_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_295_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_296_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_296_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_297_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_297_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_298_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_298_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_299_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_299_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_300_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_300_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_301_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_301_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_302_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_302_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_303_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_303_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_304_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_304_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_305_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_305_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_306_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_306_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_307_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_307_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_308_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_308_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_309_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_309_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_310_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_310_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_311_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_311_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_312_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_312_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_313_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_313_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_314_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_314_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_315_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_315_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_316_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_316_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_317_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_317_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_318_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_318_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_319_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_319_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_320_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_320_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_321_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_321_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_322_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_322_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_323_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_323_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_324_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_324_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_325_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_325_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_326_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_326_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_327_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_327_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_328_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_328_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_329_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_329_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_330_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_330_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_331_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_331_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_332_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_332_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_333_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_333_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_334_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_334_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_335_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_335_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_336_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_336_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_337_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_337_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_338_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_338_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_339_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_339_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_340_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_340_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_341_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_341_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_342_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_342_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_343_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_343_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_344_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_344_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_345_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_345_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_346_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_346_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_347_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_347_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_348_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_348_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_349_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_349_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_350_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_350_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_351_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_351_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_352_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_352_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_353_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_353_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_354_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_354_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_355_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_355_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_356_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_356_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_357_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_357_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_358_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_358_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_359_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_359_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_360_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_360_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_361_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_361_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_362_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_362_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_363_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_363_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_364_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_364_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_365_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_365_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_366_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_366_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_367_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_367_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_368_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_368_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_369_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_369_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_370_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_370_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_371_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_371_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_372_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_372_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_373_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_373_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_374_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_374_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_375_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_375_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_376_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_376_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_377_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_377_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_378_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_378_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_379_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_379_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_380_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_380_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_381_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_381_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_382_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_382_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_383_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_383_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_384_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_384_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_385_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_385_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_386_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_386_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_387_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_387_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_388_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_388_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_389_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_389_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_390_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_390_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_391_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_391_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_392_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_392_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_393_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_393_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_394_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_394_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_395_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_395_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_396_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_396_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_397_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_397_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_398_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_398_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_399_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_399_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_400_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_400_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_401_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_401_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_402_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_402_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_403_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_403_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_404_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_404_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_405_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_405_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_406_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_406_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_407_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_407_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_408_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_408_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_409_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_409_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_410_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_410_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_411_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_411_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_412_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_412_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_413_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_413_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_414_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_414_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_415_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_415_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_416_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_416_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_417_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_417_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_418_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_418_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_419_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_419_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_420_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_420_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_421_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_421_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_422_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_422_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_423_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_423_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_424_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_424_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_425_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_425_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_426_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_426_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_427_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_427_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_428_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_428_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_429_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_429_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_430_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_430_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_431_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_431_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_432_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_432_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_433_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_433_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_434_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_434_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_435_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_435_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_436_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_436_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_437_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_437_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_438_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_438_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_439_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_439_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_440_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_440_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_441_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_441_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_442_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_442_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_443_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_443_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_444_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_444_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_445_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_445_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_446_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_446_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_447_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_447_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_448_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_448_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_449_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_449_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_450_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_450_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_451_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_451_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_452_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_452_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_453_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_453_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_454_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_454_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_455_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_455_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_456_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_456_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_457_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_457_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_458_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_458_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_459_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_459_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_460_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_460_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_461_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_461_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_462_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_462_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_463_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_463_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_464_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_464_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_465_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_465_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_466_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_466_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_467_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_467_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_468_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_468_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_469_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_469_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_470_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_470_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_471_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_471_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_472_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_472_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_473_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_473_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_474_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_474_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_475_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_475_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_476_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_476_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_477_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_477_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_478_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_478_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_479_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_479_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_480_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_480_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_481_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_481_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_482_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_482_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_483_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_483_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_484_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_484_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_485_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_485_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_486_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_486_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_487_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_487_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_488_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_488_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_489_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_489_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_490_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_490_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_491_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_491_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_492_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_492_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_493_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_493_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_494_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_494_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_495_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_495_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_496_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_496_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_497_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_497_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_498_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_498_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_499_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_499_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_500_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_500_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_501_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_501_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_502_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_502_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_503_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_503_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_504_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_504_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_505_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_505_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_506_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_506_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_507_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_507_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_508_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_508_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_509_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_509_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_510_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_510_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_511_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_511_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_512_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_512_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_513_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_513_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_514_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_514_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_515_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_515_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_516_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_516_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_517_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_517_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_518_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_518_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_519_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_519_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_520_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_520_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_521_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_521_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_522_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_522_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_523_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_523_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_524_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_524_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_525_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_525_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_526_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_526_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_527_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_527_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_528_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_528_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_529_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_529_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_530_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_530_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_531_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_531_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_532_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_532_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_533_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_533_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_534_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_534_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_535_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_535_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_536_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_536_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_537_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_537_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_538_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_538_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_539_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_539_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_540_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_540_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_541_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_541_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_542_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_542_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_543_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_543_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_544_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_544_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_545_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_545_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_546_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_546_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_547_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_547_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_548_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_548_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_549_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_549_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_550_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_550_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_551_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_551_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_552_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_552_io_en; // @[lib.scala 349:22]
|
|
wire _T_21 = io_dec_bp_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 134:54]
|
|
reg leak_one_f_d1; // @[Reg.scala 27:20]
|
|
wire _T_22 = ~io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 134:102]
|
|
wire _T_23 = leak_one_f_d1 & _T_22; // @[ifu_bp_ctl.scala 134:100]
|
|
wire leak_one_f = _T_21 | _T_23; // @[ifu_bp_ctl.scala 134:83]
|
|
wire _T = ~leak_one_f; // @[ifu_bp_ctl.scala 81:58]
|
|
wire exu_mp_valid = io_exu_bp_exu_mp_pkt_bits_misp & _T; // @[ifu_bp_ctl.scala 81:56]
|
|
wire dec_tlu_error_wb = io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu_bp_ctl.scala 104:50]
|
|
wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[lib.scala 57:47]
|
|
wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[lib.scala 57:85]
|
|
wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_bp_ctl.scala 112:51]
|
|
wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[lib.scala 57:47]
|
|
wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[lib.scala 57:85]
|
|
wire _T_162 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 190:39]
|
|
wire _T_2690 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3202 = _T_2690 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
|
|
wire _T_2692 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3203 = _T_2692 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3458 = _T_3202 | _T_3203; // @[Mux.scala 27:72]
|
|
wire _T_2694 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3204 = _T_2694 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3459 = _T_3458 | _T_3204; // @[Mux.scala 27:72]
|
|
wire _T_2696 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3205 = _T_2696 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3460 = _T_3459 | _T_3205; // @[Mux.scala 27:72]
|
|
wire _T_2698 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3206 = _T_2698 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3461 = _T_3460 | _T_3206; // @[Mux.scala 27:72]
|
|
wire _T_2700 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3207 = _T_2700 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3462 = _T_3461 | _T_3207; // @[Mux.scala 27:72]
|
|
wire _T_2702 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20]
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wire [21:0] _T_3208 = _T_2702 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3463 = _T_3462 | _T_3208; // @[Mux.scala 27:72]
|
|
wire _T_2704 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3209 = _T_2704 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3464 = _T_3463 | _T_3209; // @[Mux.scala 27:72]
|
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wire _T_2706 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3210 = _T_2706 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3465 = _T_3464 | _T_3210; // @[Mux.scala 27:72]
|
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wire _T_2708 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3211 = _T_2708 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3466 = _T_3465 | _T_3211; // @[Mux.scala 27:72]
|
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wire _T_2710 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3212 = _T_2710 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3467 = _T_3466 | _T_3212; // @[Mux.scala 27:72]
|
|
wire _T_2712 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3213 = _T_2712 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3468 = _T_3467 | _T_3213; // @[Mux.scala 27:72]
|
|
wire _T_2714 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3214 = _T_2714 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3469 = _T_3468 | _T_3214; // @[Mux.scala 27:72]
|
|
wire _T_2716 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3215 = _T_2716 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3470 = _T_3469 | _T_3215; // @[Mux.scala 27:72]
|
|
wire _T_2718 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3216 = _T_2718 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3471 = _T_3470 | _T_3216; // @[Mux.scala 27:72]
|
|
wire _T_2720 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3217 = _T_2720 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3472 = _T_3471 | _T_3217; // @[Mux.scala 27:72]
|
|
wire _T_2722 = btb_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_16; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3218 = _T_2722 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3473 = _T_3472 | _T_3218; // @[Mux.scala 27:72]
|
|
wire _T_2724 = btb_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_17; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3219 = _T_2724 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3474 = _T_3473 | _T_3219; // @[Mux.scala 27:72]
|
|
wire _T_2726 = btb_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_18; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3220 = _T_2726 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3475 = _T_3474 | _T_3220; // @[Mux.scala 27:72]
|
|
wire _T_2728 = btb_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_19; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3221 = _T_2728 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3476 = _T_3475 | _T_3221; // @[Mux.scala 27:72]
|
|
wire _T_2730 = btb_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_20; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3222 = _T_2730 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3477 = _T_3476 | _T_3222; // @[Mux.scala 27:72]
|
|
wire _T_2732 = btb_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_21; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3223 = _T_2732 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3478 = _T_3477 | _T_3223; // @[Mux.scala 27:72]
|
|
wire _T_2734 = btb_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_22; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3224 = _T_2734 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3479 = _T_3478 | _T_3224; // @[Mux.scala 27:72]
|
|
wire _T_2736 = btb_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_23; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3225 = _T_2736 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3480 = _T_3479 | _T_3225; // @[Mux.scala 27:72]
|
|
wire _T_2738 = btb_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_24; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3226 = _T_2738 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3481 = _T_3480 | _T_3226; // @[Mux.scala 27:72]
|
|
wire _T_2740 = btb_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_25; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3227 = _T_2740 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3482 = _T_3481 | _T_3227; // @[Mux.scala 27:72]
|
|
wire _T_2742 = btb_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_26; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3228 = _T_2742 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3483 = _T_3482 | _T_3228; // @[Mux.scala 27:72]
|
|
wire _T_2744 = btb_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_27; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3229 = _T_2744 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3484 = _T_3483 | _T_3229; // @[Mux.scala 27:72]
|
|
wire _T_2746 = btb_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_28; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3230 = _T_2746 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3485 = _T_3484 | _T_3230; // @[Mux.scala 27:72]
|
|
wire _T_2748 = btb_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_29; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3231 = _T_2748 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3486 = _T_3485 | _T_3231; // @[Mux.scala 27:72]
|
|
wire _T_2750 = btb_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_30; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3232 = _T_2750 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3487 = _T_3486 | _T_3232; // @[Mux.scala 27:72]
|
|
wire _T_2752 = btb_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_31; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3233 = _T_2752 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3488 = _T_3487 | _T_3233; // @[Mux.scala 27:72]
|
|
wire _T_2754 = btb_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_32; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3234 = _T_2754 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3489 = _T_3488 | _T_3234; // @[Mux.scala 27:72]
|
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wire _T_2756 = btb_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_33; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3235 = _T_2756 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3490 = _T_3489 | _T_3235; // @[Mux.scala 27:72]
|
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wire _T_2758 = btb_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_34; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3236 = _T_2758 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3491 = _T_3490 | _T_3236; // @[Mux.scala 27:72]
|
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wire _T_2760 = btb_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_35; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3237 = _T_2760 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3492 = _T_3491 | _T_3237; // @[Mux.scala 27:72]
|
|
wire _T_2762 = btb_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_36; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3238 = _T_2762 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3493 = _T_3492 | _T_3238; // @[Mux.scala 27:72]
|
|
wire _T_2764 = btb_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_37; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3239 = _T_2764 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3494 = _T_3493 | _T_3239; // @[Mux.scala 27:72]
|
|
wire _T_2766 = btb_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_38; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3240 = _T_2766 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3495 = _T_3494 | _T_3240; // @[Mux.scala 27:72]
|
|
wire _T_2768 = btb_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_39; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3241 = _T_2768 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3496 = _T_3495 | _T_3241; // @[Mux.scala 27:72]
|
|
wire _T_2770 = btb_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_40; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3242 = _T_2770 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3497 = _T_3496 | _T_3242; // @[Mux.scala 27:72]
|
|
wire _T_2772 = btb_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_41; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3243 = _T_2772 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3498 = _T_3497 | _T_3243; // @[Mux.scala 27:72]
|
|
wire _T_2774 = btb_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_42; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3244 = _T_2774 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3499 = _T_3498 | _T_3244; // @[Mux.scala 27:72]
|
|
wire _T_2776 = btb_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_43; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3245 = _T_2776 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3500 = _T_3499 | _T_3245; // @[Mux.scala 27:72]
|
|
wire _T_2778 = btb_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_44; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3246 = _T_2778 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3501 = _T_3500 | _T_3246; // @[Mux.scala 27:72]
|
|
wire _T_2780 = btb_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_45; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3247 = _T_2780 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3502 = _T_3501 | _T_3247; // @[Mux.scala 27:72]
|
|
wire _T_2782 = btb_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_46; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3248 = _T_2782 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3503 = _T_3502 | _T_3248; // @[Mux.scala 27:72]
|
|
wire _T_2784 = btb_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_47; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3249 = _T_2784 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3504 = _T_3503 | _T_3249; // @[Mux.scala 27:72]
|
|
wire _T_2786 = btb_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_48; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3250 = _T_2786 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3505 = _T_3504 | _T_3250; // @[Mux.scala 27:72]
|
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wire _T_2788 = btb_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_49; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3251 = _T_2788 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3506 = _T_3505 | _T_3251; // @[Mux.scala 27:72]
|
|
wire _T_2790 = btb_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_50; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3252 = _T_2790 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3507 = _T_3506 | _T_3252; // @[Mux.scala 27:72]
|
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wire _T_2792 = btb_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_51; // @[Reg.scala 27:20]
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wire [21:0] _T_3253 = _T_2792 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3508 = _T_3507 | _T_3253; // @[Mux.scala 27:72]
|
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wire _T_2794 = btb_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_52; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3254 = _T_2794 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3509 = _T_3508 | _T_3254; // @[Mux.scala 27:72]
|
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wire _T_2796 = btb_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_53; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3255 = _T_2796 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3510 = _T_3509 | _T_3255; // @[Mux.scala 27:72]
|
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wire _T_2798 = btb_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_54; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3256 = _T_2798 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3511 = _T_3510 | _T_3256; // @[Mux.scala 27:72]
|
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wire _T_2800 = btb_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_55; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3257 = _T_2800 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3512 = _T_3511 | _T_3257; // @[Mux.scala 27:72]
|
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wire _T_2802 = btb_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_56; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3258 = _T_2802 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3513 = _T_3512 | _T_3258; // @[Mux.scala 27:72]
|
|
wire _T_2804 = btb_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_57; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3259 = _T_2804 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3514 = _T_3513 | _T_3259; // @[Mux.scala 27:72]
|
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wire _T_2806 = btb_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_58; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3260 = _T_2806 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3515 = _T_3514 | _T_3260; // @[Mux.scala 27:72]
|
|
wire _T_2808 = btb_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_59; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3261 = _T_2808 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3516 = _T_3515 | _T_3261; // @[Mux.scala 27:72]
|
|
wire _T_2810 = btb_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_60; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3262 = _T_2810 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3517 = _T_3516 | _T_3262; // @[Mux.scala 27:72]
|
|
wire _T_2812 = btb_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_61; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3263 = _T_2812 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3518 = _T_3517 | _T_3263; // @[Mux.scala 27:72]
|
|
wire _T_2814 = btb_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_62; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3264 = _T_2814 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3519 = _T_3518 | _T_3264; // @[Mux.scala 27:72]
|
|
wire _T_2816 = btb_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_63; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3265 = _T_2816 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3520 = _T_3519 | _T_3265; // @[Mux.scala 27:72]
|
|
wire _T_2818 = btb_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_64; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3266 = _T_2818 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3521 = _T_3520 | _T_3266; // @[Mux.scala 27:72]
|
|
wire _T_2820 = btb_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_65; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3267 = _T_2820 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3522 = _T_3521 | _T_3267; // @[Mux.scala 27:72]
|
|
wire _T_2822 = btb_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_66; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3268 = _T_2822 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3523 = _T_3522 | _T_3268; // @[Mux.scala 27:72]
|
|
wire _T_2824 = btb_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_67; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3269 = _T_2824 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3524 = _T_3523 | _T_3269; // @[Mux.scala 27:72]
|
|
wire _T_2826 = btb_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_68; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3270 = _T_2826 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3525 = _T_3524 | _T_3270; // @[Mux.scala 27:72]
|
|
wire _T_2828 = btb_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_69; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3271 = _T_2828 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3526 = _T_3525 | _T_3271; // @[Mux.scala 27:72]
|
|
wire _T_2830 = btb_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_70; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3272 = _T_2830 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3527 = _T_3526 | _T_3272; // @[Mux.scala 27:72]
|
|
wire _T_2832 = btb_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_71; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3273 = _T_2832 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3528 = _T_3527 | _T_3273; // @[Mux.scala 27:72]
|
|
wire _T_2834 = btb_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_72; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3274 = _T_2834 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3529 = _T_3528 | _T_3274; // @[Mux.scala 27:72]
|
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wire _T_2836 = btb_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_73; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3275 = _T_2836 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3530 = _T_3529 | _T_3275; // @[Mux.scala 27:72]
|
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wire _T_2838 = btb_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_74; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3276 = _T_2838 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3531 = _T_3530 | _T_3276; // @[Mux.scala 27:72]
|
|
wire _T_2840 = btb_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_75; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3277 = _T_2840 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3532 = _T_3531 | _T_3277; // @[Mux.scala 27:72]
|
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wire _T_2842 = btb_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_76; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3278 = _T_2842 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3533 = _T_3532 | _T_3278; // @[Mux.scala 27:72]
|
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wire _T_2844 = btb_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_77; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3279 = _T_2844 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3534 = _T_3533 | _T_3279; // @[Mux.scala 27:72]
|
|
wire _T_2846 = btb_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_78; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3280 = _T_2846 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3535 = _T_3534 | _T_3280; // @[Mux.scala 27:72]
|
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wire _T_2848 = btb_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_79; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3281 = _T_2848 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3536 = _T_3535 | _T_3281; // @[Mux.scala 27:72]
|
|
wire _T_2850 = btb_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_80; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3282 = _T_2850 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3537 = _T_3536 | _T_3282; // @[Mux.scala 27:72]
|
|
wire _T_2852 = btb_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_81; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3283 = _T_2852 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3538 = _T_3537 | _T_3283; // @[Mux.scala 27:72]
|
|
wire _T_2854 = btb_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_82; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3284 = _T_2854 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3539 = _T_3538 | _T_3284; // @[Mux.scala 27:72]
|
|
wire _T_2856 = btb_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_83; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3285 = _T_2856 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3540 = _T_3539 | _T_3285; // @[Mux.scala 27:72]
|
|
wire _T_2858 = btb_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_84; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3286 = _T_2858 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3541 = _T_3540 | _T_3286; // @[Mux.scala 27:72]
|
|
wire _T_2860 = btb_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_85; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3287 = _T_2860 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3542 = _T_3541 | _T_3287; // @[Mux.scala 27:72]
|
|
wire _T_2862 = btb_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_86; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3288 = _T_2862 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3543 = _T_3542 | _T_3288; // @[Mux.scala 27:72]
|
|
wire _T_2864 = btb_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_87; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3289 = _T_2864 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3544 = _T_3543 | _T_3289; // @[Mux.scala 27:72]
|
|
wire _T_2866 = btb_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_88; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3290 = _T_2866 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3545 = _T_3544 | _T_3290; // @[Mux.scala 27:72]
|
|
wire _T_2868 = btb_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_89; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3291 = _T_2868 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3546 = _T_3545 | _T_3291; // @[Mux.scala 27:72]
|
|
wire _T_2870 = btb_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_90; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3292 = _T_2870 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3547 = _T_3546 | _T_3292; // @[Mux.scala 27:72]
|
|
wire _T_2872 = btb_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_91; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3293 = _T_2872 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3548 = _T_3547 | _T_3293; // @[Mux.scala 27:72]
|
|
wire _T_2874 = btb_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_92; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3294 = _T_2874 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3549 = _T_3548 | _T_3294; // @[Mux.scala 27:72]
|
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wire _T_2876 = btb_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_93; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3295 = _T_2876 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3550 = _T_3549 | _T_3295; // @[Mux.scala 27:72]
|
|
wire _T_2878 = btb_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_94; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3296 = _T_2878 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3551 = _T_3550 | _T_3296; // @[Mux.scala 27:72]
|
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wire _T_2880 = btb_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_95; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3297 = _T_2880 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3552 = _T_3551 | _T_3297; // @[Mux.scala 27:72]
|
|
wire _T_2882 = btb_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_96; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3298 = _T_2882 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3553 = _T_3552 | _T_3298; // @[Mux.scala 27:72]
|
|
wire _T_2884 = btb_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_97; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3299 = _T_2884 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3554 = _T_3553 | _T_3299; // @[Mux.scala 27:72]
|
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wire _T_2886 = btb_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_98; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3300 = _T_2886 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3555 = _T_3554 | _T_3300; // @[Mux.scala 27:72]
|
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wire _T_2888 = btb_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_99; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3301 = _T_2888 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3556 = _T_3555 | _T_3301; // @[Mux.scala 27:72]
|
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wire _T_2890 = btb_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_100; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3302 = _T_2890 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3557 = _T_3556 | _T_3302; // @[Mux.scala 27:72]
|
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wire _T_2892 = btb_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_101; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3303 = _T_2892 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3558 = _T_3557 | _T_3303; // @[Mux.scala 27:72]
|
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wire _T_2894 = btb_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_102; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3304 = _T_2894 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3559 = _T_3558 | _T_3304; // @[Mux.scala 27:72]
|
|
wire _T_2896 = btb_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_103; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3305 = _T_2896 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3560 = _T_3559 | _T_3305; // @[Mux.scala 27:72]
|
|
wire _T_2898 = btb_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_104; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3306 = _T_2898 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3561 = _T_3560 | _T_3306; // @[Mux.scala 27:72]
|
|
wire _T_2900 = btb_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_105; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3307 = _T_2900 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3562 = _T_3561 | _T_3307; // @[Mux.scala 27:72]
|
|
wire _T_2902 = btb_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_106; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3308 = _T_2902 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3563 = _T_3562 | _T_3308; // @[Mux.scala 27:72]
|
|
wire _T_2904 = btb_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_107; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3309 = _T_2904 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3564 = _T_3563 | _T_3309; // @[Mux.scala 27:72]
|
|
wire _T_2906 = btb_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_108; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3310 = _T_2906 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3565 = _T_3564 | _T_3310; // @[Mux.scala 27:72]
|
|
wire _T_2908 = btb_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_109; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3311 = _T_2908 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3566 = _T_3565 | _T_3311; // @[Mux.scala 27:72]
|
|
wire _T_2910 = btb_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_110; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3312 = _T_2910 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3567 = _T_3566 | _T_3312; // @[Mux.scala 27:72]
|
|
wire _T_2912 = btb_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_111; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3313 = _T_2912 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3568 = _T_3567 | _T_3313; // @[Mux.scala 27:72]
|
|
wire _T_2914 = btb_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_112; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3314 = _T_2914 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3569 = _T_3568 | _T_3314; // @[Mux.scala 27:72]
|
|
wire _T_2916 = btb_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_113; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3315 = _T_2916 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3570 = _T_3569 | _T_3315; // @[Mux.scala 27:72]
|
|
wire _T_2918 = btb_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_114; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3316 = _T_2918 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3571 = _T_3570 | _T_3316; // @[Mux.scala 27:72]
|
|
wire _T_2920 = btb_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_115; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3317 = _T_2920 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3572 = _T_3571 | _T_3317; // @[Mux.scala 27:72]
|
|
wire _T_2922 = btb_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_116; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3318 = _T_2922 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3573 = _T_3572 | _T_3318; // @[Mux.scala 27:72]
|
|
wire _T_2924 = btb_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_117; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3319 = _T_2924 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3574 = _T_3573 | _T_3319; // @[Mux.scala 27:72]
|
|
wire _T_2926 = btb_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_118; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3320 = _T_2926 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3575 = _T_3574 | _T_3320; // @[Mux.scala 27:72]
|
|
wire _T_2928 = btb_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_119; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3321 = _T_2928 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3576 = _T_3575 | _T_3321; // @[Mux.scala 27:72]
|
|
wire _T_2930 = btb_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_120; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3322 = _T_2930 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3577 = _T_3576 | _T_3322; // @[Mux.scala 27:72]
|
|
wire _T_2932 = btb_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_121; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3323 = _T_2932 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3578 = _T_3577 | _T_3323; // @[Mux.scala 27:72]
|
|
wire _T_2934 = btb_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_122; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3324 = _T_2934 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3579 = _T_3578 | _T_3324; // @[Mux.scala 27:72]
|
|
wire _T_2936 = btb_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_123; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3325 = _T_2936 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3580 = _T_3579 | _T_3325; // @[Mux.scala 27:72]
|
|
wire _T_2938 = btb_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_124; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3326 = _T_2938 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3581 = _T_3580 | _T_3326; // @[Mux.scala 27:72]
|
|
wire _T_2940 = btb_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_125; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3327 = _T_2940 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3582 = _T_3581 | _T_3327; // @[Mux.scala 27:72]
|
|
wire _T_2942 = btb_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_126; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3328 = _T_2942 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3583 = _T_3582 | _T_3328; // @[Mux.scala 27:72]
|
|
wire _T_2944 = btb_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_127; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3329 = _T_2944 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3584 = _T_3583 | _T_3329; // @[Mux.scala 27:72]
|
|
wire _T_2946 = btb_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_128; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3330 = _T_2946 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3585 = _T_3584 | _T_3330; // @[Mux.scala 27:72]
|
|
wire _T_2948 = btb_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_129; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3331 = _T_2948 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3586 = _T_3585 | _T_3331; // @[Mux.scala 27:72]
|
|
wire _T_2950 = btb_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_130; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3332 = _T_2950 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3587 = _T_3586 | _T_3332; // @[Mux.scala 27:72]
|
|
wire _T_2952 = btb_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_131; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3333 = _T_2952 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3588 = _T_3587 | _T_3333; // @[Mux.scala 27:72]
|
|
wire _T_2954 = btb_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_132; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3334 = _T_2954 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3589 = _T_3588 | _T_3334; // @[Mux.scala 27:72]
|
|
wire _T_2956 = btb_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_133; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3335 = _T_2956 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3590 = _T_3589 | _T_3335; // @[Mux.scala 27:72]
|
|
wire _T_2958 = btb_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_134; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3336 = _T_2958 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3591 = _T_3590 | _T_3336; // @[Mux.scala 27:72]
|
|
wire _T_2960 = btb_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_135; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3337 = _T_2960 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3592 = _T_3591 | _T_3337; // @[Mux.scala 27:72]
|
|
wire _T_2962 = btb_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_136; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3338 = _T_2962 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3593 = _T_3592 | _T_3338; // @[Mux.scala 27:72]
|
|
wire _T_2964 = btb_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_137; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3339 = _T_2964 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3594 = _T_3593 | _T_3339; // @[Mux.scala 27:72]
|
|
wire _T_2966 = btb_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_138; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3340 = _T_2966 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3595 = _T_3594 | _T_3340; // @[Mux.scala 27:72]
|
|
wire _T_2968 = btb_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_139; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3341 = _T_2968 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3596 = _T_3595 | _T_3341; // @[Mux.scala 27:72]
|
|
wire _T_2970 = btb_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_140; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3342 = _T_2970 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3597 = _T_3596 | _T_3342; // @[Mux.scala 27:72]
|
|
wire _T_2972 = btb_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_141; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3343 = _T_2972 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3598 = _T_3597 | _T_3343; // @[Mux.scala 27:72]
|
|
wire _T_2974 = btb_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_142; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3344 = _T_2974 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3599 = _T_3598 | _T_3344; // @[Mux.scala 27:72]
|
|
wire _T_2976 = btb_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_143; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3345 = _T_2976 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3600 = _T_3599 | _T_3345; // @[Mux.scala 27:72]
|
|
wire _T_2978 = btb_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_144; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3346 = _T_2978 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3601 = _T_3600 | _T_3346; // @[Mux.scala 27:72]
|
|
wire _T_2980 = btb_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_145; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3347 = _T_2980 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3602 = _T_3601 | _T_3347; // @[Mux.scala 27:72]
|
|
wire _T_2982 = btb_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_146; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3348 = _T_2982 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3603 = _T_3602 | _T_3348; // @[Mux.scala 27:72]
|
|
wire _T_2984 = btb_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_147; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3349 = _T_2984 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3604 = _T_3603 | _T_3349; // @[Mux.scala 27:72]
|
|
wire _T_2986 = btb_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_148; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3350 = _T_2986 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3605 = _T_3604 | _T_3350; // @[Mux.scala 27:72]
|
|
wire _T_2988 = btb_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_149; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3351 = _T_2988 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3606 = _T_3605 | _T_3351; // @[Mux.scala 27:72]
|
|
wire _T_2990 = btb_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_150; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3352 = _T_2990 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3607 = _T_3606 | _T_3352; // @[Mux.scala 27:72]
|
|
wire _T_2992 = btb_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_151; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3353 = _T_2992 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3608 = _T_3607 | _T_3353; // @[Mux.scala 27:72]
|
|
wire _T_2994 = btb_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_152; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3354 = _T_2994 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3609 = _T_3608 | _T_3354; // @[Mux.scala 27:72]
|
|
wire _T_2996 = btb_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_153; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3355 = _T_2996 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3610 = _T_3609 | _T_3355; // @[Mux.scala 27:72]
|
|
wire _T_2998 = btb_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_154; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3356 = _T_2998 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3611 = _T_3610 | _T_3356; // @[Mux.scala 27:72]
|
|
wire _T_3000 = btb_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_155; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3357 = _T_3000 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3612 = _T_3611 | _T_3357; // @[Mux.scala 27:72]
|
|
wire _T_3002 = btb_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_156; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3358 = _T_3002 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3613 = _T_3612 | _T_3358; // @[Mux.scala 27:72]
|
|
wire _T_3004 = btb_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_157; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3359 = _T_3004 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3614 = _T_3613 | _T_3359; // @[Mux.scala 27:72]
|
|
wire _T_3006 = btb_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_158; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3360 = _T_3006 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3615 = _T_3614 | _T_3360; // @[Mux.scala 27:72]
|
|
wire _T_3008 = btb_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_159; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3361 = _T_3008 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3616 = _T_3615 | _T_3361; // @[Mux.scala 27:72]
|
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wire _T_3010 = btb_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_160; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3362 = _T_3010 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3617 = _T_3616 | _T_3362; // @[Mux.scala 27:72]
|
|
wire _T_3012 = btb_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_161; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3363 = _T_3012 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3618 = _T_3617 | _T_3363; // @[Mux.scala 27:72]
|
|
wire _T_3014 = btb_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_162; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3364 = _T_3014 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3619 = _T_3618 | _T_3364; // @[Mux.scala 27:72]
|
|
wire _T_3016 = btb_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_163; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3365 = _T_3016 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3620 = _T_3619 | _T_3365; // @[Mux.scala 27:72]
|
|
wire _T_3018 = btb_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_164; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3366 = _T_3018 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3621 = _T_3620 | _T_3366; // @[Mux.scala 27:72]
|
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wire _T_3020 = btb_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_165; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3367 = _T_3020 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3622 = _T_3621 | _T_3367; // @[Mux.scala 27:72]
|
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wire _T_3022 = btb_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_166; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3368 = _T_3022 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3623 = _T_3622 | _T_3368; // @[Mux.scala 27:72]
|
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wire _T_3024 = btb_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_167; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3369 = _T_3024 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3624 = _T_3623 | _T_3369; // @[Mux.scala 27:72]
|
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wire _T_3026 = btb_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_168; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3370 = _T_3026 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3625 = _T_3624 | _T_3370; // @[Mux.scala 27:72]
|
|
wire _T_3028 = btb_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_169; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3371 = _T_3028 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3626 = _T_3625 | _T_3371; // @[Mux.scala 27:72]
|
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wire _T_3030 = btb_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_170; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3372 = _T_3030 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3627 = _T_3626 | _T_3372; // @[Mux.scala 27:72]
|
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wire _T_3032 = btb_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_171; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3373 = _T_3032 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3628 = _T_3627 | _T_3373; // @[Mux.scala 27:72]
|
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wire _T_3034 = btb_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_172; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3374 = _T_3034 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3629 = _T_3628 | _T_3374; // @[Mux.scala 27:72]
|
|
wire _T_3036 = btb_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_173; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3375 = _T_3036 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3630 = _T_3629 | _T_3375; // @[Mux.scala 27:72]
|
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wire _T_3038 = btb_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_174; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3376 = _T_3038 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3631 = _T_3630 | _T_3376; // @[Mux.scala 27:72]
|
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wire _T_3040 = btb_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_175; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3377 = _T_3040 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3632 = _T_3631 | _T_3377; // @[Mux.scala 27:72]
|
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wire _T_3042 = btb_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_176; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3378 = _T_3042 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3633 = _T_3632 | _T_3378; // @[Mux.scala 27:72]
|
|
wire _T_3044 = btb_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_177; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3379 = _T_3044 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3634 = _T_3633 | _T_3379; // @[Mux.scala 27:72]
|
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wire _T_3046 = btb_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_178; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3380 = _T_3046 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3635 = _T_3634 | _T_3380; // @[Mux.scala 27:72]
|
|
wire _T_3048 = btb_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_179; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3381 = _T_3048 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3636 = _T_3635 | _T_3381; // @[Mux.scala 27:72]
|
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wire _T_3050 = btb_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_180; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3382 = _T_3050 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3637 = _T_3636 | _T_3382; // @[Mux.scala 27:72]
|
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wire _T_3052 = btb_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_181; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3383 = _T_3052 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3638 = _T_3637 | _T_3383; // @[Mux.scala 27:72]
|
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wire _T_3054 = btb_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_182; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3384 = _T_3054 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3639 = _T_3638 | _T_3384; // @[Mux.scala 27:72]
|
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wire _T_3056 = btb_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_183; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3385 = _T_3056 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3640 = _T_3639 | _T_3385; // @[Mux.scala 27:72]
|
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wire _T_3058 = btb_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_184; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3386 = _T_3058 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3641 = _T_3640 | _T_3386; // @[Mux.scala 27:72]
|
|
wire _T_3060 = btb_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_185; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3387 = _T_3060 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3642 = _T_3641 | _T_3387; // @[Mux.scala 27:72]
|
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wire _T_3062 = btb_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_186; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3388 = _T_3062 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3643 = _T_3642 | _T_3388; // @[Mux.scala 27:72]
|
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wire _T_3064 = btb_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_187; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3389 = _T_3064 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3644 = _T_3643 | _T_3389; // @[Mux.scala 27:72]
|
|
wire _T_3066 = btb_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_188; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3390 = _T_3066 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3645 = _T_3644 | _T_3390; // @[Mux.scala 27:72]
|
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wire _T_3068 = btb_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_189; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3391 = _T_3068 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3646 = _T_3645 | _T_3391; // @[Mux.scala 27:72]
|
|
wire _T_3070 = btb_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_190; // @[Reg.scala 27:20]
|
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wire [21:0] _T_3392 = _T_3070 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_3647 = _T_3646 | _T_3392; // @[Mux.scala 27:72]
|
|
wire _T_3072 = btb_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_191; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3393 = _T_3072 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3648 = _T_3647 | _T_3393; // @[Mux.scala 27:72]
|
|
wire _T_3074 = btb_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_192; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3394 = _T_3074 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3649 = _T_3648 | _T_3394; // @[Mux.scala 27:72]
|
|
wire _T_3076 = btb_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_193; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3395 = _T_3076 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3650 = _T_3649 | _T_3395; // @[Mux.scala 27:72]
|
|
wire _T_3078 = btb_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_194; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3396 = _T_3078 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3651 = _T_3650 | _T_3396; // @[Mux.scala 27:72]
|
|
wire _T_3080 = btb_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_195; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3397 = _T_3080 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3652 = _T_3651 | _T_3397; // @[Mux.scala 27:72]
|
|
wire _T_3082 = btb_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_196; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3398 = _T_3082 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3653 = _T_3652 | _T_3398; // @[Mux.scala 27:72]
|
|
wire _T_3084 = btb_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_197; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3399 = _T_3084 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3654 = _T_3653 | _T_3399; // @[Mux.scala 27:72]
|
|
wire _T_3086 = btb_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_198; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3400 = _T_3086 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3655 = _T_3654 | _T_3400; // @[Mux.scala 27:72]
|
|
wire _T_3088 = btb_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_199; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3401 = _T_3088 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3656 = _T_3655 | _T_3401; // @[Mux.scala 27:72]
|
|
wire _T_3090 = btb_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_200; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3402 = _T_3090 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3657 = _T_3656 | _T_3402; // @[Mux.scala 27:72]
|
|
wire _T_3092 = btb_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_201; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3403 = _T_3092 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3658 = _T_3657 | _T_3403; // @[Mux.scala 27:72]
|
|
wire _T_3094 = btb_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 435:82]
|
|
reg [21:0] btb_bank0_rd_data_way0_out_202; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_3404 = _T_3094 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_3659 = _T_3658 | _T_3404; // @[Mux.scala 27:72]
|
|
wire _T_3096 = btb_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_203; // @[Reg.scala 27:20]
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wire [21:0] _T_3405 = _T_3096 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3660 = _T_3659 | _T_3405; // @[Mux.scala 27:72]
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wire _T_3098 = btb_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_204; // @[Reg.scala 27:20]
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wire [21:0] _T_3406 = _T_3098 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3661 = _T_3660 | _T_3406; // @[Mux.scala 27:72]
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wire _T_3100 = btb_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_205; // @[Reg.scala 27:20]
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wire [21:0] _T_3407 = _T_3100 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3662 = _T_3661 | _T_3407; // @[Mux.scala 27:72]
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wire _T_3102 = btb_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_206; // @[Reg.scala 27:20]
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wire [21:0] _T_3408 = _T_3102 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3663 = _T_3662 | _T_3408; // @[Mux.scala 27:72]
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wire _T_3104 = btb_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_207; // @[Reg.scala 27:20]
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wire [21:0] _T_3409 = _T_3104 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3664 = _T_3663 | _T_3409; // @[Mux.scala 27:72]
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wire _T_3106 = btb_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_208; // @[Reg.scala 27:20]
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wire [21:0] _T_3410 = _T_3106 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3665 = _T_3664 | _T_3410; // @[Mux.scala 27:72]
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wire _T_3108 = btb_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_209; // @[Reg.scala 27:20]
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wire [21:0] _T_3411 = _T_3108 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3666 = _T_3665 | _T_3411; // @[Mux.scala 27:72]
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wire _T_3110 = btb_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_210; // @[Reg.scala 27:20]
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wire [21:0] _T_3412 = _T_3110 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3667 = _T_3666 | _T_3412; // @[Mux.scala 27:72]
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wire _T_3112 = btb_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_211; // @[Reg.scala 27:20]
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wire [21:0] _T_3413 = _T_3112 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3668 = _T_3667 | _T_3413; // @[Mux.scala 27:72]
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wire _T_3114 = btb_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_212; // @[Reg.scala 27:20]
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wire [21:0] _T_3414 = _T_3114 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3669 = _T_3668 | _T_3414; // @[Mux.scala 27:72]
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wire _T_3116 = btb_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_213; // @[Reg.scala 27:20]
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wire [21:0] _T_3415 = _T_3116 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3670 = _T_3669 | _T_3415; // @[Mux.scala 27:72]
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wire _T_3118 = btb_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_214; // @[Reg.scala 27:20]
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wire [21:0] _T_3416 = _T_3118 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3671 = _T_3670 | _T_3416; // @[Mux.scala 27:72]
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wire _T_3120 = btb_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_215; // @[Reg.scala 27:20]
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wire [21:0] _T_3417 = _T_3120 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3672 = _T_3671 | _T_3417; // @[Mux.scala 27:72]
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wire _T_3122 = btb_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_216; // @[Reg.scala 27:20]
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wire [21:0] _T_3418 = _T_3122 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3673 = _T_3672 | _T_3418; // @[Mux.scala 27:72]
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wire _T_3124 = btb_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_217; // @[Reg.scala 27:20]
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wire [21:0] _T_3419 = _T_3124 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3674 = _T_3673 | _T_3419; // @[Mux.scala 27:72]
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wire _T_3126 = btb_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_218; // @[Reg.scala 27:20]
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wire [21:0] _T_3420 = _T_3126 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3675 = _T_3674 | _T_3420; // @[Mux.scala 27:72]
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wire _T_3128 = btb_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_219; // @[Reg.scala 27:20]
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wire [21:0] _T_3421 = _T_3128 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3676 = _T_3675 | _T_3421; // @[Mux.scala 27:72]
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wire _T_3130 = btb_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_220; // @[Reg.scala 27:20]
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wire [21:0] _T_3422 = _T_3130 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3677 = _T_3676 | _T_3422; // @[Mux.scala 27:72]
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wire _T_3132 = btb_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_221; // @[Reg.scala 27:20]
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wire [21:0] _T_3423 = _T_3132 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3678 = _T_3677 | _T_3423; // @[Mux.scala 27:72]
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wire _T_3134 = btb_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_222; // @[Reg.scala 27:20]
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wire [21:0] _T_3424 = _T_3134 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3679 = _T_3678 | _T_3424; // @[Mux.scala 27:72]
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wire _T_3136 = btb_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_223; // @[Reg.scala 27:20]
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wire [21:0] _T_3425 = _T_3136 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3680 = _T_3679 | _T_3425; // @[Mux.scala 27:72]
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wire _T_3138 = btb_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_224; // @[Reg.scala 27:20]
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wire [21:0] _T_3426 = _T_3138 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3681 = _T_3680 | _T_3426; // @[Mux.scala 27:72]
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wire _T_3140 = btb_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_225; // @[Reg.scala 27:20]
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wire [21:0] _T_3427 = _T_3140 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3682 = _T_3681 | _T_3427; // @[Mux.scala 27:72]
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wire _T_3142 = btb_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_226; // @[Reg.scala 27:20]
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wire [21:0] _T_3428 = _T_3142 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3683 = _T_3682 | _T_3428; // @[Mux.scala 27:72]
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wire _T_3144 = btb_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_227; // @[Reg.scala 27:20]
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wire [21:0] _T_3429 = _T_3144 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3684 = _T_3683 | _T_3429; // @[Mux.scala 27:72]
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wire _T_3146 = btb_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_228; // @[Reg.scala 27:20]
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wire [21:0] _T_3430 = _T_3146 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3685 = _T_3684 | _T_3430; // @[Mux.scala 27:72]
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wire _T_3148 = btb_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_229; // @[Reg.scala 27:20]
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wire [21:0] _T_3431 = _T_3148 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3686 = _T_3685 | _T_3431; // @[Mux.scala 27:72]
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wire _T_3150 = btb_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_230; // @[Reg.scala 27:20]
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wire [21:0] _T_3432 = _T_3150 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3687 = _T_3686 | _T_3432; // @[Mux.scala 27:72]
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wire _T_3152 = btb_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_231; // @[Reg.scala 27:20]
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wire [21:0] _T_3433 = _T_3152 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3688 = _T_3687 | _T_3433; // @[Mux.scala 27:72]
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wire _T_3154 = btb_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_232; // @[Reg.scala 27:20]
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wire [21:0] _T_3434 = _T_3154 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3689 = _T_3688 | _T_3434; // @[Mux.scala 27:72]
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wire _T_3156 = btb_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_233; // @[Reg.scala 27:20]
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wire [21:0] _T_3435 = _T_3156 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3690 = _T_3689 | _T_3435; // @[Mux.scala 27:72]
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wire _T_3158 = btb_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_234; // @[Reg.scala 27:20]
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wire [21:0] _T_3436 = _T_3158 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3691 = _T_3690 | _T_3436; // @[Mux.scala 27:72]
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wire _T_3160 = btb_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_235; // @[Reg.scala 27:20]
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wire [21:0] _T_3437 = _T_3160 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3692 = _T_3691 | _T_3437; // @[Mux.scala 27:72]
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wire _T_3162 = btb_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_236; // @[Reg.scala 27:20]
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wire [21:0] _T_3438 = _T_3162 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3693 = _T_3692 | _T_3438; // @[Mux.scala 27:72]
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wire _T_3164 = btb_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_237; // @[Reg.scala 27:20]
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wire [21:0] _T_3439 = _T_3164 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3694 = _T_3693 | _T_3439; // @[Mux.scala 27:72]
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wire _T_3166 = btb_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_238; // @[Reg.scala 27:20]
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wire [21:0] _T_3440 = _T_3166 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3695 = _T_3694 | _T_3440; // @[Mux.scala 27:72]
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wire _T_3168 = btb_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_239; // @[Reg.scala 27:20]
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wire [21:0] _T_3441 = _T_3168 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3696 = _T_3695 | _T_3441; // @[Mux.scala 27:72]
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wire _T_3170 = btb_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_240; // @[Reg.scala 27:20]
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wire [21:0] _T_3442 = _T_3170 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3697 = _T_3696 | _T_3442; // @[Mux.scala 27:72]
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wire _T_3172 = btb_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_241; // @[Reg.scala 27:20]
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wire [21:0] _T_3443 = _T_3172 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3698 = _T_3697 | _T_3443; // @[Mux.scala 27:72]
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wire _T_3174 = btb_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_242; // @[Reg.scala 27:20]
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wire [21:0] _T_3444 = _T_3174 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3699 = _T_3698 | _T_3444; // @[Mux.scala 27:72]
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wire _T_3176 = btb_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_243; // @[Reg.scala 27:20]
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wire [21:0] _T_3445 = _T_3176 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3700 = _T_3699 | _T_3445; // @[Mux.scala 27:72]
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wire _T_3178 = btb_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_244; // @[Reg.scala 27:20]
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wire [21:0] _T_3446 = _T_3178 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3701 = _T_3700 | _T_3446; // @[Mux.scala 27:72]
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wire _T_3180 = btb_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_245; // @[Reg.scala 27:20]
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wire [21:0] _T_3447 = _T_3180 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3702 = _T_3701 | _T_3447; // @[Mux.scala 27:72]
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wire _T_3182 = btb_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_246; // @[Reg.scala 27:20]
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wire [21:0] _T_3448 = _T_3182 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3703 = _T_3702 | _T_3448; // @[Mux.scala 27:72]
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wire _T_3184 = btb_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_247; // @[Reg.scala 27:20]
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wire [21:0] _T_3449 = _T_3184 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3704 = _T_3703 | _T_3449; // @[Mux.scala 27:72]
|
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wire _T_3186 = btb_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_248; // @[Reg.scala 27:20]
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wire [21:0] _T_3450 = _T_3186 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3705 = _T_3704 | _T_3450; // @[Mux.scala 27:72]
|
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wire _T_3188 = btb_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_249; // @[Reg.scala 27:20]
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wire [21:0] _T_3451 = _T_3188 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3706 = _T_3705 | _T_3451; // @[Mux.scala 27:72]
|
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wire _T_3190 = btb_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_250; // @[Reg.scala 27:20]
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wire [21:0] _T_3452 = _T_3190 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3707 = _T_3706 | _T_3452; // @[Mux.scala 27:72]
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wire _T_3192 = btb_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_251; // @[Reg.scala 27:20]
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wire [21:0] _T_3453 = _T_3192 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3708 = _T_3707 | _T_3453; // @[Mux.scala 27:72]
|
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wire _T_3194 = btb_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 435:82]
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reg [21:0] btb_bank0_rd_data_way0_out_252; // @[Reg.scala 27:20]
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wire [21:0] _T_3454 = _T_3194 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3709 = _T_3708 | _T_3454; // @[Mux.scala 27:72]
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wire _T_3196 = btb_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_253; // @[Reg.scala 27:20]
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wire [21:0] _T_3455 = _T_3196 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3710 = _T_3709 | _T_3455; // @[Mux.scala 27:72]
|
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wire _T_3198 = btb_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_254; // @[Reg.scala 27:20]
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wire [21:0] _T_3456 = _T_3198 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_3711 = _T_3710 | _T_3456; // @[Mux.scala 27:72]
|
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wire _T_3200 = btb_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 435:82]
|
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reg [21:0] btb_bank0_rd_data_way0_out_255; // @[Reg.scala 27:20]
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wire [21:0] _T_3457 = _T_3200 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] btb_bank0_rd_data_way0_f = _T_3711 | _T_3457; // @[Mux.scala 27:72]
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wire [4:0] _T_29 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[lib.scala 48:111]
|
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wire [4:0] _T_30 = _T_29 ^ io_ifc_fetch_addr_f[23:19]; // @[lib.scala 48:111]
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wire _T_50 = btb_bank0_rd_data_way0_f[21:17] == _T_30; // @[ifu_bp_ctl.scala 143:100]
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wire _T_51 = btb_bank0_rd_data_way0_f[0] & _T_50; // @[ifu_bp_ctl.scala 143:57]
|
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wire _T_19 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_f; // @[ifu_bp_ctl.scala 124:72]
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wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[ifu_bp_ctl.scala 124:51]
|
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wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 128:63]
|
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wire _T_52 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_f; // @[ifu_bp_ctl.scala 144:24]
|
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wire _T_53 = ~_T_52; // @[ifu_bp_ctl.scala 144:7]
|
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wire _T_54 = _T_51 & _T_53; // @[ifu_bp_ctl.scala 143:120]
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wire _T_55 = _T_54 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 144:56]
|
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wire _T_57 = _T_55 & _T; // @[ifu_bp_ctl.scala 144:77]
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wire _T_90 = btb_bank0_rd_data_way0_f[3] ^ btb_bank0_rd_data_way0_f[4]; // @[ifu_bp_ctl.scala 158:92]
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wire _T_91 = _T_57 & _T_90; // @[ifu_bp_ctl.scala 158:58]
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wire _T_95 = ~_T_90; // @[ifu_bp_ctl.scala 159:26]
|
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wire _T_96 = _T_57 & _T_95; // @[ifu_bp_ctl.scala 159:24]
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wire [1:0] _T_97 = {_T_91,_T_96}; // @[Cat.scala 29:58]
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wire [21:0] _T_142 = _T_97[1] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_0; // @[Reg.scala 27:20]
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wire [21:0] _T_4226 = _T_2690 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_1; // @[Reg.scala 27:20]
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wire [21:0] _T_4227 = _T_2692 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4482 = _T_4226 | _T_4227; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_2; // @[Reg.scala 27:20]
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wire [21:0] _T_4228 = _T_2694 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4483 = _T_4482 | _T_4228; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_3; // @[Reg.scala 27:20]
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wire [21:0] _T_4229 = _T_2696 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4484 = _T_4483 | _T_4229; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_4; // @[Reg.scala 27:20]
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wire [21:0] _T_4230 = _T_2698 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4485 = _T_4484 | _T_4230; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_5; // @[Reg.scala 27:20]
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wire [21:0] _T_4231 = _T_2700 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4486 = _T_4485 | _T_4231; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_6; // @[Reg.scala 27:20]
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wire [21:0] _T_4232 = _T_2702 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4487 = _T_4486 | _T_4232; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_7; // @[Reg.scala 27:20]
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wire [21:0] _T_4233 = _T_2704 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4488 = _T_4487 | _T_4233; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_8; // @[Reg.scala 27:20]
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wire [21:0] _T_4234 = _T_2706 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4489 = _T_4488 | _T_4234; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_9; // @[Reg.scala 27:20]
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wire [21:0] _T_4235 = _T_2708 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4490 = _T_4489 | _T_4235; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_10; // @[Reg.scala 27:20]
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wire [21:0] _T_4236 = _T_2710 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4491 = _T_4490 | _T_4236; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_11; // @[Reg.scala 27:20]
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wire [21:0] _T_4237 = _T_2712 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4492 = _T_4491 | _T_4237; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_12; // @[Reg.scala 27:20]
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wire [21:0] _T_4238 = _T_2714 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4493 = _T_4492 | _T_4238; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_13; // @[Reg.scala 27:20]
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wire [21:0] _T_4239 = _T_2716 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4494 = _T_4493 | _T_4239; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_14; // @[Reg.scala 27:20]
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wire [21:0] _T_4240 = _T_2718 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4495 = _T_4494 | _T_4240; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_15; // @[Reg.scala 27:20]
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wire [21:0] _T_4241 = _T_2720 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4496 = _T_4495 | _T_4241; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_16; // @[Reg.scala 27:20]
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wire [21:0] _T_4242 = _T_2722 ? btb_bank0_rd_data_way1_out_16 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4497 = _T_4496 | _T_4242; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_17; // @[Reg.scala 27:20]
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wire [21:0] _T_4243 = _T_2724 ? btb_bank0_rd_data_way1_out_17 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4498 = _T_4497 | _T_4243; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_18; // @[Reg.scala 27:20]
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wire [21:0] _T_4244 = _T_2726 ? btb_bank0_rd_data_way1_out_18 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4499 = _T_4498 | _T_4244; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_19; // @[Reg.scala 27:20]
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wire [21:0] _T_4245 = _T_2728 ? btb_bank0_rd_data_way1_out_19 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4500 = _T_4499 | _T_4245; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_20; // @[Reg.scala 27:20]
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wire [21:0] _T_4246 = _T_2730 ? btb_bank0_rd_data_way1_out_20 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4501 = _T_4500 | _T_4246; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_21; // @[Reg.scala 27:20]
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wire [21:0] _T_4247 = _T_2732 ? btb_bank0_rd_data_way1_out_21 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4502 = _T_4501 | _T_4247; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_22; // @[Reg.scala 27:20]
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wire [21:0] _T_4248 = _T_2734 ? btb_bank0_rd_data_way1_out_22 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4503 = _T_4502 | _T_4248; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_23; // @[Reg.scala 27:20]
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wire [21:0] _T_4249 = _T_2736 ? btb_bank0_rd_data_way1_out_23 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4504 = _T_4503 | _T_4249; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_24; // @[Reg.scala 27:20]
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wire [21:0] _T_4250 = _T_2738 ? btb_bank0_rd_data_way1_out_24 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4505 = _T_4504 | _T_4250; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_25; // @[Reg.scala 27:20]
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wire [21:0] _T_4251 = _T_2740 ? btb_bank0_rd_data_way1_out_25 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4506 = _T_4505 | _T_4251; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_26; // @[Reg.scala 27:20]
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wire [21:0] _T_4252 = _T_2742 ? btb_bank0_rd_data_way1_out_26 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4507 = _T_4506 | _T_4252; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_27; // @[Reg.scala 27:20]
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wire [21:0] _T_4253 = _T_2744 ? btb_bank0_rd_data_way1_out_27 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4508 = _T_4507 | _T_4253; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_28; // @[Reg.scala 27:20]
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wire [21:0] _T_4254 = _T_2746 ? btb_bank0_rd_data_way1_out_28 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4509 = _T_4508 | _T_4254; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_29; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4255 = _T_2748 ? btb_bank0_rd_data_way1_out_29 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4510 = _T_4509 | _T_4255; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_30; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4256 = _T_2750 ? btb_bank0_rd_data_way1_out_30 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4511 = _T_4510 | _T_4256; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_31; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4257 = _T_2752 ? btb_bank0_rd_data_way1_out_31 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4512 = _T_4511 | _T_4257; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_32; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4258 = _T_2754 ? btb_bank0_rd_data_way1_out_32 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4513 = _T_4512 | _T_4258; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_33; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4259 = _T_2756 ? btb_bank0_rd_data_way1_out_33 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4514 = _T_4513 | _T_4259; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_34; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4260 = _T_2758 ? btb_bank0_rd_data_way1_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4515 = _T_4514 | _T_4260; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_35; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4261 = _T_2760 ? btb_bank0_rd_data_way1_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4516 = _T_4515 | _T_4261; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_36; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4262 = _T_2762 ? btb_bank0_rd_data_way1_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4517 = _T_4516 | _T_4262; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_37; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4263 = _T_2764 ? btb_bank0_rd_data_way1_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4518 = _T_4517 | _T_4263; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_38; // @[Reg.scala 27:20]
|
|
wire [21:0] _T_4264 = _T_2766 ? btb_bank0_rd_data_way1_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_4519 = _T_4518 | _T_4264; // @[Mux.scala 27:72]
|
|
reg [21:0] btb_bank0_rd_data_way1_out_39; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4265 = _T_2768 ? btb_bank0_rd_data_way1_out_39 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4520 = _T_4519 | _T_4265; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_40; // @[Reg.scala 27:20]
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wire [21:0] _T_4266 = _T_2770 ? btb_bank0_rd_data_way1_out_40 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4521 = _T_4520 | _T_4266; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_41; // @[Reg.scala 27:20]
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wire [21:0] _T_4267 = _T_2772 ? btb_bank0_rd_data_way1_out_41 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4522 = _T_4521 | _T_4267; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_42; // @[Reg.scala 27:20]
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wire [21:0] _T_4268 = _T_2774 ? btb_bank0_rd_data_way1_out_42 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4523 = _T_4522 | _T_4268; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_43; // @[Reg.scala 27:20]
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wire [21:0] _T_4269 = _T_2776 ? btb_bank0_rd_data_way1_out_43 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4524 = _T_4523 | _T_4269; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_44; // @[Reg.scala 27:20]
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wire [21:0] _T_4270 = _T_2778 ? btb_bank0_rd_data_way1_out_44 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4525 = _T_4524 | _T_4270; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_45; // @[Reg.scala 27:20]
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wire [21:0] _T_4271 = _T_2780 ? btb_bank0_rd_data_way1_out_45 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4526 = _T_4525 | _T_4271; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_46; // @[Reg.scala 27:20]
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wire [21:0] _T_4272 = _T_2782 ? btb_bank0_rd_data_way1_out_46 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4527 = _T_4526 | _T_4272; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_47; // @[Reg.scala 27:20]
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wire [21:0] _T_4273 = _T_2784 ? btb_bank0_rd_data_way1_out_47 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4528 = _T_4527 | _T_4273; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_48; // @[Reg.scala 27:20]
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wire [21:0] _T_4274 = _T_2786 ? btb_bank0_rd_data_way1_out_48 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4529 = _T_4528 | _T_4274; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_49; // @[Reg.scala 27:20]
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wire [21:0] _T_4275 = _T_2788 ? btb_bank0_rd_data_way1_out_49 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4530 = _T_4529 | _T_4275; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_50; // @[Reg.scala 27:20]
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wire [21:0] _T_4276 = _T_2790 ? btb_bank0_rd_data_way1_out_50 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4531 = _T_4530 | _T_4276; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_51; // @[Reg.scala 27:20]
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wire [21:0] _T_4277 = _T_2792 ? btb_bank0_rd_data_way1_out_51 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4532 = _T_4531 | _T_4277; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_52; // @[Reg.scala 27:20]
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wire [21:0] _T_4278 = _T_2794 ? btb_bank0_rd_data_way1_out_52 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4533 = _T_4532 | _T_4278; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_53; // @[Reg.scala 27:20]
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wire [21:0] _T_4279 = _T_2796 ? btb_bank0_rd_data_way1_out_53 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4534 = _T_4533 | _T_4279; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_54; // @[Reg.scala 27:20]
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wire [21:0] _T_4280 = _T_2798 ? btb_bank0_rd_data_way1_out_54 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4535 = _T_4534 | _T_4280; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_55; // @[Reg.scala 27:20]
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wire [21:0] _T_4281 = _T_2800 ? btb_bank0_rd_data_way1_out_55 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4536 = _T_4535 | _T_4281; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_56; // @[Reg.scala 27:20]
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wire [21:0] _T_4282 = _T_2802 ? btb_bank0_rd_data_way1_out_56 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4537 = _T_4536 | _T_4282; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_57; // @[Reg.scala 27:20]
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wire [21:0] _T_4283 = _T_2804 ? btb_bank0_rd_data_way1_out_57 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4538 = _T_4537 | _T_4283; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_58; // @[Reg.scala 27:20]
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wire [21:0] _T_4284 = _T_2806 ? btb_bank0_rd_data_way1_out_58 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4539 = _T_4538 | _T_4284; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_59; // @[Reg.scala 27:20]
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wire [21:0] _T_4285 = _T_2808 ? btb_bank0_rd_data_way1_out_59 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4540 = _T_4539 | _T_4285; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_60; // @[Reg.scala 27:20]
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wire [21:0] _T_4286 = _T_2810 ? btb_bank0_rd_data_way1_out_60 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4541 = _T_4540 | _T_4286; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_61; // @[Reg.scala 27:20]
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wire [21:0] _T_4287 = _T_2812 ? btb_bank0_rd_data_way1_out_61 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4542 = _T_4541 | _T_4287; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_62; // @[Reg.scala 27:20]
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wire [21:0] _T_4288 = _T_2814 ? btb_bank0_rd_data_way1_out_62 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4543 = _T_4542 | _T_4288; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_63; // @[Reg.scala 27:20]
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wire [21:0] _T_4289 = _T_2816 ? btb_bank0_rd_data_way1_out_63 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4544 = _T_4543 | _T_4289; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_64; // @[Reg.scala 27:20]
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wire [21:0] _T_4290 = _T_2818 ? btb_bank0_rd_data_way1_out_64 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4545 = _T_4544 | _T_4290; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_65; // @[Reg.scala 27:20]
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wire [21:0] _T_4291 = _T_2820 ? btb_bank0_rd_data_way1_out_65 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4546 = _T_4545 | _T_4291; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_66; // @[Reg.scala 27:20]
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wire [21:0] _T_4292 = _T_2822 ? btb_bank0_rd_data_way1_out_66 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4547 = _T_4546 | _T_4292; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_67; // @[Reg.scala 27:20]
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wire [21:0] _T_4293 = _T_2824 ? btb_bank0_rd_data_way1_out_67 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4548 = _T_4547 | _T_4293; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_68; // @[Reg.scala 27:20]
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wire [21:0] _T_4294 = _T_2826 ? btb_bank0_rd_data_way1_out_68 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4549 = _T_4548 | _T_4294; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_69; // @[Reg.scala 27:20]
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wire [21:0] _T_4295 = _T_2828 ? btb_bank0_rd_data_way1_out_69 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4550 = _T_4549 | _T_4295; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_70; // @[Reg.scala 27:20]
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wire [21:0] _T_4296 = _T_2830 ? btb_bank0_rd_data_way1_out_70 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4551 = _T_4550 | _T_4296; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_71; // @[Reg.scala 27:20]
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wire [21:0] _T_4297 = _T_2832 ? btb_bank0_rd_data_way1_out_71 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4552 = _T_4551 | _T_4297; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_72; // @[Reg.scala 27:20]
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wire [21:0] _T_4298 = _T_2834 ? btb_bank0_rd_data_way1_out_72 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4553 = _T_4552 | _T_4298; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_73; // @[Reg.scala 27:20]
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wire [21:0] _T_4299 = _T_2836 ? btb_bank0_rd_data_way1_out_73 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4554 = _T_4553 | _T_4299; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_74; // @[Reg.scala 27:20]
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wire [21:0] _T_4300 = _T_2838 ? btb_bank0_rd_data_way1_out_74 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4555 = _T_4554 | _T_4300; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_75; // @[Reg.scala 27:20]
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wire [21:0] _T_4301 = _T_2840 ? btb_bank0_rd_data_way1_out_75 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4556 = _T_4555 | _T_4301; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_76; // @[Reg.scala 27:20]
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wire [21:0] _T_4302 = _T_2842 ? btb_bank0_rd_data_way1_out_76 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4557 = _T_4556 | _T_4302; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_77; // @[Reg.scala 27:20]
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wire [21:0] _T_4303 = _T_2844 ? btb_bank0_rd_data_way1_out_77 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4558 = _T_4557 | _T_4303; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_78; // @[Reg.scala 27:20]
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wire [21:0] _T_4304 = _T_2846 ? btb_bank0_rd_data_way1_out_78 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4559 = _T_4558 | _T_4304; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_79; // @[Reg.scala 27:20]
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wire [21:0] _T_4305 = _T_2848 ? btb_bank0_rd_data_way1_out_79 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4560 = _T_4559 | _T_4305; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_80; // @[Reg.scala 27:20]
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wire [21:0] _T_4306 = _T_2850 ? btb_bank0_rd_data_way1_out_80 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4561 = _T_4560 | _T_4306; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_81; // @[Reg.scala 27:20]
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wire [21:0] _T_4307 = _T_2852 ? btb_bank0_rd_data_way1_out_81 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4562 = _T_4561 | _T_4307; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_82; // @[Reg.scala 27:20]
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wire [21:0] _T_4308 = _T_2854 ? btb_bank0_rd_data_way1_out_82 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4563 = _T_4562 | _T_4308; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_83; // @[Reg.scala 27:20]
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wire [21:0] _T_4309 = _T_2856 ? btb_bank0_rd_data_way1_out_83 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4564 = _T_4563 | _T_4309; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_84; // @[Reg.scala 27:20]
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wire [21:0] _T_4310 = _T_2858 ? btb_bank0_rd_data_way1_out_84 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4565 = _T_4564 | _T_4310; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_85; // @[Reg.scala 27:20]
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wire [21:0] _T_4311 = _T_2860 ? btb_bank0_rd_data_way1_out_85 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4566 = _T_4565 | _T_4311; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_86; // @[Reg.scala 27:20]
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wire [21:0] _T_4312 = _T_2862 ? btb_bank0_rd_data_way1_out_86 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4567 = _T_4566 | _T_4312; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_87; // @[Reg.scala 27:20]
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wire [21:0] _T_4313 = _T_2864 ? btb_bank0_rd_data_way1_out_87 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4568 = _T_4567 | _T_4313; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_88; // @[Reg.scala 27:20]
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wire [21:0] _T_4314 = _T_2866 ? btb_bank0_rd_data_way1_out_88 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4569 = _T_4568 | _T_4314; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_89; // @[Reg.scala 27:20]
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wire [21:0] _T_4315 = _T_2868 ? btb_bank0_rd_data_way1_out_89 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4570 = _T_4569 | _T_4315; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_90; // @[Reg.scala 27:20]
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wire [21:0] _T_4316 = _T_2870 ? btb_bank0_rd_data_way1_out_90 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4571 = _T_4570 | _T_4316; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_91; // @[Reg.scala 27:20]
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wire [21:0] _T_4317 = _T_2872 ? btb_bank0_rd_data_way1_out_91 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4572 = _T_4571 | _T_4317; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_92; // @[Reg.scala 27:20]
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wire [21:0] _T_4318 = _T_2874 ? btb_bank0_rd_data_way1_out_92 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4573 = _T_4572 | _T_4318; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_93; // @[Reg.scala 27:20]
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wire [21:0] _T_4319 = _T_2876 ? btb_bank0_rd_data_way1_out_93 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4574 = _T_4573 | _T_4319; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_94; // @[Reg.scala 27:20]
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wire [21:0] _T_4320 = _T_2878 ? btb_bank0_rd_data_way1_out_94 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4575 = _T_4574 | _T_4320; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_95; // @[Reg.scala 27:20]
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wire [21:0] _T_4321 = _T_2880 ? btb_bank0_rd_data_way1_out_95 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4576 = _T_4575 | _T_4321; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_96; // @[Reg.scala 27:20]
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wire [21:0] _T_4322 = _T_2882 ? btb_bank0_rd_data_way1_out_96 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4577 = _T_4576 | _T_4322; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_97; // @[Reg.scala 27:20]
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wire [21:0] _T_4323 = _T_2884 ? btb_bank0_rd_data_way1_out_97 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4578 = _T_4577 | _T_4323; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_98; // @[Reg.scala 27:20]
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wire [21:0] _T_4324 = _T_2886 ? btb_bank0_rd_data_way1_out_98 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4579 = _T_4578 | _T_4324; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_99; // @[Reg.scala 27:20]
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wire [21:0] _T_4325 = _T_2888 ? btb_bank0_rd_data_way1_out_99 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4580 = _T_4579 | _T_4325; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_100; // @[Reg.scala 27:20]
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wire [21:0] _T_4326 = _T_2890 ? btb_bank0_rd_data_way1_out_100 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4581 = _T_4580 | _T_4326; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_101; // @[Reg.scala 27:20]
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wire [21:0] _T_4327 = _T_2892 ? btb_bank0_rd_data_way1_out_101 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4582 = _T_4581 | _T_4327; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_102; // @[Reg.scala 27:20]
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wire [21:0] _T_4328 = _T_2894 ? btb_bank0_rd_data_way1_out_102 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4583 = _T_4582 | _T_4328; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_103; // @[Reg.scala 27:20]
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wire [21:0] _T_4329 = _T_2896 ? btb_bank0_rd_data_way1_out_103 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4584 = _T_4583 | _T_4329; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_104; // @[Reg.scala 27:20]
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wire [21:0] _T_4330 = _T_2898 ? btb_bank0_rd_data_way1_out_104 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4585 = _T_4584 | _T_4330; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_105; // @[Reg.scala 27:20]
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wire [21:0] _T_4331 = _T_2900 ? btb_bank0_rd_data_way1_out_105 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4586 = _T_4585 | _T_4331; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_106; // @[Reg.scala 27:20]
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wire [21:0] _T_4332 = _T_2902 ? btb_bank0_rd_data_way1_out_106 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4587 = _T_4586 | _T_4332; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_107; // @[Reg.scala 27:20]
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wire [21:0] _T_4333 = _T_2904 ? btb_bank0_rd_data_way1_out_107 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4588 = _T_4587 | _T_4333; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_108; // @[Reg.scala 27:20]
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wire [21:0] _T_4334 = _T_2906 ? btb_bank0_rd_data_way1_out_108 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4589 = _T_4588 | _T_4334; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_109; // @[Reg.scala 27:20]
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wire [21:0] _T_4335 = _T_2908 ? btb_bank0_rd_data_way1_out_109 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4590 = _T_4589 | _T_4335; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_110; // @[Reg.scala 27:20]
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wire [21:0] _T_4336 = _T_2910 ? btb_bank0_rd_data_way1_out_110 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4591 = _T_4590 | _T_4336; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_111; // @[Reg.scala 27:20]
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wire [21:0] _T_4337 = _T_2912 ? btb_bank0_rd_data_way1_out_111 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4592 = _T_4591 | _T_4337; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_112; // @[Reg.scala 27:20]
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wire [21:0] _T_4338 = _T_2914 ? btb_bank0_rd_data_way1_out_112 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4593 = _T_4592 | _T_4338; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_113; // @[Reg.scala 27:20]
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wire [21:0] _T_4339 = _T_2916 ? btb_bank0_rd_data_way1_out_113 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4594 = _T_4593 | _T_4339; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_114; // @[Reg.scala 27:20]
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wire [21:0] _T_4340 = _T_2918 ? btb_bank0_rd_data_way1_out_114 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4595 = _T_4594 | _T_4340; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_115; // @[Reg.scala 27:20]
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wire [21:0] _T_4341 = _T_2920 ? btb_bank0_rd_data_way1_out_115 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4596 = _T_4595 | _T_4341; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_116; // @[Reg.scala 27:20]
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wire [21:0] _T_4342 = _T_2922 ? btb_bank0_rd_data_way1_out_116 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4597 = _T_4596 | _T_4342; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_117; // @[Reg.scala 27:20]
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wire [21:0] _T_4343 = _T_2924 ? btb_bank0_rd_data_way1_out_117 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4598 = _T_4597 | _T_4343; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_118; // @[Reg.scala 27:20]
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wire [21:0] _T_4344 = _T_2926 ? btb_bank0_rd_data_way1_out_118 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4599 = _T_4598 | _T_4344; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_119; // @[Reg.scala 27:20]
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wire [21:0] _T_4345 = _T_2928 ? btb_bank0_rd_data_way1_out_119 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4600 = _T_4599 | _T_4345; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_120; // @[Reg.scala 27:20]
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wire [21:0] _T_4346 = _T_2930 ? btb_bank0_rd_data_way1_out_120 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4601 = _T_4600 | _T_4346; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_121; // @[Reg.scala 27:20]
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wire [21:0] _T_4347 = _T_2932 ? btb_bank0_rd_data_way1_out_121 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4602 = _T_4601 | _T_4347; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_122; // @[Reg.scala 27:20]
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wire [21:0] _T_4348 = _T_2934 ? btb_bank0_rd_data_way1_out_122 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4603 = _T_4602 | _T_4348; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_123; // @[Reg.scala 27:20]
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wire [21:0] _T_4349 = _T_2936 ? btb_bank0_rd_data_way1_out_123 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4604 = _T_4603 | _T_4349; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_124; // @[Reg.scala 27:20]
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wire [21:0] _T_4350 = _T_2938 ? btb_bank0_rd_data_way1_out_124 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4605 = _T_4604 | _T_4350; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_125; // @[Reg.scala 27:20]
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wire [21:0] _T_4351 = _T_2940 ? btb_bank0_rd_data_way1_out_125 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4606 = _T_4605 | _T_4351; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_126; // @[Reg.scala 27:20]
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wire [21:0] _T_4352 = _T_2942 ? btb_bank0_rd_data_way1_out_126 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4607 = _T_4606 | _T_4352; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_127; // @[Reg.scala 27:20]
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wire [21:0] _T_4353 = _T_2944 ? btb_bank0_rd_data_way1_out_127 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4608 = _T_4607 | _T_4353; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_128; // @[Reg.scala 27:20]
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wire [21:0] _T_4354 = _T_2946 ? btb_bank0_rd_data_way1_out_128 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4609 = _T_4608 | _T_4354; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_129; // @[Reg.scala 27:20]
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wire [21:0] _T_4355 = _T_2948 ? btb_bank0_rd_data_way1_out_129 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4610 = _T_4609 | _T_4355; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_130; // @[Reg.scala 27:20]
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wire [21:0] _T_4356 = _T_2950 ? btb_bank0_rd_data_way1_out_130 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4611 = _T_4610 | _T_4356; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_131; // @[Reg.scala 27:20]
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wire [21:0] _T_4357 = _T_2952 ? btb_bank0_rd_data_way1_out_131 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4612 = _T_4611 | _T_4357; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_132; // @[Reg.scala 27:20]
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wire [21:0] _T_4358 = _T_2954 ? btb_bank0_rd_data_way1_out_132 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4613 = _T_4612 | _T_4358; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_133; // @[Reg.scala 27:20]
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wire [21:0] _T_4359 = _T_2956 ? btb_bank0_rd_data_way1_out_133 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4614 = _T_4613 | _T_4359; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_134; // @[Reg.scala 27:20]
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wire [21:0] _T_4360 = _T_2958 ? btb_bank0_rd_data_way1_out_134 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4615 = _T_4614 | _T_4360; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_135; // @[Reg.scala 27:20]
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wire [21:0] _T_4361 = _T_2960 ? btb_bank0_rd_data_way1_out_135 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4616 = _T_4615 | _T_4361; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_136; // @[Reg.scala 27:20]
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wire [21:0] _T_4362 = _T_2962 ? btb_bank0_rd_data_way1_out_136 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4617 = _T_4616 | _T_4362; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_137; // @[Reg.scala 27:20]
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wire [21:0] _T_4363 = _T_2964 ? btb_bank0_rd_data_way1_out_137 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4618 = _T_4617 | _T_4363; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_138; // @[Reg.scala 27:20]
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wire [21:0] _T_4364 = _T_2966 ? btb_bank0_rd_data_way1_out_138 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4619 = _T_4618 | _T_4364; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_139; // @[Reg.scala 27:20]
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wire [21:0] _T_4365 = _T_2968 ? btb_bank0_rd_data_way1_out_139 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4620 = _T_4619 | _T_4365; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_140; // @[Reg.scala 27:20]
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wire [21:0] _T_4366 = _T_2970 ? btb_bank0_rd_data_way1_out_140 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4621 = _T_4620 | _T_4366; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_141; // @[Reg.scala 27:20]
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wire [21:0] _T_4367 = _T_2972 ? btb_bank0_rd_data_way1_out_141 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4622 = _T_4621 | _T_4367; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_142; // @[Reg.scala 27:20]
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wire [21:0] _T_4368 = _T_2974 ? btb_bank0_rd_data_way1_out_142 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4623 = _T_4622 | _T_4368; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_143; // @[Reg.scala 27:20]
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wire [21:0] _T_4369 = _T_2976 ? btb_bank0_rd_data_way1_out_143 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4624 = _T_4623 | _T_4369; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_144; // @[Reg.scala 27:20]
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wire [21:0] _T_4370 = _T_2978 ? btb_bank0_rd_data_way1_out_144 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4625 = _T_4624 | _T_4370; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_145; // @[Reg.scala 27:20]
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wire [21:0] _T_4371 = _T_2980 ? btb_bank0_rd_data_way1_out_145 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4626 = _T_4625 | _T_4371; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_146; // @[Reg.scala 27:20]
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wire [21:0] _T_4372 = _T_2982 ? btb_bank0_rd_data_way1_out_146 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4627 = _T_4626 | _T_4372; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_147; // @[Reg.scala 27:20]
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wire [21:0] _T_4373 = _T_2984 ? btb_bank0_rd_data_way1_out_147 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4628 = _T_4627 | _T_4373; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_148; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4374 = _T_2986 ? btb_bank0_rd_data_way1_out_148 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4629 = _T_4628 | _T_4374; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_149; // @[Reg.scala 27:20]
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wire [21:0] _T_4375 = _T_2988 ? btb_bank0_rd_data_way1_out_149 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4630 = _T_4629 | _T_4375; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_150; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4376 = _T_2990 ? btb_bank0_rd_data_way1_out_150 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4631 = _T_4630 | _T_4376; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_151; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4377 = _T_2992 ? btb_bank0_rd_data_way1_out_151 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4632 = _T_4631 | _T_4377; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_152; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4378 = _T_2994 ? btb_bank0_rd_data_way1_out_152 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_4633 = _T_4632 | _T_4378; // @[Mux.scala 27:72]
|
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reg [21:0] btb_bank0_rd_data_way1_out_153; // @[Reg.scala 27:20]
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wire [21:0] _T_4379 = _T_2996 ? btb_bank0_rd_data_way1_out_153 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4634 = _T_4633 | _T_4379; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_154; // @[Reg.scala 27:20]
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wire [21:0] _T_4380 = _T_2998 ? btb_bank0_rd_data_way1_out_154 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4635 = _T_4634 | _T_4380; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_155; // @[Reg.scala 27:20]
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wire [21:0] _T_4381 = _T_3000 ? btb_bank0_rd_data_way1_out_155 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4636 = _T_4635 | _T_4381; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_156; // @[Reg.scala 27:20]
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wire [21:0] _T_4382 = _T_3002 ? btb_bank0_rd_data_way1_out_156 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4637 = _T_4636 | _T_4382; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_157; // @[Reg.scala 27:20]
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wire [21:0] _T_4383 = _T_3004 ? btb_bank0_rd_data_way1_out_157 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4638 = _T_4637 | _T_4383; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_158; // @[Reg.scala 27:20]
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wire [21:0] _T_4384 = _T_3006 ? btb_bank0_rd_data_way1_out_158 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4639 = _T_4638 | _T_4384; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_159; // @[Reg.scala 27:20]
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wire [21:0] _T_4385 = _T_3008 ? btb_bank0_rd_data_way1_out_159 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4640 = _T_4639 | _T_4385; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_160; // @[Reg.scala 27:20]
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wire [21:0] _T_4386 = _T_3010 ? btb_bank0_rd_data_way1_out_160 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4641 = _T_4640 | _T_4386; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_161; // @[Reg.scala 27:20]
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wire [21:0] _T_4387 = _T_3012 ? btb_bank0_rd_data_way1_out_161 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4642 = _T_4641 | _T_4387; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_162; // @[Reg.scala 27:20]
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wire [21:0] _T_4388 = _T_3014 ? btb_bank0_rd_data_way1_out_162 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4643 = _T_4642 | _T_4388; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_163; // @[Reg.scala 27:20]
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wire [21:0] _T_4389 = _T_3016 ? btb_bank0_rd_data_way1_out_163 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4644 = _T_4643 | _T_4389; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_164; // @[Reg.scala 27:20]
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wire [21:0] _T_4390 = _T_3018 ? btb_bank0_rd_data_way1_out_164 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4645 = _T_4644 | _T_4390; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_165; // @[Reg.scala 27:20]
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wire [21:0] _T_4391 = _T_3020 ? btb_bank0_rd_data_way1_out_165 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4646 = _T_4645 | _T_4391; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_166; // @[Reg.scala 27:20]
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wire [21:0] _T_4392 = _T_3022 ? btb_bank0_rd_data_way1_out_166 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4647 = _T_4646 | _T_4392; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_167; // @[Reg.scala 27:20]
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wire [21:0] _T_4393 = _T_3024 ? btb_bank0_rd_data_way1_out_167 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4648 = _T_4647 | _T_4393; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_168; // @[Reg.scala 27:20]
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wire [21:0] _T_4394 = _T_3026 ? btb_bank0_rd_data_way1_out_168 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4649 = _T_4648 | _T_4394; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_169; // @[Reg.scala 27:20]
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wire [21:0] _T_4395 = _T_3028 ? btb_bank0_rd_data_way1_out_169 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4650 = _T_4649 | _T_4395; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_170; // @[Reg.scala 27:20]
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wire [21:0] _T_4396 = _T_3030 ? btb_bank0_rd_data_way1_out_170 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4651 = _T_4650 | _T_4396; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_171; // @[Reg.scala 27:20]
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wire [21:0] _T_4397 = _T_3032 ? btb_bank0_rd_data_way1_out_171 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4652 = _T_4651 | _T_4397; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_172; // @[Reg.scala 27:20]
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wire [21:0] _T_4398 = _T_3034 ? btb_bank0_rd_data_way1_out_172 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4653 = _T_4652 | _T_4398; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_173; // @[Reg.scala 27:20]
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wire [21:0] _T_4399 = _T_3036 ? btb_bank0_rd_data_way1_out_173 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4654 = _T_4653 | _T_4399; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_174; // @[Reg.scala 27:20]
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wire [21:0] _T_4400 = _T_3038 ? btb_bank0_rd_data_way1_out_174 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4655 = _T_4654 | _T_4400; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_175; // @[Reg.scala 27:20]
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wire [21:0] _T_4401 = _T_3040 ? btb_bank0_rd_data_way1_out_175 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4656 = _T_4655 | _T_4401; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_176; // @[Reg.scala 27:20]
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wire [21:0] _T_4402 = _T_3042 ? btb_bank0_rd_data_way1_out_176 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4657 = _T_4656 | _T_4402; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_177; // @[Reg.scala 27:20]
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wire [21:0] _T_4403 = _T_3044 ? btb_bank0_rd_data_way1_out_177 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4658 = _T_4657 | _T_4403; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_178; // @[Reg.scala 27:20]
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wire [21:0] _T_4404 = _T_3046 ? btb_bank0_rd_data_way1_out_178 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4659 = _T_4658 | _T_4404; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_179; // @[Reg.scala 27:20]
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wire [21:0] _T_4405 = _T_3048 ? btb_bank0_rd_data_way1_out_179 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4660 = _T_4659 | _T_4405; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_180; // @[Reg.scala 27:20]
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wire [21:0] _T_4406 = _T_3050 ? btb_bank0_rd_data_way1_out_180 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4661 = _T_4660 | _T_4406; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_181; // @[Reg.scala 27:20]
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wire [21:0] _T_4407 = _T_3052 ? btb_bank0_rd_data_way1_out_181 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4662 = _T_4661 | _T_4407; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_182; // @[Reg.scala 27:20]
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wire [21:0] _T_4408 = _T_3054 ? btb_bank0_rd_data_way1_out_182 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4663 = _T_4662 | _T_4408; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_183; // @[Reg.scala 27:20]
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wire [21:0] _T_4409 = _T_3056 ? btb_bank0_rd_data_way1_out_183 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4664 = _T_4663 | _T_4409; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_184; // @[Reg.scala 27:20]
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wire [21:0] _T_4410 = _T_3058 ? btb_bank0_rd_data_way1_out_184 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4665 = _T_4664 | _T_4410; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_185; // @[Reg.scala 27:20]
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wire [21:0] _T_4411 = _T_3060 ? btb_bank0_rd_data_way1_out_185 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4666 = _T_4665 | _T_4411; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_186; // @[Reg.scala 27:20]
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wire [21:0] _T_4412 = _T_3062 ? btb_bank0_rd_data_way1_out_186 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4667 = _T_4666 | _T_4412; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_187; // @[Reg.scala 27:20]
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wire [21:0] _T_4413 = _T_3064 ? btb_bank0_rd_data_way1_out_187 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4668 = _T_4667 | _T_4413; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_188; // @[Reg.scala 27:20]
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wire [21:0] _T_4414 = _T_3066 ? btb_bank0_rd_data_way1_out_188 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4669 = _T_4668 | _T_4414; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_189; // @[Reg.scala 27:20]
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wire [21:0] _T_4415 = _T_3068 ? btb_bank0_rd_data_way1_out_189 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4670 = _T_4669 | _T_4415; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_190; // @[Reg.scala 27:20]
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wire [21:0] _T_4416 = _T_3070 ? btb_bank0_rd_data_way1_out_190 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4671 = _T_4670 | _T_4416; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_191; // @[Reg.scala 27:20]
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wire [21:0] _T_4417 = _T_3072 ? btb_bank0_rd_data_way1_out_191 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4672 = _T_4671 | _T_4417; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_192; // @[Reg.scala 27:20]
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wire [21:0] _T_4418 = _T_3074 ? btb_bank0_rd_data_way1_out_192 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4673 = _T_4672 | _T_4418; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_193; // @[Reg.scala 27:20]
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wire [21:0] _T_4419 = _T_3076 ? btb_bank0_rd_data_way1_out_193 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4674 = _T_4673 | _T_4419; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_194; // @[Reg.scala 27:20]
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wire [21:0] _T_4420 = _T_3078 ? btb_bank0_rd_data_way1_out_194 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4675 = _T_4674 | _T_4420; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_195; // @[Reg.scala 27:20]
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wire [21:0] _T_4421 = _T_3080 ? btb_bank0_rd_data_way1_out_195 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4676 = _T_4675 | _T_4421; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_196; // @[Reg.scala 27:20]
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wire [21:0] _T_4422 = _T_3082 ? btb_bank0_rd_data_way1_out_196 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4677 = _T_4676 | _T_4422; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_197; // @[Reg.scala 27:20]
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wire [21:0] _T_4423 = _T_3084 ? btb_bank0_rd_data_way1_out_197 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4678 = _T_4677 | _T_4423; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_198; // @[Reg.scala 27:20]
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wire [21:0] _T_4424 = _T_3086 ? btb_bank0_rd_data_way1_out_198 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4679 = _T_4678 | _T_4424; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_199; // @[Reg.scala 27:20]
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wire [21:0] _T_4425 = _T_3088 ? btb_bank0_rd_data_way1_out_199 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4680 = _T_4679 | _T_4425; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_200; // @[Reg.scala 27:20]
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wire [21:0] _T_4426 = _T_3090 ? btb_bank0_rd_data_way1_out_200 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4681 = _T_4680 | _T_4426; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_201; // @[Reg.scala 27:20]
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wire [21:0] _T_4427 = _T_3092 ? btb_bank0_rd_data_way1_out_201 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4682 = _T_4681 | _T_4427; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_202; // @[Reg.scala 27:20]
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wire [21:0] _T_4428 = _T_3094 ? btb_bank0_rd_data_way1_out_202 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4683 = _T_4682 | _T_4428; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_203; // @[Reg.scala 27:20]
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wire [21:0] _T_4429 = _T_3096 ? btb_bank0_rd_data_way1_out_203 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4684 = _T_4683 | _T_4429; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_204; // @[Reg.scala 27:20]
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wire [21:0] _T_4430 = _T_3098 ? btb_bank0_rd_data_way1_out_204 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4685 = _T_4684 | _T_4430; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_205; // @[Reg.scala 27:20]
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wire [21:0] _T_4431 = _T_3100 ? btb_bank0_rd_data_way1_out_205 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4686 = _T_4685 | _T_4431; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_206; // @[Reg.scala 27:20]
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wire [21:0] _T_4432 = _T_3102 ? btb_bank0_rd_data_way1_out_206 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4687 = _T_4686 | _T_4432; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_207; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4433 = _T_3104 ? btb_bank0_rd_data_way1_out_207 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4688 = _T_4687 | _T_4433; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_208; // @[Reg.scala 27:20]
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wire [21:0] _T_4434 = _T_3106 ? btb_bank0_rd_data_way1_out_208 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4689 = _T_4688 | _T_4434; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_209; // @[Reg.scala 27:20]
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wire [21:0] _T_4435 = _T_3108 ? btb_bank0_rd_data_way1_out_209 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4690 = _T_4689 | _T_4435; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_210; // @[Reg.scala 27:20]
|
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wire [21:0] _T_4436 = _T_3110 ? btb_bank0_rd_data_way1_out_210 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4691 = _T_4690 | _T_4436; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_211; // @[Reg.scala 27:20]
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wire [21:0] _T_4437 = _T_3112 ? btb_bank0_rd_data_way1_out_211 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4692 = _T_4691 | _T_4437; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_212; // @[Reg.scala 27:20]
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wire [21:0] _T_4438 = _T_3114 ? btb_bank0_rd_data_way1_out_212 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4693 = _T_4692 | _T_4438; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_213; // @[Reg.scala 27:20]
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wire [21:0] _T_4439 = _T_3116 ? btb_bank0_rd_data_way1_out_213 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4694 = _T_4693 | _T_4439; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_214; // @[Reg.scala 27:20]
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wire [21:0] _T_4440 = _T_3118 ? btb_bank0_rd_data_way1_out_214 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4695 = _T_4694 | _T_4440; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_215; // @[Reg.scala 27:20]
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wire [21:0] _T_4441 = _T_3120 ? btb_bank0_rd_data_way1_out_215 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4696 = _T_4695 | _T_4441; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_216; // @[Reg.scala 27:20]
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wire [21:0] _T_4442 = _T_3122 ? btb_bank0_rd_data_way1_out_216 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4697 = _T_4696 | _T_4442; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_217; // @[Reg.scala 27:20]
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wire [21:0] _T_4443 = _T_3124 ? btb_bank0_rd_data_way1_out_217 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4698 = _T_4697 | _T_4443; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_218; // @[Reg.scala 27:20]
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wire [21:0] _T_4444 = _T_3126 ? btb_bank0_rd_data_way1_out_218 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4699 = _T_4698 | _T_4444; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_219; // @[Reg.scala 27:20]
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wire [21:0] _T_4445 = _T_3128 ? btb_bank0_rd_data_way1_out_219 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4700 = _T_4699 | _T_4445; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_220; // @[Reg.scala 27:20]
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wire [21:0] _T_4446 = _T_3130 ? btb_bank0_rd_data_way1_out_220 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4701 = _T_4700 | _T_4446; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_221; // @[Reg.scala 27:20]
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wire [21:0] _T_4447 = _T_3132 ? btb_bank0_rd_data_way1_out_221 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4702 = _T_4701 | _T_4447; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_222; // @[Reg.scala 27:20]
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wire [21:0] _T_4448 = _T_3134 ? btb_bank0_rd_data_way1_out_222 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4703 = _T_4702 | _T_4448; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_223; // @[Reg.scala 27:20]
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wire [21:0] _T_4449 = _T_3136 ? btb_bank0_rd_data_way1_out_223 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4704 = _T_4703 | _T_4449; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_224; // @[Reg.scala 27:20]
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wire [21:0] _T_4450 = _T_3138 ? btb_bank0_rd_data_way1_out_224 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4705 = _T_4704 | _T_4450; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_225; // @[Reg.scala 27:20]
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wire [21:0] _T_4451 = _T_3140 ? btb_bank0_rd_data_way1_out_225 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4706 = _T_4705 | _T_4451; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_226; // @[Reg.scala 27:20]
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wire [21:0] _T_4452 = _T_3142 ? btb_bank0_rd_data_way1_out_226 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4707 = _T_4706 | _T_4452; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_227; // @[Reg.scala 27:20]
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wire [21:0] _T_4453 = _T_3144 ? btb_bank0_rd_data_way1_out_227 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4708 = _T_4707 | _T_4453; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_228; // @[Reg.scala 27:20]
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wire [21:0] _T_4454 = _T_3146 ? btb_bank0_rd_data_way1_out_228 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4709 = _T_4708 | _T_4454; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_229; // @[Reg.scala 27:20]
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wire [21:0] _T_4455 = _T_3148 ? btb_bank0_rd_data_way1_out_229 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4710 = _T_4709 | _T_4455; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_230; // @[Reg.scala 27:20]
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wire [21:0] _T_4456 = _T_3150 ? btb_bank0_rd_data_way1_out_230 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4711 = _T_4710 | _T_4456; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_231; // @[Reg.scala 27:20]
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wire [21:0] _T_4457 = _T_3152 ? btb_bank0_rd_data_way1_out_231 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4712 = _T_4711 | _T_4457; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_232; // @[Reg.scala 27:20]
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wire [21:0] _T_4458 = _T_3154 ? btb_bank0_rd_data_way1_out_232 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4713 = _T_4712 | _T_4458; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_233; // @[Reg.scala 27:20]
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wire [21:0] _T_4459 = _T_3156 ? btb_bank0_rd_data_way1_out_233 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4714 = _T_4713 | _T_4459; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_234; // @[Reg.scala 27:20]
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wire [21:0] _T_4460 = _T_3158 ? btb_bank0_rd_data_way1_out_234 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4715 = _T_4714 | _T_4460; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_235; // @[Reg.scala 27:20]
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wire [21:0] _T_4461 = _T_3160 ? btb_bank0_rd_data_way1_out_235 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4716 = _T_4715 | _T_4461; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_236; // @[Reg.scala 27:20]
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wire [21:0] _T_4462 = _T_3162 ? btb_bank0_rd_data_way1_out_236 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4717 = _T_4716 | _T_4462; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_237; // @[Reg.scala 27:20]
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wire [21:0] _T_4463 = _T_3164 ? btb_bank0_rd_data_way1_out_237 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4718 = _T_4717 | _T_4463; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_238; // @[Reg.scala 27:20]
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wire [21:0] _T_4464 = _T_3166 ? btb_bank0_rd_data_way1_out_238 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4719 = _T_4718 | _T_4464; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_239; // @[Reg.scala 27:20]
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wire [21:0] _T_4465 = _T_3168 ? btb_bank0_rd_data_way1_out_239 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4720 = _T_4719 | _T_4465; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_240; // @[Reg.scala 27:20]
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wire [21:0] _T_4466 = _T_3170 ? btb_bank0_rd_data_way1_out_240 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4721 = _T_4720 | _T_4466; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_241; // @[Reg.scala 27:20]
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wire [21:0] _T_4467 = _T_3172 ? btb_bank0_rd_data_way1_out_241 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4722 = _T_4721 | _T_4467; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_242; // @[Reg.scala 27:20]
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wire [21:0] _T_4468 = _T_3174 ? btb_bank0_rd_data_way1_out_242 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4723 = _T_4722 | _T_4468; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_243; // @[Reg.scala 27:20]
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wire [21:0] _T_4469 = _T_3176 ? btb_bank0_rd_data_way1_out_243 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4724 = _T_4723 | _T_4469; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_244; // @[Reg.scala 27:20]
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wire [21:0] _T_4470 = _T_3178 ? btb_bank0_rd_data_way1_out_244 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4725 = _T_4724 | _T_4470; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_245; // @[Reg.scala 27:20]
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wire [21:0] _T_4471 = _T_3180 ? btb_bank0_rd_data_way1_out_245 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4726 = _T_4725 | _T_4471; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_246; // @[Reg.scala 27:20]
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wire [21:0] _T_4472 = _T_3182 ? btb_bank0_rd_data_way1_out_246 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4727 = _T_4726 | _T_4472; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_247; // @[Reg.scala 27:20]
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wire [21:0] _T_4473 = _T_3184 ? btb_bank0_rd_data_way1_out_247 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4728 = _T_4727 | _T_4473; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_248; // @[Reg.scala 27:20]
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wire [21:0] _T_4474 = _T_3186 ? btb_bank0_rd_data_way1_out_248 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4729 = _T_4728 | _T_4474; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_249; // @[Reg.scala 27:20]
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wire [21:0] _T_4475 = _T_3188 ? btb_bank0_rd_data_way1_out_249 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4730 = _T_4729 | _T_4475; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_250; // @[Reg.scala 27:20]
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wire [21:0] _T_4476 = _T_3190 ? btb_bank0_rd_data_way1_out_250 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4731 = _T_4730 | _T_4476; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_251; // @[Reg.scala 27:20]
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wire [21:0] _T_4477 = _T_3192 ? btb_bank0_rd_data_way1_out_251 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4732 = _T_4731 | _T_4477; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_252; // @[Reg.scala 27:20]
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wire [21:0] _T_4478 = _T_3194 ? btb_bank0_rd_data_way1_out_252 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4733 = _T_4732 | _T_4478; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_253; // @[Reg.scala 27:20]
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wire [21:0] _T_4479 = _T_3196 ? btb_bank0_rd_data_way1_out_253 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4734 = _T_4733 | _T_4479; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_254; // @[Reg.scala 27:20]
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wire [21:0] _T_4480 = _T_3198 ? btb_bank0_rd_data_way1_out_254 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_4735 = _T_4734 | _T_4480; // @[Mux.scala 27:72]
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reg [21:0] btb_bank0_rd_data_way1_out_255; // @[Reg.scala 27:20]
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wire [21:0] _T_4481 = _T_3200 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] btb_bank0_rd_data_way1_f = _T_4735 | _T_4481; // @[Mux.scala 27:72]
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wire _T_60 = btb_bank0_rd_data_way1_f[21:17] == _T_30; // @[ifu_bp_ctl.scala 147:100]
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wire _T_61 = btb_bank0_rd_data_way1_f[0] & _T_60; // @[ifu_bp_ctl.scala 147:57]
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wire _T_64 = _T_61 & _T_53; // @[ifu_bp_ctl.scala 147:120]
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wire _T_65 = _T_64 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 148:56]
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wire _T_67 = _T_65 & _T; // @[ifu_bp_ctl.scala 148:77]
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wire _T_100 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[ifu_bp_ctl.scala 161:92]
|
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wire _T_101 = _T_67 & _T_100; // @[ifu_bp_ctl.scala 161:58]
|
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wire _T_105 = ~_T_100; // @[ifu_bp_ctl.scala 162:26]
|
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wire _T_106 = _T_67 & _T_105; // @[ifu_bp_ctl.scala 162:24]
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wire [1:0] _T_107 = {_T_101,_T_106}; // @[Cat.scala 29:58]
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wire [21:0] _T_143 = _T_107[1] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72]
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wire [21:0] _T_144 = _T_142 | _T_143; // @[Mux.scala 27:72]
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wire [21:0] _T_164 = _T_162 ? _T_144 : 22'h0; // @[Mux.scala 27:72]
|
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wire _T_4738 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5250 = _T_4738 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
|
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wire _T_4740 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5251 = _T_4740 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5506 = _T_5250 | _T_5251; // @[Mux.scala 27:72]
|
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wire _T_4742 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5252 = _T_4742 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5507 = _T_5506 | _T_5252; // @[Mux.scala 27:72]
|
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wire _T_4744 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5253 = _T_4744 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5508 = _T_5507 | _T_5253; // @[Mux.scala 27:72]
|
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wire _T_4746 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5254 = _T_4746 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5509 = _T_5508 | _T_5254; // @[Mux.scala 27:72]
|
|
wire _T_4748 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5255 = _T_4748 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5510 = _T_5509 | _T_5255; // @[Mux.scala 27:72]
|
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wire _T_4750 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 438:88]
|
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wire [21:0] _T_5256 = _T_4750 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5511 = _T_5510 | _T_5256; // @[Mux.scala 27:72]
|
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wire _T_4752 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5257 = _T_4752 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5512 = _T_5511 | _T_5257; // @[Mux.scala 27:72]
|
|
wire _T_4754 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5258 = _T_4754 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5513 = _T_5512 | _T_5258; // @[Mux.scala 27:72]
|
|
wire _T_4756 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5259 = _T_4756 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5514 = _T_5513 | _T_5259; // @[Mux.scala 27:72]
|
|
wire _T_4758 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5260 = _T_4758 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5515 = _T_5514 | _T_5260; // @[Mux.scala 27:72]
|
|
wire _T_4760 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5261 = _T_4760 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5516 = _T_5515 | _T_5261; // @[Mux.scala 27:72]
|
|
wire _T_4762 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5262 = _T_4762 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5517 = _T_5516 | _T_5262; // @[Mux.scala 27:72]
|
|
wire _T_4764 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5263 = _T_4764 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5518 = _T_5517 | _T_5263; // @[Mux.scala 27:72]
|
|
wire _T_4766 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5264 = _T_4766 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5519 = _T_5518 | _T_5264; // @[Mux.scala 27:72]
|
|
wire _T_4768 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5265 = _T_4768 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5520 = _T_5519 | _T_5265; // @[Mux.scala 27:72]
|
|
wire _T_4770 = btb_rd_addr_p1_f == 8'h10; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5266 = _T_4770 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5521 = _T_5520 | _T_5266; // @[Mux.scala 27:72]
|
|
wire _T_4772 = btb_rd_addr_p1_f == 8'h11; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5267 = _T_4772 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5522 = _T_5521 | _T_5267; // @[Mux.scala 27:72]
|
|
wire _T_4774 = btb_rd_addr_p1_f == 8'h12; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5268 = _T_4774 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5523 = _T_5522 | _T_5268; // @[Mux.scala 27:72]
|
|
wire _T_4776 = btb_rd_addr_p1_f == 8'h13; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5269 = _T_4776 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5524 = _T_5523 | _T_5269; // @[Mux.scala 27:72]
|
|
wire _T_4778 = btb_rd_addr_p1_f == 8'h14; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5270 = _T_4778 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5525 = _T_5524 | _T_5270; // @[Mux.scala 27:72]
|
|
wire _T_4780 = btb_rd_addr_p1_f == 8'h15; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5271 = _T_4780 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5526 = _T_5525 | _T_5271; // @[Mux.scala 27:72]
|
|
wire _T_4782 = btb_rd_addr_p1_f == 8'h16; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5272 = _T_4782 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5527 = _T_5526 | _T_5272; // @[Mux.scala 27:72]
|
|
wire _T_4784 = btb_rd_addr_p1_f == 8'h17; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5273 = _T_4784 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5528 = _T_5527 | _T_5273; // @[Mux.scala 27:72]
|
|
wire _T_4786 = btb_rd_addr_p1_f == 8'h18; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5274 = _T_4786 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5529 = _T_5528 | _T_5274; // @[Mux.scala 27:72]
|
|
wire _T_4788 = btb_rd_addr_p1_f == 8'h19; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5275 = _T_4788 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5530 = _T_5529 | _T_5275; // @[Mux.scala 27:72]
|
|
wire _T_4790 = btb_rd_addr_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5276 = _T_4790 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5531 = _T_5530 | _T_5276; // @[Mux.scala 27:72]
|
|
wire _T_4792 = btb_rd_addr_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5277 = _T_4792 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5532 = _T_5531 | _T_5277; // @[Mux.scala 27:72]
|
|
wire _T_4794 = btb_rd_addr_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5278 = _T_4794 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5533 = _T_5532 | _T_5278; // @[Mux.scala 27:72]
|
|
wire _T_4796 = btb_rd_addr_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5279 = _T_4796 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5534 = _T_5533 | _T_5279; // @[Mux.scala 27:72]
|
|
wire _T_4798 = btb_rd_addr_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5280 = _T_4798 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5535 = _T_5534 | _T_5280; // @[Mux.scala 27:72]
|
|
wire _T_4800 = btb_rd_addr_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5281 = _T_4800 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5536 = _T_5535 | _T_5281; // @[Mux.scala 27:72]
|
|
wire _T_4802 = btb_rd_addr_p1_f == 8'h20; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5282 = _T_4802 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5537 = _T_5536 | _T_5282; // @[Mux.scala 27:72]
|
|
wire _T_4804 = btb_rd_addr_p1_f == 8'h21; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5283 = _T_4804 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5538 = _T_5537 | _T_5283; // @[Mux.scala 27:72]
|
|
wire _T_4806 = btb_rd_addr_p1_f == 8'h22; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5284 = _T_4806 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5539 = _T_5538 | _T_5284; // @[Mux.scala 27:72]
|
|
wire _T_4808 = btb_rd_addr_p1_f == 8'h23; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5285 = _T_4808 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5540 = _T_5539 | _T_5285; // @[Mux.scala 27:72]
|
|
wire _T_4810 = btb_rd_addr_p1_f == 8'h24; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5286 = _T_4810 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5541 = _T_5540 | _T_5286; // @[Mux.scala 27:72]
|
|
wire _T_4812 = btb_rd_addr_p1_f == 8'h25; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5287 = _T_4812 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5542 = _T_5541 | _T_5287; // @[Mux.scala 27:72]
|
|
wire _T_4814 = btb_rd_addr_p1_f == 8'h26; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5288 = _T_4814 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5543 = _T_5542 | _T_5288; // @[Mux.scala 27:72]
|
|
wire _T_4816 = btb_rd_addr_p1_f == 8'h27; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5289 = _T_4816 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5544 = _T_5543 | _T_5289; // @[Mux.scala 27:72]
|
|
wire _T_4818 = btb_rd_addr_p1_f == 8'h28; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5290 = _T_4818 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5545 = _T_5544 | _T_5290; // @[Mux.scala 27:72]
|
|
wire _T_4820 = btb_rd_addr_p1_f == 8'h29; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5291 = _T_4820 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5546 = _T_5545 | _T_5291; // @[Mux.scala 27:72]
|
|
wire _T_4822 = btb_rd_addr_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5292 = _T_4822 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5547 = _T_5546 | _T_5292; // @[Mux.scala 27:72]
|
|
wire _T_4824 = btb_rd_addr_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5293 = _T_4824 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5548 = _T_5547 | _T_5293; // @[Mux.scala 27:72]
|
|
wire _T_4826 = btb_rd_addr_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5294 = _T_4826 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5549 = _T_5548 | _T_5294; // @[Mux.scala 27:72]
|
|
wire _T_4828 = btb_rd_addr_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5295 = _T_4828 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5550 = _T_5549 | _T_5295; // @[Mux.scala 27:72]
|
|
wire _T_4830 = btb_rd_addr_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5296 = _T_4830 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5551 = _T_5550 | _T_5296; // @[Mux.scala 27:72]
|
|
wire _T_4832 = btb_rd_addr_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5297 = _T_4832 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5552 = _T_5551 | _T_5297; // @[Mux.scala 27:72]
|
|
wire _T_4834 = btb_rd_addr_p1_f == 8'h30; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5298 = _T_4834 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5553 = _T_5552 | _T_5298; // @[Mux.scala 27:72]
|
|
wire _T_4836 = btb_rd_addr_p1_f == 8'h31; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5299 = _T_4836 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5554 = _T_5553 | _T_5299; // @[Mux.scala 27:72]
|
|
wire _T_4838 = btb_rd_addr_p1_f == 8'h32; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5300 = _T_4838 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5555 = _T_5554 | _T_5300; // @[Mux.scala 27:72]
|
|
wire _T_4840 = btb_rd_addr_p1_f == 8'h33; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5301 = _T_4840 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5556 = _T_5555 | _T_5301; // @[Mux.scala 27:72]
|
|
wire _T_4842 = btb_rd_addr_p1_f == 8'h34; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5302 = _T_4842 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5557 = _T_5556 | _T_5302; // @[Mux.scala 27:72]
|
|
wire _T_4844 = btb_rd_addr_p1_f == 8'h35; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5303 = _T_4844 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5558 = _T_5557 | _T_5303; // @[Mux.scala 27:72]
|
|
wire _T_4846 = btb_rd_addr_p1_f == 8'h36; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5304 = _T_4846 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5559 = _T_5558 | _T_5304; // @[Mux.scala 27:72]
|
|
wire _T_4848 = btb_rd_addr_p1_f == 8'h37; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5305 = _T_4848 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5560 = _T_5559 | _T_5305; // @[Mux.scala 27:72]
|
|
wire _T_4850 = btb_rd_addr_p1_f == 8'h38; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5306 = _T_4850 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5561 = _T_5560 | _T_5306; // @[Mux.scala 27:72]
|
|
wire _T_4852 = btb_rd_addr_p1_f == 8'h39; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5307 = _T_4852 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5562 = _T_5561 | _T_5307; // @[Mux.scala 27:72]
|
|
wire _T_4854 = btb_rd_addr_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5308 = _T_4854 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5563 = _T_5562 | _T_5308; // @[Mux.scala 27:72]
|
|
wire _T_4856 = btb_rd_addr_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5309 = _T_4856 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5564 = _T_5563 | _T_5309; // @[Mux.scala 27:72]
|
|
wire _T_4858 = btb_rd_addr_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5310 = _T_4858 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5565 = _T_5564 | _T_5310; // @[Mux.scala 27:72]
|
|
wire _T_4860 = btb_rd_addr_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5311 = _T_4860 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5566 = _T_5565 | _T_5311; // @[Mux.scala 27:72]
|
|
wire _T_4862 = btb_rd_addr_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5312 = _T_4862 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5567 = _T_5566 | _T_5312; // @[Mux.scala 27:72]
|
|
wire _T_4864 = btb_rd_addr_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5313 = _T_4864 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5568 = _T_5567 | _T_5313; // @[Mux.scala 27:72]
|
|
wire _T_4866 = btb_rd_addr_p1_f == 8'h40; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5314 = _T_4866 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5569 = _T_5568 | _T_5314; // @[Mux.scala 27:72]
|
|
wire _T_4868 = btb_rd_addr_p1_f == 8'h41; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5315 = _T_4868 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5570 = _T_5569 | _T_5315; // @[Mux.scala 27:72]
|
|
wire _T_4870 = btb_rd_addr_p1_f == 8'h42; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5316 = _T_4870 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5571 = _T_5570 | _T_5316; // @[Mux.scala 27:72]
|
|
wire _T_4872 = btb_rd_addr_p1_f == 8'h43; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5317 = _T_4872 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5572 = _T_5571 | _T_5317; // @[Mux.scala 27:72]
|
|
wire _T_4874 = btb_rd_addr_p1_f == 8'h44; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5318 = _T_4874 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5573 = _T_5572 | _T_5318; // @[Mux.scala 27:72]
|
|
wire _T_4876 = btb_rd_addr_p1_f == 8'h45; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5319 = _T_4876 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5574 = _T_5573 | _T_5319; // @[Mux.scala 27:72]
|
|
wire _T_4878 = btb_rd_addr_p1_f == 8'h46; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5320 = _T_4878 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5575 = _T_5574 | _T_5320; // @[Mux.scala 27:72]
|
|
wire _T_4880 = btb_rd_addr_p1_f == 8'h47; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5321 = _T_4880 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5576 = _T_5575 | _T_5321; // @[Mux.scala 27:72]
|
|
wire _T_4882 = btb_rd_addr_p1_f == 8'h48; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5322 = _T_4882 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5577 = _T_5576 | _T_5322; // @[Mux.scala 27:72]
|
|
wire _T_4884 = btb_rd_addr_p1_f == 8'h49; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5323 = _T_4884 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5578 = _T_5577 | _T_5323; // @[Mux.scala 27:72]
|
|
wire _T_4886 = btb_rd_addr_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5324 = _T_4886 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5579 = _T_5578 | _T_5324; // @[Mux.scala 27:72]
|
|
wire _T_4888 = btb_rd_addr_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5325 = _T_4888 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5580 = _T_5579 | _T_5325; // @[Mux.scala 27:72]
|
|
wire _T_4890 = btb_rd_addr_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5326 = _T_4890 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5581 = _T_5580 | _T_5326; // @[Mux.scala 27:72]
|
|
wire _T_4892 = btb_rd_addr_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5327 = _T_4892 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5582 = _T_5581 | _T_5327; // @[Mux.scala 27:72]
|
|
wire _T_4894 = btb_rd_addr_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5328 = _T_4894 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5583 = _T_5582 | _T_5328; // @[Mux.scala 27:72]
|
|
wire _T_4896 = btb_rd_addr_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5329 = _T_4896 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5584 = _T_5583 | _T_5329; // @[Mux.scala 27:72]
|
|
wire _T_4898 = btb_rd_addr_p1_f == 8'h50; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5330 = _T_4898 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5585 = _T_5584 | _T_5330; // @[Mux.scala 27:72]
|
|
wire _T_4900 = btb_rd_addr_p1_f == 8'h51; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5331 = _T_4900 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5586 = _T_5585 | _T_5331; // @[Mux.scala 27:72]
|
|
wire _T_4902 = btb_rd_addr_p1_f == 8'h52; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5332 = _T_4902 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5587 = _T_5586 | _T_5332; // @[Mux.scala 27:72]
|
|
wire _T_4904 = btb_rd_addr_p1_f == 8'h53; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5333 = _T_4904 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5588 = _T_5587 | _T_5333; // @[Mux.scala 27:72]
|
|
wire _T_4906 = btb_rd_addr_p1_f == 8'h54; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5334 = _T_4906 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5589 = _T_5588 | _T_5334; // @[Mux.scala 27:72]
|
|
wire _T_4908 = btb_rd_addr_p1_f == 8'h55; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5335 = _T_4908 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5590 = _T_5589 | _T_5335; // @[Mux.scala 27:72]
|
|
wire _T_4910 = btb_rd_addr_p1_f == 8'h56; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5336 = _T_4910 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5591 = _T_5590 | _T_5336; // @[Mux.scala 27:72]
|
|
wire _T_4912 = btb_rd_addr_p1_f == 8'h57; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5337 = _T_4912 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5592 = _T_5591 | _T_5337; // @[Mux.scala 27:72]
|
|
wire _T_4914 = btb_rd_addr_p1_f == 8'h58; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5338 = _T_4914 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5593 = _T_5592 | _T_5338; // @[Mux.scala 27:72]
|
|
wire _T_4916 = btb_rd_addr_p1_f == 8'h59; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5339 = _T_4916 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5594 = _T_5593 | _T_5339; // @[Mux.scala 27:72]
|
|
wire _T_4918 = btb_rd_addr_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5340 = _T_4918 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5595 = _T_5594 | _T_5340; // @[Mux.scala 27:72]
|
|
wire _T_4920 = btb_rd_addr_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5341 = _T_4920 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5596 = _T_5595 | _T_5341; // @[Mux.scala 27:72]
|
|
wire _T_4922 = btb_rd_addr_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5342 = _T_4922 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5597 = _T_5596 | _T_5342; // @[Mux.scala 27:72]
|
|
wire _T_4924 = btb_rd_addr_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5343 = _T_4924 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5598 = _T_5597 | _T_5343; // @[Mux.scala 27:72]
|
|
wire _T_4926 = btb_rd_addr_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5344 = _T_4926 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5599 = _T_5598 | _T_5344; // @[Mux.scala 27:72]
|
|
wire _T_4928 = btb_rd_addr_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5345 = _T_4928 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5600 = _T_5599 | _T_5345; // @[Mux.scala 27:72]
|
|
wire _T_4930 = btb_rd_addr_p1_f == 8'h60; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5346 = _T_4930 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5601 = _T_5600 | _T_5346; // @[Mux.scala 27:72]
|
|
wire _T_4932 = btb_rd_addr_p1_f == 8'h61; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5347 = _T_4932 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5602 = _T_5601 | _T_5347; // @[Mux.scala 27:72]
|
|
wire _T_4934 = btb_rd_addr_p1_f == 8'h62; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5348 = _T_4934 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5603 = _T_5602 | _T_5348; // @[Mux.scala 27:72]
|
|
wire _T_4936 = btb_rd_addr_p1_f == 8'h63; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5349 = _T_4936 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5604 = _T_5603 | _T_5349; // @[Mux.scala 27:72]
|
|
wire _T_4938 = btb_rd_addr_p1_f == 8'h64; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5350 = _T_4938 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5605 = _T_5604 | _T_5350; // @[Mux.scala 27:72]
|
|
wire _T_4940 = btb_rd_addr_p1_f == 8'h65; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5351 = _T_4940 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5606 = _T_5605 | _T_5351; // @[Mux.scala 27:72]
|
|
wire _T_4942 = btb_rd_addr_p1_f == 8'h66; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5352 = _T_4942 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5607 = _T_5606 | _T_5352; // @[Mux.scala 27:72]
|
|
wire _T_4944 = btb_rd_addr_p1_f == 8'h67; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5353 = _T_4944 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5608 = _T_5607 | _T_5353; // @[Mux.scala 27:72]
|
|
wire _T_4946 = btb_rd_addr_p1_f == 8'h68; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5354 = _T_4946 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5609 = _T_5608 | _T_5354; // @[Mux.scala 27:72]
|
|
wire _T_4948 = btb_rd_addr_p1_f == 8'h69; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5355 = _T_4948 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5610 = _T_5609 | _T_5355; // @[Mux.scala 27:72]
|
|
wire _T_4950 = btb_rd_addr_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5356 = _T_4950 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5611 = _T_5610 | _T_5356; // @[Mux.scala 27:72]
|
|
wire _T_4952 = btb_rd_addr_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5357 = _T_4952 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5612 = _T_5611 | _T_5357; // @[Mux.scala 27:72]
|
|
wire _T_4954 = btb_rd_addr_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5358 = _T_4954 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5613 = _T_5612 | _T_5358; // @[Mux.scala 27:72]
|
|
wire _T_4956 = btb_rd_addr_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5359 = _T_4956 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5614 = _T_5613 | _T_5359; // @[Mux.scala 27:72]
|
|
wire _T_4958 = btb_rd_addr_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5360 = _T_4958 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5615 = _T_5614 | _T_5360; // @[Mux.scala 27:72]
|
|
wire _T_4960 = btb_rd_addr_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5361 = _T_4960 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5616 = _T_5615 | _T_5361; // @[Mux.scala 27:72]
|
|
wire _T_4962 = btb_rd_addr_p1_f == 8'h70; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5362 = _T_4962 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5617 = _T_5616 | _T_5362; // @[Mux.scala 27:72]
|
|
wire _T_4964 = btb_rd_addr_p1_f == 8'h71; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5363 = _T_4964 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5618 = _T_5617 | _T_5363; // @[Mux.scala 27:72]
|
|
wire _T_4966 = btb_rd_addr_p1_f == 8'h72; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5364 = _T_4966 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5619 = _T_5618 | _T_5364; // @[Mux.scala 27:72]
|
|
wire _T_4968 = btb_rd_addr_p1_f == 8'h73; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5365 = _T_4968 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5620 = _T_5619 | _T_5365; // @[Mux.scala 27:72]
|
|
wire _T_4970 = btb_rd_addr_p1_f == 8'h74; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5366 = _T_4970 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5621 = _T_5620 | _T_5366; // @[Mux.scala 27:72]
|
|
wire _T_4972 = btb_rd_addr_p1_f == 8'h75; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5367 = _T_4972 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5622 = _T_5621 | _T_5367; // @[Mux.scala 27:72]
|
|
wire _T_4974 = btb_rd_addr_p1_f == 8'h76; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5368 = _T_4974 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5623 = _T_5622 | _T_5368; // @[Mux.scala 27:72]
|
|
wire _T_4976 = btb_rd_addr_p1_f == 8'h77; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5369 = _T_4976 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5624 = _T_5623 | _T_5369; // @[Mux.scala 27:72]
|
|
wire _T_4978 = btb_rd_addr_p1_f == 8'h78; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5370 = _T_4978 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5625 = _T_5624 | _T_5370; // @[Mux.scala 27:72]
|
|
wire _T_4980 = btb_rd_addr_p1_f == 8'h79; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5371 = _T_4980 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5626 = _T_5625 | _T_5371; // @[Mux.scala 27:72]
|
|
wire _T_4982 = btb_rd_addr_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5372 = _T_4982 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5627 = _T_5626 | _T_5372; // @[Mux.scala 27:72]
|
|
wire _T_4984 = btb_rd_addr_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5373 = _T_4984 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5628 = _T_5627 | _T_5373; // @[Mux.scala 27:72]
|
|
wire _T_4986 = btb_rd_addr_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5374 = _T_4986 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5629 = _T_5628 | _T_5374; // @[Mux.scala 27:72]
|
|
wire _T_4988 = btb_rd_addr_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5375 = _T_4988 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5630 = _T_5629 | _T_5375; // @[Mux.scala 27:72]
|
|
wire _T_4990 = btb_rd_addr_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5376 = _T_4990 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5631 = _T_5630 | _T_5376; // @[Mux.scala 27:72]
|
|
wire _T_4992 = btb_rd_addr_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5377 = _T_4992 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5632 = _T_5631 | _T_5377; // @[Mux.scala 27:72]
|
|
wire _T_4994 = btb_rd_addr_p1_f == 8'h80; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5378 = _T_4994 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5633 = _T_5632 | _T_5378; // @[Mux.scala 27:72]
|
|
wire _T_4996 = btb_rd_addr_p1_f == 8'h81; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5379 = _T_4996 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5634 = _T_5633 | _T_5379; // @[Mux.scala 27:72]
|
|
wire _T_4998 = btb_rd_addr_p1_f == 8'h82; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5380 = _T_4998 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5635 = _T_5634 | _T_5380; // @[Mux.scala 27:72]
|
|
wire _T_5000 = btb_rd_addr_p1_f == 8'h83; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5381 = _T_5000 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5636 = _T_5635 | _T_5381; // @[Mux.scala 27:72]
|
|
wire _T_5002 = btb_rd_addr_p1_f == 8'h84; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5382 = _T_5002 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5637 = _T_5636 | _T_5382; // @[Mux.scala 27:72]
|
|
wire _T_5004 = btb_rd_addr_p1_f == 8'h85; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5383 = _T_5004 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5638 = _T_5637 | _T_5383; // @[Mux.scala 27:72]
|
|
wire _T_5006 = btb_rd_addr_p1_f == 8'h86; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5384 = _T_5006 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5639 = _T_5638 | _T_5384; // @[Mux.scala 27:72]
|
|
wire _T_5008 = btb_rd_addr_p1_f == 8'h87; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5385 = _T_5008 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5640 = _T_5639 | _T_5385; // @[Mux.scala 27:72]
|
|
wire _T_5010 = btb_rd_addr_p1_f == 8'h88; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5386 = _T_5010 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5641 = _T_5640 | _T_5386; // @[Mux.scala 27:72]
|
|
wire _T_5012 = btb_rd_addr_p1_f == 8'h89; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5387 = _T_5012 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5642 = _T_5641 | _T_5387; // @[Mux.scala 27:72]
|
|
wire _T_5014 = btb_rd_addr_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5388 = _T_5014 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5643 = _T_5642 | _T_5388; // @[Mux.scala 27:72]
|
|
wire _T_5016 = btb_rd_addr_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5389 = _T_5016 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5644 = _T_5643 | _T_5389; // @[Mux.scala 27:72]
|
|
wire _T_5018 = btb_rd_addr_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5390 = _T_5018 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5645 = _T_5644 | _T_5390; // @[Mux.scala 27:72]
|
|
wire _T_5020 = btb_rd_addr_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5391 = _T_5020 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5646 = _T_5645 | _T_5391; // @[Mux.scala 27:72]
|
|
wire _T_5022 = btb_rd_addr_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5392 = _T_5022 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5647 = _T_5646 | _T_5392; // @[Mux.scala 27:72]
|
|
wire _T_5024 = btb_rd_addr_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5393 = _T_5024 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5648 = _T_5647 | _T_5393; // @[Mux.scala 27:72]
|
|
wire _T_5026 = btb_rd_addr_p1_f == 8'h90; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5394 = _T_5026 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5649 = _T_5648 | _T_5394; // @[Mux.scala 27:72]
|
|
wire _T_5028 = btb_rd_addr_p1_f == 8'h91; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5395 = _T_5028 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5650 = _T_5649 | _T_5395; // @[Mux.scala 27:72]
|
|
wire _T_5030 = btb_rd_addr_p1_f == 8'h92; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5396 = _T_5030 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5651 = _T_5650 | _T_5396; // @[Mux.scala 27:72]
|
|
wire _T_5032 = btb_rd_addr_p1_f == 8'h93; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5397 = _T_5032 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5652 = _T_5651 | _T_5397; // @[Mux.scala 27:72]
|
|
wire _T_5034 = btb_rd_addr_p1_f == 8'h94; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5398 = _T_5034 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5653 = _T_5652 | _T_5398; // @[Mux.scala 27:72]
|
|
wire _T_5036 = btb_rd_addr_p1_f == 8'h95; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5399 = _T_5036 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5654 = _T_5653 | _T_5399; // @[Mux.scala 27:72]
|
|
wire _T_5038 = btb_rd_addr_p1_f == 8'h96; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5400 = _T_5038 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5655 = _T_5654 | _T_5400; // @[Mux.scala 27:72]
|
|
wire _T_5040 = btb_rd_addr_p1_f == 8'h97; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5401 = _T_5040 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5656 = _T_5655 | _T_5401; // @[Mux.scala 27:72]
|
|
wire _T_5042 = btb_rd_addr_p1_f == 8'h98; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5402 = _T_5042 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5657 = _T_5656 | _T_5402; // @[Mux.scala 27:72]
|
|
wire _T_5044 = btb_rd_addr_p1_f == 8'h99; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5403 = _T_5044 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5658 = _T_5657 | _T_5403; // @[Mux.scala 27:72]
|
|
wire _T_5046 = btb_rd_addr_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5404 = _T_5046 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5659 = _T_5658 | _T_5404; // @[Mux.scala 27:72]
|
|
wire _T_5048 = btb_rd_addr_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5405 = _T_5048 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5660 = _T_5659 | _T_5405; // @[Mux.scala 27:72]
|
|
wire _T_5050 = btb_rd_addr_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5406 = _T_5050 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5661 = _T_5660 | _T_5406; // @[Mux.scala 27:72]
|
|
wire _T_5052 = btb_rd_addr_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5407 = _T_5052 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5662 = _T_5661 | _T_5407; // @[Mux.scala 27:72]
|
|
wire _T_5054 = btb_rd_addr_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5408 = _T_5054 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5663 = _T_5662 | _T_5408; // @[Mux.scala 27:72]
|
|
wire _T_5056 = btb_rd_addr_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5409 = _T_5056 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5664 = _T_5663 | _T_5409; // @[Mux.scala 27:72]
|
|
wire _T_5058 = btb_rd_addr_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5410 = _T_5058 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5665 = _T_5664 | _T_5410; // @[Mux.scala 27:72]
|
|
wire _T_5060 = btb_rd_addr_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5411 = _T_5060 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5666 = _T_5665 | _T_5411; // @[Mux.scala 27:72]
|
|
wire _T_5062 = btb_rd_addr_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5412 = _T_5062 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5667 = _T_5666 | _T_5412; // @[Mux.scala 27:72]
|
|
wire _T_5064 = btb_rd_addr_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5413 = _T_5064 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5668 = _T_5667 | _T_5413; // @[Mux.scala 27:72]
|
|
wire _T_5066 = btb_rd_addr_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5414 = _T_5066 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5669 = _T_5668 | _T_5414; // @[Mux.scala 27:72]
|
|
wire _T_5068 = btb_rd_addr_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5415 = _T_5068 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5670 = _T_5669 | _T_5415; // @[Mux.scala 27:72]
|
|
wire _T_5070 = btb_rd_addr_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5416 = _T_5070 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5671 = _T_5670 | _T_5416; // @[Mux.scala 27:72]
|
|
wire _T_5072 = btb_rd_addr_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5417 = _T_5072 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5672 = _T_5671 | _T_5417; // @[Mux.scala 27:72]
|
|
wire _T_5074 = btb_rd_addr_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5418 = _T_5074 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5673 = _T_5672 | _T_5418; // @[Mux.scala 27:72]
|
|
wire _T_5076 = btb_rd_addr_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5419 = _T_5076 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5674 = _T_5673 | _T_5419; // @[Mux.scala 27:72]
|
|
wire _T_5078 = btb_rd_addr_p1_f == 8'haa; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5420 = _T_5078 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5675 = _T_5674 | _T_5420; // @[Mux.scala 27:72]
|
|
wire _T_5080 = btb_rd_addr_p1_f == 8'hab; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5421 = _T_5080 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5676 = _T_5675 | _T_5421; // @[Mux.scala 27:72]
|
|
wire _T_5082 = btb_rd_addr_p1_f == 8'hac; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5422 = _T_5082 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5677 = _T_5676 | _T_5422; // @[Mux.scala 27:72]
|
|
wire _T_5084 = btb_rd_addr_p1_f == 8'had; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5423 = _T_5084 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5678 = _T_5677 | _T_5423; // @[Mux.scala 27:72]
|
|
wire _T_5086 = btb_rd_addr_p1_f == 8'hae; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5424 = _T_5086 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5679 = _T_5678 | _T_5424; // @[Mux.scala 27:72]
|
|
wire _T_5088 = btb_rd_addr_p1_f == 8'haf; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5425 = _T_5088 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5680 = _T_5679 | _T_5425; // @[Mux.scala 27:72]
|
|
wire _T_5090 = btb_rd_addr_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5426 = _T_5090 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5681 = _T_5680 | _T_5426; // @[Mux.scala 27:72]
|
|
wire _T_5092 = btb_rd_addr_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5427 = _T_5092 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5682 = _T_5681 | _T_5427; // @[Mux.scala 27:72]
|
|
wire _T_5094 = btb_rd_addr_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5428 = _T_5094 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5683 = _T_5682 | _T_5428; // @[Mux.scala 27:72]
|
|
wire _T_5096 = btb_rd_addr_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5429 = _T_5096 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5684 = _T_5683 | _T_5429; // @[Mux.scala 27:72]
|
|
wire _T_5098 = btb_rd_addr_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5430 = _T_5098 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5685 = _T_5684 | _T_5430; // @[Mux.scala 27:72]
|
|
wire _T_5100 = btb_rd_addr_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5431 = _T_5100 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5686 = _T_5685 | _T_5431; // @[Mux.scala 27:72]
|
|
wire _T_5102 = btb_rd_addr_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5432 = _T_5102 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5687 = _T_5686 | _T_5432; // @[Mux.scala 27:72]
|
|
wire _T_5104 = btb_rd_addr_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5433 = _T_5104 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5688 = _T_5687 | _T_5433; // @[Mux.scala 27:72]
|
|
wire _T_5106 = btb_rd_addr_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5434 = _T_5106 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5689 = _T_5688 | _T_5434; // @[Mux.scala 27:72]
|
|
wire _T_5108 = btb_rd_addr_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5435 = _T_5108 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5690 = _T_5689 | _T_5435; // @[Mux.scala 27:72]
|
|
wire _T_5110 = btb_rd_addr_p1_f == 8'hba; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5436 = _T_5110 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5691 = _T_5690 | _T_5436; // @[Mux.scala 27:72]
|
|
wire _T_5112 = btb_rd_addr_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5437 = _T_5112 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5692 = _T_5691 | _T_5437; // @[Mux.scala 27:72]
|
|
wire _T_5114 = btb_rd_addr_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5438 = _T_5114 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5693 = _T_5692 | _T_5438; // @[Mux.scala 27:72]
|
|
wire _T_5116 = btb_rd_addr_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5439 = _T_5116 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5694 = _T_5693 | _T_5439; // @[Mux.scala 27:72]
|
|
wire _T_5118 = btb_rd_addr_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5440 = _T_5118 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5695 = _T_5694 | _T_5440; // @[Mux.scala 27:72]
|
|
wire _T_5120 = btb_rd_addr_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5441 = _T_5120 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5696 = _T_5695 | _T_5441; // @[Mux.scala 27:72]
|
|
wire _T_5122 = btb_rd_addr_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5442 = _T_5122 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5697 = _T_5696 | _T_5442; // @[Mux.scala 27:72]
|
|
wire _T_5124 = btb_rd_addr_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5443 = _T_5124 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5698 = _T_5697 | _T_5443; // @[Mux.scala 27:72]
|
|
wire _T_5126 = btb_rd_addr_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5444 = _T_5126 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5699 = _T_5698 | _T_5444; // @[Mux.scala 27:72]
|
|
wire _T_5128 = btb_rd_addr_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5445 = _T_5128 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5700 = _T_5699 | _T_5445; // @[Mux.scala 27:72]
|
|
wire _T_5130 = btb_rd_addr_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5446 = _T_5130 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5701 = _T_5700 | _T_5446; // @[Mux.scala 27:72]
|
|
wire _T_5132 = btb_rd_addr_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5447 = _T_5132 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5702 = _T_5701 | _T_5447; // @[Mux.scala 27:72]
|
|
wire _T_5134 = btb_rd_addr_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5448 = _T_5134 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5703 = _T_5702 | _T_5448; // @[Mux.scala 27:72]
|
|
wire _T_5136 = btb_rd_addr_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5449 = _T_5136 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5704 = _T_5703 | _T_5449; // @[Mux.scala 27:72]
|
|
wire _T_5138 = btb_rd_addr_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5450 = _T_5138 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5705 = _T_5704 | _T_5450; // @[Mux.scala 27:72]
|
|
wire _T_5140 = btb_rd_addr_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5451 = _T_5140 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5706 = _T_5705 | _T_5451; // @[Mux.scala 27:72]
|
|
wire _T_5142 = btb_rd_addr_p1_f == 8'hca; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5452 = _T_5142 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5707 = _T_5706 | _T_5452; // @[Mux.scala 27:72]
|
|
wire _T_5144 = btb_rd_addr_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5453 = _T_5144 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5708 = _T_5707 | _T_5453; // @[Mux.scala 27:72]
|
|
wire _T_5146 = btb_rd_addr_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5454 = _T_5146 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5709 = _T_5708 | _T_5454; // @[Mux.scala 27:72]
|
|
wire _T_5148 = btb_rd_addr_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5455 = _T_5148 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5710 = _T_5709 | _T_5455; // @[Mux.scala 27:72]
|
|
wire _T_5150 = btb_rd_addr_p1_f == 8'hce; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5456 = _T_5150 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5711 = _T_5710 | _T_5456; // @[Mux.scala 27:72]
|
|
wire _T_5152 = btb_rd_addr_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5457 = _T_5152 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5712 = _T_5711 | _T_5457; // @[Mux.scala 27:72]
|
|
wire _T_5154 = btb_rd_addr_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5458 = _T_5154 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5713 = _T_5712 | _T_5458; // @[Mux.scala 27:72]
|
|
wire _T_5156 = btb_rd_addr_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5459 = _T_5156 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5714 = _T_5713 | _T_5459; // @[Mux.scala 27:72]
|
|
wire _T_5158 = btb_rd_addr_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5460 = _T_5158 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5715 = _T_5714 | _T_5460; // @[Mux.scala 27:72]
|
|
wire _T_5160 = btb_rd_addr_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5461 = _T_5160 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5716 = _T_5715 | _T_5461; // @[Mux.scala 27:72]
|
|
wire _T_5162 = btb_rd_addr_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5462 = _T_5162 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5717 = _T_5716 | _T_5462; // @[Mux.scala 27:72]
|
|
wire _T_5164 = btb_rd_addr_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5463 = _T_5164 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5718 = _T_5717 | _T_5463; // @[Mux.scala 27:72]
|
|
wire _T_5166 = btb_rd_addr_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5464 = _T_5166 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5719 = _T_5718 | _T_5464; // @[Mux.scala 27:72]
|
|
wire _T_5168 = btb_rd_addr_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5465 = _T_5168 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5720 = _T_5719 | _T_5465; // @[Mux.scala 27:72]
|
|
wire _T_5170 = btb_rd_addr_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5466 = _T_5170 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5721 = _T_5720 | _T_5466; // @[Mux.scala 27:72]
|
|
wire _T_5172 = btb_rd_addr_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5467 = _T_5172 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5722 = _T_5721 | _T_5467; // @[Mux.scala 27:72]
|
|
wire _T_5174 = btb_rd_addr_p1_f == 8'hda; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5468 = _T_5174 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5723 = _T_5722 | _T_5468; // @[Mux.scala 27:72]
|
|
wire _T_5176 = btb_rd_addr_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5469 = _T_5176 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5724 = _T_5723 | _T_5469; // @[Mux.scala 27:72]
|
|
wire _T_5178 = btb_rd_addr_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5470 = _T_5178 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5725 = _T_5724 | _T_5470; // @[Mux.scala 27:72]
|
|
wire _T_5180 = btb_rd_addr_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5471 = _T_5180 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5726 = _T_5725 | _T_5471; // @[Mux.scala 27:72]
|
|
wire _T_5182 = btb_rd_addr_p1_f == 8'hde; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5472 = _T_5182 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5727 = _T_5726 | _T_5472; // @[Mux.scala 27:72]
|
|
wire _T_5184 = btb_rd_addr_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5473 = _T_5184 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5728 = _T_5727 | _T_5473; // @[Mux.scala 27:72]
|
|
wire _T_5186 = btb_rd_addr_p1_f == 8'he0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5474 = _T_5186 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5729 = _T_5728 | _T_5474; // @[Mux.scala 27:72]
|
|
wire _T_5188 = btb_rd_addr_p1_f == 8'he1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5475 = _T_5188 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5730 = _T_5729 | _T_5475; // @[Mux.scala 27:72]
|
|
wire _T_5190 = btb_rd_addr_p1_f == 8'he2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5476 = _T_5190 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5731 = _T_5730 | _T_5476; // @[Mux.scala 27:72]
|
|
wire _T_5192 = btb_rd_addr_p1_f == 8'he3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5477 = _T_5192 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5732 = _T_5731 | _T_5477; // @[Mux.scala 27:72]
|
|
wire _T_5194 = btb_rd_addr_p1_f == 8'he4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5478 = _T_5194 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5733 = _T_5732 | _T_5478; // @[Mux.scala 27:72]
|
|
wire _T_5196 = btb_rd_addr_p1_f == 8'he5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5479 = _T_5196 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5734 = _T_5733 | _T_5479; // @[Mux.scala 27:72]
|
|
wire _T_5198 = btb_rd_addr_p1_f == 8'he6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5480 = _T_5198 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5735 = _T_5734 | _T_5480; // @[Mux.scala 27:72]
|
|
wire _T_5200 = btb_rd_addr_p1_f == 8'he7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5481 = _T_5200 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5736 = _T_5735 | _T_5481; // @[Mux.scala 27:72]
|
|
wire _T_5202 = btb_rd_addr_p1_f == 8'he8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5482 = _T_5202 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5737 = _T_5736 | _T_5482; // @[Mux.scala 27:72]
|
|
wire _T_5204 = btb_rd_addr_p1_f == 8'he9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5483 = _T_5204 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5738 = _T_5737 | _T_5483; // @[Mux.scala 27:72]
|
|
wire _T_5206 = btb_rd_addr_p1_f == 8'hea; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5484 = _T_5206 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5739 = _T_5738 | _T_5484; // @[Mux.scala 27:72]
|
|
wire _T_5208 = btb_rd_addr_p1_f == 8'heb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5485 = _T_5208 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5740 = _T_5739 | _T_5485; // @[Mux.scala 27:72]
|
|
wire _T_5210 = btb_rd_addr_p1_f == 8'hec; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5486 = _T_5210 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5741 = _T_5740 | _T_5486; // @[Mux.scala 27:72]
|
|
wire _T_5212 = btb_rd_addr_p1_f == 8'hed; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5487 = _T_5212 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5742 = _T_5741 | _T_5487; // @[Mux.scala 27:72]
|
|
wire _T_5214 = btb_rd_addr_p1_f == 8'hee; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5488 = _T_5214 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5743 = _T_5742 | _T_5488; // @[Mux.scala 27:72]
|
|
wire _T_5216 = btb_rd_addr_p1_f == 8'hef; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5489 = _T_5216 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5744 = _T_5743 | _T_5489; // @[Mux.scala 27:72]
|
|
wire _T_5218 = btb_rd_addr_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5490 = _T_5218 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5745 = _T_5744 | _T_5490; // @[Mux.scala 27:72]
|
|
wire _T_5220 = btb_rd_addr_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5491 = _T_5220 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5746 = _T_5745 | _T_5491; // @[Mux.scala 27:72]
|
|
wire _T_5222 = btb_rd_addr_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5492 = _T_5222 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5747 = _T_5746 | _T_5492; // @[Mux.scala 27:72]
|
|
wire _T_5224 = btb_rd_addr_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5493 = _T_5224 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5748 = _T_5747 | _T_5493; // @[Mux.scala 27:72]
|
|
wire _T_5226 = btb_rd_addr_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5494 = _T_5226 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5749 = _T_5748 | _T_5494; // @[Mux.scala 27:72]
|
|
wire _T_5228 = btb_rd_addr_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5495 = _T_5228 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5750 = _T_5749 | _T_5495; // @[Mux.scala 27:72]
|
|
wire _T_5230 = btb_rd_addr_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5496 = _T_5230 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5751 = _T_5750 | _T_5496; // @[Mux.scala 27:72]
|
|
wire _T_5232 = btb_rd_addr_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5497 = _T_5232 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5752 = _T_5751 | _T_5497; // @[Mux.scala 27:72]
|
|
wire _T_5234 = btb_rd_addr_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5498 = _T_5234 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5753 = _T_5752 | _T_5498; // @[Mux.scala 27:72]
|
|
wire _T_5236 = btb_rd_addr_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5499 = _T_5236 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5754 = _T_5753 | _T_5499; // @[Mux.scala 27:72]
|
|
wire _T_5238 = btb_rd_addr_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5500 = _T_5238 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5755 = _T_5754 | _T_5500; // @[Mux.scala 27:72]
|
|
wire _T_5240 = btb_rd_addr_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5501 = _T_5240 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5756 = _T_5755 | _T_5501; // @[Mux.scala 27:72]
|
|
wire _T_5242 = btb_rd_addr_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5502 = _T_5242 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_5757 = _T_5756 | _T_5502; // @[Mux.scala 27:72]
|
|
wire _T_5244 = btb_rd_addr_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5503 = _T_5244 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5758 = _T_5757 | _T_5503; // @[Mux.scala 27:72]
|
|
wire _T_5246 = btb_rd_addr_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5504 = _T_5246 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_5759 = _T_5758 | _T_5504; // @[Mux.scala 27:72]
|
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wire _T_5248 = btb_rd_addr_p1_f == 8'hff; // @[ifu_bp_ctl.scala 438:88]
|
|
wire [21:0] _T_5505 = _T_5248 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5759 | _T_5505; // @[Mux.scala 27:72]
|
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wire [4:0] _T_36 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 48:111]
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wire [4:0] _T_37 = _T_36 ^ _T_8[23:19]; // @[lib.scala 48:111]
|
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wire _T_70 = btb_bank0_rd_data_way0_p1_f[21:17] == _T_37; // @[ifu_bp_ctl.scala 151:109]
|
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wire _T_71 = btb_bank0_rd_data_way0_p1_f[0] & _T_70; // @[ifu_bp_ctl.scala 151:63]
|
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wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 125:75]
|
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wire branch_error_collision_p1_f = dec_tlu_error_wb & _T_20; // @[ifu_bp_ctl.scala 125:54]
|
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wire branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 129:69]
|
|
wire _T_72 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_p1_f; // @[ifu_bp_ctl.scala 152:24]
|
|
wire _T_73 = ~_T_72; // @[ifu_bp_ctl.scala 152:7]
|
|
wire _T_74 = _T_71 & _T_73; // @[ifu_bp_ctl.scala 151:132]
|
|
wire _T_75 = _T_74 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 152:59]
|
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wire _T_77 = _T_75 & _T; // @[ifu_bp_ctl.scala 152:80]
|
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wire _T_110 = btb_bank0_rd_data_way0_p1_f[3] ^ btb_bank0_rd_data_way0_p1_f[4]; // @[ifu_bp_ctl.scala 164:101]
|
|
wire _T_111 = _T_77 & _T_110; // @[ifu_bp_ctl.scala 164:64]
|
|
wire _T_115 = ~_T_110; // @[ifu_bp_ctl.scala 165:29]
|
|
wire _T_116 = _T_77 & _T_115; // @[ifu_bp_ctl.scala 165:27]
|
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wire [1:0] _T_117 = {_T_111,_T_116}; // @[Cat.scala 29:58]
|
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wire [21:0] _T_150 = _T_117[0] ? btb_bank0_rd_data_way0_p1_f : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_6274 = _T_4738 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_6275 = _T_4740 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72]
|
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wire [21:0] _T_6530 = _T_6274 | _T_6275; // @[Mux.scala 27:72]
|
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wire [21:0] _T_6276 = _T_4742 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6531 = _T_6530 | _T_6276; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6277 = _T_4744 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6532 = _T_6531 | _T_6277; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6278 = _T_4746 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6533 = _T_6532 | _T_6278; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6279 = _T_4748 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6534 = _T_6533 | _T_6279; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6280 = _T_4750 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6535 = _T_6534 | _T_6280; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6281 = _T_4752 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6536 = _T_6535 | _T_6281; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6282 = _T_4754 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6537 = _T_6536 | _T_6282; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6283 = _T_4756 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6538 = _T_6537 | _T_6283; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6284 = _T_4758 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6539 = _T_6538 | _T_6284; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6285 = _T_4760 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6540 = _T_6539 | _T_6285; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6286 = _T_4762 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6541 = _T_6540 | _T_6286; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6287 = _T_4764 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6542 = _T_6541 | _T_6287; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6288 = _T_4766 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6543 = _T_6542 | _T_6288; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6289 = _T_4768 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6544 = _T_6543 | _T_6289; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6290 = _T_4770 ? btb_bank0_rd_data_way1_out_16 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6545 = _T_6544 | _T_6290; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6291 = _T_4772 ? btb_bank0_rd_data_way1_out_17 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6546 = _T_6545 | _T_6291; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6292 = _T_4774 ? btb_bank0_rd_data_way1_out_18 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6547 = _T_6546 | _T_6292; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6293 = _T_4776 ? btb_bank0_rd_data_way1_out_19 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6548 = _T_6547 | _T_6293; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6294 = _T_4778 ? btb_bank0_rd_data_way1_out_20 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6549 = _T_6548 | _T_6294; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6295 = _T_4780 ? btb_bank0_rd_data_way1_out_21 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6550 = _T_6549 | _T_6295; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6296 = _T_4782 ? btb_bank0_rd_data_way1_out_22 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6551 = _T_6550 | _T_6296; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6297 = _T_4784 ? btb_bank0_rd_data_way1_out_23 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6552 = _T_6551 | _T_6297; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6298 = _T_4786 ? btb_bank0_rd_data_way1_out_24 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6553 = _T_6552 | _T_6298; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6299 = _T_4788 ? btb_bank0_rd_data_way1_out_25 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6554 = _T_6553 | _T_6299; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6300 = _T_4790 ? btb_bank0_rd_data_way1_out_26 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6555 = _T_6554 | _T_6300; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6301 = _T_4792 ? btb_bank0_rd_data_way1_out_27 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6556 = _T_6555 | _T_6301; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6302 = _T_4794 ? btb_bank0_rd_data_way1_out_28 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6557 = _T_6556 | _T_6302; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6303 = _T_4796 ? btb_bank0_rd_data_way1_out_29 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6558 = _T_6557 | _T_6303; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6304 = _T_4798 ? btb_bank0_rd_data_way1_out_30 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6559 = _T_6558 | _T_6304; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6305 = _T_4800 ? btb_bank0_rd_data_way1_out_31 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6560 = _T_6559 | _T_6305; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6306 = _T_4802 ? btb_bank0_rd_data_way1_out_32 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6561 = _T_6560 | _T_6306; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6307 = _T_4804 ? btb_bank0_rd_data_way1_out_33 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6562 = _T_6561 | _T_6307; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6308 = _T_4806 ? btb_bank0_rd_data_way1_out_34 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6563 = _T_6562 | _T_6308; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6309 = _T_4808 ? btb_bank0_rd_data_way1_out_35 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6564 = _T_6563 | _T_6309; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6310 = _T_4810 ? btb_bank0_rd_data_way1_out_36 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6565 = _T_6564 | _T_6310; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6311 = _T_4812 ? btb_bank0_rd_data_way1_out_37 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6566 = _T_6565 | _T_6311; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6312 = _T_4814 ? btb_bank0_rd_data_way1_out_38 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6567 = _T_6566 | _T_6312; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6313 = _T_4816 ? btb_bank0_rd_data_way1_out_39 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6568 = _T_6567 | _T_6313; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6314 = _T_4818 ? btb_bank0_rd_data_way1_out_40 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6569 = _T_6568 | _T_6314; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6315 = _T_4820 ? btb_bank0_rd_data_way1_out_41 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6570 = _T_6569 | _T_6315; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6316 = _T_4822 ? btb_bank0_rd_data_way1_out_42 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6571 = _T_6570 | _T_6316; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6317 = _T_4824 ? btb_bank0_rd_data_way1_out_43 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6572 = _T_6571 | _T_6317; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6318 = _T_4826 ? btb_bank0_rd_data_way1_out_44 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6573 = _T_6572 | _T_6318; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6319 = _T_4828 ? btb_bank0_rd_data_way1_out_45 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6574 = _T_6573 | _T_6319; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6320 = _T_4830 ? btb_bank0_rd_data_way1_out_46 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6575 = _T_6574 | _T_6320; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6321 = _T_4832 ? btb_bank0_rd_data_way1_out_47 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6576 = _T_6575 | _T_6321; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6322 = _T_4834 ? btb_bank0_rd_data_way1_out_48 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6577 = _T_6576 | _T_6322; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6323 = _T_4836 ? btb_bank0_rd_data_way1_out_49 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6578 = _T_6577 | _T_6323; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6324 = _T_4838 ? btb_bank0_rd_data_way1_out_50 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6579 = _T_6578 | _T_6324; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6325 = _T_4840 ? btb_bank0_rd_data_way1_out_51 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6580 = _T_6579 | _T_6325; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6326 = _T_4842 ? btb_bank0_rd_data_way1_out_52 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6581 = _T_6580 | _T_6326; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6327 = _T_4844 ? btb_bank0_rd_data_way1_out_53 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6582 = _T_6581 | _T_6327; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6328 = _T_4846 ? btb_bank0_rd_data_way1_out_54 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6583 = _T_6582 | _T_6328; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6329 = _T_4848 ? btb_bank0_rd_data_way1_out_55 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6584 = _T_6583 | _T_6329; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6330 = _T_4850 ? btb_bank0_rd_data_way1_out_56 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6585 = _T_6584 | _T_6330; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6331 = _T_4852 ? btb_bank0_rd_data_way1_out_57 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6586 = _T_6585 | _T_6331; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6332 = _T_4854 ? btb_bank0_rd_data_way1_out_58 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6587 = _T_6586 | _T_6332; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6333 = _T_4856 ? btb_bank0_rd_data_way1_out_59 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6588 = _T_6587 | _T_6333; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6334 = _T_4858 ? btb_bank0_rd_data_way1_out_60 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6589 = _T_6588 | _T_6334; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6335 = _T_4860 ? btb_bank0_rd_data_way1_out_61 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6590 = _T_6589 | _T_6335; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6336 = _T_4862 ? btb_bank0_rd_data_way1_out_62 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6591 = _T_6590 | _T_6336; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6337 = _T_4864 ? btb_bank0_rd_data_way1_out_63 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6592 = _T_6591 | _T_6337; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6338 = _T_4866 ? btb_bank0_rd_data_way1_out_64 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6593 = _T_6592 | _T_6338; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6339 = _T_4868 ? btb_bank0_rd_data_way1_out_65 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6594 = _T_6593 | _T_6339; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6340 = _T_4870 ? btb_bank0_rd_data_way1_out_66 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6595 = _T_6594 | _T_6340; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6341 = _T_4872 ? btb_bank0_rd_data_way1_out_67 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6596 = _T_6595 | _T_6341; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6342 = _T_4874 ? btb_bank0_rd_data_way1_out_68 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6597 = _T_6596 | _T_6342; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6343 = _T_4876 ? btb_bank0_rd_data_way1_out_69 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6598 = _T_6597 | _T_6343; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6344 = _T_4878 ? btb_bank0_rd_data_way1_out_70 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6599 = _T_6598 | _T_6344; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6345 = _T_4880 ? btb_bank0_rd_data_way1_out_71 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6600 = _T_6599 | _T_6345; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6346 = _T_4882 ? btb_bank0_rd_data_way1_out_72 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6601 = _T_6600 | _T_6346; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6347 = _T_4884 ? btb_bank0_rd_data_way1_out_73 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6602 = _T_6601 | _T_6347; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6348 = _T_4886 ? btb_bank0_rd_data_way1_out_74 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6603 = _T_6602 | _T_6348; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6349 = _T_4888 ? btb_bank0_rd_data_way1_out_75 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6604 = _T_6603 | _T_6349; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6350 = _T_4890 ? btb_bank0_rd_data_way1_out_76 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6605 = _T_6604 | _T_6350; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6351 = _T_4892 ? btb_bank0_rd_data_way1_out_77 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6606 = _T_6605 | _T_6351; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6352 = _T_4894 ? btb_bank0_rd_data_way1_out_78 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6607 = _T_6606 | _T_6352; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6353 = _T_4896 ? btb_bank0_rd_data_way1_out_79 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6608 = _T_6607 | _T_6353; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6354 = _T_4898 ? btb_bank0_rd_data_way1_out_80 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6609 = _T_6608 | _T_6354; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6355 = _T_4900 ? btb_bank0_rd_data_way1_out_81 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6610 = _T_6609 | _T_6355; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6356 = _T_4902 ? btb_bank0_rd_data_way1_out_82 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6611 = _T_6610 | _T_6356; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6357 = _T_4904 ? btb_bank0_rd_data_way1_out_83 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6612 = _T_6611 | _T_6357; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6358 = _T_4906 ? btb_bank0_rd_data_way1_out_84 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6613 = _T_6612 | _T_6358; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6359 = _T_4908 ? btb_bank0_rd_data_way1_out_85 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6614 = _T_6613 | _T_6359; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6360 = _T_4910 ? btb_bank0_rd_data_way1_out_86 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6615 = _T_6614 | _T_6360; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6361 = _T_4912 ? btb_bank0_rd_data_way1_out_87 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6616 = _T_6615 | _T_6361; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6362 = _T_4914 ? btb_bank0_rd_data_way1_out_88 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6617 = _T_6616 | _T_6362; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6363 = _T_4916 ? btb_bank0_rd_data_way1_out_89 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6618 = _T_6617 | _T_6363; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6364 = _T_4918 ? btb_bank0_rd_data_way1_out_90 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6619 = _T_6618 | _T_6364; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6365 = _T_4920 ? btb_bank0_rd_data_way1_out_91 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6620 = _T_6619 | _T_6365; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6366 = _T_4922 ? btb_bank0_rd_data_way1_out_92 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6621 = _T_6620 | _T_6366; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6367 = _T_4924 ? btb_bank0_rd_data_way1_out_93 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6622 = _T_6621 | _T_6367; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6368 = _T_4926 ? btb_bank0_rd_data_way1_out_94 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6623 = _T_6622 | _T_6368; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6369 = _T_4928 ? btb_bank0_rd_data_way1_out_95 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6624 = _T_6623 | _T_6369; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6370 = _T_4930 ? btb_bank0_rd_data_way1_out_96 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6625 = _T_6624 | _T_6370; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6371 = _T_4932 ? btb_bank0_rd_data_way1_out_97 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6626 = _T_6625 | _T_6371; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6372 = _T_4934 ? btb_bank0_rd_data_way1_out_98 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6627 = _T_6626 | _T_6372; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6373 = _T_4936 ? btb_bank0_rd_data_way1_out_99 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6628 = _T_6627 | _T_6373; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6374 = _T_4938 ? btb_bank0_rd_data_way1_out_100 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6629 = _T_6628 | _T_6374; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6375 = _T_4940 ? btb_bank0_rd_data_way1_out_101 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6630 = _T_6629 | _T_6375; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6376 = _T_4942 ? btb_bank0_rd_data_way1_out_102 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6631 = _T_6630 | _T_6376; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6377 = _T_4944 ? btb_bank0_rd_data_way1_out_103 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6632 = _T_6631 | _T_6377; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6378 = _T_4946 ? btb_bank0_rd_data_way1_out_104 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6633 = _T_6632 | _T_6378; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6379 = _T_4948 ? btb_bank0_rd_data_way1_out_105 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6634 = _T_6633 | _T_6379; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6380 = _T_4950 ? btb_bank0_rd_data_way1_out_106 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6635 = _T_6634 | _T_6380; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6381 = _T_4952 ? btb_bank0_rd_data_way1_out_107 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6636 = _T_6635 | _T_6381; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6382 = _T_4954 ? btb_bank0_rd_data_way1_out_108 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6637 = _T_6636 | _T_6382; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6383 = _T_4956 ? btb_bank0_rd_data_way1_out_109 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6638 = _T_6637 | _T_6383; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6384 = _T_4958 ? btb_bank0_rd_data_way1_out_110 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6639 = _T_6638 | _T_6384; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6385 = _T_4960 ? btb_bank0_rd_data_way1_out_111 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6640 = _T_6639 | _T_6385; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6386 = _T_4962 ? btb_bank0_rd_data_way1_out_112 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6641 = _T_6640 | _T_6386; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6387 = _T_4964 ? btb_bank0_rd_data_way1_out_113 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6642 = _T_6641 | _T_6387; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6388 = _T_4966 ? btb_bank0_rd_data_way1_out_114 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6643 = _T_6642 | _T_6388; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6389 = _T_4968 ? btb_bank0_rd_data_way1_out_115 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6644 = _T_6643 | _T_6389; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6390 = _T_4970 ? btb_bank0_rd_data_way1_out_116 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6645 = _T_6644 | _T_6390; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6391 = _T_4972 ? btb_bank0_rd_data_way1_out_117 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6646 = _T_6645 | _T_6391; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6392 = _T_4974 ? btb_bank0_rd_data_way1_out_118 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6647 = _T_6646 | _T_6392; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6393 = _T_4976 ? btb_bank0_rd_data_way1_out_119 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6648 = _T_6647 | _T_6393; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6394 = _T_4978 ? btb_bank0_rd_data_way1_out_120 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6649 = _T_6648 | _T_6394; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6395 = _T_4980 ? btb_bank0_rd_data_way1_out_121 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6650 = _T_6649 | _T_6395; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6396 = _T_4982 ? btb_bank0_rd_data_way1_out_122 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6651 = _T_6650 | _T_6396; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6397 = _T_4984 ? btb_bank0_rd_data_way1_out_123 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6652 = _T_6651 | _T_6397; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6398 = _T_4986 ? btb_bank0_rd_data_way1_out_124 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6653 = _T_6652 | _T_6398; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6399 = _T_4988 ? btb_bank0_rd_data_way1_out_125 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6654 = _T_6653 | _T_6399; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6400 = _T_4990 ? btb_bank0_rd_data_way1_out_126 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6655 = _T_6654 | _T_6400; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6401 = _T_4992 ? btb_bank0_rd_data_way1_out_127 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6656 = _T_6655 | _T_6401; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6402 = _T_4994 ? btb_bank0_rd_data_way1_out_128 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6657 = _T_6656 | _T_6402; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6403 = _T_4996 ? btb_bank0_rd_data_way1_out_129 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6658 = _T_6657 | _T_6403; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6404 = _T_4998 ? btb_bank0_rd_data_way1_out_130 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6659 = _T_6658 | _T_6404; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6405 = _T_5000 ? btb_bank0_rd_data_way1_out_131 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6660 = _T_6659 | _T_6405; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6406 = _T_5002 ? btb_bank0_rd_data_way1_out_132 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6661 = _T_6660 | _T_6406; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6407 = _T_5004 ? btb_bank0_rd_data_way1_out_133 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6662 = _T_6661 | _T_6407; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6408 = _T_5006 ? btb_bank0_rd_data_way1_out_134 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6663 = _T_6662 | _T_6408; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6409 = _T_5008 ? btb_bank0_rd_data_way1_out_135 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6664 = _T_6663 | _T_6409; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6410 = _T_5010 ? btb_bank0_rd_data_way1_out_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6665 = _T_6664 | _T_6410; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6411 = _T_5012 ? btb_bank0_rd_data_way1_out_137 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6666 = _T_6665 | _T_6411; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6412 = _T_5014 ? btb_bank0_rd_data_way1_out_138 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6667 = _T_6666 | _T_6412; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6413 = _T_5016 ? btb_bank0_rd_data_way1_out_139 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6668 = _T_6667 | _T_6413; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6414 = _T_5018 ? btb_bank0_rd_data_way1_out_140 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6669 = _T_6668 | _T_6414; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6415 = _T_5020 ? btb_bank0_rd_data_way1_out_141 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6670 = _T_6669 | _T_6415; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6416 = _T_5022 ? btb_bank0_rd_data_way1_out_142 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6671 = _T_6670 | _T_6416; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6417 = _T_5024 ? btb_bank0_rd_data_way1_out_143 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6672 = _T_6671 | _T_6417; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6418 = _T_5026 ? btb_bank0_rd_data_way1_out_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6673 = _T_6672 | _T_6418; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6419 = _T_5028 ? btb_bank0_rd_data_way1_out_145 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6674 = _T_6673 | _T_6419; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6420 = _T_5030 ? btb_bank0_rd_data_way1_out_146 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6675 = _T_6674 | _T_6420; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6421 = _T_5032 ? btb_bank0_rd_data_way1_out_147 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6676 = _T_6675 | _T_6421; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6422 = _T_5034 ? btb_bank0_rd_data_way1_out_148 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6677 = _T_6676 | _T_6422; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6423 = _T_5036 ? btb_bank0_rd_data_way1_out_149 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6678 = _T_6677 | _T_6423; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6424 = _T_5038 ? btb_bank0_rd_data_way1_out_150 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6679 = _T_6678 | _T_6424; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6425 = _T_5040 ? btb_bank0_rd_data_way1_out_151 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6680 = _T_6679 | _T_6425; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6426 = _T_5042 ? btb_bank0_rd_data_way1_out_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6681 = _T_6680 | _T_6426; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6427 = _T_5044 ? btb_bank0_rd_data_way1_out_153 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6682 = _T_6681 | _T_6427; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6428 = _T_5046 ? btb_bank0_rd_data_way1_out_154 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6683 = _T_6682 | _T_6428; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6429 = _T_5048 ? btb_bank0_rd_data_way1_out_155 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6684 = _T_6683 | _T_6429; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6430 = _T_5050 ? btb_bank0_rd_data_way1_out_156 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6685 = _T_6684 | _T_6430; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6431 = _T_5052 ? btb_bank0_rd_data_way1_out_157 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6686 = _T_6685 | _T_6431; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6432 = _T_5054 ? btb_bank0_rd_data_way1_out_158 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6687 = _T_6686 | _T_6432; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6433 = _T_5056 ? btb_bank0_rd_data_way1_out_159 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6688 = _T_6687 | _T_6433; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6434 = _T_5058 ? btb_bank0_rd_data_way1_out_160 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6689 = _T_6688 | _T_6434; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6435 = _T_5060 ? btb_bank0_rd_data_way1_out_161 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6690 = _T_6689 | _T_6435; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6436 = _T_5062 ? btb_bank0_rd_data_way1_out_162 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6691 = _T_6690 | _T_6436; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6437 = _T_5064 ? btb_bank0_rd_data_way1_out_163 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6692 = _T_6691 | _T_6437; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6438 = _T_5066 ? btb_bank0_rd_data_way1_out_164 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6693 = _T_6692 | _T_6438; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6439 = _T_5068 ? btb_bank0_rd_data_way1_out_165 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6694 = _T_6693 | _T_6439; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6440 = _T_5070 ? btb_bank0_rd_data_way1_out_166 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6695 = _T_6694 | _T_6440; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6441 = _T_5072 ? btb_bank0_rd_data_way1_out_167 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6696 = _T_6695 | _T_6441; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6442 = _T_5074 ? btb_bank0_rd_data_way1_out_168 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6697 = _T_6696 | _T_6442; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6443 = _T_5076 ? btb_bank0_rd_data_way1_out_169 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6698 = _T_6697 | _T_6443; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6444 = _T_5078 ? btb_bank0_rd_data_way1_out_170 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6699 = _T_6698 | _T_6444; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6445 = _T_5080 ? btb_bank0_rd_data_way1_out_171 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6700 = _T_6699 | _T_6445; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6446 = _T_5082 ? btb_bank0_rd_data_way1_out_172 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6701 = _T_6700 | _T_6446; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6447 = _T_5084 ? btb_bank0_rd_data_way1_out_173 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6702 = _T_6701 | _T_6447; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6448 = _T_5086 ? btb_bank0_rd_data_way1_out_174 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6703 = _T_6702 | _T_6448; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6449 = _T_5088 ? btb_bank0_rd_data_way1_out_175 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6704 = _T_6703 | _T_6449; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6450 = _T_5090 ? btb_bank0_rd_data_way1_out_176 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6705 = _T_6704 | _T_6450; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6451 = _T_5092 ? btb_bank0_rd_data_way1_out_177 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6706 = _T_6705 | _T_6451; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6452 = _T_5094 ? btb_bank0_rd_data_way1_out_178 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6707 = _T_6706 | _T_6452; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6453 = _T_5096 ? btb_bank0_rd_data_way1_out_179 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6708 = _T_6707 | _T_6453; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6454 = _T_5098 ? btb_bank0_rd_data_way1_out_180 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6709 = _T_6708 | _T_6454; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6455 = _T_5100 ? btb_bank0_rd_data_way1_out_181 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6710 = _T_6709 | _T_6455; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6456 = _T_5102 ? btb_bank0_rd_data_way1_out_182 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6711 = _T_6710 | _T_6456; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6457 = _T_5104 ? btb_bank0_rd_data_way1_out_183 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6712 = _T_6711 | _T_6457; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6458 = _T_5106 ? btb_bank0_rd_data_way1_out_184 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6713 = _T_6712 | _T_6458; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6459 = _T_5108 ? btb_bank0_rd_data_way1_out_185 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6714 = _T_6713 | _T_6459; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6460 = _T_5110 ? btb_bank0_rd_data_way1_out_186 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6715 = _T_6714 | _T_6460; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6461 = _T_5112 ? btb_bank0_rd_data_way1_out_187 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6716 = _T_6715 | _T_6461; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6462 = _T_5114 ? btb_bank0_rd_data_way1_out_188 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6717 = _T_6716 | _T_6462; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6463 = _T_5116 ? btb_bank0_rd_data_way1_out_189 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6718 = _T_6717 | _T_6463; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6464 = _T_5118 ? btb_bank0_rd_data_way1_out_190 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6719 = _T_6718 | _T_6464; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6465 = _T_5120 ? btb_bank0_rd_data_way1_out_191 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6720 = _T_6719 | _T_6465; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6466 = _T_5122 ? btb_bank0_rd_data_way1_out_192 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6721 = _T_6720 | _T_6466; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6467 = _T_5124 ? btb_bank0_rd_data_way1_out_193 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6722 = _T_6721 | _T_6467; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6468 = _T_5126 ? btb_bank0_rd_data_way1_out_194 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6723 = _T_6722 | _T_6468; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6469 = _T_5128 ? btb_bank0_rd_data_way1_out_195 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6724 = _T_6723 | _T_6469; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6470 = _T_5130 ? btb_bank0_rd_data_way1_out_196 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6725 = _T_6724 | _T_6470; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6471 = _T_5132 ? btb_bank0_rd_data_way1_out_197 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6726 = _T_6725 | _T_6471; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6472 = _T_5134 ? btb_bank0_rd_data_way1_out_198 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6727 = _T_6726 | _T_6472; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6473 = _T_5136 ? btb_bank0_rd_data_way1_out_199 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6728 = _T_6727 | _T_6473; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6474 = _T_5138 ? btb_bank0_rd_data_way1_out_200 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6729 = _T_6728 | _T_6474; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6475 = _T_5140 ? btb_bank0_rd_data_way1_out_201 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6730 = _T_6729 | _T_6475; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6476 = _T_5142 ? btb_bank0_rd_data_way1_out_202 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6731 = _T_6730 | _T_6476; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6477 = _T_5144 ? btb_bank0_rd_data_way1_out_203 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6732 = _T_6731 | _T_6477; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6478 = _T_5146 ? btb_bank0_rd_data_way1_out_204 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6733 = _T_6732 | _T_6478; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6479 = _T_5148 ? btb_bank0_rd_data_way1_out_205 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6734 = _T_6733 | _T_6479; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6480 = _T_5150 ? btb_bank0_rd_data_way1_out_206 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6735 = _T_6734 | _T_6480; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6481 = _T_5152 ? btb_bank0_rd_data_way1_out_207 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6736 = _T_6735 | _T_6481; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6482 = _T_5154 ? btb_bank0_rd_data_way1_out_208 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6737 = _T_6736 | _T_6482; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6483 = _T_5156 ? btb_bank0_rd_data_way1_out_209 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6738 = _T_6737 | _T_6483; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6484 = _T_5158 ? btb_bank0_rd_data_way1_out_210 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6739 = _T_6738 | _T_6484; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6485 = _T_5160 ? btb_bank0_rd_data_way1_out_211 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6740 = _T_6739 | _T_6485; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6486 = _T_5162 ? btb_bank0_rd_data_way1_out_212 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6741 = _T_6740 | _T_6486; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6487 = _T_5164 ? btb_bank0_rd_data_way1_out_213 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6742 = _T_6741 | _T_6487; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6488 = _T_5166 ? btb_bank0_rd_data_way1_out_214 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6743 = _T_6742 | _T_6488; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6489 = _T_5168 ? btb_bank0_rd_data_way1_out_215 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6744 = _T_6743 | _T_6489; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6490 = _T_5170 ? btb_bank0_rd_data_way1_out_216 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6745 = _T_6744 | _T_6490; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6491 = _T_5172 ? btb_bank0_rd_data_way1_out_217 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6746 = _T_6745 | _T_6491; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6492 = _T_5174 ? btb_bank0_rd_data_way1_out_218 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6747 = _T_6746 | _T_6492; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6493 = _T_5176 ? btb_bank0_rd_data_way1_out_219 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6748 = _T_6747 | _T_6493; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6494 = _T_5178 ? btb_bank0_rd_data_way1_out_220 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6749 = _T_6748 | _T_6494; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6495 = _T_5180 ? btb_bank0_rd_data_way1_out_221 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6750 = _T_6749 | _T_6495; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6496 = _T_5182 ? btb_bank0_rd_data_way1_out_222 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6751 = _T_6750 | _T_6496; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6497 = _T_5184 ? btb_bank0_rd_data_way1_out_223 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6752 = _T_6751 | _T_6497; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6498 = _T_5186 ? btb_bank0_rd_data_way1_out_224 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6753 = _T_6752 | _T_6498; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6499 = _T_5188 ? btb_bank0_rd_data_way1_out_225 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6754 = _T_6753 | _T_6499; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6500 = _T_5190 ? btb_bank0_rd_data_way1_out_226 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6755 = _T_6754 | _T_6500; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6501 = _T_5192 ? btb_bank0_rd_data_way1_out_227 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6756 = _T_6755 | _T_6501; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6502 = _T_5194 ? btb_bank0_rd_data_way1_out_228 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6757 = _T_6756 | _T_6502; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6503 = _T_5196 ? btb_bank0_rd_data_way1_out_229 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6758 = _T_6757 | _T_6503; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6504 = _T_5198 ? btb_bank0_rd_data_way1_out_230 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6759 = _T_6758 | _T_6504; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6505 = _T_5200 ? btb_bank0_rd_data_way1_out_231 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6760 = _T_6759 | _T_6505; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6506 = _T_5202 ? btb_bank0_rd_data_way1_out_232 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6761 = _T_6760 | _T_6506; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6507 = _T_5204 ? btb_bank0_rd_data_way1_out_233 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6762 = _T_6761 | _T_6507; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6508 = _T_5206 ? btb_bank0_rd_data_way1_out_234 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6763 = _T_6762 | _T_6508; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6509 = _T_5208 ? btb_bank0_rd_data_way1_out_235 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6764 = _T_6763 | _T_6509; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6510 = _T_5210 ? btb_bank0_rd_data_way1_out_236 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6765 = _T_6764 | _T_6510; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6511 = _T_5212 ? btb_bank0_rd_data_way1_out_237 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6766 = _T_6765 | _T_6511; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6512 = _T_5214 ? btb_bank0_rd_data_way1_out_238 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6767 = _T_6766 | _T_6512; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6513 = _T_5216 ? btb_bank0_rd_data_way1_out_239 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6768 = _T_6767 | _T_6513; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6514 = _T_5218 ? btb_bank0_rd_data_way1_out_240 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6769 = _T_6768 | _T_6514; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6515 = _T_5220 ? btb_bank0_rd_data_way1_out_241 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6770 = _T_6769 | _T_6515; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6516 = _T_5222 ? btb_bank0_rd_data_way1_out_242 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6771 = _T_6770 | _T_6516; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6517 = _T_5224 ? btb_bank0_rd_data_way1_out_243 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6772 = _T_6771 | _T_6517; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6518 = _T_5226 ? btb_bank0_rd_data_way1_out_244 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6773 = _T_6772 | _T_6518; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6519 = _T_5228 ? btb_bank0_rd_data_way1_out_245 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6774 = _T_6773 | _T_6519; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6520 = _T_5230 ? btb_bank0_rd_data_way1_out_246 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6775 = _T_6774 | _T_6520; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6521 = _T_5232 ? btb_bank0_rd_data_way1_out_247 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6776 = _T_6775 | _T_6521; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6522 = _T_5234 ? btb_bank0_rd_data_way1_out_248 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6777 = _T_6776 | _T_6522; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6523 = _T_5236 ? btb_bank0_rd_data_way1_out_249 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6778 = _T_6777 | _T_6523; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6524 = _T_5238 ? btb_bank0_rd_data_way1_out_250 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6779 = _T_6778 | _T_6524; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6525 = _T_5240 ? btb_bank0_rd_data_way1_out_251 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6780 = _T_6779 | _T_6525; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6526 = _T_5242 ? btb_bank0_rd_data_way1_out_252 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6781 = _T_6780 | _T_6526; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6527 = _T_5244 ? btb_bank0_rd_data_way1_out_253 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6782 = _T_6781 | _T_6527; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6528 = _T_5246 ? btb_bank0_rd_data_way1_out_254 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6783 = _T_6782 | _T_6528; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_6529 = _T_5248 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_bank0_rd_data_way1_p1_f = _T_6783 | _T_6529; // @[Mux.scala 27:72]
|
|
wire _T_80 = btb_bank0_rd_data_way1_p1_f[21:17] == _T_37; // @[ifu_bp_ctl.scala 154:109]
|
|
wire _T_81 = btb_bank0_rd_data_way1_p1_f[0] & _T_80; // @[ifu_bp_ctl.scala 154:63]
|
|
wire _T_84 = _T_81 & _T_73; // @[ifu_bp_ctl.scala 154:132]
|
|
wire _T_85 = _T_84 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 155:59]
|
|
wire _T_87 = _T_85 & _T; // @[ifu_bp_ctl.scala 155:80]
|
|
wire _T_120 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[ifu_bp_ctl.scala 167:101]
|
|
wire _T_121 = _T_87 & _T_120; // @[ifu_bp_ctl.scala 167:64]
|
|
wire _T_125 = ~_T_120; // @[ifu_bp_ctl.scala 168:29]
|
|
wire _T_126 = _T_87 & _T_125; // @[ifu_bp_ctl.scala 168:27]
|
|
wire [1:0] _T_127 = {_T_121,_T_126}; // @[Cat.scala 29:58]
|
|
wire [21:0] _T_151 = _T_127[0] ? btb_bank0_rd_data_way1_p1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_152 = _T_150 | _T_151; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_165 = io_ifc_fetch_addr_f[0] ? _T_152 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_vbank1_rd_data_f = _T_164 | _T_165; // @[Mux.scala 27:72]
|
|
wire _T_262 = btb_vbank1_rd_data_f[2] | btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 279:59]
|
|
wire [21:0] _T_134 = _T_97[0] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_135 = _T_107[0] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_136 = _T_134 | _T_135; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_157 = _T_162 ? _T_136 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] _T_158 = io_ifc_fetch_addr_f[0] ? _T_144 : 22'h0; // @[Mux.scala 27:72]
|
|
wire [21:0] btb_vbank0_rd_data_f = _T_157 | _T_158; // @[Mux.scala 27:72]
|
|
wire _T_265 = btb_vbank0_rd_data_f[2] | btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 280:32]
|
|
wire [1:0] bht_force_taken_f = {_T_262,_T_265}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_608 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
|
|
reg [7:0] fghr; // @[Reg.scala 27:20]
|
|
wire [7:0] bht_rd_addr_f = _T_608[9:2] ^ fghr; // @[lib.scala 62:35]
|
|
wire _T_22498 = bht_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23010 = _T_22498 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
|
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wire _T_22500 = bht_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23011 = _T_22500 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23266 = _T_23010 | _T_23011; // @[Mux.scala 27:72]
|
|
wire _T_22502 = bht_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23012 = _T_22502 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23267 = _T_23266 | _T_23012; // @[Mux.scala 27:72]
|
|
wire _T_22504 = bht_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23013 = _T_22504 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23268 = _T_23267 | _T_23013; // @[Mux.scala 27:72]
|
|
wire _T_22506 = bht_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23014 = _T_22506 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23269 = _T_23268 | _T_23014; // @[Mux.scala 27:72]
|
|
wire _T_22508 = bht_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23015 = _T_22508 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23270 = _T_23269 | _T_23015; // @[Mux.scala 27:72]
|
|
wire _T_22510 = bht_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23016 = _T_22510 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23271 = _T_23270 | _T_23016; // @[Mux.scala 27:72]
|
|
wire _T_22512 = bht_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23017 = _T_22512 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23272 = _T_23271 | _T_23017; // @[Mux.scala 27:72]
|
|
wire _T_22514 = bht_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23018 = _T_22514 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23273 = _T_23272 | _T_23018; // @[Mux.scala 27:72]
|
|
wire _T_22516 = bht_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23019 = _T_22516 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23274 = _T_23273 | _T_23019; // @[Mux.scala 27:72]
|
|
wire _T_22518 = bht_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23020 = _T_22518 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23275 = _T_23274 | _T_23020; // @[Mux.scala 27:72]
|
|
wire _T_22520 = bht_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23021 = _T_22520 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23276 = _T_23275 | _T_23021; // @[Mux.scala 27:72]
|
|
wire _T_22522 = bht_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23022 = _T_22522 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23277 = _T_23276 | _T_23022; // @[Mux.scala 27:72]
|
|
wire _T_22524 = bht_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23023 = _T_22524 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23278 = _T_23277 | _T_23023; // @[Mux.scala 27:72]
|
|
wire _T_22526 = bht_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23024 = _T_22526 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23279 = _T_23278 | _T_23024; // @[Mux.scala 27:72]
|
|
wire _T_22528 = bht_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23025 = _T_22528 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23280 = _T_23279 | _T_23025; // @[Mux.scala 27:72]
|
|
wire _T_22530 = bht_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_16; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23026 = _T_22530 ? bht_bank_rd_data_out_1_16 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23281 = _T_23280 | _T_23026; // @[Mux.scala 27:72]
|
|
wire _T_22532 = bht_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_17; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23027 = _T_22532 ? bht_bank_rd_data_out_1_17 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23282 = _T_23281 | _T_23027; // @[Mux.scala 27:72]
|
|
wire _T_22534 = bht_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_18; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23028 = _T_22534 ? bht_bank_rd_data_out_1_18 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23283 = _T_23282 | _T_23028; // @[Mux.scala 27:72]
|
|
wire _T_22536 = bht_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_19; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23029 = _T_22536 ? bht_bank_rd_data_out_1_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23284 = _T_23283 | _T_23029; // @[Mux.scala 27:72]
|
|
wire _T_22538 = bht_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_20; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23030 = _T_22538 ? bht_bank_rd_data_out_1_20 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23285 = _T_23284 | _T_23030; // @[Mux.scala 27:72]
|
|
wire _T_22540 = bht_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_21; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23031 = _T_22540 ? bht_bank_rd_data_out_1_21 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23286 = _T_23285 | _T_23031; // @[Mux.scala 27:72]
|
|
wire _T_22542 = bht_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_22; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23032 = _T_22542 ? bht_bank_rd_data_out_1_22 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23287 = _T_23286 | _T_23032; // @[Mux.scala 27:72]
|
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wire _T_22544 = bht_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_23; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23033 = _T_22544 ? bht_bank_rd_data_out_1_23 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23288 = _T_23287 | _T_23033; // @[Mux.scala 27:72]
|
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wire _T_22546 = bht_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_24; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23034 = _T_22546 ? bht_bank_rd_data_out_1_24 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23289 = _T_23288 | _T_23034; // @[Mux.scala 27:72]
|
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wire _T_22548 = bht_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_25; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23035 = _T_22548 ? bht_bank_rd_data_out_1_25 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_23290 = _T_23289 | _T_23035; // @[Mux.scala 27:72]
|
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wire _T_22550 = bht_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_26; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23036 = _T_22550 ? bht_bank_rd_data_out_1_26 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23291 = _T_23290 | _T_23036; // @[Mux.scala 27:72]
|
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wire _T_22552 = bht_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_27; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23037 = _T_22552 ? bht_bank_rd_data_out_1_27 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23292 = _T_23291 | _T_23037; // @[Mux.scala 27:72]
|
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wire _T_22554 = bht_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_28; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23038 = _T_22554 ? bht_bank_rd_data_out_1_28 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23293 = _T_23292 | _T_23038; // @[Mux.scala 27:72]
|
|
wire _T_22556 = bht_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_29; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23039 = _T_22556 ? bht_bank_rd_data_out_1_29 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23294 = _T_23293 | _T_23039; // @[Mux.scala 27:72]
|
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wire _T_22558 = bht_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_30; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23040 = _T_22558 ? bht_bank_rd_data_out_1_30 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23295 = _T_23294 | _T_23040; // @[Mux.scala 27:72]
|
|
wire _T_22560 = bht_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_31; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23041 = _T_22560 ? bht_bank_rd_data_out_1_31 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23296 = _T_23295 | _T_23041; // @[Mux.scala 27:72]
|
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wire _T_22562 = bht_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_32; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23042 = _T_22562 ? bht_bank_rd_data_out_1_32 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23297 = _T_23296 | _T_23042; // @[Mux.scala 27:72]
|
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wire _T_22564 = bht_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_33; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23043 = _T_22564 ? bht_bank_rd_data_out_1_33 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23298 = _T_23297 | _T_23043; // @[Mux.scala 27:72]
|
|
wire _T_22566 = bht_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_34; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23044 = _T_22566 ? bht_bank_rd_data_out_1_34 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23299 = _T_23298 | _T_23044; // @[Mux.scala 27:72]
|
|
wire _T_22568 = bht_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_35; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23045 = _T_22568 ? bht_bank_rd_data_out_1_35 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23300 = _T_23299 | _T_23045; // @[Mux.scala 27:72]
|
|
wire _T_22570 = bht_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_36; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23046 = _T_22570 ? bht_bank_rd_data_out_1_36 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23301 = _T_23300 | _T_23046; // @[Mux.scala 27:72]
|
|
wire _T_22572 = bht_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_37; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23047 = _T_22572 ? bht_bank_rd_data_out_1_37 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23302 = _T_23301 | _T_23047; // @[Mux.scala 27:72]
|
|
wire _T_22574 = bht_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_38; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23048 = _T_22574 ? bht_bank_rd_data_out_1_38 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23303 = _T_23302 | _T_23048; // @[Mux.scala 27:72]
|
|
wire _T_22576 = bht_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_39; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23049 = _T_22576 ? bht_bank_rd_data_out_1_39 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23304 = _T_23303 | _T_23049; // @[Mux.scala 27:72]
|
|
wire _T_22578 = bht_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_40; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23050 = _T_22578 ? bht_bank_rd_data_out_1_40 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23305 = _T_23304 | _T_23050; // @[Mux.scala 27:72]
|
|
wire _T_22580 = bht_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_41; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23051 = _T_22580 ? bht_bank_rd_data_out_1_41 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23306 = _T_23305 | _T_23051; // @[Mux.scala 27:72]
|
|
wire _T_22582 = bht_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_42; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23052 = _T_22582 ? bht_bank_rd_data_out_1_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23307 = _T_23306 | _T_23052; // @[Mux.scala 27:72]
|
|
wire _T_22584 = bht_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_43; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23053 = _T_22584 ? bht_bank_rd_data_out_1_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23308 = _T_23307 | _T_23053; // @[Mux.scala 27:72]
|
|
wire _T_22586 = bht_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_44; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23054 = _T_22586 ? bht_bank_rd_data_out_1_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23309 = _T_23308 | _T_23054; // @[Mux.scala 27:72]
|
|
wire _T_22588 = bht_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_45; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23055 = _T_22588 ? bht_bank_rd_data_out_1_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23310 = _T_23309 | _T_23055; // @[Mux.scala 27:72]
|
|
wire _T_22590 = bht_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_46; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23056 = _T_22590 ? bht_bank_rd_data_out_1_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23311 = _T_23310 | _T_23056; // @[Mux.scala 27:72]
|
|
wire _T_22592 = bht_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_47; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23057 = _T_22592 ? bht_bank_rd_data_out_1_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23312 = _T_23311 | _T_23057; // @[Mux.scala 27:72]
|
|
wire _T_22594 = bht_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_48; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23058 = _T_22594 ? bht_bank_rd_data_out_1_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23313 = _T_23312 | _T_23058; // @[Mux.scala 27:72]
|
|
wire _T_22596 = bht_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_49; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23059 = _T_22596 ? bht_bank_rd_data_out_1_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23314 = _T_23313 | _T_23059; // @[Mux.scala 27:72]
|
|
wire _T_22598 = bht_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_50; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23060 = _T_22598 ? bht_bank_rd_data_out_1_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23315 = _T_23314 | _T_23060; // @[Mux.scala 27:72]
|
|
wire _T_22600 = bht_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_51; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23061 = _T_22600 ? bht_bank_rd_data_out_1_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23316 = _T_23315 | _T_23061; // @[Mux.scala 27:72]
|
|
wire _T_22602 = bht_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_52; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23062 = _T_22602 ? bht_bank_rd_data_out_1_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23317 = _T_23316 | _T_23062; // @[Mux.scala 27:72]
|
|
wire _T_22604 = bht_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_53; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23063 = _T_22604 ? bht_bank_rd_data_out_1_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23318 = _T_23317 | _T_23063; // @[Mux.scala 27:72]
|
|
wire _T_22606 = bht_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_54; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23064 = _T_22606 ? bht_bank_rd_data_out_1_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23319 = _T_23318 | _T_23064; // @[Mux.scala 27:72]
|
|
wire _T_22608 = bht_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_55; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23065 = _T_22608 ? bht_bank_rd_data_out_1_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23320 = _T_23319 | _T_23065; // @[Mux.scala 27:72]
|
|
wire _T_22610 = bht_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_56; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23066 = _T_22610 ? bht_bank_rd_data_out_1_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23321 = _T_23320 | _T_23066; // @[Mux.scala 27:72]
|
|
wire _T_22612 = bht_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_57; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23067 = _T_22612 ? bht_bank_rd_data_out_1_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23322 = _T_23321 | _T_23067; // @[Mux.scala 27:72]
|
|
wire _T_22614 = bht_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_58; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23068 = _T_22614 ? bht_bank_rd_data_out_1_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23323 = _T_23322 | _T_23068; // @[Mux.scala 27:72]
|
|
wire _T_22616 = bht_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_59; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23069 = _T_22616 ? bht_bank_rd_data_out_1_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23324 = _T_23323 | _T_23069; // @[Mux.scala 27:72]
|
|
wire _T_22618 = bht_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_60; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23070 = _T_22618 ? bht_bank_rd_data_out_1_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23325 = _T_23324 | _T_23070; // @[Mux.scala 27:72]
|
|
wire _T_22620 = bht_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_61; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23071 = _T_22620 ? bht_bank_rd_data_out_1_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23326 = _T_23325 | _T_23071; // @[Mux.scala 27:72]
|
|
wire _T_22622 = bht_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_62; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23072 = _T_22622 ? bht_bank_rd_data_out_1_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23327 = _T_23326 | _T_23072; // @[Mux.scala 27:72]
|
|
wire _T_22624 = bht_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_63; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23073 = _T_22624 ? bht_bank_rd_data_out_1_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23328 = _T_23327 | _T_23073; // @[Mux.scala 27:72]
|
|
wire _T_22626 = bht_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_64; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23074 = _T_22626 ? bht_bank_rd_data_out_1_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23329 = _T_23328 | _T_23074; // @[Mux.scala 27:72]
|
|
wire _T_22628 = bht_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_65; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23075 = _T_22628 ? bht_bank_rd_data_out_1_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23330 = _T_23329 | _T_23075; // @[Mux.scala 27:72]
|
|
wire _T_22630 = bht_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_66; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23076 = _T_22630 ? bht_bank_rd_data_out_1_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23331 = _T_23330 | _T_23076; // @[Mux.scala 27:72]
|
|
wire _T_22632 = bht_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_67; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23077 = _T_22632 ? bht_bank_rd_data_out_1_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23332 = _T_23331 | _T_23077; // @[Mux.scala 27:72]
|
|
wire _T_22634 = bht_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_68; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23078 = _T_22634 ? bht_bank_rd_data_out_1_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23333 = _T_23332 | _T_23078; // @[Mux.scala 27:72]
|
|
wire _T_22636 = bht_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_69; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23079 = _T_22636 ? bht_bank_rd_data_out_1_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23334 = _T_23333 | _T_23079; // @[Mux.scala 27:72]
|
|
wire _T_22638 = bht_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_70; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23080 = _T_22638 ? bht_bank_rd_data_out_1_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23335 = _T_23334 | _T_23080; // @[Mux.scala 27:72]
|
|
wire _T_22640 = bht_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_71; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23081 = _T_22640 ? bht_bank_rd_data_out_1_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23336 = _T_23335 | _T_23081; // @[Mux.scala 27:72]
|
|
wire _T_22642 = bht_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_72; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23082 = _T_22642 ? bht_bank_rd_data_out_1_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23337 = _T_23336 | _T_23082; // @[Mux.scala 27:72]
|
|
wire _T_22644 = bht_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_73; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23083 = _T_22644 ? bht_bank_rd_data_out_1_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23338 = _T_23337 | _T_23083; // @[Mux.scala 27:72]
|
|
wire _T_22646 = bht_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_74; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23084 = _T_22646 ? bht_bank_rd_data_out_1_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23339 = _T_23338 | _T_23084; // @[Mux.scala 27:72]
|
|
wire _T_22648 = bht_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_75; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23085 = _T_22648 ? bht_bank_rd_data_out_1_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23340 = _T_23339 | _T_23085; // @[Mux.scala 27:72]
|
|
wire _T_22650 = bht_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_76; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23086 = _T_22650 ? bht_bank_rd_data_out_1_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23341 = _T_23340 | _T_23086; // @[Mux.scala 27:72]
|
|
wire _T_22652 = bht_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_77; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23087 = _T_22652 ? bht_bank_rd_data_out_1_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23342 = _T_23341 | _T_23087; // @[Mux.scala 27:72]
|
|
wire _T_22654 = bht_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_78; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23088 = _T_22654 ? bht_bank_rd_data_out_1_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23343 = _T_23342 | _T_23088; // @[Mux.scala 27:72]
|
|
wire _T_22656 = bht_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_79; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23089 = _T_22656 ? bht_bank_rd_data_out_1_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23344 = _T_23343 | _T_23089; // @[Mux.scala 27:72]
|
|
wire _T_22658 = bht_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_80; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23090 = _T_22658 ? bht_bank_rd_data_out_1_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23345 = _T_23344 | _T_23090; // @[Mux.scala 27:72]
|
|
wire _T_22660 = bht_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_81; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23091 = _T_22660 ? bht_bank_rd_data_out_1_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23346 = _T_23345 | _T_23091; // @[Mux.scala 27:72]
|
|
wire _T_22662 = bht_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_82; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23092 = _T_22662 ? bht_bank_rd_data_out_1_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23347 = _T_23346 | _T_23092; // @[Mux.scala 27:72]
|
|
wire _T_22664 = bht_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_83; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23093 = _T_22664 ? bht_bank_rd_data_out_1_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23348 = _T_23347 | _T_23093; // @[Mux.scala 27:72]
|
|
wire _T_22666 = bht_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_84; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23094 = _T_22666 ? bht_bank_rd_data_out_1_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23349 = _T_23348 | _T_23094; // @[Mux.scala 27:72]
|
|
wire _T_22668 = bht_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_85; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23095 = _T_22668 ? bht_bank_rd_data_out_1_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23350 = _T_23349 | _T_23095; // @[Mux.scala 27:72]
|
|
wire _T_22670 = bht_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_86; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23096 = _T_22670 ? bht_bank_rd_data_out_1_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23351 = _T_23350 | _T_23096; // @[Mux.scala 27:72]
|
|
wire _T_22672 = bht_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_87; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23097 = _T_22672 ? bht_bank_rd_data_out_1_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23352 = _T_23351 | _T_23097; // @[Mux.scala 27:72]
|
|
wire _T_22674 = bht_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_88; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23098 = _T_22674 ? bht_bank_rd_data_out_1_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23353 = _T_23352 | _T_23098; // @[Mux.scala 27:72]
|
|
wire _T_22676 = bht_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_89; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23099 = _T_22676 ? bht_bank_rd_data_out_1_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23354 = _T_23353 | _T_23099; // @[Mux.scala 27:72]
|
|
wire _T_22678 = bht_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_90; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23100 = _T_22678 ? bht_bank_rd_data_out_1_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23355 = _T_23354 | _T_23100; // @[Mux.scala 27:72]
|
|
wire _T_22680 = bht_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_91; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23101 = _T_22680 ? bht_bank_rd_data_out_1_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23356 = _T_23355 | _T_23101; // @[Mux.scala 27:72]
|
|
wire _T_22682 = bht_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_92; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23102 = _T_22682 ? bht_bank_rd_data_out_1_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23357 = _T_23356 | _T_23102; // @[Mux.scala 27:72]
|
|
wire _T_22684 = bht_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_93; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23103 = _T_22684 ? bht_bank_rd_data_out_1_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23358 = _T_23357 | _T_23103; // @[Mux.scala 27:72]
|
|
wire _T_22686 = bht_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_94; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23104 = _T_22686 ? bht_bank_rd_data_out_1_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23359 = _T_23358 | _T_23104; // @[Mux.scala 27:72]
|
|
wire _T_22688 = bht_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_95; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23105 = _T_22688 ? bht_bank_rd_data_out_1_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23360 = _T_23359 | _T_23105; // @[Mux.scala 27:72]
|
|
wire _T_22690 = bht_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_96; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23106 = _T_22690 ? bht_bank_rd_data_out_1_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23361 = _T_23360 | _T_23106; // @[Mux.scala 27:72]
|
|
wire _T_22692 = bht_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_97; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23107 = _T_22692 ? bht_bank_rd_data_out_1_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23362 = _T_23361 | _T_23107; // @[Mux.scala 27:72]
|
|
wire _T_22694 = bht_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_98; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23108 = _T_22694 ? bht_bank_rd_data_out_1_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23363 = _T_23362 | _T_23108; // @[Mux.scala 27:72]
|
|
wire _T_22696 = bht_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_99; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23109 = _T_22696 ? bht_bank_rd_data_out_1_99 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23364 = _T_23363 | _T_23109; // @[Mux.scala 27:72]
|
|
wire _T_22698 = bht_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_100; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23110 = _T_22698 ? bht_bank_rd_data_out_1_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23365 = _T_23364 | _T_23110; // @[Mux.scala 27:72]
|
|
wire _T_22700 = bht_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_101; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23111 = _T_22700 ? bht_bank_rd_data_out_1_101 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23366 = _T_23365 | _T_23111; // @[Mux.scala 27:72]
|
|
wire _T_22702 = bht_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_102; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23112 = _T_22702 ? bht_bank_rd_data_out_1_102 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23367 = _T_23366 | _T_23112; // @[Mux.scala 27:72]
|
|
wire _T_22704 = bht_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_103; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23113 = _T_22704 ? bht_bank_rd_data_out_1_103 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23368 = _T_23367 | _T_23113; // @[Mux.scala 27:72]
|
|
wire _T_22706 = bht_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_104; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23114 = _T_22706 ? bht_bank_rd_data_out_1_104 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23369 = _T_23368 | _T_23114; // @[Mux.scala 27:72]
|
|
wire _T_22708 = bht_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_105; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23115 = _T_22708 ? bht_bank_rd_data_out_1_105 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23370 = _T_23369 | _T_23115; // @[Mux.scala 27:72]
|
|
wire _T_22710 = bht_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_106; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23116 = _T_22710 ? bht_bank_rd_data_out_1_106 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23371 = _T_23370 | _T_23116; // @[Mux.scala 27:72]
|
|
wire _T_22712 = bht_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_107; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23117 = _T_22712 ? bht_bank_rd_data_out_1_107 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23372 = _T_23371 | _T_23117; // @[Mux.scala 27:72]
|
|
wire _T_22714 = bht_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_108; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23118 = _T_22714 ? bht_bank_rd_data_out_1_108 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23373 = _T_23372 | _T_23118; // @[Mux.scala 27:72]
|
|
wire _T_22716 = bht_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_109; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23119 = _T_22716 ? bht_bank_rd_data_out_1_109 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23374 = _T_23373 | _T_23119; // @[Mux.scala 27:72]
|
|
wire _T_22718 = bht_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_110; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23120 = _T_22718 ? bht_bank_rd_data_out_1_110 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23375 = _T_23374 | _T_23120; // @[Mux.scala 27:72]
|
|
wire _T_22720 = bht_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_111; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23121 = _T_22720 ? bht_bank_rd_data_out_1_111 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23376 = _T_23375 | _T_23121; // @[Mux.scala 27:72]
|
|
wire _T_22722 = bht_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_112; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23122 = _T_22722 ? bht_bank_rd_data_out_1_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23377 = _T_23376 | _T_23122; // @[Mux.scala 27:72]
|
|
wire _T_22724 = bht_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_113; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23123 = _T_22724 ? bht_bank_rd_data_out_1_113 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23378 = _T_23377 | _T_23123; // @[Mux.scala 27:72]
|
|
wire _T_22726 = bht_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_114; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23124 = _T_22726 ? bht_bank_rd_data_out_1_114 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23379 = _T_23378 | _T_23124; // @[Mux.scala 27:72]
|
|
wire _T_22728 = bht_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_115; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23125 = _T_22728 ? bht_bank_rd_data_out_1_115 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23380 = _T_23379 | _T_23125; // @[Mux.scala 27:72]
|
|
wire _T_22730 = bht_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_116; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23126 = _T_22730 ? bht_bank_rd_data_out_1_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23381 = _T_23380 | _T_23126; // @[Mux.scala 27:72]
|
|
wire _T_22732 = bht_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_117; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23127 = _T_22732 ? bht_bank_rd_data_out_1_117 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23382 = _T_23381 | _T_23127; // @[Mux.scala 27:72]
|
|
wire _T_22734 = bht_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_118; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23128 = _T_22734 ? bht_bank_rd_data_out_1_118 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23383 = _T_23382 | _T_23128; // @[Mux.scala 27:72]
|
|
wire _T_22736 = bht_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_119; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23129 = _T_22736 ? bht_bank_rd_data_out_1_119 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23384 = _T_23383 | _T_23129; // @[Mux.scala 27:72]
|
|
wire _T_22738 = bht_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_120; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23130 = _T_22738 ? bht_bank_rd_data_out_1_120 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23385 = _T_23384 | _T_23130; // @[Mux.scala 27:72]
|
|
wire _T_22740 = bht_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_121; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23131 = _T_22740 ? bht_bank_rd_data_out_1_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23386 = _T_23385 | _T_23131; // @[Mux.scala 27:72]
|
|
wire _T_22742 = bht_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_122; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23132 = _T_22742 ? bht_bank_rd_data_out_1_122 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23387 = _T_23386 | _T_23132; // @[Mux.scala 27:72]
|
|
wire _T_22744 = bht_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_123; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23133 = _T_22744 ? bht_bank_rd_data_out_1_123 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23388 = _T_23387 | _T_23133; // @[Mux.scala 27:72]
|
|
wire _T_22746 = bht_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_124; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23134 = _T_22746 ? bht_bank_rd_data_out_1_124 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23389 = _T_23388 | _T_23134; // @[Mux.scala 27:72]
|
|
wire _T_22748 = bht_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_125; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23135 = _T_22748 ? bht_bank_rd_data_out_1_125 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23390 = _T_23389 | _T_23135; // @[Mux.scala 27:72]
|
|
wire _T_22750 = bht_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_126; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23136 = _T_22750 ? bht_bank_rd_data_out_1_126 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23391 = _T_23390 | _T_23136; // @[Mux.scala 27:72]
|
|
wire _T_22752 = bht_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_127; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23137 = _T_22752 ? bht_bank_rd_data_out_1_127 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23392 = _T_23391 | _T_23137; // @[Mux.scala 27:72]
|
|
wire _T_22754 = bht_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_128; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23138 = _T_22754 ? bht_bank_rd_data_out_1_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23393 = _T_23392 | _T_23138; // @[Mux.scala 27:72]
|
|
wire _T_22756 = bht_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_129; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23139 = _T_22756 ? bht_bank_rd_data_out_1_129 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23394 = _T_23393 | _T_23139; // @[Mux.scala 27:72]
|
|
wire _T_22758 = bht_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_130; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23140 = _T_22758 ? bht_bank_rd_data_out_1_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23395 = _T_23394 | _T_23140; // @[Mux.scala 27:72]
|
|
wire _T_22760 = bht_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_131; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23141 = _T_22760 ? bht_bank_rd_data_out_1_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23396 = _T_23395 | _T_23141; // @[Mux.scala 27:72]
|
|
wire _T_22762 = bht_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_132; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23142 = _T_22762 ? bht_bank_rd_data_out_1_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23397 = _T_23396 | _T_23142; // @[Mux.scala 27:72]
|
|
wire _T_22764 = bht_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_133; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23143 = _T_22764 ? bht_bank_rd_data_out_1_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23398 = _T_23397 | _T_23143; // @[Mux.scala 27:72]
|
|
wire _T_22766 = bht_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_134; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23144 = _T_22766 ? bht_bank_rd_data_out_1_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23399 = _T_23398 | _T_23144; // @[Mux.scala 27:72]
|
|
wire _T_22768 = bht_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_135; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23145 = _T_22768 ? bht_bank_rd_data_out_1_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23400 = _T_23399 | _T_23145; // @[Mux.scala 27:72]
|
|
wire _T_22770 = bht_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_136; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23146 = _T_22770 ? bht_bank_rd_data_out_1_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23401 = _T_23400 | _T_23146; // @[Mux.scala 27:72]
|
|
wire _T_22772 = bht_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_137; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23147 = _T_22772 ? bht_bank_rd_data_out_1_137 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23402 = _T_23401 | _T_23147; // @[Mux.scala 27:72]
|
|
wire _T_22774 = bht_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_138; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23148 = _T_22774 ? bht_bank_rd_data_out_1_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23403 = _T_23402 | _T_23148; // @[Mux.scala 27:72]
|
|
wire _T_22776 = bht_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_139; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23149 = _T_22776 ? bht_bank_rd_data_out_1_139 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23404 = _T_23403 | _T_23149; // @[Mux.scala 27:72]
|
|
wire _T_22778 = bht_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_140; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23150 = _T_22778 ? bht_bank_rd_data_out_1_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23405 = _T_23404 | _T_23150; // @[Mux.scala 27:72]
|
|
wire _T_22780 = bht_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_141; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23151 = _T_22780 ? bht_bank_rd_data_out_1_141 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23406 = _T_23405 | _T_23151; // @[Mux.scala 27:72]
|
|
wire _T_22782 = bht_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_142; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23152 = _T_22782 ? bht_bank_rd_data_out_1_142 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23407 = _T_23406 | _T_23152; // @[Mux.scala 27:72]
|
|
wire _T_22784 = bht_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_143; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23153 = _T_22784 ? bht_bank_rd_data_out_1_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23408 = _T_23407 | _T_23153; // @[Mux.scala 27:72]
|
|
wire _T_22786 = bht_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_144; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23154 = _T_22786 ? bht_bank_rd_data_out_1_144 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23409 = _T_23408 | _T_23154; // @[Mux.scala 27:72]
|
|
wire _T_22788 = bht_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_145; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23155 = _T_22788 ? bht_bank_rd_data_out_1_145 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23410 = _T_23409 | _T_23155; // @[Mux.scala 27:72]
|
|
wire _T_22790 = bht_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_146; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23156 = _T_22790 ? bht_bank_rd_data_out_1_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23411 = _T_23410 | _T_23156; // @[Mux.scala 27:72]
|
|
wire _T_22792 = bht_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_147; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23157 = _T_22792 ? bht_bank_rd_data_out_1_147 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23412 = _T_23411 | _T_23157; // @[Mux.scala 27:72]
|
|
wire _T_22794 = bht_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_148; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23158 = _T_22794 ? bht_bank_rd_data_out_1_148 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23413 = _T_23412 | _T_23158; // @[Mux.scala 27:72]
|
|
wire _T_22796 = bht_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_149; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23159 = _T_22796 ? bht_bank_rd_data_out_1_149 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23414 = _T_23413 | _T_23159; // @[Mux.scala 27:72]
|
|
wire _T_22798 = bht_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_150; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23160 = _T_22798 ? bht_bank_rd_data_out_1_150 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23415 = _T_23414 | _T_23160; // @[Mux.scala 27:72]
|
|
wire _T_22800 = bht_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_151; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23161 = _T_22800 ? bht_bank_rd_data_out_1_151 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23416 = _T_23415 | _T_23161; // @[Mux.scala 27:72]
|
|
wire _T_22802 = bht_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_152; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23162 = _T_22802 ? bht_bank_rd_data_out_1_152 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23417 = _T_23416 | _T_23162; // @[Mux.scala 27:72]
|
|
wire _T_22804 = bht_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_153; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23163 = _T_22804 ? bht_bank_rd_data_out_1_153 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23418 = _T_23417 | _T_23163; // @[Mux.scala 27:72]
|
|
wire _T_22806 = bht_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_154; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23164 = _T_22806 ? bht_bank_rd_data_out_1_154 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23419 = _T_23418 | _T_23164; // @[Mux.scala 27:72]
|
|
wire _T_22808 = bht_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_155; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23165 = _T_22808 ? bht_bank_rd_data_out_1_155 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23420 = _T_23419 | _T_23165; // @[Mux.scala 27:72]
|
|
wire _T_22810 = bht_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_156; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23166 = _T_22810 ? bht_bank_rd_data_out_1_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23421 = _T_23420 | _T_23166; // @[Mux.scala 27:72]
|
|
wire _T_22812 = bht_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_157; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23167 = _T_22812 ? bht_bank_rd_data_out_1_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23422 = _T_23421 | _T_23167; // @[Mux.scala 27:72]
|
|
wire _T_22814 = bht_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_158; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23168 = _T_22814 ? bht_bank_rd_data_out_1_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23423 = _T_23422 | _T_23168; // @[Mux.scala 27:72]
|
|
wire _T_22816 = bht_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_159; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23169 = _T_22816 ? bht_bank_rd_data_out_1_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23424 = _T_23423 | _T_23169; // @[Mux.scala 27:72]
|
|
wire _T_22818 = bht_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_160; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23170 = _T_22818 ? bht_bank_rd_data_out_1_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23425 = _T_23424 | _T_23170; // @[Mux.scala 27:72]
|
|
wire _T_22820 = bht_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_161; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23171 = _T_22820 ? bht_bank_rd_data_out_1_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23426 = _T_23425 | _T_23171; // @[Mux.scala 27:72]
|
|
wire _T_22822 = bht_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_162; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23172 = _T_22822 ? bht_bank_rd_data_out_1_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23427 = _T_23426 | _T_23172; // @[Mux.scala 27:72]
|
|
wire _T_22824 = bht_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_163; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23173 = _T_22824 ? bht_bank_rd_data_out_1_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23428 = _T_23427 | _T_23173; // @[Mux.scala 27:72]
|
|
wire _T_22826 = bht_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_164; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23174 = _T_22826 ? bht_bank_rd_data_out_1_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23429 = _T_23428 | _T_23174; // @[Mux.scala 27:72]
|
|
wire _T_22828 = bht_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_165; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23175 = _T_22828 ? bht_bank_rd_data_out_1_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23430 = _T_23429 | _T_23175; // @[Mux.scala 27:72]
|
|
wire _T_22830 = bht_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_166; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23176 = _T_22830 ? bht_bank_rd_data_out_1_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23431 = _T_23430 | _T_23176; // @[Mux.scala 27:72]
|
|
wire _T_22832 = bht_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_167; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23177 = _T_22832 ? bht_bank_rd_data_out_1_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23432 = _T_23431 | _T_23177; // @[Mux.scala 27:72]
|
|
wire _T_22834 = bht_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_168; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23178 = _T_22834 ? bht_bank_rd_data_out_1_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23433 = _T_23432 | _T_23178; // @[Mux.scala 27:72]
|
|
wire _T_22836 = bht_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_169; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23179 = _T_22836 ? bht_bank_rd_data_out_1_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23434 = _T_23433 | _T_23179; // @[Mux.scala 27:72]
|
|
wire _T_22838 = bht_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_170; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23180 = _T_22838 ? bht_bank_rd_data_out_1_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23435 = _T_23434 | _T_23180; // @[Mux.scala 27:72]
|
|
wire _T_22840 = bht_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_171; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23181 = _T_22840 ? bht_bank_rd_data_out_1_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23436 = _T_23435 | _T_23181; // @[Mux.scala 27:72]
|
|
wire _T_22842 = bht_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_172; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23182 = _T_22842 ? bht_bank_rd_data_out_1_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23437 = _T_23436 | _T_23182; // @[Mux.scala 27:72]
|
|
wire _T_22844 = bht_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_173; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23183 = _T_22844 ? bht_bank_rd_data_out_1_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23438 = _T_23437 | _T_23183; // @[Mux.scala 27:72]
|
|
wire _T_22846 = bht_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_174; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23184 = _T_22846 ? bht_bank_rd_data_out_1_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23439 = _T_23438 | _T_23184; // @[Mux.scala 27:72]
|
|
wire _T_22848 = bht_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_175; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23185 = _T_22848 ? bht_bank_rd_data_out_1_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23440 = _T_23439 | _T_23185; // @[Mux.scala 27:72]
|
|
wire _T_22850 = bht_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_176; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23186 = _T_22850 ? bht_bank_rd_data_out_1_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23441 = _T_23440 | _T_23186; // @[Mux.scala 27:72]
|
|
wire _T_22852 = bht_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_177; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23187 = _T_22852 ? bht_bank_rd_data_out_1_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23442 = _T_23441 | _T_23187; // @[Mux.scala 27:72]
|
|
wire _T_22854 = bht_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_178; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23188 = _T_22854 ? bht_bank_rd_data_out_1_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23443 = _T_23442 | _T_23188; // @[Mux.scala 27:72]
|
|
wire _T_22856 = bht_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_179; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23189 = _T_22856 ? bht_bank_rd_data_out_1_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23444 = _T_23443 | _T_23189; // @[Mux.scala 27:72]
|
|
wire _T_22858 = bht_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_180; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23190 = _T_22858 ? bht_bank_rd_data_out_1_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23445 = _T_23444 | _T_23190; // @[Mux.scala 27:72]
|
|
wire _T_22860 = bht_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_181; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23191 = _T_22860 ? bht_bank_rd_data_out_1_181 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23446 = _T_23445 | _T_23191; // @[Mux.scala 27:72]
|
|
wire _T_22862 = bht_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_182; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23192 = _T_22862 ? bht_bank_rd_data_out_1_182 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23447 = _T_23446 | _T_23192; // @[Mux.scala 27:72]
|
|
wire _T_22864 = bht_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_183; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23193 = _T_22864 ? bht_bank_rd_data_out_1_183 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23448 = _T_23447 | _T_23193; // @[Mux.scala 27:72]
|
|
wire _T_22866 = bht_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_184; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23194 = _T_22866 ? bht_bank_rd_data_out_1_184 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23449 = _T_23448 | _T_23194; // @[Mux.scala 27:72]
|
|
wire _T_22868 = bht_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_185; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23195 = _T_22868 ? bht_bank_rd_data_out_1_185 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23450 = _T_23449 | _T_23195; // @[Mux.scala 27:72]
|
|
wire _T_22870 = bht_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_186; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23196 = _T_22870 ? bht_bank_rd_data_out_1_186 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23451 = _T_23450 | _T_23196; // @[Mux.scala 27:72]
|
|
wire _T_22872 = bht_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_187; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23197 = _T_22872 ? bht_bank_rd_data_out_1_187 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23452 = _T_23451 | _T_23197; // @[Mux.scala 27:72]
|
|
wire _T_22874 = bht_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_188; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23198 = _T_22874 ? bht_bank_rd_data_out_1_188 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23453 = _T_23452 | _T_23198; // @[Mux.scala 27:72]
|
|
wire _T_22876 = bht_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_189; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23199 = _T_22876 ? bht_bank_rd_data_out_1_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23454 = _T_23453 | _T_23199; // @[Mux.scala 27:72]
|
|
wire _T_22878 = bht_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_190; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23200 = _T_22878 ? bht_bank_rd_data_out_1_190 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23455 = _T_23454 | _T_23200; // @[Mux.scala 27:72]
|
|
wire _T_22880 = bht_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_191; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23201 = _T_22880 ? bht_bank_rd_data_out_1_191 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23456 = _T_23455 | _T_23201; // @[Mux.scala 27:72]
|
|
wire _T_22882 = bht_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_192; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23202 = _T_22882 ? bht_bank_rd_data_out_1_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23457 = _T_23456 | _T_23202; // @[Mux.scala 27:72]
|
|
wire _T_22884 = bht_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_193; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23203 = _T_22884 ? bht_bank_rd_data_out_1_193 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23458 = _T_23457 | _T_23203; // @[Mux.scala 27:72]
|
|
wire _T_22886 = bht_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_194; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23204 = _T_22886 ? bht_bank_rd_data_out_1_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23459 = _T_23458 | _T_23204; // @[Mux.scala 27:72]
|
|
wire _T_22888 = bht_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_195; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23205 = _T_22888 ? bht_bank_rd_data_out_1_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23460 = _T_23459 | _T_23205; // @[Mux.scala 27:72]
|
|
wire _T_22890 = bht_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_196; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23206 = _T_22890 ? bht_bank_rd_data_out_1_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23461 = _T_23460 | _T_23206; // @[Mux.scala 27:72]
|
|
wire _T_22892 = bht_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_197; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23207 = _T_22892 ? bht_bank_rd_data_out_1_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23462 = _T_23461 | _T_23207; // @[Mux.scala 27:72]
|
|
wire _T_22894 = bht_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_198; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23208 = _T_22894 ? bht_bank_rd_data_out_1_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23463 = _T_23462 | _T_23208; // @[Mux.scala 27:72]
|
|
wire _T_22896 = bht_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_199; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23209 = _T_22896 ? bht_bank_rd_data_out_1_199 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23464 = _T_23463 | _T_23209; // @[Mux.scala 27:72]
|
|
wire _T_22898 = bht_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_200; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23210 = _T_22898 ? bht_bank_rd_data_out_1_200 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23465 = _T_23464 | _T_23210; // @[Mux.scala 27:72]
|
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wire _T_22900 = bht_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_201; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23211 = _T_22900 ? bht_bank_rd_data_out_1_201 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23466 = _T_23465 | _T_23211; // @[Mux.scala 27:72]
|
|
wire _T_22902 = bht_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_202; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23212 = _T_22902 ? bht_bank_rd_data_out_1_202 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23467 = _T_23466 | _T_23212; // @[Mux.scala 27:72]
|
|
wire _T_22904 = bht_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_203; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23213 = _T_22904 ? bht_bank_rd_data_out_1_203 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23468 = _T_23467 | _T_23213; // @[Mux.scala 27:72]
|
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wire _T_22906 = bht_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_204; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23214 = _T_22906 ? bht_bank_rd_data_out_1_204 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23469 = _T_23468 | _T_23214; // @[Mux.scala 27:72]
|
|
wire _T_22908 = bht_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_205; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23215 = _T_22908 ? bht_bank_rd_data_out_1_205 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23470 = _T_23469 | _T_23215; // @[Mux.scala 27:72]
|
|
wire _T_22910 = bht_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_206; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23216 = _T_22910 ? bht_bank_rd_data_out_1_206 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23471 = _T_23470 | _T_23216; // @[Mux.scala 27:72]
|
|
wire _T_22912 = bht_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_207; // @[Reg.scala 27:20]
|
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wire [1:0] _T_23217 = _T_22912 ? bht_bank_rd_data_out_1_207 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23472 = _T_23471 | _T_23217; // @[Mux.scala 27:72]
|
|
wire _T_22914 = bht_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_208; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23218 = _T_22914 ? bht_bank_rd_data_out_1_208 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_23473 = _T_23472 | _T_23218; // @[Mux.scala 27:72]
|
|
wire _T_22916 = bht_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 530:79]
|
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reg [1:0] bht_bank_rd_data_out_1_209; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23219 = _T_22916 ? bht_bank_rd_data_out_1_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23474 = _T_23473 | _T_23219; // @[Mux.scala 27:72]
|
|
wire _T_22918 = bht_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_210; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23220 = _T_22918 ? bht_bank_rd_data_out_1_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23475 = _T_23474 | _T_23220; // @[Mux.scala 27:72]
|
|
wire _T_22920 = bht_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_211; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23221 = _T_22920 ? bht_bank_rd_data_out_1_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23476 = _T_23475 | _T_23221; // @[Mux.scala 27:72]
|
|
wire _T_22922 = bht_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_212; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23222 = _T_22922 ? bht_bank_rd_data_out_1_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23477 = _T_23476 | _T_23222; // @[Mux.scala 27:72]
|
|
wire _T_22924 = bht_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_213; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23223 = _T_22924 ? bht_bank_rd_data_out_1_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23478 = _T_23477 | _T_23223; // @[Mux.scala 27:72]
|
|
wire _T_22926 = bht_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_214; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23224 = _T_22926 ? bht_bank_rd_data_out_1_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23479 = _T_23478 | _T_23224; // @[Mux.scala 27:72]
|
|
wire _T_22928 = bht_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_215; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23225 = _T_22928 ? bht_bank_rd_data_out_1_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23480 = _T_23479 | _T_23225; // @[Mux.scala 27:72]
|
|
wire _T_22930 = bht_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_216; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23226 = _T_22930 ? bht_bank_rd_data_out_1_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23481 = _T_23480 | _T_23226; // @[Mux.scala 27:72]
|
|
wire _T_22932 = bht_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_217; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23227 = _T_22932 ? bht_bank_rd_data_out_1_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23482 = _T_23481 | _T_23227; // @[Mux.scala 27:72]
|
|
wire _T_22934 = bht_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_218; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23228 = _T_22934 ? bht_bank_rd_data_out_1_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23483 = _T_23482 | _T_23228; // @[Mux.scala 27:72]
|
|
wire _T_22936 = bht_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_219; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23229 = _T_22936 ? bht_bank_rd_data_out_1_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23484 = _T_23483 | _T_23229; // @[Mux.scala 27:72]
|
|
wire _T_22938 = bht_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_220; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23230 = _T_22938 ? bht_bank_rd_data_out_1_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23485 = _T_23484 | _T_23230; // @[Mux.scala 27:72]
|
|
wire _T_22940 = bht_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_221; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23231 = _T_22940 ? bht_bank_rd_data_out_1_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23486 = _T_23485 | _T_23231; // @[Mux.scala 27:72]
|
|
wire _T_22942 = bht_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_222; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23232 = _T_22942 ? bht_bank_rd_data_out_1_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23487 = _T_23486 | _T_23232; // @[Mux.scala 27:72]
|
|
wire _T_22944 = bht_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_223; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23233 = _T_22944 ? bht_bank_rd_data_out_1_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23488 = _T_23487 | _T_23233; // @[Mux.scala 27:72]
|
|
wire _T_22946 = bht_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_224; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23234 = _T_22946 ? bht_bank_rd_data_out_1_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23489 = _T_23488 | _T_23234; // @[Mux.scala 27:72]
|
|
wire _T_22948 = bht_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_225; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23235 = _T_22948 ? bht_bank_rd_data_out_1_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23490 = _T_23489 | _T_23235; // @[Mux.scala 27:72]
|
|
wire _T_22950 = bht_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_226; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23236 = _T_22950 ? bht_bank_rd_data_out_1_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23491 = _T_23490 | _T_23236; // @[Mux.scala 27:72]
|
|
wire _T_22952 = bht_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_227; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23237 = _T_22952 ? bht_bank_rd_data_out_1_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23492 = _T_23491 | _T_23237; // @[Mux.scala 27:72]
|
|
wire _T_22954 = bht_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_228; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23238 = _T_22954 ? bht_bank_rd_data_out_1_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23493 = _T_23492 | _T_23238; // @[Mux.scala 27:72]
|
|
wire _T_22956 = bht_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_229; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23239 = _T_22956 ? bht_bank_rd_data_out_1_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23494 = _T_23493 | _T_23239; // @[Mux.scala 27:72]
|
|
wire _T_22958 = bht_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_230; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23240 = _T_22958 ? bht_bank_rd_data_out_1_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23495 = _T_23494 | _T_23240; // @[Mux.scala 27:72]
|
|
wire _T_22960 = bht_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_231; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23241 = _T_22960 ? bht_bank_rd_data_out_1_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23496 = _T_23495 | _T_23241; // @[Mux.scala 27:72]
|
|
wire _T_22962 = bht_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_232; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23242 = _T_22962 ? bht_bank_rd_data_out_1_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23497 = _T_23496 | _T_23242; // @[Mux.scala 27:72]
|
|
wire _T_22964 = bht_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_233; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23243 = _T_22964 ? bht_bank_rd_data_out_1_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23498 = _T_23497 | _T_23243; // @[Mux.scala 27:72]
|
|
wire _T_22966 = bht_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_234; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23244 = _T_22966 ? bht_bank_rd_data_out_1_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23499 = _T_23498 | _T_23244; // @[Mux.scala 27:72]
|
|
wire _T_22968 = bht_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_235; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23245 = _T_22968 ? bht_bank_rd_data_out_1_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23500 = _T_23499 | _T_23245; // @[Mux.scala 27:72]
|
|
wire _T_22970 = bht_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_236; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23246 = _T_22970 ? bht_bank_rd_data_out_1_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23501 = _T_23500 | _T_23246; // @[Mux.scala 27:72]
|
|
wire _T_22972 = bht_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_237; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23247 = _T_22972 ? bht_bank_rd_data_out_1_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23502 = _T_23501 | _T_23247; // @[Mux.scala 27:72]
|
|
wire _T_22974 = bht_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_238; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23248 = _T_22974 ? bht_bank_rd_data_out_1_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23503 = _T_23502 | _T_23248; // @[Mux.scala 27:72]
|
|
wire _T_22976 = bht_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_239; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23249 = _T_22976 ? bht_bank_rd_data_out_1_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23504 = _T_23503 | _T_23249; // @[Mux.scala 27:72]
|
|
wire _T_22978 = bht_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_240; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23250 = _T_22978 ? bht_bank_rd_data_out_1_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23505 = _T_23504 | _T_23250; // @[Mux.scala 27:72]
|
|
wire _T_22980 = bht_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_241; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23251 = _T_22980 ? bht_bank_rd_data_out_1_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23506 = _T_23505 | _T_23251; // @[Mux.scala 27:72]
|
|
wire _T_22982 = bht_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_242; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23252 = _T_22982 ? bht_bank_rd_data_out_1_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23507 = _T_23506 | _T_23252; // @[Mux.scala 27:72]
|
|
wire _T_22984 = bht_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_243; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23253 = _T_22984 ? bht_bank_rd_data_out_1_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23508 = _T_23507 | _T_23253; // @[Mux.scala 27:72]
|
|
wire _T_22986 = bht_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_244; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23254 = _T_22986 ? bht_bank_rd_data_out_1_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23509 = _T_23508 | _T_23254; // @[Mux.scala 27:72]
|
|
wire _T_22988 = bht_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_245; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23255 = _T_22988 ? bht_bank_rd_data_out_1_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23510 = _T_23509 | _T_23255; // @[Mux.scala 27:72]
|
|
wire _T_22990 = bht_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_246; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23256 = _T_22990 ? bht_bank_rd_data_out_1_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23511 = _T_23510 | _T_23256; // @[Mux.scala 27:72]
|
|
wire _T_22992 = bht_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_247; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23257 = _T_22992 ? bht_bank_rd_data_out_1_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23512 = _T_23511 | _T_23257; // @[Mux.scala 27:72]
|
|
wire _T_22994 = bht_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_248; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23258 = _T_22994 ? bht_bank_rd_data_out_1_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23513 = _T_23512 | _T_23258; // @[Mux.scala 27:72]
|
|
wire _T_22996 = bht_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_249; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23259 = _T_22996 ? bht_bank_rd_data_out_1_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23514 = _T_23513 | _T_23259; // @[Mux.scala 27:72]
|
|
wire _T_22998 = bht_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_250; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23260 = _T_22998 ? bht_bank_rd_data_out_1_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23515 = _T_23514 | _T_23260; // @[Mux.scala 27:72]
|
|
wire _T_23000 = bht_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_251; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23261 = _T_23000 ? bht_bank_rd_data_out_1_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23516 = _T_23515 | _T_23261; // @[Mux.scala 27:72]
|
|
wire _T_23002 = bht_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_252; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23262 = _T_23002 ? bht_bank_rd_data_out_1_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23517 = _T_23516 | _T_23262; // @[Mux.scala 27:72]
|
|
wire _T_23004 = bht_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_253; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23263 = _T_23004 ? bht_bank_rd_data_out_1_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23518 = _T_23517 | _T_23263; // @[Mux.scala 27:72]
|
|
wire _T_23006 = bht_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_254; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23264 = _T_23006 ? bht_bank_rd_data_out_1_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_23519 = _T_23518 | _T_23264; // @[Mux.scala 27:72]
|
|
wire _T_23008 = bht_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 530:79]
|
|
reg [1:0] bht_bank_rd_data_out_1_255; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_23265 = _T_23008 ? bht_bank_rd_data_out_1_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank1_rd_data_f = _T_23519 | _T_23265; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_279 = _T_162 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [9:0] _T_611 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] bht_rd_addr_hashed_p1_f = _T_611[9:2] ^ fghr; // @[lib.scala 62:35]
|
|
wire _T_23522 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24034 = _T_23522 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_23524 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24035 = _T_23524 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24290 = _T_24034 | _T_24035; // @[Mux.scala 27:72]
|
|
wire _T_23526 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24036 = _T_23526 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24291 = _T_24290 | _T_24036; // @[Mux.scala 27:72]
|
|
wire _T_23528 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24037 = _T_23528 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24292 = _T_24291 | _T_24037; // @[Mux.scala 27:72]
|
|
wire _T_23530 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24038 = _T_23530 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24293 = _T_24292 | _T_24038; // @[Mux.scala 27:72]
|
|
wire _T_23532 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24039 = _T_23532 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24294 = _T_24293 | _T_24039; // @[Mux.scala 27:72]
|
|
wire _T_23534 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24040 = _T_23534 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24295 = _T_24294 | _T_24040; // @[Mux.scala 27:72]
|
|
wire _T_23536 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24041 = _T_23536 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24296 = _T_24295 | _T_24041; // @[Mux.scala 27:72]
|
|
wire _T_23538 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24042 = _T_23538 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24297 = _T_24296 | _T_24042; // @[Mux.scala 27:72]
|
|
wire _T_23540 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24043 = _T_23540 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24298 = _T_24297 | _T_24043; // @[Mux.scala 27:72]
|
|
wire _T_23542 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20]
|
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wire [1:0] _T_24044 = _T_23542 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24299 = _T_24298 | _T_24044; // @[Mux.scala 27:72]
|
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wire _T_23544 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24045 = _T_23544 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24300 = _T_24299 | _T_24045; // @[Mux.scala 27:72]
|
|
wire _T_23546 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24046 = _T_23546 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24301 = _T_24300 | _T_24046; // @[Mux.scala 27:72]
|
|
wire _T_23548 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24047 = _T_23548 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24302 = _T_24301 | _T_24047; // @[Mux.scala 27:72]
|
|
wire _T_23550 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24048 = _T_23550 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24303 = _T_24302 | _T_24048; // @[Mux.scala 27:72]
|
|
wire _T_23552 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24049 = _T_23552 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24304 = _T_24303 | _T_24049; // @[Mux.scala 27:72]
|
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wire _T_23554 = bht_rd_addr_hashed_p1_f == 8'h10; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_16; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24050 = _T_23554 ? bht_bank_rd_data_out_0_16 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24305 = _T_24304 | _T_24050; // @[Mux.scala 27:72]
|
|
wire _T_23556 = bht_rd_addr_hashed_p1_f == 8'h11; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_17; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24051 = _T_23556 ? bht_bank_rd_data_out_0_17 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24306 = _T_24305 | _T_24051; // @[Mux.scala 27:72]
|
|
wire _T_23558 = bht_rd_addr_hashed_p1_f == 8'h12; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_18; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24052 = _T_23558 ? bht_bank_rd_data_out_0_18 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24307 = _T_24306 | _T_24052; // @[Mux.scala 27:72]
|
|
wire _T_23560 = bht_rd_addr_hashed_p1_f == 8'h13; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_19; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24053 = _T_23560 ? bht_bank_rd_data_out_0_19 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24308 = _T_24307 | _T_24053; // @[Mux.scala 27:72]
|
|
wire _T_23562 = bht_rd_addr_hashed_p1_f == 8'h14; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_20; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24054 = _T_23562 ? bht_bank_rd_data_out_0_20 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24309 = _T_24308 | _T_24054; // @[Mux.scala 27:72]
|
|
wire _T_23564 = bht_rd_addr_hashed_p1_f == 8'h15; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_21; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24055 = _T_23564 ? bht_bank_rd_data_out_0_21 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24310 = _T_24309 | _T_24055; // @[Mux.scala 27:72]
|
|
wire _T_23566 = bht_rd_addr_hashed_p1_f == 8'h16; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_22; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24056 = _T_23566 ? bht_bank_rd_data_out_0_22 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24311 = _T_24310 | _T_24056; // @[Mux.scala 27:72]
|
|
wire _T_23568 = bht_rd_addr_hashed_p1_f == 8'h17; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_23; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24057 = _T_23568 ? bht_bank_rd_data_out_0_23 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24312 = _T_24311 | _T_24057; // @[Mux.scala 27:72]
|
|
wire _T_23570 = bht_rd_addr_hashed_p1_f == 8'h18; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_24; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24058 = _T_23570 ? bht_bank_rd_data_out_0_24 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24313 = _T_24312 | _T_24058; // @[Mux.scala 27:72]
|
|
wire _T_23572 = bht_rd_addr_hashed_p1_f == 8'h19; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_25; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24059 = _T_23572 ? bht_bank_rd_data_out_0_25 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24314 = _T_24313 | _T_24059; // @[Mux.scala 27:72]
|
|
wire _T_23574 = bht_rd_addr_hashed_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_26; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24060 = _T_23574 ? bht_bank_rd_data_out_0_26 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24315 = _T_24314 | _T_24060; // @[Mux.scala 27:72]
|
|
wire _T_23576 = bht_rd_addr_hashed_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_27; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24061 = _T_23576 ? bht_bank_rd_data_out_0_27 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24316 = _T_24315 | _T_24061; // @[Mux.scala 27:72]
|
|
wire _T_23578 = bht_rd_addr_hashed_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_28; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24062 = _T_23578 ? bht_bank_rd_data_out_0_28 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24317 = _T_24316 | _T_24062; // @[Mux.scala 27:72]
|
|
wire _T_23580 = bht_rd_addr_hashed_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_29; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24063 = _T_23580 ? bht_bank_rd_data_out_0_29 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24318 = _T_24317 | _T_24063; // @[Mux.scala 27:72]
|
|
wire _T_23582 = bht_rd_addr_hashed_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_30; // @[Reg.scala 27:20]
|
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wire [1:0] _T_24064 = _T_23582 ? bht_bank_rd_data_out_0_30 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24319 = _T_24318 | _T_24064; // @[Mux.scala 27:72]
|
|
wire _T_23584 = bht_rd_addr_hashed_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_31; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24065 = _T_23584 ? bht_bank_rd_data_out_0_31 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24320 = _T_24319 | _T_24065; // @[Mux.scala 27:72]
|
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wire _T_23586 = bht_rd_addr_hashed_p1_f == 8'h20; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_32; // @[Reg.scala 27:20]
|
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wire [1:0] _T_24066 = _T_23586 ? bht_bank_rd_data_out_0_32 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24321 = _T_24320 | _T_24066; // @[Mux.scala 27:72]
|
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wire _T_23588 = bht_rd_addr_hashed_p1_f == 8'h21; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_33; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24067 = _T_23588 ? bht_bank_rd_data_out_0_33 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24322 = _T_24321 | _T_24067; // @[Mux.scala 27:72]
|
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wire _T_23590 = bht_rd_addr_hashed_p1_f == 8'h22; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_34; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24068 = _T_23590 ? bht_bank_rd_data_out_0_34 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24323 = _T_24322 | _T_24068; // @[Mux.scala 27:72]
|
|
wire _T_23592 = bht_rd_addr_hashed_p1_f == 8'h23; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_35; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24069 = _T_23592 ? bht_bank_rd_data_out_0_35 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24324 = _T_24323 | _T_24069; // @[Mux.scala 27:72]
|
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wire _T_23594 = bht_rd_addr_hashed_p1_f == 8'h24; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_36; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24070 = _T_23594 ? bht_bank_rd_data_out_0_36 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_24325 = _T_24324 | _T_24070; // @[Mux.scala 27:72]
|
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wire _T_23596 = bht_rd_addr_hashed_p1_f == 8'h25; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_37; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24071 = _T_23596 ? bht_bank_rd_data_out_0_37 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24326 = _T_24325 | _T_24071; // @[Mux.scala 27:72]
|
|
wire _T_23598 = bht_rd_addr_hashed_p1_f == 8'h26; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_38; // @[Reg.scala 27:20]
|
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wire [1:0] _T_24072 = _T_23598 ? bht_bank_rd_data_out_0_38 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24327 = _T_24326 | _T_24072; // @[Mux.scala 27:72]
|
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wire _T_23600 = bht_rd_addr_hashed_p1_f == 8'h27; // @[ifu_bp_ctl.scala 531:85]
|
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reg [1:0] bht_bank_rd_data_out_0_39; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24073 = _T_23600 ? bht_bank_rd_data_out_0_39 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24328 = _T_24327 | _T_24073; // @[Mux.scala 27:72]
|
|
wire _T_23602 = bht_rd_addr_hashed_p1_f == 8'h28; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_40; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24074 = _T_23602 ? bht_bank_rd_data_out_0_40 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24329 = _T_24328 | _T_24074; // @[Mux.scala 27:72]
|
|
wire _T_23604 = bht_rd_addr_hashed_p1_f == 8'h29; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_41; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24075 = _T_23604 ? bht_bank_rd_data_out_0_41 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_24330 = _T_24329 | _T_24075; // @[Mux.scala 27:72]
|
|
wire _T_23606 = bht_rd_addr_hashed_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_42; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24076 = _T_23606 ? bht_bank_rd_data_out_0_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24331 = _T_24330 | _T_24076; // @[Mux.scala 27:72]
|
|
wire _T_23608 = bht_rd_addr_hashed_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_43; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24077 = _T_23608 ? bht_bank_rd_data_out_0_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24332 = _T_24331 | _T_24077; // @[Mux.scala 27:72]
|
|
wire _T_23610 = bht_rd_addr_hashed_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_44; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24078 = _T_23610 ? bht_bank_rd_data_out_0_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24333 = _T_24332 | _T_24078; // @[Mux.scala 27:72]
|
|
wire _T_23612 = bht_rd_addr_hashed_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_45; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24079 = _T_23612 ? bht_bank_rd_data_out_0_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24334 = _T_24333 | _T_24079; // @[Mux.scala 27:72]
|
|
wire _T_23614 = bht_rd_addr_hashed_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_46; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24080 = _T_23614 ? bht_bank_rd_data_out_0_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24335 = _T_24334 | _T_24080; // @[Mux.scala 27:72]
|
|
wire _T_23616 = bht_rd_addr_hashed_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_47; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24081 = _T_23616 ? bht_bank_rd_data_out_0_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24336 = _T_24335 | _T_24081; // @[Mux.scala 27:72]
|
|
wire _T_23618 = bht_rd_addr_hashed_p1_f == 8'h30; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_48; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24082 = _T_23618 ? bht_bank_rd_data_out_0_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24337 = _T_24336 | _T_24082; // @[Mux.scala 27:72]
|
|
wire _T_23620 = bht_rd_addr_hashed_p1_f == 8'h31; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_49; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24083 = _T_23620 ? bht_bank_rd_data_out_0_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24338 = _T_24337 | _T_24083; // @[Mux.scala 27:72]
|
|
wire _T_23622 = bht_rd_addr_hashed_p1_f == 8'h32; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_50; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24084 = _T_23622 ? bht_bank_rd_data_out_0_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24339 = _T_24338 | _T_24084; // @[Mux.scala 27:72]
|
|
wire _T_23624 = bht_rd_addr_hashed_p1_f == 8'h33; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_51; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24085 = _T_23624 ? bht_bank_rd_data_out_0_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24340 = _T_24339 | _T_24085; // @[Mux.scala 27:72]
|
|
wire _T_23626 = bht_rd_addr_hashed_p1_f == 8'h34; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_52; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24086 = _T_23626 ? bht_bank_rd_data_out_0_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24341 = _T_24340 | _T_24086; // @[Mux.scala 27:72]
|
|
wire _T_23628 = bht_rd_addr_hashed_p1_f == 8'h35; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_53; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24087 = _T_23628 ? bht_bank_rd_data_out_0_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24342 = _T_24341 | _T_24087; // @[Mux.scala 27:72]
|
|
wire _T_23630 = bht_rd_addr_hashed_p1_f == 8'h36; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_54; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24088 = _T_23630 ? bht_bank_rd_data_out_0_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24343 = _T_24342 | _T_24088; // @[Mux.scala 27:72]
|
|
wire _T_23632 = bht_rd_addr_hashed_p1_f == 8'h37; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_55; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24089 = _T_23632 ? bht_bank_rd_data_out_0_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24344 = _T_24343 | _T_24089; // @[Mux.scala 27:72]
|
|
wire _T_23634 = bht_rd_addr_hashed_p1_f == 8'h38; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_56; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24090 = _T_23634 ? bht_bank_rd_data_out_0_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24345 = _T_24344 | _T_24090; // @[Mux.scala 27:72]
|
|
wire _T_23636 = bht_rd_addr_hashed_p1_f == 8'h39; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_57; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24091 = _T_23636 ? bht_bank_rd_data_out_0_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24346 = _T_24345 | _T_24091; // @[Mux.scala 27:72]
|
|
wire _T_23638 = bht_rd_addr_hashed_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_58; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24092 = _T_23638 ? bht_bank_rd_data_out_0_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24347 = _T_24346 | _T_24092; // @[Mux.scala 27:72]
|
|
wire _T_23640 = bht_rd_addr_hashed_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_59; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24093 = _T_23640 ? bht_bank_rd_data_out_0_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24348 = _T_24347 | _T_24093; // @[Mux.scala 27:72]
|
|
wire _T_23642 = bht_rd_addr_hashed_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_60; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24094 = _T_23642 ? bht_bank_rd_data_out_0_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24349 = _T_24348 | _T_24094; // @[Mux.scala 27:72]
|
|
wire _T_23644 = bht_rd_addr_hashed_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_61; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24095 = _T_23644 ? bht_bank_rd_data_out_0_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24350 = _T_24349 | _T_24095; // @[Mux.scala 27:72]
|
|
wire _T_23646 = bht_rd_addr_hashed_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_62; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24096 = _T_23646 ? bht_bank_rd_data_out_0_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24351 = _T_24350 | _T_24096; // @[Mux.scala 27:72]
|
|
wire _T_23648 = bht_rd_addr_hashed_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_63; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24097 = _T_23648 ? bht_bank_rd_data_out_0_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24352 = _T_24351 | _T_24097; // @[Mux.scala 27:72]
|
|
wire _T_23650 = bht_rd_addr_hashed_p1_f == 8'h40; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_64; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24098 = _T_23650 ? bht_bank_rd_data_out_0_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24353 = _T_24352 | _T_24098; // @[Mux.scala 27:72]
|
|
wire _T_23652 = bht_rd_addr_hashed_p1_f == 8'h41; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_65; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24099 = _T_23652 ? bht_bank_rd_data_out_0_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24354 = _T_24353 | _T_24099; // @[Mux.scala 27:72]
|
|
wire _T_23654 = bht_rd_addr_hashed_p1_f == 8'h42; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_66; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24100 = _T_23654 ? bht_bank_rd_data_out_0_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24355 = _T_24354 | _T_24100; // @[Mux.scala 27:72]
|
|
wire _T_23656 = bht_rd_addr_hashed_p1_f == 8'h43; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_67; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24101 = _T_23656 ? bht_bank_rd_data_out_0_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24356 = _T_24355 | _T_24101; // @[Mux.scala 27:72]
|
|
wire _T_23658 = bht_rd_addr_hashed_p1_f == 8'h44; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_68; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24102 = _T_23658 ? bht_bank_rd_data_out_0_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24357 = _T_24356 | _T_24102; // @[Mux.scala 27:72]
|
|
wire _T_23660 = bht_rd_addr_hashed_p1_f == 8'h45; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_69; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24103 = _T_23660 ? bht_bank_rd_data_out_0_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24358 = _T_24357 | _T_24103; // @[Mux.scala 27:72]
|
|
wire _T_23662 = bht_rd_addr_hashed_p1_f == 8'h46; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_70; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24104 = _T_23662 ? bht_bank_rd_data_out_0_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24359 = _T_24358 | _T_24104; // @[Mux.scala 27:72]
|
|
wire _T_23664 = bht_rd_addr_hashed_p1_f == 8'h47; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_71; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24105 = _T_23664 ? bht_bank_rd_data_out_0_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24360 = _T_24359 | _T_24105; // @[Mux.scala 27:72]
|
|
wire _T_23666 = bht_rd_addr_hashed_p1_f == 8'h48; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_72; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24106 = _T_23666 ? bht_bank_rd_data_out_0_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24361 = _T_24360 | _T_24106; // @[Mux.scala 27:72]
|
|
wire _T_23668 = bht_rd_addr_hashed_p1_f == 8'h49; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_73; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24107 = _T_23668 ? bht_bank_rd_data_out_0_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24362 = _T_24361 | _T_24107; // @[Mux.scala 27:72]
|
|
wire _T_23670 = bht_rd_addr_hashed_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_74; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24108 = _T_23670 ? bht_bank_rd_data_out_0_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24363 = _T_24362 | _T_24108; // @[Mux.scala 27:72]
|
|
wire _T_23672 = bht_rd_addr_hashed_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_75; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24109 = _T_23672 ? bht_bank_rd_data_out_0_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24364 = _T_24363 | _T_24109; // @[Mux.scala 27:72]
|
|
wire _T_23674 = bht_rd_addr_hashed_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_76; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24110 = _T_23674 ? bht_bank_rd_data_out_0_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24365 = _T_24364 | _T_24110; // @[Mux.scala 27:72]
|
|
wire _T_23676 = bht_rd_addr_hashed_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_77; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24111 = _T_23676 ? bht_bank_rd_data_out_0_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24366 = _T_24365 | _T_24111; // @[Mux.scala 27:72]
|
|
wire _T_23678 = bht_rd_addr_hashed_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_78; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24112 = _T_23678 ? bht_bank_rd_data_out_0_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24367 = _T_24366 | _T_24112; // @[Mux.scala 27:72]
|
|
wire _T_23680 = bht_rd_addr_hashed_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_79; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24113 = _T_23680 ? bht_bank_rd_data_out_0_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24368 = _T_24367 | _T_24113; // @[Mux.scala 27:72]
|
|
wire _T_23682 = bht_rd_addr_hashed_p1_f == 8'h50; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_80; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24114 = _T_23682 ? bht_bank_rd_data_out_0_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24369 = _T_24368 | _T_24114; // @[Mux.scala 27:72]
|
|
wire _T_23684 = bht_rd_addr_hashed_p1_f == 8'h51; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_81; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24115 = _T_23684 ? bht_bank_rd_data_out_0_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24370 = _T_24369 | _T_24115; // @[Mux.scala 27:72]
|
|
wire _T_23686 = bht_rd_addr_hashed_p1_f == 8'h52; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_82; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24116 = _T_23686 ? bht_bank_rd_data_out_0_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24371 = _T_24370 | _T_24116; // @[Mux.scala 27:72]
|
|
wire _T_23688 = bht_rd_addr_hashed_p1_f == 8'h53; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_83; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24117 = _T_23688 ? bht_bank_rd_data_out_0_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24372 = _T_24371 | _T_24117; // @[Mux.scala 27:72]
|
|
wire _T_23690 = bht_rd_addr_hashed_p1_f == 8'h54; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_84; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24118 = _T_23690 ? bht_bank_rd_data_out_0_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24373 = _T_24372 | _T_24118; // @[Mux.scala 27:72]
|
|
wire _T_23692 = bht_rd_addr_hashed_p1_f == 8'h55; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_85; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24119 = _T_23692 ? bht_bank_rd_data_out_0_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24374 = _T_24373 | _T_24119; // @[Mux.scala 27:72]
|
|
wire _T_23694 = bht_rd_addr_hashed_p1_f == 8'h56; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_86; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24120 = _T_23694 ? bht_bank_rd_data_out_0_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24375 = _T_24374 | _T_24120; // @[Mux.scala 27:72]
|
|
wire _T_23696 = bht_rd_addr_hashed_p1_f == 8'h57; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_87; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24121 = _T_23696 ? bht_bank_rd_data_out_0_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24376 = _T_24375 | _T_24121; // @[Mux.scala 27:72]
|
|
wire _T_23698 = bht_rd_addr_hashed_p1_f == 8'h58; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_88; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24122 = _T_23698 ? bht_bank_rd_data_out_0_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24377 = _T_24376 | _T_24122; // @[Mux.scala 27:72]
|
|
wire _T_23700 = bht_rd_addr_hashed_p1_f == 8'h59; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_89; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24123 = _T_23700 ? bht_bank_rd_data_out_0_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24378 = _T_24377 | _T_24123; // @[Mux.scala 27:72]
|
|
wire _T_23702 = bht_rd_addr_hashed_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_90; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24124 = _T_23702 ? bht_bank_rd_data_out_0_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24379 = _T_24378 | _T_24124; // @[Mux.scala 27:72]
|
|
wire _T_23704 = bht_rd_addr_hashed_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_91; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24125 = _T_23704 ? bht_bank_rd_data_out_0_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24380 = _T_24379 | _T_24125; // @[Mux.scala 27:72]
|
|
wire _T_23706 = bht_rd_addr_hashed_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_92; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24126 = _T_23706 ? bht_bank_rd_data_out_0_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24381 = _T_24380 | _T_24126; // @[Mux.scala 27:72]
|
|
wire _T_23708 = bht_rd_addr_hashed_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_93; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24127 = _T_23708 ? bht_bank_rd_data_out_0_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24382 = _T_24381 | _T_24127; // @[Mux.scala 27:72]
|
|
wire _T_23710 = bht_rd_addr_hashed_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_94; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24128 = _T_23710 ? bht_bank_rd_data_out_0_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24383 = _T_24382 | _T_24128; // @[Mux.scala 27:72]
|
|
wire _T_23712 = bht_rd_addr_hashed_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_95; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24129 = _T_23712 ? bht_bank_rd_data_out_0_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24384 = _T_24383 | _T_24129; // @[Mux.scala 27:72]
|
|
wire _T_23714 = bht_rd_addr_hashed_p1_f == 8'h60; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_96; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24130 = _T_23714 ? bht_bank_rd_data_out_0_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24385 = _T_24384 | _T_24130; // @[Mux.scala 27:72]
|
|
wire _T_23716 = bht_rd_addr_hashed_p1_f == 8'h61; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_97; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24131 = _T_23716 ? bht_bank_rd_data_out_0_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24386 = _T_24385 | _T_24131; // @[Mux.scala 27:72]
|
|
wire _T_23718 = bht_rd_addr_hashed_p1_f == 8'h62; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_98; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24132 = _T_23718 ? bht_bank_rd_data_out_0_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24387 = _T_24386 | _T_24132; // @[Mux.scala 27:72]
|
|
wire _T_23720 = bht_rd_addr_hashed_p1_f == 8'h63; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_99; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24133 = _T_23720 ? bht_bank_rd_data_out_0_99 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24388 = _T_24387 | _T_24133; // @[Mux.scala 27:72]
|
|
wire _T_23722 = bht_rd_addr_hashed_p1_f == 8'h64; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_100; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24134 = _T_23722 ? bht_bank_rd_data_out_0_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24389 = _T_24388 | _T_24134; // @[Mux.scala 27:72]
|
|
wire _T_23724 = bht_rd_addr_hashed_p1_f == 8'h65; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_101; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24135 = _T_23724 ? bht_bank_rd_data_out_0_101 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24390 = _T_24389 | _T_24135; // @[Mux.scala 27:72]
|
|
wire _T_23726 = bht_rd_addr_hashed_p1_f == 8'h66; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_102; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24136 = _T_23726 ? bht_bank_rd_data_out_0_102 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24391 = _T_24390 | _T_24136; // @[Mux.scala 27:72]
|
|
wire _T_23728 = bht_rd_addr_hashed_p1_f == 8'h67; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_103; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24137 = _T_23728 ? bht_bank_rd_data_out_0_103 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24392 = _T_24391 | _T_24137; // @[Mux.scala 27:72]
|
|
wire _T_23730 = bht_rd_addr_hashed_p1_f == 8'h68; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_104; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24138 = _T_23730 ? bht_bank_rd_data_out_0_104 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24393 = _T_24392 | _T_24138; // @[Mux.scala 27:72]
|
|
wire _T_23732 = bht_rd_addr_hashed_p1_f == 8'h69; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_105; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24139 = _T_23732 ? bht_bank_rd_data_out_0_105 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24394 = _T_24393 | _T_24139; // @[Mux.scala 27:72]
|
|
wire _T_23734 = bht_rd_addr_hashed_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_106; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24140 = _T_23734 ? bht_bank_rd_data_out_0_106 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24395 = _T_24394 | _T_24140; // @[Mux.scala 27:72]
|
|
wire _T_23736 = bht_rd_addr_hashed_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_107; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24141 = _T_23736 ? bht_bank_rd_data_out_0_107 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24396 = _T_24395 | _T_24141; // @[Mux.scala 27:72]
|
|
wire _T_23738 = bht_rd_addr_hashed_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_108; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24142 = _T_23738 ? bht_bank_rd_data_out_0_108 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24397 = _T_24396 | _T_24142; // @[Mux.scala 27:72]
|
|
wire _T_23740 = bht_rd_addr_hashed_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_109; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24143 = _T_23740 ? bht_bank_rd_data_out_0_109 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24398 = _T_24397 | _T_24143; // @[Mux.scala 27:72]
|
|
wire _T_23742 = bht_rd_addr_hashed_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_110; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24144 = _T_23742 ? bht_bank_rd_data_out_0_110 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24399 = _T_24398 | _T_24144; // @[Mux.scala 27:72]
|
|
wire _T_23744 = bht_rd_addr_hashed_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_111; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24145 = _T_23744 ? bht_bank_rd_data_out_0_111 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24400 = _T_24399 | _T_24145; // @[Mux.scala 27:72]
|
|
wire _T_23746 = bht_rd_addr_hashed_p1_f == 8'h70; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_112; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24146 = _T_23746 ? bht_bank_rd_data_out_0_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24401 = _T_24400 | _T_24146; // @[Mux.scala 27:72]
|
|
wire _T_23748 = bht_rd_addr_hashed_p1_f == 8'h71; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_113; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24147 = _T_23748 ? bht_bank_rd_data_out_0_113 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24402 = _T_24401 | _T_24147; // @[Mux.scala 27:72]
|
|
wire _T_23750 = bht_rd_addr_hashed_p1_f == 8'h72; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_114; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24148 = _T_23750 ? bht_bank_rd_data_out_0_114 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24403 = _T_24402 | _T_24148; // @[Mux.scala 27:72]
|
|
wire _T_23752 = bht_rd_addr_hashed_p1_f == 8'h73; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_115; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24149 = _T_23752 ? bht_bank_rd_data_out_0_115 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24404 = _T_24403 | _T_24149; // @[Mux.scala 27:72]
|
|
wire _T_23754 = bht_rd_addr_hashed_p1_f == 8'h74; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_116; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24150 = _T_23754 ? bht_bank_rd_data_out_0_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24405 = _T_24404 | _T_24150; // @[Mux.scala 27:72]
|
|
wire _T_23756 = bht_rd_addr_hashed_p1_f == 8'h75; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_117; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24151 = _T_23756 ? bht_bank_rd_data_out_0_117 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24406 = _T_24405 | _T_24151; // @[Mux.scala 27:72]
|
|
wire _T_23758 = bht_rd_addr_hashed_p1_f == 8'h76; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_118; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24152 = _T_23758 ? bht_bank_rd_data_out_0_118 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24407 = _T_24406 | _T_24152; // @[Mux.scala 27:72]
|
|
wire _T_23760 = bht_rd_addr_hashed_p1_f == 8'h77; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_119; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24153 = _T_23760 ? bht_bank_rd_data_out_0_119 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24408 = _T_24407 | _T_24153; // @[Mux.scala 27:72]
|
|
wire _T_23762 = bht_rd_addr_hashed_p1_f == 8'h78; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_120; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24154 = _T_23762 ? bht_bank_rd_data_out_0_120 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24409 = _T_24408 | _T_24154; // @[Mux.scala 27:72]
|
|
wire _T_23764 = bht_rd_addr_hashed_p1_f == 8'h79; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_121; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24155 = _T_23764 ? bht_bank_rd_data_out_0_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24410 = _T_24409 | _T_24155; // @[Mux.scala 27:72]
|
|
wire _T_23766 = bht_rd_addr_hashed_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_122; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24156 = _T_23766 ? bht_bank_rd_data_out_0_122 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24411 = _T_24410 | _T_24156; // @[Mux.scala 27:72]
|
|
wire _T_23768 = bht_rd_addr_hashed_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_123; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24157 = _T_23768 ? bht_bank_rd_data_out_0_123 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24412 = _T_24411 | _T_24157; // @[Mux.scala 27:72]
|
|
wire _T_23770 = bht_rd_addr_hashed_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_124; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24158 = _T_23770 ? bht_bank_rd_data_out_0_124 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24413 = _T_24412 | _T_24158; // @[Mux.scala 27:72]
|
|
wire _T_23772 = bht_rd_addr_hashed_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_125; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24159 = _T_23772 ? bht_bank_rd_data_out_0_125 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24414 = _T_24413 | _T_24159; // @[Mux.scala 27:72]
|
|
wire _T_23774 = bht_rd_addr_hashed_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_126; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24160 = _T_23774 ? bht_bank_rd_data_out_0_126 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24415 = _T_24414 | _T_24160; // @[Mux.scala 27:72]
|
|
wire _T_23776 = bht_rd_addr_hashed_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_127; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24161 = _T_23776 ? bht_bank_rd_data_out_0_127 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24416 = _T_24415 | _T_24161; // @[Mux.scala 27:72]
|
|
wire _T_23778 = bht_rd_addr_hashed_p1_f == 8'h80; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_128; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24162 = _T_23778 ? bht_bank_rd_data_out_0_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24417 = _T_24416 | _T_24162; // @[Mux.scala 27:72]
|
|
wire _T_23780 = bht_rd_addr_hashed_p1_f == 8'h81; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_129; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24163 = _T_23780 ? bht_bank_rd_data_out_0_129 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24418 = _T_24417 | _T_24163; // @[Mux.scala 27:72]
|
|
wire _T_23782 = bht_rd_addr_hashed_p1_f == 8'h82; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_130; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24164 = _T_23782 ? bht_bank_rd_data_out_0_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24419 = _T_24418 | _T_24164; // @[Mux.scala 27:72]
|
|
wire _T_23784 = bht_rd_addr_hashed_p1_f == 8'h83; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_131; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24165 = _T_23784 ? bht_bank_rd_data_out_0_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24420 = _T_24419 | _T_24165; // @[Mux.scala 27:72]
|
|
wire _T_23786 = bht_rd_addr_hashed_p1_f == 8'h84; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_132; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24166 = _T_23786 ? bht_bank_rd_data_out_0_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24421 = _T_24420 | _T_24166; // @[Mux.scala 27:72]
|
|
wire _T_23788 = bht_rd_addr_hashed_p1_f == 8'h85; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_133; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24167 = _T_23788 ? bht_bank_rd_data_out_0_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24422 = _T_24421 | _T_24167; // @[Mux.scala 27:72]
|
|
wire _T_23790 = bht_rd_addr_hashed_p1_f == 8'h86; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_134; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24168 = _T_23790 ? bht_bank_rd_data_out_0_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24423 = _T_24422 | _T_24168; // @[Mux.scala 27:72]
|
|
wire _T_23792 = bht_rd_addr_hashed_p1_f == 8'h87; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_135; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24169 = _T_23792 ? bht_bank_rd_data_out_0_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24424 = _T_24423 | _T_24169; // @[Mux.scala 27:72]
|
|
wire _T_23794 = bht_rd_addr_hashed_p1_f == 8'h88; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_136; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24170 = _T_23794 ? bht_bank_rd_data_out_0_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24425 = _T_24424 | _T_24170; // @[Mux.scala 27:72]
|
|
wire _T_23796 = bht_rd_addr_hashed_p1_f == 8'h89; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_137; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24171 = _T_23796 ? bht_bank_rd_data_out_0_137 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24426 = _T_24425 | _T_24171; // @[Mux.scala 27:72]
|
|
wire _T_23798 = bht_rd_addr_hashed_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_138; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24172 = _T_23798 ? bht_bank_rd_data_out_0_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24427 = _T_24426 | _T_24172; // @[Mux.scala 27:72]
|
|
wire _T_23800 = bht_rd_addr_hashed_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_139; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24173 = _T_23800 ? bht_bank_rd_data_out_0_139 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24428 = _T_24427 | _T_24173; // @[Mux.scala 27:72]
|
|
wire _T_23802 = bht_rd_addr_hashed_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_140; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24174 = _T_23802 ? bht_bank_rd_data_out_0_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24429 = _T_24428 | _T_24174; // @[Mux.scala 27:72]
|
|
wire _T_23804 = bht_rd_addr_hashed_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_141; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24175 = _T_23804 ? bht_bank_rd_data_out_0_141 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24430 = _T_24429 | _T_24175; // @[Mux.scala 27:72]
|
|
wire _T_23806 = bht_rd_addr_hashed_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_142; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24176 = _T_23806 ? bht_bank_rd_data_out_0_142 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24431 = _T_24430 | _T_24176; // @[Mux.scala 27:72]
|
|
wire _T_23808 = bht_rd_addr_hashed_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_143; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24177 = _T_23808 ? bht_bank_rd_data_out_0_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24432 = _T_24431 | _T_24177; // @[Mux.scala 27:72]
|
|
wire _T_23810 = bht_rd_addr_hashed_p1_f == 8'h90; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_144; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24178 = _T_23810 ? bht_bank_rd_data_out_0_144 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24433 = _T_24432 | _T_24178; // @[Mux.scala 27:72]
|
|
wire _T_23812 = bht_rd_addr_hashed_p1_f == 8'h91; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_145; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24179 = _T_23812 ? bht_bank_rd_data_out_0_145 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24434 = _T_24433 | _T_24179; // @[Mux.scala 27:72]
|
|
wire _T_23814 = bht_rd_addr_hashed_p1_f == 8'h92; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_146; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24180 = _T_23814 ? bht_bank_rd_data_out_0_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24435 = _T_24434 | _T_24180; // @[Mux.scala 27:72]
|
|
wire _T_23816 = bht_rd_addr_hashed_p1_f == 8'h93; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_147; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24181 = _T_23816 ? bht_bank_rd_data_out_0_147 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24436 = _T_24435 | _T_24181; // @[Mux.scala 27:72]
|
|
wire _T_23818 = bht_rd_addr_hashed_p1_f == 8'h94; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_148; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24182 = _T_23818 ? bht_bank_rd_data_out_0_148 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24437 = _T_24436 | _T_24182; // @[Mux.scala 27:72]
|
|
wire _T_23820 = bht_rd_addr_hashed_p1_f == 8'h95; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_149; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24183 = _T_23820 ? bht_bank_rd_data_out_0_149 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24438 = _T_24437 | _T_24183; // @[Mux.scala 27:72]
|
|
wire _T_23822 = bht_rd_addr_hashed_p1_f == 8'h96; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_150; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24184 = _T_23822 ? bht_bank_rd_data_out_0_150 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24439 = _T_24438 | _T_24184; // @[Mux.scala 27:72]
|
|
wire _T_23824 = bht_rd_addr_hashed_p1_f == 8'h97; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_151; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24185 = _T_23824 ? bht_bank_rd_data_out_0_151 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24440 = _T_24439 | _T_24185; // @[Mux.scala 27:72]
|
|
wire _T_23826 = bht_rd_addr_hashed_p1_f == 8'h98; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_152; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24186 = _T_23826 ? bht_bank_rd_data_out_0_152 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24441 = _T_24440 | _T_24186; // @[Mux.scala 27:72]
|
|
wire _T_23828 = bht_rd_addr_hashed_p1_f == 8'h99; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_153; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24187 = _T_23828 ? bht_bank_rd_data_out_0_153 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24442 = _T_24441 | _T_24187; // @[Mux.scala 27:72]
|
|
wire _T_23830 = bht_rd_addr_hashed_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_154; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24188 = _T_23830 ? bht_bank_rd_data_out_0_154 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24443 = _T_24442 | _T_24188; // @[Mux.scala 27:72]
|
|
wire _T_23832 = bht_rd_addr_hashed_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_155; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24189 = _T_23832 ? bht_bank_rd_data_out_0_155 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24444 = _T_24443 | _T_24189; // @[Mux.scala 27:72]
|
|
wire _T_23834 = bht_rd_addr_hashed_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_156; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24190 = _T_23834 ? bht_bank_rd_data_out_0_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24445 = _T_24444 | _T_24190; // @[Mux.scala 27:72]
|
|
wire _T_23836 = bht_rd_addr_hashed_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_157; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24191 = _T_23836 ? bht_bank_rd_data_out_0_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24446 = _T_24445 | _T_24191; // @[Mux.scala 27:72]
|
|
wire _T_23838 = bht_rd_addr_hashed_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_158; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24192 = _T_23838 ? bht_bank_rd_data_out_0_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24447 = _T_24446 | _T_24192; // @[Mux.scala 27:72]
|
|
wire _T_23840 = bht_rd_addr_hashed_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_159; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24193 = _T_23840 ? bht_bank_rd_data_out_0_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24448 = _T_24447 | _T_24193; // @[Mux.scala 27:72]
|
|
wire _T_23842 = bht_rd_addr_hashed_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_160; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24194 = _T_23842 ? bht_bank_rd_data_out_0_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24449 = _T_24448 | _T_24194; // @[Mux.scala 27:72]
|
|
wire _T_23844 = bht_rd_addr_hashed_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_161; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24195 = _T_23844 ? bht_bank_rd_data_out_0_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24450 = _T_24449 | _T_24195; // @[Mux.scala 27:72]
|
|
wire _T_23846 = bht_rd_addr_hashed_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_162; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24196 = _T_23846 ? bht_bank_rd_data_out_0_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24451 = _T_24450 | _T_24196; // @[Mux.scala 27:72]
|
|
wire _T_23848 = bht_rd_addr_hashed_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_163; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24197 = _T_23848 ? bht_bank_rd_data_out_0_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24452 = _T_24451 | _T_24197; // @[Mux.scala 27:72]
|
|
wire _T_23850 = bht_rd_addr_hashed_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_164; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24198 = _T_23850 ? bht_bank_rd_data_out_0_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24453 = _T_24452 | _T_24198; // @[Mux.scala 27:72]
|
|
wire _T_23852 = bht_rd_addr_hashed_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_165; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24199 = _T_23852 ? bht_bank_rd_data_out_0_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24454 = _T_24453 | _T_24199; // @[Mux.scala 27:72]
|
|
wire _T_23854 = bht_rd_addr_hashed_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_166; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24200 = _T_23854 ? bht_bank_rd_data_out_0_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24455 = _T_24454 | _T_24200; // @[Mux.scala 27:72]
|
|
wire _T_23856 = bht_rd_addr_hashed_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_167; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24201 = _T_23856 ? bht_bank_rd_data_out_0_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24456 = _T_24455 | _T_24201; // @[Mux.scala 27:72]
|
|
wire _T_23858 = bht_rd_addr_hashed_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_168; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24202 = _T_23858 ? bht_bank_rd_data_out_0_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24457 = _T_24456 | _T_24202; // @[Mux.scala 27:72]
|
|
wire _T_23860 = bht_rd_addr_hashed_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_169; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24203 = _T_23860 ? bht_bank_rd_data_out_0_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24458 = _T_24457 | _T_24203; // @[Mux.scala 27:72]
|
|
wire _T_23862 = bht_rd_addr_hashed_p1_f == 8'haa; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_170; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24204 = _T_23862 ? bht_bank_rd_data_out_0_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24459 = _T_24458 | _T_24204; // @[Mux.scala 27:72]
|
|
wire _T_23864 = bht_rd_addr_hashed_p1_f == 8'hab; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_171; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24205 = _T_23864 ? bht_bank_rd_data_out_0_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24460 = _T_24459 | _T_24205; // @[Mux.scala 27:72]
|
|
wire _T_23866 = bht_rd_addr_hashed_p1_f == 8'hac; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_172; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24206 = _T_23866 ? bht_bank_rd_data_out_0_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24461 = _T_24460 | _T_24206; // @[Mux.scala 27:72]
|
|
wire _T_23868 = bht_rd_addr_hashed_p1_f == 8'had; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_173; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24207 = _T_23868 ? bht_bank_rd_data_out_0_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24462 = _T_24461 | _T_24207; // @[Mux.scala 27:72]
|
|
wire _T_23870 = bht_rd_addr_hashed_p1_f == 8'hae; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_174; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24208 = _T_23870 ? bht_bank_rd_data_out_0_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24463 = _T_24462 | _T_24208; // @[Mux.scala 27:72]
|
|
wire _T_23872 = bht_rd_addr_hashed_p1_f == 8'haf; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_175; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24209 = _T_23872 ? bht_bank_rd_data_out_0_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24464 = _T_24463 | _T_24209; // @[Mux.scala 27:72]
|
|
wire _T_23874 = bht_rd_addr_hashed_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_176; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24210 = _T_23874 ? bht_bank_rd_data_out_0_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24465 = _T_24464 | _T_24210; // @[Mux.scala 27:72]
|
|
wire _T_23876 = bht_rd_addr_hashed_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_177; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24211 = _T_23876 ? bht_bank_rd_data_out_0_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24466 = _T_24465 | _T_24211; // @[Mux.scala 27:72]
|
|
wire _T_23878 = bht_rd_addr_hashed_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_178; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24212 = _T_23878 ? bht_bank_rd_data_out_0_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24467 = _T_24466 | _T_24212; // @[Mux.scala 27:72]
|
|
wire _T_23880 = bht_rd_addr_hashed_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_179; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24213 = _T_23880 ? bht_bank_rd_data_out_0_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24468 = _T_24467 | _T_24213; // @[Mux.scala 27:72]
|
|
wire _T_23882 = bht_rd_addr_hashed_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_180; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24214 = _T_23882 ? bht_bank_rd_data_out_0_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24469 = _T_24468 | _T_24214; // @[Mux.scala 27:72]
|
|
wire _T_23884 = bht_rd_addr_hashed_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_181; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24215 = _T_23884 ? bht_bank_rd_data_out_0_181 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24470 = _T_24469 | _T_24215; // @[Mux.scala 27:72]
|
|
wire _T_23886 = bht_rd_addr_hashed_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_182; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24216 = _T_23886 ? bht_bank_rd_data_out_0_182 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24471 = _T_24470 | _T_24216; // @[Mux.scala 27:72]
|
|
wire _T_23888 = bht_rd_addr_hashed_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_183; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24217 = _T_23888 ? bht_bank_rd_data_out_0_183 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24472 = _T_24471 | _T_24217; // @[Mux.scala 27:72]
|
|
wire _T_23890 = bht_rd_addr_hashed_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_184; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24218 = _T_23890 ? bht_bank_rd_data_out_0_184 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24473 = _T_24472 | _T_24218; // @[Mux.scala 27:72]
|
|
wire _T_23892 = bht_rd_addr_hashed_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_185; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24219 = _T_23892 ? bht_bank_rd_data_out_0_185 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24474 = _T_24473 | _T_24219; // @[Mux.scala 27:72]
|
|
wire _T_23894 = bht_rd_addr_hashed_p1_f == 8'hba; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_186; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24220 = _T_23894 ? bht_bank_rd_data_out_0_186 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24475 = _T_24474 | _T_24220; // @[Mux.scala 27:72]
|
|
wire _T_23896 = bht_rd_addr_hashed_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_187; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24221 = _T_23896 ? bht_bank_rd_data_out_0_187 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24476 = _T_24475 | _T_24221; // @[Mux.scala 27:72]
|
|
wire _T_23898 = bht_rd_addr_hashed_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_188; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24222 = _T_23898 ? bht_bank_rd_data_out_0_188 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24477 = _T_24476 | _T_24222; // @[Mux.scala 27:72]
|
|
wire _T_23900 = bht_rd_addr_hashed_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_189; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24223 = _T_23900 ? bht_bank_rd_data_out_0_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24478 = _T_24477 | _T_24223; // @[Mux.scala 27:72]
|
|
wire _T_23902 = bht_rd_addr_hashed_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_190; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24224 = _T_23902 ? bht_bank_rd_data_out_0_190 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24479 = _T_24478 | _T_24224; // @[Mux.scala 27:72]
|
|
wire _T_23904 = bht_rd_addr_hashed_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_191; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24225 = _T_23904 ? bht_bank_rd_data_out_0_191 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24480 = _T_24479 | _T_24225; // @[Mux.scala 27:72]
|
|
wire _T_23906 = bht_rd_addr_hashed_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_192; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24226 = _T_23906 ? bht_bank_rd_data_out_0_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24481 = _T_24480 | _T_24226; // @[Mux.scala 27:72]
|
|
wire _T_23908 = bht_rd_addr_hashed_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_193; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24227 = _T_23908 ? bht_bank_rd_data_out_0_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24482 = _T_24481 | _T_24227; // @[Mux.scala 27:72]
|
|
wire _T_23910 = bht_rd_addr_hashed_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_194; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24228 = _T_23910 ? bht_bank_rd_data_out_0_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24483 = _T_24482 | _T_24228; // @[Mux.scala 27:72]
|
|
wire _T_23912 = bht_rd_addr_hashed_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_195; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24229 = _T_23912 ? bht_bank_rd_data_out_0_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24484 = _T_24483 | _T_24229; // @[Mux.scala 27:72]
|
|
wire _T_23914 = bht_rd_addr_hashed_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_196; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24230 = _T_23914 ? bht_bank_rd_data_out_0_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24485 = _T_24484 | _T_24230; // @[Mux.scala 27:72]
|
|
wire _T_23916 = bht_rd_addr_hashed_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_197; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24231 = _T_23916 ? bht_bank_rd_data_out_0_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24486 = _T_24485 | _T_24231; // @[Mux.scala 27:72]
|
|
wire _T_23918 = bht_rd_addr_hashed_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_198; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24232 = _T_23918 ? bht_bank_rd_data_out_0_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24487 = _T_24486 | _T_24232; // @[Mux.scala 27:72]
|
|
wire _T_23920 = bht_rd_addr_hashed_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_199; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24233 = _T_23920 ? bht_bank_rd_data_out_0_199 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24488 = _T_24487 | _T_24233; // @[Mux.scala 27:72]
|
|
wire _T_23922 = bht_rd_addr_hashed_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_200; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24234 = _T_23922 ? bht_bank_rd_data_out_0_200 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24489 = _T_24488 | _T_24234; // @[Mux.scala 27:72]
|
|
wire _T_23924 = bht_rd_addr_hashed_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_201; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24235 = _T_23924 ? bht_bank_rd_data_out_0_201 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24490 = _T_24489 | _T_24235; // @[Mux.scala 27:72]
|
|
wire _T_23926 = bht_rd_addr_hashed_p1_f == 8'hca; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_202; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24236 = _T_23926 ? bht_bank_rd_data_out_0_202 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24491 = _T_24490 | _T_24236; // @[Mux.scala 27:72]
|
|
wire _T_23928 = bht_rd_addr_hashed_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_203; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24237 = _T_23928 ? bht_bank_rd_data_out_0_203 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24492 = _T_24491 | _T_24237; // @[Mux.scala 27:72]
|
|
wire _T_23930 = bht_rd_addr_hashed_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_204; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24238 = _T_23930 ? bht_bank_rd_data_out_0_204 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24493 = _T_24492 | _T_24238; // @[Mux.scala 27:72]
|
|
wire _T_23932 = bht_rd_addr_hashed_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_205; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24239 = _T_23932 ? bht_bank_rd_data_out_0_205 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24494 = _T_24493 | _T_24239; // @[Mux.scala 27:72]
|
|
wire _T_23934 = bht_rd_addr_hashed_p1_f == 8'hce; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_206; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24240 = _T_23934 ? bht_bank_rd_data_out_0_206 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24495 = _T_24494 | _T_24240; // @[Mux.scala 27:72]
|
|
wire _T_23936 = bht_rd_addr_hashed_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_207; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24241 = _T_23936 ? bht_bank_rd_data_out_0_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24496 = _T_24495 | _T_24241; // @[Mux.scala 27:72]
|
|
wire _T_23938 = bht_rd_addr_hashed_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_208; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24242 = _T_23938 ? bht_bank_rd_data_out_0_208 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24497 = _T_24496 | _T_24242; // @[Mux.scala 27:72]
|
|
wire _T_23940 = bht_rd_addr_hashed_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_209; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24243 = _T_23940 ? bht_bank_rd_data_out_0_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24498 = _T_24497 | _T_24243; // @[Mux.scala 27:72]
|
|
wire _T_23942 = bht_rd_addr_hashed_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_210; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24244 = _T_23942 ? bht_bank_rd_data_out_0_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24499 = _T_24498 | _T_24244; // @[Mux.scala 27:72]
|
|
wire _T_23944 = bht_rd_addr_hashed_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_211; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24245 = _T_23944 ? bht_bank_rd_data_out_0_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24500 = _T_24499 | _T_24245; // @[Mux.scala 27:72]
|
|
wire _T_23946 = bht_rd_addr_hashed_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_212; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24246 = _T_23946 ? bht_bank_rd_data_out_0_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24501 = _T_24500 | _T_24246; // @[Mux.scala 27:72]
|
|
wire _T_23948 = bht_rd_addr_hashed_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_213; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24247 = _T_23948 ? bht_bank_rd_data_out_0_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24502 = _T_24501 | _T_24247; // @[Mux.scala 27:72]
|
|
wire _T_23950 = bht_rd_addr_hashed_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_214; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24248 = _T_23950 ? bht_bank_rd_data_out_0_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24503 = _T_24502 | _T_24248; // @[Mux.scala 27:72]
|
|
wire _T_23952 = bht_rd_addr_hashed_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_215; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24249 = _T_23952 ? bht_bank_rd_data_out_0_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24504 = _T_24503 | _T_24249; // @[Mux.scala 27:72]
|
|
wire _T_23954 = bht_rd_addr_hashed_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_216; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24250 = _T_23954 ? bht_bank_rd_data_out_0_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24505 = _T_24504 | _T_24250; // @[Mux.scala 27:72]
|
|
wire _T_23956 = bht_rd_addr_hashed_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_217; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24251 = _T_23956 ? bht_bank_rd_data_out_0_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24506 = _T_24505 | _T_24251; // @[Mux.scala 27:72]
|
|
wire _T_23958 = bht_rd_addr_hashed_p1_f == 8'hda; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_218; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24252 = _T_23958 ? bht_bank_rd_data_out_0_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24507 = _T_24506 | _T_24252; // @[Mux.scala 27:72]
|
|
wire _T_23960 = bht_rd_addr_hashed_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_219; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24253 = _T_23960 ? bht_bank_rd_data_out_0_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24508 = _T_24507 | _T_24253; // @[Mux.scala 27:72]
|
|
wire _T_23962 = bht_rd_addr_hashed_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_220; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24254 = _T_23962 ? bht_bank_rd_data_out_0_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24509 = _T_24508 | _T_24254; // @[Mux.scala 27:72]
|
|
wire _T_23964 = bht_rd_addr_hashed_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_221; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24255 = _T_23964 ? bht_bank_rd_data_out_0_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24510 = _T_24509 | _T_24255; // @[Mux.scala 27:72]
|
|
wire _T_23966 = bht_rd_addr_hashed_p1_f == 8'hde; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_222; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24256 = _T_23966 ? bht_bank_rd_data_out_0_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24511 = _T_24510 | _T_24256; // @[Mux.scala 27:72]
|
|
wire _T_23968 = bht_rd_addr_hashed_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_223; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24257 = _T_23968 ? bht_bank_rd_data_out_0_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24512 = _T_24511 | _T_24257; // @[Mux.scala 27:72]
|
|
wire _T_23970 = bht_rd_addr_hashed_p1_f == 8'he0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_224; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24258 = _T_23970 ? bht_bank_rd_data_out_0_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24513 = _T_24512 | _T_24258; // @[Mux.scala 27:72]
|
|
wire _T_23972 = bht_rd_addr_hashed_p1_f == 8'he1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_225; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24259 = _T_23972 ? bht_bank_rd_data_out_0_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24514 = _T_24513 | _T_24259; // @[Mux.scala 27:72]
|
|
wire _T_23974 = bht_rd_addr_hashed_p1_f == 8'he2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_226; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24260 = _T_23974 ? bht_bank_rd_data_out_0_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24515 = _T_24514 | _T_24260; // @[Mux.scala 27:72]
|
|
wire _T_23976 = bht_rd_addr_hashed_p1_f == 8'he3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_227; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24261 = _T_23976 ? bht_bank_rd_data_out_0_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24516 = _T_24515 | _T_24261; // @[Mux.scala 27:72]
|
|
wire _T_23978 = bht_rd_addr_hashed_p1_f == 8'he4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_228; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24262 = _T_23978 ? bht_bank_rd_data_out_0_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24517 = _T_24516 | _T_24262; // @[Mux.scala 27:72]
|
|
wire _T_23980 = bht_rd_addr_hashed_p1_f == 8'he5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_229; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24263 = _T_23980 ? bht_bank_rd_data_out_0_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24518 = _T_24517 | _T_24263; // @[Mux.scala 27:72]
|
|
wire _T_23982 = bht_rd_addr_hashed_p1_f == 8'he6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_230; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24264 = _T_23982 ? bht_bank_rd_data_out_0_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24519 = _T_24518 | _T_24264; // @[Mux.scala 27:72]
|
|
wire _T_23984 = bht_rd_addr_hashed_p1_f == 8'he7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_231; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24265 = _T_23984 ? bht_bank_rd_data_out_0_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24520 = _T_24519 | _T_24265; // @[Mux.scala 27:72]
|
|
wire _T_23986 = bht_rd_addr_hashed_p1_f == 8'he8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_232; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24266 = _T_23986 ? bht_bank_rd_data_out_0_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24521 = _T_24520 | _T_24266; // @[Mux.scala 27:72]
|
|
wire _T_23988 = bht_rd_addr_hashed_p1_f == 8'he9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_233; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24267 = _T_23988 ? bht_bank_rd_data_out_0_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24522 = _T_24521 | _T_24267; // @[Mux.scala 27:72]
|
|
wire _T_23990 = bht_rd_addr_hashed_p1_f == 8'hea; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_234; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24268 = _T_23990 ? bht_bank_rd_data_out_0_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24523 = _T_24522 | _T_24268; // @[Mux.scala 27:72]
|
|
wire _T_23992 = bht_rd_addr_hashed_p1_f == 8'heb; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_235; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24269 = _T_23992 ? bht_bank_rd_data_out_0_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24524 = _T_24523 | _T_24269; // @[Mux.scala 27:72]
|
|
wire _T_23994 = bht_rd_addr_hashed_p1_f == 8'hec; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_236; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24270 = _T_23994 ? bht_bank_rd_data_out_0_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24525 = _T_24524 | _T_24270; // @[Mux.scala 27:72]
|
|
wire _T_23996 = bht_rd_addr_hashed_p1_f == 8'hed; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_237; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24271 = _T_23996 ? bht_bank_rd_data_out_0_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24526 = _T_24525 | _T_24271; // @[Mux.scala 27:72]
|
|
wire _T_23998 = bht_rd_addr_hashed_p1_f == 8'hee; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_238; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24272 = _T_23998 ? bht_bank_rd_data_out_0_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24527 = _T_24526 | _T_24272; // @[Mux.scala 27:72]
|
|
wire _T_24000 = bht_rd_addr_hashed_p1_f == 8'hef; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_239; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24273 = _T_24000 ? bht_bank_rd_data_out_0_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24528 = _T_24527 | _T_24273; // @[Mux.scala 27:72]
|
|
wire _T_24002 = bht_rd_addr_hashed_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_240; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24274 = _T_24002 ? bht_bank_rd_data_out_0_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24529 = _T_24528 | _T_24274; // @[Mux.scala 27:72]
|
|
wire _T_24004 = bht_rd_addr_hashed_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_241; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24275 = _T_24004 ? bht_bank_rd_data_out_0_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24530 = _T_24529 | _T_24275; // @[Mux.scala 27:72]
|
|
wire _T_24006 = bht_rd_addr_hashed_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_242; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24276 = _T_24006 ? bht_bank_rd_data_out_0_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24531 = _T_24530 | _T_24276; // @[Mux.scala 27:72]
|
|
wire _T_24008 = bht_rd_addr_hashed_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_243; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24277 = _T_24008 ? bht_bank_rd_data_out_0_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24532 = _T_24531 | _T_24277; // @[Mux.scala 27:72]
|
|
wire _T_24010 = bht_rd_addr_hashed_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_244; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24278 = _T_24010 ? bht_bank_rd_data_out_0_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24533 = _T_24532 | _T_24278; // @[Mux.scala 27:72]
|
|
wire _T_24012 = bht_rd_addr_hashed_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_245; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24279 = _T_24012 ? bht_bank_rd_data_out_0_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24534 = _T_24533 | _T_24279; // @[Mux.scala 27:72]
|
|
wire _T_24014 = bht_rd_addr_hashed_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_246; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24280 = _T_24014 ? bht_bank_rd_data_out_0_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24535 = _T_24534 | _T_24280; // @[Mux.scala 27:72]
|
|
wire _T_24016 = bht_rd_addr_hashed_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_247; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24281 = _T_24016 ? bht_bank_rd_data_out_0_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24536 = _T_24535 | _T_24281; // @[Mux.scala 27:72]
|
|
wire _T_24018 = bht_rd_addr_hashed_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_248; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24282 = _T_24018 ? bht_bank_rd_data_out_0_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24537 = _T_24536 | _T_24282; // @[Mux.scala 27:72]
|
|
wire _T_24020 = bht_rd_addr_hashed_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_249; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24283 = _T_24020 ? bht_bank_rd_data_out_0_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24538 = _T_24537 | _T_24283; // @[Mux.scala 27:72]
|
|
wire _T_24022 = bht_rd_addr_hashed_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_250; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24284 = _T_24022 ? bht_bank_rd_data_out_0_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24539 = _T_24538 | _T_24284; // @[Mux.scala 27:72]
|
|
wire _T_24024 = bht_rd_addr_hashed_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_251; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24285 = _T_24024 ? bht_bank_rd_data_out_0_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24540 = _T_24539 | _T_24285; // @[Mux.scala 27:72]
|
|
wire _T_24026 = bht_rd_addr_hashed_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_252; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24286 = _T_24026 ? bht_bank_rd_data_out_0_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24541 = _T_24540 | _T_24286; // @[Mux.scala 27:72]
|
|
wire _T_24028 = bht_rd_addr_hashed_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_253; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24287 = _T_24028 ? bht_bank_rd_data_out_0_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24542 = _T_24541 | _T_24287; // @[Mux.scala 27:72]
|
|
wire _T_24030 = bht_rd_addr_hashed_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_254; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24288 = _T_24030 ? bht_bank_rd_data_out_0_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_24543 = _T_24542 | _T_24288; // @[Mux.scala 27:72]
|
|
wire _T_24032 = bht_rd_addr_hashed_p1_f == 8'hff; // @[ifu_bp_ctl.scala 531:85]
|
|
reg [1:0] bht_bank_rd_data_out_0_255; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_24289 = _T_24032 ? bht_bank_rd_data_out_0_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank0_rd_data_p1_f = _T_24543 | _T_24289; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_280 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_vbank1_rd_data_f = _T_279 | _T_280; // @[Mux.scala 27:72]
|
|
wire _T_284 = bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 297:42]
|
|
wire [1:0] wayhit_f = _T_97 | _T_107; // @[ifu_bp_ctl.scala 171:43]
|
|
wire [1:0] _T_636 = _T_162 ? wayhit_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] wayhit_p1_f = _T_117 | _T_127; // @[ifu_bp_ctl.scala 173:49]
|
|
wire [1:0] _T_635 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_637 = io_ifc_fetch_addr_f[0] ? _T_635 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_638 = _T_636 | _T_637; // @[Mux.scala 27:72]
|
|
wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 257:64]
|
|
wire _T_238 = ~eoc_near; // @[ifu_bp_ctl.scala 259:15]
|
|
wire [1:0] _T_240 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 259:28]
|
|
wire _T_241 = |_T_240; // @[ifu_bp_ctl.scala 259:58]
|
|
wire eoc_mask = _T_238 | _T_241; // @[ifu_bp_ctl.scala 259:25]
|
|
wire [1:0] _T_640 = {eoc_mask,1'h1}; // @[Cat.scala 29:58]
|
|
wire [1:0] bht_valid_f = _T_638 & _T_640; // @[ifu_bp_ctl.scala 431:73]
|
|
wire _T_286 = _T_284 & bht_valid_f[1]; // @[ifu_bp_ctl.scala 297:69]
|
|
wire [1:0] _T_21986 = _T_22498 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21987 = _T_22500 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22242 = _T_21986 | _T_21987; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21988 = _T_22502 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22243 = _T_22242 | _T_21988; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21989 = _T_22504 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22244 = _T_22243 | _T_21989; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21990 = _T_22506 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22245 = _T_22244 | _T_21990; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21991 = _T_22508 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22246 = _T_22245 | _T_21991; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21992 = _T_22510 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22247 = _T_22246 | _T_21992; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21993 = _T_22512 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22248 = _T_22247 | _T_21993; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21994 = _T_22514 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22249 = _T_22248 | _T_21994; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21995 = _T_22516 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22250 = _T_22249 | _T_21995; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21996 = _T_22518 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22251 = _T_22250 | _T_21996; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21997 = _T_22520 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22252 = _T_22251 | _T_21997; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21998 = _T_22522 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22253 = _T_22252 | _T_21998; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_21999 = _T_22524 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22254 = _T_22253 | _T_21999; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22000 = _T_22526 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22255 = _T_22254 | _T_22000; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22001 = _T_22528 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22256 = _T_22255 | _T_22001; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22002 = _T_22530 ? bht_bank_rd_data_out_0_16 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22257 = _T_22256 | _T_22002; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22003 = _T_22532 ? bht_bank_rd_data_out_0_17 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22258 = _T_22257 | _T_22003; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22004 = _T_22534 ? bht_bank_rd_data_out_0_18 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22259 = _T_22258 | _T_22004; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22005 = _T_22536 ? bht_bank_rd_data_out_0_19 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22260 = _T_22259 | _T_22005; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22006 = _T_22538 ? bht_bank_rd_data_out_0_20 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22261 = _T_22260 | _T_22006; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22007 = _T_22540 ? bht_bank_rd_data_out_0_21 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22262 = _T_22261 | _T_22007; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22008 = _T_22542 ? bht_bank_rd_data_out_0_22 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22263 = _T_22262 | _T_22008; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22009 = _T_22544 ? bht_bank_rd_data_out_0_23 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22264 = _T_22263 | _T_22009; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22010 = _T_22546 ? bht_bank_rd_data_out_0_24 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22265 = _T_22264 | _T_22010; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22011 = _T_22548 ? bht_bank_rd_data_out_0_25 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22266 = _T_22265 | _T_22011; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22012 = _T_22550 ? bht_bank_rd_data_out_0_26 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22267 = _T_22266 | _T_22012; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22013 = _T_22552 ? bht_bank_rd_data_out_0_27 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22268 = _T_22267 | _T_22013; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22014 = _T_22554 ? bht_bank_rd_data_out_0_28 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22269 = _T_22268 | _T_22014; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22015 = _T_22556 ? bht_bank_rd_data_out_0_29 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22270 = _T_22269 | _T_22015; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22016 = _T_22558 ? bht_bank_rd_data_out_0_30 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22271 = _T_22270 | _T_22016; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22017 = _T_22560 ? bht_bank_rd_data_out_0_31 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22272 = _T_22271 | _T_22017; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22018 = _T_22562 ? bht_bank_rd_data_out_0_32 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22273 = _T_22272 | _T_22018; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22019 = _T_22564 ? bht_bank_rd_data_out_0_33 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22274 = _T_22273 | _T_22019; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22020 = _T_22566 ? bht_bank_rd_data_out_0_34 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22275 = _T_22274 | _T_22020; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22021 = _T_22568 ? bht_bank_rd_data_out_0_35 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22276 = _T_22275 | _T_22021; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22022 = _T_22570 ? bht_bank_rd_data_out_0_36 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22277 = _T_22276 | _T_22022; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22023 = _T_22572 ? bht_bank_rd_data_out_0_37 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22278 = _T_22277 | _T_22023; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22024 = _T_22574 ? bht_bank_rd_data_out_0_38 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22279 = _T_22278 | _T_22024; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22025 = _T_22576 ? bht_bank_rd_data_out_0_39 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22280 = _T_22279 | _T_22025; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22026 = _T_22578 ? bht_bank_rd_data_out_0_40 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22281 = _T_22280 | _T_22026; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22027 = _T_22580 ? bht_bank_rd_data_out_0_41 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22282 = _T_22281 | _T_22027; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22028 = _T_22582 ? bht_bank_rd_data_out_0_42 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22283 = _T_22282 | _T_22028; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22029 = _T_22584 ? bht_bank_rd_data_out_0_43 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22284 = _T_22283 | _T_22029; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22030 = _T_22586 ? bht_bank_rd_data_out_0_44 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22285 = _T_22284 | _T_22030; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22031 = _T_22588 ? bht_bank_rd_data_out_0_45 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22286 = _T_22285 | _T_22031; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22032 = _T_22590 ? bht_bank_rd_data_out_0_46 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22287 = _T_22286 | _T_22032; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22033 = _T_22592 ? bht_bank_rd_data_out_0_47 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22288 = _T_22287 | _T_22033; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22034 = _T_22594 ? bht_bank_rd_data_out_0_48 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22289 = _T_22288 | _T_22034; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22035 = _T_22596 ? bht_bank_rd_data_out_0_49 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22290 = _T_22289 | _T_22035; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22036 = _T_22598 ? bht_bank_rd_data_out_0_50 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22291 = _T_22290 | _T_22036; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22037 = _T_22600 ? bht_bank_rd_data_out_0_51 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22292 = _T_22291 | _T_22037; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22038 = _T_22602 ? bht_bank_rd_data_out_0_52 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22293 = _T_22292 | _T_22038; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22039 = _T_22604 ? bht_bank_rd_data_out_0_53 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22294 = _T_22293 | _T_22039; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22040 = _T_22606 ? bht_bank_rd_data_out_0_54 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22295 = _T_22294 | _T_22040; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22041 = _T_22608 ? bht_bank_rd_data_out_0_55 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22296 = _T_22295 | _T_22041; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22042 = _T_22610 ? bht_bank_rd_data_out_0_56 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22297 = _T_22296 | _T_22042; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22043 = _T_22612 ? bht_bank_rd_data_out_0_57 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22298 = _T_22297 | _T_22043; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22044 = _T_22614 ? bht_bank_rd_data_out_0_58 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22299 = _T_22298 | _T_22044; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22045 = _T_22616 ? bht_bank_rd_data_out_0_59 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22300 = _T_22299 | _T_22045; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22046 = _T_22618 ? bht_bank_rd_data_out_0_60 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22301 = _T_22300 | _T_22046; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22047 = _T_22620 ? bht_bank_rd_data_out_0_61 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22302 = _T_22301 | _T_22047; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22048 = _T_22622 ? bht_bank_rd_data_out_0_62 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22303 = _T_22302 | _T_22048; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22049 = _T_22624 ? bht_bank_rd_data_out_0_63 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22304 = _T_22303 | _T_22049; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22050 = _T_22626 ? bht_bank_rd_data_out_0_64 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22305 = _T_22304 | _T_22050; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22051 = _T_22628 ? bht_bank_rd_data_out_0_65 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22306 = _T_22305 | _T_22051; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22052 = _T_22630 ? bht_bank_rd_data_out_0_66 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22307 = _T_22306 | _T_22052; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22053 = _T_22632 ? bht_bank_rd_data_out_0_67 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22308 = _T_22307 | _T_22053; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22054 = _T_22634 ? bht_bank_rd_data_out_0_68 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22309 = _T_22308 | _T_22054; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22055 = _T_22636 ? bht_bank_rd_data_out_0_69 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22310 = _T_22309 | _T_22055; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22056 = _T_22638 ? bht_bank_rd_data_out_0_70 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22311 = _T_22310 | _T_22056; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22057 = _T_22640 ? bht_bank_rd_data_out_0_71 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22312 = _T_22311 | _T_22057; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22058 = _T_22642 ? bht_bank_rd_data_out_0_72 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22313 = _T_22312 | _T_22058; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22059 = _T_22644 ? bht_bank_rd_data_out_0_73 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22314 = _T_22313 | _T_22059; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22060 = _T_22646 ? bht_bank_rd_data_out_0_74 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22315 = _T_22314 | _T_22060; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22061 = _T_22648 ? bht_bank_rd_data_out_0_75 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22316 = _T_22315 | _T_22061; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22062 = _T_22650 ? bht_bank_rd_data_out_0_76 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22317 = _T_22316 | _T_22062; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22063 = _T_22652 ? bht_bank_rd_data_out_0_77 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22318 = _T_22317 | _T_22063; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22064 = _T_22654 ? bht_bank_rd_data_out_0_78 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22319 = _T_22318 | _T_22064; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22065 = _T_22656 ? bht_bank_rd_data_out_0_79 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22320 = _T_22319 | _T_22065; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22066 = _T_22658 ? bht_bank_rd_data_out_0_80 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22321 = _T_22320 | _T_22066; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22067 = _T_22660 ? bht_bank_rd_data_out_0_81 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22322 = _T_22321 | _T_22067; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22068 = _T_22662 ? bht_bank_rd_data_out_0_82 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22323 = _T_22322 | _T_22068; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22069 = _T_22664 ? bht_bank_rd_data_out_0_83 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22324 = _T_22323 | _T_22069; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22070 = _T_22666 ? bht_bank_rd_data_out_0_84 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22325 = _T_22324 | _T_22070; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22071 = _T_22668 ? bht_bank_rd_data_out_0_85 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22326 = _T_22325 | _T_22071; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22072 = _T_22670 ? bht_bank_rd_data_out_0_86 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22327 = _T_22326 | _T_22072; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22073 = _T_22672 ? bht_bank_rd_data_out_0_87 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22328 = _T_22327 | _T_22073; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22074 = _T_22674 ? bht_bank_rd_data_out_0_88 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22329 = _T_22328 | _T_22074; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22075 = _T_22676 ? bht_bank_rd_data_out_0_89 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22330 = _T_22329 | _T_22075; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22076 = _T_22678 ? bht_bank_rd_data_out_0_90 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22331 = _T_22330 | _T_22076; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22077 = _T_22680 ? bht_bank_rd_data_out_0_91 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22332 = _T_22331 | _T_22077; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22078 = _T_22682 ? bht_bank_rd_data_out_0_92 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22333 = _T_22332 | _T_22078; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22079 = _T_22684 ? bht_bank_rd_data_out_0_93 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22334 = _T_22333 | _T_22079; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22080 = _T_22686 ? bht_bank_rd_data_out_0_94 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22335 = _T_22334 | _T_22080; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22081 = _T_22688 ? bht_bank_rd_data_out_0_95 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22336 = _T_22335 | _T_22081; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22082 = _T_22690 ? bht_bank_rd_data_out_0_96 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22337 = _T_22336 | _T_22082; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22083 = _T_22692 ? bht_bank_rd_data_out_0_97 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22338 = _T_22337 | _T_22083; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22084 = _T_22694 ? bht_bank_rd_data_out_0_98 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22339 = _T_22338 | _T_22084; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22085 = _T_22696 ? bht_bank_rd_data_out_0_99 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22340 = _T_22339 | _T_22085; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22086 = _T_22698 ? bht_bank_rd_data_out_0_100 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22341 = _T_22340 | _T_22086; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22087 = _T_22700 ? bht_bank_rd_data_out_0_101 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22342 = _T_22341 | _T_22087; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22088 = _T_22702 ? bht_bank_rd_data_out_0_102 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22343 = _T_22342 | _T_22088; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22089 = _T_22704 ? bht_bank_rd_data_out_0_103 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22344 = _T_22343 | _T_22089; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22090 = _T_22706 ? bht_bank_rd_data_out_0_104 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22345 = _T_22344 | _T_22090; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22091 = _T_22708 ? bht_bank_rd_data_out_0_105 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22346 = _T_22345 | _T_22091; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22092 = _T_22710 ? bht_bank_rd_data_out_0_106 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22347 = _T_22346 | _T_22092; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22093 = _T_22712 ? bht_bank_rd_data_out_0_107 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22348 = _T_22347 | _T_22093; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22094 = _T_22714 ? bht_bank_rd_data_out_0_108 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22349 = _T_22348 | _T_22094; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22095 = _T_22716 ? bht_bank_rd_data_out_0_109 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22350 = _T_22349 | _T_22095; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22096 = _T_22718 ? bht_bank_rd_data_out_0_110 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22351 = _T_22350 | _T_22096; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22097 = _T_22720 ? bht_bank_rd_data_out_0_111 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22352 = _T_22351 | _T_22097; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22098 = _T_22722 ? bht_bank_rd_data_out_0_112 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22353 = _T_22352 | _T_22098; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22099 = _T_22724 ? bht_bank_rd_data_out_0_113 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22354 = _T_22353 | _T_22099; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22100 = _T_22726 ? bht_bank_rd_data_out_0_114 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22355 = _T_22354 | _T_22100; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22101 = _T_22728 ? bht_bank_rd_data_out_0_115 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22356 = _T_22355 | _T_22101; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22102 = _T_22730 ? bht_bank_rd_data_out_0_116 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22357 = _T_22356 | _T_22102; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22103 = _T_22732 ? bht_bank_rd_data_out_0_117 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22358 = _T_22357 | _T_22103; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22104 = _T_22734 ? bht_bank_rd_data_out_0_118 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22359 = _T_22358 | _T_22104; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22105 = _T_22736 ? bht_bank_rd_data_out_0_119 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22360 = _T_22359 | _T_22105; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22106 = _T_22738 ? bht_bank_rd_data_out_0_120 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22361 = _T_22360 | _T_22106; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22107 = _T_22740 ? bht_bank_rd_data_out_0_121 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22362 = _T_22361 | _T_22107; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22108 = _T_22742 ? bht_bank_rd_data_out_0_122 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22363 = _T_22362 | _T_22108; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22109 = _T_22744 ? bht_bank_rd_data_out_0_123 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22364 = _T_22363 | _T_22109; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22110 = _T_22746 ? bht_bank_rd_data_out_0_124 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22365 = _T_22364 | _T_22110; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22111 = _T_22748 ? bht_bank_rd_data_out_0_125 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22366 = _T_22365 | _T_22111; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22112 = _T_22750 ? bht_bank_rd_data_out_0_126 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22367 = _T_22366 | _T_22112; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22113 = _T_22752 ? bht_bank_rd_data_out_0_127 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22368 = _T_22367 | _T_22113; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22114 = _T_22754 ? bht_bank_rd_data_out_0_128 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22369 = _T_22368 | _T_22114; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22115 = _T_22756 ? bht_bank_rd_data_out_0_129 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22370 = _T_22369 | _T_22115; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22116 = _T_22758 ? bht_bank_rd_data_out_0_130 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22371 = _T_22370 | _T_22116; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22117 = _T_22760 ? bht_bank_rd_data_out_0_131 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22372 = _T_22371 | _T_22117; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22118 = _T_22762 ? bht_bank_rd_data_out_0_132 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22373 = _T_22372 | _T_22118; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22119 = _T_22764 ? bht_bank_rd_data_out_0_133 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22374 = _T_22373 | _T_22119; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22120 = _T_22766 ? bht_bank_rd_data_out_0_134 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22375 = _T_22374 | _T_22120; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22121 = _T_22768 ? bht_bank_rd_data_out_0_135 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22376 = _T_22375 | _T_22121; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22122 = _T_22770 ? bht_bank_rd_data_out_0_136 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22377 = _T_22376 | _T_22122; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22123 = _T_22772 ? bht_bank_rd_data_out_0_137 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22378 = _T_22377 | _T_22123; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22124 = _T_22774 ? bht_bank_rd_data_out_0_138 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22379 = _T_22378 | _T_22124; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22125 = _T_22776 ? bht_bank_rd_data_out_0_139 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22380 = _T_22379 | _T_22125; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22126 = _T_22778 ? bht_bank_rd_data_out_0_140 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22381 = _T_22380 | _T_22126; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22127 = _T_22780 ? bht_bank_rd_data_out_0_141 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22382 = _T_22381 | _T_22127; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22128 = _T_22782 ? bht_bank_rd_data_out_0_142 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22383 = _T_22382 | _T_22128; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22129 = _T_22784 ? bht_bank_rd_data_out_0_143 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22384 = _T_22383 | _T_22129; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22130 = _T_22786 ? bht_bank_rd_data_out_0_144 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22385 = _T_22384 | _T_22130; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22131 = _T_22788 ? bht_bank_rd_data_out_0_145 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22386 = _T_22385 | _T_22131; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22132 = _T_22790 ? bht_bank_rd_data_out_0_146 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22387 = _T_22386 | _T_22132; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22133 = _T_22792 ? bht_bank_rd_data_out_0_147 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22388 = _T_22387 | _T_22133; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22134 = _T_22794 ? bht_bank_rd_data_out_0_148 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22389 = _T_22388 | _T_22134; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22135 = _T_22796 ? bht_bank_rd_data_out_0_149 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22390 = _T_22389 | _T_22135; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22136 = _T_22798 ? bht_bank_rd_data_out_0_150 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22391 = _T_22390 | _T_22136; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22137 = _T_22800 ? bht_bank_rd_data_out_0_151 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22392 = _T_22391 | _T_22137; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22138 = _T_22802 ? bht_bank_rd_data_out_0_152 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22393 = _T_22392 | _T_22138; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22139 = _T_22804 ? bht_bank_rd_data_out_0_153 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22394 = _T_22393 | _T_22139; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22140 = _T_22806 ? bht_bank_rd_data_out_0_154 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22395 = _T_22394 | _T_22140; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22141 = _T_22808 ? bht_bank_rd_data_out_0_155 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22396 = _T_22395 | _T_22141; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22142 = _T_22810 ? bht_bank_rd_data_out_0_156 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22397 = _T_22396 | _T_22142; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22143 = _T_22812 ? bht_bank_rd_data_out_0_157 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22398 = _T_22397 | _T_22143; // @[Mux.scala 27:72]
|
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wire [1:0] _T_22144 = _T_22814 ? bht_bank_rd_data_out_0_158 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22399 = _T_22398 | _T_22144; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22145 = _T_22816 ? bht_bank_rd_data_out_0_159 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22400 = _T_22399 | _T_22145; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22146 = _T_22818 ? bht_bank_rd_data_out_0_160 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22401 = _T_22400 | _T_22146; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22147 = _T_22820 ? bht_bank_rd_data_out_0_161 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22402 = _T_22401 | _T_22147; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22148 = _T_22822 ? bht_bank_rd_data_out_0_162 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22403 = _T_22402 | _T_22148; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22149 = _T_22824 ? bht_bank_rd_data_out_0_163 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22404 = _T_22403 | _T_22149; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22150 = _T_22826 ? bht_bank_rd_data_out_0_164 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22405 = _T_22404 | _T_22150; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22151 = _T_22828 ? bht_bank_rd_data_out_0_165 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22406 = _T_22405 | _T_22151; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22152 = _T_22830 ? bht_bank_rd_data_out_0_166 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22407 = _T_22406 | _T_22152; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22153 = _T_22832 ? bht_bank_rd_data_out_0_167 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22408 = _T_22407 | _T_22153; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22154 = _T_22834 ? bht_bank_rd_data_out_0_168 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22409 = _T_22408 | _T_22154; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22155 = _T_22836 ? bht_bank_rd_data_out_0_169 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22410 = _T_22409 | _T_22155; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22156 = _T_22838 ? bht_bank_rd_data_out_0_170 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22411 = _T_22410 | _T_22156; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22157 = _T_22840 ? bht_bank_rd_data_out_0_171 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22412 = _T_22411 | _T_22157; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22158 = _T_22842 ? bht_bank_rd_data_out_0_172 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22413 = _T_22412 | _T_22158; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22159 = _T_22844 ? bht_bank_rd_data_out_0_173 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22414 = _T_22413 | _T_22159; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22160 = _T_22846 ? bht_bank_rd_data_out_0_174 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22415 = _T_22414 | _T_22160; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22161 = _T_22848 ? bht_bank_rd_data_out_0_175 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22416 = _T_22415 | _T_22161; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22162 = _T_22850 ? bht_bank_rd_data_out_0_176 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22417 = _T_22416 | _T_22162; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22163 = _T_22852 ? bht_bank_rd_data_out_0_177 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22418 = _T_22417 | _T_22163; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22164 = _T_22854 ? bht_bank_rd_data_out_0_178 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22419 = _T_22418 | _T_22164; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22165 = _T_22856 ? bht_bank_rd_data_out_0_179 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22420 = _T_22419 | _T_22165; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22166 = _T_22858 ? bht_bank_rd_data_out_0_180 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22421 = _T_22420 | _T_22166; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22167 = _T_22860 ? bht_bank_rd_data_out_0_181 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22422 = _T_22421 | _T_22167; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22168 = _T_22862 ? bht_bank_rd_data_out_0_182 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22423 = _T_22422 | _T_22168; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22169 = _T_22864 ? bht_bank_rd_data_out_0_183 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22424 = _T_22423 | _T_22169; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22170 = _T_22866 ? bht_bank_rd_data_out_0_184 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22425 = _T_22424 | _T_22170; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22171 = _T_22868 ? bht_bank_rd_data_out_0_185 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22426 = _T_22425 | _T_22171; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22172 = _T_22870 ? bht_bank_rd_data_out_0_186 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22427 = _T_22426 | _T_22172; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22173 = _T_22872 ? bht_bank_rd_data_out_0_187 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22428 = _T_22427 | _T_22173; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22174 = _T_22874 ? bht_bank_rd_data_out_0_188 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22429 = _T_22428 | _T_22174; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22175 = _T_22876 ? bht_bank_rd_data_out_0_189 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22430 = _T_22429 | _T_22175; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22176 = _T_22878 ? bht_bank_rd_data_out_0_190 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22431 = _T_22430 | _T_22176; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22177 = _T_22880 ? bht_bank_rd_data_out_0_191 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22432 = _T_22431 | _T_22177; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22178 = _T_22882 ? bht_bank_rd_data_out_0_192 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22433 = _T_22432 | _T_22178; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22179 = _T_22884 ? bht_bank_rd_data_out_0_193 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22434 = _T_22433 | _T_22179; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22180 = _T_22886 ? bht_bank_rd_data_out_0_194 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22435 = _T_22434 | _T_22180; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22181 = _T_22888 ? bht_bank_rd_data_out_0_195 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22436 = _T_22435 | _T_22181; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22182 = _T_22890 ? bht_bank_rd_data_out_0_196 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22437 = _T_22436 | _T_22182; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22183 = _T_22892 ? bht_bank_rd_data_out_0_197 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22438 = _T_22437 | _T_22183; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22184 = _T_22894 ? bht_bank_rd_data_out_0_198 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22439 = _T_22438 | _T_22184; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22185 = _T_22896 ? bht_bank_rd_data_out_0_199 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22440 = _T_22439 | _T_22185; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22186 = _T_22898 ? bht_bank_rd_data_out_0_200 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22441 = _T_22440 | _T_22186; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22187 = _T_22900 ? bht_bank_rd_data_out_0_201 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22442 = _T_22441 | _T_22187; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22188 = _T_22902 ? bht_bank_rd_data_out_0_202 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22443 = _T_22442 | _T_22188; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22189 = _T_22904 ? bht_bank_rd_data_out_0_203 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22444 = _T_22443 | _T_22189; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22190 = _T_22906 ? bht_bank_rd_data_out_0_204 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22445 = _T_22444 | _T_22190; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22191 = _T_22908 ? bht_bank_rd_data_out_0_205 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22446 = _T_22445 | _T_22191; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22192 = _T_22910 ? bht_bank_rd_data_out_0_206 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22447 = _T_22446 | _T_22192; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22193 = _T_22912 ? bht_bank_rd_data_out_0_207 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22448 = _T_22447 | _T_22193; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22194 = _T_22914 ? bht_bank_rd_data_out_0_208 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22449 = _T_22448 | _T_22194; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22195 = _T_22916 ? bht_bank_rd_data_out_0_209 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22450 = _T_22449 | _T_22195; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22196 = _T_22918 ? bht_bank_rd_data_out_0_210 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22451 = _T_22450 | _T_22196; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22197 = _T_22920 ? bht_bank_rd_data_out_0_211 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22452 = _T_22451 | _T_22197; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22198 = _T_22922 ? bht_bank_rd_data_out_0_212 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22453 = _T_22452 | _T_22198; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22199 = _T_22924 ? bht_bank_rd_data_out_0_213 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22454 = _T_22453 | _T_22199; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22200 = _T_22926 ? bht_bank_rd_data_out_0_214 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22455 = _T_22454 | _T_22200; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22201 = _T_22928 ? bht_bank_rd_data_out_0_215 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22456 = _T_22455 | _T_22201; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22202 = _T_22930 ? bht_bank_rd_data_out_0_216 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22457 = _T_22456 | _T_22202; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22203 = _T_22932 ? bht_bank_rd_data_out_0_217 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22458 = _T_22457 | _T_22203; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22204 = _T_22934 ? bht_bank_rd_data_out_0_218 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22459 = _T_22458 | _T_22204; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22205 = _T_22936 ? bht_bank_rd_data_out_0_219 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22460 = _T_22459 | _T_22205; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22206 = _T_22938 ? bht_bank_rd_data_out_0_220 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22461 = _T_22460 | _T_22206; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22207 = _T_22940 ? bht_bank_rd_data_out_0_221 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22462 = _T_22461 | _T_22207; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22208 = _T_22942 ? bht_bank_rd_data_out_0_222 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22463 = _T_22462 | _T_22208; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22209 = _T_22944 ? bht_bank_rd_data_out_0_223 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22464 = _T_22463 | _T_22209; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22210 = _T_22946 ? bht_bank_rd_data_out_0_224 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22465 = _T_22464 | _T_22210; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22211 = _T_22948 ? bht_bank_rd_data_out_0_225 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22466 = _T_22465 | _T_22211; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22212 = _T_22950 ? bht_bank_rd_data_out_0_226 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22467 = _T_22466 | _T_22212; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22213 = _T_22952 ? bht_bank_rd_data_out_0_227 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22468 = _T_22467 | _T_22213; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22214 = _T_22954 ? bht_bank_rd_data_out_0_228 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22469 = _T_22468 | _T_22214; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22215 = _T_22956 ? bht_bank_rd_data_out_0_229 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22470 = _T_22469 | _T_22215; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22216 = _T_22958 ? bht_bank_rd_data_out_0_230 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22471 = _T_22470 | _T_22216; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22217 = _T_22960 ? bht_bank_rd_data_out_0_231 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22472 = _T_22471 | _T_22217; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22218 = _T_22962 ? bht_bank_rd_data_out_0_232 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22473 = _T_22472 | _T_22218; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22219 = _T_22964 ? bht_bank_rd_data_out_0_233 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22474 = _T_22473 | _T_22219; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22220 = _T_22966 ? bht_bank_rd_data_out_0_234 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22475 = _T_22474 | _T_22220; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22221 = _T_22968 ? bht_bank_rd_data_out_0_235 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22476 = _T_22475 | _T_22221; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22222 = _T_22970 ? bht_bank_rd_data_out_0_236 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22477 = _T_22476 | _T_22222; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22223 = _T_22972 ? bht_bank_rd_data_out_0_237 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22478 = _T_22477 | _T_22223; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22224 = _T_22974 ? bht_bank_rd_data_out_0_238 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22479 = _T_22478 | _T_22224; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22225 = _T_22976 ? bht_bank_rd_data_out_0_239 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22480 = _T_22479 | _T_22225; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22226 = _T_22978 ? bht_bank_rd_data_out_0_240 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22481 = _T_22480 | _T_22226; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22227 = _T_22980 ? bht_bank_rd_data_out_0_241 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22482 = _T_22481 | _T_22227; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22228 = _T_22982 ? bht_bank_rd_data_out_0_242 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22483 = _T_22482 | _T_22228; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22229 = _T_22984 ? bht_bank_rd_data_out_0_243 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22484 = _T_22483 | _T_22229; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22230 = _T_22986 ? bht_bank_rd_data_out_0_244 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22485 = _T_22484 | _T_22230; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22231 = _T_22988 ? bht_bank_rd_data_out_0_245 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22486 = _T_22485 | _T_22231; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22232 = _T_22990 ? bht_bank_rd_data_out_0_246 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22487 = _T_22486 | _T_22232; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22233 = _T_22992 ? bht_bank_rd_data_out_0_247 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22488 = _T_22487 | _T_22233; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22234 = _T_22994 ? bht_bank_rd_data_out_0_248 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22489 = _T_22488 | _T_22234; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22235 = _T_22996 ? bht_bank_rd_data_out_0_249 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22490 = _T_22489 | _T_22235; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22236 = _T_22998 ? bht_bank_rd_data_out_0_250 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22491 = _T_22490 | _T_22236; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22237 = _T_23000 ? bht_bank_rd_data_out_0_251 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22492 = _T_22491 | _T_22237; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22238 = _T_23002 ? bht_bank_rd_data_out_0_252 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22493 = _T_22492 | _T_22238; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22239 = _T_23004 ? bht_bank_rd_data_out_0_253 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22494 = _T_22493 | _T_22239; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22240 = _T_23006 ? bht_bank_rd_data_out_0_254 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22495 = _T_22494 | _T_22240; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_22241 = _T_23008 ? bht_bank_rd_data_out_0_255 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_bank0_rd_data_f = _T_22495 | _T_22241; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_271 = _T_162 ? bht_bank0_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_272 = io_ifc_fetch_addr_f[0] ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] bht_vbank0_rd_data_f = _T_271 | _T_272; // @[Mux.scala 27:72]
|
|
wire _T_289 = bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 298:27]
|
|
wire _T_291 = _T_289 & bht_valid_f[0]; // @[ifu_bp_ctl.scala 298:54]
|
|
wire [1:0] bht_dir_f = {_T_286,_T_291}; // @[Cat.scala 29:58]
|
|
wire _T_14 = ~bht_dir_f[0]; // @[ifu_bp_ctl.scala 118:23]
|
|
wire [1:0] btb_sel_f = {_T_14,bht_dir_f[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] fetch_start_f = {io_ifc_fetch_addr_f[0],_T_162}; // @[Cat.scala 29:58]
|
|
wire _T_38 = io_exu_bp_exu_mp_btag == _T_30; // @[ifu_bp_ctl.scala 139:55]
|
|
wire _T_39 = _T_38 & exu_mp_valid; // @[ifu_bp_ctl.scala 139:75]
|
|
wire _T_40 = _T_39 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 139:90]
|
|
wire _T_41 = io_exu_bp_exu_mp_index == btb_rd_addr_f; // @[ifu_bp_ctl.scala 139:126]
|
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wire _T_42 = _T_40 & _T_41; // @[ifu_bp_ctl.scala 139:111]
|
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wire _T_43 = io_exu_bp_exu_mp_btag == _T_37; // @[ifu_bp_ctl.scala 140:58]
|
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wire _T_44 = _T_43 & exu_mp_valid; // @[ifu_bp_ctl.scala 140:81]
|
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wire _T_45 = _T_44 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 140:96]
|
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wire _T_46 = io_exu_bp_exu_mp_index == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 140:132]
|
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wire _T_47 = _T_45 & _T_46; // @[ifu_bp_ctl.scala 140:117]
|
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wire [1:0] _T_168 = ~bht_valid_f; // @[ifu_bp_ctl.scala 193:46]
|
|
reg exu_mp_way_f; // @[Reg.scala 27:20]
|
|
wire [255:0] _T_172 = 256'h1 << btb_rd_addr_f; // @[ifu_bp_ctl.scala 212:33]
|
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reg [255:0] btb_lru_b0_f; // @[Reg.scala 27:20]
|
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wire [255:0] _T_205 = _T_172 & btb_lru_b0_f; // @[ifu_bp_ctl.scala 238:80]
|
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wire _T_206 = |_T_205; // @[ifu_bp_ctl.scala 238:96]
|
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wire _T_207 = _T_42 ? exu_mp_way_f : _T_206; // @[ifu_bp_ctl.scala 238:27]
|
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wire [1:0] _T_214 = {_T_207,_T_207}; // @[Cat.scala 29:58]
|
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wire [1:0] _T_218 = _T_162 ? _T_214 : 2'h0; // @[Mux.scala 27:72]
|
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wire [255:0] _T_173 = 256'h1 << btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 215:36]
|
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wire [255:0] _T_209 = _T_173 & btb_lru_b0_f; // @[ifu_bp_ctl.scala 240:89]
|
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wire _T_210 = |_T_209; // @[ifu_bp_ctl.scala 240:105]
|
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wire _T_211 = _T_47 ? exu_mp_way_f : _T_210; // @[ifu_bp_ctl.scala 240:30]
|
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wire [1:0] _T_217 = {_T_211,_T_207}; // @[Cat.scala 29:58]
|
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wire [1:0] _T_219 = io_ifc_fetch_addr_f[0] ? _T_217 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] btb_vlru_rd_f = _T_218 | _T_219; // @[Mux.scala 27:72]
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wire [1:0] _T_169 = _T_168 & btb_vlru_rd_f; // @[ifu_bp_ctl.scala 193:57]
|
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wire [1:0] _T_230 = _T_162 ? _T_107 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_229 = {_T_127[0],_T_107[1]}; // @[Cat.scala 29:58]
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wire [1:0] _T_231 = io_ifc_fetch_addr_f[0] ? _T_229 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] tag_match_vway1_expanded_f = _T_230 | _T_231; // @[Mux.scala 27:72]
|
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wire [255:0] _T_171 = 256'h1 << io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 209:30]
|
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wire [255:0] _T_175 = exu_mp_valid ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12]
|
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wire [255:0] _T_176 = _T_171 & _T_175; // @[ifu_bp_ctl.scala 218:38]
|
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wire _T_179 = bht_valid_f[0] | bht_valid_f[1]; // @[ifu_bp_ctl.scala 221:44]
|
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wire _T_180 = _T_179 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 221:60]
|
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wire _T_182 = _T_180 & _T; // @[ifu_bp_ctl.scala 221:81]
|
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wire [255:0] _T_184 = _T_182 ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12]
|
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wire [255:0] _T_185 = _T_172 & _T_184; // @[ifu_bp_ctl.scala 223:44]
|
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wire [255:0] _T_188 = _T_173 & _T_184; // @[ifu_bp_ctl.scala 224:50]
|
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wire [255:0] _T_189 = ~_T_176; // @[ifu_bp_ctl.scala 226:27]
|
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wire [255:0] _T_190 = ~_T_185; // @[ifu_bp_ctl.scala 226:42]
|
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wire [255:0] _T_191 = _T_189 & _T_190; // @[ifu_bp_ctl.scala 226:40]
|
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wire _T_193 = ~io_exu_bp_exu_mp_pkt_bits_way; // @[ifu_bp_ctl.scala 233:41]
|
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wire [255:0] _T_196 = _T_193 ? _T_176 : 256'h0; // @[Mux.scala 27:72]
|
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wire [255:0] _T_197 = _T_57 ? _T_185 : 256'h0; // @[Mux.scala 27:72]
|
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wire [255:0] _T_198 = _T_77 ? _T_188 : 256'h0; // @[Mux.scala 27:72]
|
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wire [255:0] _T_199 = _T_196 | _T_197; // @[Mux.scala 27:72]
|
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wire [255:0] _T_200 = _T_199 | _T_198; // @[Mux.scala 27:72]
|
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wire [255:0] _T_202 = _T_191 & btb_lru_b0_f; // @[ifu_bp_ctl.scala 235:75]
|
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wire [255:0] _T_203 = _T_200 | _T_202; // @[ifu_bp_ctl.scala 235:57]
|
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wire _T_234 = io_ifc_fetch_req_f | exu_mp_valid; // @[ifu_bp_ctl.scala 250:62]
|
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wire [15:0] _T_249 = btb_sel_f[1] ? btb_vbank1_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] _T_250 = btb_sel_f[0] ? btb_vbank0_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
|
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wire [15:0] btb_sel_data_f = _T_249 | _T_250; // @[Mux.scala 27:72]
|
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wire [11:0] btb_rd_tgt_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 266:36]
|
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wire btb_rd_pc4_f = btb_sel_data_f[3]; // @[ifu_bp_ctl.scala 267:36]
|
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wire btb_rd_call_f = btb_sel_data_f[1]; // @[ifu_bp_ctl.scala 268:37]
|
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wire btb_rd_ret_f = btb_sel_data_f[0]; // @[ifu_bp_ctl.scala 269:36]
|
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wire [1:0] _T_299 = {bht_vbank1_rd_data_f[1],bht_vbank0_rd_data_f[1]}; // @[Cat.scala 29:58]
|
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wire [1:0] hist1_raw = bht_force_taken_f | _T_299; // @[ifu_bp_ctl.scala 304:34]
|
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wire [1:0] _T_253 = bht_valid_f & hist1_raw; // @[ifu_bp_ctl.scala 276:39]
|
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wire _T_254 = |_T_253; // @[ifu_bp_ctl.scala 276:52]
|
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wire _T_255 = _T_254 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 276:56]
|
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wire _T_256 = ~leak_one_f_d1; // @[ifu_bp_ctl.scala 276:79]
|
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wire _T_257 = _T_255 & _T_256; // @[ifu_bp_ctl.scala 276:77]
|
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wire _T_258 = ~io_dec_bp_dec_tlu_bpred_disable; // @[ifu_bp_ctl.scala 276:96]
|
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wire _T_294 = io_ifu_bp_hit_taken_f & btb_sel_f[1]; // @[ifu_bp_ctl.scala 301:51]
|
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wire _T_295 = ~io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 301:69]
|
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wire _T_305 = bht_valid_f[1] & btb_vbank1_rd_data_f[4]; // @[ifu_bp_ctl.scala 310:34]
|
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wire _T_308 = bht_valid_f[0] & btb_vbank0_rd_data_f[4]; // @[ifu_bp_ctl.scala 311:18]
|
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wire _T_311 = ~btb_vbank1_rd_data_f[2]; // @[ifu_bp_ctl.scala 314:37]
|
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wire _T_312 = bht_valid_f[1] & _T_311; // @[ifu_bp_ctl.scala 314:35]
|
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wire _T_314 = _T_312 & btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 314:65]
|
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wire _T_317 = ~btb_vbank0_rd_data_f[2]; // @[ifu_bp_ctl.scala 315:20]
|
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wire _T_318 = bht_valid_f[0] & _T_317; // @[ifu_bp_ctl.scala 315:18]
|
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wire _T_320 = _T_318 & btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 315:48]
|
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wire [1:0] num_valids = bht_valid_f[1] + bht_valid_f[0]; // @[ifu_bp_ctl.scala 318:35]
|
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wire [1:0] _T_323 = btb_sel_f & bht_dir_f; // @[ifu_bp_ctl.scala 321:28]
|
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wire final_h = |_T_323; // @[ifu_bp_ctl.scala 321:41]
|
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wire _T_324 = num_valids == 2'h2; // @[ifu_bp_ctl.scala 325:41]
|
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wire [7:0] _T_328 = {fghr[5:0],1'h0,final_h}; // @[Cat.scala 29:58]
|
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wire _T_329 = num_valids == 2'h1; // @[ifu_bp_ctl.scala 326:16]
|
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wire [7:0] _T_332 = {fghr[6:0],final_h}; // @[Cat.scala 29:58]
|
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wire _T_333 = num_valids == 2'h0; // @[ifu_bp_ctl.scala 327:16]
|
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wire [7:0] _T_336 = _T_324 ? _T_328 : 8'h0; // @[Mux.scala 27:72]
|
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wire [7:0] _T_337 = _T_329 ? _T_332 : 8'h0; // @[Mux.scala 27:72]
|
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wire [7:0] _T_338 = _T_333 ? fghr : 8'h0; // @[Mux.scala 27:72]
|
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wire [7:0] _T_339 = _T_336 | _T_337; // @[Mux.scala 27:72]
|
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wire [7:0] merged_ghr = _T_339 | _T_338; // @[Mux.scala 27:72]
|
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reg exu_flush_final_d1; // @[Reg.scala 27:20]
|
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wire _T_342 = ~exu_flush_final_d1; // @[ifu_bp_ctl.scala 336:6]
|
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wire _T_343 = _T_342 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 336:26]
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wire _T_344 = _T_343 & io_ic_hit_f; // @[ifu_bp_ctl.scala 336:49]
|
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wire _T_346 = _T_344 & _T_256; // @[ifu_bp_ctl.scala 336:63]
|
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wire _T_349 = io_ifc_fetch_req_f & io_ic_hit_f; // @[ifu_bp_ctl.scala 337:49]
|
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wire _T_351 = _T_349 & _T_256; // @[ifu_bp_ctl.scala 337:63]
|
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wire _T_352 = ~_T_351; // @[ifu_bp_ctl.scala 337:28]
|
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wire _T_353 = _T_342 & _T_352; // @[ifu_bp_ctl.scala 337:26]
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wire [7:0] _T_355 = exu_flush_final_d1 ? io_exu_bp_exu_mp_fghr : 8'h0; // @[Mux.scala 27:72]
|
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wire [7:0] _T_356 = _T_346 ? merged_ghr : 8'h0; // @[Mux.scala 27:72]
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wire [7:0] _T_357 = _T_353 ? fghr : 8'h0; // @[Mux.scala 27:72]
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wire [7:0] _T_358 = _T_355 | _T_356; // @[Mux.scala 27:72]
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wire [7:0] fghr_ns = _T_358 | _T_357; // @[Mux.scala 27:72]
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wire _T_362 = leak_one_f ^ leak_one_f_d1; // @[lib.scala 466:21]
|
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wire _T_363 = |_T_362; // @[lib.scala 466:29]
|
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wire _T_366 = io_exu_bp_exu_mp_pkt_bits_way ^ exu_mp_way_f; // @[lib.scala 466:21]
|
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wire _T_367 = |_T_366; // @[lib.scala 466:29]
|
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wire _T_370 = io_exu_flush_final ^ exu_flush_final_d1; // @[lib.scala 488:21]
|
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wire _T_371 = |_T_370; // @[lib.scala 488:29]
|
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wire [7:0] _T_374 = fghr_ns ^ fghr; // @[lib.scala 466:21]
|
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wire _T_375 = |_T_374; // @[lib.scala 466:29]
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wire [1:0] _T_378 = io_dec_bp_dec_tlu_bpred_disable ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
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wire [1:0] _T_379 = ~_T_378; // @[ifu_bp_ctl.scala 349:36]
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wire _T_383 = ~fetch_start_f[0]; // @[ifu_bp_ctl.scala 353:36]
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wire _T_384 = bht_dir_f[0] & _T_383; // @[ifu_bp_ctl.scala 353:34]
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wire _T_388 = _T_14 & fetch_start_f[0]; // @[ifu_bp_ctl.scala 353:72]
|
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wire _T_389 = _T_384 | _T_388; // @[ifu_bp_ctl.scala 353:55]
|
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wire _T_392 = bht_dir_f[0] & fetch_start_f[0]; // @[ifu_bp_ctl.scala 354:19]
|
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wire _T_397 = _T_14 & _T_383; // @[ifu_bp_ctl.scala 354:56]
|
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wire _T_398 = _T_392 | _T_397; // @[ifu_bp_ctl.scala 354:39]
|
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wire [1:0] bloc_f = {_T_389,_T_398}; // @[Cat.scala 29:58]
|
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wire _T_402 = _T_14 & io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 356:35]
|
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wire _T_403 = ~btb_rd_pc4_f; // @[ifu_bp_ctl.scala 356:62]
|
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wire use_fa_plus = _T_402 & _T_403; // @[ifu_bp_ctl.scala 356:60]
|
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wire _T_406 = fetch_start_f[0] & btb_sel_f[0]; // @[ifu_bp_ctl.scala 358:44]
|
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wire btb_fg_crossing_f = _T_406 & btb_rd_pc4_f; // @[ifu_bp_ctl.scala 358:59]
|
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wire bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; // @[ifu_bp_ctl.scala 359:43]
|
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wire _T_410 = io_ifc_fetch_req_f & _T_295; // @[ifu_bp_ctl.scala 360:117]
|
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wire _T_411 = _T_410 & io_ic_hit_f; // @[ifu_bp_ctl.scala 360:142]
|
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reg [29:0] ifc_fetch_adder_prior; // @[Reg.scala 27:20]
|
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wire _T_416 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 365:6]
|
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wire _T_417 = ~use_fa_plus; // @[ifu_bp_ctl.scala 365:27]
|
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wire _T_418 = _T_416 & _T_417; // @[ifu_bp_ctl.scala 365:25]
|
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wire [29:0] _T_421 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72]
|
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wire [29:0] _T_422 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 30'h0; // @[Mux.scala 27:72]
|
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wire [29:0] _T_423 = _T_418 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72]
|
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wire [29:0] _T_424 = _T_421 | _T_422; // @[Mux.scala 27:72]
|
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wire [29:0] adder_pc_in_f = _T_424 | _T_423; // @[Mux.scala 27:72]
|
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wire [31:0] _T_428 = {adder_pc_in_f,bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58]
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wire [12:0] _T_429 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58]
|
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wire [12:0] _T_432 = _T_428[12:1] + _T_429[12:1]; // @[lib.scala 74:31]
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wire [18:0] _T_435 = _T_428[31:13] + 19'h1; // @[lib.scala 75:27]
|
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wire [18:0] _T_438 = _T_428[31:13] - 19'h1; // @[lib.scala 76:27]
|
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wire _T_441 = ~_T_432[12]; // @[lib.scala 78:28]
|
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wire _T_442 = _T_429[12] ^ _T_441; // @[lib.scala 78:26]
|
|
wire _T_445 = ~_T_429[12]; // @[lib.scala 79:8]
|
|
wire _T_447 = _T_445 & _T_432[12]; // @[lib.scala 79:14]
|
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wire _T_451 = _T_429[12] & _T_441; // @[lib.scala 80:14]
|
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wire [18:0] _T_453 = _T_442 ? _T_428[31:13] : 19'h0; // @[Mux.scala 27:72]
|
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wire [18:0] _T_454 = _T_447 ? _T_435 : 19'h0; // @[Mux.scala 27:72]
|
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wire [18:0] _T_455 = _T_451 ? _T_438 : 19'h0; // @[Mux.scala 27:72]
|
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wire [18:0] _T_456 = _T_453 | _T_454; // @[Mux.scala 27:72]
|
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wire [18:0] _T_457 = _T_456 | _T_455; // @[Mux.scala 27:72]
|
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wire [31:0] bp_btb_target_adder_f = {_T_457,_T_432[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_461 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 373:55]
|
|
wire _T_462 = btb_rd_ret_f & _T_461; // @[ifu_bp_ctl.scala 373:53]
|
|
reg [31:0] rets_out_0; // @[Reg.scala 27:20]
|
|
wire _T_464 = _T_462 & rets_out_0[0]; // @[ifu_bp_ctl.scala 373:70]
|
|
wire _T_465 = _T_464 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 373:87]
|
|
wire [30:0] _T_467 = _T_465 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
|
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wire [30:0] _T_469 = _T_467 & rets_out_0[31:1]; // @[ifu_bp_ctl.scala 373:113]
|
|
wire _T_474 = ~_T_464; // @[ifu_bp_ctl.scala 374:15]
|
|
wire _T_475 = _T_474 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 374:65]
|
|
wire [30:0] _T_477 = _T_475 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
|
|
wire [30:0] _T_479 = _T_477 & bp_btb_target_adder_f[31:1]; // @[ifu_bp_ctl.scala 374:91]
|
|
wire [12:0] _T_487 = {11'h0,_T_403,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_490 = _T_428[12:1] + _T_487[12:1]; // @[lib.scala 74:31]
|
|
wire _T_499 = ~_T_490[12]; // @[lib.scala 78:28]
|
|
wire _T_500 = _T_487[12] ^ _T_499; // @[lib.scala 78:26]
|
|
wire _T_503 = ~_T_487[12]; // @[lib.scala 79:8]
|
|
wire _T_505 = _T_503 & _T_490[12]; // @[lib.scala 79:14]
|
|
wire _T_509 = _T_487[12] & _T_499; // @[lib.scala 80:14]
|
|
wire [18:0] _T_511 = _T_500 ? _T_428[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_512 = _T_505 ? _T_435 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_513 = _T_509 ? _T_438 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_514 = _T_511 | _T_512; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_515 = _T_514 | _T_513; // @[Mux.scala 27:72]
|
|
wire [31:0] bp_rs_call_target_f = {_T_515,_T_490[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_519 = ~btb_rd_ret_f; // @[ifu_bp_ctl.scala 378:33]
|
|
wire _T_520 = btb_rd_call_f & _T_519; // @[ifu_bp_ctl.scala 378:31]
|
|
wire rs_push = _T_520 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 378:47]
|
|
wire rs_pop = _T_462 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 379:46]
|
|
wire _T_523 = ~rs_push; // @[ifu_bp_ctl.scala 380:17]
|
|
wire _T_524 = ~rs_pop; // @[ifu_bp_ctl.scala 380:28]
|
|
wire rs_hold = _T_523 & _T_524; // @[ifu_bp_ctl.scala 380:26]
|
|
wire rsenable_0 = ~rs_hold; // @[ifu_bp_ctl.scala 382:60]
|
|
wire rsenable_1 = rs_push | rs_pop; // @[ifu_bp_ctl.scala 382:119]
|
|
wire [31:0] _T_527 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_529 = rs_push ? _T_527 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_1; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_530 = rs_pop ? rets_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_0 = _T_529 | _T_530; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_534 = rs_push ? rets_out_0 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_2; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_535 = rs_pop ? rets_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_1 = _T_534 | _T_535; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_539 = rs_push ? rets_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_3; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_540 = rs_pop ? rets_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_2 = _T_539 | _T_540; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_544 = rs_push ? rets_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_4; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_545 = rs_pop ? rets_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_3 = _T_544 | _T_545; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_549 = rs_push ? rets_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_5; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_550 = rs_pop ? rets_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_4 = _T_549 | _T_550; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_554 = rs_push ? rets_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_6; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_555 = rs_pop ? rets_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_5 = _T_554 | _T_555; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_559 = rs_push ? rets_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] rets_out_7; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_560 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] rets_in_6 = _T_559 | _T_560; // @[Mux.scala 27:72]
|
|
wire _T_578 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 394:35]
|
|
wire btb_valid = exu_mp_valid & _T_578; // @[ifu_bp_ctl.scala 394:32]
|
|
wire _T_579 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 398:89]
|
|
wire _T_580 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 398:113]
|
|
wire [21:0] btb_wr_data = {io_exu_bp_exu_mp_btag,io_exu_bp_exu_mp_pkt_bits_toffset,io_exu_bp_exu_mp_pkt_bits_pc4,io_exu_bp_exu_mp_pkt_bits_boffset,_T_579,_T_580,btb_valid}; // @[Cat.scala 29:58]
|
|
wire _T_586 = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 399:41]
|
|
wire _T_587 = ~io_exu_bp_exu_mp_pkt_valid; // @[ifu_bp_ctl.scala 399:59]
|
|
wire exu_mp_valid_write = _T_586 & _T_587; // @[ifu_bp_ctl.scala 399:57]
|
|
wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 400:35]
|
|
wire _T_588 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 403:43]
|
|
wire _T_589 = exu_mp_valid & _T_588; // @[ifu_bp_ctl.scala 403:41]
|
|
wire _T_590 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 403:58]
|
|
wire _T_591 = _T_589 & _T_590; // @[ifu_bp_ctl.scala 403:56]
|
|
wire _T_592 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 403:72]
|
|
wire _T_593 = _T_591 & _T_592; // @[ifu_bp_ctl.scala 403:70]
|
|
wire [1:0] _T_595 = _T_593 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_596 = ~middle_of_bank; // @[ifu_bp_ctl.scala 403:106]
|
|
wire [1:0] _T_597 = {middle_of_bank,_T_596}; // @[Cat.scala 29:58]
|
|
wire [1:0] bht_wr_en0 = _T_595 & _T_597; // @[ifu_bp_ctl.scala 403:84]
|
|
wire [1:0] _T_599 = io_dec_bp_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_600 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 404:75]
|
|
wire [1:0] _T_601 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_600}; // @[Cat.scala 29:58]
|
|
wire [1:0] bht_wr_en2 = _T_599 & _T_601; // @[ifu_bp_ctl.scala 404:46]
|
|
wire [9:0] _T_602 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] bht_wr_addr0 = _T_602[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 62:35]
|
|
wire [9:0] _T_605 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] bht_wr_addr2 = _T_605[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 62:35]
|
|
wire _T_615 = _T_193 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 424:41]
|
|
wire _T_617 = _T_615 & _T_578; // @[ifu_bp_ctl.scala 424:62]
|
|
wire _T_618 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 424:89]
|
|
wire _T_619 = _T_618 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 424:106]
|
|
wire _T_620 = _T_617 | _T_619; // @[ifu_bp_ctl.scala 424:85]
|
|
wire _T_621 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 425:38]
|
|
wire _T_623 = _T_621 & _T_578; // @[ifu_bp_ctl.scala 425:59]
|
|
wire _T_624 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 425:100]
|
|
wire _T_625 = _T_623 | _T_624; // @[ifu_bp_ctl.scala 425:82]
|
|
wire [7:0] _T_627 = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 428:26]
|
|
wire _T_642 = _T_627 == 8'h0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_643 = _T_642 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_646 = _T_627 == 8'h1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_647 = _T_646 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_650 = _T_627 == 8'h2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_651 = _T_650 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_654 = _T_627 == 8'h3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_655 = _T_654 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_658 = _T_627 == 8'h4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_659 = _T_658 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_662 = _T_627 == 8'h5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_663 = _T_662 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_666 = _T_627 == 8'h6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_667 = _T_666 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_670 = _T_627 == 8'h7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_671 = _T_670 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_674 = _T_627 == 8'h8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_675 = _T_674 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_678 = _T_627 == 8'h9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_679 = _T_678 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_682 = _T_627 == 8'ha; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_683 = _T_682 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_686 = _T_627 == 8'hb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_687 = _T_686 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_690 = _T_627 == 8'hc; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_691 = _T_690 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_694 = _T_627 == 8'hd; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_695 = _T_694 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_698 = _T_627 == 8'he; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_699 = _T_698 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_702 = _T_627 == 8'hf; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_703 = _T_702 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_706 = _T_627 == 8'h10; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_707 = _T_706 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_710 = _T_627 == 8'h11; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_711 = _T_710 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_714 = _T_627 == 8'h12; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_715 = _T_714 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_718 = _T_627 == 8'h13; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_719 = _T_718 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_722 = _T_627 == 8'h14; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_723 = _T_722 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_726 = _T_627 == 8'h15; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_727 = _T_726 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_730 = _T_627 == 8'h16; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_731 = _T_730 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_734 = _T_627 == 8'h17; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_735 = _T_734 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_738 = _T_627 == 8'h18; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_739 = _T_738 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_742 = _T_627 == 8'h19; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_743 = _T_742 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_746 = _T_627 == 8'h1a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_747 = _T_746 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_750 = _T_627 == 8'h1b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_751 = _T_750 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_754 = _T_627 == 8'h1c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_755 = _T_754 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_758 = _T_627 == 8'h1d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_759 = _T_758 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_762 = _T_627 == 8'h1e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_763 = _T_762 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_766 = _T_627 == 8'h1f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_767 = _T_766 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_770 = _T_627 == 8'h20; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_771 = _T_770 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_774 = _T_627 == 8'h21; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_775 = _T_774 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_778 = _T_627 == 8'h22; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_779 = _T_778 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_782 = _T_627 == 8'h23; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_783 = _T_782 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_786 = _T_627 == 8'h24; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_787 = _T_786 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_790 = _T_627 == 8'h25; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_791 = _T_790 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_794 = _T_627 == 8'h26; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_795 = _T_794 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_798 = _T_627 == 8'h27; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_799 = _T_798 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_802 = _T_627 == 8'h28; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_803 = _T_802 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_806 = _T_627 == 8'h29; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_807 = _T_806 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_810 = _T_627 == 8'h2a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_811 = _T_810 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_814 = _T_627 == 8'h2b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_815 = _T_814 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_818 = _T_627 == 8'h2c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_819 = _T_818 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_822 = _T_627 == 8'h2d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_823 = _T_822 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_826 = _T_627 == 8'h2e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_827 = _T_826 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_830 = _T_627 == 8'h2f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_831 = _T_830 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_834 = _T_627 == 8'h30; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_835 = _T_834 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_838 = _T_627 == 8'h31; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_839 = _T_838 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_842 = _T_627 == 8'h32; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_843 = _T_842 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_846 = _T_627 == 8'h33; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_847 = _T_846 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_850 = _T_627 == 8'h34; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_851 = _T_850 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_854 = _T_627 == 8'h35; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_855 = _T_854 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_858 = _T_627 == 8'h36; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_859 = _T_858 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_862 = _T_627 == 8'h37; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_863 = _T_862 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_866 = _T_627 == 8'h38; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_867 = _T_866 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_870 = _T_627 == 8'h39; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_871 = _T_870 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_874 = _T_627 == 8'h3a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_875 = _T_874 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_878 = _T_627 == 8'h3b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_879 = _T_878 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_882 = _T_627 == 8'h3c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_883 = _T_882 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_886 = _T_627 == 8'h3d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_887 = _T_886 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_890 = _T_627 == 8'h3e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_891 = _T_890 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_894 = _T_627 == 8'h3f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_895 = _T_894 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_898 = _T_627 == 8'h40; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_899 = _T_898 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_902 = _T_627 == 8'h41; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_903 = _T_902 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_906 = _T_627 == 8'h42; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_907 = _T_906 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_910 = _T_627 == 8'h43; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_911 = _T_910 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_914 = _T_627 == 8'h44; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_915 = _T_914 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_918 = _T_627 == 8'h45; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_919 = _T_918 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_922 = _T_627 == 8'h46; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_923 = _T_922 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_926 = _T_627 == 8'h47; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_927 = _T_926 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_930 = _T_627 == 8'h48; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_931 = _T_930 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_934 = _T_627 == 8'h49; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_935 = _T_934 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_938 = _T_627 == 8'h4a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_939 = _T_938 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_942 = _T_627 == 8'h4b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_943 = _T_942 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_946 = _T_627 == 8'h4c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_947 = _T_946 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_950 = _T_627 == 8'h4d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_951 = _T_950 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_954 = _T_627 == 8'h4e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_955 = _T_954 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_958 = _T_627 == 8'h4f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_959 = _T_958 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_962 = _T_627 == 8'h50; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_963 = _T_962 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_966 = _T_627 == 8'h51; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_967 = _T_966 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_970 = _T_627 == 8'h52; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_971 = _T_970 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_974 = _T_627 == 8'h53; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_975 = _T_974 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_978 = _T_627 == 8'h54; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_979 = _T_978 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_982 = _T_627 == 8'h55; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_983 = _T_982 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_986 = _T_627 == 8'h56; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_987 = _T_986 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_990 = _T_627 == 8'h57; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_991 = _T_990 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_994 = _T_627 == 8'h58; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_995 = _T_994 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_998 = _T_627 == 8'h59; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_999 = _T_998 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1002 = _T_627 == 8'h5a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1003 = _T_1002 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1006 = _T_627 == 8'h5b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1007 = _T_1006 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1010 = _T_627 == 8'h5c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1011 = _T_1010 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1014 = _T_627 == 8'h5d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1015 = _T_1014 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1018 = _T_627 == 8'h5e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1019 = _T_1018 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1022 = _T_627 == 8'h5f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1023 = _T_1022 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1026 = _T_627 == 8'h60; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1027 = _T_1026 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1030 = _T_627 == 8'h61; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1031 = _T_1030 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1034 = _T_627 == 8'h62; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1035 = _T_1034 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1038 = _T_627 == 8'h63; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1039 = _T_1038 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1042 = _T_627 == 8'h64; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1043 = _T_1042 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1046 = _T_627 == 8'h65; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1047 = _T_1046 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1050 = _T_627 == 8'h66; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1051 = _T_1050 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1054 = _T_627 == 8'h67; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1055 = _T_1054 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1058 = _T_627 == 8'h68; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1059 = _T_1058 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1062 = _T_627 == 8'h69; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1063 = _T_1062 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1066 = _T_627 == 8'h6a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1067 = _T_1066 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1070 = _T_627 == 8'h6b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1071 = _T_1070 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1074 = _T_627 == 8'h6c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1075 = _T_1074 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1078 = _T_627 == 8'h6d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1079 = _T_1078 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1082 = _T_627 == 8'h6e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1083 = _T_1082 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1086 = _T_627 == 8'h6f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1087 = _T_1086 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1090 = _T_627 == 8'h70; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1091 = _T_1090 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1094 = _T_627 == 8'h71; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1095 = _T_1094 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1098 = _T_627 == 8'h72; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1099 = _T_1098 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1102 = _T_627 == 8'h73; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1103 = _T_1102 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1106 = _T_627 == 8'h74; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1107 = _T_1106 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1110 = _T_627 == 8'h75; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1111 = _T_1110 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1114 = _T_627 == 8'h76; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1115 = _T_1114 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1118 = _T_627 == 8'h77; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1119 = _T_1118 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1122 = _T_627 == 8'h78; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1123 = _T_1122 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1126 = _T_627 == 8'h79; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1127 = _T_1126 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1130 = _T_627 == 8'h7a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1131 = _T_1130 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1134 = _T_627 == 8'h7b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1135 = _T_1134 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1138 = _T_627 == 8'h7c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1139 = _T_1138 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1142 = _T_627 == 8'h7d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1143 = _T_1142 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1146 = _T_627 == 8'h7e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1147 = _T_1146 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1150 = _T_627 == 8'h7f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1151 = _T_1150 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1154 = _T_627 == 8'h80; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1155 = _T_1154 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1158 = _T_627 == 8'h81; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1159 = _T_1158 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1162 = _T_627 == 8'h82; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1163 = _T_1162 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1166 = _T_627 == 8'h83; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1167 = _T_1166 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1170 = _T_627 == 8'h84; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1171 = _T_1170 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1174 = _T_627 == 8'h85; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1175 = _T_1174 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1178 = _T_627 == 8'h86; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1179 = _T_1178 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1182 = _T_627 == 8'h87; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1183 = _T_1182 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1186 = _T_627 == 8'h88; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1187 = _T_1186 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1190 = _T_627 == 8'h89; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1191 = _T_1190 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1194 = _T_627 == 8'h8a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1195 = _T_1194 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1198 = _T_627 == 8'h8b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1199 = _T_1198 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1202 = _T_627 == 8'h8c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1203 = _T_1202 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1206 = _T_627 == 8'h8d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1207 = _T_1206 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1210 = _T_627 == 8'h8e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1211 = _T_1210 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1214 = _T_627 == 8'h8f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1215 = _T_1214 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1218 = _T_627 == 8'h90; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1219 = _T_1218 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1222 = _T_627 == 8'h91; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1223 = _T_1222 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1226 = _T_627 == 8'h92; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1227 = _T_1226 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1230 = _T_627 == 8'h93; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1231 = _T_1230 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1234 = _T_627 == 8'h94; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1235 = _T_1234 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1238 = _T_627 == 8'h95; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1239 = _T_1238 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1242 = _T_627 == 8'h96; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1243 = _T_1242 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1246 = _T_627 == 8'h97; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1247 = _T_1246 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1250 = _T_627 == 8'h98; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1251 = _T_1250 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1254 = _T_627 == 8'h99; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1255 = _T_1254 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1258 = _T_627 == 8'h9a; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1259 = _T_1258 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1262 = _T_627 == 8'h9b; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1263 = _T_1262 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1266 = _T_627 == 8'h9c; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1267 = _T_1266 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1270 = _T_627 == 8'h9d; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1271 = _T_1270 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1274 = _T_627 == 8'h9e; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1275 = _T_1274 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1278 = _T_627 == 8'h9f; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1279 = _T_1278 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1282 = _T_627 == 8'ha0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1283 = _T_1282 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1286 = _T_627 == 8'ha1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1287 = _T_1286 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1290 = _T_627 == 8'ha2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1291 = _T_1290 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1294 = _T_627 == 8'ha3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1295 = _T_1294 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1298 = _T_627 == 8'ha4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1299 = _T_1298 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1302 = _T_627 == 8'ha5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1303 = _T_1302 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1306 = _T_627 == 8'ha6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1307 = _T_1306 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1310 = _T_627 == 8'ha7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1311 = _T_1310 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1314 = _T_627 == 8'ha8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1315 = _T_1314 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1318 = _T_627 == 8'ha9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1319 = _T_1318 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1322 = _T_627 == 8'haa; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1323 = _T_1322 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1326 = _T_627 == 8'hab; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1327 = _T_1326 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1330 = _T_627 == 8'hac; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1331 = _T_1330 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1334 = _T_627 == 8'had; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1335 = _T_1334 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1338 = _T_627 == 8'hae; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1339 = _T_1338 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1342 = _T_627 == 8'haf; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1343 = _T_1342 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1346 = _T_627 == 8'hb0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1347 = _T_1346 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1350 = _T_627 == 8'hb1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1351 = _T_1350 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1354 = _T_627 == 8'hb2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1355 = _T_1354 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1358 = _T_627 == 8'hb3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1359 = _T_1358 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1362 = _T_627 == 8'hb4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1363 = _T_1362 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1366 = _T_627 == 8'hb5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1367 = _T_1366 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1370 = _T_627 == 8'hb6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1371 = _T_1370 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1374 = _T_627 == 8'hb7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1375 = _T_1374 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1378 = _T_627 == 8'hb8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1379 = _T_1378 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1382 = _T_627 == 8'hb9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1383 = _T_1382 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1386 = _T_627 == 8'hba; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1387 = _T_1386 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1390 = _T_627 == 8'hbb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1391 = _T_1390 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1394 = _T_627 == 8'hbc; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1395 = _T_1394 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1398 = _T_627 == 8'hbd; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1399 = _T_1398 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1402 = _T_627 == 8'hbe; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1403 = _T_1402 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1406 = _T_627 == 8'hbf; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1407 = _T_1406 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1410 = _T_627 == 8'hc0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1411 = _T_1410 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1414 = _T_627 == 8'hc1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1415 = _T_1414 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1418 = _T_627 == 8'hc2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1419 = _T_1418 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1422 = _T_627 == 8'hc3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1423 = _T_1422 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1426 = _T_627 == 8'hc4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1427 = _T_1426 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1430 = _T_627 == 8'hc5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1431 = _T_1430 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1434 = _T_627 == 8'hc6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1435 = _T_1434 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1438 = _T_627 == 8'hc7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1439 = _T_1438 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1442 = _T_627 == 8'hc8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1443 = _T_1442 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1446 = _T_627 == 8'hc9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1447 = _T_1446 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1450 = _T_627 == 8'hca; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1451 = _T_1450 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1454 = _T_627 == 8'hcb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1455 = _T_1454 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1458 = _T_627 == 8'hcc; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1459 = _T_1458 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1462 = _T_627 == 8'hcd; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1463 = _T_1462 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1466 = _T_627 == 8'hce; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1467 = _T_1466 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1470 = _T_627 == 8'hcf; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1471 = _T_1470 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1474 = _T_627 == 8'hd0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1475 = _T_1474 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1478 = _T_627 == 8'hd1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1479 = _T_1478 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1482 = _T_627 == 8'hd2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1483 = _T_1482 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1486 = _T_627 == 8'hd3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1487 = _T_1486 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1490 = _T_627 == 8'hd4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1491 = _T_1490 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1494 = _T_627 == 8'hd5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1495 = _T_1494 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1498 = _T_627 == 8'hd6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1499 = _T_1498 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1502 = _T_627 == 8'hd7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1503 = _T_1502 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1506 = _T_627 == 8'hd8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1507 = _T_1506 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1510 = _T_627 == 8'hd9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1511 = _T_1510 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1514 = _T_627 == 8'hda; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1515 = _T_1514 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1518 = _T_627 == 8'hdb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1519 = _T_1518 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1522 = _T_627 == 8'hdc; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1523 = _T_1522 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1526 = _T_627 == 8'hdd; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1527 = _T_1526 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1530 = _T_627 == 8'hde; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1531 = _T_1530 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1534 = _T_627 == 8'hdf; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1535 = _T_1534 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1538 = _T_627 == 8'he0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1539 = _T_1538 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1542 = _T_627 == 8'he1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1543 = _T_1542 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1546 = _T_627 == 8'he2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1547 = _T_1546 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1550 = _T_627 == 8'he3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1551 = _T_1550 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1554 = _T_627 == 8'he4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1555 = _T_1554 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1558 = _T_627 == 8'he5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1559 = _T_1558 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1562 = _T_627 == 8'he6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1563 = _T_1562 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1566 = _T_627 == 8'he7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1567 = _T_1566 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1570 = _T_627 == 8'he8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1571 = _T_1570 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1574 = _T_627 == 8'he9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1575 = _T_1574 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1578 = _T_627 == 8'hea; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1579 = _T_1578 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1582 = _T_627 == 8'heb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1583 = _T_1582 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1586 = _T_627 == 8'hec; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1587 = _T_1586 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1590 = _T_627 == 8'hed; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1591 = _T_1590 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1594 = _T_627 == 8'hee; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1595 = _T_1594 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1598 = _T_627 == 8'hef; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1599 = _T_1598 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1602 = _T_627 == 8'hf0; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1603 = _T_1602 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1606 = _T_627 == 8'hf1; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1607 = _T_1606 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1610 = _T_627 == 8'hf2; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1611 = _T_1610 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1614 = _T_627 == 8'hf3; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1615 = _T_1614 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1618 = _T_627 == 8'hf4; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1619 = _T_1618 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1622 = _T_627 == 8'hf5; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1623 = _T_1622 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1626 = _T_627 == 8'hf6; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1627 = _T_1626 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1630 = _T_627 == 8'hf7; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1631 = _T_1630 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1634 = _T_627 == 8'hf8; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1635 = _T_1634 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1638 = _T_627 == 8'hf9; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1639 = _T_1638 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1642 = _T_627 == 8'hfa; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1643 = _T_1642 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1646 = _T_627 == 8'hfb; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1647 = _T_1646 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1650 = _T_627 == 8'hfc; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1651 = _T_1650 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1654 = _T_627 == 8'hfd; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1655 = _T_1654 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1658 = _T_627 == 8'hfe; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1659 = _T_1658 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1662 = _T_627 == 8'hff; // @[ifu_bp_ctl.scala 433:97]
|
|
wire _T_1663 = _T_1662 & _T_620; // @[ifu_bp_ctl.scala 433:106]
|
|
wire _T_1667 = _T_642 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1671 = _T_646 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1675 = _T_650 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1679 = _T_654 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1683 = _T_658 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1687 = _T_662 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1691 = _T_666 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1695 = _T_670 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1699 = _T_674 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1703 = _T_678 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1707 = _T_682 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1711 = _T_686 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1715 = _T_690 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1719 = _T_694 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1723 = _T_698 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1727 = _T_702 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1731 = _T_706 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1735 = _T_710 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1739 = _T_714 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1743 = _T_718 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1747 = _T_722 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1751 = _T_726 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1755 = _T_730 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1759 = _T_734 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1763 = _T_738 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1767 = _T_742 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1771 = _T_746 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1775 = _T_750 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1779 = _T_754 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1783 = _T_758 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1787 = _T_762 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1791 = _T_766 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1795 = _T_770 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1799 = _T_774 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1803 = _T_778 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1807 = _T_782 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1811 = _T_786 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1815 = _T_790 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1819 = _T_794 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1823 = _T_798 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1827 = _T_802 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1831 = _T_806 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1835 = _T_810 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1839 = _T_814 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1843 = _T_818 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1847 = _T_822 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1851 = _T_826 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1855 = _T_830 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1859 = _T_834 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1863 = _T_838 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1867 = _T_842 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1871 = _T_846 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1875 = _T_850 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1879 = _T_854 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1883 = _T_858 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1887 = _T_862 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1891 = _T_866 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1895 = _T_870 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1899 = _T_874 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1903 = _T_878 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1907 = _T_882 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1911 = _T_886 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1915 = _T_890 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1919 = _T_894 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1923 = _T_898 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1927 = _T_902 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1931 = _T_906 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1935 = _T_910 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1939 = _T_914 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1943 = _T_918 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1947 = _T_922 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1951 = _T_926 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1955 = _T_930 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1959 = _T_934 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1963 = _T_938 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1967 = _T_942 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1971 = _T_946 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1975 = _T_950 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1979 = _T_954 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1983 = _T_958 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1987 = _T_962 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1991 = _T_966 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1995 = _T_970 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_1999 = _T_974 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2003 = _T_978 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2007 = _T_982 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2011 = _T_986 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2015 = _T_990 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2019 = _T_994 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2023 = _T_998 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2027 = _T_1002 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2031 = _T_1006 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2035 = _T_1010 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2039 = _T_1014 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2043 = _T_1018 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2047 = _T_1022 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2051 = _T_1026 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2055 = _T_1030 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2059 = _T_1034 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2063 = _T_1038 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2067 = _T_1042 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2071 = _T_1046 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2075 = _T_1050 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2079 = _T_1054 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2083 = _T_1058 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2087 = _T_1062 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2091 = _T_1066 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2095 = _T_1070 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2099 = _T_1074 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2103 = _T_1078 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2107 = _T_1082 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2111 = _T_1086 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2115 = _T_1090 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2119 = _T_1094 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2123 = _T_1098 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2127 = _T_1102 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2131 = _T_1106 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2135 = _T_1110 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2139 = _T_1114 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2143 = _T_1118 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2147 = _T_1122 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2151 = _T_1126 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2155 = _T_1130 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2159 = _T_1134 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2163 = _T_1138 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2167 = _T_1142 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2171 = _T_1146 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2175 = _T_1150 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2179 = _T_1154 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2183 = _T_1158 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2187 = _T_1162 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2191 = _T_1166 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2195 = _T_1170 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2199 = _T_1174 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2203 = _T_1178 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2207 = _T_1182 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2211 = _T_1186 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2215 = _T_1190 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2219 = _T_1194 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2223 = _T_1198 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2227 = _T_1202 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2231 = _T_1206 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2235 = _T_1210 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2239 = _T_1214 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2243 = _T_1218 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2247 = _T_1222 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2251 = _T_1226 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2255 = _T_1230 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2259 = _T_1234 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2263 = _T_1238 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2267 = _T_1242 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2271 = _T_1246 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2275 = _T_1250 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2279 = _T_1254 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2283 = _T_1258 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2287 = _T_1262 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2291 = _T_1266 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2295 = _T_1270 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2299 = _T_1274 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2303 = _T_1278 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2307 = _T_1282 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2311 = _T_1286 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2315 = _T_1290 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2319 = _T_1294 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2323 = _T_1298 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2327 = _T_1302 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2331 = _T_1306 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2335 = _T_1310 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2339 = _T_1314 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2343 = _T_1318 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2347 = _T_1322 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2351 = _T_1326 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2355 = _T_1330 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2359 = _T_1334 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2363 = _T_1338 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2367 = _T_1342 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2371 = _T_1346 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2375 = _T_1350 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2379 = _T_1354 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2383 = _T_1358 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2387 = _T_1362 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2391 = _T_1366 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2395 = _T_1370 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2399 = _T_1374 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2403 = _T_1378 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2407 = _T_1382 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2411 = _T_1386 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2415 = _T_1390 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2419 = _T_1394 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2423 = _T_1398 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2427 = _T_1402 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2431 = _T_1406 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2435 = _T_1410 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2439 = _T_1414 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2443 = _T_1418 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2447 = _T_1422 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2451 = _T_1426 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2455 = _T_1430 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2459 = _T_1434 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2463 = _T_1438 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2467 = _T_1442 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2471 = _T_1446 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2475 = _T_1450 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2479 = _T_1454 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2483 = _T_1458 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2487 = _T_1462 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2491 = _T_1466 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2495 = _T_1470 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2499 = _T_1474 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2503 = _T_1478 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2507 = _T_1482 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2511 = _T_1486 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2515 = _T_1490 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2519 = _T_1494 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2523 = _T_1498 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2527 = _T_1502 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2531 = _T_1506 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2535 = _T_1510 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2539 = _T_1514 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2543 = _T_1518 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2547 = _T_1522 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2551 = _T_1526 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2555 = _T_1530 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2559 = _T_1534 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2563 = _T_1538 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2567 = _T_1542 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2571 = _T_1546 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2575 = _T_1550 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2579 = _T_1554 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2583 = _T_1558 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2587 = _T_1562 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2591 = _T_1566 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2595 = _T_1570 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2599 = _T_1574 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2603 = _T_1578 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2607 = _T_1582 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2611 = _T_1586 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2615 = _T_1590 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2619 = _T_1594 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2623 = _T_1598 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2627 = _T_1602 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2631 = _T_1606 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2635 = _T_1610 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2639 = _T_1614 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2643 = _T_1618 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2647 = _T_1622 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2651 = _T_1626 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2655 = _T_1630 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2659 = _T_1634 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2663 = _T_1638 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2667 = _T_1642 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2671 = _T_1646 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2675 = _T_1650 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2679 = _T_1654 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2683 = _T_1658 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_2687 = _T_1662 & _T_625; // @[ifu_bp_ctl.scala 434:106]
|
|
wire _T_6788 = bht_wr_addr0[7:4] == 4'h0; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6790 = bht_wr_en0[0] & _T_6788; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6793 = bht_wr_addr2[7:4] == 4'h0; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6795 = bht_wr_en2[0] & _T_6793; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6799 = bht_wr_addr0[7:4] == 4'h1; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6801 = bht_wr_en0[0] & _T_6799; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6804 = bht_wr_addr2[7:4] == 4'h1; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6806 = bht_wr_en2[0] & _T_6804; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6810 = bht_wr_addr0[7:4] == 4'h2; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6812 = bht_wr_en0[0] & _T_6810; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6815 = bht_wr_addr2[7:4] == 4'h2; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6817 = bht_wr_en2[0] & _T_6815; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6821 = bht_wr_addr0[7:4] == 4'h3; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6823 = bht_wr_en0[0] & _T_6821; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6826 = bht_wr_addr2[7:4] == 4'h3; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6828 = bht_wr_en2[0] & _T_6826; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6832 = bht_wr_addr0[7:4] == 4'h4; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6834 = bht_wr_en0[0] & _T_6832; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6837 = bht_wr_addr2[7:4] == 4'h4; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6839 = bht_wr_en2[0] & _T_6837; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6843 = bht_wr_addr0[7:4] == 4'h5; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6845 = bht_wr_en0[0] & _T_6843; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6848 = bht_wr_addr2[7:4] == 4'h5; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6850 = bht_wr_en2[0] & _T_6848; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6854 = bht_wr_addr0[7:4] == 4'h6; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6856 = bht_wr_en0[0] & _T_6854; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6859 = bht_wr_addr2[7:4] == 4'h6; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6861 = bht_wr_en2[0] & _T_6859; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6865 = bht_wr_addr0[7:4] == 4'h7; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6867 = bht_wr_en0[0] & _T_6865; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6870 = bht_wr_addr2[7:4] == 4'h7; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6872 = bht_wr_en2[0] & _T_6870; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6876 = bht_wr_addr0[7:4] == 4'h8; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6878 = bht_wr_en0[0] & _T_6876; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6881 = bht_wr_addr2[7:4] == 4'h8; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6883 = bht_wr_en2[0] & _T_6881; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6887 = bht_wr_addr0[7:4] == 4'h9; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6889 = bht_wr_en0[0] & _T_6887; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6892 = bht_wr_addr2[7:4] == 4'h9; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6894 = bht_wr_en2[0] & _T_6892; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6898 = bht_wr_addr0[7:4] == 4'ha; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6900 = bht_wr_en0[0] & _T_6898; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6903 = bht_wr_addr2[7:4] == 4'ha; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6905 = bht_wr_en2[0] & _T_6903; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6909 = bht_wr_addr0[7:4] == 4'hb; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6911 = bht_wr_en0[0] & _T_6909; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6914 = bht_wr_addr2[7:4] == 4'hb; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6916 = bht_wr_en2[0] & _T_6914; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6920 = bht_wr_addr0[7:4] == 4'hc; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6922 = bht_wr_en0[0] & _T_6920; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6925 = bht_wr_addr2[7:4] == 4'hc; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6927 = bht_wr_en2[0] & _T_6925; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6931 = bht_wr_addr0[7:4] == 4'hd; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6933 = bht_wr_en0[0] & _T_6931; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6936 = bht_wr_addr2[7:4] == 4'hd; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6938 = bht_wr_en2[0] & _T_6936; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6942 = bht_wr_addr0[7:4] == 4'he; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6944 = bht_wr_en0[0] & _T_6942; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6947 = bht_wr_addr2[7:4] == 4'he; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6949 = bht_wr_en2[0] & _T_6947; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6953 = bht_wr_addr0[7:4] == 4'hf; // @[ifu_bp_ctl.scala 506:109]
|
|
wire _T_6955 = bht_wr_en0[0] & _T_6953; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6958 = bht_wr_addr2[7:4] == 4'hf; // @[ifu_bp_ctl.scala 507:87]
|
|
wire _T_6960 = bht_wr_en2[0] & _T_6958; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6966 = bht_wr_en0[1] & _T_6788; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6971 = bht_wr_en2[1] & _T_6793; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6977 = bht_wr_en0[1] & _T_6799; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6982 = bht_wr_en2[1] & _T_6804; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6988 = bht_wr_en0[1] & _T_6810; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_6993 = bht_wr_en2[1] & _T_6815; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_6999 = bht_wr_en0[1] & _T_6821; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7004 = bht_wr_en2[1] & _T_6826; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7010 = bht_wr_en0[1] & _T_6832; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7015 = bht_wr_en2[1] & _T_6837; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7021 = bht_wr_en0[1] & _T_6843; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7026 = bht_wr_en2[1] & _T_6848; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7032 = bht_wr_en0[1] & _T_6854; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7037 = bht_wr_en2[1] & _T_6859; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7043 = bht_wr_en0[1] & _T_6865; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7048 = bht_wr_en2[1] & _T_6870; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7054 = bht_wr_en0[1] & _T_6876; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7059 = bht_wr_en2[1] & _T_6881; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7065 = bht_wr_en0[1] & _T_6887; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7070 = bht_wr_en2[1] & _T_6892; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7076 = bht_wr_en0[1] & _T_6898; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7081 = bht_wr_en2[1] & _T_6903; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7087 = bht_wr_en0[1] & _T_6909; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7092 = bht_wr_en2[1] & _T_6914; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7098 = bht_wr_en0[1] & _T_6920; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7103 = bht_wr_en2[1] & _T_6925; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7109 = bht_wr_en0[1] & _T_6931; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7114 = bht_wr_en2[1] & _T_6936; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7120 = bht_wr_en0[1] & _T_6942; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7125 = bht_wr_en2[1] & _T_6947; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7131 = bht_wr_en0[1] & _T_6953; // @[ifu_bp_ctl.scala 506:44]
|
|
wire _T_7136 = bht_wr_en2[1] & _T_6958; // @[ifu_bp_ctl.scala 507:22]
|
|
wire _T_7140 = bht_wr_addr2[3:0] == 4'h0; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7141 = bht_wr_en2[0] & _T_7140; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7145 = _T_7141 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7149 = bht_wr_addr2[3:0] == 4'h1; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7150 = bht_wr_en2[0] & _T_7149; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7154 = _T_7150 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7158 = bht_wr_addr2[3:0] == 4'h2; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7159 = bht_wr_en2[0] & _T_7158; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7163 = _T_7159 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7167 = bht_wr_addr2[3:0] == 4'h3; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7168 = bht_wr_en2[0] & _T_7167; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7172 = _T_7168 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7176 = bht_wr_addr2[3:0] == 4'h4; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7177 = bht_wr_en2[0] & _T_7176; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7181 = _T_7177 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7185 = bht_wr_addr2[3:0] == 4'h5; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7186 = bht_wr_en2[0] & _T_7185; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7190 = _T_7186 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7194 = bht_wr_addr2[3:0] == 4'h6; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7195 = bht_wr_en2[0] & _T_7194; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7199 = _T_7195 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7203 = bht_wr_addr2[3:0] == 4'h7; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7204 = bht_wr_en2[0] & _T_7203; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7208 = _T_7204 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7212 = bht_wr_addr2[3:0] == 4'h8; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7213 = bht_wr_en2[0] & _T_7212; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7217 = _T_7213 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7221 = bht_wr_addr2[3:0] == 4'h9; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7222 = bht_wr_en2[0] & _T_7221; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7226 = _T_7222 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7230 = bht_wr_addr2[3:0] == 4'ha; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7231 = bht_wr_en2[0] & _T_7230; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7235 = _T_7231 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7239 = bht_wr_addr2[3:0] == 4'hb; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7240 = bht_wr_en2[0] & _T_7239; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7244 = _T_7240 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7248 = bht_wr_addr2[3:0] == 4'hc; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7249 = bht_wr_en2[0] & _T_7248; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7253 = _T_7249 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7257 = bht_wr_addr2[3:0] == 4'hd; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7258 = bht_wr_en2[0] & _T_7257; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7262 = _T_7258 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7266 = bht_wr_addr2[3:0] == 4'he; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7267 = bht_wr_en2[0] & _T_7266; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7271 = _T_7267 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7275 = bht_wr_addr2[3:0] == 4'hf; // @[ifu_bp_ctl.scala 511:74]
|
|
wire _T_7276 = bht_wr_en2[0] & _T_7275; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_7280 = _T_7276 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7289 = _T_7141 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7298 = _T_7150 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7307 = _T_7159 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7316 = _T_7168 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7325 = _T_7177 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7334 = _T_7186 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7343 = _T_7195 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7352 = _T_7204 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7361 = _T_7213 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7370 = _T_7222 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7379 = _T_7231 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7388 = _T_7240 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7397 = _T_7249 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7406 = _T_7258 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7415 = _T_7267 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7424 = _T_7276 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7433 = _T_7141 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7442 = _T_7150 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7451 = _T_7159 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7460 = _T_7168 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7469 = _T_7177 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7478 = _T_7186 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7487 = _T_7195 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7496 = _T_7204 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7505 = _T_7213 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7514 = _T_7222 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7523 = _T_7231 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7532 = _T_7240 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7541 = _T_7249 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7550 = _T_7258 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7559 = _T_7267 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7568 = _T_7276 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7577 = _T_7141 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7586 = _T_7150 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7595 = _T_7159 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7604 = _T_7168 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7613 = _T_7177 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7622 = _T_7186 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7631 = _T_7195 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7640 = _T_7204 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7649 = _T_7213 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7658 = _T_7222 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7667 = _T_7231 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7676 = _T_7240 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7685 = _T_7249 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7694 = _T_7258 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7703 = _T_7267 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7712 = _T_7276 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7721 = _T_7141 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7730 = _T_7150 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7739 = _T_7159 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7748 = _T_7168 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7757 = _T_7177 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7766 = _T_7186 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7775 = _T_7195 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7784 = _T_7204 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7793 = _T_7213 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7802 = _T_7222 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7811 = _T_7231 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7820 = _T_7240 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7829 = _T_7249 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7838 = _T_7258 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7847 = _T_7267 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7856 = _T_7276 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7865 = _T_7141 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7874 = _T_7150 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7883 = _T_7159 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7892 = _T_7168 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7901 = _T_7177 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7910 = _T_7186 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7919 = _T_7195 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7928 = _T_7204 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7937 = _T_7213 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7946 = _T_7222 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7955 = _T_7231 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7964 = _T_7240 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7973 = _T_7249 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7982 = _T_7258 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_7991 = _T_7267 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8000 = _T_7276 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8009 = _T_7141 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8018 = _T_7150 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8027 = _T_7159 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8036 = _T_7168 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8045 = _T_7177 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8054 = _T_7186 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8063 = _T_7195 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8072 = _T_7204 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8081 = _T_7213 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8090 = _T_7222 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8099 = _T_7231 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8108 = _T_7240 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8117 = _T_7249 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8126 = _T_7258 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8135 = _T_7267 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8144 = _T_7276 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8153 = _T_7141 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8162 = _T_7150 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8171 = _T_7159 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8180 = _T_7168 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8189 = _T_7177 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8198 = _T_7186 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8207 = _T_7195 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8216 = _T_7204 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8225 = _T_7213 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8234 = _T_7222 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8243 = _T_7231 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8252 = _T_7240 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8261 = _T_7249 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8270 = _T_7258 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8279 = _T_7267 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8288 = _T_7276 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8297 = _T_7141 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8306 = _T_7150 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8315 = _T_7159 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8324 = _T_7168 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8333 = _T_7177 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8342 = _T_7186 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8351 = _T_7195 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8360 = _T_7204 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8369 = _T_7213 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8378 = _T_7222 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8387 = _T_7231 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8396 = _T_7240 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8405 = _T_7249 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8414 = _T_7258 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8423 = _T_7267 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8432 = _T_7276 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8441 = _T_7141 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8450 = _T_7150 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8459 = _T_7159 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8468 = _T_7168 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8477 = _T_7177 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8486 = _T_7186 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8495 = _T_7195 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8504 = _T_7204 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8513 = _T_7213 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8522 = _T_7222 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8531 = _T_7231 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8540 = _T_7240 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8549 = _T_7249 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8558 = _T_7258 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8567 = _T_7267 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8576 = _T_7276 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8585 = _T_7141 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8594 = _T_7150 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8603 = _T_7159 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8612 = _T_7168 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8621 = _T_7177 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8630 = _T_7186 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8639 = _T_7195 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8648 = _T_7204 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8657 = _T_7213 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8666 = _T_7222 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8675 = _T_7231 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8684 = _T_7240 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8693 = _T_7249 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8702 = _T_7258 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8711 = _T_7267 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8720 = _T_7276 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8729 = _T_7141 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8738 = _T_7150 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8747 = _T_7159 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8756 = _T_7168 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8765 = _T_7177 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8774 = _T_7186 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8783 = _T_7195 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8792 = _T_7204 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8801 = _T_7213 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8810 = _T_7222 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8819 = _T_7231 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8828 = _T_7240 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8837 = _T_7249 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8846 = _T_7258 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8855 = _T_7267 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8864 = _T_7276 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8873 = _T_7141 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8882 = _T_7150 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8891 = _T_7159 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8900 = _T_7168 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8909 = _T_7177 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8918 = _T_7186 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8927 = _T_7195 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8936 = _T_7204 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8945 = _T_7213 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8954 = _T_7222 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8963 = _T_7231 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8972 = _T_7240 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8981 = _T_7249 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8990 = _T_7258 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_8999 = _T_7267 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9008 = _T_7276 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9017 = _T_7141 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9026 = _T_7150 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9035 = _T_7159 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9044 = _T_7168 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9053 = _T_7177 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9062 = _T_7186 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9071 = _T_7195 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9080 = _T_7204 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9089 = _T_7213 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9098 = _T_7222 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9107 = _T_7231 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9116 = _T_7240 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9125 = _T_7249 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9134 = _T_7258 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9143 = _T_7267 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9152 = _T_7276 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9161 = _T_7141 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9170 = _T_7150 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9179 = _T_7159 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9188 = _T_7168 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9197 = _T_7177 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9206 = _T_7186 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9215 = _T_7195 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9224 = _T_7204 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9233 = _T_7213 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9242 = _T_7222 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9251 = _T_7231 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9260 = _T_7240 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9269 = _T_7249 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9278 = _T_7258 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9287 = _T_7267 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9296 = _T_7276 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9305 = _T_7141 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9314 = _T_7150 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9323 = _T_7159 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9332 = _T_7168 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9341 = _T_7177 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9350 = _T_7186 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9359 = _T_7195 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9368 = _T_7204 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9377 = _T_7213 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9386 = _T_7222 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9395 = _T_7231 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9404 = _T_7240 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9413 = _T_7249 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9422 = _T_7258 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9431 = _T_7267 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9440 = _T_7276 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9445 = bht_wr_en2[1] & _T_7140; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9449 = _T_9445 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9454 = bht_wr_en2[1] & _T_7149; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9458 = _T_9454 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9463 = bht_wr_en2[1] & _T_7158; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9467 = _T_9463 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9472 = bht_wr_en2[1] & _T_7167; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9476 = _T_9472 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9481 = bht_wr_en2[1] & _T_7176; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9485 = _T_9481 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9490 = bht_wr_en2[1] & _T_7185; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9494 = _T_9490 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9499 = bht_wr_en2[1] & _T_7194; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9503 = _T_9499 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9508 = bht_wr_en2[1] & _T_7203; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9512 = _T_9508 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9517 = bht_wr_en2[1] & _T_7212; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9521 = _T_9517 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9526 = bht_wr_en2[1] & _T_7221; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9530 = _T_9526 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9535 = bht_wr_en2[1] & _T_7230; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9539 = _T_9535 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9544 = bht_wr_en2[1] & _T_7239; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9548 = _T_9544 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9553 = bht_wr_en2[1] & _T_7248; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9557 = _T_9553 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9562 = bht_wr_en2[1] & _T_7257; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9566 = _T_9562 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9571 = bht_wr_en2[1] & _T_7266; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9575 = _T_9571 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9580 = bht_wr_en2[1] & _T_7275; // @[ifu_bp_ctl.scala 511:23]
|
|
wire _T_9584 = _T_9580 & _T_6793; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9593 = _T_9445 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9602 = _T_9454 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9611 = _T_9463 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9620 = _T_9472 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9629 = _T_9481 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9638 = _T_9490 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9647 = _T_9499 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9656 = _T_9508 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9665 = _T_9517 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9674 = _T_9526 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9683 = _T_9535 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9692 = _T_9544 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9701 = _T_9553 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9710 = _T_9562 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9719 = _T_9571 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9728 = _T_9580 & _T_6804; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9737 = _T_9445 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9746 = _T_9454 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9755 = _T_9463 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9764 = _T_9472 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9773 = _T_9481 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9782 = _T_9490 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9791 = _T_9499 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9800 = _T_9508 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9809 = _T_9517 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9818 = _T_9526 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9827 = _T_9535 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9836 = _T_9544 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9845 = _T_9553 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9854 = _T_9562 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9863 = _T_9571 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9872 = _T_9580 & _T_6815; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9881 = _T_9445 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9890 = _T_9454 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9899 = _T_9463 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9908 = _T_9472 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9917 = _T_9481 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9926 = _T_9490 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9935 = _T_9499 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9944 = _T_9508 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9953 = _T_9517 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9962 = _T_9526 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9971 = _T_9535 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9980 = _T_9544 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9989 = _T_9553 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_9998 = _T_9562 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10007 = _T_9571 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10016 = _T_9580 & _T_6826; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10025 = _T_9445 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10034 = _T_9454 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10043 = _T_9463 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10052 = _T_9472 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10061 = _T_9481 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10070 = _T_9490 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10079 = _T_9499 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10088 = _T_9508 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10097 = _T_9517 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10106 = _T_9526 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10115 = _T_9535 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10124 = _T_9544 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10133 = _T_9553 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10142 = _T_9562 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10151 = _T_9571 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10160 = _T_9580 & _T_6837; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10169 = _T_9445 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10178 = _T_9454 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10187 = _T_9463 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10196 = _T_9472 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10205 = _T_9481 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10214 = _T_9490 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10223 = _T_9499 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10232 = _T_9508 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10241 = _T_9517 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10250 = _T_9526 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10259 = _T_9535 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10268 = _T_9544 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10277 = _T_9553 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10286 = _T_9562 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10295 = _T_9571 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10304 = _T_9580 & _T_6848; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10313 = _T_9445 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10322 = _T_9454 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10331 = _T_9463 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10340 = _T_9472 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10349 = _T_9481 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10358 = _T_9490 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10367 = _T_9499 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10376 = _T_9508 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10385 = _T_9517 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10394 = _T_9526 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10403 = _T_9535 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10412 = _T_9544 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10421 = _T_9553 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10430 = _T_9562 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10439 = _T_9571 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10448 = _T_9580 & _T_6859; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10457 = _T_9445 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10466 = _T_9454 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10475 = _T_9463 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10484 = _T_9472 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10493 = _T_9481 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10502 = _T_9490 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10511 = _T_9499 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10520 = _T_9508 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10529 = _T_9517 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10538 = _T_9526 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10547 = _T_9535 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10556 = _T_9544 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10565 = _T_9553 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10574 = _T_9562 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10583 = _T_9571 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10592 = _T_9580 & _T_6870; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10601 = _T_9445 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10610 = _T_9454 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10619 = _T_9463 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10628 = _T_9472 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10637 = _T_9481 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10646 = _T_9490 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10655 = _T_9499 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10664 = _T_9508 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10673 = _T_9517 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10682 = _T_9526 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10691 = _T_9535 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10700 = _T_9544 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10709 = _T_9553 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10718 = _T_9562 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10727 = _T_9571 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10736 = _T_9580 & _T_6881; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10745 = _T_9445 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10754 = _T_9454 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10763 = _T_9463 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10772 = _T_9472 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10781 = _T_9481 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10790 = _T_9490 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10799 = _T_9499 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10808 = _T_9508 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10817 = _T_9517 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10826 = _T_9526 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10835 = _T_9535 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10844 = _T_9544 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10853 = _T_9553 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10862 = _T_9562 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10871 = _T_9571 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10880 = _T_9580 & _T_6892; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10889 = _T_9445 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10898 = _T_9454 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10907 = _T_9463 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10916 = _T_9472 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10925 = _T_9481 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10934 = _T_9490 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10943 = _T_9499 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10952 = _T_9508 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10961 = _T_9517 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10970 = _T_9526 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10979 = _T_9535 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10988 = _T_9544 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_10997 = _T_9553 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11006 = _T_9562 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11015 = _T_9571 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11024 = _T_9580 & _T_6903; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11033 = _T_9445 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11042 = _T_9454 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11051 = _T_9463 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11060 = _T_9472 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11069 = _T_9481 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11078 = _T_9490 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11087 = _T_9499 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11096 = _T_9508 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11105 = _T_9517 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11114 = _T_9526 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11123 = _T_9535 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11132 = _T_9544 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11141 = _T_9553 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11150 = _T_9562 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11159 = _T_9571 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11168 = _T_9580 & _T_6914; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11177 = _T_9445 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11186 = _T_9454 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11195 = _T_9463 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11204 = _T_9472 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11213 = _T_9481 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11222 = _T_9490 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11231 = _T_9499 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11240 = _T_9508 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11249 = _T_9517 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11258 = _T_9526 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11267 = _T_9535 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11276 = _T_9544 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11285 = _T_9553 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11294 = _T_9562 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11303 = _T_9571 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11312 = _T_9580 & _T_6925; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11321 = _T_9445 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11330 = _T_9454 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11339 = _T_9463 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11348 = _T_9472 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11357 = _T_9481 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11366 = _T_9490 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11375 = _T_9499 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11384 = _T_9508 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11393 = _T_9517 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11402 = _T_9526 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11411 = _T_9535 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11420 = _T_9544 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11429 = _T_9553 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11438 = _T_9562 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11447 = _T_9571 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11456 = _T_9580 & _T_6936; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11465 = _T_9445 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11474 = _T_9454 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11483 = _T_9463 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11492 = _T_9472 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11501 = _T_9481 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11510 = _T_9490 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11519 = _T_9499 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11528 = _T_9508 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11537 = _T_9517 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11546 = _T_9526 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11555 = _T_9535 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11564 = _T_9544 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11573 = _T_9553 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11582 = _T_9562 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11591 = _T_9571 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11600 = _T_9580 & _T_6947; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11609 = _T_9445 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11618 = _T_9454 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11627 = _T_9463 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11636 = _T_9472 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11645 = _T_9481 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11654 = _T_9490 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11663 = _T_9499 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11672 = _T_9508 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11681 = _T_9517 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11690 = _T_9526 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11699 = _T_9535 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11708 = _T_9544 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11717 = _T_9553 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11726 = _T_9562 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11735 = _T_9571 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11744 = _T_9580 & _T_6958; // @[ifu_bp_ctl.scala 511:81]
|
|
wire _T_11748 = bht_wr_addr0[3:0] == 4'h0; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11749 = bht_wr_en0[0] & _T_11748; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11753 = _T_11749 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_0 = _T_11753 | _T_7145; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11765 = bht_wr_addr0[3:0] == 4'h1; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11766 = bht_wr_en0[0] & _T_11765; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11770 = _T_11766 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_1 = _T_11770 | _T_7154; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11782 = bht_wr_addr0[3:0] == 4'h2; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11783 = bht_wr_en0[0] & _T_11782; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11787 = _T_11783 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_2 = _T_11787 | _T_7163; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11799 = bht_wr_addr0[3:0] == 4'h3; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11800 = bht_wr_en0[0] & _T_11799; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11804 = _T_11800 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_3 = _T_11804 | _T_7172; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11816 = bht_wr_addr0[3:0] == 4'h4; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11817 = bht_wr_en0[0] & _T_11816; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11821 = _T_11817 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_4 = _T_11821 | _T_7181; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11833 = bht_wr_addr0[3:0] == 4'h5; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11834 = bht_wr_en0[0] & _T_11833; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11838 = _T_11834 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_5 = _T_11838 | _T_7190; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11850 = bht_wr_addr0[3:0] == 4'h6; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11851 = bht_wr_en0[0] & _T_11850; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11855 = _T_11851 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_6 = _T_11855 | _T_7199; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11867 = bht_wr_addr0[3:0] == 4'h7; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11868 = bht_wr_en0[0] & _T_11867; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11872 = _T_11868 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_7 = _T_11872 | _T_7208; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11884 = bht_wr_addr0[3:0] == 4'h8; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11885 = bht_wr_en0[0] & _T_11884; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11889 = _T_11885 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_8 = _T_11889 | _T_7217; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11901 = bht_wr_addr0[3:0] == 4'h9; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11902 = bht_wr_en0[0] & _T_11901; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11906 = _T_11902 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_9 = _T_11906 | _T_7226; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11918 = bht_wr_addr0[3:0] == 4'ha; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11919 = bht_wr_en0[0] & _T_11918; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11923 = _T_11919 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_10 = _T_11923 | _T_7235; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11935 = bht_wr_addr0[3:0] == 4'hb; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11936 = bht_wr_en0[0] & _T_11935; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11940 = _T_11936 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_11 = _T_11940 | _T_7244; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11952 = bht_wr_addr0[3:0] == 4'hc; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11953 = bht_wr_en0[0] & _T_11952; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11957 = _T_11953 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_12 = _T_11957 | _T_7253; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11969 = bht_wr_addr0[3:0] == 4'hd; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11970 = bht_wr_en0[0] & _T_11969; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11974 = _T_11970 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_13 = _T_11974 | _T_7262; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_11986 = bht_wr_addr0[3:0] == 4'he; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_11987 = bht_wr_en0[0] & _T_11986; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_11991 = _T_11987 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_14 = _T_11991 | _T_7271; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_12003 = bht_wr_addr0[3:0] == 4'hf; // @[ifu_bp_ctl.scala 520:97]
|
|
wire _T_12004 = bht_wr_en0[0] & _T_12003; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_12008 = _T_12004 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_0_15 = _T_12008 | _T_7280; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_12025 = _T_11749 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_1_0 = _T_12025 | _T_7289; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_12042 = _T_11766 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_1 = _T_12042 | _T_7298; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12059 = _T_11783 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_2 = _T_12059 | _T_7307; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12076 = _T_11800 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_3 = _T_12076 | _T_7316; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12093 = _T_11817 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_4 = _T_12093 | _T_7325; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12110 = _T_11834 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_5 = _T_12110 | _T_7334; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12127 = _T_11851 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_6 = _T_12127 | _T_7343; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12144 = _T_11868 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_7 = _T_12144 | _T_7352; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12161 = _T_11885 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_8 = _T_12161 | _T_7361; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12178 = _T_11902 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_9 = _T_12178 | _T_7370; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12195 = _T_11919 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_10 = _T_12195 | _T_7379; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12212 = _T_11936 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_11 = _T_12212 | _T_7388; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12229 = _T_11953 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_12 = _T_12229 | _T_7397; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12246 = _T_11970 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_13 = _T_12246 | _T_7406; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12263 = _T_11987 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_14 = _T_12263 | _T_7415; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12280 = _T_12004 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_1_15 = _T_12280 | _T_7424; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12297 = _T_11749 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_0 = _T_12297 | _T_7433; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12314 = _T_11766 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_1 = _T_12314 | _T_7442; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12331 = _T_11783 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_2 = _T_12331 | _T_7451; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12348 = _T_11800 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_3 = _T_12348 | _T_7460; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12365 = _T_11817 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_4 = _T_12365 | _T_7469; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12382 = _T_11834 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_5 = _T_12382 | _T_7478; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12399 = _T_11851 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_6 = _T_12399 | _T_7487; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12416 = _T_11868 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_7 = _T_12416 | _T_7496; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12433 = _T_11885 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_8 = _T_12433 | _T_7505; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12450 = _T_11902 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_9 = _T_12450 | _T_7514; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12467 = _T_11919 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_10 = _T_12467 | _T_7523; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12484 = _T_11936 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_11 = _T_12484 | _T_7532; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12501 = _T_11953 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_12 = _T_12501 | _T_7541; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12518 = _T_11970 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_13 = _T_12518 | _T_7550; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12535 = _T_11987 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_14 = _T_12535 | _T_7559; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12552 = _T_12004 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_2_15 = _T_12552 | _T_7568; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12569 = _T_11749 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_0 = _T_12569 | _T_7577; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12586 = _T_11766 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_1 = _T_12586 | _T_7586; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12603 = _T_11783 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_2 = _T_12603 | _T_7595; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12620 = _T_11800 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_3 = _T_12620 | _T_7604; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12637 = _T_11817 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_4 = _T_12637 | _T_7613; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12654 = _T_11834 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_5 = _T_12654 | _T_7622; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12671 = _T_11851 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_6 = _T_12671 | _T_7631; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12688 = _T_11868 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_7 = _T_12688 | _T_7640; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12705 = _T_11885 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_8 = _T_12705 | _T_7649; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12722 = _T_11902 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_9 = _T_12722 | _T_7658; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12739 = _T_11919 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_10 = _T_12739 | _T_7667; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12756 = _T_11936 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_11 = _T_12756 | _T_7676; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12773 = _T_11953 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_12 = _T_12773 | _T_7685; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12790 = _T_11970 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_13 = _T_12790 | _T_7694; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12807 = _T_11987 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_14 = _T_12807 | _T_7703; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12824 = _T_12004 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_3_15 = _T_12824 | _T_7712; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12841 = _T_11749 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_0 = _T_12841 | _T_7721; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12858 = _T_11766 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_1 = _T_12858 | _T_7730; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12875 = _T_11783 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_2 = _T_12875 | _T_7739; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12892 = _T_11800 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_3 = _T_12892 | _T_7748; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12909 = _T_11817 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_4 = _T_12909 | _T_7757; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12926 = _T_11834 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_5 = _T_12926 | _T_7766; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12943 = _T_11851 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_6 = _T_12943 | _T_7775; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12960 = _T_11868 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_7 = _T_12960 | _T_7784; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12977 = _T_11885 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_8 = _T_12977 | _T_7793; // @[ifu_bp_ctl.scala 520:223]
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wire _T_12994 = _T_11902 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_9 = _T_12994 | _T_7802; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13011 = _T_11919 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_10 = _T_13011 | _T_7811; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13028 = _T_11936 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_11 = _T_13028 | _T_7820; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13045 = _T_11953 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_12 = _T_13045 | _T_7829; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13062 = _T_11970 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_13 = _T_13062 | _T_7838; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13079 = _T_11987 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_14 = _T_13079 | _T_7847; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13096 = _T_12004 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_4_15 = _T_13096 | _T_7856; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13113 = _T_11749 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_0 = _T_13113 | _T_7865; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13130 = _T_11766 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_1 = _T_13130 | _T_7874; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13147 = _T_11783 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_2 = _T_13147 | _T_7883; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13164 = _T_11800 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_3 = _T_13164 | _T_7892; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13181 = _T_11817 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_4 = _T_13181 | _T_7901; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13198 = _T_11834 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_5 = _T_13198 | _T_7910; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13215 = _T_11851 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_6 = _T_13215 | _T_7919; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13232 = _T_11868 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_7 = _T_13232 | _T_7928; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13249 = _T_11885 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_8 = _T_13249 | _T_7937; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13266 = _T_11902 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_9 = _T_13266 | _T_7946; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13283 = _T_11919 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_10 = _T_13283 | _T_7955; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13300 = _T_11936 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_11 = _T_13300 | _T_7964; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13317 = _T_11953 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_12 = _T_13317 | _T_7973; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13334 = _T_11970 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_13 = _T_13334 | _T_7982; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13351 = _T_11987 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_14 = _T_13351 | _T_7991; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13368 = _T_12004 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_5_15 = _T_13368 | _T_8000; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13385 = _T_11749 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_0 = _T_13385 | _T_8009; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13402 = _T_11766 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_1 = _T_13402 | _T_8018; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13419 = _T_11783 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_2 = _T_13419 | _T_8027; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13436 = _T_11800 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_3 = _T_13436 | _T_8036; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_13453 = _T_11817 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_4 = _T_13453 | _T_8045; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13470 = _T_11834 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_5 = _T_13470 | _T_8054; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_13487 = _T_11851 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_6 = _T_13487 | _T_8063; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_13504 = _T_11868 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_7 = _T_13504 | _T_8072; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13521 = _T_11885 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_8 = _T_13521 | _T_8081; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13538 = _T_11902 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_6_9 = _T_13538 | _T_8090; // @[ifu_bp_ctl.scala 520:223]
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wire _T_13555 = _T_11919 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_0_6_10 = _T_13555 | _T_8099; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13572 = _T_11936 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_6_11 = _T_13572 | _T_8108; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13589 = _T_11953 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_6_12 = _T_13589 | _T_8117; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13606 = _T_11970 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_6_13 = _T_13606 | _T_8126; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13623 = _T_11987 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_6_14 = _T_13623 | _T_8135; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13640 = _T_12004 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_6_15 = _T_13640 | _T_8144; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13657 = _T_11749 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_0 = _T_13657 | _T_8153; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13674 = _T_11766 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_1 = _T_13674 | _T_8162; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13691 = _T_11783 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_2 = _T_13691 | _T_8171; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13708 = _T_11800 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_3 = _T_13708 | _T_8180; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13725 = _T_11817 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_4 = _T_13725 | _T_8189; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13742 = _T_11834 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_5 = _T_13742 | _T_8198; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13759 = _T_11851 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_6 = _T_13759 | _T_8207; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13776 = _T_11868 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_7 = _T_13776 | _T_8216; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13793 = _T_11885 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_8 = _T_13793 | _T_8225; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13810 = _T_11902 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_9 = _T_13810 | _T_8234; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13827 = _T_11919 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_10 = _T_13827 | _T_8243; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13844 = _T_11936 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_11 = _T_13844 | _T_8252; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13861 = _T_11953 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_12 = _T_13861 | _T_8261; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13878 = _T_11970 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_13 = _T_13878 | _T_8270; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13895 = _T_11987 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_14 = _T_13895 | _T_8279; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13912 = _T_12004 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_7_15 = _T_13912 | _T_8288; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13929 = _T_11749 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_0 = _T_13929 | _T_8297; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13946 = _T_11766 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_1 = _T_13946 | _T_8306; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13963 = _T_11783 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_2 = _T_13963 | _T_8315; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13980 = _T_11800 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_3 = _T_13980 | _T_8324; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_13997 = _T_11817 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_4 = _T_13997 | _T_8333; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14014 = _T_11834 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_5 = _T_14014 | _T_8342; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14031 = _T_11851 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_6 = _T_14031 | _T_8351; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14048 = _T_11868 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_7 = _T_14048 | _T_8360; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14065 = _T_11885 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_8 = _T_14065 | _T_8369; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14082 = _T_11902 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_9 = _T_14082 | _T_8378; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14099 = _T_11919 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_10 = _T_14099 | _T_8387; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14116 = _T_11936 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_11 = _T_14116 | _T_8396; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14133 = _T_11953 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_12 = _T_14133 | _T_8405; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14150 = _T_11970 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_13 = _T_14150 | _T_8414; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14167 = _T_11987 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_14 = _T_14167 | _T_8423; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14184 = _T_12004 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_8_15 = _T_14184 | _T_8432; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14201 = _T_11749 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_0 = _T_14201 | _T_8441; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14218 = _T_11766 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_1 = _T_14218 | _T_8450; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14235 = _T_11783 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_2 = _T_14235 | _T_8459; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14252 = _T_11800 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_3 = _T_14252 | _T_8468; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14269 = _T_11817 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_4 = _T_14269 | _T_8477; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14286 = _T_11834 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_5 = _T_14286 | _T_8486; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14303 = _T_11851 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_6 = _T_14303 | _T_8495; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14320 = _T_11868 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_7 = _T_14320 | _T_8504; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14337 = _T_11885 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_8 = _T_14337 | _T_8513; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14354 = _T_11902 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_9 = _T_14354 | _T_8522; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14371 = _T_11919 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_10 = _T_14371 | _T_8531; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14388 = _T_11936 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_11 = _T_14388 | _T_8540; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14405 = _T_11953 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_12 = _T_14405 | _T_8549; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14422 = _T_11970 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_13 = _T_14422 | _T_8558; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14439 = _T_11987 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_14 = _T_14439 | _T_8567; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14456 = _T_12004 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_9_15 = _T_14456 | _T_8576; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14473 = _T_11749 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_0 = _T_14473 | _T_8585; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14490 = _T_11766 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_1 = _T_14490 | _T_8594; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14507 = _T_11783 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_2 = _T_14507 | _T_8603; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14524 = _T_11800 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_3 = _T_14524 | _T_8612; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14541 = _T_11817 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_4 = _T_14541 | _T_8621; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14558 = _T_11834 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_5 = _T_14558 | _T_8630; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14575 = _T_11851 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_6 = _T_14575 | _T_8639; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14592 = _T_11868 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_7 = _T_14592 | _T_8648; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14609 = _T_11885 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_8 = _T_14609 | _T_8657; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14626 = _T_11902 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_9 = _T_14626 | _T_8666; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14643 = _T_11919 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_10 = _T_14643 | _T_8675; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14660 = _T_11936 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_11 = _T_14660 | _T_8684; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14677 = _T_11953 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_12 = _T_14677 | _T_8693; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14694 = _T_11970 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_13 = _T_14694 | _T_8702; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14711 = _T_11987 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_14 = _T_14711 | _T_8711; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14728 = _T_12004 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_10_15 = _T_14728 | _T_8720; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14745 = _T_11749 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_0 = _T_14745 | _T_8729; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14762 = _T_11766 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_1 = _T_14762 | _T_8738; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14779 = _T_11783 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_2 = _T_14779 | _T_8747; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14796 = _T_11800 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_3 = _T_14796 | _T_8756; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14813 = _T_11817 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_4 = _T_14813 | _T_8765; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14830 = _T_11834 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_5 = _T_14830 | _T_8774; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14847 = _T_11851 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_6 = _T_14847 | _T_8783; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14864 = _T_11868 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_7 = _T_14864 | _T_8792; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14881 = _T_11885 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_8 = _T_14881 | _T_8801; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14898 = _T_11902 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_9 = _T_14898 | _T_8810; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14915 = _T_11919 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_10 = _T_14915 | _T_8819; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14932 = _T_11936 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_11 = _T_14932 | _T_8828; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14949 = _T_11953 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_12 = _T_14949 | _T_8837; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14966 = _T_11970 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_13 = _T_14966 | _T_8846; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_14983 = _T_11987 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_14 = _T_14983 | _T_8855; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15000 = _T_12004 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_11_15 = _T_15000 | _T_8864; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15017 = _T_11749 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_12_0 = _T_15017 | _T_8873; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15034 = _T_11766 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_12_1 = _T_15034 | _T_8882; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15051 = _T_11783 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_12_2 = _T_15051 | _T_8891; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15068 = _T_11800 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_0_12_3 = _T_15068 | _T_8900; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_15085 = _T_11817 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_4 = _T_15085 | _T_8909; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15102 = _T_11834 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_5 = _T_15102 | _T_8918; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15119 = _T_11851 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_6 = _T_15119 | _T_8927; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15136 = _T_11868 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_7 = _T_15136 | _T_8936; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15153 = _T_11885 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_8 = _T_15153 | _T_8945; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15170 = _T_11902 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_9 = _T_15170 | _T_8954; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15187 = _T_11919 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_10 = _T_15187 | _T_8963; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15204 = _T_11936 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_11 = _T_15204 | _T_8972; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15221 = _T_11953 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_12 = _T_15221 | _T_8981; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15238 = _T_11970 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_13 = _T_15238 | _T_8990; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15255 = _T_11987 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_14 = _T_15255 | _T_8999; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15272 = _T_12004 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_12_15 = _T_15272 | _T_9008; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15289 = _T_11749 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_0 = _T_15289 | _T_9017; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15306 = _T_11766 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_1 = _T_15306 | _T_9026; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15323 = _T_11783 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_2 = _T_15323 | _T_9035; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15340 = _T_11800 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_3 = _T_15340 | _T_9044; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15357 = _T_11817 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_4 = _T_15357 | _T_9053; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15374 = _T_11834 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_5 = _T_15374 | _T_9062; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_15391 = _T_11851 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_6 = _T_15391 | _T_9071; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_15408 = _T_11868 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_7 = _T_15408 | _T_9080; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15425 = _T_11885 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_8 = _T_15425 | _T_9089; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15442 = _T_11902 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_9 = _T_15442 | _T_9098; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_15459 = _T_11919 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_10 = _T_15459 | _T_9107; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15476 = _T_11936 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_11 = _T_15476 | _T_9116; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15493 = _T_11953 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_12 = _T_15493 | _T_9125; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15510 = _T_11970 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_13 = _T_15510 | _T_9134; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15527 = _T_11987 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_14 = _T_15527 | _T_9143; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15544 = _T_12004 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_13_15 = _T_15544 | _T_9152; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15561 = _T_11749 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_0 = _T_15561 | _T_9161; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15578 = _T_11766 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_1 = _T_15578 | _T_9170; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15595 = _T_11783 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_2 = _T_15595 | _T_9179; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15612 = _T_11800 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_3 = _T_15612 | _T_9188; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15629 = _T_11817 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_4 = _T_15629 | _T_9197; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15646 = _T_11834 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_5 = _T_15646 | _T_9206; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15663 = _T_11851 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_6 = _T_15663 | _T_9215; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15680 = _T_11868 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_7 = _T_15680 | _T_9224; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15697 = _T_11885 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_8 = _T_15697 | _T_9233; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15714 = _T_11902 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_9 = _T_15714 | _T_9242; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15731 = _T_11919 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_10 = _T_15731 | _T_9251; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15748 = _T_11936 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_11 = _T_15748 | _T_9260; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15765 = _T_11953 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_12 = _T_15765 | _T_9269; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15782 = _T_11970 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_13 = _T_15782 | _T_9278; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15799 = _T_11987 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_14 = _T_15799 | _T_9287; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15816 = _T_12004 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_14_15 = _T_15816 | _T_9296; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15833 = _T_11749 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_0 = _T_15833 | _T_9305; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15850 = _T_11766 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_1 = _T_15850 | _T_9314; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15867 = _T_11783 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_2 = _T_15867 | _T_9323; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15884 = _T_11800 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_3 = _T_15884 | _T_9332; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15901 = _T_11817 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_4 = _T_15901 | _T_9341; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15918 = _T_11834 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_5 = _T_15918 | _T_9350; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15935 = _T_11851 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_6 = _T_15935 | _T_9359; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15952 = _T_11868 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_7 = _T_15952 | _T_9368; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15969 = _T_11885 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_8 = _T_15969 | _T_9377; // @[ifu_bp_ctl.scala 520:223]
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wire _T_15986 = _T_11902 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_9 = _T_15986 | _T_9386; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16003 = _T_11919 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_10 = _T_16003 | _T_9395; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16020 = _T_11936 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_11 = _T_16020 | _T_9404; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16037 = _T_11953 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_12 = _T_16037 | _T_9413; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16054 = _T_11970 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_13 = _T_16054 | _T_9422; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16071 = _T_11987 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_14 = _T_16071 | _T_9431; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16088 = _T_12004 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_0_15_15 = _T_16088 | _T_9440; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16101 = bht_wr_en0[1] & _T_11748; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16105 = _T_16101 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_0 = _T_16105 | _T_9449; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16118 = bht_wr_en0[1] & _T_11765; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16122 = _T_16118 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_1 = _T_16122 | _T_9458; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16135 = bht_wr_en0[1] & _T_11782; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16139 = _T_16135 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_2 = _T_16139 | _T_9467; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16152 = bht_wr_en0[1] & _T_11799; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16156 = _T_16152 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_3 = _T_16156 | _T_9476; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16169 = bht_wr_en0[1] & _T_11816; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16173 = _T_16169 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_4 = _T_16173 | _T_9485; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16186 = bht_wr_en0[1] & _T_11833; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16190 = _T_16186 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_5 = _T_16190 | _T_9494; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16203 = bht_wr_en0[1] & _T_11850; // @[ifu_bp_ctl.scala 520:45]
|
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wire _T_16207 = _T_16203 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_0_6 = _T_16207 | _T_9503; // @[ifu_bp_ctl.scala 520:223]
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wire _T_16220 = bht_wr_en0[1] & _T_11867; // @[ifu_bp_ctl.scala 520:45]
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wire _T_16224 = _T_16220 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_0_7 = _T_16224 | _T_9512; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_16237 = bht_wr_en0[1] & _T_11884; // @[ifu_bp_ctl.scala 520:45]
|
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wire _T_16241 = _T_16237 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_0_8 = _T_16241 | _T_9521; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_16254 = bht_wr_en0[1] & _T_11901; // @[ifu_bp_ctl.scala 520:45]
|
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wire _T_16258 = _T_16254 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_0_9 = _T_16258 | _T_9530; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_16271 = bht_wr_en0[1] & _T_11918; // @[ifu_bp_ctl.scala 520:45]
|
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wire _T_16275 = _T_16271 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_0_10 = _T_16275 | _T_9539; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16288 = bht_wr_en0[1] & _T_11935; // @[ifu_bp_ctl.scala 520:45]
|
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wire _T_16292 = _T_16288 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_0_11 = _T_16292 | _T_9548; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16305 = bht_wr_en0[1] & _T_11952; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_16309 = _T_16305 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_0_12 = _T_16309 | _T_9557; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16322 = bht_wr_en0[1] & _T_11969; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_16326 = _T_16322 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_0_13 = _T_16326 | _T_9566; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16339 = bht_wr_en0[1] & _T_11986; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_16343 = _T_16339 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_0_14 = _T_16343 | _T_9575; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16356 = bht_wr_en0[1] & _T_12003; // @[ifu_bp_ctl.scala 520:45]
|
|
wire _T_16360 = _T_16356 & _T_6788; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_0_15 = _T_16360 | _T_9584; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16377 = _T_16101 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_0 = _T_16377 | _T_9593; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16394 = _T_16118 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_1 = _T_16394 | _T_9602; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16411 = _T_16135 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_2 = _T_16411 | _T_9611; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16428 = _T_16152 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_3 = _T_16428 | _T_9620; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16445 = _T_16169 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_4 = _T_16445 | _T_9629; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16462 = _T_16186 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_5 = _T_16462 | _T_9638; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16479 = _T_16203 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_6 = _T_16479 | _T_9647; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16496 = _T_16220 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_7 = _T_16496 | _T_9656; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16513 = _T_16237 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_8 = _T_16513 | _T_9665; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16530 = _T_16254 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_9 = _T_16530 | _T_9674; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16547 = _T_16271 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_10 = _T_16547 | _T_9683; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16564 = _T_16288 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_11 = _T_16564 | _T_9692; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16581 = _T_16305 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_12 = _T_16581 | _T_9701; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16598 = _T_16322 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_13 = _T_16598 | _T_9710; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16615 = _T_16339 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_14 = _T_16615 | _T_9719; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16632 = _T_16356 & _T_6799; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_1_15 = _T_16632 | _T_9728; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16649 = _T_16101 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_0 = _T_16649 | _T_9737; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16666 = _T_16118 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_1 = _T_16666 | _T_9746; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16683 = _T_16135 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_2 = _T_16683 | _T_9755; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16700 = _T_16152 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_3 = _T_16700 | _T_9764; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16717 = _T_16169 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_4 = _T_16717 | _T_9773; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16734 = _T_16186 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_5 = _T_16734 | _T_9782; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16751 = _T_16203 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_6 = _T_16751 | _T_9791; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16768 = _T_16220 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_7 = _T_16768 | _T_9800; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16785 = _T_16237 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_8 = _T_16785 | _T_9809; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16802 = _T_16254 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_9 = _T_16802 | _T_9818; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16819 = _T_16271 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_10 = _T_16819 | _T_9827; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16836 = _T_16288 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_11 = _T_16836 | _T_9836; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16853 = _T_16305 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_12 = _T_16853 | _T_9845; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16870 = _T_16322 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_13 = _T_16870 | _T_9854; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16887 = _T_16339 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_14 = _T_16887 | _T_9863; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16904 = _T_16356 & _T_6810; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_2_15 = _T_16904 | _T_9872; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16921 = _T_16101 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_0 = _T_16921 | _T_9881; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16938 = _T_16118 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_1 = _T_16938 | _T_9890; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16955 = _T_16135 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_2 = _T_16955 | _T_9899; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16972 = _T_16152 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_3 = _T_16972 | _T_9908; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_16989 = _T_16169 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_4 = _T_16989 | _T_9917; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17006 = _T_16186 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_5 = _T_17006 | _T_9926; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17023 = _T_16203 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_6 = _T_17023 | _T_9935; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17040 = _T_16220 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_7 = _T_17040 | _T_9944; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17057 = _T_16237 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_8 = _T_17057 | _T_9953; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17074 = _T_16254 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_9 = _T_17074 | _T_9962; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17091 = _T_16271 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_10 = _T_17091 | _T_9971; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17108 = _T_16288 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_11 = _T_17108 | _T_9980; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17125 = _T_16305 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_12 = _T_17125 | _T_9989; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17142 = _T_16322 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_13 = _T_17142 | _T_9998; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17159 = _T_16339 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_14 = _T_17159 | _T_10007; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17176 = _T_16356 & _T_6821; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_3_15 = _T_17176 | _T_10016; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17193 = _T_16101 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_0 = _T_17193 | _T_10025; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17210 = _T_16118 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_1 = _T_17210 | _T_10034; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17227 = _T_16135 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_2 = _T_17227 | _T_10043; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17244 = _T_16152 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_3 = _T_17244 | _T_10052; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17261 = _T_16169 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_4 = _T_17261 | _T_10061; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17278 = _T_16186 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_5 = _T_17278 | _T_10070; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17295 = _T_16203 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_6 = _T_17295 | _T_10079; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17312 = _T_16220 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_7 = _T_17312 | _T_10088; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17329 = _T_16237 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_8 = _T_17329 | _T_10097; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17346 = _T_16254 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_9 = _T_17346 | _T_10106; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17363 = _T_16271 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_10 = _T_17363 | _T_10115; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17380 = _T_16288 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_11 = _T_17380 | _T_10124; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17397 = _T_16305 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_12 = _T_17397 | _T_10133; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17414 = _T_16322 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_13 = _T_17414 | _T_10142; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17431 = _T_16339 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_14 = _T_17431 | _T_10151; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17448 = _T_16356 & _T_6832; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_4_15 = _T_17448 | _T_10160; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17465 = _T_16101 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_0 = _T_17465 | _T_10169; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17482 = _T_16118 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_1 = _T_17482 | _T_10178; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17499 = _T_16135 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_2 = _T_17499 | _T_10187; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17516 = _T_16152 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_3 = _T_17516 | _T_10196; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17533 = _T_16169 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_4 = _T_17533 | _T_10205; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17550 = _T_16186 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_5 = _T_17550 | _T_10214; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17567 = _T_16203 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_6 = _T_17567 | _T_10223; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17584 = _T_16220 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_7 = _T_17584 | _T_10232; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17601 = _T_16237 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_8 = _T_17601 | _T_10241; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17618 = _T_16254 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_9 = _T_17618 | _T_10250; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17635 = _T_16271 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_10 = _T_17635 | _T_10259; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17652 = _T_16288 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_11 = _T_17652 | _T_10268; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17669 = _T_16305 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_12 = _T_17669 | _T_10277; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17686 = _T_16322 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_13 = _T_17686 | _T_10286; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17703 = _T_16339 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_14 = _T_17703 | _T_10295; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17720 = _T_16356 & _T_6843; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_5_15 = _T_17720 | _T_10304; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17737 = _T_16101 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_0 = _T_17737 | _T_10313; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17754 = _T_16118 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_1 = _T_17754 | _T_10322; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17771 = _T_16135 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_2 = _T_17771 | _T_10331; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17788 = _T_16152 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_3 = _T_17788 | _T_10340; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17805 = _T_16169 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_4 = _T_17805 | _T_10349; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17822 = _T_16186 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_5 = _T_17822 | _T_10358; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17839 = _T_16203 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_6 = _T_17839 | _T_10367; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17856 = _T_16220 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_7 = _T_17856 | _T_10376; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17873 = _T_16237 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_8 = _T_17873 | _T_10385; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17890 = _T_16254 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_9 = _T_17890 | _T_10394; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17907 = _T_16271 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_10 = _T_17907 | _T_10403; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17924 = _T_16288 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_11 = _T_17924 | _T_10412; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17941 = _T_16305 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_12 = _T_17941 | _T_10421; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17958 = _T_16322 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_13 = _T_17958 | _T_10430; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17975 = _T_16339 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_6_14 = _T_17975 | _T_10439; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_17992 = _T_16356 & _T_6854; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_6_15 = _T_17992 | _T_10448; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18009 = _T_16101 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_0 = _T_18009 | _T_10457; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18026 = _T_16118 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_1 = _T_18026 | _T_10466; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18043 = _T_16135 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_2 = _T_18043 | _T_10475; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18060 = _T_16152 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_3 = _T_18060 | _T_10484; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18077 = _T_16169 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_4 = _T_18077 | _T_10493; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18094 = _T_16186 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_5 = _T_18094 | _T_10502; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18111 = _T_16203 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_6 = _T_18111 | _T_10511; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18128 = _T_16220 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_7 = _T_18128 | _T_10520; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18145 = _T_16237 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_8 = _T_18145 | _T_10529; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18162 = _T_16254 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_9 = _T_18162 | _T_10538; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18179 = _T_16271 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_10 = _T_18179 | _T_10547; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18196 = _T_16288 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_11 = _T_18196 | _T_10556; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18213 = _T_16305 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_12 = _T_18213 | _T_10565; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18230 = _T_16322 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_13 = _T_18230 | _T_10574; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18247 = _T_16339 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_14 = _T_18247 | _T_10583; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18264 = _T_16356 & _T_6865; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_7_15 = _T_18264 | _T_10592; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18281 = _T_16101 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_0 = _T_18281 | _T_10601; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18298 = _T_16118 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_1 = _T_18298 | _T_10610; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18315 = _T_16135 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_2 = _T_18315 | _T_10619; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18332 = _T_16152 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_3 = _T_18332 | _T_10628; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18349 = _T_16169 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_4 = _T_18349 | _T_10637; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18366 = _T_16186 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_5 = _T_18366 | _T_10646; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18383 = _T_16203 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_6 = _T_18383 | _T_10655; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18400 = _T_16220 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_7 = _T_18400 | _T_10664; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18417 = _T_16237 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_8 = _T_18417 | _T_10673; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18434 = _T_16254 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_9 = _T_18434 | _T_10682; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18451 = _T_16271 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_10 = _T_18451 | _T_10691; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18468 = _T_16288 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_11 = _T_18468 | _T_10700; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18485 = _T_16305 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_12 = _T_18485 | _T_10709; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18502 = _T_16322 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_13 = _T_18502 | _T_10718; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18519 = _T_16339 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_14 = _T_18519 | _T_10727; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18536 = _T_16356 & _T_6876; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_8_15 = _T_18536 | _T_10736; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18553 = _T_16101 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_0 = _T_18553 | _T_10745; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18570 = _T_16118 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_1 = _T_18570 | _T_10754; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18587 = _T_16135 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_2 = _T_18587 | _T_10763; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18604 = _T_16152 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_3 = _T_18604 | _T_10772; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18621 = _T_16169 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_4 = _T_18621 | _T_10781; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18638 = _T_16186 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_5 = _T_18638 | _T_10790; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18655 = _T_16203 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_6 = _T_18655 | _T_10799; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18672 = _T_16220 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_7 = _T_18672 | _T_10808; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18689 = _T_16237 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_8 = _T_18689 | _T_10817; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18706 = _T_16254 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_9 = _T_18706 | _T_10826; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18723 = _T_16271 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_10 = _T_18723 | _T_10835; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18740 = _T_16288 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_11 = _T_18740 | _T_10844; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18757 = _T_16305 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_12 = _T_18757 | _T_10853; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18774 = _T_16322 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_13 = _T_18774 | _T_10862; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18791 = _T_16339 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_14 = _T_18791 | _T_10871; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18808 = _T_16356 & _T_6887; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_9_15 = _T_18808 | _T_10880; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18825 = _T_16101 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_0 = _T_18825 | _T_10889; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18842 = _T_16118 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_1 = _T_18842 | _T_10898; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18859 = _T_16135 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_2 = _T_18859 | _T_10907; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18876 = _T_16152 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_3 = _T_18876 | _T_10916; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18893 = _T_16169 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_4 = _T_18893 | _T_10925; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18910 = _T_16186 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_5 = _T_18910 | _T_10934; // @[ifu_bp_ctl.scala 520:223]
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wire _T_18927 = _T_16203 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
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wire bht_bank_sel_1_10_6 = _T_18927 | _T_10943; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18944 = _T_16220 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_7 = _T_18944 | _T_10952; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18961 = _T_16237 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_8 = _T_18961 | _T_10961; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18978 = _T_16254 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_9 = _T_18978 | _T_10970; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_18995 = _T_16271 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_10 = _T_18995 | _T_10979; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19012 = _T_16288 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_11 = _T_19012 | _T_10988; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19029 = _T_16305 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_12 = _T_19029 | _T_10997; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19046 = _T_16322 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_13 = _T_19046 | _T_11006; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19063 = _T_16339 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_14 = _T_19063 | _T_11015; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19080 = _T_16356 & _T_6898; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_10_15 = _T_19080 | _T_11024; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19097 = _T_16101 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_11_0 = _T_19097 | _T_11033; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19114 = _T_16118 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_11_1 = _T_19114 | _T_11042; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19131 = _T_16135 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_11_2 = _T_19131 | _T_11051; // @[ifu_bp_ctl.scala 520:223]
|
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wire _T_19148 = _T_16152 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
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wire bht_bank_sel_1_11_3 = _T_19148 | _T_11060; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19165 = _T_16169 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_4 = _T_19165 | _T_11069; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19182 = _T_16186 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_5 = _T_19182 | _T_11078; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19199 = _T_16203 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_6 = _T_19199 | _T_11087; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19216 = _T_16220 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_7 = _T_19216 | _T_11096; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19233 = _T_16237 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_8 = _T_19233 | _T_11105; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19250 = _T_16254 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_9 = _T_19250 | _T_11114; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19267 = _T_16271 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_10 = _T_19267 | _T_11123; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19284 = _T_16288 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_11 = _T_19284 | _T_11132; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19301 = _T_16305 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_12 = _T_19301 | _T_11141; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19318 = _T_16322 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_13 = _T_19318 | _T_11150; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19335 = _T_16339 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_14 = _T_19335 | _T_11159; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19352 = _T_16356 & _T_6909; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_11_15 = _T_19352 | _T_11168; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19369 = _T_16101 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_0 = _T_19369 | _T_11177; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19386 = _T_16118 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_1 = _T_19386 | _T_11186; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19403 = _T_16135 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_2 = _T_19403 | _T_11195; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19420 = _T_16152 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_3 = _T_19420 | _T_11204; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19437 = _T_16169 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_4 = _T_19437 | _T_11213; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19454 = _T_16186 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_5 = _T_19454 | _T_11222; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19471 = _T_16203 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_6 = _T_19471 | _T_11231; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19488 = _T_16220 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_7 = _T_19488 | _T_11240; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19505 = _T_16237 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_8 = _T_19505 | _T_11249; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19522 = _T_16254 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_9 = _T_19522 | _T_11258; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19539 = _T_16271 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_10 = _T_19539 | _T_11267; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19556 = _T_16288 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_11 = _T_19556 | _T_11276; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19573 = _T_16305 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_12 = _T_19573 | _T_11285; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19590 = _T_16322 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_13 = _T_19590 | _T_11294; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19607 = _T_16339 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_14 = _T_19607 | _T_11303; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19624 = _T_16356 & _T_6920; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_12_15 = _T_19624 | _T_11312; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19641 = _T_16101 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_0 = _T_19641 | _T_11321; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19658 = _T_16118 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_1 = _T_19658 | _T_11330; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19675 = _T_16135 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_2 = _T_19675 | _T_11339; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19692 = _T_16152 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_3 = _T_19692 | _T_11348; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19709 = _T_16169 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_4 = _T_19709 | _T_11357; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19726 = _T_16186 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_5 = _T_19726 | _T_11366; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19743 = _T_16203 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_6 = _T_19743 | _T_11375; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19760 = _T_16220 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_7 = _T_19760 | _T_11384; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19777 = _T_16237 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_8 = _T_19777 | _T_11393; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19794 = _T_16254 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_9 = _T_19794 | _T_11402; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19811 = _T_16271 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_10 = _T_19811 | _T_11411; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19828 = _T_16288 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_11 = _T_19828 | _T_11420; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19845 = _T_16305 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_12 = _T_19845 | _T_11429; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19862 = _T_16322 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_13 = _T_19862 | _T_11438; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19879 = _T_16339 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_14 = _T_19879 | _T_11447; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19896 = _T_16356 & _T_6931; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_13_15 = _T_19896 | _T_11456; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19913 = _T_16101 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_0 = _T_19913 | _T_11465; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19930 = _T_16118 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_1 = _T_19930 | _T_11474; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19947 = _T_16135 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_2 = _T_19947 | _T_11483; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19964 = _T_16152 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_3 = _T_19964 | _T_11492; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19981 = _T_16169 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_4 = _T_19981 | _T_11501; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_19998 = _T_16186 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_5 = _T_19998 | _T_11510; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20015 = _T_16203 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_6 = _T_20015 | _T_11519; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20032 = _T_16220 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_7 = _T_20032 | _T_11528; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20049 = _T_16237 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_8 = _T_20049 | _T_11537; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20066 = _T_16254 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_9 = _T_20066 | _T_11546; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20083 = _T_16271 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_10 = _T_20083 | _T_11555; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20100 = _T_16288 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_11 = _T_20100 | _T_11564; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20117 = _T_16305 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_12 = _T_20117 | _T_11573; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20134 = _T_16322 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_13 = _T_20134 | _T_11582; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20151 = _T_16339 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_14 = _T_20151 | _T_11591; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20168 = _T_16356 & _T_6942; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_14_15 = _T_20168 | _T_11600; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20185 = _T_16101 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_0 = _T_20185 | _T_11609; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20202 = _T_16118 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_1 = _T_20202 | _T_11618; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20219 = _T_16135 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_2 = _T_20219 | _T_11627; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20236 = _T_16152 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_3 = _T_20236 | _T_11636; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20253 = _T_16169 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_4 = _T_20253 | _T_11645; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20270 = _T_16186 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_5 = _T_20270 | _T_11654; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20287 = _T_16203 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_6 = _T_20287 | _T_11663; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20304 = _T_16220 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_7 = _T_20304 | _T_11672; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20321 = _T_16237 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_8 = _T_20321 | _T_11681; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20338 = _T_16254 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_9 = _T_20338 | _T_11690; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20355 = _T_16271 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_10 = _T_20355 | _T_11699; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20372 = _T_16288 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_11 = _T_20372 | _T_11708; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20389 = _T_16305 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_12 = _T_20389 | _T_11717; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20406 = _T_16322 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_13 = _T_20406 | _T_11726; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20423 = _T_16339 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_14 = _T_20423 | _T_11735; // @[ifu_bp_ctl.scala 520:223]
|
|
wire _T_20440 = _T_16356 & _T_6953; // @[ifu_bp_ctl.scala 520:110]
|
|
wire bht_bank_sel_1_15_15 = _T_20440 | _T_11744; // @[ifu_bp_ctl.scala 520:223]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_35 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_35_io_clk),
|
|
.io_en(rvclkhdr_35_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_36 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_36_io_clk),
|
|
.io_en(rvclkhdr_36_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_37 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_37_io_clk),
|
|
.io_en(rvclkhdr_37_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_38 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_38_io_clk),
|
|
.io_en(rvclkhdr_38_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_39 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_39_io_clk),
|
|
.io_en(rvclkhdr_39_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_40 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_40_io_clk),
|
|
.io_en(rvclkhdr_40_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_41 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_41_io_clk),
|
|
.io_en(rvclkhdr_41_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_42 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_42_io_clk),
|
|
.io_en(rvclkhdr_42_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_43 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_43_io_clk),
|
|
.io_en(rvclkhdr_43_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_44 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_44_io_clk),
|
|
.io_en(rvclkhdr_44_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_45 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_45_io_clk),
|
|
.io_en(rvclkhdr_45_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_46 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_46_io_clk),
|
|
.io_en(rvclkhdr_46_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_47 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_47_io_clk),
|
|
.io_en(rvclkhdr_47_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_48 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_48_io_clk),
|
|
.io_en(rvclkhdr_48_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_49 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_49_io_clk),
|
|
.io_en(rvclkhdr_49_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_50 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_50_io_clk),
|
|
.io_en(rvclkhdr_50_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_51 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_51_io_clk),
|
|
.io_en(rvclkhdr_51_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_52 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_52_io_clk),
|
|
.io_en(rvclkhdr_52_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_53 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_53_io_clk),
|
|
.io_en(rvclkhdr_53_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_54 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_54_io_clk),
|
|
.io_en(rvclkhdr_54_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_55 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_55_io_clk),
|
|
.io_en(rvclkhdr_55_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_56 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_56_io_clk),
|
|
.io_en(rvclkhdr_56_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_57 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_57_io_clk),
|
|
.io_en(rvclkhdr_57_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_58 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_58_io_clk),
|
|
.io_en(rvclkhdr_58_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_59 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_59_io_clk),
|
|
.io_en(rvclkhdr_59_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_60 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_60_io_clk),
|
|
.io_en(rvclkhdr_60_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_61 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_61_io_clk),
|
|
.io_en(rvclkhdr_61_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_62 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_62_io_clk),
|
|
.io_en(rvclkhdr_62_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_63 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_63_io_clk),
|
|
.io_en(rvclkhdr_63_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_64 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_64_io_clk),
|
|
.io_en(rvclkhdr_64_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_65 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_65_io_clk),
|
|
.io_en(rvclkhdr_65_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_66 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_66_io_clk),
|
|
.io_en(rvclkhdr_66_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_67 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_67_io_clk),
|
|
.io_en(rvclkhdr_67_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_68 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_68_io_clk),
|
|
.io_en(rvclkhdr_68_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_69 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_69_io_clk),
|
|
.io_en(rvclkhdr_69_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_70 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_70_io_clk),
|
|
.io_en(rvclkhdr_70_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_71 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_71_io_clk),
|
|
.io_en(rvclkhdr_71_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_72 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_72_io_clk),
|
|
.io_en(rvclkhdr_72_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_73 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_73_io_clk),
|
|
.io_en(rvclkhdr_73_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_74 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_74_io_clk),
|
|
.io_en(rvclkhdr_74_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_75 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_75_io_clk),
|
|
.io_en(rvclkhdr_75_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_76 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_76_io_clk),
|
|
.io_en(rvclkhdr_76_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_77 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_77_io_clk),
|
|
.io_en(rvclkhdr_77_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_78 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_78_io_clk),
|
|
.io_en(rvclkhdr_78_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_79 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_79_io_clk),
|
|
.io_en(rvclkhdr_79_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_80 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_80_io_clk),
|
|
.io_en(rvclkhdr_80_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_81 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_81_io_clk),
|
|
.io_en(rvclkhdr_81_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_82 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_82_io_clk),
|
|
.io_en(rvclkhdr_82_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_83 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_83_io_clk),
|
|
.io_en(rvclkhdr_83_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_84 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_84_io_clk),
|
|
.io_en(rvclkhdr_84_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_85 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_85_io_clk),
|
|
.io_en(rvclkhdr_85_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_86 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_86_io_clk),
|
|
.io_en(rvclkhdr_86_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_87 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_87_io_clk),
|
|
.io_en(rvclkhdr_87_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_88 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_88_io_clk),
|
|
.io_en(rvclkhdr_88_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_89 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_89_io_clk),
|
|
.io_en(rvclkhdr_89_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_90 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_90_io_clk),
|
|
.io_en(rvclkhdr_90_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_91 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_91_io_clk),
|
|
.io_en(rvclkhdr_91_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_92 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_92_io_clk),
|
|
.io_en(rvclkhdr_92_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_93 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_93_io_clk),
|
|
.io_en(rvclkhdr_93_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_94 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_94_io_clk),
|
|
.io_en(rvclkhdr_94_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_95 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_95_io_clk),
|
|
.io_en(rvclkhdr_95_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_96 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_96_io_clk),
|
|
.io_en(rvclkhdr_96_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_97 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_97_io_clk),
|
|
.io_en(rvclkhdr_97_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_98 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_98_io_clk),
|
|
.io_en(rvclkhdr_98_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_99 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_99_io_clk),
|
|
.io_en(rvclkhdr_99_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_100 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_100_io_clk),
|
|
.io_en(rvclkhdr_100_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_101 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_101_io_clk),
|
|
.io_en(rvclkhdr_101_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_102 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_102_io_clk),
|
|
.io_en(rvclkhdr_102_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_103 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_103_io_clk),
|
|
.io_en(rvclkhdr_103_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_104 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_104_io_clk),
|
|
.io_en(rvclkhdr_104_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_105 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_105_io_clk),
|
|
.io_en(rvclkhdr_105_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_106 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_106_io_clk),
|
|
.io_en(rvclkhdr_106_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_107 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_107_io_clk),
|
|
.io_en(rvclkhdr_107_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_108 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_108_io_clk),
|
|
.io_en(rvclkhdr_108_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_109 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_109_io_clk),
|
|
.io_en(rvclkhdr_109_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_110 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_110_io_clk),
|
|
.io_en(rvclkhdr_110_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_111 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_111_io_clk),
|
|
.io_en(rvclkhdr_111_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_112 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_112_io_clk),
|
|
.io_en(rvclkhdr_112_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_113 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_113_io_clk),
|
|
.io_en(rvclkhdr_113_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_114 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_114_io_clk),
|
|
.io_en(rvclkhdr_114_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_115 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_115_io_clk),
|
|
.io_en(rvclkhdr_115_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_116 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_116_io_clk),
|
|
.io_en(rvclkhdr_116_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_117 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_117_io_clk),
|
|
.io_en(rvclkhdr_117_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_118 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_118_io_clk),
|
|
.io_en(rvclkhdr_118_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_119 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_119_io_clk),
|
|
.io_en(rvclkhdr_119_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_120 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_120_io_clk),
|
|
.io_en(rvclkhdr_120_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_121 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_121_io_clk),
|
|
.io_en(rvclkhdr_121_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_122 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_122_io_clk),
|
|
.io_en(rvclkhdr_122_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_123 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_123_io_clk),
|
|
.io_en(rvclkhdr_123_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_124 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_124_io_clk),
|
|
.io_en(rvclkhdr_124_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_125 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_125_io_clk),
|
|
.io_en(rvclkhdr_125_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_126 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_126_io_clk),
|
|
.io_en(rvclkhdr_126_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_127 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_127_io_clk),
|
|
.io_en(rvclkhdr_127_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_128 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_128_io_clk),
|
|
.io_en(rvclkhdr_128_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_129 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_129_io_clk),
|
|
.io_en(rvclkhdr_129_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_130 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_130_io_clk),
|
|
.io_en(rvclkhdr_130_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_131 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_131_io_clk),
|
|
.io_en(rvclkhdr_131_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_132 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_132_io_clk),
|
|
.io_en(rvclkhdr_132_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_133 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_133_io_clk),
|
|
.io_en(rvclkhdr_133_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_134 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_134_io_clk),
|
|
.io_en(rvclkhdr_134_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_135 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_135_io_clk),
|
|
.io_en(rvclkhdr_135_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_136 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_136_io_clk),
|
|
.io_en(rvclkhdr_136_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_137 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_137_io_clk),
|
|
.io_en(rvclkhdr_137_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_138 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_138_io_clk),
|
|
.io_en(rvclkhdr_138_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_139 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_139_io_clk),
|
|
.io_en(rvclkhdr_139_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_140 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_140_io_clk),
|
|
.io_en(rvclkhdr_140_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_141 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_141_io_clk),
|
|
.io_en(rvclkhdr_141_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_142 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_142_io_clk),
|
|
.io_en(rvclkhdr_142_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_143 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_143_io_clk),
|
|
.io_en(rvclkhdr_143_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_144 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_144_io_clk),
|
|
.io_en(rvclkhdr_144_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_145 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_145_io_clk),
|
|
.io_en(rvclkhdr_145_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_146 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_146_io_clk),
|
|
.io_en(rvclkhdr_146_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_147 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_147_io_clk),
|
|
.io_en(rvclkhdr_147_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_148 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_148_io_clk),
|
|
.io_en(rvclkhdr_148_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_149 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_149_io_clk),
|
|
.io_en(rvclkhdr_149_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_150 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_150_io_clk),
|
|
.io_en(rvclkhdr_150_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_151 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_151_io_clk),
|
|
.io_en(rvclkhdr_151_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_152 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_152_io_clk),
|
|
.io_en(rvclkhdr_152_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_153 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_153_io_clk),
|
|
.io_en(rvclkhdr_153_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_154 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_154_io_clk),
|
|
.io_en(rvclkhdr_154_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_155 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_155_io_clk),
|
|
.io_en(rvclkhdr_155_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_156 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_156_io_clk),
|
|
.io_en(rvclkhdr_156_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_157 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_157_io_clk),
|
|
.io_en(rvclkhdr_157_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_158 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_158_io_clk),
|
|
.io_en(rvclkhdr_158_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_159 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_159_io_clk),
|
|
.io_en(rvclkhdr_159_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_160 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_160_io_clk),
|
|
.io_en(rvclkhdr_160_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_161 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_161_io_clk),
|
|
.io_en(rvclkhdr_161_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_162 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_162_io_clk),
|
|
.io_en(rvclkhdr_162_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_163 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_163_io_clk),
|
|
.io_en(rvclkhdr_163_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_164 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_164_io_clk),
|
|
.io_en(rvclkhdr_164_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_165 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_165_io_clk),
|
|
.io_en(rvclkhdr_165_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_166 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_166_io_clk),
|
|
.io_en(rvclkhdr_166_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_167 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_167_io_clk),
|
|
.io_en(rvclkhdr_167_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_168 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_168_io_clk),
|
|
.io_en(rvclkhdr_168_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_169 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_169_io_clk),
|
|
.io_en(rvclkhdr_169_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_170 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_170_io_clk),
|
|
.io_en(rvclkhdr_170_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_171 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_171_io_clk),
|
|
.io_en(rvclkhdr_171_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_172 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_172_io_clk),
|
|
.io_en(rvclkhdr_172_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_173 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_173_io_clk),
|
|
.io_en(rvclkhdr_173_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_174 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_174_io_clk),
|
|
.io_en(rvclkhdr_174_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_175 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_175_io_clk),
|
|
.io_en(rvclkhdr_175_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_176 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_176_io_clk),
|
|
.io_en(rvclkhdr_176_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_177 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_177_io_clk),
|
|
.io_en(rvclkhdr_177_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_178 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_178_io_clk),
|
|
.io_en(rvclkhdr_178_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_179 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_179_io_clk),
|
|
.io_en(rvclkhdr_179_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_180 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_180_io_clk),
|
|
.io_en(rvclkhdr_180_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_181 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_181_io_clk),
|
|
.io_en(rvclkhdr_181_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_182 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_182_io_clk),
|
|
.io_en(rvclkhdr_182_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_183 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_183_io_clk),
|
|
.io_en(rvclkhdr_183_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_184 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_184_io_clk),
|
|
.io_en(rvclkhdr_184_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_185 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_185_io_clk),
|
|
.io_en(rvclkhdr_185_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_186 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_186_io_clk),
|
|
.io_en(rvclkhdr_186_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_187 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_187_io_clk),
|
|
.io_en(rvclkhdr_187_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_188 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_188_io_clk),
|
|
.io_en(rvclkhdr_188_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_189 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_189_io_clk),
|
|
.io_en(rvclkhdr_189_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_190 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_190_io_clk),
|
|
.io_en(rvclkhdr_190_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_191 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_191_io_clk),
|
|
.io_en(rvclkhdr_191_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_192 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_192_io_clk),
|
|
.io_en(rvclkhdr_192_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_193 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_193_io_clk),
|
|
.io_en(rvclkhdr_193_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_194 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_194_io_clk),
|
|
.io_en(rvclkhdr_194_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_195 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_195_io_clk),
|
|
.io_en(rvclkhdr_195_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_196 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_196_io_clk),
|
|
.io_en(rvclkhdr_196_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_197 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_197_io_clk),
|
|
.io_en(rvclkhdr_197_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_198 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_198_io_clk),
|
|
.io_en(rvclkhdr_198_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_199 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_199_io_clk),
|
|
.io_en(rvclkhdr_199_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_200 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_200_io_clk),
|
|
.io_en(rvclkhdr_200_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_201 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_201_io_clk),
|
|
.io_en(rvclkhdr_201_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_202 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_202_io_clk),
|
|
.io_en(rvclkhdr_202_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_203 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_203_io_clk),
|
|
.io_en(rvclkhdr_203_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_204 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_204_io_clk),
|
|
.io_en(rvclkhdr_204_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_205 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_205_io_clk),
|
|
.io_en(rvclkhdr_205_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_206 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_206_io_clk),
|
|
.io_en(rvclkhdr_206_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_207 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_207_io_clk),
|
|
.io_en(rvclkhdr_207_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_208 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_208_io_clk),
|
|
.io_en(rvclkhdr_208_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_209 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_209_io_clk),
|
|
.io_en(rvclkhdr_209_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_210 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_210_io_clk),
|
|
.io_en(rvclkhdr_210_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_211 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_211_io_clk),
|
|
.io_en(rvclkhdr_211_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_212 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_212_io_clk),
|
|
.io_en(rvclkhdr_212_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_213 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_213_io_clk),
|
|
.io_en(rvclkhdr_213_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_214 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_214_io_clk),
|
|
.io_en(rvclkhdr_214_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_215 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_215_io_clk),
|
|
.io_en(rvclkhdr_215_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_216 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_216_io_clk),
|
|
.io_en(rvclkhdr_216_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_217 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_217_io_clk),
|
|
.io_en(rvclkhdr_217_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_218 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_218_io_clk),
|
|
.io_en(rvclkhdr_218_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_219 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_219_io_clk),
|
|
.io_en(rvclkhdr_219_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_220 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_220_io_clk),
|
|
.io_en(rvclkhdr_220_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_221 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_221_io_clk),
|
|
.io_en(rvclkhdr_221_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_222 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_222_io_clk),
|
|
.io_en(rvclkhdr_222_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_223 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_223_io_clk),
|
|
.io_en(rvclkhdr_223_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_224 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_224_io_clk),
|
|
.io_en(rvclkhdr_224_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_225 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_225_io_clk),
|
|
.io_en(rvclkhdr_225_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_226 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_226_io_clk),
|
|
.io_en(rvclkhdr_226_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_227 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_227_io_clk),
|
|
.io_en(rvclkhdr_227_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_228 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_228_io_clk),
|
|
.io_en(rvclkhdr_228_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_229 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_229_io_clk),
|
|
.io_en(rvclkhdr_229_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_230 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_230_io_clk),
|
|
.io_en(rvclkhdr_230_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_231 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_231_io_clk),
|
|
.io_en(rvclkhdr_231_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_232 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_232_io_clk),
|
|
.io_en(rvclkhdr_232_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_233 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_233_io_clk),
|
|
.io_en(rvclkhdr_233_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_234 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_234_io_clk),
|
|
.io_en(rvclkhdr_234_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_235 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_235_io_clk),
|
|
.io_en(rvclkhdr_235_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_236 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_236_io_clk),
|
|
.io_en(rvclkhdr_236_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_237 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_237_io_clk),
|
|
.io_en(rvclkhdr_237_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_238 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_238_io_clk),
|
|
.io_en(rvclkhdr_238_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_239 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_239_io_clk),
|
|
.io_en(rvclkhdr_239_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_240 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_240_io_clk),
|
|
.io_en(rvclkhdr_240_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_241 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_241_io_clk),
|
|
.io_en(rvclkhdr_241_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_242 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_242_io_clk),
|
|
.io_en(rvclkhdr_242_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_243 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_243_io_clk),
|
|
.io_en(rvclkhdr_243_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_244 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_244_io_clk),
|
|
.io_en(rvclkhdr_244_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_245 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_245_io_clk),
|
|
.io_en(rvclkhdr_245_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_246 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_246_io_clk),
|
|
.io_en(rvclkhdr_246_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_247 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_247_io_clk),
|
|
.io_en(rvclkhdr_247_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_248 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_248_io_clk),
|
|
.io_en(rvclkhdr_248_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_249 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_249_io_clk),
|
|
.io_en(rvclkhdr_249_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_250 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_250_io_clk),
|
|
.io_en(rvclkhdr_250_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_251 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_251_io_clk),
|
|
.io_en(rvclkhdr_251_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_252 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_252_io_clk),
|
|
.io_en(rvclkhdr_252_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_253 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_253_io_clk),
|
|
.io_en(rvclkhdr_253_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_254 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_254_io_clk),
|
|
.io_en(rvclkhdr_254_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_255 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_255_io_clk),
|
|
.io_en(rvclkhdr_255_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_256 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_256_io_clk),
|
|
.io_en(rvclkhdr_256_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_257 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_257_io_clk),
|
|
.io_en(rvclkhdr_257_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_258 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_258_io_clk),
|
|
.io_en(rvclkhdr_258_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_259 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_259_io_clk),
|
|
.io_en(rvclkhdr_259_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_260 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_260_io_clk),
|
|
.io_en(rvclkhdr_260_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_261 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_261_io_clk),
|
|
.io_en(rvclkhdr_261_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_262 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_262_io_clk),
|
|
.io_en(rvclkhdr_262_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_263 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_263_io_clk),
|
|
.io_en(rvclkhdr_263_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_264 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_264_io_clk),
|
|
.io_en(rvclkhdr_264_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_265 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_265_io_clk),
|
|
.io_en(rvclkhdr_265_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_266 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_266_io_clk),
|
|
.io_en(rvclkhdr_266_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_267 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_267_io_clk),
|
|
.io_en(rvclkhdr_267_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_268 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_268_io_clk),
|
|
.io_en(rvclkhdr_268_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_269 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_269_io_clk),
|
|
.io_en(rvclkhdr_269_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_270 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_270_io_clk),
|
|
.io_en(rvclkhdr_270_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_271 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_271_io_clk),
|
|
.io_en(rvclkhdr_271_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_272 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_272_io_clk),
|
|
.io_en(rvclkhdr_272_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_273 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_273_io_clk),
|
|
.io_en(rvclkhdr_273_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_274 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_274_io_clk),
|
|
.io_en(rvclkhdr_274_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_275 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_275_io_clk),
|
|
.io_en(rvclkhdr_275_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_276 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_276_io_clk),
|
|
.io_en(rvclkhdr_276_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_277 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_277_io_clk),
|
|
.io_en(rvclkhdr_277_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_278 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_278_io_clk),
|
|
.io_en(rvclkhdr_278_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_279 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_279_io_clk),
|
|
.io_en(rvclkhdr_279_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_280 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_280_io_clk),
|
|
.io_en(rvclkhdr_280_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_281 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_281_io_clk),
|
|
.io_en(rvclkhdr_281_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_282 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_282_io_clk),
|
|
.io_en(rvclkhdr_282_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_283 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_283_io_clk),
|
|
.io_en(rvclkhdr_283_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_284 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_284_io_clk),
|
|
.io_en(rvclkhdr_284_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_285 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_285_io_clk),
|
|
.io_en(rvclkhdr_285_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_286 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_286_io_clk),
|
|
.io_en(rvclkhdr_286_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_287 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_287_io_clk),
|
|
.io_en(rvclkhdr_287_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_288 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_288_io_clk),
|
|
.io_en(rvclkhdr_288_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_289 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_289_io_clk),
|
|
.io_en(rvclkhdr_289_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_290 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_290_io_clk),
|
|
.io_en(rvclkhdr_290_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_291 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_291_io_clk),
|
|
.io_en(rvclkhdr_291_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_292 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_292_io_clk),
|
|
.io_en(rvclkhdr_292_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_293 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_293_io_clk),
|
|
.io_en(rvclkhdr_293_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_294 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_294_io_clk),
|
|
.io_en(rvclkhdr_294_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_295 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_295_io_clk),
|
|
.io_en(rvclkhdr_295_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_296 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_296_io_clk),
|
|
.io_en(rvclkhdr_296_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_297 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_297_io_clk),
|
|
.io_en(rvclkhdr_297_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_298 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_298_io_clk),
|
|
.io_en(rvclkhdr_298_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_299 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_299_io_clk),
|
|
.io_en(rvclkhdr_299_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_300 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_300_io_clk),
|
|
.io_en(rvclkhdr_300_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_301 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_301_io_clk),
|
|
.io_en(rvclkhdr_301_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_302 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_302_io_clk),
|
|
.io_en(rvclkhdr_302_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_303 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_303_io_clk),
|
|
.io_en(rvclkhdr_303_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_304 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_304_io_clk),
|
|
.io_en(rvclkhdr_304_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_305 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_305_io_clk),
|
|
.io_en(rvclkhdr_305_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_306 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_306_io_clk),
|
|
.io_en(rvclkhdr_306_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_307 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_307_io_clk),
|
|
.io_en(rvclkhdr_307_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_308 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_308_io_clk),
|
|
.io_en(rvclkhdr_308_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_309 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_309_io_clk),
|
|
.io_en(rvclkhdr_309_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_310 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_310_io_clk),
|
|
.io_en(rvclkhdr_310_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_311 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_311_io_clk),
|
|
.io_en(rvclkhdr_311_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_312 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_312_io_clk),
|
|
.io_en(rvclkhdr_312_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_313 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_313_io_clk),
|
|
.io_en(rvclkhdr_313_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_314 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_314_io_clk),
|
|
.io_en(rvclkhdr_314_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_315 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_315_io_clk),
|
|
.io_en(rvclkhdr_315_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_316 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_316_io_clk),
|
|
.io_en(rvclkhdr_316_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_317 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_317_io_clk),
|
|
.io_en(rvclkhdr_317_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_318 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_318_io_clk),
|
|
.io_en(rvclkhdr_318_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_319 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_319_io_clk),
|
|
.io_en(rvclkhdr_319_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_320 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_320_io_clk),
|
|
.io_en(rvclkhdr_320_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_321 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_321_io_clk),
|
|
.io_en(rvclkhdr_321_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_322 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_322_io_clk),
|
|
.io_en(rvclkhdr_322_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_323 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_323_io_clk),
|
|
.io_en(rvclkhdr_323_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_324 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_324_io_clk),
|
|
.io_en(rvclkhdr_324_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_325 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_325_io_clk),
|
|
.io_en(rvclkhdr_325_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_326 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_326_io_clk),
|
|
.io_en(rvclkhdr_326_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_327 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_327_io_clk),
|
|
.io_en(rvclkhdr_327_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_328 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_328_io_clk),
|
|
.io_en(rvclkhdr_328_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_329 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_329_io_clk),
|
|
.io_en(rvclkhdr_329_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_330 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_330_io_clk),
|
|
.io_en(rvclkhdr_330_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_331 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_331_io_clk),
|
|
.io_en(rvclkhdr_331_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_332 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_332_io_clk),
|
|
.io_en(rvclkhdr_332_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_333 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_333_io_clk),
|
|
.io_en(rvclkhdr_333_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_334 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_334_io_clk),
|
|
.io_en(rvclkhdr_334_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_335 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_335_io_clk),
|
|
.io_en(rvclkhdr_335_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_336 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_336_io_clk),
|
|
.io_en(rvclkhdr_336_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_337 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_337_io_clk),
|
|
.io_en(rvclkhdr_337_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_338 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_338_io_clk),
|
|
.io_en(rvclkhdr_338_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_339 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_339_io_clk),
|
|
.io_en(rvclkhdr_339_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_340 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_340_io_clk),
|
|
.io_en(rvclkhdr_340_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_341 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_341_io_clk),
|
|
.io_en(rvclkhdr_341_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_342 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_342_io_clk),
|
|
.io_en(rvclkhdr_342_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_343 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_343_io_clk),
|
|
.io_en(rvclkhdr_343_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_344 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_344_io_clk),
|
|
.io_en(rvclkhdr_344_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_345 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_345_io_clk),
|
|
.io_en(rvclkhdr_345_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_346 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_346_io_clk),
|
|
.io_en(rvclkhdr_346_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_347 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_347_io_clk),
|
|
.io_en(rvclkhdr_347_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_348 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_348_io_clk),
|
|
.io_en(rvclkhdr_348_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_349 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_349_io_clk),
|
|
.io_en(rvclkhdr_349_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_350 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_350_io_clk),
|
|
.io_en(rvclkhdr_350_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_351 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_351_io_clk),
|
|
.io_en(rvclkhdr_351_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_352 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_352_io_clk),
|
|
.io_en(rvclkhdr_352_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_353 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_353_io_clk),
|
|
.io_en(rvclkhdr_353_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_354 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_354_io_clk),
|
|
.io_en(rvclkhdr_354_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_355 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_355_io_clk),
|
|
.io_en(rvclkhdr_355_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_356 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_356_io_clk),
|
|
.io_en(rvclkhdr_356_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_357 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_357_io_clk),
|
|
.io_en(rvclkhdr_357_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_358 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_358_io_clk),
|
|
.io_en(rvclkhdr_358_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_359 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_359_io_clk),
|
|
.io_en(rvclkhdr_359_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_360 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_360_io_clk),
|
|
.io_en(rvclkhdr_360_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_361 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_361_io_clk),
|
|
.io_en(rvclkhdr_361_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_362 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_362_io_clk),
|
|
.io_en(rvclkhdr_362_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_363 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_363_io_clk),
|
|
.io_en(rvclkhdr_363_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_364 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_364_io_clk),
|
|
.io_en(rvclkhdr_364_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_365 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_365_io_clk),
|
|
.io_en(rvclkhdr_365_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_366 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_366_io_clk),
|
|
.io_en(rvclkhdr_366_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_367 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_367_io_clk),
|
|
.io_en(rvclkhdr_367_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_368 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_368_io_clk),
|
|
.io_en(rvclkhdr_368_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_369 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_369_io_clk),
|
|
.io_en(rvclkhdr_369_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_370 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_370_io_clk),
|
|
.io_en(rvclkhdr_370_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_371 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_371_io_clk),
|
|
.io_en(rvclkhdr_371_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_372 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_372_io_clk),
|
|
.io_en(rvclkhdr_372_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_373 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_373_io_clk),
|
|
.io_en(rvclkhdr_373_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_374 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_374_io_clk),
|
|
.io_en(rvclkhdr_374_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_375 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_375_io_clk),
|
|
.io_en(rvclkhdr_375_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_376 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_376_io_clk),
|
|
.io_en(rvclkhdr_376_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_377 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_377_io_clk),
|
|
.io_en(rvclkhdr_377_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_378 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_378_io_clk),
|
|
.io_en(rvclkhdr_378_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_379 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_379_io_clk),
|
|
.io_en(rvclkhdr_379_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_380 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_380_io_clk),
|
|
.io_en(rvclkhdr_380_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_381 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_381_io_clk),
|
|
.io_en(rvclkhdr_381_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_382 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_382_io_clk),
|
|
.io_en(rvclkhdr_382_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_383 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_383_io_clk),
|
|
.io_en(rvclkhdr_383_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_384 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_384_io_clk),
|
|
.io_en(rvclkhdr_384_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_385 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_385_io_clk),
|
|
.io_en(rvclkhdr_385_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_386 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_386_io_clk),
|
|
.io_en(rvclkhdr_386_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_387 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_387_io_clk),
|
|
.io_en(rvclkhdr_387_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_388 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_388_io_clk),
|
|
.io_en(rvclkhdr_388_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_389 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_389_io_clk),
|
|
.io_en(rvclkhdr_389_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_390 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_390_io_clk),
|
|
.io_en(rvclkhdr_390_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_391 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_391_io_clk),
|
|
.io_en(rvclkhdr_391_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_392 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_392_io_clk),
|
|
.io_en(rvclkhdr_392_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_393 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_393_io_clk),
|
|
.io_en(rvclkhdr_393_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_394 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_394_io_clk),
|
|
.io_en(rvclkhdr_394_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_395 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_395_io_clk),
|
|
.io_en(rvclkhdr_395_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_396 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_396_io_clk),
|
|
.io_en(rvclkhdr_396_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_397 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_397_io_clk),
|
|
.io_en(rvclkhdr_397_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_398 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_398_io_clk),
|
|
.io_en(rvclkhdr_398_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_399 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_399_io_clk),
|
|
.io_en(rvclkhdr_399_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_400 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_400_io_clk),
|
|
.io_en(rvclkhdr_400_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_401 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_401_io_clk),
|
|
.io_en(rvclkhdr_401_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_402 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_402_io_clk),
|
|
.io_en(rvclkhdr_402_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_403 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_403_io_clk),
|
|
.io_en(rvclkhdr_403_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_404 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_404_io_clk),
|
|
.io_en(rvclkhdr_404_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_405 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_405_io_clk),
|
|
.io_en(rvclkhdr_405_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_406 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_406_io_clk),
|
|
.io_en(rvclkhdr_406_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_407 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_407_io_clk),
|
|
.io_en(rvclkhdr_407_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_408 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_408_io_clk),
|
|
.io_en(rvclkhdr_408_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_409 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_409_io_clk),
|
|
.io_en(rvclkhdr_409_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_410 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_410_io_clk),
|
|
.io_en(rvclkhdr_410_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_411 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_411_io_clk),
|
|
.io_en(rvclkhdr_411_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_412 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_412_io_clk),
|
|
.io_en(rvclkhdr_412_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_413 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_413_io_clk),
|
|
.io_en(rvclkhdr_413_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_414 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_414_io_clk),
|
|
.io_en(rvclkhdr_414_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_415 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_415_io_clk),
|
|
.io_en(rvclkhdr_415_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_416 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_416_io_clk),
|
|
.io_en(rvclkhdr_416_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_417 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_417_io_clk),
|
|
.io_en(rvclkhdr_417_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_418 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_418_io_clk),
|
|
.io_en(rvclkhdr_418_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_419 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_419_io_clk),
|
|
.io_en(rvclkhdr_419_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_420 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_420_io_clk),
|
|
.io_en(rvclkhdr_420_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_421 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_421_io_clk),
|
|
.io_en(rvclkhdr_421_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_422 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_422_io_clk),
|
|
.io_en(rvclkhdr_422_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_423 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_423_io_clk),
|
|
.io_en(rvclkhdr_423_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_424 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_424_io_clk),
|
|
.io_en(rvclkhdr_424_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_425 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_425_io_clk),
|
|
.io_en(rvclkhdr_425_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_426 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_426_io_clk),
|
|
.io_en(rvclkhdr_426_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_427 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_427_io_clk),
|
|
.io_en(rvclkhdr_427_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_428 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_428_io_clk),
|
|
.io_en(rvclkhdr_428_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_429 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_429_io_clk),
|
|
.io_en(rvclkhdr_429_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_430 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_430_io_clk),
|
|
.io_en(rvclkhdr_430_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_431 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_431_io_clk),
|
|
.io_en(rvclkhdr_431_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_432 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_432_io_clk),
|
|
.io_en(rvclkhdr_432_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_433 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_433_io_clk),
|
|
.io_en(rvclkhdr_433_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_434 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_434_io_clk),
|
|
.io_en(rvclkhdr_434_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_435 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_435_io_clk),
|
|
.io_en(rvclkhdr_435_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_436 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_436_io_clk),
|
|
.io_en(rvclkhdr_436_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_437 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_437_io_clk),
|
|
.io_en(rvclkhdr_437_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_438 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_438_io_clk),
|
|
.io_en(rvclkhdr_438_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_439 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_439_io_clk),
|
|
.io_en(rvclkhdr_439_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_440 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_440_io_clk),
|
|
.io_en(rvclkhdr_440_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_441 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_441_io_clk),
|
|
.io_en(rvclkhdr_441_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_442 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_442_io_clk),
|
|
.io_en(rvclkhdr_442_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_443 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_443_io_clk),
|
|
.io_en(rvclkhdr_443_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_444 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_444_io_clk),
|
|
.io_en(rvclkhdr_444_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_445 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_445_io_clk),
|
|
.io_en(rvclkhdr_445_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_446 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_446_io_clk),
|
|
.io_en(rvclkhdr_446_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_447 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_447_io_clk),
|
|
.io_en(rvclkhdr_447_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_448 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_448_io_clk),
|
|
.io_en(rvclkhdr_448_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_449 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_449_io_clk),
|
|
.io_en(rvclkhdr_449_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_450 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_450_io_clk),
|
|
.io_en(rvclkhdr_450_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_451 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_451_io_clk),
|
|
.io_en(rvclkhdr_451_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_452 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_452_io_clk),
|
|
.io_en(rvclkhdr_452_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_453 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_453_io_clk),
|
|
.io_en(rvclkhdr_453_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_454 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_454_io_clk),
|
|
.io_en(rvclkhdr_454_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_455 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_455_io_clk),
|
|
.io_en(rvclkhdr_455_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_456 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_456_io_clk),
|
|
.io_en(rvclkhdr_456_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_457 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_457_io_clk),
|
|
.io_en(rvclkhdr_457_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_458 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_458_io_clk),
|
|
.io_en(rvclkhdr_458_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_459 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_459_io_clk),
|
|
.io_en(rvclkhdr_459_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_460 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_460_io_clk),
|
|
.io_en(rvclkhdr_460_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_461 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_461_io_clk),
|
|
.io_en(rvclkhdr_461_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_462 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_462_io_clk),
|
|
.io_en(rvclkhdr_462_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_463 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_463_io_clk),
|
|
.io_en(rvclkhdr_463_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_464 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_464_io_clk),
|
|
.io_en(rvclkhdr_464_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_465 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_465_io_clk),
|
|
.io_en(rvclkhdr_465_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_466 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_466_io_clk),
|
|
.io_en(rvclkhdr_466_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_467 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_467_io_clk),
|
|
.io_en(rvclkhdr_467_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_468 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_468_io_clk),
|
|
.io_en(rvclkhdr_468_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_469 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_469_io_clk),
|
|
.io_en(rvclkhdr_469_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_470 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_470_io_clk),
|
|
.io_en(rvclkhdr_470_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_471 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_471_io_clk),
|
|
.io_en(rvclkhdr_471_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_472 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_472_io_clk),
|
|
.io_en(rvclkhdr_472_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_473 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_473_io_clk),
|
|
.io_en(rvclkhdr_473_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_474 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_474_io_clk),
|
|
.io_en(rvclkhdr_474_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_475 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_475_io_clk),
|
|
.io_en(rvclkhdr_475_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_476 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_476_io_clk),
|
|
.io_en(rvclkhdr_476_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_477 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_477_io_clk),
|
|
.io_en(rvclkhdr_477_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_478 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_478_io_clk),
|
|
.io_en(rvclkhdr_478_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_479 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_479_io_clk),
|
|
.io_en(rvclkhdr_479_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_480 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_480_io_clk),
|
|
.io_en(rvclkhdr_480_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_481 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_481_io_clk),
|
|
.io_en(rvclkhdr_481_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_482 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_482_io_clk),
|
|
.io_en(rvclkhdr_482_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_483 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_483_io_clk),
|
|
.io_en(rvclkhdr_483_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_484 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_484_io_clk),
|
|
.io_en(rvclkhdr_484_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_485 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_485_io_clk),
|
|
.io_en(rvclkhdr_485_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_486 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_486_io_clk),
|
|
.io_en(rvclkhdr_486_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_487 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_487_io_clk),
|
|
.io_en(rvclkhdr_487_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_488 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_488_io_clk),
|
|
.io_en(rvclkhdr_488_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_489 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_489_io_clk),
|
|
.io_en(rvclkhdr_489_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_490 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_490_io_clk),
|
|
.io_en(rvclkhdr_490_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_491 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_491_io_clk),
|
|
.io_en(rvclkhdr_491_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_492 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_492_io_clk),
|
|
.io_en(rvclkhdr_492_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_493 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_493_io_clk),
|
|
.io_en(rvclkhdr_493_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_494 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_494_io_clk),
|
|
.io_en(rvclkhdr_494_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_495 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_495_io_clk),
|
|
.io_en(rvclkhdr_495_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_496 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_496_io_clk),
|
|
.io_en(rvclkhdr_496_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_497 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_497_io_clk),
|
|
.io_en(rvclkhdr_497_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_498 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_498_io_clk),
|
|
.io_en(rvclkhdr_498_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_499 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_499_io_clk),
|
|
.io_en(rvclkhdr_499_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_500 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_500_io_clk),
|
|
.io_en(rvclkhdr_500_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_501 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_501_io_clk),
|
|
.io_en(rvclkhdr_501_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_502 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_502_io_clk),
|
|
.io_en(rvclkhdr_502_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_503 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_503_io_clk),
|
|
.io_en(rvclkhdr_503_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_504 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_504_io_clk),
|
|
.io_en(rvclkhdr_504_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_505 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_505_io_clk),
|
|
.io_en(rvclkhdr_505_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_506 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_506_io_clk),
|
|
.io_en(rvclkhdr_506_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_507 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_507_io_clk),
|
|
.io_en(rvclkhdr_507_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_508 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_508_io_clk),
|
|
.io_en(rvclkhdr_508_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_509 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_509_io_clk),
|
|
.io_en(rvclkhdr_509_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_510 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_510_io_clk),
|
|
.io_en(rvclkhdr_510_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_511 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_511_io_clk),
|
|
.io_en(rvclkhdr_511_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_512 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_512_io_clk),
|
|
.io_en(rvclkhdr_512_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_513 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_513_io_clk),
|
|
.io_en(rvclkhdr_513_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_514 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_514_io_clk),
|
|
.io_en(rvclkhdr_514_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_515 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_515_io_clk),
|
|
.io_en(rvclkhdr_515_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_516 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_516_io_clk),
|
|
.io_en(rvclkhdr_516_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_517 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_517_io_clk),
|
|
.io_en(rvclkhdr_517_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_518 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_518_io_clk),
|
|
.io_en(rvclkhdr_518_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_519 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_519_io_clk),
|
|
.io_en(rvclkhdr_519_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_520 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_520_io_clk),
|
|
.io_en(rvclkhdr_520_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_521 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_521_io_clk),
|
|
.io_en(rvclkhdr_521_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_522 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_522_io_clk),
|
|
.io_en(rvclkhdr_522_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_523 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_523_io_clk),
|
|
.io_en(rvclkhdr_523_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_524 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_524_io_clk),
|
|
.io_en(rvclkhdr_524_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_525 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_525_io_clk),
|
|
.io_en(rvclkhdr_525_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_526 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_526_io_clk),
|
|
.io_en(rvclkhdr_526_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_527 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_527_io_clk),
|
|
.io_en(rvclkhdr_527_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_528 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_528_io_clk),
|
|
.io_en(rvclkhdr_528_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_529 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_529_io_clk),
|
|
.io_en(rvclkhdr_529_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_530 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_530_io_clk),
|
|
.io_en(rvclkhdr_530_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_531 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_531_io_clk),
|
|
.io_en(rvclkhdr_531_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_532 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_532_io_clk),
|
|
.io_en(rvclkhdr_532_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_533 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_533_io_clk),
|
|
.io_en(rvclkhdr_533_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_534 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_534_io_clk),
|
|
.io_en(rvclkhdr_534_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_535 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_535_io_clk),
|
|
.io_en(rvclkhdr_535_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_536 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_536_io_clk),
|
|
.io_en(rvclkhdr_536_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_537 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_537_io_clk),
|
|
.io_en(rvclkhdr_537_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_538 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_538_io_clk),
|
|
.io_en(rvclkhdr_538_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_539 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_539_io_clk),
|
|
.io_en(rvclkhdr_539_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_540 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_540_io_clk),
|
|
.io_en(rvclkhdr_540_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_541 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_541_io_clk),
|
|
.io_en(rvclkhdr_541_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_542 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_542_io_clk),
|
|
.io_en(rvclkhdr_542_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_543 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_543_io_clk),
|
|
.io_en(rvclkhdr_543_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_544 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_544_io_clk),
|
|
.io_en(rvclkhdr_544_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_545 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_545_io_clk),
|
|
.io_en(rvclkhdr_545_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_546 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_546_io_clk),
|
|
.io_en(rvclkhdr_546_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_547 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_547_io_clk),
|
|
.io_en(rvclkhdr_547_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_548 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_548_io_clk),
|
|
.io_en(rvclkhdr_548_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_549 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_549_io_clk),
|
|
.io_en(rvclkhdr_549_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_550 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_550_io_clk),
|
|
.io_en(rvclkhdr_550_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_551 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_551_io_clk),
|
|
.io_en(rvclkhdr_551_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_552 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_552_io_clk),
|
|
.io_en(rvclkhdr_552_io_en)
|
|
);
|
|
assign io_ifu_bp_hit_taken_f = _T_257 & _T_258; // @[ifu_bp_ctl.scala 276:25]
|
|
assign io_ifu_bp_btb_target_f = _T_469 | _T_479; // @[ifu_bp_ctl.scala 373:26]
|
|
assign io_ifu_bp_inst_mask_f = _T_294 | _T_295; // @[ifu_bp_ctl.scala 301:25]
|
|
assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 344:20]
|
|
assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_169; // @[ifu_bp_ctl.scala 253:19]
|
|
assign io_ifu_bp_ret_f = {_T_314,_T_320}; // @[ifu_bp_ctl.scala 350:19]
|
|
assign io_ifu_bp_hist1_f = bht_force_taken_f | _T_299; // @[ifu_bp_ctl.scala 345:21]
|
|
assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 346:21]
|
|
assign io_ifu_bp_pc4_f = {_T_305,_T_308}; // @[ifu_bp_ctl.scala 347:19]
|
|
assign io_ifu_bp_valid_f = bht_valid_f & _T_379; // @[ifu_bp_ctl.scala 349:21]
|
|
assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 361:23]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = ~rs_hold; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = rs_push | rs_pop; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = _T_520 & io_ifu_bp_hit_taken_f; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = _T_642 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = _T_646 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = _T_650 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_12_io_en = _T_654 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_13_io_en = _T_658 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_14_io_en = _T_662 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_15_io_en = _T_666 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_16_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_16_io_en = _T_670 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_17_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_17_io_en = _T_674 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_18_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_18_io_en = _T_678 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_19_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_19_io_en = _T_682 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_20_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_20_io_en = _T_686 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_21_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_21_io_en = _T_690 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_22_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_22_io_en = _T_694 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_23_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_23_io_en = _T_698 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_24_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_24_io_en = _T_702 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_25_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_25_io_en = _T_706 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_26_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_26_io_en = _T_710 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_27_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_27_io_en = _T_714 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_28_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_28_io_en = _T_718 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_29_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_29_io_en = _T_722 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_30_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_30_io_en = _T_726 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_31_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_31_io_en = _T_730 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_32_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_32_io_en = _T_734 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_33_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_33_io_en = _T_738 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_34_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_34_io_en = _T_742 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_35_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_35_io_en = _T_746 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_36_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_36_io_en = _T_750 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_37_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_37_io_en = _T_754 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_38_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_38_io_en = _T_758 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_39_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_39_io_en = _T_762 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_40_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_40_io_en = _T_766 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_41_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_41_io_en = _T_770 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_42_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_42_io_en = _T_774 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_43_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_43_io_en = _T_778 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_44_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_44_io_en = _T_782 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_45_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_45_io_en = _T_786 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_46_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_46_io_en = _T_790 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_47_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_47_io_en = _T_794 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_48_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_48_io_en = _T_798 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_49_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_49_io_en = _T_802 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_50_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_50_io_en = _T_806 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_51_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_51_io_en = _T_810 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_52_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_52_io_en = _T_814 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_53_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_53_io_en = _T_818 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_54_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_54_io_en = _T_822 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_55_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_55_io_en = _T_826 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_56_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_56_io_en = _T_830 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_57_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_57_io_en = _T_834 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_58_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_58_io_en = _T_838 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_59_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_59_io_en = _T_842 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_60_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_60_io_en = _T_846 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_61_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_61_io_en = _T_850 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_62_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_62_io_en = _T_854 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_63_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_63_io_en = _T_858 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_64_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_64_io_en = _T_862 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_65_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_65_io_en = _T_866 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_66_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_66_io_en = _T_870 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_67_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_67_io_en = _T_874 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_68_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_68_io_en = _T_878 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_69_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_69_io_en = _T_882 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_70_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_70_io_en = _T_886 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_71_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_71_io_en = _T_890 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_72_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_72_io_en = _T_894 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_73_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_73_io_en = _T_898 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_74_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_74_io_en = _T_902 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_75_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_75_io_en = _T_906 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_76_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_76_io_en = _T_910 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_77_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_77_io_en = _T_914 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_78_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_78_io_en = _T_918 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_79_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_79_io_en = _T_922 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_80_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_80_io_en = _T_926 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_81_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_81_io_en = _T_930 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_82_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_82_io_en = _T_934 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_83_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_83_io_en = _T_938 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_84_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_84_io_en = _T_942 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_85_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_85_io_en = _T_946 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_86_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_86_io_en = _T_950 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_87_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_87_io_en = _T_954 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_88_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_88_io_en = _T_958 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_89_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_89_io_en = _T_962 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_90_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_90_io_en = _T_966 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_91_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_91_io_en = _T_970 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_92_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_92_io_en = _T_974 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_93_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_93_io_en = _T_978 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_94_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_94_io_en = _T_982 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_95_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_95_io_en = _T_986 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_96_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_96_io_en = _T_990 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_97_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_97_io_en = _T_994 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_98_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_98_io_en = _T_998 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_99_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_99_io_en = _T_1002 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_100_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_100_io_en = _T_1006 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_101_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_101_io_en = _T_1010 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_102_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_102_io_en = _T_1014 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_103_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_103_io_en = _T_1018 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_104_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_104_io_en = _T_1022 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_105_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_105_io_en = _T_1026 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_106_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_106_io_en = _T_1030 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_107_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_107_io_en = _T_1034 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_108_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_108_io_en = _T_1038 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_109_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_109_io_en = _T_1042 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_110_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_110_io_en = _T_1046 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_111_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_111_io_en = _T_1050 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_112_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_112_io_en = _T_1054 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_113_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_113_io_en = _T_1058 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_114_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_114_io_en = _T_1062 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_115_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_115_io_en = _T_1066 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_116_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_116_io_en = _T_1070 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_117_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_117_io_en = _T_1074 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_118_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_118_io_en = _T_1078 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_119_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_119_io_en = _T_1082 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_120_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_120_io_en = _T_1086 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_121_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_121_io_en = _T_1090 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_122_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_122_io_en = _T_1094 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_123_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_123_io_en = _T_1098 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_124_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_124_io_en = _T_1102 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_125_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_125_io_en = _T_1106 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_126_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_126_io_en = _T_1110 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_127_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_127_io_en = _T_1114 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_128_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_128_io_en = _T_1118 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_129_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_129_io_en = _T_1122 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_130_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_130_io_en = _T_1126 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_131_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_131_io_en = _T_1130 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_132_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_132_io_en = _T_1134 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_133_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_133_io_en = _T_1138 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_134_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_134_io_en = _T_1142 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_135_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_135_io_en = _T_1146 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_136_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_136_io_en = _T_1150 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_137_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_137_io_en = _T_1154 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_138_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_138_io_en = _T_1158 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_139_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_139_io_en = _T_1162 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_140_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_140_io_en = _T_1166 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_141_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_141_io_en = _T_1170 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_142_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_142_io_en = _T_1174 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_143_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_143_io_en = _T_1178 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_144_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_144_io_en = _T_1182 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_145_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_145_io_en = _T_1186 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_146_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_146_io_en = _T_1190 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_147_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_147_io_en = _T_1194 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_148_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_148_io_en = _T_1198 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_149_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_149_io_en = _T_1202 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_150_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_150_io_en = _T_1206 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_151_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_151_io_en = _T_1210 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_152_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_152_io_en = _T_1214 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_153_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_153_io_en = _T_1218 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_154_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_154_io_en = _T_1222 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_155_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_155_io_en = _T_1226 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_156_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_156_io_en = _T_1230 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_157_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_157_io_en = _T_1234 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_158_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_158_io_en = _T_1238 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_159_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_159_io_en = _T_1242 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_160_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_160_io_en = _T_1246 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_161_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_161_io_en = _T_1250 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_162_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_162_io_en = _T_1254 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_163_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_163_io_en = _T_1258 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_164_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_164_io_en = _T_1262 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_165_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_165_io_en = _T_1266 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_166_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_166_io_en = _T_1270 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_167_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_167_io_en = _T_1274 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_168_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_168_io_en = _T_1278 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_169_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_169_io_en = _T_1282 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_170_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_170_io_en = _T_1286 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_171_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_171_io_en = _T_1290 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_172_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_172_io_en = _T_1294 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_173_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_173_io_en = _T_1298 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_174_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_174_io_en = _T_1302 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_175_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_175_io_en = _T_1306 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_176_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_176_io_en = _T_1310 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_177_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_177_io_en = _T_1314 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_178_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_178_io_en = _T_1318 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_179_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_179_io_en = _T_1322 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_180_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_180_io_en = _T_1326 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_181_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_181_io_en = _T_1330 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_182_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_182_io_en = _T_1334 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_183_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_183_io_en = _T_1338 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_184_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_184_io_en = _T_1342 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_185_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_185_io_en = _T_1346 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_186_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_186_io_en = _T_1350 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_187_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_187_io_en = _T_1354 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_188_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_188_io_en = _T_1358 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_189_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_189_io_en = _T_1362 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_190_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_190_io_en = _T_1366 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_191_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_191_io_en = _T_1370 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_192_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_192_io_en = _T_1374 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_193_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_193_io_en = _T_1378 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_194_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_194_io_en = _T_1382 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_195_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_195_io_en = _T_1386 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_196_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_196_io_en = _T_1390 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_197_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_197_io_en = _T_1394 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_198_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_198_io_en = _T_1398 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_199_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_199_io_en = _T_1402 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_200_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_200_io_en = _T_1406 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_201_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_201_io_en = _T_1410 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_202_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_202_io_en = _T_1414 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_203_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_203_io_en = _T_1418 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_204_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_204_io_en = _T_1422 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_205_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_205_io_en = _T_1426 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_206_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_206_io_en = _T_1430 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_207_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_207_io_en = _T_1434 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_208_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_208_io_en = _T_1438 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_209_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_209_io_en = _T_1442 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_210_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_210_io_en = _T_1446 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_211_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_211_io_en = _T_1450 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_212_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_212_io_en = _T_1454 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_213_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_213_io_en = _T_1458 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_214_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_214_io_en = _T_1462 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_215_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_215_io_en = _T_1466 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_216_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_216_io_en = _T_1470 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_217_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_217_io_en = _T_1474 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_218_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_218_io_en = _T_1478 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_219_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_219_io_en = _T_1482 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_220_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_220_io_en = _T_1486 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_221_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_221_io_en = _T_1490 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_222_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_222_io_en = _T_1494 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_223_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_223_io_en = _T_1498 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_224_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_224_io_en = _T_1502 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_225_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_225_io_en = _T_1506 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_226_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_226_io_en = _T_1510 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_227_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_227_io_en = _T_1514 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_228_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_228_io_en = _T_1518 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_229_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_229_io_en = _T_1522 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_230_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_230_io_en = _T_1526 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_231_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_231_io_en = _T_1530 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_232_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_232_io_en = _T_1534 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_233_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_233_io_en = _T_1538 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_234_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_234_io_en = _T_1542 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_235_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_235_io_en = _T_1546 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_236_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_236_io_en = _T_1550 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_237_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_237_io_en = _T_1554 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_238_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_238_io_en = _T_1558 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_239_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_239_io_en = _T_1562 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_240_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_240_io_en = _T_1566 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_241_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_241_io_en = _T_1570 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_242_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_242_io_en = _T_1574 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_243_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_243_io_en = _T_1578 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_244_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_244_io_en = _T_1582 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_245_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_245_io_en = _T_1586 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_246_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_246_io_en = _T_1590 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_247_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_247_io_en = _T_1594 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_248_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_248_io_en = _T_1598 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_249_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_249_io_en = _T_1602 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_250_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_250_io_en = _T_1606 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_251_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_251_io_en = _T_1610 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_252_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_252_io_en = _T_1614 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_253_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_253_io_en = _T_1618 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_254_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_254_io_en = _T_1622 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_255_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_255_io_en = _T_1626 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_256_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_256_io_en = _T_1630 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_257_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_257_io_en = _T_1634 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_258_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_258_io_en = _T_1638 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_259_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_259_io_en = _T_1642 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_260_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_260_io_en = _T_1646 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_261_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_261_io_en = _T_1650 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_262_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_262_io_en = _T_1654 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_263_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_263_io_en = _T_1658 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_264_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_264_io_en = _T_1662 & _T_620; // @[lib.scala 425:17]
|
|
assign rvclkhdr_265_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_265_io_en = _T_642 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_266_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_266_io_en = _T_646 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_267_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_267_io_en = _T_650 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_268_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_268_io_en = _T_654 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_269_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_269_io_en = _T_658 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_270_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_270_io_en = _T_662 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_271_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_271_io_en = _T_666 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_272_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_272_io_en = _T_670 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_273_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_273_io_en = _T_674 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_274_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_274_io_en = _T_678 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_275_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_275_io_en = _T_682 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_276_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_276_io_en = _T_686 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_277_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_277_io_en = _T_690 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_278_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_278_io_en = _T_694 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_279_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_279_io_en = _T_698 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_280_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_280_io_en = _T_702 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_281_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_281_io_en = _T_706 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_282_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_282_io_en = _T_710 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_283_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_283_io_en = _T_714 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_284_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_284_io_en = _T_718 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_285_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_285_io_en = _T_722 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_286_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_286_io_en = _T_726 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_287_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_287_io_en = _T_730 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_288_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_288_io_en = _T_734 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_289_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_289_io_en = _T_738 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_290_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_290_io_en = _T_742 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_291_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_291_io_en = _T_746 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_292_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_292_io_en = _T_750 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_293_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_293_io_en = _T_754 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_294_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_294_io_en = _T_758 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_295_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_295_io_en = _T_762 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_296_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_296_io_en = _T_766 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_297_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_297_io_en = _T_770 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_298_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_298_io_en = _T_774 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_299_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_299_io_en = _T_778 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_300_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_300_io_en = _T_782 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_301_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_301_io_en = _T_786 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_302_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_302_io_en = _T_790 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_303_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_303_io_en = _T_794 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_304_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_304_io_en = _T_798 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_305_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_305_io_en = _T_802 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_306_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_306_io_en = _T_806 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_307_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_307_io_en = _T_810 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_308_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_308_io_en = _T_814 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_309_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_309_io_en = _T_818 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_310_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_310_io_en = _T_822 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_311_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_311_io_en = _T_826 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_312_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_312_io_en = _T_830 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_313_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_313_io_en = _T_834 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_314_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_314_io_en = _T_838 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_315_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_315_io_en = _T_842 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_316_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_316_io_en = _T_846 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_317_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_317_io_en = _T_850 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_318_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_318_io_en = _T_854 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_319_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_319_io_en = _T_858 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_320_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_320_io_en = _T_862 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_321_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_321_io_en = _T_866 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_322_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_322_io_en = _T_870 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_323_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_323_io_en = _T_874 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_324_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_324_io_en = _T_878 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_325_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_325_io_en = _T_882 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_326_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_326_io_en = _T_886 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_327_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_327_io_en = _T_890 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_328_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_328_io_en = _T_894 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_329_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_329_io_en = _T_898 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_330_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_330_io_en = _T_902 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_331_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_331_io_en = _T_906 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_332_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_332_io_en = _T_910 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_333_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_333_io_en = _T_914 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_334_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_334_io_en = _T_918 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_335_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_335_io_en = _T_922 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_336_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_336_io_en = _T_926 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_337_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_337_io_en = _T_930 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_338_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_338_io_en = _T_934 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_339_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_339_io_en = _T_938 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_340_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_340_io_en = _T_942 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_341_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_341_io_en = _T_946 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_342_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_342_io_en = _T_950 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_343_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_343_io_en = _T_954 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_344_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_344_io_en = _T_958 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_345_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_345_io_en = _T_962 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_346_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_346_io_en = _T_966 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_347_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_347_io_en = _T_970 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_348_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_348_io_en = _T_974 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_349_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_349_io_en = _T_978 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_350_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_350_io_en = _T_982 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_351_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_351_io_en = _T_986 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_352_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_352_io_en = _T_990 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_353_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_353_io_en = _T_994 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_354_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_354_io_en = _T_998 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_355_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_355_io_en = _T_1002 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_356_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_356_io_en = _T_1006 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_357_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_357_io_en = _T_1010 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_358_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_358_io_en = _T_1014 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_359_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_359_io_en = _T_1018 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_360_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_360_io_en = _T_1022 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_361_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_361_io_en = _T_1026 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_362_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_362_io_en = _T_1030 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_363_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_363_io_en = _T_1034 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_364_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_364_io_en = _T_1038 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_365_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_365_io_en = _T_1042 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_366_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_366_io_en = _T_1046 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_367_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_367_io_en = _T_1050 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_368_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_368_io_en = _T_1054 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_369_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_369_io_en = _T_1058 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_370_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_370_io_en = _T_1062 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_371_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_371_io_en = _T_1066 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_372_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_372_io_en = _T_1070 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_373_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_373_io_en = _T_1074 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_374_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_374_io_en = _T_1078 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_375_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_375_io_en = _T_1082 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_376_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_376_io_en = _T_1086 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_377_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_377_io_en = _T_1090 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_378_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_378_io_en = _T_1094 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_379_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_379_io_en = _T_1098 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_380_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_380_io_en = _T_1102 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_381_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_381_io_en = _T_1106 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_382_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_382_io_en = _T_1110 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_383_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_383_io_en = _T_1114 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_384_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_384_io_en = _T_1118 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_385_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_385_io_en = _T_1122 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_386_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_386_io_en = _T_1126 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_387_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_387_io_en = _T_1130 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_388_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_388_io_en = _T_1134 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_389_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_389_io_en = _T_1138 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_390_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_390_io_en = _T_1142 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_391_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_391_io_en = _T_1146 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_392_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_392_io_en = _T_1150 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_393_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_393_io_en = _T_1154 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_394_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_394_io_en = _T_1158 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_395_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_395_io_en = _T_1162 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_396_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_396_io_en = _T_1166 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_397_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_397_io_en = _T_1170 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_398_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_398_io_en = _T_1174 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_399_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_399_io_en = _T_1178 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_400_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_400_io_en = _T_1182 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_401_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_401_io_en = _T_1186 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_402_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_402_io_en = _T_1190 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_403_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_403_io_en = _T_1194 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_404_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_404_io_en = _T_1198 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_405_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_405_io_en = _T_1202 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_406_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_406_io_en = _T_1206 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_407_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_407_io_en = _T_1210 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_408_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_408_io_en = _T_1214 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_409_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_409_io_en = _T_1218 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_410_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_410_io_en = _T_1222 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_411_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_411_io_en = _T_1226 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_412_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_412_io_en = _T_1230 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_413_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_413_io_en = _T_1234 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_414_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_414_io_en = _T_1238 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_415_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_415_io_en = _T_1242 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_416_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_416_io_en = _T_1246 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_417_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_417_io_en = _T_1250 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_418_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_418_io_en = _T_1254 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_419_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_419_io_en = _T_1258 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_420_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_420_io_en = _T_1262 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_421_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_421_io_en = _T_1266 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_422_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_422_io_en = _T_1270 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_423_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_423_io_en = _T_1274 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_424_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_424_io_en = _T_1278 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_425_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_425_io_en = _T_1282 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_426_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_426_io_en = _T_1286 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_427_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_427_io_en = _T_1290 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_428_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_428_io_en = _T_1294 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_429_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_429_io_en = _T_1298 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_430_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_430_io_en = _T_1302 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_431_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_431_io_en = _T_1306 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_432_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_432_io_en = _T_1310 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_433_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_433_io_en = _T_1314 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_434_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_434_io_en = _T_1318 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_435_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_435_io_en = _T_1322 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_436_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_436_io_en = _T_1326 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_437_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_437_io_en = _T_1330 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_438_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_438_io_en = _T_1334 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_439_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_439_io_en = _T_1338 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_440_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_440_io_en = _T_1342 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_441_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_441_io_en = _T_1346 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_442_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_442_io_en = _T_1350 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_443_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_443_io_en = _T_1354 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_444_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_444_io_en = _T_1358 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_445_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_445_io_en = _T_1362 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_446_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_446_io_en = _T_1366 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_447_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_447_io_en = _T_1370 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_448_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_448_io_en = _T_1374 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_449_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_449_io_en = _T_1378 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_450_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_450_io_en = _T_1382 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_451_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_451_io_en = _T_1386 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_452_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_452_io_en = _T_1390 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_453_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_453_io_en = _T_1394 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_454_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_454_io_en = _T_1398 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_455_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_455_io_en = _T_1402 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_456_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_456_io_en = _T_1406 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_457_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_457_io_en = _T_1410 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_458_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_458_io_en = _T_1414 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_459_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_459_io_en = _T_1418 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_460_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_460_io_en = _T_1422 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_461_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_461_io_en = _T_1426 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_462_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_462_io_en = _T_1430 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_463_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_463_io_en = _T_1434 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_464_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_464_io_en = _T_1438 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_465_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_465_io_en = _T_1442 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_466_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_466_io_en = _T_1446 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_467_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_467_io_en = _T_1450 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_468_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_468_io_en = _T_1454 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_469_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_469_io_en = _T_1458 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_470_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_470_io_en = _T_1462 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_471_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_471_io_en = _T_1466 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_472_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_472_io_en = _T_1470 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_473_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_473_io_en = _T_1474 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_474_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_474_io_en = _T_1478 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_475_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_475_io_en = _T_1482 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_476_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_476_io_en = _T_1486 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_477_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_477_io_en = _T_1490 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_478_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_478_io_en = _T_1494 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_479_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_479_io_en = _T_1498 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_480_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_480_io_en = _T_1502 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_481_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_481_io_en = _T_1506 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_482_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_482_io_en = _T_1510 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_483_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_483_io_en = _T_1514 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_484_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_484_io_en = _T_1518 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_485_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_485_io_en = _T_1522 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_486_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_486_io_en = _T_1526 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_487_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_487_io_en = _T_1530 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_488_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_488_io_en = _T_1534 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_489_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_489_io_en = _T_1538 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_490_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_490_io_en = _T_1542 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_491_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_491_io_en = _T_1546 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_492_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_492_io_en = _T_1550 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_493_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_493_io_en = _T_1554 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_494_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_494_io_en = _T_1558 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_495_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_495_io_en = _T_1562 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_496_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_496_io_en = _T_1566 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_497_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_497_io_en = _T_1570 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_498_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_498_io_en = _T_1574 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_499_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_499_io_en = _T_1578 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_500_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_500_io_en = _T_1582 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_501_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_501_io_en = _T_1586 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_502_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_502_io_en = _T_1590 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_503_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_503_io_en = _T_1594 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_504_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_504_io_en = _T_1598 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_505_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_505_io_en = _T_1602 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_506_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_506_io_en = _T_1606 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_507_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_507_io_en = _T_1610 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_508_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_508_io_en = _T_1614 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_509_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_509_io_en = _T_1618 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_510_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_510_io_en = _T_1622 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_511_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_511_io_en = _T_1626 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_512_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_512_io_en = _T_1630 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_513_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_513_io_en = _T_1634 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_514_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_514_io_en = _T_1638 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_515_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_515_io_en = _T_1642 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_516_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_516_io_en = _T_1646 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_517_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_517_io_en = _T_1650 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_518_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_518_io_en = _T_1654 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_519_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_519_io_en = _T_1658 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_520_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_520_io_en = _T_1662 & _T_625; // @[lib.scala 425:17]
|
|
assign rvclkhdr_521_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_521_io_en = _T_6790 | _T_6795; // @[lib.scala 351:16]
|
|
assign rvclkhdr_522_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_522_io_en = _T_6801 | _T_6806; // @[lib.scala 351:16]
|
|
assign rvclkhdr_523_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_523_io_en = _T_6812 | _T_6817; // @[lib.scala 351:16]
|
|
assign rvclkhdr_524_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_524_io_en = _T_6823 | _T_6828; // @[lib.scala 351:16]
|
|
assign rvclkhdr_525_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_525_io_en = _T_6834 | _T_6839; // @[lib.scala 351:16]
|
|
assign rvclkhdr_526_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_526_io_en = _T_6845 | _T_6850; // @[lib.scala 351:16]
|
|
assign rvclkhdr_527_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_527_io_en = _T_6856 | _T_6861; // @[lib.scala 351:16]
|
|
assign rvclkhdr_528_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_528_io_en = _T_6867 | _T_6872; // @[lib.scala 351:16]
|
|
assign rvclkhdr_529_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_529_io_en = _T_6878 | _T_6883; // @[lib.scala 351:16]
|
|
assign rvclkhdr_530_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_530_io_en = _T_6889 | _T_6894; // @[lib.scala 351:16]
|
|
assign rvclkhdr_531_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_531_io_en = _T_6900 | _T_6905; // @[lib.scala 351:16]
|
|
assign rvclkhdr_532_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_532_io_en = _T_6911 | _T_6916; // @[lib.scala 351:16]
|
|
assign rvclkhdr_533_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_533_io_en = _T_6922 | _T_6927; // @[lib.scala 351:16]
|
|
assign rvclkhdr_534_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_534_io_en = _T_6933 | _T_6938; // @[lib.scala 351:16]
|
|
assign rvclkhdr_535_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_535_io_en = _T_6944 | _T_6949; // @[lib.scala 351:16]
|
|
assign rvclkhdr_536_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_536_io_en = _T_6955 | _T_6960; // @[lib.scala 351:16]
|
|
assign rvclkhdr_537_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_537_io_en = _T_6966 | _T_6971; // @[lib.scala 351:16]
|
|
assign rvclkhdr_538_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_538_io_en = _T_6977 | _T_6982; // @[lib.scala 351:16]
|
|
assign rvclkhdr_539_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_539_io_en = _T_6988 | _T_6993; // @[lib.scala 351:16]
|
|
assign rvclkhdr_540_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_540_io_en = _T_6999 | _T_7004; // @[lib.scala 351:16]
|
|
assign rvclkhdr_541_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_541_io_en = _T_7010 | _T_7015; // @[lib.scala 351:16]
|
|
assign rvclkhdr_542_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_542_io_en = _T_7021 | _T_7026; // @[lib.scala 351:16]
|
|
assign rvclkhdr_543_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_543_io_en = _T_7032 | _T_7037; // @[lib.scala 351:16]
|
|
assign rvclkhdr_544_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_544_io_en = _T_7043 | _T_7048; // @[lib.scala 351:16]
|
|
assign rvclkhdr_545_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_545_io_en = _T_7054 | _T_7059; // @[lib.scala 351:16]
|
|
assign rvclkhdr_546_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_546_io_en = _T_7065 | _T_7070; // @[lib.scala 351:16]
|
|
assign rvclkhdr_547_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_547_io_en = _T_7076 | _T_7081; // @[lib.scala 351:16]
|
|
assign rvclkhdr_548_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_548_io_en = _T_7087 | _T_7092; // @[lib.scala 351:16]
|
|
assign rvclkhdr_549_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_549_io_en = _T_7098 | _T_7103; // @[lib.scala 351:16]
|
|
assign rvclkhdr_550_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_550_io_en = _T_7109 | _T_7114; // @[lib.scala 351:16]
|
|
assign rvclkhdr_551_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_551_io_en = _T_7120 | _T_7125; // @[lib.scala 351:16]
|
|
assign rvclkhdr_552_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_552_io_en = _T_7131 | _T_7136; // @[lib.scala 351:16]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
leak_one_f_d1 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_0 = _RAND_1[21:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_1 = _RAND_2[21:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_2 = _RAND_3[21:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_3 = _RAND_4[21:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_4 = _RAND_5[21:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_5 = _RAND_6[21:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_6 = _RAND_7[21:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_7 = _RAND_8[21:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_8 = _RAND_9[21:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_9 = _RAND_10[21:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_10 = _RAND_11[21:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_11 = _RAND_12[21:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_12 = _RAND_13[21:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_13 = _RAND_14[21:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_14 = _RAND_15[21:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_15 = _RAND_16[21:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_16 = _RAND_17[21:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_17 = _RAND_18[21:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_18 = _RAND_19[21:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_19 = _RAND_20[21:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_20 = _RAND_21[21:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_21 = _RAND_22[21:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_22 = _RAND_23[21:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_23 = _RAND_24[21:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_24 = _RAND_25[21:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_25 = _RAND_26[21:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_26 = _RAND_27[21:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_27 = _RAND_28[21:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_28 = _RAND_29[21:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_29 = _RAND_30[21:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_30 = _RAND_31[21:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_31 = _RAND_32[21:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_32 = _RAND_33[21:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_33 = _RAND_34[21:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_34 = _RAND_35[21:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_35 = _RAND_36[21:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_36 = _RAND_37[21:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_37 = _RAND_38[21:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_38 = _RAND_39[21:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_39 = _RAND_40[21:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_40 = _RAND_41[21:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_41 = _RAND_42[21:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_42 = _RAND_43[21:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_43 = _RAND_44[21:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_44 = _RAND_45[21:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_45 = _RAND_46[21:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_46 = _RAND_47[21:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_47 = _RAND_48[21:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_48 = _RAND_49[21:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_49 = _RAND_50[21:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_50 = _RAND_51[21:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_51 = _RAND_52[21:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_52 = _RAND_53[21:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_53 = _RAND_54[21:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_54 = _RAND_55[21:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_55 = _RAND_56[21:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_56 = _RAND_57[21:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_57 = _RAND_58[21:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_58 = _RAND_59[21:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_59 = _RAND_60[21:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_60 = _RAND_61[21:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_61 = _RAND_62[21:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_62 = _RAND_63[21:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_63 = _RAND_64[21:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_64 = _RAND_65[21:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_65 = _RAND_66[21:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_66 = _RAND_67[21:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_67 = _RAND_68[21:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_68 = _RAND_69[21:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_69 = _RAND_70[21:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_70 = _RAND_71[21:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_71 = _RAND_72[21:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_72 = _RAND_73[21:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_73 = _RAND_74[21:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_74 = _RAND_75[21:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_75 = _RAND_76[21:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_76 = _RAND_77[21:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_77 = _RAND_78[21:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_78 = _RAND_79[21:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_79 = _RAND_80[21:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_80 = _RAND_81[21:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_81 = _RAND_82[21:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_82 = _RAND_83[21:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_83 = _RAND_84[21:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_84 = _RAND_85[21:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_85 = _RAND_86[21:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_86 = _RAND_87[21:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_87 = _RAND_88[21:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_88 = _RAND_89[21:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_89 = _RAND_90[21:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_90 = _RAND_91[21:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_91 = _RAND_92[21:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_92 = _RAND_93[21:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_93 = _RAND_94[21:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_94 = _RAND_95[21:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_95 = _RAND_96[21:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_96 = _RAND_97[21:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_97 = _RAND_98[21:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_98 = _RAND_99[21:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_99 = _RAND_100[21:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_100 = _RAND_101[21:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_101 = _RAND_102[21:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_102 = _RAND_103[21:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_103 = _RAND_104[21:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_104 = _RAND_105[21:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_105 = _RAND_106[21:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_106 = _RAND_107[21:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_107 = _RAND_108[21:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_108 = _RAND_109[21:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_109 = _RAND_110[21:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_110 = _RAND_111[21:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_111 = _RAND_112[21:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_112 = _RAND_113[21:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_113 = _RAND_114[21:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_114 = _RAND_115[21:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_115 = _RAND_116[21:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_116 = _RAND_117[21:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_117 = _RAND_118[21:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_118 = _RAND_119[21:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_119 = _RAND_120[21:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_120 = _RAND_121[21:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_121 = _RAND_122[21:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_122 = _RAND_123[21:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_123 = _RAND_124[21:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_124 = _RAND_125[21:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_125 = _RAND_126[21:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_126 = _RAND_127[21:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_127 = _RAND_128[21:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_128 = _RAND_129[21:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_129 = _RAND_130[21:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_130 = _RAND_131[21:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_131 = _RAND_132[21:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_132 = _RAND_133[21:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_133 = _RAND_134[21:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_134 = _RAND_135[21:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_135 = _RAND_136[21:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_136 = _RAND_137[21:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_137 = _RAND_138[21:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_138 = _RAND_139[21:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_139 = _RAND_140[21:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_140 = _RAND_141[21:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_141 = _RAND_142[21:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_142 = _RAND_143[21:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_143 = _RAND_144[21:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_144 = _RAND_145[21:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_145 = _RAND_146[21:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_146 = _RAND_147[21:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_147 = _RAND_148[21:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_148 = _RAND_149[21:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_149 = _RAND_150[21:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_150 = _RAND_151[21:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_151 = _RAND_152[21:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_152 = _RAND_153[21:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_153 = _RAND_154[21:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_154 = _RAND_155[21:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_155 = _RAND_156[21:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_156 = _RAND_157[21:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_157 = _RAND_158[21:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_158 = _RAND_159[21:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_159 = _RAND_160[21:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_160 = _RAND_161[21:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_161 = _RAND_162[21:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_162 = _RAND_163[21:0];
|
|
_RAND_164 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_163 = _RAND_164[21:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_164 = _RAND_165[21:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_165 = _RAND_166[21:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_166 = _RAND_167[21:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_167 = _RAND_168[21:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_168 = _RAND_169[21:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_169 = _RAND_170[21:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_170 = _RAND_171[21:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_171 = _RAND_172[21:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_172 = _RAND_173[21:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_173 = _RAND_174[21:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_174 = _RAND_175[21:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_175 = _RAND_176[21:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_176 = _RAND_177[21:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_177 = _RAND_178[21:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_178 = _RAND_179[21:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_179 = _RAND_180[21:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_180 = _RAND_181[21:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_181 = _RAND_182[21:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_182 = _RAND_183[21:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_183 = _RAND_184[21:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_184 = _RAND_185[21:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_185 = _RAND_186[21:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_186 = _RAND_187[21:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_187 = _RAND_188[21:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_188 = _RAND_189[21:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_189 = _RAND_190[21:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_190 = _RAND_191[21:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_191 = _RAND_192[21:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_192 = _RAND_193[21:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_193 = _RAND_194[21:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_194 = _RAND_195[21:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_195 = _RAND_196[21:0];
|
|
_RAND_197 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_196 = _RAND_197[21:0];
|
|
_RAND_198 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_197 = _RAND_198[21:0];
|
|
_RAND_199 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_198 = _RAND_199[21:0];
|
|
_RAND_200 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_199 = _RAND_200[21:0];
|
|
_RAND_201 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_200 = _RAND_201[21:0];
|
|
_RAND_202 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_201 = _RAND_202[21:0];
|
|
_RAND_203 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_202 = _RAND_203[21:0];
|
|
_RAND_204 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_203 = _RAND_204[21:0];
|
|
_RAND_205 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_204 = _RAND_205[21:0];
|
|
_RAND_206 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_205 = _RAND_206[21:0];
|
|
_RAND_207 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_206 = _RAND_207[21:0];
|
|
_RAND_208 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_207 = _RAND_208[21:0];
|
|
_RAND_209 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_208 = _RAND_209[21:0];
|
|
_RAND_210 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_209 = _RAND_210[21:0];
|
|
_RAND_211 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_210 = _RAND_211[21:0];
|
|
_RAND_212 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_211 = _RAND_212[21:0];
|
|
_RAND_213 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_212 = _RAND_213[21:0];
|
|
_RAND_214 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_213 = _RAND_214[21:0];
|
|
_RAND_215 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_214 = _RAND_215[21:0];
|
|
_RAND_216 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_215 = _RAND_216[21:0];
|
|
_RAND_217 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_216 = _RAND_217[21:0];
|
|
_RAND_218 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_217 = _RAND_218[21:0];
|
|
_RAND_219 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_218 = _RAND_219[21:0];
|
|
_RAND_220 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_219 = _RAND_220[21:0];
|
|
_RAND_221 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_220 = _RAND_221[21:0];
|
|
_RAND_222 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_221 = _RAND_222[21:0];
|
|
_RAND_223 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_222 = _RAND_223[21:0];
|
|
_RAND_224 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_223 = _RAND_224[21:0];
|
|
_RAND_225 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_224 = _RAND_225[21:0];
|
|
_RAND_226 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_225 = _RAND_226[21:0];
|
|
_RAND_227 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_226 = _RAND_227[21:0];
|
|
_RAND_228 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_227 = _RAND_228[21:0];
|
|
_RAND_229 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_228 = _RAND_229[21:0];
|
|
_RAND_230 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_229 = _RAND_230[21:0];
|
|
_RAND_231 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_230 = _RAND_231[21:0];
|
|
_RAND_232 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_231 = _RAND_232[21:0];
|
|
_RAND_233 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_232 = _RAND_233[21:0];
|
|
_RAND_234 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_233 = _RAND_234[21:0];
|
|
_RAND_235 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_234 = _RAND_235[21:0];
|
|
_RAND_236 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_235 = _RAND_236[21:0];
|
|
_RAND_237 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_236 = _RAND_237[21:0];
|
|
_RAND_238 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_237 = _RAND_238[21:0];
|
|
_RAND_239 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_238 = _RAND_239[21:0];
|
|
_RAND_240 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_239 = _RAND_240[21:0];
|
|
_RAND_241 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_240 = _RAND_241[21:0];
|
|
_RAND_242 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_241 = _RAND_242[21:0];
|
|
_RAND_243 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_242 = _RAND_243[21:0];
|
|
_RAND_244 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_243 = _RAND_244[21:0];
|
|
_RAND_245 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_244 = _RAND_245[21:0];
|
|
_RAND_246 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_245 = _RAND_246[21:0];
|
|
_RAND_247 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_246 = _RAND_247[21:0];
|
|
_RAND_248 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_247 = _RAND_248[21:0];
|
|
_RAND_249 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_248 = _RAND_249[21:0];
|
|
_RAND_250 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_249 = _RAND_250[21:0];
|
|
_RAND_251 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_250 = _RAND_251[21:0];
|
|
_RAND_252 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_251 = _RAND_252[21:0];
|
|
_RAND_253 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_252 = _RAND_253[21:0];
|
|
_RAND_254 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_253 = _RAND_254[21:0];
|
|
_RAND_255 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_254 = _RAND_255[21:0];
|
|
_RAND_256 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way0_out_255 = _RAND_256[21:0];
|
|
_RAND_257 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_0 = _RAND_257[21:0];
|
|
_RAND_258 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_1 = _RAND_258[21:0];
|
|
_RAND_259 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_2 = _RAND_259[21:0];
|
|
_RAND_260 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_3 = _RAND_260[21:0];
|
|
_RAND_261 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_4 = _RAND_261[21:0];
|
|
_RAND_262 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_5 = _RAND_262[21:0];
|
|
_RAND_263 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_6 = _RAND_263[21:0];
|
|
_RAND_264 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_7 = _RAND_264[21:0];
|
|
_RAND_265 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_8 = _RAND_265[21:0];
|
|
_RAND_266 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_9 = _RAND_266[21:0];
|
|
_RAND_267 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_10 = _RAND_267[21:0];
|
|
_RAND_268 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_11 = _RAND_268[21:0];
|
|
_RAND_269 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_12 = _RAND_269[21:0];
|
|
_RAND_270 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_13 = _RAND_270[21:0];
|
|
_RAND_271 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_14 = _RAND_271[21:0];
|
|
_RAND_272 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_15 = _RAND_272[21:0];
|
|
_RAND_273 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_16 = _RAND_273[21:0];
|
|
_RAND_274 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_17 = _RAND_274[21:0];
|
|
_RAND_275 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_18 = _RAND_275[21:0];
|
|
_RAND_276 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_19 = _RAND_276[21:0];
|
|
_RAND_277 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_20 = _RAND_277[21:0];
|
|
_RAND_278 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_21 = _RAND_278[21:0];
|
|
_RAND_279 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_22 = _RAND_279[21:0];
|
|
_RAND_280 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_23 = _RAND_280[21:0];
|
|
_RAND_281 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_24 = _RAND_281[21:0];
|
|
_RAND_282 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_25 = _RAND_282[21:0];
|
|
_RAND_283 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_26 = _RAND_283[21:0];
|
|
_RAND_284 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_27 = _RAND_284[21:0];
|
|
_RAND_285 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_28 = _RAND_285[21:0];
|
|
_RAND_286 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_29 = _RAND_286[21:0];
|
|
_RAND_287 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_30 = _RAND_287[21:0];
|
|
_RAND_288 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_31 = _RAND_288[21:0];
|
|
_RAND_289 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_32 = _RAND_289[21:0];
|
|
_RAND_290 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_33 = _RAND_290[21:0];
|
|
_RAND_291 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_34 = _RAND_291[21:0];
|
|
_RAND_292 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_35 = _RAND_292[21:0];
|
|
_RAND_293 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_36 = _RAND_293[21:0];
|
|
_RAND_294 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_37 = _RAND_294[21:0];
|
|
_RAND_295 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_38 = _RAND_295[21:0];
|
|
_RAND_296 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_39 = _RAND_296[21:0];
|
|
_RAND_297 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_40 = _RAND_297[21:0];
|
|
_RAND_298 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_41 = _RAND_298[21:0];
|
|
_RAND_299 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_42 = _RAND_299[21:0];
|
|
_RAND_300 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_43 = _RAND_300[21:0];
|
|
_RAND_301 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_44 = _RAND_301[21:0];
|
|
_RAND_302 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_45 = _RAND_302[21:0];
|
|
_RAND_303 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_46 = _RAND_303[21:0];
|
|
_RAND_304 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_47 = _RAND_304[21:0];
|
|
_RAND_305 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_48 = _RAND_305[21:0];
|
|
_RAND_306 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_49 = _RAND_306[21:0];
|
|
_RAND_307 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_50 = _RAND_307[21:0];
|
|
_RAND_308 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_51 = _RAND_308[21:0];
|
|
_RAND_309 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_52 = _RAND_309[21:0];
|
|
_RAND_310 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_53 = _RAND_310[21:0];
|
|
_RAND_311 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_54 = _RAND_311[21:0];
|
|
_RAND_312 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_55 = _RAND_312[21:0];
|
|
_RAND_313 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_56 = _RAND_313[21:0];
|
|
_RAND_314 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_57 = _RAND_314[21:0];
|
|
_RAND_315 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_58 = _RAND_315[21:0];
|
|
_RAND_316 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_59 = _RAND_316[21:0];
|
|
_RAND_317 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_60 = _RAND_317[21:0];
|
|
_RAND_318 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_61 = _RAND_318[21:0];
|
|
_RAND_319 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_62 = _RAND_319[21:0];
|
|
_RAND_320 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_63 = _RAND_320[21:0];
|
|
_RAND_321 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_64 = _RAND_321[21:0];
|
|
_RAND_322 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_65 = _RAND_322[21:0];
|
|
_RAND_323 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_66 = _RAND_323[21:0];
|
|
_RAND_324 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_67 = _RAND_324[21:0];
|
|
_RAND_325 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_68 = _RAND_325[21:0];
|
|
_RAND_326 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_69 = _RAND_326[21:0];
|
|
_RAND_327 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_70 = _RAND_327[21:0];
|
|
_RAND_328 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_71 = _RAND_328[21:0];
|
|
_RAND_329 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_72 = _RAND_329[21:0];
|
|
_RAND_330 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_73 = _RAND_330[21:0];
|
|
_RAND_331 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_74 = _RAND_331[21:0];
|
|
_RAND_332 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_75 = _RAND_332[21:0];
|
|
_RAND_333 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_76 = _RAND_333[21:0];
|
|
_RAND_334 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_77 = _RAND_334[21:0];
|
|
_RAND_335 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_78 = _RAND_335[21:0];
|
|
_RAND_336 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_79 = _RAND_336[21:0];
|
|
_RAND_337 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_80 = _RAND_337[21:0];
|
|
_RAND_338 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_81 = _RAND_338[21:0];
|
|
_RAND_339 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_82 = _RAND_339[21:0];
|
|
_RAND_340 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_83 = _RAND_340[21:0];
|
|
_RAND_341 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_84 = _RAND_341[21:0];
|
|
_RAND_342 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_85 = _RAND_342[21:0];
|
|
_RAND_343 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_86 = _RAND_343[21:0];
|
|
_RAND_344 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_87 = _RAND_344[21:0];
|
|
_RAND_345 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_88 = _RAND_345[21:0];
|
|
_RAND_346 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_89 = _RAND_346[21:0];
|
|
_RAND_347 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_90 = _RAND_347[21:0];
|
|
_RAND_348 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_91 = _RAND_348[21:0];
|
|
_RAND_349 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_92 = _RAND_349[21:0];
|
|
_RAND_350 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_93 = _RAND_350[21:0];
|
|
_RAND_351 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_94 = _RAND_351[21:0];
|
|
_RAND_352 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_95 = _RAND_352[21:0];
|
|
_RAND_353 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_96 = _RAND_353[21:0];
|
|
_RAND_354 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_97 = _RAND_354[21:0];
|
|
_RAND_355 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_98 = _RAND_355[21:0];
|
|
_RAND_356 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_99 = _RAND_356[21:0];
|
|
_RAND_357 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_100 = _RAND_357[21:0];
|
|
_RAND_358 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_101 = _RAND_358[21:0];
|
|
_RAND_359 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_102 = _RAND_359[21:0];
|
|
_RAND_360 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_103 = _RAND_360[21:0];
|
|
_RAND_361 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_104 = _RAND_361[21:0];
|
|
_RAND_362 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_105 = _RAND_362[21:0];
|
|
_RAND_363 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_106 = _RAND_363[21:0];
|
|
_RAND_364 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_107 = _RAND_364[21:0];
|
|
_RAND_365 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_108 = _RAND_365[21:0];
|
|
_RAND_366 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_109 = _RAND_366[21:0];
|
|
_RAND_367 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_110 = _RAND_367[21:0];
|
|
_RAND_368 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_111 = _RAND_368[21:0];
|
|
_RAND_369 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_112 = _RAND_369[21:0];
|
|
_RAND_370 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_113 = _RAND_370[21:0];
|
|
_RAND_371 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_114 = _RAND_371[21:0];
|
|
_RAND_372 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_115 = _RAND_372[21:0];
|
|
_RAND_373 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_116 = _RAND_373[21:0];
|
|
_RAND_374 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_117 = _RAND_374[21:0];
|
|
_RAND_375 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_118 = _RAND_375[21:0];
|
|
_RAND_376 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_119 = _RAND_376[21:0];
|
|
_RAND_377 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_120 = _RAND_377[21:0];
|
|
_RAND_378 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_121 = _RAND_378[21:0];
|
|
_RAND_379 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_122 = _RAND_379[21:0];
|
|
_RAND_380 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_123 = _RAND_380[21:0];
|
|
_RAND_381 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_124 = _RAND_381[21:0];
|
|
_RAND_382 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_125 = _RAND_382[21:0];
|
|
_RAND_383 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_126 = _RAND_383[21:0];
|
|
_RAND_384 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_127 = _RAND_384[21:0];
|
|
_RAND_385 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_128 = _RAND_385[21:0];
|
|
_RAND_386 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_129 = _RAND_386[21:0];
|
|
_RAND_387 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_130 = _RAND_387[21:0];
|
|
_RAND_388 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_131 = _RAND_388[21:0];
|
|
_RAND_389 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_132 = _RAND_389[21:0];
|
|
_RAND_390 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_133 = _RAND_390[21:0];
|
|
_RAND_391 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_134 = _RAND_391[21:0];
|
|
_RAND_392 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_135 = _RAND_392[21:0];
|
|
_RAND_393 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_136 = _RAND_393[21:0];
|
|
_RAND_394 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_137 = _RAND_394[21:0];
|
|
_RAND_395 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_138 = _RAND_395[21:0];
|
|
_RAND_396 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_139 = _RAND_396[21:0];
|
|
_RAND_397 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_140 = _RAND_397[21:0];
|
|
_RAND_398 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_141 = _RAND_398[21:0];
|
|
_RAND_399 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_142 = _RAND_399[21:0];
|
|
_RAND_400 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_143 = _RAND_400[21:0];
|
|
_RAND_401 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_144 = _RAND_401[21:0];
|
|
_RAND_402 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_145 = _RAND_402[21:0];
|
|
_RAND_403 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_146 = _RAND_403[21:0];
|
|
_RAND_404 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_147 = _RAND_404[21:0];
|
|
_RAND_405 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_148 = _RAND_405[21:0];
|
|
_RAND_406 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_149 = _RAND_406[21:0];
|
|
_RAND_407 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_150 = _RAND_407[21:0];
|
|
_RAND_408 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_151 = _RAND_408[21:0];
|
|
_RAND_409 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_152 = _RAND_409[21:0];
|
|
_RAND_410 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_153 = _RAND_410[21:0];
|
|
_RAND_411 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_154 = _RAND_411[21:0];
|
|
_RAND_412 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_155 = _RAND_412[21:0];
|
|
_RAND_413 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_156 = _RAND_413[21:0];
|
|
_RAND_414 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_157 = _RAND_414[21:0];
|
|
_RAND_415 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_158 = _RAND_415[21:0];
|
|
_RAND_416 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_159 = _RAND_416[21:0];
|
|
_RAND_417 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_160 = _RAND_417[21:0];
|
|
_RAND_418 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_161 = _RAND_418[21:0];
|
|
_RAND_419 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_162 = _RAND_419[21:0];
|
|
_RAND_420 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_163 = _RAND_420[21:0];
|
|
_RAND_421 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_164 = _RAND_421[21:0];
|
|
_RAND_422 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_165 = _RAND_422[21:0];
|
|
_RAND_423 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_166 = _RAND_423[21:0];
|
|
_RAND_424 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_167 = _RAND_424[21:0];
|
|
_RAND_425 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_168 = _RAND_425[21:0];
|
|
_RAND_426 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_169 = _RAND_426[21:0];
|
|
_RAND_427 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_170 = _RAND_427[21:0];
|
|
_RAND_428 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_171 = _RAND_428[21:0];
|
|
_RAND_429 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_172 = _RAND_429[21:0];
|
|
_RAND_430 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_173 = _RAND_430[21:0];
|
|
_RAND_431 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_174 = _RAND_431[21:0];
|
|
_RAND_432 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_175 = _RAND_432[21:0];
|
|
_RAND_433 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_176 = _RAND_433[21:0];
|
|
_RAND_434 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_177 = _RAND_434[21:0];
|
|
_RAND_435 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_178 = _RAND_435[21:0];
|
|
_RAND_436 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_179 = _RAND_436[21:0];
|
|
_RAND_437 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_180 = _RAND_437[21:0];
|
|
_RAND_438 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_181 = _RAND_438[21:0];
|
|
_RAND_439 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_182 = _RAND_439[21:0];
|
|
_RAND_440 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_183 = _RAND_440[21:0];
|
|
_RAND_441 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_184 = _RAND_441[21:0];
|
|
_RAND_442 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_185 = _RAND_442[21:0];
|
|
_RAND_443 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_186 = _RAND_443[21:0];
|
|
_RAND_444 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_187 = _RAND_444[21:0];
|
|
_RAND_445 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_188 = _RAND_445[21:0];
|
|
_RAND_446 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_189 = _RAND_446[21:0];
|
|
_RAND_447 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_190 = _RAND_447[21:0];
|
|
_RAND_448 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_191 = _RAND_448[21:0];
|
|
_RAND_449 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_192 = _RAND_449[21:0];
|
|
_RAND_450 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_193 = _RAND_450[21:0];
|
|
_RAND_451 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_194 = _RAND_451[21:0];
|
|
_RAND_452 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_195 = _RAND_452[21:0];
|
|
_RAND_453 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_196 = _RAND_453[21:0];
|
|
_RAND_454 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_197 = _RAND_454[21:0];
|
|
_RAND_455 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_198 = _RAND_455[21:0];
|
|
_RAND_456 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_199 = _RAND_456[21:0];
|
|
_RAND_457 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_200 = _RAND_457[21:0];
|
|
_RAND_458 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_201 = _RAND_458[21:0];
|
|
_RAND_459 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_202 = _RAND_459[21:0];
|
|
_RAND_460 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_203 = _RAND_460[21:0];
|
|
_RAND_461 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_204 = _RAND_461[21:0];
|
|
_RAND_462 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_205 = _RAND_462[21:0];
|
|
_RAND_463 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_206 = _RAND_463[21:0];
|
|
_RAND_464 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_207 = _RAND_464[21:0];
|
|
_RAND_465 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_208 = _RAND_465[21:0];
|
|
_RAND_466 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_209 = _RAND_466[21:0];
|
|
_RAND_467 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_210 = _RAND_467[21:0];
|
|
_RAND_468 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_211 = _RAND_468[21:0];
|
|
_RAND_469 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_212 = _RAND_469[21:0];
|
|
_RAND_470 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_213 = _RAND_470[21:0];
|
|
_RAND_471 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_214 = _RAND_471[21:0];
|
|
_RAND_472 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_215 = _RAND_472[21:0];
|
|
_RAND_473 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_216 = _RAND_473[21:0];
|
|
_RAND_474 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_217 = _RAND_474[21:0];
|
|
_RAND_475 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_218 = _RAND_475[21:0];
|
|
_RAND_476 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_219 = _RAND_476[21:0];
|
|
_RAND_477 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_220 = _RAND_477[21:0];
|
|
_RAND_478 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_221 = _RAND_478[21:0];
|
|
_RAND_479 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_222 = _RAND_479[21:0];
|
|
_RAND_480 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_223 = _RAND_480[21:0];
|
|
_RAND_481 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_224 = _RAND_481[21:0];
|
|
_RAND_482 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_225 = _RAND_482[21:0];
|
|
_RAND_483 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_226 = _RAND_483[21:0];
|
|
_RAND_484 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_227 = _RAND_484[21:0];
|
|
_RAND_485 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_228 = _RAND_485[21:0];
|
|
_RAND_486 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_229 = _RAND_486[21:0];
|
|
_RAND_487 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_230 = _RAND_487[21:0];
|
|
_RAND_488 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_231 = _RAND_488[21:0];
|
|
_RAND_489 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_232 = _RAND_489[21:0];
|
|
_RAND_490 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_233 = _RAND_490[21:0];
|
|
_RAND_491 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_234 = _RAND_491[21:0];
|
|
_RAND_492 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_235 = _RAND_492[21:0];
|
|
_RAND_493 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_236 = _RAND_493[21:0];
|
|
_RAND_494 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_237 = _RAND_494[21:0];
|
|
_RAND_495 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_238 = _RAND_495[21:0];
|
|
_RAND_496 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_239 = _RAND_496[21:0];
|
|
_RAND_497 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_240 = _RAND_497[21:0];
|
|
_RAND_498 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_241 = _RAND_498[21:0];
|
|
_RAND_499 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_242 = _RAND_499[21:0];
|
|
_RAND_500 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_243 = _RAND_500[21:0];
|
|
_RAND_501 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_244 = _RAND_501[21:0];
|
|
_RAND_502 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_245 = _RAND_502[21:0];
|
|
_RAND_503 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_246 = _RAND_503[21:0];
|
|
_RAND_504 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_247 = _RAND_504[21:0];
|
|
_RAND_505 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_248 = _RAND_505[21:0];
|
|
_RAND_506 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_249 = _RAND_506[21:0];
|
|
_RAND_507 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_250 = _RAND_507[21:0];
|
|
_RAND_508 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_251 = _RAND_508[21:0];
|
|
_RAND_509 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_252 = _RAND_509[21:0];
|
|
_RAND_510 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_253 = _RAND_510[21:0];
|
|
_RAND_511 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_254 = _RAND_511[21:0];
|
|
_RAND_512 = {1{`RANDOM}};
|
|
btb_bank0_rd_data_way1_out_255 = _RAND_512[21:0];
|
|
_RAND_513 = {1{`RANDOM}};
|
|
fghr = _RAND_513[7:0];
|
|
_RAND_514 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_0 = _RAND_514[1:0];
|
|
_RAND_515 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_1 = _RAND_515[1:0];
|
|
_RAND_516 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_2 = _RAND_516[1:0];
|
|
_RAND_517 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_3 = _RAND_517[1:0];
|
|
_RAND_518 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_4 = _RAND_518[1:0];
|
|
_RAND_519 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_5 = _RAND_519[1:0];
|
|
_RAND_520 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_6 = _RAND_520[1:0];
|
|
_RAND_521 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_7 = _RAND_521[1:0];
|
|
_RAND_522 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_8 = _RAND_522[1:0];
|
|
_RAND_523 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_9 = _RAND_523[1:0];
|
|
_RAND_524 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_10 = _RAND_524[1:0];
|
|
_RAND_525 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_11 = _RAND_525[1:0];
|
|
_RAND_526 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_12 = _RAND_526[1:0];
|
|
_RAND_527 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_13 = _RAND_527[1:0];
|
|
_RAND_528 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_14 = _RAND_528[1:0];
|
|
_RAND_529 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_15 = _RAND_529[1:0];
|
|
_RAND_530 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_16 = _RAND_530[1:0];
|
|
_RAND_531 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_17 = _RAND_531[1:0];
|
|
_RAND_532 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_18 = _RAND_532[1:0];
|
|
_RAND_533 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_19 = _RAND_533[1:0];
|
|
_RAND_534 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_20 = _RAND_534[1:0];
|
|
_RAND_535 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_21 = _RAND_535[1:0];
|
|
_RAND_536 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_22 = _RAND_536[1:0];
|
|
_RAND_537 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_23 = _RAND_537[1:0];
|
|
_RAND_538 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_24 = _RAND_538[1:0];
|
|
_RAND_539 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_25 = _RAND_539[1:0];
|
|
_RAND_540 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_26 = _RAND_540[1:0];
|
|
_RAND_541 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_27 = _RAND_541[1:0];
|
|
_RAND_542 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_28 = _RAND_542[1:0];
|
|
_RAND_543 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_29 = _RAND_543[1:0];
|
|
_RAND_544 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_30 = _RAND_544[1:0];
|
|
_RAND_545 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_31 = _RAND_545[1:0];
|
|
_RAND_546 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_32 = _RAND_546[1:0];
|
|
_RAND_547 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_33 = _RAND_547[1:0];
|
|
_RAND_548 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_34 = _RAND_548[1:0];
|
|
_RAND_549 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_35 = _RAND_549[1:0];
|
|
_RAND_550 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_36 = _RAND_550[1:0];
|
|
_RAND_551 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_37 = _RAND_551[1:0];
|
|
_RAND_552 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_38 = _RAND_552[1:0];
|
|
_RAND_553 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_39 = _RAND_553[1:0];
|
|
_RAND_554 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_40 = _RAND_554[1:0];
|
|
_RAND_555 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_41 = _RAND_555[1:0];
|
|
_RAND_556 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_42 = _RAND_556[1:0];
|
|
_RAND_557 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_43 = _RAND_557[1:0];
|
|
_RAND_558 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_44 = _RAND_558[1:0];
|
|
_RAND_559 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_45 = _RAND_559[1:0];
|
|
_RAND_560 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_46 = _RAND_560[1:0];
|
|
_RAND_561 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_47 = _RAND_561[1:0];
|
|
_RAND_562 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_48 = _RAND_562[1:0];
|
|
_RAND_563 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_49 = _RAND_563[1:0];
|
|
_RAND_564 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_50 = _RAND_564[1:0];
|
|
_RAND_565 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_51 = _RAND_565[1:0];
|
|
_RAND_566 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_52 = _RAND_566[1:0];
|
|
_RAND_567 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_53 = _RAND_567[1:0];
|
|
_RAND_568 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_54 = _RAND_568[1:0];
|
|
_RAND_569 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_55 = _RAND_569[1:0];
|
|
_RAND_570 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_56 = _RAND_570[1:0];
|
|
_RAND_571 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_57 = _RAND_571[1:0];
|
|
_RAND_572 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_58 = _RAND_572[1:0];
|
|
_RAND_573 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_59 = _RAND_573[1:0];
|
|
_RAND_574 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_60 = _RAND_574[1:0];
|
|
_RAND_575 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_61 = _RAND_575[1:0];
|
|
_RAND_576 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_62 = _RAND_576[1:0];
|
|
_RAND_577 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_63 = _RAND_577[1:0];
|
|
_RAND_578 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_64 = _RAND_578[1:0];
|
|
_RAND_579 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_65 = _RAND_579[1:0];
|
|
_RAND_580 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_66 = _RAND_580[1:0];
|
|
_RAND_581 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_67 = _RAND_581[1:0];
|
|
_RAND_582 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_68 = _RAND_582[1:0];
|
|
_RAND_583 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_69 = _RAND_583[1:0];
|
|
_RAND_584 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_70 = _RAND_584[1:0];
|
|
_RAND_585 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_71 = _RAND_585[1:0];
|
|
_RAND_586 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_72 = _RAND_586[1:0];
|
|
_RAND_587 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_73 = _RAND_587[1:0];
|
|
_RAND_588 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_74 = _RAND_588[1:0];
|
|
_RAND_589 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_75 = _RAND_589[1:0];
|
|
_RAND_590 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_76 = _RAND_590[1:0];
|
|
_RAND_591 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_77 = _RAND_591[1:0];
|
|
_RAND_592 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_78 = _RAND_592[1:0];
|
|
_RAND_593 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_79 = _RAND_593[1:0];
|
|
_RAND_594 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_80 = _RAND_594[1:0];
|
|
_RAND_595 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_81 = _RAND_595[1:0];
|
|
_RAND_596 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_82 = _RAND_596[1:0];
|
|
_RAND_597 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_83 = _RAND_597[1:0];
|
|
_RAND_598 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_84 = _RAND_598[1:0];
|
|
_RAND_599 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_85 = _RAND_599[1:0];
|
|
_RAND_600 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_86 = _RAND_600[1:0];
|
|
_RAND_601 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_87 = _RAND_601[1:0];
|
|
_RAND_602 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_88 = _RAND_602[1:0];
|
|
_RAND_603 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_89 = _RAND_603[1:0];
|
|
_RAND_604 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_90 = _RAND_604[1:0];
|
|
_RAND_605 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_91 = _RAND_605[1:0];
|
|
_RAND_606 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_92 = _RAND_606[1:0];
|
|
_RAND_607 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_93 = _RAND_607[1:0];
|
|
_RAND_608 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_94 = _RAND_608[1:0];
|
|
_RAND_609 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_95 = _RAND_609[1:0];
|
|
_RAND_610 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_96 = _RAND_610[1:0];
|
|
_RAND_611 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_97 = _RAND_611[1:0];
|
|
_RAND_612 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_98 = _RAND_612[1:0];
|
|
_RAND_613 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_99 = _RAND_613[1:0];
|
|
_RAND_614 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_100 = _RAND_614[1:0];
|
|
_RAND_615 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_101 = _RAND_615[1:0];
|
|
_RAND_616 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_102 = _RAND_616[1:0];
|
|
_RAND_617 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_103 = _RAND_617[1:0];
|
|
_RAND_618 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_104 = _RAND_618[1:0];
|
|
_RAND_619 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_105 = _RAND_619[1:0];
|
|
_RAND_620 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_106 = _RAND_620[1:0];
|
|
_RAND_621 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_107 = _RAND_621[1:0];
|
|
_RAND_622 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_108 = _RAND_622[1:0];
|
|
_RAND_623 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_109 = _RAND_623[1:0];
|
|
_RAND_624 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_110 = _RAND_624[1:0];
|
|
_RAND_625 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_111 = _RAND_625[1:0];
|
|
_RAND_626 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_112 = _RAND_626[1:0];
|
|
_RAND_627 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_113 = _RAND_627[1:0];
|
|
_RAND_628 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_114 = _RAND_628[1:0];
|
|
_RAND_629 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_115 = _RAND_629[1:0];
|
|
_RAND_630 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_116 = _RAND_630[1:0];
|
|
_RAND_631 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_117 = _RAND_631[1:0];
|
|
_RAND_632 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_118 = _RAND_632[1:0];
|
|
_RAND_633 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_119 = _RAND_633[1:0];
|
|
_RAND_634 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_120 = _RAND_634[1:0];
|
|
_RAND_635 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_121 = _RAND_635[1:0];
|
|
_RAND_636 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_122 = _RAND_636[1:0];
|
|
_RAND_637 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_123 = _RAND_637[1:0];
|
|
_RAND_638 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_124 = _RAND_638[1:0];
|
|
_RAND_639 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_125 = _RAND_639[1:0];
|
|
_RAND_640 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_126 = _RAND_640[1:0];
|
|
_RAND_641 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_127 = _RAND_641[1:0];
|
|
_RAND_642 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_128 = _RAND_642[1:0];
|
|
_RAND_643 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_129 = _RAND_643[1:0];
|
|
_RAND_644 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_130 = _RAND_644[1:0];
|
|
_RAND_645 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_131 = _RAND_645[1:0];
|
|
_RAND_646 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_132 = _RAND_646[1:0];
|
|
_RAND_647 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_133 = _RAND_647[1:0];
|
|
_RAND_648 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_134 = _RAND_648[1:0];
|
|
_RAND_649 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_135 = _RAND_649[1:0];
|
|
_RAND_650 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_136 = _RAND_650[1:0];
|
|
_RAND_651 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_137 = _RAND_651[1:0];
|
|
_RAND_652 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_138 = _RAND_652[1:0];
|
|
_RAND_653 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_139 = _RAND_653[1:0];
|
|
_RAND_654 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_140 = _RAND_654[1:0];
|
|
_RAND_655 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_141 = _RAND_655[1:0];
|
|
_RAND_656 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_142 = _RAND_656[1:0];
|
|
_RAND_657 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_143 = _RAND_657[1:0];
|
|
_RAND_658 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_144 = _RAND_658[1:0];
|
|
_RAND_659 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_145 = _RAND_659[1:0];
|
|
_RAND_660 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_146 = _RAND_660[1:0];
|
|
_RAND_661 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_147 = _RAND_661[1:0];
|
|
_RAND_662 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_148 = _RAND_662[1:0];
|
|
_RAND_663 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_149 = _RAND_663[1:0];
|
|
_RAND_664 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_150 = _RAND_664[1:0];
|
|
_RAND_665 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_151 = _RAND_665[1:0];
|
|
_RAND_666 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_152 = _RAND_666[1:0];
|
|
_RAND_667 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_153 = _RAND_667[1:0];
|
|
_RAND_668 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_154 = _RAND_668[1:0];
|
|
_RAND_669 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_155 = _RAND_669[1:0];
|
|
_RAND_670 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_156 = _RAND_670[1:0];
|
|
_RAND_671 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_157 = _RAND_671[1:0];
|
|
_RAND_672 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_158 = _RAND_672[1:0];
|
|
_RAND_673 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_159 = _RAND_673[1:0];
|
|
_RAND_674 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_160 = _RAND_674[1:0];
|
|
_RAND_675 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_161 = _RAND_675[1:0];
|
|
_RAND_676 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_162 = _RAND_676[1:0];
|
|
_RAND_677 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_163 = _RAND_677[1:0];
|
|
_RAND_678 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_164 = _RAND_678[1:0];
|
|
_RAND_679 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_165 = _RAND_679[1:0];
|
|
_RAND_680 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_166 = _RAND_680[1:0];
|
|
_RAND_681 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_167 = _RAND_681[1:0];
|
|
_RAND_682 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_168 = _RAND_682[1:0];
|
|
_RAND_683 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_169 = _RAND_683[1:0];
|
|
_RAND_684 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_170 = _RAND_684[1:0];
|
|
_RAND_685 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_171 = _RAND_685[1:0];
|
|
_RAND_686 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_172 = _RAND_686[1:0];
|
|
_RAND_687 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_173 = _RAND_687[1:0];
|
|
_RAND_688 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_174 = _RAND_688[1:0];
|
|
_RAND_689 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_175 = _RAND_689[1:0];
|
|
_RAND_690 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_176 = _RAND_690[1:0];
|
|
_RAND_691 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_177 = _RAND_691[1:0];
|
|
_RAND_692 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_178 = _RAND_692[1:0];
|
|
_RAND_693 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_179 = _RAND_693[1:0];
|
|
_RAND_694 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_180 = _RAND_694[1:0];
|
|
_RAND_695 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_181 = _RAND_695[1:0];
|
|
_RAND_696 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_182 = _RAND_696[1:0];
|
|
_RAND_697 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_183 = _RAND_697[1:0];
|
|
_RAND_698 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_184 = _RAND_698[1:0];
|
|
_RAND_699 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_185 = _RAND_699[1:0];
|
|
_RAND_700 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_186 = _RAND_700[1:0];
|
|
_RAND_701 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_187 = _RAND_701[1:0];
|
|
_RAND_702 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_188 = _RAND_702[1:0];
|
|
_RAND_703 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_189 = _RAND_703[1:0];
|
|
_RAND_704 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_190 = _RAND_704[1:0];
|
|
_RAND_705 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_191 = _RAND_705[1:0];
|
|
_RAND_706 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_192 = _RAND_706[1:0];
|
|
_RAND_707 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_193 = _RAND_707[1:0];
|
|
_RAND_708 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_194 = _RAND_708[1:0];
|
|
_RAND_709 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_195 = _RAND_709[1:0];
|
|
_RAND_710 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_196 = _RAND_710[1:0];
|
|
_RAND_711 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_197 = _RAND_711[1:0];
|
|
_RAND_712 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_198 = _RAND_712[1:0];
|
|
_RAND_713 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_199 = _RAND_713[1:0];
|
|
_RAND_714 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_200 = _RAND_714[1:0];
|
|
_RAND_715 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_201 = _RAND_715[1:0];
|
|
_RAND_716 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_202 = _RAND_716[1:0];
|
|
_RAND_717 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_203 = _RAND_717[1:0];
|
|
_RAND_718 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_204 = _RAND_718[1:0];
|
|
_RAND_719 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_205 = _RAND_719[1:0];
|
|
_RAND_720 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_206 = _RAND_720[1:0];
|
|
_RAND_721 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_207 = _RAND_721[1:0];
|
|
_RAND_722 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_208 = _RAND_722[1:0];
|
|
_RAND_723 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_209 = _RAND_723[1:0];
|
|
_RAND_724 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_210 = _RAND_724[1:0];
|
|
_RAND_725 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_211 = _RAND_725[1:0];
|
|
_RAND_726 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_212 = _RAND_726[1:0];
|
|
_RAND_727 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_213 = _RAND_727[1:0];
|
|
_RAND_728 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_214 = _RAND_728[1:0];
|
|
_RAND_729 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_215 = _RAND_729[1:0];
|
|
_RAND_730 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_216 = _RAND_730[1:0];
|
|
_RAND_731 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_217 = _RAND_731[1:0];
|
|
_RAND_732 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_218 = _RAND_732[1:0];
|
|
_RAND_733 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_219 = _RAND_733[1:0];
|
|
_RAND_734 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_220 = _RAND_734[1:0];
|
|
_RAND_735 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_221 = _RAND_735[1:0];
|
|
_RAND_736 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_222 = _RAND_736[1:0];
|
|
_RAND_737 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_223 = _RAND_737[1:0];
|
|
_RAND_738 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_224 = _RAND_738[1:0];
|
|
_RAND_739 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_225 = _RAND_739[1:0];
|
|
_RAND_740 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_226 = _RAND_740[1:0];
|
|
_RAND_741 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_227 = _RAND_741[1:0];
|
|
_RAND_742 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_228 = _RAND_742[1:0];
|
|
_RAND_743 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_229 = _RAND_743[1:0];
|
|
_RAND_744 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_230 = _RAND_744[1:0];
|
|
_RAND_745 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_231 = _RAND_745[1:0];
|
|
_RAND_746 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_232 = _RAND_746[1:0];
|
|
_RAND_747 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_233 = _RAND_747[1:0];
|
|
_RAND_748 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_234 = _RAND_748[1:0];
|
|
_RAND_749 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_235 = _RAND_749[1:0];
|
|
_RAND_750 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_236 = _RAND_750[1:0];
|
|
_RAND_751 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_237 = _RAND_751[1:0];
|
|
_RAND_752 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_238 = _RAND_752[1:0];
|
|
_RAND_753 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_239 = _RAND_753[1:0];
|
|
_RAND_754 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_240 = _RAND_754[1:0];
|
|
_RAND_755 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_241 = _RAND_755[1:0];
|
|
_RAND_756 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_242 = _RAND_756[1:0];
|
|
_RAND_757 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_243 = _RAND_757[1:0];
|
|
_RAND_758 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_244 = _RAND_758[1:0];
|
|
_RAND_759 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_245 = _RAND_759[1:0];
|
|
_RAND_760 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_246 = _RAND_760[1:0];
|
|
_RAND_761 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_247 = _RAND_761[1:0];
|
|
_RAND_762 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_248 = _RAND_762[1:0];
|
|
_RAND_763 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_249 = _RAND_763[1:0];
|
|
_RAND_764 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_250 = _RAND_764[1:0];
|
|
_RAND_765 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_251 = _RAND_765[1:0];
|
|
_RAND_766 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_252 = _RAND_766[1:0];
|
|
_RAND_767 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_253 = _RAND_767[1:0];
|
|
_RAND_768 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_254 = _RAND_768[1:0];
|
|
_RAND_769 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_1_255 = _RAND_769[1:0];
|
|
_RAND_770 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_0 = _RAND_770[1:0];
|
|
_RAND_771 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_1 = _RAND_771[1:0];
|
|
_RAND_772 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_2 = _RAND_772[1:0];
|
|
_RAND_773 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_3 = _RAND_773[1:0];
|
|
_RAND_774 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_4 = _RAND_774[1:0];
|
|
_RAND_775 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_5 = _RAND_775[1:0];
|
|
_RAND_776 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_6 = _RAND_776[1:0];
|
|
_RAND_777 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_7 = _RAND_777[1:0];
|
|
_RAND_778 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_8 = _RAND_778[1:0];
|
|
_RAND_779 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_9 = _RAND_779[1:0];
|
|
_RAND_780 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_10 = _RAND_780[1:0];
|
|
_RAND_781 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_11 = _RAND_781[1:0];
|
|
_RAND_782 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_12 = _RAND_782[1:0];
|
|
_RAND_783 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_13 = _RAND_783[1:0];
|
|
_RAND_784 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_14 = _RAND_784[1:0];
|
|
_RAND_785 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_15 = _RAND_785[1:0];
|
|
_RAND_786 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_16 = _RAND_786[1:0];
|
|
_RAND_787 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_17 = _RAND_787[1:0];
|
|
_RAND_788 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_18 = _RAND_788[1:0];
|
|
_RAND_789 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_19 = _RAND_789[1:0];
|
|
_RAND_790 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_20 = _RAND_790[1:0];
|
|
_RAND_791 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_21 = _RAND_791[1:0];
|
|
_RAND_792 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_22 = _RAND_792[1:0];
|
|
_RAND_793 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_23 = _RAND_793[1:0];
|
|
_RAND_794 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_24 = _RAND_794[1:0];
|
|
_RAND_795 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_25 = _RAND_795[1:0];
|
|
_RAND_796 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_26 = _RAND_796[1:0];
|
|
_RAND_797 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_27 = _RAND_797[1:0];
|
|
_RAND_798 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_28 = _RAND_798[1:0];
|
|
_RAND_799 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_29 = _RAND_799[1:0];
|
|
_RAND_800 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_30 = _RAND_800[1:0];
|
|
_RAND_801 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_31 = _RAND_801[1:0];
|
|
_RAND_802 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_32 = _RAND_802[1:0];
|
|
_RAND_803 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_33 = _RAND_803[1:0];
|
|
_RAND_804 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_34 = _RAND_804[1:0];
|
|
_RAND_805 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_35 = _RAND_805[1:0];
|
|
_RAND_806 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_36 = _RAND_806[1:0];
|
|
_RAND_807 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_37 = _RAND_807[1:0];
|
|
_RAND_808 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_38 = _RAND_808[1:0];
|
|
_RAND_809 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_39 = _RAND_809[1:0];
|
|
_RAND_810 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_40 = _RAND_810[1:0];
|
|
_RAND_811 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_41 = _RAND_811[1:0];
|
|
_RAND_812 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_42 = _RAND_812[1:0];
|
|
_RAND_813 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_43 = _RAND_813[1:0];
|
|
_RAND_814 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_44 = _RAND_814[1:0];
|
|
_RAND_815 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_45 = _RAND_815[1:0];
|
|
_RAND_816 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_46 = _RAND_816[1:0];
|
|
_RAND_817 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_47 = _RAND_817[1:0];
|
|
_RAND_818 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_48 = _RAND_818[1:0];
|
|
_RAND_819 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_49 = _RAND_819[1:0];
|
|
_RAND_820 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_50 = _RAND_820[1:0];
|
|
_RAND_821 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_51 = _RAND_821[1:0];
|
|
_RAND_822 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_52 = _RAND_822[1:0];
|
|
_RAND_823 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_53 = _RAND_823[1:0];
|
|
_RAND_824 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_54 = _RAND_824[1:0];
|
|
_RAND_825 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_55 = _RAND_825[1:0];
|
|
_RAND_826 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_56 = _RAND_826[1:0];
|
|
_RAND_827 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_57 = _RAND_827[1:0];
|
|
_RAND_828 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_58 = _RAND_828[1:0];
|
|
_RAND_829 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_59 = _RAND_829[1:0];
|
|
_RAND_830 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_60 = _RAND_830[1:0];
|
|
_RAND_831 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_61 = _RAND_831[1:0];
|
|
_RAND_832 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_62 = _RAND_832[1:0];
|
|
_RAND_833 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_63 = _RAND_833[1:0];
|
|
_RAND_834 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_64 = _RAND_834[1:0];
|
|
_RAND_835 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_65 = _RAND_835[1:0];
|
|
_RAND_836 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_66 = _RAND_836[1:0];
|
|
_RAND_837 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_67 = _RAND_837[1:0];
|
|
_RAND_838 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_68 = _RAND_838[1:0];
|
|
_RAND_839 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_69 = _RAND_839[1:0];
|
|
_RAND_840 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_70 = _RAND_840[1:0];
|
|
_RAND_841 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_71 = _RAND_841[1:0];
|
|
_RAND_842 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_72 = _RAND_842[1:0];
|
|
_RAND_843 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_73 = _RAND_843[1:0];
|
|
_RAND_844 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_74 = _RAND_844[1:0];
|
|
_RAND_845 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_75 = _RAND_845[1:0];
|
|
_RAND_846 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_76 = _RAND_846[1:0];
|
|
_RAND_847 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_77 = _RAND_847[1:0];
|
|
_RAND_848 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_78 = _RAND_848[1:0];
|
|
_RAND_849 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_79 = _RAND_849[1:0];
|
|
_RAND_850 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_80 = _RAND_850[1:0];
|
|
_RAND_851 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_81 = _RAND_851[1:0];
|
|
_RAND_852 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_82 = _RAND_852[1:0];
|
|
_RAND_853 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_83 = _RAND_853[1:0];
|
|
_RAND_854 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_84 = _RAND_854[1:0];
|
|
_RAND_855 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_85 = _RAND_855[1:0];
|
|
_RAND_856 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_86 = _RAND_856[1:0];
|
|
_RAND_857 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_87 = _RAND_857[1:0];
|
|
_RAND_858 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_88 = _RAND_858[1:0];
|
|
_RAND_859 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_89 = _RAND_859[1:0];
|
|
_RAND_860 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_90 = _RAND_860[1:0];
|
|
_RAND_861 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_91 = _RAND_861[1:0];
|
|
_RAND_862 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_92 = _RAND_862[1:0];
|
|
_RAND_863 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_93 = _RAND_863[1:0];
|
|
_RAND_864 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_94 = _RAND_864[1:0];
|
|
_RAND_865 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_95 = _RAND_865[1:0];
|
|
_RAND_866 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_96 = _RAND_866[1:0];
|
|
_RAND_867 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_97 = _RAND_867[1:0];
|
|
_RAND_868 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_98 = _RAND_868[1:0];
|
|
_RAND_869 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_99 = _RAND_869[1:0];
|
|
_RAND_870 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_100 = _RAND_870[1:0];
|
|
_RAND_871 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_101 = _RAND_871[1:0];
|
|
_RAND_872 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_102 = _RAND_872[1:0];
|
|
_RAND_873 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_103 = _RAND_873[1:0];
|
|
_RAND_874 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_104 = _RAND_874[1:0];
|
|
_RAND_875 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_105 = _RAND_875[1:0];
|
|
_RAND_876 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_106 = _RAND_876[1:0];
|
|
_RAND_877 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_107 = _RAND_877[1:0];
|
|
_RAND_878 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_108 = _RAND_878[1:0];
|
|
_RAND_879 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_109 = _RAND_879[1:0];
|
|
_RAND_880 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_110 = _RAND_880[1:0];
|
|
_RAND_881 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_111 = _RAND_881[1:0];
|
|
_RAND_882 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_112 = _RAND_882[1:0];
|
|
_RAND_883 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_113 = _RAND_883[1:0];
|
|
_RAND_884 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_114 = _RAND_884[1:0];
|
|
_RAND_885 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_115 = _RAND_885[1:0];
|
|
_RAND_886 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_116 = _RAND_886[1:0];
|
|
_RAND_887 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_117 = _RAND_887[1:0];
|
|
_RAND_888 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_118 = _RAND_888[1:0];
|
|
_RAND_889 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_119 = _RAND_889[1:0];
|
|
_RAND_890 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_120 = _RAND_890[1:0];
|
|
_RAND_891 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_121 = _RAND_891[1:0];
|
|
_RAND_892 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_122 = _RAND_892[1:0];
|
|
_RAND_893 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_123 = _RAND_893[1:0];
|
|
_RAND_894 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_124 = _RAND_894[1:0];
|
|
_RAND_895 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_125 = _RAND_895[1:0];
|
|
_RAND_896 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_126 = _RAND_896[1:0];
|
|
_RAND_897 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_127 = _RAND_897[1:0];
|
|
_RAND_898 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_128 = _RAND_898[1:0];
|
|
_RAND_899 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_129 = _RAND_899[1:0];
|
|
_RAND_900 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_130 = _RAND_900[1:0];
|
|
_RAND_901 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_131 = _RAND_901[1:0];
|
|
_RAND_902 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_132 = _RAND_902[1:0];
|
|
_RAND_903 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_133 = _RAND_903[1:0];
|
|
_RAND_904 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_134 = _RAND_904[1:0];
|
|
_RAND_905 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_135 = _RAND_905[1:0];
|
|
_RAND_906 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_136 = _RAND_906[1:0];
|
|
_RAND_907 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_137 = _RAND_907[1:0];
|
|
_RAND_908 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_138 = _RAND_908[1:0];
|
|
_RAND_909 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_139 = _RAND_909[1:0];
|
|
_RAND_910 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_140 = _RAND_910[1:0];
|
|
_RAND_911 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_141 = _RAND_911[1:0];
|
|
_RAND_912 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_142 = _RAND_912[1:0];
|
|
_RAND_913 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_143 = _RAND_913[1:0];
|
|
_RAND_914 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_144 = _RAND_914[1:0];
|
|
_RAND_915 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_145 = _RAND_915[1:0];
|
|
_RAND_916 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_146 = _RAND_916[1:0];
|
|
_RAND_917 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_147 = _RAND_917[1:0];
|
|
_RAND_918 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_148 = _RAND_918[1:0];
|
|
_RAND_919 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_149 = _RAND_919[1:0];
|
|
_RAND_920 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_150 = _RAND_920[1:0];
|
|
_RAND_921 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_151 = _RAND_921[1:0];
|
|
_RAND_922 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_152 = _RAND_922[1:0];
|
|
_RAND_923 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_153 = _RAND_923[1:0];
|
|
_RAND_924 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_154 = _RAND_924[1:0];
|
|
_RAND_925 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_155 = _RAND_925[1:0];
|
|
_RAND_926 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_156 = _RAND_926[1:0];
|
|
_RAND_927 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_157 = _RAND_927[1:0];
|
|
_RAND_928 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_158 = _RAND_928[1:0];
|
|
_RAND_929 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_159 = _RAND_929[1:0];
|
|
_RAND_930 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_160 = _RAND_930[1:0];
|
|
_RAND_931 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_161 = _RAND_931[1:0];
|
|
_RAND_932 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_162 = _RAND_932[1:0];
|
|
_RAND_933 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_163 = _RAND_933[1:0];
|
|
_RAND_934 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_164 = _RAND_934[1:0];
|
|
_RAND_935 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_165 = _RAND_935[1:0];
|
|
_RAND_936 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_166 = _RAND_936[1:0];
|
|
_RAND_937 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_167 = _RAND_937[1:0];
|
|
_RAND_938 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_168 = _RAND_938[1:0];
|
|
_RAND_939 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_169 = _RAND_939[1:0];
|
|
_RAND_940 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_170 = _RAND_940[1:0];
|
|
_RAND_941 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_171 = _RAND_941[1:0];
|
|
_RAND_942 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_172 = _RAND_942[1:0];
|
|
_RAND_943 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_173 = _RAND_943[1:0];
|
|
_RAND_944 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_174 = _RAND_944[1:0];
|
|
_RAND_945 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_175 = _RAND_945[1:0];
|
|
_RAND_946 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_176 = _RAND_946[1:0];
|
|
_RAND_947 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_177 = _RAND_947[1:0];
|
|
_RAND_948 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_178 = _RAND_948[1:0];
|
|
_RAND_949 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_179 = _RAND_949[1:0];
|
|
_RAND_950 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_180 = _RAND_950[1:0];
|
|
_RAND_951 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_181 = _RAND_951[1:0];
|
|
_RAND_952 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_182 = _RAND_952[1:0];
|
|
_RAND_953 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_183 = _RAND_953[1:0];
|
|
_RAND_954 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_184 = _RAND_954[1:0];
|
|
_RAND_955 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_185 = _RAND_955[1:0];
|
|
_RAND_956 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_186 = _RAND_956[1:0];
|
|
_RAND_957 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_187 = _RAND_957[1:0];
|
|
_RAND_958 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_188 = _RAND_958[1:0];
|
|
_RAND_959 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_189 = _RAND_959[1:0];
|
|
_RAND_960 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_190 = _RAND_960[1:0];
|
|
_RAND_961 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_191 = _RAND_961[1:0];
|
|
_RAND_962 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_192 = _RAND_962[1:0];
|
|
_RAND_963 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_193 = _RAND_963[1:0];
|
|
_RAND_964 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_194 = _RAND_964[1:0];
|
|
_RAND_965 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_195 = _RAND_965[1:0];
|
|
_RAND_966 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_196 = _RAND_966[1:0];
|
|
_RAND_967 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_197 = _RAND_967[1:0];
|
|
_RAND_968 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_198 = _RAND_968[1:0];
|
|
_RAND_969 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_199 = _RAND_969[1:0];
|
|
_RAND_970 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_200 = _RAND_970[1:0];
|
|
_RAND_971 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_201 = _RAND_971[1:0];
|
|
_RAND_972 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_202 = _RAND_972[1:0];
|
|
_RAND_973 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_203 = _RAND_973[1:0];
|
|
_RAND_974 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_204 = _RAND_974[1:0];
|
|
_RAND_975 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_205 = _RAND_975[1:0];
|
|
_RAND_976 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_206 = _RAND_976[1:0];
|
|
_RAND_977 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_207 = _RAND_977[1:0];
|
|
_RAND_978 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_208 = _RAND_978[1:0];
|
|
_RAND_979 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_209 = _RAND_979[1:0];
|
|
_RAND_980 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_210 = _RAND_980[1:0];
|
|
_RAND_981 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_211 = _RAND_981[1:0];
|
|
_RAND_982 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_212 = _RAND_982[1:0];
|
|
_RAND_983 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_213 = _RAND_983[1:0];
|
|
_RAND_984 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_214 = _RAND_984[1:0];
|
|
_RAND_985 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_215 = _RAND_985[1:0];
|
|
_RAND_986 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_216 = _RAND_986[1:0];
|
|
_RAND_987 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_217 = _RAND_987[1:0];
|
|
_RAND_988 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_218 = _RAND_988[1:0];
|
|
_RAND_989 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_219 = _RAND_989[1:0];
|
|
_RAND_990 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_220 = _RAND_990[1:0];
|
|
_RAND_991 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_221 = _RAND_991[1:0];
|
|
_RAND_992 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_222 = _RAND_992[1:0];
|
|
_RAND_993 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_223 = _RAND_993[1:0];
|
|
_RAND_994 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_224 = _RAND_994[1:0];
|
|
_RAND_995 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_225 = _RAND_995[1:0];
|
|
_RAND_996 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_226 = _RAND_996[1:0];
|
|
_RAND_997 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_227 = _RAND_997[1:0];
|
|
_RAND_998 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_228 = _RAND_998[1:0];
|
|
_RAND_999 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_229 = _RAND_999[1:0];
|
|
_RAND_1000 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_230 = _RAND_1000[1:0];
|
|
_RAND_1001 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_231 = _RAND_1001[1:0];
|
|
_RAND_1002 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_232 = _RAND_1002[1:0];
|
|
_RAND_1003 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_233 = _RAND_1003[1:0];
|
|
_RAND_1004 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_234 = _RAND_1004[1:0];
|
|
_RAND_1005 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_235 = _RAND_1005[1:0];
|
|
_RAND_1006 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_236 = _RAND_1006[1:0];
|
|
_RAND_1007 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_237 = _RAND_1007[1:0];
|
|
_RAND_1008 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_238 = _RAND_1008[1:0];
|
|
_RAND_1009 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_239 = _RAND_1009[1:0];
|
|
_RAND_1010 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_240 = _RAND_1010[1:0];
|
|
_RAND_1011 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_241 = _RAND_1011[1:0];
|
|
_RAND_1012 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_242 = _RAND_1012[1:0];
|
|
_RAND_1013 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_243 = _RAND_1013[1:0];
|
|
_RAND_1014 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_244 = _RAND_1014[1:0];
|
|
_RAND_1015 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_245 = _RAND_1015[1:0];
|
|
_RAND_1016 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_246 = _RAND_1016[1:0];
|
|
_RAND_1017 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_247 = _RAND_1017[1:0];
|
|
_RAND_1018 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_248 = _RAND_1018[1:0];
|
|
_RAND_1019 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_249 = _RAND_1019[1:0];
|
|
_RAND_1020 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_250 = _RAND_1020[1:0];
|
|
_RAND_1021 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_251 = _RAND_1021[1:0];
|
|
_RAND_1022 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_252 = _RAND_1022[1:0];
|
|
_RAND_1023 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_253 = _RAND_1023[1:0];
|
|
_RAND_1024 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_254 = _RAND_1024[1:0];
|
|
_RAND_1025 = {1{`RANDOM}};
|
|
bht_bank_rd_data_out_0_255 = _RAND_1025[1:0];
|
|
_RAND_1026 = {1{`RANDOM}};
|
|
exu_mp_way_f = _RAND_1026[0:0];
|
|
_RAND_1027 = {8{`RANDOM}};
|
|
btb_lru_b0_f = _RAND_1027[255:0];
|
|
_RAND_1028 = {1{`RANDOM}};
|
|
exu_flush_final_d1 = _RAND_1028[0:0];
|
|
_RAND_1029 = {1{`RANDOM}};
|
|
ifc_fetch_adder_prior = _RAND_1029[29:0];
|
|
_RAND_1030 = {1{`RANDOM}};
|
|
rets_out_0 = _RAND_1030[31:0];
|
|
_RAND_1031 = {1{`RANDOM}};
|
|
rets_out_1 = _RAND_1031[31:0];
|
|
_RAND_1032 = {1{`RANDOM}};
|
|
rets_out_2 = _RAND_1032[31:0];
|
|
_RAND_1033 = {1{`RANDOM}};
|
|
rets_out_3 = _RAND_1033[31:0];
|
|
_RAND_1034 = {1{`RANDOM}};
|
|
rets_out_4 = _RAND_1034[31:0];
|
|
_RAND_1035 = {1{`RANDOM}};
|
|
rets_out_5 = _RAND_1035[31:0];
|
|
_RAND_1036 = {1{`RANDOM}};
|
|
rets_out_6 = _RAND_1036[31:0];
|
|
_RAND_1037 = {1{`RANDOM}};
|
|
rets_out_7 = _RAND_1037[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
leak_one_f_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_0 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_1 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_2 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_3 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_4 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_5 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_6 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_7 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_8 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_9 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_10 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_11 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_12 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_13 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_14 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_15 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_16 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_17 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_18 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_19 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_20 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_21 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_22 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_23 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_24 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_25 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_26 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_27 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_28 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_29 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_30 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_31 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_32 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_33 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_34 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_35 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_36 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_37 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_38 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_39 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_40 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_41 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_42 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_43 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_44 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_45 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_46 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_47 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_48 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_49 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_50 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_51 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_52 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_53 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_54 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_55 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_56 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_57 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_58 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_59 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_60 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_61 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_62 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_63 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_64 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_65 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_66 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_67 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_68 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_69 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_70 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_71 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_72 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_73 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_74 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_75 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_76 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_77 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_78 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_79 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_80 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_81 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_82 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_83 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_84 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_85 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_86 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_87 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_88 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_89 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_90 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_91 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_92 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_93 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_94 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_95 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_96 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_97 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_98 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_99 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_100 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_101 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_102 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_103 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_104 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_105 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_106 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_107 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_108 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_109 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_110 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_111 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_112 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_113 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_114 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_115 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_116 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_117 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_118 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_119 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_120 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_121 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_122 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_123 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_124 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_125 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_126 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_127 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_128 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_129 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_130 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_131 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_132 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_133 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_134 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_135 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_136 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_137 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_138 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_139 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_140 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_141 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_142 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_143 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_144 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_145 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_146 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_147 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_148 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_149 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_150 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_151 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_152 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_153 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_154 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_155 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_156 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_157 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_158 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_159 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_160 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_161 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_162 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_163 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_164 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_165 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_166 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_167 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_168 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_169 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_170 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_171 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_172 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_173 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_174 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_175 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_176 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_177 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_178 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_179 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_180 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_181 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_182 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_183 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_184 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_185 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_186 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_187 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_188 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_189 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_190 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_191 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_192 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_193 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_194 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_195 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_196 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_197 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_198 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_199 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_200 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_201 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_202 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_203 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_204 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_205 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_206 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_207 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_208 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_209 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_210 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_211 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_212 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_213 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_214 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_215 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_216 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_217 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_218 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_219 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_220 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_221 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_222 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_223 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_224 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_225 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_226 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_227 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_228 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_229 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_230 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_231 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_232 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_233 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_234 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_235 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_236 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_237 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_238 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_239 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_240 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_241 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_242 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_243 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_244 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_245 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_246 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_247 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_248 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_249 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_250 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_251 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_252 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_253 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_254 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_255 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_0 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_1 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_2 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_3 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_4 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_5 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_6 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_7 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_8 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_9 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_10 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_11 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_12 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_13 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_14 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_15 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_16 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_17 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_18 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_19 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_20 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_21 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_22 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_23 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_24 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_25 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_26 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_27 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_28 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_29 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_30 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_31 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_32 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_33 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_34 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_35 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_36 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_37 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_38 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_39 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_40 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_41 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_42 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_43 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_44 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_45 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_46 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_47 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_48 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_49 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_50 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_51 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_52 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_53 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_54 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_55 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_56 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_57 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_58 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_59 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_60 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_61 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_62 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_63 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_64 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_65 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_66 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_67 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_68 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_69 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_70 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_71 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_72 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_73 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_74 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_75 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_76 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_77 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_78 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_79 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_80 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_81 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_82 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_83 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_84 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_85 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_86 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_87 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_88 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_89 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_90 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_91 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_92 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_93 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_94 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_95 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_96 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_97 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_98 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_99 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_100 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_101 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_102 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_103 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_104 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_105 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_106 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_107 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_108 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_109 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_110 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_111 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_112 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_113 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_114 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_115 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_116 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_117 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_118 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_119 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_120 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_121 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_122 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_123 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_124 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_125 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_126 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_127 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_128 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_129 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_130 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_131 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_132 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_133 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_134 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_135 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_136 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_137 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_138 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_139 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_140 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_141 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_142 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_143 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_144 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_145 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_146 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_147 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_148 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_149 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_150 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_151 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_152 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_153 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_154 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_155 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_156 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_157 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_158 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_159 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_160 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_161 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_162 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_163 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_164 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_165 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_166 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_167 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_168 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_169 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_170 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_171 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_172 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_173 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_174 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_175 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_176 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_177 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_178 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_179 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_180 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_181 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_182 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_183 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_184 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_185 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_186 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_187 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_188 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_189 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_190 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_191 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_192 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_193 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_194 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_195 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_196 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_197 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_198 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_199 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_200 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_201 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_202 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_203 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_204 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_205 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_206 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_207 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_208 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_209 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_210 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_211 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_212 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_213 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_214 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_215 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_216 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_217 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_218 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_219 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_220 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_221 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_222 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_223 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_224 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_225 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_226 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_227 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_228 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_229 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_230 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_231 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_232 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_233 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_234 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_235 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_236 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_237 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_238 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_239 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_240 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_241 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_242 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_243 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_244 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_245 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_246 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_247 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_248 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_249 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_250 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_251 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_252 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_253 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_254 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_255 = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
fghr = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_32 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_33 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_34 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_35 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_36 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_37 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_38 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_39 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_40 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_41 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_42 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_43 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_44 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_45 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_46 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_47 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_48 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_49 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_50 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_51 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_52 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_53 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_55 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_56 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_58 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_59 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_60 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_61 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_62 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_63 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_64 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_65 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_66 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_67 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_68 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_69 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_70 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_71 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_72 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_73 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_74 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_75 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_76 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_77 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_78 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_79 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_80 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_81 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_82 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_83 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_84 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_85 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_86 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_87 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_88 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_89 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_90 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_91 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_92 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_93 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_94 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_95 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_96 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_97 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_98 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_99 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_100 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_101 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_102 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_103 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_104 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_105 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_106 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_107 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_108 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_109 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_110 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_111 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_112 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_113 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_114 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_115 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_116 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_117 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_118 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_119 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_120 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_121 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_122 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_123 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_124 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_125 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_126 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_127 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_128 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_129 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_130 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_131 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_132 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_133 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_134 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_135 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_136 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_137 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_138 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_139 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_140 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_141 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_142 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_143 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_144 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_145 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_146 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_147 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_148 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_149 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_150 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_151 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_152 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_153 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_154 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_155 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_156 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_157 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_158 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_159 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_160 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_161 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_162 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_163 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_164 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_165 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_166 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_167 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_168 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_169 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_170 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_171 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_172 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_173 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_174 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_175 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_176 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_177 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_178 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_179 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_180 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_181 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_182 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_183 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_184 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_185 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_186 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_187 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_188 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_189 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_190 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_191 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_192 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_193 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_194 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_195 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_196 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_197 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_198 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_199 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_200 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_201 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_202 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_203 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_204 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_205 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_206 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_207 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_208 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_209 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_210 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_211 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_212 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_213 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_214 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_215 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_216 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_217 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_218 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_219 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_220 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_221 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_222 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_223 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_224 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_225 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_226 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_227 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_228 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_229 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_230 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_231 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_232 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_233 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_234 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_235 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_236 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_237 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_238 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_239 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_240 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_241 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_242 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_243 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_244 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_245 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_246 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_247 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_248 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_249 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_250 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_251 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_252 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_253 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_254 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_255 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_32 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_33 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_34 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_35 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_36 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_37 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_38 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_39 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_40 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_41 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_42 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_43 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_44 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_45 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_46 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_47 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_48 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_49 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_50 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_51 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_52 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_53 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_55 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_56 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_58 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_59 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_60 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_61 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_62 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_63 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_64 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_65 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_66 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_67 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_68 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_69 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_70 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_71 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_72 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_73 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_74 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_75 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_76 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_77 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_78 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_79 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_80 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_81 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_82 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_83 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_84 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_85 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_86 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_87 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_88 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_89 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_90 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_91 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_92 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_93 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_94 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_95 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_96 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_97 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_98 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_99 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_100 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_101 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_102 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_103 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_104 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_105 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_106 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_107 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_108 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_109 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_110 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_111 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_112 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_113 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_114 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_115 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_116 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_117 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_118 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_119 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_120 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_121 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_122 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_123 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_124 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_125 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_126 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_127 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_128 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_129 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_130 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_131 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_132 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_133 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_134 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_135 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_136 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_137 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_138 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_139 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_140 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_141 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_142 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_143 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_144 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_145 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_146 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_147 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_148 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_149 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_150 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_151 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_152 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_153 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_154 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_155 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_156 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_157 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_158 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_159 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_160 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_161 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_162 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_163 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_164 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_165 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_166 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_167 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_168 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_169 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_170 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_171 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_172 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_173 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_174 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_175 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_176 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_177 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_178 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_179 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_180 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_181 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_182 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_183 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_184 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_185 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_186 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_187 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_188 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_189 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_190 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_191 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_192 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_193 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_194 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_195 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_196 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_197 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_198 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_199 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_200 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_201 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_202 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_203 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_204 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_205 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_206 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_207 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_208 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_209 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_210 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_211 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_212 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_213 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_214 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_215 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_216 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_217 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_218 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_219 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_220 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_221 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_222 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_223 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_224 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_225 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_226 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_227 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_228 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_229 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_230 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_231 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_232 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_233 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_234 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_235 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_236 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_237 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_238 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_239 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_240 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_241 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_242 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_243 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_244 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_245 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_246 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_247 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_248 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_249 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_250 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_251 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_252 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_253 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_254 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_255 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
exu_mp_way_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
btb_lru_b0_f = 256'h0;
|
|
end
|
|
if (reset) begin
|
|
exu_flush_final_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifc_fetch_adder_prior = 30'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rets_out_7 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
leak_one_f_d1 <= 1'h0;
|
|
end else if (_T_363) begin
|
|
leak_one_f_d1 <= leak_one_f;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_0 <= 22'h0;
|
|
end else if (_T_643) begin
|
|
btb_bank0_rd_data_way0_out_0 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_1 <= 22'h0;
|
|
end else if (_T_647) begin
|
|
btb_bank0_rd_data_way0_out_1 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_2 <= 22'h0;
|
|
end else if (_T_651) begin
|
|
btb_bank0_rd_data_way0_out_2 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_3 <= 22'h0;
|
|
end else if (_T_655) begin
|
|
btb_bank0_rd_data_way0_out_3 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_4 <= 22'h0;
|
|
end else if (_T_659) begin
|
|
btb_bank0_rd_data_way0_out_4 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_5 <= 22'h0;
|
|
end else if (_T_663) begin
|
|
btb_bank0_rd_data_way0_out_5 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_6 <= 22'h0;
|
|
end else if (_T_667) begin
|
|
btb_bank0_rd_data_way0_out_6 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_7 <= 22'h0;
|
|
end else if (_T_671) begin
|
|
btb_bank0_rd_data_way0_out_7 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_8 <= 22'h0;
|
|
end else if (_T_675) begin
|
|
btb_bank0_rd_data_way0_out_8 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_9 <= 22'h0;
|
|
end else if (_T_679) begin
|
|
btb_bank0_rd_data_way0_out_9 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_10 <= 22'h0;
|
|
end else if (_T_683) begin
|
|
btb_bank0_rd_data_way0_out_10 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_11 <= 22'h0;
|
|
end else if (_T_687) begin
|
|
btb_bank0_rd_data_way0_out_11 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_12 <= 22'h0;
|
|
end else if (_T_691) begin
|
|
btb_bank0_rd_data_way0_out_12 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_13 <= 22'h0;
|
|
end else if (_T_695) begin
|
|
btb_bank0_rd_data_way0_out_13 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_14 <= 22'h0;
|
|
end else if (_T_699) begin
|
|
btb_bank0_rd_data_way0_out_14 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_15 <= 22'h0;
|
|
end else if (_T_703) begin
|
|
btb_bank0_rd_data_way0_out_15 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_16 <= 22'h0;
|
|
end else if (_T_707) begin
|
|
btb_bank0_rd_data_way0_out_16 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_17 <= 22'h0;
|
|
end else if (_T_711) begin
|
|
btb_bank0_rd_data_way0_out_17 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_18 <= 22'h0;
|
|
end else if (_T_715) begin
|
|
btb_bank0_rd_data_way0_out_18 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_19 <= 22'h0;
|
|
end else if (_T_719) begin
|
|
btb_bank0_rd_data_way0_out_19 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_20 <= 22'h0;
|
|
end else if (_T_723) begin
|
|
btb_bank0_rd_data_way0_out_20 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_21 <= 22'h0;
|
|
end else if (_T_727) begin
|
|
btb_bank0_rd_data_way0_out_21 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_22 <= 22'h0;
|
|
end else if (_T_731) begin
|
|
btb_bank0_rd_data_way0_out_22 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_23 <= 22'h0;
|
|
end else if (_T_735) begin
|
|
btb_bank0_rd_data_way0_out_23 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_24 <= 22'h0;
|
|
end else if (_T_739) begin
|
|
btb_bank0_rd_data_way0_out_24 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_25 <= 22'h0;
|
|
end else if (_T_743) begin
|
|
btb_bank0_rd_data_way0_out_25 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_26 <= 22'h0;
|
|
end else if (_T_747) begin
|
|
btb_bank0_rd_data_way0_out_26 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_27 <= 22'h0;
|
|
end else if (_T_751) begin
|
|
btb_bank0_rd_data_way0_out_27 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_28 <= 22'h0;
|
|
end else if (_T_755) begin
|
|
btb_bank0_rd_data_way0_out_28 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_29 <= 22'h0;
|
|
end else if (_T_759) begin
|
|
btb_bank0_rd_data_way0_out_29 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_30 <= 22'h0;
|
|
end else if (_T_763) begin
|
|
btb_bank0_rd_data_way0_out_30 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_31 <= 22'h0;
|
|
end else if (_T_767) begin
|
|
btb_bank0_rd_data_way0_out_31 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_32 <= 22'h0;
|
|
end else if (_T_771) begin
|
|
btb_bank0_rd_data_way0_out_32 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_33 <= 22'h0;
|
|
end else if (_T_775) begin
|
|
btb_bank0_rd_data_way0_out_33 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_34 <= 22'h0;
|
|
end else if (_T_779) begin
|
|
btb_bank0_rd_data_way0_out_34 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_35 <= 22'h0;
|
|
end else if (_T_783) begin
|
|
btb_bank0_rd_data_way0_out_35 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_36 <= 22'h0;
|
|
end else if (_T_787) begin
|
|
btb_bank0_rd_data_way0_out_36 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_37 <= 22'h0;
|
|
end else if (_T_791) begin
|
|
btb_bank0_rd_data_way0_out_37 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_38 <= 22'h0;
|
|
end else if (_T_795) begin
|
|
btb_bank0_rd_data_way0_out_38 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_39 <= 22'h0;
|
|
end else if (_T_799) begin
|
|
btb_bank0_rd_data_way0_out_39 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_40 <= 22'h0;
|
|
end else if (_T_803) begin
|
|
btb_bank0_rd_data_way0_out_40 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_41 <= 22'h0;
|
|
end else if (_T_807) begin
|
|
btb_bank0_rd_data_way0_out_41 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_42 <= 22'h0;
|
|
end else if (_T_811) begin
|
|
btb_bank0_rd_data_way0_out_42 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_43 <= 22'h0;
|
|
end else if (_T_815) begin
|
|
btb_bank0_rd_data_way0_out_43 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_44 <= 22'h0;
|
|
end else if (_T_819) begin
|
|
btb_bank0_rd_data_way0_out_44 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_45 <= 22'h0;
|
|
end else if (_T_823) begin
|
|
btb_bank0_rd_data_way0_out_45 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_46 <= 22'h0;
|
|
end else if (_T_827) begin
|
|
btb_bank0_rd_data_way0_out_46 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_47 <= 22'h0;
|
|
end else if (_T_831) begin
|
|
btb_bank0_rd_data_way0_out_47 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_48 <= 22'h0;
|
|
end else if (_T_835) begin
|
|
btb_bank0_rd_data_way0_out_48 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_49 <= 22'h0;
|
|
end else if (_T_839) begin
|
|
btb_bank0_rd_data_way0_out_49 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_50 <= 22'h0;
|
|
end else if (_T_843) begin
|
|
btb_bank0_rd_data_way0_out_50 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_51 <= 22'h0;
|
|
end else if (_T_847) begin
|
|
btb_bank0_rd_data_way0_out_51 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_52 <= 22'h0;
|
|
end else if (_T_851) begin
|
|
btb_bank0_rd_data_way0_out_52 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_53 <= 22'h0;
|
|
end else if (_T_855) begin
|
|
btb_bank0_rd_data_way0_out_53 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_54 <= 22'h0;
|
|
end else if (_T_859) begin
|
|
btb_bank0_rd_data_way0_out_54 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_55 <= 22'h0;
|
|
end else if (_T_863) begin
|
|
btb_bank0_rd_data_way0_out_55 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_56 <= 22'h0;
|
|
end else if (_T_867) begin
|
|
btb_bank0_rd_data_way0_out_56 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_57 <= 22'h0;
|
|
end else if (_T_871) begin
|
|
btb_bank0_rd_data_way0_out_57 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_58 <= 22'h0;
|
|
end else if (_T_875) begin
|
|
btb_bank0_rd_data_way0_out_58 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_59 <= 22'h0;
|
|
end else if (_T_879) begin
|
|
btb_bank0_rd_data_way0_out_59 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_60 <= 22'h0;
|
|
end else if (_T_883) begin
|
|
btb_bank0_rd_data_way0_out_60 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_61 <= 22'h0;
|
|
end else if (_T_887) begin
|
|
btb_bank0_rd_data_way0_out_61 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_62 <= 22'h0;
|
|
end else if (_T_891) begin
|
|
btb_bank0_rd_data_way0_out_62 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_63 <= 22'h0;
|
|
end else if (_T_895) begin
|
|
btb_bank0_rd_data_way0_out_63 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_64 <= 22'h0;
|
|
end else if (_T_899) begin
|
|
btb_bank0_rd_data_way0_out_64 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_65 <= 22'h0;
|
|
end else if (_T_903) begin
|
|
btb_bank0_rd_data_way0_out_65 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_66 <= 22'h0;
|
|
end else if (_T_907) begin
|
|
btb_bank0_rd_data_way0_out_66 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_67 <= 22'h0;
|
|
end else if (_T_911) begin
|
|
btb_bank0_rd_data_way0_out_67 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_68 <= 22'h0;
|
|
end else if (_T_915) begin
|
|
btb_bank0_rd_data_way0_out_68 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_69 <= 22'h0;
|
|
end else if (_T_919) begin
|
|
btb_bank0_rd_data_way0_out_69 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_70 <= 22'h0;
|
|
end else if (_T_923) begin
|
|
btb_bank0_rd_data_way0_out_70 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_71 <= 22'h0;
|
|
end else if (_T_927) begin
|
|
btb_bank0_rd_data_way0_out_71 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_72 <= 22'h0;
|
|
end else if (_T_931) begin
|
|
btb_bank0_rd_data_way0_out_72 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_73 <= 22'h0;
|
|
end else if (_T_935) begin
|
|
btb_bank0_rd_data_way0_out_73 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_74 <= 22'h0;
|
|
end else if (_T_939) begin
|
|
btb_bank0_rd_data_way0_out_74 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_75 <= 22'h0;
|
|
end else if (_T_943) begin
|
|
btb_bank0_rd_data_way0_out_75 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_76 <= 22'h0;
|
|
end else if (_T_947) begin
|
|
btb_bank0_rd_data_way0_out_76 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_77 <= 22'h0;
|
|
end else if (_T_951) begin
|
|
btb_bank0_rd_data_way0_out_77 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_78 <= 22'h0;
|
|
end else if (_T_955) begin
|
|
btb_bank0_rd_data_way0_out_78 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_79 <= 22'h0;
|
|
end else if (_T_959) begin
|
|
btb_bank0_rd_data_way0_out_79 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_80 <= 22'h0;
|
|
end else if (_T_963) begin
|
|
btb_bank0_rd_data_way0_out_80 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_81 <= 22'h0;
|
|
end else if (_T_967) begin
|
|
btb_bank0_rd_data_way0_out_81 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_82 <= 22'h0;
|
|
end else if (_T_971) begin
|
|
btb_bank0_rd_data_way0_out_82 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_83 <= 22'h0;
|
|
end else if (_T_975) begin
|
|
btb_bank0_rd_data_way0_out_83 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_84 <= 22'h0;
|
|
end else if (_T_979) begin
|
|
btb_bank0_rd_data_way0_out_84 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_85 <= 22'h0;
|
|
end else if (_T_983) begin
|
|
btb_bank0_rd_data_way0_out_85 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_86 <= 22'h0;
|
|
end else if (_T_987) begin
|
|
btb_bank0_rd_data_way0_out_86 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_87 <= 22'h0;
|
|
end else if (_T_991) begin
|
|
btb_bank0_rd_data_way0_out_87 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_88 <= 22'h0;
|
|
end else if (_T_995) begin
|
|
btb_bank0_rd_data_way0_out_88 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_89 <= 22'h0;
|
|
end else if (_T_999) begin
|
|
btb_bank0_rd_data_way0_out_89 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_90 <= 22'h0;
|
|
end else if (_T_1003) begin
|
|
btb_bank0_rd_data_way0_out_90 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_91 <= 22'h0;
|
|
end else if (_T_1007) begin
|
|
btb_bank0_rd_data_way0_out_91 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_92 <= 22'h0;
|
|
end else if (_T_1011) begin
|
|
btb_bank0_rd_data_way0_out_92 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_93 <= 22'h0;
|
|
end else if (_T_1015) begin
|
|
btb_bank0_rd_data_way0_out_93 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_94 <= 22'h0;
|
|
end else if (_T_1019) begin
|
|
btb_bank0_rd_data_way0_out_94 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_95 <= 22'h0;
|
|
end else if (_T_1023) begin
|
|
btb_bank0_rd_data_way0_out_95 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_96 <= 22'h0;
|
|
end else if (_T_1027) begin
|
|
btb_bank0_rd_data_way0_out_96 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_97 <= 22'h0;
|
|
end else if (_T_1031) begin
|
|
btb_bank0_rd_data_way0_out_97 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_98 <= 22'h0;
|
|
end else if (_T_1035) begin
|
|
btb_bank0_rd_data_way0_out_98 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_99 <= 22'h0;
|
|
end else if (_T_1039) begin
|
|
btb_bank0_rd_data_way0_out_99 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_100 <= 22'h0;
|
|
end else if (_T_1043) begin
|
|
btb_bank0_rd_data_way0_out_100 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_101 <= 22'h0;
|
|
end else if (_T_1047) begin
|
|
btb_bank0_rd_data_way0_out_101 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_102 <= 22'h0;
|
|
end else if (_T_1051) begin
|
|
btb_bank0_rd_data_way0_out_102 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_103 <= 22'h0;
|
|
end else if (_T_1055) begin
|
|
btb_bank0_rd_data_way0_out_103 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_104 <= 22'h0;
|
|
end else if (_T_1059) begin
|
|
btb_bank0_rd_data_way0_out_104 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_105 <= 22'h0;
|
|
end else if (_T_1063) begin
|
|
btb_bank0_rd_data_way0_out_105 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_106 <= 22'h0;
|
|
end else if (_T_1067) begin
|
|
btb_bank0_rd_data_way0_out_106 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_107 <= 22'h0;
|
|
end else if (_T_1071) begin
|
|
btb_bank0_rd_data_way0_out_107 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_108 <= 22'h0;
|
|
end else if (_T_1075) begin
|
|
btb_bank0_rd_data_way0_out_108 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_109 <= 22'h0;
|
|
end else if (_T_1079) begin
|
|
btb_bank0_rd_data_way0_out_109 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_110 <= 22'h0;
|
|
end else if (_T_1083) begin
|
|
btb_bank0_rd_data_way0_out_110 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_111 <= 22'h0;
|
|
end else if (_T_1087) begin
|
|
btb_bank0_rd_data_way0_out_111 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_112 <= 22'h0;
|
|
end else if (_T_1091) begin
|
|
btb_bank0_rd_data_way0_out_112 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_113 <= 22'h0;
|
|
end else if (_T_1095) begin
|
|
btb_bank0_rd_data_way0_out_113 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_114 <= 22'h0;
|
|
end else if (_T_1099) begin
|
|
btb_bank0_rd_data_way0_out_114 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_115 <= 22'h0;
|
|
end else if (_T_1103) begin
|
|
btb_bank0_rd_data_way0_out_115 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_116 <= 22'h0;
|
|
end else if (_T_1107) begin
|
|
btb_bank0_rd_data_way0_out_116 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_117 <= 22'h0;
|
|
end else if (_T_1111) begin
|
|
btb_bank0_rd_data_way0_out_117 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_118 <= 22'h0;
|
|
end else if (_T_1115) begin
|
|
btb_bank0_rd_data_way0_out_118 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_119 <= 22'h0;
|
|
end else if (_T_1119) begin
|
|
btb_bank0_rd_data_way0_out_119 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_120 <= 22'h0;
|
|
end else if (_T_1123) begin
|
|
btb_bank0_rd_data_way0_out_120 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_121 <= 22'h0;
|
|
end else if (_T_1127) begin
|
|
btb_bank0_rd_data_way0_out_121 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_122 <= 22'h0;
|
|
end else if (_T_1131) begin
|
|
btb_bank0_rd_data_way0_out_122 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_123 <= 22'h0;
|
|
end else if (_T_1135) begin
|
|
btb_bank0_rd_data_way0_out_123 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_124 <= 22'h0;
|
|
end else if (_T_1139) begin
|
|
btb_bank0_rd_data_way0_out_124 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_125 <= 22'h0;
|
|
end else if (_T_1143) begin
|
|
btb_bank0_rd_data_way0_out_125 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_126 <= 22'h0;
|
|
end else if (_T_1147) begin
|
|
btb_bank0_rd_data_way0_out_126 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_127 <= 22'h0;
|
|
end else if (_T_1151) begin
|
|
btb_bank0_rd_data_way0_out_127 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_128 <= 22'h0;
|
|
end else if (_T_1155) begin
|
|
btb_bank0_rd_data_way0_out_128 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_129 <= 22'h0;
|
|
end else if (_T_1159) begin
|
|
btb_bank0_rd_data_way0_out_129 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_130 <= 22'h0;
|
|
end else if (_T_1163) begin
|
|
btb_bank0_rd_data_way0_out_130 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_131 <= 22'h0;
|
|
end else if (_T_1167) begin
|
|
btb_bank0_rd_data_way0_out_131 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_132 <= 22'h0;
|
|
end else if (_T_1171) begin
|
|
btb_bank0_rd_data_way0_out_132 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_133 <= 22'h0;
|
|
end else if (_T_1175) begin
|
|
btb_bank0_rd_data_way0_out_133 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_134 <= 22'h0;
|
|
end else if (_T_1179) begin
|
|
btb_bank0_rd_data_way0_out_134 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_135 <= 22'h0;
|
|
end else if (_T_1183) begin
|
|
btb_bank0_rd_data_way0_out_135 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_136 <= 22'h0;
|
|
end else if (_T_1187) begin
|
|
btb_bank0_rd_data_way0_out_136 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_137 <= 22'h0;
|
|
end else if (_T_1191) begin
|
|
btb_bank0_rd_data_way0_out_137 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_138 <= 22'h0;
|
|
end else if (_T_1195) begin
|
|
btb_bank0_rd_data_way0_out_138 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_139 <= 22'h0;
|
|
end else if (_T_1199) begin
|
|
btb_bank0_rd_data_way0_out_139 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_140 <= 22'h0;
|
|
end else if (_T_1203) begin
|
|
btb_bank0_rd_data_way0_out_140 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_141 <= 22'h0;
|
|
end else if (_T_1207) begin
|
|
btb_bank0_rd_data_way0_out_141 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_142 <= 22'h0;
|
|
end else if (_T_1211) begin
|
|
btb_bank0_rd_data_way0_out_142 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_143 <= 22'h0;
|
|
end else if (_T_1215) begin
|
|
btb_bank0_rd_data_way0_out_143 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_144 <= 22'h0;
|
|
end else if (_T_1219) begin
|
|
btb_bank0_rd_data_way0_out_144 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_145 <= 22'h0;
|
|
end else if (_T_1223) begin
|
|
btb_bank0_rd_data_way0_out_145 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_146 <= 22'h0;
|
|
end else if (_T_1227) begin
|
|
btb_bank0_rd_data_way0_out_146 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_147 <= 22'h0;
|
|
end else if (_T_1231) begin
|
|
btb_bank0_rd_data_way0_out_147 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_148 <= 22'h0;
|
|
end else if (_T_1235) begin
|
|
btb_bank0_rd_data_way0_out_148 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_149 <= 22'h0;
|
|
end else if (_T_1239) begin
|
|
btb_bank0_rd_data_way0_out_149 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_150 <= 22'h0;
|
|
end else if (_T_1243) begin
|
|
btb_bank0_rd_data_way0_out_150 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_151 <= 22'h0;
|
|
end else if (_T_1247) begin
|
|
btb_bank0_rd_data_way0_out_151 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_152 <= 22'h0;
|
|
end else if (_T_1251) begin
|
|
btb_bank0_rd_data_way0_out_152 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_153 <= 22'h0;
|
|
end else if (_T_1255) begin
|
|
btb_bank0_rd_data_way0_out_153 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_154 <= 22'h0;
|
|
end else if (_T_1259) begin
|
|
btb_bank0_rd_data_way0_out_154 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_155 <= 22'h0;
|
|
end else if (_T_1263) begin
|
|
btb_bank0_rd_data_way0_out_155 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_156 <= 22'h0;
|
|
end else if (_T_1267) begin
|
|
btb_bank0_rd_data_way0_out_156 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_157 <= 22'h0;
|
|
end else if (_T_1271) begin
|
|
btb_bank0_rd_data_way0_out_157 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_158 <= 22'h0;
|
|
end else if (_T_1275) begin
|
|
btb_bank0_rd_data_way0_out_158 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_159 <= 22'h0;
|
|
end else if (_T_1279) begin
|
|
btb_bank0_rd_data_way0_out_159 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_160 <= 22'h0;
|
|
end else if (_T_1283) begin
|
|
btb_bank0_rd_data_way0_out_160 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_161 <= 22'h0;
|
|
end else if (_T_1287) begin
|
|
btb_bank0_rd_data_way0_out_161 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_162 <= 22'h0;
|
|
end else if (_T_1291) begin
|
|
btb_bank0_rd_data_way0_out_162 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_163 <= 22'h0;
|
|
end else if (_T_1295) begin
|
|
btb_bank0_rd_data_way0_out_163 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_164 <= 22'h0;
|
|
end else if (_T_1299) begin
|
|
btb_bank0_rd_data_way0_out_164 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_165 <= 22'h0;
|
|
end else if (_T_1303) begin
|
|
btb_bank0_rd_data_way0_out_165 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_166 <= 22'h0;
|
|
end else if (_T_1307) begin
|
|
btb_bank0_rd_data_way0_out_166 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_167 <= 22'h0;
|
|
end else if (_T_1311) begin
|
|
btb_bank0_rd_data_way0_out_167 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_168 <= 22'h0;
|
|
end else if (_T_1315) begin
|
|
btb_bank0_rd_data_way0_out_168 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_169 <= 22'h0;
|
|
end else if (_T_1319) begin
|
|
btb_bank0_rd_data_way0_out_169 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_170 <= 22'h0;
|
|
end else if (_T_1323) begin
|
|
btb_bank0_rd_data_way0_out_170 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_171 <= 22'h0;
|
|
end else if (_T_1327) begin
|
|
btb_bank0_rd_data_way0_out_171 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_172 <= 22'h0;
|
|
end else if (_T_1331) begin
|
|
btb_bank0_rd_data_way0_out_172 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_173 <= 22'h0;
|
|
end else if (_T_1335) begin
|
|
btb_bank0_rd_data_way0_out_173 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_174 <= 22'h0;
|
|
end else if (_T_1339) begin
|
|
btb_bank0_rd_data_way0_out_174 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_175 <= 22'h0;
|
|
end else if (_T_1343) begin
|
|
btb_bank0_rd_data_way0_out_175 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_176 <= 22'h0;
|
|
end else if (_T_1347) begin
|
|
btb_bank0_rd_data_way0_out_176 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_177 <= 22'h0;
|
|
end else if (_T_1351) begin
|
|
btb_bank0_rd_data_way0_out_177 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_178 <= 22'h0;
|
|
end else if (_T_1355) begin
|
|
btb_bank0_rd_data_way0_out_178 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_179 <= 22'h0;
|
|
end else if (_T_1359) begin
|
|
btb_bank0_rd_data_way0_out_179 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_180 <= 22'h0;
|
|
end else if (_T_1363) begin
|
|
btb_bank0_rd_data_way0_out_180 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_181 <= 22'h0;
|
|
end else if (_T_1367) begin
|
|
btb_bank0_rd_data_way0_out_181 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_182 <= 22'h0;
|
|
end else if (_T_1371) begin
|
|
btb_bank0_rd_data_way0_out_182 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_183 <= 22'h0;
|
|
end else if (_T_1375) begin
|
|
btb_bank0_rd_data_way0_out_183 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_184 <= 22'h0;
|
|
end else if (_T_1379) begin
|
|
btb_bank0_rd_data_way0_out_184 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_185 <= 22'h0;
|
|
end else if (_T_1383) begin
|
|
btb_bank0_rd_data_way0_out_185 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_186 <= 22'h0;
|
|
end else if (_T_1387) begin
|
|
btb_bank0_rd_data_way0_out_186 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_187 <= 22'h0;
|
|
end else if (_T_1391) begin
|
|
btb_bank0_rd_data_way0_out_187 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_188 <= 22'h0;
|
|
end else if (_T_1395) begin
|
|
btb_bank0_rd_data_way0_out_188 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_189 <= 22'h0;
|
|
end else if (_T_1399) begin
|
|
btb_bank0_rd_data_way0_out_189 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_190 <= 22'h0;
|
|
end else if (_T_1403) begin
|
|
btb_bank0_rd_data_way0_out_190 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_191 <= 22'h0;
|
|
end else if (_T_1407) begin
|
|
btb_bank0_rd_data_way0_out_191 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_192 <= 22'h0;
|
|
end else if (_T_1411) begin
|
|
btb_bank0_rd_data_way0_out_192 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_193 <= 22'h0;
|
|
end else if (_T_1415) begin
|
|
btb_bank0_rd_data_way0_out_193 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_194 <= 22'h0;
|
|
end else if (_T_1419) begin
|
|
btb_bank0_rd_data_way0_out_194 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_195 <= 22'h0;
|
|
end else if (_T_1423) begin
|
|
btb_bank0_rd_data_way0_out_195 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_196 <= 22'h0;
|
|
end else if (_T_1427) begin
|
|
btb_bank0_rd_data_way0_out_196 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_197 <= 22'h0;
|
|
end else if (_T_1431) begin
|
|
btb_bank0_rd_data_way0_out_197 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_198 <= 22'h0;
|
|
end else if (_T_1435) begin
|
|
btb_bank0_rd_data_way0_out_198 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_199 <= 22'h0;
|
|
end else if (_T_1439) begin
|
|
btb_bank0_rd_data_way0_out_199 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_200 <= 22'h0;
|
|
end else if (_T_1443) begin
|
|
btb_bank0_rd_data_way0_out_200 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_201 <= 22'h0;
|
|
end else if (_T_1447) begin
|
|
btb_bank0_rd_data_way0_out_201 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_202 <= 22'h0;
|
|
end else if (_T_1451) begin
|
|
btb_bank0_rd_data_way0_out_202 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_203 <= 22'h0;
|
|
end else if (_T_1455) begin
|
|
btb_bank0_rd_data_way0_out_203 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_204 <= 22'h0;
|
|
end else if (_T_1459) begin
|
|
btb_bank0_rd_data_way0_out_204 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_205 <= 22'h0;
|
|
end else if (_T_1463) begin
|
|
btb_bank0_rd_data_way0_out_205 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_206 <= 22'h0;
|
|
end else if (_T_1467) begin
|
|
btb_bank0_rd_data_way0_out_206 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_207 <= 22'h0;
|
|
end else if (_T_1471) begin
|
|
btb_bank0_rd_data_way0_out_207 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_208 <= 22'h0;
|
|
end else if (_T_1475) begin
|
|
btb_bank0_rd_data_way0_out_208 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_209 <= 22'h0;
|
|
end else if (_T_1479) begin
|
|
btb_bank0_rd_data_way0_out_209 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_210 <= 22'h0;
|
|
end else if (_T_1483) begin
|
|
btb_bank0_rd_data_way0_out_210 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_211 <= 22'h0;
|
|
end else if (_T_1487) begin
|
|
btb_bank0_rd_data_way0_out_211 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_212 <= 22'h0;
|
|
end else if (_T_1491) begin
|
|
btb_bank0_rd_data_way0_out_212 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_213 <= 22'h0;
|
|
end else if (_T_1495) begin
|
|
btb_bank0_rd_data_way0_out_213 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_214 <= 22'h0;
|
|
end else if (_T_1499) begin
|
|
btb_bank0_rd_data_way0_out_214 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_215 <= 22'h0;
|
|
end else if (_T_1503) begin
|
|
btb_bank0_rd_data_way0_out_215 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_216 <= 22'h0;
|
|
end else if (_T_1507) begin
|
|
btb_bank0_rd_data_way0_out_216 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_217 <= 22'h0;
|
|
end else if (_T_1511) begin
|
|
btb_bank0_rd_data_way0_out_217 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_218 <= 22'h0;
|
|
end else if (_T_1515) begin
|
|
btb_bank0_rd_data_way0_out_218 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_219 <= 22'h0;
|
|
end else if (_T_1519) begin
|
|
btb_bank0_rd_data_way0_out_219 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_220 <= 22'h0;
|
|
end else if (_T_1523) begin
|
|
btb_bank0_rd_data_way0_out_220 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_221 <= 22'h0;
|
|
end else if (_T_1527) begin
|
|
btb_bank0_rd_data_way0_out_221 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_222 <= 22'h0;
|
|
end else if (_T_1531) begin
|
|
btb_bank0_rd_data_way0_out_222 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_223 <= 22'h0;
|
|
end else if (_T_1535) begin
|
|
btb_bank0_rd_data_way0_out_223 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_224 <= 22'h0;
|
|
end else if (_T_1539) begin
|
|
btb_bank0_rd_data_way0_out_224 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_225 <= 22'h0;
|
|
end else if (_T_1543) begin
|
|
btb_bank0_rd_data_way0_out_225 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_226 <= 22'h0;
|
|
end else if (_T_1547) begin
|
|
btb_bank0_rd_data_way0_out_226 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_227 <= 22'h0;
|
|
end else if (_T_1551) begin
|
|
btb_bank0_rd_data_way0_out_227 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_228 <= 22'h0;
|
|
end else if (_T_1555) begin
|
|
btb_bank0_rd_data_way0_out_228 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_229 <= 22'h0;
|
|
end else if (_T_1559) begin
|
|
btb_bank0_rd_data_way0_out_229 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_230 <= 22'h0;
|
|
end else if (_T_1563) begin
|
|
btb_bank0_rd_data_way0_out_230 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_231 <= 22'h0;
|
|
end else if (_T_1567) begin
|
|
btb_bank0_rd_data_way0_out_231 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_232 <= 22'h0;
|
|
end else if (_T_1571) begin
|
|
btb_bank0_rd_data_way0_out_232 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_233 <= 22'h0;
|
|
end else if (_T_1575) begin
|
|
btb_bank0_rd_data_way0_out_233 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_234 <= 22'h0;
|
|
end else if (_T_1579) begin
|
|
btb_bank0_rd_data_way0_out_234 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_235 <= 22'h0;
|
|
end else if (_T_1583) begin
|
|
btb_bank0_rd_data_way0_out_235 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_236 <= 22'h0;
|
|
end else if (_T_1587) begin
|
|
btb_bank0_rd_data_way0_out_236 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_237 <= 22'h0;
|
|
end else if (_T_1591) begin
|
|
btb_bank0_rd_data_way0_out_237 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_238 <= 22'h0;
|
|
end else if (_T_1595) begin
|
|
btb_bank0_rd_data_way0_out_238 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_239 <= 22'h0;
|
|
end else if (_T_1599) begin
|
|
btb_bank0_rd_data_way0_out_239 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_240 <= 22'h0;
|
|
end else if (_T_1603) begin
|
|
btb_bank0_rd_data_way0_out_240 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_241 <= 22'h0;
|
|
end else if (_T_1607) begin
|
|
btb_bank0_rd_data_way0_out_241 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_242 <= 22'h0;
|
|
end else if (_T_1611) begin
|
|
btb_bank0_rd_data_way0_out_242 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_243 <= 22'h0;
|
|
end else if (_T_1615) begin
|
|
btb_bank0_rd_data_way0_out_243 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_244 <= 22'h0;
|
|
end else if (_T_1619) begin
|
|
btb_bank0_rd_data_way0_out_244 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_245 <= 22'h0;
|
|
end else if (_T_1623) begin
|
|
btb_bank0_rd_data_way0_out_245 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_246 <= 22'h0;
|
|
end else if (_T_1627) begin
|
|
btb_bank0_rd_data_way0_out_246 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_247 <= 22'h0;
|
|
end else if (_T_1631) begin
|
|
btb_bank0_rd_data_way0_out_247 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_248 <= 22'h0;
|
|
end else if (_T_1635) begin
|
|
btb_bank0_rd_data_way0_out_248 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_249 <= 22'h0;
|
|
end else if (_T_1639) begin
|
|
btb_bank0_rd_data_way0_out_249 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_250 <= 22'h0;
|
|
end else if (_T_1643) begin
|
|
btb_bank0_rd_data_way0_out_250 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_251 <= 22'h0;
|
|
end else if (_T_1647) begin
|
|
btb_bank0_rd_data_way0_out_251 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_252 <= 22'h0;
|
|
end else if (_T_1651) begin
|
|
btb_bank0_rd_data_way0_out_252 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_253 <= 22'h0;
|
|
end else if (_T_1655) begin
|
|
btb_bank0_rd_data_way0_out_253 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_254 <= 22'h0;
|
|
end else if (_T_1659) begin
|
|
btb_bank0_rd_data_way0_out_254 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way0_out_255 <= 22'h0;
|
|
end else if (_T_1663) begin
|
|
btb_bank0_rd_data_way0_out_255 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_0 <= 22'h0;
|
|
end else if (_T_1667) begin
|
|
btb_bank0_rd_data_way1_out_0 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_1 <= 22'h0;
|
|
end else if (_T_1671) begin
|
|
btb_bank0_rd_data_way1_out_1 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_2 <= 22'h0;
|
|
end else if (_T_1675) begin
|
|
btb_bank0_rd_data_way1_out_2 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_3 <= 22'h0;
|
|
end else if (_T_1679) begin
|
|
btb_bank0_rd_data_way1_out_3 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_4 <= 22'h0;
|
|
end else if (_T_1683) begin
|
|
btb_bank0_rd_data_way1_out_4 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_5 <= 22'h0;
|
|
end else if (_T_1687) begin
|
|
btb_bank0_rd_data_way1_out_5 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_6 <= 22'h0;
|
|
end else if (_T_1691) begin
|
|
btb_bank0_rd_data_way1_out_6 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_7 <= 22'h0;
|
|
end else if (_T_1695) begin
|
|
btb_bank0_rd_data_way1_out_7 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_8 <= 22'h0;
|
|
end else if (_T_1699) begin
|
|
btb_bank0_rd_data_way1_out_8 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_9 <= 22'h0;
|
|
end else if (_T_1703) begin
|
|
btb_bank0_rd_data_way1_out_9 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_10 <= 22'h0;
|
|
end else if (_T_1707) begin
|
|
btb_bank0_rd_data_way1_out_10 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_11 <= 22'h0;
|
|
end else if (_T_1711) begin
|
|
btb_bank0_rd_data_way1_out_11 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_12 <= 22'h0;
|
|
end else if (_T_1715) begin
|
|
btb_bank0_rd_data_way1_out_12 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_13 <= 22'h0;
|
|
end else if (_T_1719) begin
|
|
btb_bank0_rd_data_way1_out_13 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_14 <= 22'h0;
|
|
end else if (_T_1723) begin
|
|
btb_bank0_rd_data_way1_out_14 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_15 <= 22'h0;
|
|
end else if (_T_1727) begin
|
|
btb_bank0_rd_data_way1_out_15 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_16 <= 22'h0;
|
|
end else if (_T_1731) begin
|
|
btb_bank0_rd_data_way1_out_16 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_17 <= 22'h0;
|
|
end else if (_T_1735) begin
|
|
btb_bank0_rd_data_way1_out_17 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_18 <= 22'h0;
|
|
end else if (_T_1739) begin
|
|
btb_bank0_rd_data_way1_out_18 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_19 <= 22'h0;
|
|
end else if (_T_1743) begin
|
|
btb_bank0_rd_data_way1_out_19 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_20 <= 22'h0;
|
|
end else if (_T_1747) begin
|
|
btb_bank0_rd_data_way1_out_20 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_21 <= 22'h0;
|
|
end else if (_T_1751) begin
|
|
btb_bank0_rd_data_way1_out_21 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_22 <= 22'h0;
|
|
end else if (_T_1755) begin
|
|
btb_bank0_rd_data_way1_out_22 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_23 <= 22'h0;
|
|
end else if (_T_1759) begin
|
|
btb_bank0_rd_data_way1_out_23 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_24 <= 22'h0;
|
|
end else if (_T_1763) begin
|
|
btb_bank0_rd_data_way1_out_24 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_25 <= 22'h0;
|
|
end else if (_T_1767) begin
|
|
btb_bank0_rd_data_way1_out_25 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_26 <= 22'h0;
|
|
end else if (_T_1771) begin
|
|
btb_bank0_rd_data_way1_out_26 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_27 <= 22'h0;
|
|
end else if (_T_1775) begin
|
|
btb_bank0_rd_data_way1_out_27 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_28 <= 22'h0;
|
|
end else if (_T_1779) begin
|
|
btb_bank0_rd_data_way1_out_28 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_29 <= 22'h0;
|
|
end else if (_T_1783) begin
|
|
btb_bank0_rd_data_way1_out_29 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_30 <= 22'h0;
|
|
end else if (_T_1787) begin
|
|
btb_bank0_rd_data_way1_out_30 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_31 <= 22'h0;
|
|
end else if (_T_1791) begin
|
|
btb_bank0_rd_data_way1_out_31 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_32 <= 22'h0;
|
|
end else if (_T_1795) begin
|
|
btb_bank0_rd_data_way1_out_32 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_33 <= 22'h0;
|
|
end else if (_T_1799) begin
|
|
btb_bank0_rd_data_way1_out_33 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_34 <= 22'h0;
|
|
end else if (_T_1803) begin
|
|
btb_bank0_rd_data_way1_out_34 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_35 <= 22'h0;
|
|
end else if (_T_1807) begin
|
|
btb_bank0_rd_data_way1_out_35 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_36 <= 22'h0;
|
|
end else if (_T_1811) begin
|
|
btb_bank0_rd_data_way1_out_36 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_37 <= 22'h0;
|
|
end else if (_T_1815) begin
|
|
btb_bank0_rd_data_way1_out_37 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_38 <= 22'h0;
|
|
end else if (_T_1819) begin
|
|
btb_bank0_rd_data_way1_out_38 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_39 <= 22'h0;
|
|
end else if (_T_1823) begin
|
|
btb_bank0_rd_data_way1_out_39 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_40 <= 22'h0;
|
|
end else if (_T_1827) begin
|
|
btb_bank0_rd_data_way1_out_40 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_41 <= 22'h0;
|
|
end else if (_T_1831) begin
|
|
btb_bank0_rd_data_way1_out_41 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_42 <= 22'h0;
|
|
end else if (_T_1835) begin
|
|
btb_bank0_rd_data_way1_out_42 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_43 <= 22'h0;
|
|
end else if (_T_1839) begin
|
|
btb_bank0_rd_data_way1_out_43 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_44 <= 22'h0;
|
|
end else if (_T_1843) begin
|
|
btb_bank0_rd_data_way1_out_44 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_45 <= 22'h0;
|
|
end else if (_T_1847) begin
|
|
btb_bank0_rd_data_way1_out_45 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_46 <= 22'h0;
|
|
end else if (_T_1851) begin
|
|
btb_bank0_rd_data_way1_out_46 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_47 <= 22'h0;
|
|
end else if (_T_1855) begin
|
|
btb_bank0_rd_data_way1_out_47 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_48 <= 22'h0;
|
|
end else if (_T_1859) begin
|
|
btb_bank0_rd_data_way1_out_48 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_49 <= 22'h0;
|
|
end else if (_T_1863) begin
|
|
btb_bank0_rd_data_way1_out_49 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_50 <= 22'h0;
|
|
end else if (_T_1867) begin
|
|
btb_bank0_rd_data_way1_out_50 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_51 <= 22'h0;
|
|
end else if (_T_1871) begin
|
|
btb_bank0_rd_data_way1_out_51 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_52 <= 22'h0;
|
|
end else if (_T_1875) begin
|
|
btb_bank0_rd_data_way1_out_52 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_53 <= 22'h0;
|
|
end else if (_T_1879) begin
|
|
btb_bank0_rd_data_way1_out_53 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_54 <= 22'h0;
|
|
end else if (_T_1883) begin
|
|
btb_bank0_rd_data_way1_out_54 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_55 <= 22'h0;
|
|
end else if (_T_1887) begin
|
|
btb_bank0_rd_data_way1_out_55 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_56 <= 22'h0;
|
|
end else if (_T_1891) begin
|
|
btb_bank0_rd_data_way1_out_56 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_57 <= 22'h0;
|
|
end else if (_T_1895) begin
|
|
btb_bank0_rd_data_way1_out_57 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_58 <= 22'h0;
|
|
end else if (_T_1899) begin
|
|
btb_bank0_rd_data_way1_out_58 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_59 <= 22'h0;
|
|
end else if (_T_1903) begin
|
|
btb_bank0_rd_data_way1_out_59 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_60 <= 22'h0;
|
|
end else if (_T_1907) begin
|
|
btb_bank0_rd_data_way1_out_60 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_61 <= 22'h0;
|
|
end else if (_T_1911) begin
|
|
btb_bank0_rd_data_way1_out_61 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_62 <= 22'h0;
|
|
end else if (_T_1915) begin
|
|
btb_bank0_rd_data_way1_out_62 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_63 <= 22'h0;
|
|
end else if (_T_1919) begin
|
|
btb_bank0_rd_data_way1_out_63 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_64 <= 22'h0;
|
|
end else if (_T_1923) begin
|
|
btb_bank0_rd_data_way1_out_64 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_65 <= 22'h0;
|
|
end else if (_T_1927) begin
|
|
btb_bank0_rd_data_way1_out_65 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_66 <= 22'h0;
|
|
end else if (_T_1931) begin
|
|
btb_bank0_rd_data_way1_out_66 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_67 <= 22'h0;
|
|
end else if (_T_1935) begin
|
|
btb_bank0_rd_data_way1_out_67 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_68 <= 22'h0;
|
|
end else if (_T_1939) begin
|
|
btb_bank0_rd_data_way1_out_68 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_69 <= 22'h0;
|
|
end else if (_T_1943) begin
|
|
btb_bank0_rd_data_way1_out_69 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_70 <= 22'h0;
|
|
end else if (_T_1947) begin
|
|
btb_bank0_rd_data_way1_out_70 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_71 <= 22'h0;
|
|
end else if (_T_1951) begin
|
|
btb_bank0_rd_data_way1_out_71 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_72 <= 22'h0;
|
|
end else if (_T_1955) begin
|
|
btb_bank0_rd_data_way1_out_72 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_73 <= 22'h0;
|
|
end else if (_T_1959) begin
|
|
btb_bank0_rd_data_way1_out_73 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_74 <= 22'h0;
|
|
end else if (_T_1963) begin
|
|
btb_bank0_rd_data_way1_out_74 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_75 <= 22'h0;
|
|
end else if (_T_1967) begin
|
|
btb_bank0_rd_data_way1_out_75 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_76 <= 22'h0;
|
|
end else if (_T_1971) begin
|
|
btb_bank0_rd_data_way1_out_76 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_77 <= 22'h0;
|
|
end else if (_T_1975) begin
|
|
btb_bank0_rd_data_way1_out_77 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_78 <= 22'h0;
|
|
end else if (_T_1979) begin
|
|
btb_bank0_rd_data_way1_out_78 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_79 <= 22'h0;
|
|
end else if (_T_1983) begin
|
|
btb_bank0_rd_data_way1_out_79 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_80 <= 22'h0;
|
|
end else if (_T_1987) begin
|
|
btb_bank0_rd_data_way1_out_80 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_81 <= 22'h0;
|
|
end else if (_T_1991) begin
|
|
btb_bank0_rd_data_way1_out_81 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_82 <= 22'h0;
|
|
end else if (_T_1995) begin
|
|
btb_bank0_rd_data_way1_out_82 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_83 <= 22'h0;
|
|
end else if (_T_1999) begin
|
|
btb_bank0_rd_data_way1_out_83 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_84 <= 22'h0;
|
|
end else if (_T_2003) begin
|
|
btb_bank0_rd_data_way1_out_84 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_85 <= 22'h0;
|
|
end else if (_T_2007) begin
|
|
btb_bank0_rd_data_way1_out_85 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_86 <= 22'h0;
|
|
end else if (_T_2011) begin
|
|
btb_bank0_rd_data_way1_out_86 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_87 <= 22'h0;
|
|
end else if (_T_2015) begin
|
|
btb_bank0_rd_data_way1_out_87 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_88 <= 22'h0;
|
|
end else if (_T_2019) begin
|
|
btb_bank0_rd_data_way1_out_88 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_89 <= 22'h0;
|
|
end else if (_T_2023) begin
|
|
btb_bank0_rd_data_way1_out_89 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_90 <= 22'h0;
|
|
end else if (_T_2027) begin
|
|
btb_bank0_rd_data_way1_out_90 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_91 <= 22'h0;
|
|
end else if (_T_2031) begin
|
|
btb_bank0_rd_data_way1_out_91 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_92 <= 22'h0;
|
|
end else if (_T_2035) begin
|
|
btb_bank0_rd_data_way1_out_92 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_93 <= 22'h0;
|
|
end else if (_T_2039) begin
|
|
btb_bank0_rd_data_way1_out_93 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_94 <= 22'h0;
|
|
end else if (_T_2043) begin
|
|
btb_bank0_rd_data_way1_out_94 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_95 <= 22'h0;
|
|
end else if (_T_2047) begin
|
|
btb_bank0_rd_data_way1_out_95 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_96 <= 22'h0;
|
|
end else if (_T_2051) begin
|
|
btb_bank0_rd_data_way1_out_96 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_97 <= 22'h0;
|
|
end else if (_T_2055) begin
|
|
btb_bank0_rd_data_way1_out_97 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_98 <= 22'h0;
|
|
end else if (_T_2059) begin
|
|
btb_bank0_rd_data_way1_out_98 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_99 <= 22'h0;
|
|
end else if (_T_2063) begin
|
|
btb_bank0_rd_data_way1_out_99 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_100 <= 22'h0;
|
|
end else if (_T_2067) begin
|
|
btb_bank0_rd_data_way1_out_100 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_101 <= 22'h0;
|
|
end else if (_T_2071) begin
|
|
btb_bank0_rd_data_way1_out_101 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_102 <= 22'h0;
|
|
end else if (_T_2075) begin
|
|
btb_bank0_rd_data_way1_out_102 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_103 <= 22'h0;
|
|
end else if (_T_2079) begin
|
|
btb_bank0_rd_data_way1_out_103 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_104 <= 22'h0;
|
|
end else if (_T_2083) begin
|
|
btb_bank0_rd_data_way1_out_104 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_105 <= 22'h0;
|
|
end else if (_T_2087) begin
|
|
btb_bank0_rd_data_way1_out_105 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_106 <= 22'h0;
|
|
end else if (_T_2091) begin
|
|
btb_bank0_rd_data_way1_out_106 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_107 <= 22'h0;
|
|
end else if (_T_2095) begin
|
|
btb_bank0_rd_data_way1_out_107 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_108 <= 22'h0;
|
|
end else if (_T_2099) begin
|
|
btb_bank0_rd_data_way1_out_108 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_109 <= 22'h0;
|
|
end else if (_T_2103) begin
|
|
btb_bank0_rd_data_way1_out_109 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_110 <= 22'h0;
|
|
end else if (_T_2107) begin
|
|
btb_bank0_rd_data_way1_out_110 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_111 <= 22'h0;
|
|
end else if (_T_2111) begin
|
|
btb_bank0_rd_data_way1_out_111 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_112 <= 22'h0;
|
|
end else if (_T_2115) begin
|
|
btb_bank0_rd_data_way1_out_112 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_113 <= 22'h0;
|
|
end else if (_T_2119) begin
|
|
btb_bank0_rd_data_way1_out_113 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_114 <= 22'h0;
|
|
end else if (_T_2123) begin
|
|
btb_bank0_rd_data_way1_out_114 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_115 <= 22'h0;
|
|
end else if (_T_2127) begin
|
|
btb_bank0_rd_data_way1_out_115 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_116 <= 22'h0;
|
|
end else if (_T_2131) begin
|
|
btb_bank0_rd_data_way1_out_116 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_117 <= 22'h0;
|
|
end else if (_T_2135) begin
|
|
btb_bank0_rd_data_way1_out_117 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_118 <= 22'h0;
|
|
end else if (_T_2139) begin
|
|
btb_bank0_rd_data_way1_out_118 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_119 <= 22'h0;
|
|
end else if (_T_2143) begin
|
|
btb_bank0_rd_data_way1_out_119 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_120 <= 22'h0;
|
|
end else if (_T_2147) begin
|
|
btb_bank0_rd_data_way1_out_120 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_121 <= 22'h0;
|
|
end else if (_T_2151) begin
|
|
btb_bank0_rd_data_way1_out_121 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_122 <= 22'h0;
|
|
end else if (_T_2155) begin
|
|
btb_bank0_rd_data_way1_out_122 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_123 <= 22'h0;
|
|
end else if (_T_2159) begin
|
|
btb_bank0_rd_data_way1_out_123 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_124 <= 22'h0;
|
|
end else if (_T_2163) begin
|
|
btb_bank0_rd_data_way1_out_124 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_125 <= 22'h0;
|
|
end else if (_T_2167) begin
|
|
btb_bank0_rd_data_way1_out_125 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_126 <= 22'h0;
|
|
end else if (_T_2171) begin
|
|
btb_bank0_rd_data_way1_out_126 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_127 <= 22'h0;
|
|
end else if (_T_2175) begin
|
|
btb_bank0_rd_data_way1_out_127 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_128 <= 22'h0;
|
|
end else if (_T_2179) begin
|
|
btb_bank0_rd_data_way1_out_128 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_129 <= 22'h0;
|
|
end else if (_T_2183) begin
|
|
btb_bank0_rd_data_way1_out_129 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_130 <= 22'h0;
|
|
end else if (_T_2187) begin
|
|
btb_bank0_rd_data_way1_out_130 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_131 <= 22'h0;
|
|
end else if (_T_2191) begin
|
|
btb_bank0_rd_data_way1_out_131 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_132 <= 22'h0;
|
|
end else if (_T_2195) begin
|
|
btb_bank0_rd_data_way1_out_132 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_133 <= 22'h0;
|
|
end else if (_T_2199) begin
|
|
btb_bank0_rd_data_way1_out_133 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_134 <= 22'h0;
|
|
end else if (_T_2203) begin
|
|
btb_bank0_rd_data_way1_out_134 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_135 <= 22'h0;
|
|
end else if (_T_2207) begin
|
|
btb_bank0_rd_data_way1_out_135 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_136 <= 22'h0;
|
|
end else if (_T_2211) begin
|
|
btb_bank0_rd_data_way1_out_136 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_137 <= 22'h0;
|
|
end else if (_T_2215) begin
|
|
btb_bank0_rd_data_way1_out_137 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_138 <= 22'h0;
|
|
end else if (_T_2219) begin
|
|
btb_bank0_rd_data_way1_out_138 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_139 <= 22'h0;
|
|
end else if (_T_2223) begin
|
|
btb_bank0_rd_data_way1_out_139 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_140 <= 22'h0;
|
|
end else if (_T_2227) begin
|
|
btb_bank0_rd_data_way1_out_140 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_141 <= 22'h0;
|
|
end else if (_T_2231) begin
|
|
btb_bank0_rd_data_way1_out_141 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_142 <= 22'h0;
|
|
end else if (_T_2235) begin
|
|
btb_bank0_rd_data_way1_out_142 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_143 <= 22'h0;
|
|
end else if (_T_2239) begin
|
|
btb_bank0_rd_data_way1_out_143 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_144 <= 22'h0;
|
|
end else if (_T_2243) begin
|
|
btb_bank0_rd_data_way1_out_144 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_145 <= 22'h0;
|
|
end else if (_T_2247) begin
|
|
btb_bank0_rd_data_way1_out_145 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_146 <= 22'h0;
|
|
end else if (_T_2251) begin
|
|
btb_bank0_rd_data_way1_out_146 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_147 <= 22'h0;
|
|
end else if (_T_2255) begin
|
|
btb_bank0_rd_data_way1_out_147 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_148 <= 22'h0;
|
|
end else if (_T_2259) begin
|
|
btb_bank0_rd_data_way1_out_148 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_149 <= 22'h0;
|
|
end else if (_T_2263) begin
|
|
btb_bank0_rd_data_way1_out_149 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_150 <= 22'h0;
|
|
end else if (_T_2267) begin
|
|
btb_bank0_rd_data_way1_out_150 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_151 <= 22'h0;
|
|
end else if (_T_2271) begin
|
|
btb_bank0_rd_data_way1_out_151 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_152 <= 22'h0;
|
|
end else if (_T_2275) begin
|
|
btb_bank0_rd_data_way1_out_152 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_153 <= 22'h0;
|
|
end else if (_T_2279) begin
|
|
btb_bank0_rd_data_way1_out_153 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_154 <= 22'h0;
|
|
end else if (_T_2283) begin
|
|
btb_bank0_rd_data_way1_out_154 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_155 <= 22'h0;
|
|
end else if (_T_2287) begin
|
|
btb_bank0_rd_data_way1_out_155 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_156 <= 22'h0;
|
|
end else if (_T_2291) begin
|
|
btb_bank0_rd_data_way1_out_156 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_157 <= 22'h0;
|
|
end else if (_T_2295) begin
|
|
btb_bank0_rd_data_way1_out_157 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_158 <= 22'h0;
|
|
end else if (_T_2299) begin
|
|
btb_bank0_rd_data_way1_out_158 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_159 <= 22'h0;
|
|
end else if (_T_2303) begin
|
|
btb_bank0_rd_data_way1_out_159 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_160 <= 22'h0;
|
|
end else if (_T_2307) begin
|
|
btb_bank0_rd_data_way1_out_160 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_161 <= 22'h0;
|
|
end else if (_T_2311) begin
|
|
btb_bank0_rd_data_way1_out_161 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_162 <= 22'h0;
|
|
end else if (_T_2315) begin
|
|
btb_bank0_rd_data_way1_out_162 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_163 <= 22'h0;
|
|
end else if (_T_2319) begin
|
|
btb_bank0_rd_data_way1_out_163 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_164 <= 22'h0;
|
|
end else if (_T_2323) begin
|
|
btb_bank0_rd_data_way1_out_164 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_165 <= 22'h0;
|
|
end else if (_T_2327) begin
|
|
btb_bank0_rd_data_way1_out_165 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_166 <= 22'h0;
|
|
end else if (_T_2331) begin
|
|
btb_bank0_rd_data_way1_out_166 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_167 <= 22'h0;
|
|
end else if (_T_2335) begin
|
|
btb_bank0_rd_data_way1_out_167 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_168 <= 22'h0;
|
|
end else if (_T_2339) begin
|
|
btb_bank0_rd_data_way1_out_168 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_169 <= 22'h0;
|
|
end else if (_T_2343) begin
|
|
btb_bank0_rd_data_way1_out_169 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_170 <= 22'h0;
|
|
end else if (_T_2347) begin
|
|
btb_bank0_rd_data_way1_out_170 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_171 <= 22'h0;
|
|
end else if (_T_2351) begin
|
|
btb_bank0_rd_data_way1_out_171 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_172 <= 22'h0;
|
|
end else if (_T_2355) begin
|
|
btb_bank0_rd_data_way1_out_172 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_173 <= 22'h0;
|
|
end else if (_T_2359) begin
|
|
btb_bank0_rd_data_way1_out_173 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_174 <= 22'h0;
|
|
end else if (_T_2363) begin
|
|
btb_bank0_rd_data_way1_out_174 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_175 <= 22'h0;
|
|
end else if (_T_2367) begin
|
|
btb_bank0_rd_data_way1_out_175 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_176 <= 22'h0;
|
|
end else if (_T_2371) begin
|
|
btb_bank0_rd_data_way1_out_176 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_177 <= 22'h0;
|
|
end else if (_T_2375) begin
|
|
btb_bank0_rd_data_way1_out_177 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_178 <= 22'h0;
|
|
end else if (_T_2379) begin
|
|
btb_bank0_rd_data_way1_out_178 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_179 <= 22'h0;
|
|
end else if (_T_2383) begin
|
|
btb_bank0_rd_data_way1_out_179 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_180 <= 22'h0;
|
|
end else if (_T_2387) begin
|
|
btb_bank0_rd_data_way1_out_180 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_181 <= 22'h0;
|
|
end else if (_T_2391) begin
|
|
btb_bank0_rd_data_way1_out_181 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_182 <= 22'h0;
|
|
end else if (_T_2395) begin
|
|
btb_bank0_rd_data_way1_out_182 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_183 <= 22'h0;
|
|
end else if (_T_2399) begin
|
|
btb_bank0_rd_data_way1_out_183 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_184 <= 22'h0;
|
|
end else if (_T_2403) begin
|
|
btb_bank0_rd_data_way1_out_184 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_185 <= 22'h0;
|
|
end else if (_T_2407) begin
|
|
btb_bank0_rd_data_way1_out_185 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_186 <= 22'h0;
|
|
end else if (_T_2411) begin
|
|
btb_bank0_rd_data_way1_out_186 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_187 <= 22'h0;
|
|
end else if (_T_2415) begin
|
|
btb_bank0_rd_data_way1_out_187 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_188 <= 22'h0;
|
|
end else if (_T_2419) begin
|
|
btb_bank0_rd_data_way1_out_188 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_189 <= 22'h0;
|
|
end else if (_T_2423) begin
|
|
btb_bank0_rd_data_way1_out_189 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_190 <= 22'h0;
|
|
end else if (_T_2427) begin
|
|
btb_bank0_rd_data_way1_out_190 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_191 <= 22'h0;
|
|
end else if (_T_2431) begin
|
|
btb_bank0_rd_data_way1_out_191 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_192 <= 22'h0;
|
|
end else if (_T_2435) begin
|
|
btb_bank0_rd_data_way1_out_192 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_193 <= 22'h0;
|
|
end else if (_T_2439) begin
|
|
btb_bank0_rd_data_way1_out_193 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_194 <= 22'h0;
|
|
end else if (_T_2443) begin
|
|
btb_bank0_rd_data_way1_out_194 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_195 <= 22'h0;
|
|
end else if (_T_2447) begin
|
|
btb_bank0_rd_data_way1_out_195 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_196 <= 22'h0;
|
|
end else if (_T_2451) begin
|
|
btb_bank0_rd_data_way1_out_196 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_197 <= 22'h0;
|
|
end else if (_T_2455) begin
|
|
btb_bank0_rd_data_way1_out_197 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_198 <= 22'h0;
|
|
end else if (_T_2459) begin
|
|
btb_bank0_rd_data_way1_out_198 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_199 <= 22'h0;
|
|
end else if (_T_2463) begin
|
|
btb_bank0_rd_data_way1_out_199 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_200 <= 22'h0;
|
|
end else if (_T_2467) begin
|
|
btb_bank0_rd_data_way1_out_200 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_201 <= 22'h0;
|
|
end else if (_T_2471) begin
|
|
btb_bank0_rd_data_way1_out_201 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_202 <= 22'h0;
|
|
end else if (_T_2475) begin
|
|
btb_bank0_rd_data_way1_out_202 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_203 <= 22'h0;
|
|
end else if (_T_2479) begin
|
|
btb_bank0_rd_data_way1_out_203 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_204 <= 22'h0;
|
|
end else if (_T_2483) begin
|
|
btb_bank0_rd_data_way1_out_204 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_205 <= 22'h0;
|
|
end else if (_T_2487) begin
|
|
btb_bank0_rd_data_way1_out_205 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_206 <= 22'h0;
|
|
end else if (_T_2491) begin
|
|
btb_bank0_rd_data_way1_out_206 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_207 <= 22'h0;
|
|
end else if (_T_2495) begin
|
|
btb_bank0_rd_data_way1_out_207 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_208 <= 22'h0;
|
|
end else if (_T_2499) begin
|
|
btb_bank0_rd_data_way1_out_208 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_209 <= 22'h0;
|
|
end else if (_T_2503) begin
|
|
btb_bank0_rd_data_way1_out_209 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_210 <= 22'h0;
|
|
end else if (_T_2507) begin
|
|
btb_bank0_rd_data_way1_out_210 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_211 <= 22'h0;
|
|
end else if (_T_2511) begin
|
|
btb_bank0_rd_data_way1_out_211 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_212 <= 22'h0;
|
|
end else if (_T_2515) begin
|
|
btb_bank0_rd_data_way1_out_212 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_213 <= 22'h0;
|
|
end else if (_T_2519) begin
|
|
btb_bank0_rd_data_way1_out_213 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_214 <= 22'h0;
|
|
end else if (_T_2523) begin
|
|
btb_bank0_rd_data_way1_out_214 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_215 <= 22'h0;
|
|
end else if (_T_2527) begin
|
|
btb_bank0_rd_data_way1_out_215 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_216 <= 22'h0;
|
|
end else if (_T_2531) begin
|
|
btb_bank0_rd_data_way1_out_216 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_217 <= 22'h0;
|
|
end else if (_T_2535) begin
|
|
btb_bank0_rd_data_way1_out_217 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_218 <= 22'h0;
|
|
end else if (_T_2539) begin
|
|
btb_bank0_rd_data_way1_out_218 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_219 <= 22'h0;
|
|
end else if (_T_2543) begin
|
|
btb_bank0_rd_data_way1_out_219 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_220 <= 22'h0;
|
|
end else if (_T_2547) begin
|
|
btb_bank0_rd_data_way1_out_220 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_221 <= 22'h0;
|
|
end else if (_T_2551) begin
|
|
btb_bank0_rd_data_way1_out_221 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_222 <= 22'h0;
|
|
end else if (_T_2555) begin
|
|
btb_bank0_rd_data_way1_out_222 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_223 <= 22'h0;
|
|
end else if (_T_2559) begin
|
|
btb_bank0_rd_data_way1_out_223 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_224 <= 22'h0;
|
|
end else if (_T_2563) begin
|
|
btb_bank0_rd_data_way1_out_224 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_225 <= 22'h0;
|
|
end else if (_T_2567) begin
|
|
btb_bank0_rd_data_way1_out_225 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_226 <= 22'h0;
|
|
end else if (_T_2571) begin
|
|
btb_bank0_rd_data_way1_out_226 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_227 <= 22'h0;
|
|
end else if (_T_2575) begin
|
|
btb_bank0_rd_data_way1_out_227 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_228 <= 22'h0;
|
|
end else if (_T_2579) begin
|
|
btb_bank0_rd_data_way1_out_228 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_229 <= 22'h0;
|
|
end else if (_T_2583) begin
|
|
btb_bank0_rd_data_way1_out_229 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_230 <= 22'h0;
|
|
end else if (_T_2587) begin
|
|
btb_bank0_rd_data_way1_out_230 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_231 <= 22'h0;
|
|
end else if (_T_2591) begin
|
|
btb_bank0_rd_data_way1_out_231 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_232 <= 22'h0;
|
|
end else if (_T_2595) begin
|
|
btb_bank0_rd_data_way1_out_232 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_233 <= 22'h0;
|
|
end else if (_T_2599) begin
|
|
btb_bank0_rd_data_way1_out_233 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_234 <= 22'h0;
|
|
end else if (_T_2603) begin
|
|
btb_bank0_rd_data_way1_out_234 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_235 <= 22'h0;
|
|
end else if (_T_2607) begin
|
|
btb_bank0_rd_data_way1_out_235 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_236 <= 22'h0;
|
|
end else if (_T_2611) begin
|
|
btb_bank0_rd_data_way1_out_236 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_237 <= 22'h0;
|
|
end else if (_T_2615) begin
|
|
btb_bank0_rd_data_way1_out_237 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_238 <= 22'h0;
|
|
end else if (_T_2619) begin
|
|
btb_bank0_rd_data_way1_out_238 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_239 <= 22'h0;
|
|
end else if (_T_2623) begin
|
|
btb_bank0_rd_data_way1_out_239 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_240 <= 22'h0;
|
|
end else if (_T_2627) begin
|
|
btb_bank0_rd_data_way1_out_240 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_241 <= 22'h0;
|
|
end else if (_T_2631) begin
|
|
btb_bank0_rd_data_way1_out_241 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_242 <= 22'h0;
|
|
end else if (_T_2635) begin
|
|
btb_bank0_rd_data_way1_out_242 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_243 <= 22'h0;
|
|
end else if (_T_2639) begin
|
|
btb_bank0_rd_data_way1_out_243 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_244 <= 22'h0;
|
|
end else if (_T_2643) begin
|
|
btb_bank0_rd_data_way1_out_244 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_245 <= 22'h0;
|
|
end else if (_T_2647) begin
|
|
btb_bank0_rd_data_way1_out_245 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_246 <= 22'h0;
|
|
end else if (_T_2651) begin
|
|
btb_bank0_rd_data_way1_out_246 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_247 <= 22'h0;
|
|
end else if (_T_2655) begin
|
|
btb_bank0_rd_data_way1_out_247 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_248 <= 22'h0;
|
|
end else if (_T_2659) begin
|
|
btb_bank0_rd_data_way1_out_248 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_249 <= 22'h0;
|
|
end else if (_T_2663) begin
|
|
btb_bank0_rd_data_way1_out_249 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_250 <= 22'h0;
|
|
end else if (_T_2667) begin
|
|
btb_bank0_rd_data_way1_out_250 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_251 <= 22'h0;
|
|
end else if (_T_2671) begin
|
|
btb_bank0_rd_data_way1_out_251 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_252 <= 22'h0;
|
|
end else if (_T_2675) begin
|
|
btb_bank0_rd_data_way1_out_252 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_253 <= 22'h0;
|
|
end else if (_T_2679) begin
|
|
btb_bank0_rd_data_way1_out_253 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_254 <= 22'h0;
|
|
end else if (_T_2683) begin
|
|
btb_bank0_rd_data_way1_out_254 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_bank0_rd_data_way1_out_255 <= 22'h0;
|
|
end else if (_T_2687) begin
|
|
btb_bank0_rd_data_way1_out_255 <= btb_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fghr <= 8'h0;
|
|
end else if (_T_375) begin
|
|
fghr <= fghr_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_0 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_0) begin
|
|
if (_T_9449) begin
|
|
bht_bank_rd_data_out_1_0 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_0 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_1 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_1) begin
|
|
if (_T_9458) begin
|
|
bht_bank_rd_data_out_1_1 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_1 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_2 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_2) begin
|
|
if (_T_9467) begin
|
|
bht_bank_rd_data_out_1_2 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_2 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_3 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_3) begin
|
|
if (_T_9476) begin
|
|
bht_bank_rd_data_out_1_3 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_3 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_4 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_4) begin
|
|
if (_T_9485) begin
|
|
bht_bank_rd_data_out_1_4 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_4 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_5 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_5) begin
|
|
if (_T_9494) begin
|
|
bht_bank_rd_data_out_1_5 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_5 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_6 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_6) begin
|
|
if (_T_9503) begin
|
|
bht_bank_rd_data_out_1_6 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_6 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_7 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_7) begin
|
|
if (_T_9512) begin
|
|
bht_bank_rd_data_out_1_7 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_7 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_8 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_8) begin
|
|
if (_T_9521) begin
|
|
bht_bank_rd_data_out_1_8 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_8 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_9 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_9) begin
|
|
if (_T_9530) begin
|
|
bht_bank_rd_data_out_1_9 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_9 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_10 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_10) begin
|
|
if (_T_9539) begin
|
|
bht_bank_rd_data_out_1_10 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_10 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_11 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_11) begin
|
|
if (_T_9548) begin
|
|
bht_bank_rd_data_out_1_11 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_11 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_12 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_12) begin
|
|
if (_T_9557) begin
|
|
bht_bank_rd_data_out_1_12 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_12 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_13 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_13) begin
|
|
if (_T_9566) begin
|
|
bht_bank_rd_data_out_1_13 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_13 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_14 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_14) begin
|
|
if (_T_9575) begin
|
|
bht_bank_rd_data_out_1_14 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_14 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_15 <= 2'h0;
|
|
end else if (bht_bank_sel_1_0_15) begin
|
|
if (_T_9584) begin
|
|
bht_bank_rd_data_out_1_15 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_15 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_16 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_0) begin
|
|
if (_T_9593) begin
|
|
bht_bank_rd_data_out_1_16 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_16 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_17 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_1) begin
|
|
if (_T_9602) begin
|
|
bht_bank_rd_data_out_1_17 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_17 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_18 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_2) begin
|
|
if (_T_9611) begin
|
|
bht_bank_rd_data_out_1_18 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_18 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_19 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_3) begin
|
|
if (_T_9620) begin
|
|
bht_bank_rd_data_out_1_19 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_19 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_20 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_4) begin
|
|
if (_T_9629) begin
|
|
bht_bank_rd_data_out_1_20 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_20 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_21 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_5) begin
|
|
if (_T_9638) begin
|
|
bht_bank_rd_data_out_1_21 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_21 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_22 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_6) begin
|
|
if (_T_9647) begin
|
|
bht_bank_rd_data_out_1_22 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_22 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_23 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_7) begin
|
|
if (_T_9656) begin
|
|
bht_bank_rd_data_out_1_23 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_23 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_24 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_8) begin
|
|
if (_T_9665) begin
|
|
bht_bank_rd_data_out_1_24 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_24 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_25 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_9) begin
|
|
if (_T_9674) begin
|
|
bht_bank_rd_data_out_1_25 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_25 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_26 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_10) begin
|
|
if (_T_9683) begin
|
|
bht_bank_rd_data_out_1_26 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_26 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_27 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_11) begin
|
|
if (_T_9692) begin
|
|
bht_bank_rd_data_out_1_27 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_27 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_28 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_12) begin
|
|
if (_T_9701) begin
|
|
bht_bank_rd_data_out_1_28 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_28 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_29 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_13) begin
|
|
if (_T_9710) begin
|
|
bht_bank_rd_data_out_1_29 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_29 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_30 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_14) begin
|
|
if (_T_9719) begin
|
|
bht_bank_rd_data_out_1_30 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_30 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_31 <= 2'h0;
|
|
end else if (bht_bank_sel_1_1_15) begin
|
|
if (_T_9728) begin
|
|
bht_bank_rd_data_out_1_31 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_31 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_32 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_0) begin
|
|
if (_T_9737) begin
|
|
bht_bank_rd_data_out_1_32 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_32 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_33 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_1) begin
|
|
if (_T_9746) begin
|
|
bht_bank_rd_data_out_1_33 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_33 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_34 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_2) begin
|
|
if (_T_9755) begin
|
|
bht_bank_rd_data_out_1_34 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_34 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_35 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_3) begin
|
|
if (_T_9764) begin
|
|
bht_bank_rd_data_out_1_35 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_35 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_36 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_4) begin
|
|
if (_T_9773) begin
|
|
bht_bank_rd_data_out_1_36 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_36 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_37 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_5) begin
|
|
if (_T_9782) begin
|
|
bht_bank_rd_data_out_1_37 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_37 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_38 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_6) begin
|
|
if (_T_9791) begin
|
|
bht_bank_rd_data_out_1_38 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_38 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_39 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_7) begin
|
|
if (_T_9800) begin
|
|
bht_bank_rd_data_out_1_39 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_39 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_40 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_8) begin
|
|
if (_T_9809) begin
|
|
bht_bank_rd_data_out_1_40 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_40 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_41 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_9) begin
|
|
if (_T_9818) begin
|
|
bht_bank_rd_data_out_1_41 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_41 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_42 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_10) begin
|
|
if (_T_9827) begin
|
|
bht_bank_rd_data_out_1_42 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_42 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_43 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_11) begin
|
|
if (_T_9836) begin
|
|
bht_bank_rd_data_out_1_43 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_43 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_44 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_12) begin
|
|
if (_T_9845) begin
|
|
bht_bank_rd_data_out_1_44 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_44 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_45 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_13) begin
|
|
if (_T_9854) begin
|
|
bht_bank_rd_data_out_1_45 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_45 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_46 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_14) begin
|
|
if (_T_9863) begin
|
|
bht_bank_rd_data_out_1_46 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_46 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_47 <= 2'h0;
|
|
end else if (bht_bank_sel_1_2_15) begin
|
|
if (_T_9872) begin
|
|
bht_bank_rd_data_out_1_47 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_47 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_48 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_0) begin
|
|
if (_T_9881) begin
|
|
bht_bank_rd_data_out_1_48 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_48 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_49 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_1) begin
|
|
if (_T_9890) begin
|
|
bht_bank_rd_data_out_1_49 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_49 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_50 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_2) begin
|
|
if (_T_9899) begin
|
|
bht_bank_rd_data_out_1_50 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_50 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_51 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_3) begin
|
|
if (_T_9908) begin
|
|
bht_bank_rd_data_out_1_51 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_51 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_52 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_4) begin
|
|
if (_T_9917) begin
|
|
bht_bank_rd_data_out_1_52 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_52 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_53 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_5) begin
|
|
if (_T_9926) begin
|
|
bht_bank_rd_data_out_1_53 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_53 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_54 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_6) begin
|
|
if (_T_9935) begin
|
|
bht_bank_rd_data_out_1_54 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_54 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_55 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_7) begin
|
|
if (_T_9944) begin
|
|
bht_bank_rd_data_out_1_55 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_55 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_56 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_8) begin
|
|
if (_T_9953) begin
|
|
bht_bank_rd_data_out_1_56 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_56 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_57 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_9) begin
|
|
if (_T_9962) begin
|
|
bht_bank_rd_data_out_1_57 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_57 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_58 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_10) begin
|
|
if (_T_9971) begin
|
|
bht_bank_rd_data_out_1_58 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_58 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_59 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_11) begin
|
|
if (_T_9980) begin
|
|
bht_bank_rd_data_out_1_59 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_59 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_60 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_12) begin
|
|
if (_T_9989) begin
|
|
bht_bank_rd_data_out_1_60 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_60 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_61 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_13) begin
|
|
if (_T_9998) begin
|
|
bht_bank_rd_data_out_1_61 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_61 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_62 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_14) begin
|
|
if (_T_10007) begin
|
|
bht_bank_rd_data_out_1_62 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_62 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_63 <= 2'h0;
|
|
end else if (bht_bank_sel_1_3_15) begin
|
|
if (_T_10016) begin
|
|
bht_bank_rd_data_out_1_63 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_63 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_64 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_0) begin
|
|
if (_T_10025) begin
|
|
bht_bank_rd_data_out_1_64 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_64 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_65 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_1) begin
|
|
if (_T_10034) begin
|
|
bht_bank_rd_data_out_1_65 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_65 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_66 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_2) begin
|
|
if (_T_10043) begin
|
|
bht_bank_rd_data_out_1_66 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_66 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_67 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_3) begin
|
|
if (_T_10052) begin
|
|
bht_bank_rd_data_out_1_67 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_67 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_68 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_4) begin
|
|
if (_T_10061) begin
|
|
bht_bank_rd_data_out_1_68 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_68 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_69 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_5) begin
|
|
if (_T_10070) begin
|
|
bht_bank_rd_data_out_1_69 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_69 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_70 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_6) begin
|
|
if (_T_10079) begin
|
|
bht_bank_rd_data_out_1_70 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_70 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_71 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_7) begin
|
|
if (_T_10088) begin
|
|
bht_bank_rd_data_out_1_71 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_71 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_72 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_8) begin
|
|
if (_T_10097) begin
|
|
bht_bank_rd_data_out_1_72 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_72 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_73 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_9) begin
|
|
if (_T_10106) begin
|
|
bht_bank_rd_data_out_1_73 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_73 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_74 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_10) begin
|
|
if (_T_10115) begin
|
|
bht_bank_rd_data_out_1_74 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_74 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_75 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_11) begin
|
|
if (_T_10124) begin
|
|
bht_bank_rd_data_out_1_75 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_75 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_76 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_12) begin
|
|
if (_T_10133) begin
|
|
bht_bank_rd_data_out_1_76 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_76 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_77 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_13) begin
|
|
if (_T_10142) begin
|
|
bht_bank_rd_data_out_1_77 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_77 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_78 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_14) begin
|
|
if (_T_10151) begin
|
|
bht_bank_rd_data_out_1_78 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_78 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_79 <= 2'h0;
|
|
end else if (bht_bank_sel_1_4_15) begin
|
|
if (_T_10160) begin
|
|
bht_bank_rd_data_out_1_79 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_79 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_80 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_0) begin
|
|
if (_T_10169) begin
|
|
bht_bank_rd_data_out_1_80 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_80 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_81 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_1) begin
|
|
if (_T_10178) begin
|
|
bht_bank_rd_data_out_1_81 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_81 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_82 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_2) begin
|
|
if (_T_10187) begin
|
|
bht_bank_rd_data_out_1_82 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_82 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_83 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_3) begin
|
|
if (_T_10196) begin
|
|
bht_bank_rd_data_out_1_83 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_83 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_84 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_4) begin
|
|
if (_T_10205) begin
|
|
bht_bank_rd_data_out_1_84 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_84 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_85 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_5) begin
|
|
if (_T_10214) begin
|
|
bht_bank_rd_data_out_1_85 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_85 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_86 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_6) begin
|
|
if (_T_10223) begin
|
|
bht_bank_rd_data_out_1_86 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_86 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_87 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_7) begin
|
|
if (_T_10232) begin
|
|
bht_bank_rd_data_out_1_87 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_87 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_88 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_8) begin
|
|
if (_T_10241) begin
|
|
bht_bank_rd_data_out_1_88 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_88 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_89 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_9) begin
|
|
if (_T_10250) begin
|
|
bht_bank_rd_data_out_1_89 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_89 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_90 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_10) begin
|
|
if (_T_10259) begin
|
|
bht_bank_rd_data_out_1_90 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_90 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_91 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_11) begin
|
|
if (_T_10268) begin
|
|
bht_bank_rd_data_out_1_91 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_91 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_92 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_12) begin
|
|
if (_T_10277) begin
|
|
bht_bank_rd_data_out_1_92 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_92 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_93 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_13) begin
|
|
if (_T_10286) begin
|
|
bht_bank_rd_data_out_1_93 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_93 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_94 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_14) begin
|
|
if (_T_10295) begin
|
|
bht_bank_rd_data_out_1_94 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_94 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_95 <= 2'h0;
|
|
end else if (bht_bank_sel_1_5_15) begin
|
|
if (_T_10304) begin
|
|
bht_bank_rd_data_out_1_95 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_95 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_96 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_0) begin
|
|
if (_T_10313) begin
|
|
bht_bank_rd_data_out_1_96 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_96 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_97 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_1) begin
|
|
if (_T_10322) begin
|
|
bht_bank_rd_data_out_1_97 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_97 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_98 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_2) begin
|
|
if (_T_10331) begin
|
|
bht_bank_rd_data_out_1_98 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_98 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_99 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_3) begin
|
|
if (_T_10340) begin
|
|
bht_bank_rd_data_out_1_99 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_99 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_100 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_4) begin
|
|
if (_T_10349) begin
|
|
bht_bank_rd_data_out_1_100 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_100 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_101 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_5) begin
|
|
if (_T_10358) begin
|
|
bht_bank_rd_data_out_1_101 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_101 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_102 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_6) begin
|
|
if (_T_10367) begin
|
|
bht_bank_rd_data_out_1_102 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_102 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_103 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_7) begin
|
|
if (_T_10376) begin
|
|
bht_bank_rd_data_out_1_103 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_103 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_104 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_8) begin
|
|
if (_T_10385) begin
|
|
bht_bank_rd_data_out_1_104 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_104 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_105 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_9) begin
|
|
if (_T_10394) begin
|
|
bht_bank_rd_data_out_1_105 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_105 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_106 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_10) begin
|
|
if (_T_10403) begin
|
|
bht_bank_rd_data_out_1_106 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_106 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_107 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_11) begin
|
|
if (_T_10412) begin
|
|
bht_bank_rd_data_out_1_107 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_107 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_108 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_12) begin
|
|
if (_T_10421) begin
|
|
bht_bank_rd_data_out_1_108 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_108 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_109 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_13) begin
|
|
if (_T_10430) begin
|
|
bht_bank_rd_data_out_1_109 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_109 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_110 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_14) begin
|
|
if (_T_10439) begin
|
|
bht_bank_rd_data_out_1_110 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_110 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_111 <= 2'h0;
|
|
end else if (bht_bank_sel_1_6_15) begin
|
|
if (_T_10448) begin
|
|
bht_bank_rd_data_out_1_111 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_111 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_112 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_0) begin
|
|
if (_T_10457) begin
|
|
bht_bank_rd_data_out_1_112 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_112 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_113 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_1) begin
|
|
if (_T_10466) begin
|
|
bht_bank_rd_data_out_1_113 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_113 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_114 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_2) begin
|
|
if (_T_10475) begin
|
|
bht_bank_rd_data_out_1_114 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_114 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_115 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_3) begin
|
|
if (_T_10484) begin
|
|
bht_bank_rd_data_out_1_115 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_115 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_116 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_4) begin
|
|
if (_T_10493) begin
|
|
bht_bank_rd_data_out_1_116 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_116 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_117 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_5) begin
|
|
if (_T_10502) begin
|
|
bht_bank_rd_data_out_1_117 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_117 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_118 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_6) begin
|
|
if (_T_10511) begin
|
|
bht_bank_rd_data_out_1_118 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_118 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_119 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_7) begin
|
|
if (_T_10520) begin
|
|
bht_bank_rd_data_out_1_119 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_119 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_120 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_8) begin
|
|
if (_T_10529) begin
|
|
bht_bank_rd_data_out_1_120 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_120 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_121 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_9) begin
|
|
if (_T_10538) begin
|
|
bht_bank_rd_data_out_1_121 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_121 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_122 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_10) begin
|
|
if (_T_10547) begin
|
|
bht_bank_rd_data_out_1_122 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_122 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_123 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_11) begin
|
|
if (_T_10556) begin
|
|
bht_bank_rd_data_out_1_123 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_123 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_124 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_12) begin
|
|
if (_T_10565) begin
|
|
bht_bank_rd_data_out_1_124 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_124 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_125 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_13) begin
|
|
if (_T_10574) begin
|
|
bht_bank_rd_data_out_1_125 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_125 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_126 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_14) begin
|
|
if (_T_10583) begin
|
|
bht_bank_rd_data_out_1_126 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_126 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_127 <= 2'h0;
|
|
end else if (bht_bank_sel_1_7_15) begin
|
|
if (_T_10592) begin
|
|
bht_bank_rd_data_out_1_127 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_127 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_128 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_0) begin
|
|
if (_T_10601) begin
|
|
bht_bank_rd_data_out_1_128 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_128 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_129 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_1) begin
|
|
if (_T_10610) begin
|
|
bht_bank_rd_data_out_1_129 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_129 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_130 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_2) begin
|
|
if (_T_10619) begin
|
|
bht_bank_rd_data_out_1_130 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_130 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_131 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_3) begin
|
|
if (_T_10628) begin
|
|
bht_bank_rd_data_out_1_131 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_131 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_132 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_4) begin
|
|
if (_T_10637) begin
|
|
bht_bank_rd_data_out_1_132 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_132 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_133 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_5) begin
|
|
if (_T_10646) begin
|
|
bht_bank_rd_data_out_1_133 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_133 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_134 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_6) begin
|
|
if (_T_10655) begin
|
|
bht_bank_rd_data_out_1_134 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_134 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_135 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_7) begin
|
|
if (_T_10664) begin
|
|
bht_bank_rd_data_out_1_135 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_135 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_136 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_8) begin
|
|
if (_T_10673) begin
|
|
bht_bank_rd_data_out_1_136 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_136 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_137 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_9) begin
|
|
if (_T_10682) begin
|
|
bht_bank_rd_data_out_1_137 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_137 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_138 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_10) begin
|
|
if (_T_10691) begin
|
|
bht_bank_rd_data_out_1_138 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_138 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_139 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_11) begin
|
|
if (_T_10700) begin
|
|
bht_bank_rd_data_out_1_139 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_139 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_140 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_12) begin
|
|
if (_T_10709) begin
|
|
bht_bank_rd_data_out_1_140 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_140 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_141 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_13) begin
|
|
if (_T_10718) begin
|
|
bht_bank_rd_data_out_1_141 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_141 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_142 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_14) begin
|
|
if (_T_10727) begin
|
|
bht_bank_rd_data_out_1_142 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_142 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_143 <= 2'h0;
|
|
end else if (bht_bank_sel_1_8_15) begin
|
|
if (_T_10736) begin
|
|
bht_bank_rd_data_out_1_143 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_143 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_144 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_0) begin
|
|
if (_T_10745) begin
|
|
bht_bank_rd_data_out_1_144 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_144 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_145 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_1) begin
|
|
if (_T_10754) begin
|
|
bht_bank_rd_data_out_1_145 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_145 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_146 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_2) begin
|
|
if (_T_10763) begin
|
|
bht_bank_rd_data_out_1_146 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_146 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_147 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_3) begin
|
|
if (_T_10772) begin
|
|
bht_bank_rd_data_out_1_147 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_147 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_148 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_4) begin
|
|
if (_T_10781) begin
|
|
bht_bank_rd_data_out_1_148 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_148 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_149 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_5) begin
|
|
if (_T_10790) begin
|
|
bht_bank_rd_data_out_1_149 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_149 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_150 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_6) begin
|
|
if (_T_10799) begin
|
|
bht_bank_rd_data_out_1_150 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_150 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_151 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_7) begin
|
|
if (_T_10808) begin
|
|
bht_bank_rd_data_out_1_151 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_151 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_152 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_8) begin
|
|
if (_T_10817) begin
|
|
bht_bank_rd_data_out_1_152 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_152 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_153 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_9) begin
|
|
if (_T_10826) begin
|
|
bht_bank_rd_data_out_1_153 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_153 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_154 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_10) begin
|
|
if (_T_10835) begin
|
|
bht_bank_rd_data_out_1_154 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_154 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_155 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_11) begin
|
|
if (_T_10844) begin
|
|
bht_bank_rd_data_out_1_155 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_155 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_156 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_12) begin
|
|
if (_T_10853) begin
|
|
bht_bank_rd_data_out_1_156 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_156 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_157 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_13) begin
|
|
if (_T_10862) begin
|
|
bht_bank_rd_data_out_1_157 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_157 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_158 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_14) begin
|
|
if (_T_10871) begin
|
|
bht_bank_rd_data_out_1_158 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_158 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_159 <= 2'h0;
|
|
end else if (bht_bank_sel_1_9_15) begin
|
|
if (_T_10880) begin
|
|
bht_bank_rd_data_out_1_159 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_159 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_160 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_0) begin
|
|
if (_T_10889) begin
|
|
bht_bank_rd_data_out_1_160 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_160 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_161 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_1) begin
|
|
if (_T_10898) begin
|
|
bht_bank_rd_data_out_1_161 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_161 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_162 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_2) begin
|
|
if (_T_10907) begin
|
|
bht_bank_rd_data_out_1_162 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_162 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_163 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_3) begin
|
|
if (_T_10916) begin
|
|
bht_bank_rd_data_out_1_163 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_163 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_164 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_4) begin
|
|
if (_T_10925) begin
|
|
bht_bank_rd_data_out_1_164 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_164 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_165 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_5) begin
|
|
if (_T_10934) begin
|
|
bht_bank_rd_data_out_1_165 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_165 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_166 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_6) begin
|
|
if (_T_10943) begin
|
|
bht_bank_rd_data_out_1_166 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_166 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_167 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_7) begin
|
|
if (_T_10952) begin
|
|
bht_bank_rd_data_out_1_167 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_167 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_168 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_8) begin
|
|
if (_T_10961) begin
|
|
bht_bank_rd_data_out_1_168 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_168 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_169 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_9) begin
|
|
if (_T_10970) begin
|
|
bht_bank_rd_data_out_1_169 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_169 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_170 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_10) begin
|
|
if (_T_10979) begin
|
|
bht_bank_rd_data_out_1_170 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_170 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_171 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_11) begin
|
|
if (_T_10988) begin
|
|
bht_bank_rd_data_out_1_171 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_171 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_172 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_12) begin
|
|
if (_T_10997) begin
|
|
bht_bank_rd_data_out_1_172 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_172 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_173 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_13) begin
|
|
if (_T_11006) begin
|
|
bht_bank_rd_data_out_1_173 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_173 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_174 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_14) begin
|
|
if (_T_11015) begin
|
|
bht_bank_rd_data_out_1_174 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_174 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_175 <= 2'h0;
|
|
end else if (bht_bank_sel_1_10_15) begin
|
|
if (_T_11024) begin
|
|
bht_bank_rd_data_out_1_175 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_175 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_176 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_0) begin
|
|
if (_T_11033) begin
|
|
bht_bank_rd_data_out_1_176 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_176 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_177 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_1) begin
|
|
if (_T_11042) begin
|
|
bht_bank_rd_data_out_1_177 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_177 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_178 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_2) begin
|
|
if (_T_11051) begin
|
|
bht_bank_rd_data_out_1_178 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_178 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_179 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_3) begin
|
|
if (_T_11060) begin
|
|
bht_bank_rd_data_out_1_179 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_179 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_180 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_4) begin
|
|
if (_T_11069) begin
|
|
bht_bank_rd_data_out_1_180 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_180 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_181 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_5) begin
|
|
if (_T_11078) begin
|
|
bht_bank_rd_data_out_1_181 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_181 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_182 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_6) begin
|
|
if (_T_11087) begin
|
|
bht_bank_rd_data_out_1_182 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_182 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_183 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_7) begin
|
|
if (_T_11096) begin
|
|
bht_bank_rd_data_out_1_183 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_183 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_184 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_8) begin
|
|
if (_T_11105) begin
|
|
bht_bank_rd_data_out_1_184 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_184 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_185 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_9) begin
|
|
if (_T_11114) begin
|
|
bht_bank_rd_data_out_1_185 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_185 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_186 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_10) begin
|
|
if (_T_11123) begin
|
|
bht_bank_rd_data_out_1_186 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_186 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_187 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_11) begin
|
|
if (_T_11132) begin
|
|
bht_bank_rd_data_out_1_187 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_187 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_188 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_12) begin
|
|
if (_T_11141) begin
|
|
bht_bank_rd_data_out_1_188 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_188 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_189 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_13) begin
|
|
if (_T_11150) begin
|
|
bht_bank_rd_data_out_1_189 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_189 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_190 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_14) begin
|
|
if (_T_11159) begin
|
|
bht_bank_rd_data_out_1_190 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_190 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_191 <= 2'h0;
|
|
end else if (bht_bank_sel_1_11_15) begin
|
|
if (_T_11168) begin
|
|
bht_bank_rd_data_out_1_191 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_191 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_192 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_0) begin
|
|
if (_T_11177) begin
|
|
bht_bank_rd_data_out_1_192 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_192 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_193 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_1) begin
|
|
if (_T_11186) begin
|
|
bht_bank_rd_data_out_1_193 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_193 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_194 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_2) begin
|
|
if (_T_11195) begin
|
|
bht_bank_rd_data_out_1_194 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_194 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_195 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_3) begin
|
|
if (_T_11204) begin
|
|
bht_bank_rd_data_out_1_195 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_195 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_196 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_4) begin
|
|
if (_T_11213) begin
|
|
bht_bank_rd_data_out_1_196 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_196 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_197 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_5) begin
|
|
if (_T_11222) begin
|
|
bht_bank_rd_data_out_1_197 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_197 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_198 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_6) begin
|
|
if (_T_11231) begin
|
|
bht_bank_rd_data_out_1_198 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_198 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_199 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_7) begin
|
|
if (_T_11240) begin
|
|
bht_bank_rd_data_out_1_199 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_199 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_200 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_8) begin
|
|
if (_T_11249) begin
|
|
bht_bank_rd_data_out_1_200 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_200 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_201 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_9) begin
|
|
if (_T_11258) begin
|
|
bht_bank_rd_data_out_1_201 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_201 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_202 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_10) begin
|
|
if (_T_11267) begin
|
|
bht_bank_rd_data_out_1_202 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_202 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_203 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_11) begin
|
|
if (_T_11276) begin
|
|
bht_bank_rd_data_out_1_203 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_203 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_204 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_12) begin
|
|
if (_T_11285) begin
|
|
bht_bank_rd_data_out_1_204 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_204 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_205 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_13) begin
|
|
if (_T_11294) begin
|
|
bht_bank_rd_data_out_1_205 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_205 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_206 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_14) begin
|
|
if (_T_11303) begin
|
|
bht_bank_rd_data_out_1_206 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_206 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_207 <= 2'h0;
|
|
end else if (bht_bank_sel_1_12_15) begin
|
|
if (_T_11312) begin
|
|
bht_bank_rd_data_out_1_207 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_207 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_208 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_0) begin
|
|
if (_T_11321) begin
|
|
bht_bank_rd_data_out_1_208 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_208 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_209 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_1) begin
|
|
if (_T_11330) begin
|
|
bht_bank_rd_data_out_1_209 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_209 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_210 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_2) begin
|
|
if (_T_11339) begin
|
|
bht_bank_rd_data_out_1_210 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_210 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_211 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_3) begin
|
|
if (_T_11348) begin
|
|
bht_bank_rd_data_out_1_211 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_211 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_212 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_4) begin
|
|
if (_T_11357) begin
|
|
bht_bank_rd_data_out_1_212 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_212 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_213 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_5) begin
|
|
if (_T_11366) begin
|
|
bht_bank_rd_data_out_1_213 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_213 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_214 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_6) begin
|
|
if (_T_11375) begin
|
|
bht_bank_rd_data_out_1_214 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_214 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_215 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_7) begin
|
|
if (_T_11384) begin
|
|
bht_bank_rd_data_out_1_215 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_215 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_216 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_8) begin
|
|
if (_T_11393) begin
|
|
bht_bank_rd_data_out_1_216 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_216 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_217 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_9) begin
|
|
if (_T_11402) begin
|
|
bht_bank_rd_data_out_1_217 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_217 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_218 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_10) begin
|
|
if (_T_11411) begin
|
|
bht_bank_rd_data_out_1_218 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_218 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_219 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_11) begin
|
|
if (_T_11420) begin
|
|
bht_bank_rd_data_out_1_219 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_219 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_220 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_12) begin
|
|
if (_T_11429) begin
|
|
bht_bank_rd_data_out_1_220 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_220 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_221 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_13) begin
|
|
if (_T_11438) begin
|
|
bht_bank_rd_data_out_1_221 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_221 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_222 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_14) begin
|
|
if (_T_11447) begin
|
|
bht_bank_rd_data_out_1_222 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_222 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_223 <= 2'h0;
|
|
end else if (bht_bank_sel_1_13_15) begin
|
|
if (_T_11456) begin
|
|
bht_bank_rd_data_out_1_223 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_223 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_224 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_0) begin
|
|
if (_T_11465) begin
|
|
bht_bank_rd_data_out_1_224 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_224 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_225 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_1) begin
|
|
if (_T_11474) begin
|
|
bht_bank_rd_data_out_1_225 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_225 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_226 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_2) begin
|
|
if (_T_11483) begin
|
|
bht_bank_rd_data_out_1_226 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_226 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_227 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_3) begin
|
|
if (_T_11492) begin
|
|
bht_bank_rd_data_out_1_227 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_227 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_228 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_4) begin
|
|
if (_T_11501) begin
|
|
bht_bank_rd_data_out_1_228 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_228 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_229 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_5) begin
|
|
if (_T_11510) begin
|
|
bht_bank_rd_data_out_1_229 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_229 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_230 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_6) begin
|
|
if (_T_11519) begin
|
|
bht_bank_rd_data_out_1_230 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_230 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_231 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_7) begin
|
|
if (_T_11528) begin
|
|
bht_bank_rd_data_out_1_231 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_231 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_232 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_8) begin
|
|
if (_T_11537) begin
|
|
bht_bank_rd_data_out_1_232 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_232 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_233 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_9) begin
|
|
if (_T_11546) begin
|
|
bht_bank_rd_data_out_1_233 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_233 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_234 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_10) begin
|
|
if (_T_11555) begin
|
|
bht_bank_rd_data_out_1_234 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_234 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_235 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_11) begin
|
|
if (_T_11564) begin
|
|
bht_bank_rd_data_out_1_235 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_235 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_236 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_12) begin
|
|
if (_T_11573) begin
|
|
bht_bank_rd_data_out_1_236 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_236 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_237 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_13) begin
|
|
if (_T_11582) begin
|
|
bht_bank_rd_data_out_1_237 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_237 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_238 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_14) begin
|
|
if (_T_11591) begin
|
|
bht_bank_rd_data_out_1_238 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_238 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_239 <= 2'h0;
|
|
end else if (bht_bank_sel_1_14_15) begin
|
|
if (_T_11600) begin
|
|
bht_bank_rd_data_out_1_239 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_239 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_240 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_0) begin
|
|
if (_T_11609) begin
|
|
bht_bank_rd_data_out_1_240 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_240 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_241 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_1) begin
|
|
if (_T_11618) begin
|
|
bht_bank_rd_data_out_1_241 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_241 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_242 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_2) begin
|
|
if (_T_11627) begin
|
|
bht_bank_rd_data_out_1_242 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_242 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_243 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_3) begin
|
|
if (_T_11636) begin
|
|
bht_bank_rd_data_out_1_243 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_243 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_244 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_4) begin
|
|
if (_T_11645) begin
|
|
bht_bank_rd_data_out_1_244 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_244 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_245 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_5) begin
|
|
if (_T_11654) begin
|
|
bht_bank_rd_data_out_1_245 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_245 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_246 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_6) begin
|
|
if (_T_11663) begin
|
|
bht_bank_rd_data_out_1_246 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_246 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_247 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_7) begin
|
|
if (_T_11672) begin
|
|
bht_bank_rd_data_out_1_247 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_247 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_248 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_8) begin
|
|
if (_T_11681) begin
|
|
bht_bank_rd_data_out_1_248 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_248 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_249 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_9) begin
|
|
if (_T_11690) begin
|
|
bht_bank_rd_data_out_1_249 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_249 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_250 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_10) begin
|
|
if (_T_11699) begin
|
|
bht_bank_rd_data_out_1_250 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_250 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_251 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_11) begin
|
|
if (_T_11708) begin
|
|
bht_bank_rd_data_out_1_251 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_251 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_252 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_12) begin
|
|
if (_T_11717) begin
|
|
bht_bank_rd_data_out_1_252 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_252 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_253 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_13) begin
|
|
if (_T_11726) begin
|
|
bht_bank_rd_data_out_1_253 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_253 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_254 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_14) begin
|
|
if (_T_11735) begin
|
|
bht_bank_rd_data_out_1_254 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_254 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_1_255 <= 2'h0;
|
|
end else if (bht_bank_sel_1_15_15) begin
|
|
if (_T_11744) begin
|
|
bht_bank_rd_data_out_1_255 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_1_255 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_0 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_0) begin
|
|
if (_T_7145) begin
|
|
bht_bank_rd_data_out_0_0 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_0 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_1 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_1) begin
|
|
if (_T_7154) begin
|
|
bht_bank_rd_data_out_0_1 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_1 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_2 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_2) begin
|
|
if (_T_7163) begin
|
|
bht_bank_rd_data_out_0_2 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_2 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_3 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_3) begin
|
|
if (_T_7172) begin
|
|
bht_bank_rd_data_out_0_3 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_3 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_4 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_4) begin
|
|
if (_T_7181) begin
|
|
bht_bank_rd_data_out_0_4 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_4 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_5 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_5) begin
|
|
if (_T_7190) begin
|
|
bht_bank_rd_data_out_0_5 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_5 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_6 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_6) begin
|
|
if (_T_7199) begin
|
|
bht_bank_rd_data_out_0_6 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_6 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_7 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_7) begin
|
|
if (_T_7208) begin
|
|
bht_bank_rd_data_out_0_7 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_7 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_8 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_8) begin
|
|
if (_T_7217) begin
|
|
bht_bank_rd_data_out_0_8 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_8 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_9 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_9) begin
|
|
if (_T_7226) begin
|
|
bht_bank_rd_data_out_0_9 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_9 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_10 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_10) begin
|
|
if (_T_7235) begin
|
|
bht_bank_rd_data_out_0_10 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_10 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_11 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_11) begin
|
|
if (_T_7244) begin
|
|
bht_bank_rd_data_out_0_11 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_11 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_12 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_12) begin
|
|
if (_T_7253) begin
|
|
bht_bank_rd_data_out_0_12 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_12 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_13 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_13) begin
|
|
if (_T_7262) begin
|
|
bht_bank_rd_data_out_0_13 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_13 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_14 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_14) begin
|
|
if (_T_7271) begin
|
|
bht_bank_rd_data_out_0_14 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_14 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_15 <= 2'h0;
|
|
end else if (bht_bank_sel_0_0_15) begin
|
|
if (_T_7280) begin
|
|
bht_bank_rd_data_out_0_15 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_15 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_16 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_0) begin
|
|
if (_T_7289) begin
|
|
bht_bank_rd_data_out_0_16 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_16 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_17 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_1) begin
|
|
if (_T_7298) begin
|
|
bht_bank_rd_data_out_0_17 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_17 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_18 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_2) begin
|
|
if (_T_7307) begin
|
|
bht_bank_rd_data_out_0_18 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_18 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_19 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_3) begin
|
|
if (_T_7316) begin
|
|
bht_bank_rd_data_out_0_19 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_19 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_20 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_4) begin
|
|
if (_T_7325) begin
|
|
bht_bank_rd_data_out_0_20 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_20 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_21 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_5) begin
|
|
if (_T_7334) begin
|
|
bht_bank_rd_data_out_0_21 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_21 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_22 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_6) begin
|
|
if (_T_7343) begin
|
|
bht_bank_rd_data_out_0_22 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_22 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_23 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_7) begin
|
|
if (_T_7352) begin
|
|
bht_bank_rd_data_out_0_23 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_23 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_24 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_8) begin
|
|
if (_T_7361) begin
|
|
bht_bank_rd_data_out_0_24 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_24 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_25 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_9) begin
|
|
if (_T_7370) begin
|
|
bht_bank_rd_data_out_0_25 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_25 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_26 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_10) begin
|
|
if (_T_7379) begin
|
|
bht_bank_rd_data_out_0_26 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_26 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_27 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_11) begin
|
|
if (_T_7388) begin
|
|
bht_bank_rd_data_out_0_27 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_27 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_28 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_12) begin
|
|
if (_T_7397) begin
|
|
bht_bank_rd_data_out_0_28 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_28 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_29 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_13) begin
|
|
if (_T_7406) begin
|
|
bht_bank_rd_data_out_0_29 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_29 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_30 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_14) begin
|
|
if (_T_7415) begin
|
|
bht_bank_rd_data_out_0_30 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_30 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_31 <= 2'h0;
|
|
end else if (bht_bank_sel_0_1_15) begin
|
|
if (_T_7424) begin
|
|
bht_bank_rd_data_out_0_31 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_31 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_32 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_0) begin
|
|
if (_T_7433) begin
|
|
bht_bank_rd_data_out_0_32 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_32 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_33 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_1) begin
|
|
if (_T_7442) begin
|
|
bht_bank_rd_data_out_0_33 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_33 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_34 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_2) begin
|
|
if (_T_7451) begin
|
|
bht_bank_rd_data_out_0_34 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_34 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_35 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_3) begin
|
|
if (_T_7460) begin
|
|
bht_bank_rd_data_out_0_35 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_35 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_36 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_4) begin
|
|
if (_T_7469) begin
|
|
bht_bank_rd_data_out_0_36 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_36 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_37 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_5) begin
|
|
if (_T_7478) begin
|
|
bht_bank_rd_data_out_0_37 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_37 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_38 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_6) begin
|
|
if (_T_7487) begin
|
|
bht_bank_rd_data_out_0_38 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_38 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_39 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_7) begin
|
|
if (_T_7496) begin
|
|
bht_bank_rd_data_out_0_39 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_39 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_40 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_8) begin
|
|
if (_T_7505) begin
|
|
bht_bank_rd_data_out_0_40 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_40 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_41 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_9) begin
|
|
if (_T_7514) begin
|
|
bht_bank_rd_data_out_0_41 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_41 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_42 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_10) begin
|
|
if (_T_7523) begin
|
|
bht_bank_rd_data_out_0_42 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_42 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_43 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_11) begin
|
|
if (_T_7532) begin
|
|
bht_bank_rd_data_out_0_43 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_43 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_44 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_12) begin
|
|
if (_T_7541) begin
|
|
bht_bank_rd_data_out_0_44 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_44 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_45 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_13) begin
|
|
if (_T_7550) begin
|
|
bht_bank_rd_data_out_0_45 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_45 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_46 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_14) begin
|
|
if (_T_7559) begin
|
|
bht_bank_rd_data_out_0_46 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_46 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_47 <= 2'h0;
|
|
end else if (bht_bank_sel_0_2_15) begin
|
|
if (_T_7568) begin
|
|
bht_bank_rd_data_out_0_47 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_47 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_48 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_0) begin
|
|
if (_T_7577) begin
|
|
bht_bank_rd_data_out_0_48 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_48 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_49 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_1) begin
|
|
if (_T_7586) begin
|
|
bht_bank_rd_data_out_0_49 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_49 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_50 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_2) begin
|
|
if (_T_7595) begin
|
|
bht_bank_rd_data_out_0_50 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_50 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_51 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_3) begin
|
|
if (_T_7604) begin
|
|
bht_bank_rd_data_out_0_51 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_51 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_52 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_4) begin
|
|
if (_T_7613) begin
|
|
bht_bank_rd_data_out_0_52 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_52 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_53 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_5) begin
|
|
if (_T_7622) begin
|
|
bht_bank_rd_data_out_0_53 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_53 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_54 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_6) begin
|
|
if (_T_7631) begin
|
|
bht_bank_rd_data_out_0_54 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_54 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_55 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_7) begin
|
|
if (_T_7640) begin
|
|
bht_bank_rd_data_out_0_55 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_55 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_56 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_8) begin
|
|
if (_T_7649) begin
|
|
bht_bank_rd_data_out_0_56 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_56 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_57 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_9) begin
|
|
if (_T_7658) begin
|
|
bht_bank_rd_data_out_0_57 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_57 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_58 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_10) begin
|
|
if (_T_7667) begin
|
|
bht_bank_rd_data_out_0_58 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_58 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_59 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_11) begin
|
|
if (_T_7676) begin
|
|
bht_bank_rd_data_out_0_59 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_59 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_60 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_12) begin
|
|
if (_T_7685) begin
|
|
bht_bank_rd_data_out_0_60 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_60 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_61 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_13) begin
|
|
if (_T_7694) begin
|
|
bht_bank_rd_data_out_0_61 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_61 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_62 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_14) begin
|
|
if (_T_7703) begin
|
|
bht_bank_rd_data_out_0_62 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_62 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_63 <= 2'h0;
|
|
end else if (bht_bank_sel_0_3_15) begin
|
|
if (_T_7712) begin
|
|
bht_bank_rd_data_out_0_63 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_63 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_64 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_0) begin
|
|
if (_T_7721) begin
|
|
bht_bank_rd_data_out_0_64 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_64 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_65 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_1) begin
|
|
if (_T_7730) begin
|
|
bht_bank_rd_data_out_0_65 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_65 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_66 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_2) begin
|
|
if (_T_7739) begin
|
|
bht_bank_rd_data_out_0_66 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_66 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_67 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_3) begin
|
|
if (_T_7748) begin
|
|
bht_bank_rd_data_out_0_67 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_67 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_68 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_4) begin
|
|
if (_T_7757) begin
|
|
bht_bank_rd_data_out_0_68 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_68 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_69 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_5) begin
|
|
if (_T_7766) begin
|
|
bht_bank_rd_data_out_0_69 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_69 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_70 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_6) begin
|
|
if (_T_7775) begin
|
|
bht_bank_rd_data_out_0_70 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_70 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_71 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_7) begin
|
|
if (_T_7784) begin
|
|
bht_bank_rd_data_out_0_71 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_71 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_72 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_8) begin
|
|
if (_T_7793) begin
|
|
bht_bank_rd_data_out_0_72 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_72 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_73 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_9) begin
|
|
if (_T_7802) begin
|
|
bht_bank_rd_data_out_0_73 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_73 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_74 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_10) begin
|
|
if (_T_7811) begin
|
|
bht_bank_rd_data_out_0_74 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_74 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_75 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_11) begin
|
|
if (_T_7820) begin
|
|
bht_bank_rd_data_out_0_75 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_75 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_76 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_12) begin
|
|
if (_T_7829) begin
|
|
bht_bank_rd_data_out_0_76 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_76 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_77 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_13) begin
|
|
if (_T_7838) begin
|
|
bht_bank_rd_data_out_0_77 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_77 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_78 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_14) begin
|
|
if (_T_7847) begin
|
|
bht_bank_rd_data_out_0_78 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_78 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_79 <= 2'h0;
|
|
end else if (bht_bank_sel_0_4_15) begin
|
|
if (_T_7856) begin
|
|
bht_bank_rd_data_out_0_79 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_79 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_80 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_0) begin
|
|
if (_T_7865) begin
|
|
bht_bank_rd_data_out_0_80 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_80 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_81 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_1) begin
|
|
if (_T_7874) begin
|
|
bht_bank_rd_data_out_0_81 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_81 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_82 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_2) begin
|
|
if (_T_7883) begin
|
|
bht_bank_rd_data_out_0_82 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_82 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_83 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_3) begin
|
|
if (_T_7892) begin
|
|
bht_bank_rd_data_out_0_83 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_83 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_84 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_4) begin
|
|
if (_T_7901) begin
|
|
bht_bank_rd_data_out_0_84 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_84 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_85 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_5) begin
|
|
if (_T_7910) begin
|
|
bht_bank_rd_data_out_0_85 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_85 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_86 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_6) begin
|
|
if (_T_7919) begin
|
|
bht_bank_rd_data_out_0_86 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_86 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_87 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_7) begin
|
|
if (_T_7928) begin
|
|
bht_bank_rd_data_out_0_87 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_87 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_88 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_8) begin
|
|
if (_T_7937) begin
|
|
bht_bank_rd_data_out_0_88 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_88 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_89 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_9) begin
|
|
if (_T_7946) begin
|
|
bht_bank_rd_data_out_0_89 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_89 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_90 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_10) begin
|
|
if (_T_7955) begin
|
|
bht_bank_rd_data_out_0_90 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_90 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_91 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_11) begin
|
|
if (_T_7964) begin
|
|
bht_bank_rd_data_out_0_91 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_91 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_92 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_12) begin
|
|
if (_T_7973) begin
|
|
bht_bank_rd_data_out_0_92 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_92 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_93 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_13) begin
|
|
if (_T_7982) begin
|
|
bht_bank_rd_data_out_0_93 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_93 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_94 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_14) begin
|
|
if (_T_7991) begin
|
|
bht_bank_rd_data_out_0_94 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_94 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_95 <= 2'h0;
|
|
end else if (bht_bank_sel_0_5_15) begin
|
|
if (_T_8000) begin
|
|
bht_bank_rd_data_out_0_95 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_95 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_96 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_0) begin
|
|
if (_T_8009) begin
|
|
bht_bank_rd_data_out_0_96 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_96 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_97 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_1) begin
|
|
if (_T_8018) begin
|
|
bht_bank_rd_data_out_0_97 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_97 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_98 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_2) begin
|
|
if (_T_8027) begin
|
|
bht_bank_rd_data_out_0_98 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_98 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_99 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_3) begin
|
|
if (_T_8036) begin
|
|
bht_bank_rd_data_out_0_99 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_99 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_100 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_4) begin
|
|
if (_T_8045) begin
|
|
bht_bank_rd_data_out_0_100 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_100 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_101 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_5) begin
|
|
if (_T_8054) begin
|
|
bht_bank_rd_data_out_0_101 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_101 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_102 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_6) begin
|
|
if (_T_8063) begin
|
|
bht_bank_rd_data_out_0_102 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_102 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_103 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_7) begin
|
|
if (_T_8072) begin
|
|
bht_bank_rd_data_out_0_103 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_103 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_104 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_8) begin
|
|
if (_T_8081) begin
|
|
bht_bank_rd_data_out_0_104 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_104 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_105 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_9) begin
|
|
if (_T_8090) begin
|
|
bht_bank_rd_data_out_0_105 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_105 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_106 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_10) begin
|
|
if (_T_8099) begin
|
|
bht_bank_rd_data_out_0_106 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_106 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_107 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_11) begin
|
|
if (_T_8108) begin
|
|
bht_bank_rd_data_out_0_107 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_107 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_108 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_12) begin
|
|
if (_T_8117) begin
|
|
bht_bank_rd_data_out_0_108 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_108 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_109 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_13) begin
|
|
if (_T_8126) begin
|
|
bht_bank_rd_data_out_0_109 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_109 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_110 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_14) begin
|
|
if (_T_8135) begin
|
|
bht_bank_rd_data_out_0_110 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_110 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_111 <= 2'h0;
|
|
end else if (bht_bank_sel_0_6_15) begin
|
|
if (_T_8144) begin
|
|
bht_bank_rd_data_out_0_111 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_111 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_112 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_0) begin
|
|
if (_T_8153) begin
|
|
bht_bank_rd_data_out_0_112 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_112 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_113 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_1) begin
|
|
if (_T_8162) begin
|
|
bht_bank_rd_data_out_0_113 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_113 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_114 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_2) begin
|
|
if (_T_8171) begin
|
|
bht_bank_rd_data_out_0_114 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_114 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_115 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_3) begin
|
|
if (_T_8180) begin
|
|
bht_bank_rd_data_out_0_115 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_115 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_116 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_4) begin
|
|
if (_T_8189) begin
|
|
bht_bank_rd_data_out_0_116 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_116 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_117 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_5) begin
|
|
if (_T_8198) begin
|
|
bht_bank_rd_data_out_0_117 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_117 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_118 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_6) begin
|
|
if (_T_8207) begin
|
|
bht_bank_rd_data_out_0_118 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_118 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_119 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_7) begin
|
|
if (_T_8216) begin
|
|
bht_bank_rd_data_out_0_119 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_119 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_120 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_8) begin
|
|
if (_T_8225) begin
|
|
bht_bank_rd_data_out_0_120 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_120 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_121 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_9) begin
|
|
if (_T_8234) begin
|
|
bht_bank_rd_data_out_0_121 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_121 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_122 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_10) begin
|
|
if (_T_8243) begin
|
|
bht_bank_rd_data_out_0_122 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_122 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_123 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_11) begin
|
|
if (_T_8252) begin
|
|
bht_bank_rd_data_out_0_123 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_123 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_124 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_12) begin
|
|
if (_T_8261) begin
|
|
bht_bank_rd_data_out_0_124 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_124 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_125 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_13) begin
|
|
if (_T_8270) begin
|
|
bht_bank_rd_data_out_0_125 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_125 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_126 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_14) begin
|
|
if (_T_8279) begin
|
|
bht_bank_rd_data_out_0_126 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_126 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_127 <= 2'h0;
|
|
end else if (bht_bank_sel_0_7_15) begin
|
|
if (_T_8288) begin
|
|
bht_bank_rd_data_out_0_127 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_127 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_128 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_0) begin
|
|
if (_T_8297) begin
|
|
bht_bank_rd_data_out_0_128 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_128 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_129 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_1) begin
|
|
if (_T_8306) begin
|
|
bht_bank_rd_data_out_0_129 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_129 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_130 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_2) begin
|
|
if (_T_8315) begin
|
|
bht_bank_rd_data_out_0_130 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_130 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_131 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_3) begin
|
|
if (_T_8324) begin
|
|
bht_bank_rd_data_out_0_131 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_131 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_132 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_4) begin
|
|
if (_T_8333) begin
|
|
bht_bank_rd_data_out_0_132 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_132 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_133 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_5) begin
|
|
if (_T_8342) begin
|
|
bht_bank_rd_data_out_0_133 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_133 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_134 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_6) begin
|
|
if (_T_8351) begin
|
|
bht_bank_rd_data_out_0_134 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_134 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_135 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_7) begin
|
|
if (_T_8360) begin
|
|
bht_bank_rd_data_out_0_135 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_135 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_136 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_8) begin
|
|
if (_T_8369) begin
|
|
bht_bank_rd_data_out_0_136 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_136 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_137 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_9) begin
|
|
if (_T_8378) begin
|
|
bht_bank_rd_data_out_0_137 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_137 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_138 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_10) begin
|
|
if (_T_8387) begin
|
|
bht_bank_rd_data_out_0_138 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_138 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_139 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_11) begin
|
|
if (_T_8396) begin
|
|
bht_bank_rd_data_out_0_139 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_139 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_140 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_12) begin
|
|
if (_T_8405) begin
|
|
bht_bank_rd_data_out_0_140 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_140 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_141 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_13) begin
|
|
if (_T_8414) begin
|
|
bht_bank_rd_data_out_0_141 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_141 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_142 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_14) begin
|
|
if (_T_8423) begin
|
|
bht_bank_rd_data_out_0_142 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_142 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_143 <= 2'h0;
|
|
end else if (bht_bank_sel_0_8_15) begin
|
|
if (_T_8432) begin
|
|
bht_bank_rd_data_out_0_143 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_143 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_144 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_0) begin
|
|
if (_T_8441) begin
|
|
bht_bank_rd_data_out_0_144 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_144 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_145 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_1) begin
|
|
if (_T_8450) begin
|
|
bht_bank_rd_data_out_0_145 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_145 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_146 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_2) begin
|
|
if (_T_8459) begin
|
|
bht_bank_rd_data_out_0_146 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_146 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_147 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_3) begin
|
|
if (_T_8468) begin
|
|
bht_bank_rd_data_out_0_147 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_147 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_148 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_4) begin
|
|
if (_T_8477) begin
|
|
bht_bank_rd_data_out_0_148 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_148 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_149 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_5) begin
|
|
if (_T_8486) begin
|
|
bht_bank_rd_data_out_0_149 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_149 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_150 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_6) begin
|
|
if (_T_8495) begin
|
|
bht_bank_rd_data_out_0_150 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_150 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_151 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_7) begin
|
|
if (_T_8504) begin
|
|
bht_bank_rd_data_out_0_151 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_151 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_152 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_8) begin
|
|
if (_T_8513) begin
|
|
bht_bank_rd_data_out_0_152 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_152 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_153 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_9) begin
|
|
if (_T_8522) begin
|
|
bht_bank_rd_data_out_0_153 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_153 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_154 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_10) begin
|
|
if (_T_8531) begin
|
|
bht_bank_rd_data_out_0_154 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_154 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_155 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_11) begin
|
|
if (_T_8540) begin
|
|
bht_bank_rd_data_out_0_155 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_155 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_156 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_12) begin
|
|
if (_T_8549) begin
|
|
bht_bank_rd_data_out_0_156 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_156 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_157 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_13) begin
|
|
if (_T_8558) begin
|
|
bht_bank_rd_data_out_0_157 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_157 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_158 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_14) begin
|
|
if (_T_8567) begin
|
|
bht_bank_rd_data_out_0_158 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_158 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_159 <= 2'h0;
|
|
end else if (bht_bank_sel_0_9_15) begin
|
|
if (_T_8576) begin
|
|
bht_bank_rd_data_out_0_159 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_159 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_160 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_0) begin
|
|
if (_T_8585) begin
|
|
bht_bank_rd_data_out_0_160 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_160 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_161 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_1) begin
|
|
if (_T_8594) begin
|
|
bht_bank_rd_data_out_0_161 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_161 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_162 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_2) begin
|
|
if (_T_8603) begin
|
|
bht_bank_rd_data_out_0_162 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_162 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_163 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_3) begin
|
|
if (_T_8612) begin
|
|
bht_bank_rd_data_out_0_163 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_163 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_164 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_4) begin
|
|
if (_T_8621) begin
|
|
bht_bank_rd_data_out_0_164 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_164 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_165 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_5) begin
|
|
if (_T_8630) begin
|
|
bht_bank_rd_data_out_0_165 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_165 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_166 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_6) begin
|
|
if (_T_8639) begin
|
|
bht_bank_rd_data_out_0_166 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_166 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_167 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_7) begin
|
|
if (_T_8648) begin
|
|
bht_bank_rd_data_out_0_167 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_167 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_168 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_8) begin
|
|
if (_T_8657) begin
|
|
bht_bank_rd_data_out_0_168 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_168 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_169 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_9) begin
|
|
if (_T_8666) begin
|
|
bht_bank_rd_data_out_0_169 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_169 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_170 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_10) begin
|
|
if (_T_8675) begin
|
|
bht_bank_rd_data_out_0_170 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_170 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_171 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_11) begin
|
|
if (_T_8684) begin
|
|
bht_bank_rd_data_out_0_171 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_171 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_172 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_12) begin
|
|
if (_T_8693) begin
|
|
bht_bank_rd_data_out_0_172 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_172 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_173 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_13) begin
|
|
if (_T_8702) begin
|
|
bht_bank_rd_data_out_0_173 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_173 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_174 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_14) begin
|
|
if (_T_8711) begin
|
|
bht_bank_rd_data_out_0_174 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_174 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_175 <= 2'h0;
|
|
end else if (bht_bank_sel_0_10_15) begin
|
|
if (_T_8720) begin
|
|
bht_bank_rd_data_out_0_175 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_175 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_176 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_0) begin
|
|
if (_T_8729) begin
|
|
bht_bank_rd_data_out_0_176 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_176 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_177 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_1) begin
|
|
if (_T_8738) begin
|
|
bht_bank_rd_data_out_0_177 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_177 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_178 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_2) begin
|
|
if (_T_8747) begin
|
|
bht_bank_rd_data_out_0_178 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_178 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_179 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_3) begin
|
|
if (_T_8756) begin
|
|
bht_bank_rd_data_out_0_179 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_179 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_180 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_4) begin
|
|
if (_T_8765) begin
|
|
bht_bank_rd_data_out_0_180 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_180 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_181 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_5) begin
|
|
if (_T_8774) begin
|
|
bht_bank_rd_data_out_0_181 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_181 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_182 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_6) begin
|
|
if (_T_8783) begin
|
|
bht_bank_rd_data_out_0_182 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_182 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_183 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_7) begin
|
|
if (_T_8792) begin
|
|
bht_bank_rd_data_out_0_183 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_183 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_184 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_8) begin
|
|
if (_T_8801) begin
|
|
bht_bank_rd_data_out_0_184 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_184 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_185 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_9) begin
|
|
if (_T_8810) begin
|
|
bht_bank_rd_data_out_0_185 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_185 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_186 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_10) begin
|
|
if (_T_8819) begin
|
|
bht_bank_rd_data_out_0_186 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_186 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_187 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_11) begin
|
|
if (_T_8828) begin
|
|
bht_bank_rd_data_out_0_187 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_187 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_188 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_12) begin
|
|
if (_T_8837) begin
|
|
bht_bank_rd_data_out_0_188 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_188 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_189 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_13) begin
|
|
if (_T_8846) begin
|
|
bht_bank_rd_data_out_0_189 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_189 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_190 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_14) begin
|
|
if (_T_8855) begin
|
|
bht_bank_rd_data_out_0_190 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_190 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_191 <= 2'h0;
|
|
end else if (bht_bank_sel_0_11_15) begin
|
|
if (_T_8864) begin
|
|
bht_bank_rd_data_out_0_191 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_191 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_192 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_0) begin
|
|
if (_T_8873) begin
|
|
bht_bank_rd_data_out_0_192 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_192 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_193 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_1) begin
|
|
if (_T_8882) begin
|
|
bht_bank_rd_data_out_0_193 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_193 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_194 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_2) begin
|
|
if (_T_8891) begin
|
|
bht_bank_rd_data_out_0_194 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_194 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_195 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_3) begin
|
|
if (_T_8900) begin
|
|
bht_bank_rd_data_out_0_195 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_195 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_196 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_4) begin
|
|
if (_T_8909) begin
|
|
bht_bank_rd_data_out_0_196 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_196 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_197 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_5) begin
|
|
if (_T_8918) begin
|
|
bht_bank_rd_data_out_0_197 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_197 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_198 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_6) begin
|
|
if (_T_8927) begin
|
|
bht_bank_rd_data_out_0_198 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_198 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_199 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_7) begin
|
|
if (_T_8936) begin
|
|
bht_bank_rd_data_out_0_199 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_199 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_200 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_8) begin
|
|
if (_T_8945) begin
|
|
bht_bank_rd_data_out_0_200 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_200 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_201 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_9) begin
|
|
if (_T_8954) begin
|
|
bht_bank_rd_data_out_0_201 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_201 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_202 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_10) begin
|
|
if (_T_8963) begin
|
|
bht_bank_rd_data_out_0_202 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_202 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_203 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_11) begin
|
|
if (_T_8972) begin
|
|
bht_bank_rd_data_out_0_203 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_203 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_204 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_12) begin
|
|
if (_T_8981) begin
|
|
bht_bank_rd_data_out_0_204 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_204 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_205 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_13) begin
|
|
if (_T_8990) begin
|
|
bht_bank_rd_data_out_0_205 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_205 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_206 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_14) begin
|
|
if (_T_8999) begin
|
|
bht_bank_rd_data_out_0_206 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_206 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_207 <= 2'h0;
|
|
end else if (bht_bank_sel_0_12_15) begin
|
|
if (_T_9008) begin
|
|
bht_bank_rd_data_out_0_207 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_207 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_208 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_0) begin
|
|
if (_T_9017) begin
|
|
bht_bank_rd_data_out_0_208 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_208 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_209 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_1) begin
|
|
if (_T_9026) begin
|
|
bht_bank_rd_data_out_0_209 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_209 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_210 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_2) begin
|
|
if (_T_9035) begin
|
|
bht_bank_rd_data_out_0_210 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_210 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_211 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_3) begin
|
|
if (_T_9044) begin
|
|
bht_bank_rd_data_out_0_211 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_211 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_212 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_4) begin
|
|
if (_T_9053) begin
|
|
bht_bank_rd_data_out_0_212 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_212 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_213 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_5) begin
|
|
if (_T_9062) begin
|
|
bht_bank_rd_data_out_0_213 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_213 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_214 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_6) begin
|
|
if (_T_9071) begin
|
|
bht_bank_rd_data_out_0_214 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_214 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_215 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_7) begin
|
|
if (_T_9080) begin
|
|
bht_bank_rd_data_out_0_215 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_215 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_216 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_8) begin
|
|
if (_T_9089) begin
|
|
bht_bank_rd_data_out_0_216 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_216 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_217 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_9) begin
|
|
if (_T_9098) begin
|
|
bht_bank_rd_data_out_0_217 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_217 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_218 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_10) begin
|
|
if (_T_9107) begin
|
|
bht_bank_rd_data_out_0_218 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_218 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_219 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_11) begin
|
|
if (_T_9116) begin
|
|
bht_bank_rd_data_out_0_219 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_219 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_220 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_12) begin
|
|
if (_T_9125) begin
|
|
bht_bank_rd_data_out_0_220 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_220 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_221 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_13) begin
|
|
if (_T_9134) begin
|
|
bht_bank_rd_data_out_0_221 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_221 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_222 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_14) begin
|
|
if (_T_9143) begin
|
|
bht_bank_rd_data_out_0_222 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_222 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_223 <= 2'h0;
|
|
end else if (bht_bank_sel_0_13_15) begin
|
|
if (_T_9152) begin
|
|
bht_bank_rd_data_out_0_223 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_223 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_224 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_0) begin
|
|
if (_T_9161) begin
|
|
bht_bank_rd_data_out_0_224 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_224 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_225 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_1) begin
|
|
if (_T_9170) begin
|
|
bht_bank_rd_data_out_0_225 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_225 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_226 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_2) begin
|
|
if (_T_9179) begin
|
|
bht_bank_rd_data_out_0_226 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_226 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_227 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_3) begin
|
|
if (_T_9188) begin
|
|
bht_bank_rd_data_out_0_227 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_227 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_228 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_4) begin
|
|
if (_T_9197) begin
|
|
bht_bank_rd_data_out_0_228 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_228 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_229 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_5) begin
|
|
if (_T_9206) begin
|
|
bht_bank_rd_data_out_0_229 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_229 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_230 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_6) begin
|
|
if (_T_9215) begin
|
|
bht_bank_rd_data_out_0_230 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_230 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_231 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_7) begin
|
|
if (_T_9224) begin
|
|
bht_bank_rd_data_out_0_231 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_231 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_232 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_8) begin
|
|
if (_T_9233) begin
|
|
bht_bank_rd_data_out_0_232 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_232 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_233 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_9) begin
|
|
if (_T_9242) begin
|
|
bht_bank_rd_data_out_0_233 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_233 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_234 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_10) begin
|
|
if (_T_9251) begin
|
|
bht_bank_rd_data_out_0_234 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_234 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_235 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_11) begin
|
|
if (_T_9260) begin
|
|
bht_bank_rd_data_out_0_235 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_235 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_236 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_12) begin
|
|
if (_T_9269) begin
|
|
bht_bank_rd_data_out_0_236 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_236 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_237 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_13) begin
|
|
if (_T_9278) begin
|
|
bht_bank_rd_data_out_0_237 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_237 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_238 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_14) begin
|
|
if (_T_9287) begin
|
|
bht_bank_rd_data_out_0_238 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_238 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_239 <= 2'h0;
|
|
end else if (bht_bank_sel_0_14_15) begin
|
|
if (_T_9296) begin
|
|
bht_bank_rd_data_out_0_239 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_239 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_240 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_0) begin
|
|
if (_T_9305) begin
|
|
bht_bank_rd_data_out_0_240 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_240 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_241 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_1) begin
|
|
if (_T_9314) begin
|
|
bht_bank_rd_data_out_0_241 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_241 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_242 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_2) begin
|
|
if (_T_9323) begin
|
|
bht_bank_rd_data_out_0_242 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_242 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_243 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_3) begin
|
|
if (_T_9332) begin
|
|
bht_bank_rd_data_out_0_243 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_243 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_244 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_4) begin
|
|
if (_T_9341) begin
|
|
bht_bank_rd_data_out_0_244 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_244 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_245 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_5) begin
|
|
if (_T_9350) begin
|
|
bht_bank_rd_data_out_0_245 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_245 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_246 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_6) begin
|
|
if (_T_9359) begin
|
|
bht_bank_rd_data_out_0_246 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_246 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_247 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_7) begin
|
|
if (_T_9368) begin
|
|
bht_bank_rd_data_out_0_247 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_247 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_248 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_8) begin
|
|
if (_T_9377) begin
|
|
bht_bank_rd_data_out_0_248 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_248 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_249 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_9) begin
|
|
if (_T_9386) begin
|
|
bht_bank_rd_data_out_0_249 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_249 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_250 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_10) begin
|
|
if (_T_9395) begin
|
|
bht_bank_rd_data_out_0_250 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_250 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_251 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_11) begin
|
|
if (_T_9404) begin
|
|
bht_bank_rd_data_out_0_251 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_251 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_252 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_12) begin
|
|
if (_T_9413) begin
|
|
bht_bank_rd_data_out_0_252 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_252 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_253 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_13) begin
|
|
if (_T_9422) begin
|
|
bht_bank_rd_data_out_0_253 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_253 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_254 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_14) begin
|
|
if (_T_9431) begin
|
|
bht_bank_rd_data_out_0_254 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_254 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bht_bank_rd_data_out_0_255 <= 2'h0;
|
|
end else if (bht_bank_sel_0_15_15) begin
|
|
if (_T_9440) begin
|
|
bht_bank_rd_data_out_0_255 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist;
|
|
end else begin
|
|
bht_bank_rd_data_out_0_255 <= io_exu_bp_exu_mp_pkt_bits_hist;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
exu_mp_way_f <= 1'h0;
|
|
end else if (_T_367) begin
|
|
exu_mp_way_f <= io_exu_bp_exu_mp_pkt_bits_way;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
btb_lru_b0_f <= 256'h0;
|
|
end else if (_T_234) begin
|
|
btb_lru_b0_f <= _T_203;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
exu_flush_final_d1 <= 1'h0;
|
|
end else if (_T_371) begin
|
|
exu_flush_final_d1 <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ifc_fetch_adder_prior <= 30'h0;
|
|
end else if (_T_411) begin
|
|
ifc_fetch_adder_prior <= io_ifc_fetch_addr_f[30:1];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_0 <= 32'h0;
|
|
end else if (rsenable_0) begin
|
|
rets_out_0 <= rets_in_0;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_1 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_1 <= rets_in_1;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_2 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_2 <= rets_in_2;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_3 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_3 <= rets_in_3;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_4 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_4 <= rets_in_4;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_5 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_5 <= rets_in_5;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_6 <= 32'h0;
|
|
end else if (rsenable_1) begin
|
|
rets_out_6 <= rets_in_6;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rets_out_7 <= 32'h0;
|
|
end else if (rs_push) begin
|
|
rets_out_7 <= rets_out_6;
|
|
end
|
|
end
|
|
endmodule
|
|
module ifu_compress_ctl(
|
|
input [15:0] io_din,
|
|
output [31:0] io_dout
|
|
);
|
|
wire _T_2 = ~io_din[14]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_4 = ~io_din[13]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_7 = ~io_din[6]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_9 = ~io_din[5]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_11 = io_din[15] & _T_2; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_12 = _T_11 & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_13 = _T_12 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_14 = _T_13 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_15 = _T_14 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_16 = _T_15 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_23 = ~io_din[11]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_28 = _T_12 & _T_23; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_29 = _T_28 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_30 = _T_29 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_30 = _T_16 | _T_30; // @[ifu_compress_ctl.scala 17:53]
|
|
wire _T_38 = ~io_din[10]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_40 = ~io_din[9]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_42 = ~io_din[8]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_44 = ~io_din[7]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_50 = ~io_din[4]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_52 = ~io_din[3]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_54 = ~io_din[2]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_56 = _T_2 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_57 = _T_56 & _T_23; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_58 = _T_57 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_59 = _T_58 & _T_40; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_60 = _T_59 & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_61 = _T_60 & _T_44; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_62 = _T_61 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_63 = _T_62 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_64 = _T_63 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_65 = _T_64 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_66 = _T_65 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_20 = _T_66 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_79 = _T_28 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_90 = _T_12 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_91 = _T_90 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_92 = _T_79 | _T_91; // @[ifu_compress_ctl.scala 21:46]
|
|
wire _T_102 = _T_12 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_103 = _T_102 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_104 = _T_92 | _T_103; // @[ifu_compress_ctl.scala 21:80]
|
|
wire _T_114 = _T_12 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_115 = _T_114 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_14 = _T_104 | _T_115; // @[ifu_compress_ctl.scala 21:113]
|
|
wire _T_128 = _T_12 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_129 = _T_128 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_130 = _T_129 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_142 = _T_128 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_143 = _T_142 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_144 = _T_130 | _T_143; // @[ifu_compress_ctl.scala 23:50]
|
|
wire _T_147 = ~io_din[0]; // @[ifu_compress_ctl.scala 23:101]
|
|
wire _T_148 = io_din[14] & _T_147; // @[ifu_compress_ctl.scala 23:99]
|
|
wire out_13 = _T_144 | _T_148; // @[ifu_compress_ctl.scala 23:86]
|
|
wire _T_161 = _T_102 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_162 = _T_161 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_175 = _T_162 | _T_79; // @[ifu_compress_ctl.scala 25:47]
|
|
wire _T_188 = _T_175 | _T_91; // @[ifu_compress_ctl.scala 25:81]
|
|
wire _T_190 = ~io_din[15]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_194 = _T_190 & _T_2; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_195 = _T_194 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_196 = _T_188 | _T_195; // @[ifu_compress_ctl.scala 25:115]
|
|
wire _T_200 = io_din[15] & io_din[14]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_201 = _T_200 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_12 = _T_196 | _T_201; // @[ifu_compress_ctl.scala 26:28]
|
|
wire _T_217 = _T_11 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_218 = _T_217 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_219 = _T_218 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_220 = _T_219 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_221 = _T_220 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_224 = _T_221 & _T_147; // @[ifu_compress_ctl.scala 28:53]
|
|
wire _T_228 = _T_2 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_229 = _T_224 | _T_228; // @[ifu_compress_ctl.scala 28:67]
|
|
wire _T_234 = _T_200 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_6 = _T_229 | _T_234; // @[ifu_compress_ctl.scala 28:88]
|
|
wire _T_239 = io_din[15] & _T_147; // @[ifu_compress_ctl.scala 30:24]
|
|
wire _T_243 = io_din[15] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_244 = _T_243 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_245 = _T_239 | _T_244; // @[ifu_compress_ctl.scala 30:39]
|
|
wire _T_249 = io_din[13] & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_250 = _T_245 | _T_249; // @[ifu_compress_ctl.scala 30:63]
|
|
wire _T_253 = io_din[13] & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_254 = _T_250 | _T_253; // @[ifu_compress_ctl.scala 30:83]
|
|
wire _T_257 = io_din[13] & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_258 = _T_254 | _T_257; // @[ifu_compress_ctl.scala 30:102]
|
|
wire _T_261 = io_din[13] & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_262 = _T_258 | _T_261; // @[ifu_compress_ctl.scala 31:22]
|
|
wire _T_265 = io_din[13] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_266 = _T_262 | _T_265; // @[ifu_compress_ctl.scala 31:42]
|
|
wire _T_271 = _T_266 | _T_228; // @[ifu_compress_ctl.scala 31:62]
|
|
wire out_5 = _T_271 | _T_200; // @[ifu_compress_ctl.scala 31:83]
|
|
wire _T_288 = _T_2 & _T_23; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_289 = _T_288 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_290 = _T_289 & _T_40; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_291 = _T_290 & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_292 = _T_291 & _T_44; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_295 = _T_292 & _T_147; // @[ifu_compress_ctl.scala 33:50]
|
|
wire _T_303 = _T_194 & _T_147; // @[ifu_compress_ctl.scala 33:87]
|
|
wire _T_304 = _T_295 | _T_303; // @[ifu_compress_ctl.scala 33:65]
|
|
wire _T_308 = _T_2 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_311 = _T_308 & _T_147; // @[ifu_compress_ctl.scala 34:23]
|
|
wire _T_312 = _T_304 | _T_311; // @[ifu_compress_ctl.scala 33:102]
|
|
wire _T_317 = _T_190 & io_din[14]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_318 = _T_317 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_319 = _T_312 | _T_318; // @[ifu_compress_ctl.scala 34:38]
|
|
wire _T_323 = _T_2 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_326 = _T_323 & _T_147; // @[ifu_compress_ctl.scala 34:82]
|
|
wire _T_327 = _T_319 | _T_326; // @[ifu_compress_ctl.scala 34:62]
|
|
wire _T_331 = _T_2 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_334 = _T_331 & _T_147; // @[ifu_compress_ctl.scala 35:23]
|
|
wire _T_335 = _T_327 | _T_334; // @[ifu_compress_ctl.scala 34:97]
|
|
wire _T_339 = _T_2 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_342 = _T_339 & _T_147; // @[ifu_compress_ctl.scala 35:58]
|
|
wire _T_343 = _T_335 | _T_342; // @[ifu_compress_ctl.scala 35:38]
|
|
wire _T_347 = _T_2 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_350 = _T_347 & _T_147; // @[ifu_compress_ctl.scala 35:93]
|
|
wire _T_351 = _T_343 | _T_350; // @[ifu_compress_ctl.scala 35:73]
|
|
wire _T_357 = _T_2 & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_358 = _T_357 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire out_4 = _T_351 | _T_358; // @[ifu_compress_ctl.scala 35:108]
|
|
wire _T_380 = _T_56 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_381 = _T_380 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_382 = _T_381 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_383 = _T_382 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_384 = _T_383 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_385 = _T_384 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_386 = _T_385 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_403 = _T_56 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_404 = _T_403 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_405 = _T_404 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_406 = _T_405 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_407 = _T_406 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_408 = _T_407 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_409 = _T_408 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_410 = _T_386 | _T_409; // @[ifu_compress_ctl.scala 40:59]
|
|
wire _T_427 = _T_56 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_428 = _T_427 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_429 = _T_428 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_430 = _T_429 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_431 = _T_430 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_432 = _T_431 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_433 = _T_432 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_434 = _T_410 | _T_433; // @[ifu_compress_ctl.scala 40:107]
|
|
wire _T_451 = _T_56 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_452 = _T_451 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_453 = _T_452 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_454 = _T_453 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_455 = _T_454 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_456 = _T_455 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_457 = _T_456 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_458 = _T_434 | _T_457; // @[ifu_compress_ctl.scala 41:50]
|
|
wire _T_475 = _T_56 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_476 = _T_475 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_477 = _T_476 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_478 = _T_477 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_479 = _T_478 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_480 = _T_479 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_481 = _T_480 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_482 = _T_458 | _T_481; // @[ifu_compress_ctl.scala 41:94]
|
|
wire _T_487 = ~io_din[12]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_499 = _T_11 & _T_487; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_500 = _T_499 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_501 = _T_500 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_502 = _T_501 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_503 = _T_502 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_504 = _T_503 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_507 = _T_504 & _T_147; // @[ifu_compress_ctl.scala 42:94]
|
|
wire _T_508 = _T_482 | _T_507; // @[ifu_compress_ctl.scala 42:49]
|
|
wire _T_514 = _T_190 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_515 = _T_514 & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_516 = _T_508 | _T_515; // @[ifu_compress_ctl.scala 42:109]
|
|
wire _T_522 = _T_514 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_523 = _T_516 | _T_522; // @[ifu_compress_ctl.scala 43:26]
|
|
wire _T_529 = _T_514 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_530 = _T_523 | _T_529; // @[ifu_compress_ctl.scala 43:48]
|
|
wire _T_536 = _T_514 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_537 = _T_530 | _T_536; // @[ifu_compress_ctl.scala 43:70]
|
|
wire _T_543 = _T_514 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_544 = _T_537 | _T_543; // @[ifu_compress_ctl.scala 43:93]
|
|
wire out_2 = _T_544 | _T_228; // @[ifu_compress_ctl.scala 44:26]
|
|
wire [4:0] rs2d = io_din[6:2]; // @[ifu_compress_ctl.scala 50:20]
|
|
wire [4:0] rdd = io_din[11:7]; // @[ifu_compress_ctl.scala 51:19]
|
|
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
|
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
|
wire _T_557 = _T_308 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_564 = _T_317 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_565 = _T_564 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_566 = _T_557 | _T_565; // @[ifu_compress_ctl.scala 55:33]
|
|
wire _T_572 = _T_323 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_573 = _T_566 | _T_572; // @[ifu_compress_ctl.scala 55:58]
|
|
wire _T_580 = _T_317 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_581 = _T_580 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_582 = _T_573 | _T_581; // @[ifu_compress_ctl.scala 55:79]
|
|
wire _T_588 = _T_331 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_589 = _T_582 | _T_588; // @[ifu_compress_ctl.scala 55:104]
|
|
wire _T_596 = _T_317 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_597 = _T_596 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_598 = _T_589 | _T_597; // @[ifu_compress_ctl.scala 56:24]
|
|
wire _T_604 = _T_339 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_605 = _T_598 | _T_604; // @[ifu_compress_ctl.scala 56:48]
|
|
wire _T_613 = _T_317 & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_614 = _T_613 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_615 = _T_605 | _T_614; // @[ifu_compress_ctl.scala 56:69]
|
|
wire _T_621 = _T_347 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_622 = _T_615 | _T_621; // @[ifu_compress_ctl.scala 56:94]
|
|
wire _T_629 = _T_317 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_630 = _T_629 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_631 = _T_622 | _T_630; // @[ifu_compress_ctl.scala 57:24]
|
|
wire _T_635 = _T_190 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_636 = _T_631 | _T_635; // @[ifu_compress_ctl.scala 57:48]
|
|
wire _T_642 = _T_190 & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_643 = _T_642 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire rdrd = _T_636 | _T_643; // @[ifu_compress_ctl.scala 57:67]
|
|
wire _T_651 = _T_380 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_659 = _T_403 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_660 = _T_651 | _T_659; // @[ifu_compress_ctl.scala 59:38]
|
|
wire _T_668 = _T_427 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_669 = _T_660 | _T_668; // @[ifu_compress_ctl.scala 59:63]
|
|
wire _T_677 = _T_451 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_678 = _T_669 | _T_677; // @[ifu_compress_ctl.scala 59:87]
|
|
wire _T_686 = _T_475 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_687 = _T_678 | _T_686; // @[ifu_compress_ctl.scala 60:27]
|
|
wire _T_703 = _T_2 & _T_487; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_704 = _T_703 & _T_7; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_705 = _T_704 & _T_9; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_706 = _T_705 & _T_50; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_707 = _T_706 & _T_52; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_708 = _T_707 & _T_54; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_709 = _T_708 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_710 = _T_687 | _T_709; // @[ifu_compress_ctl.scala 60:51]
|
|
wire _T_717 = _T_56 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_718 = _T_717 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_719 = _T_710 | _T_718; // @[ifu_compress_ctl.scala 60:89]
|
|
wire _T_726 = _T_56 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_727 = _T_726 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_728 = _T_719 | _T_727; // @[ifu_compress_ctl.scala 61:27]
|
|
wire _T_735 = _T_56 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_736 = _T_735 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_737 = _T_728 | _T_736; // @[ifu_compress_ctl.scala 61:51]
|
|
wire _T_744 = _T_56 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_745 = _T_744 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_746 = _T_737 | _T_745; // @[ifu_compress_ctl.scala 61:75]
|
|
wire _T_753 = _T_56 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_754 = _T_753 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_755 = _T_746 | _T_754; // @[ifu_compress_ctl.scala 61:99]
|
|
wire _T_764 = _T_194 & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_765 = _T_764 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_766 = _T_755 | _T_765; // @[ifu_compress_ctl.scala 62:27]
|
|
wire rdrs1 = _T_766 | _T_195; // @[ifu_compress_ctl.scala 62:54]
|
|
wire _T_777 = io_din[15] & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_778 = _T_777 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_782 = io_din[15] & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_783 = _T_782 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_784 = _T_778 | _T_783; // @[ifu_compress_ctl.scala 64:34]
|
|
wire _T_788 = io_din[15] & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_789 = _T_788 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_790 = _T_784 | _T_789; // @[ifu_compress_ctl.scala 64:54]
|
|
wire _T_794 = io_din[15] & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_795 = _T_794 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_796 = _T_790 | _T_795; // @[ifu_compress_ctl.scala 64:74]
|
|
wire _T_800 = io_din[15] & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_801 = _T_800 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_802 = _T_796 | _T_801; // @[ifu_compress_ctl.scala 64:94]
|
|
wire _T_807 = _T_200 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire rs2rs2 = _T_802 | _T_807; // @[ifu_compress_ctl.scala 64:114]
|
|
wire rdprd = _T_12 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_820 = io_din[15] & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_821 = _T_820 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_827 = _T_821 | _T_234; // @[ifu_compress_ctl.scala 68:36]
|
|
wire _T_830 = ~io_din[1]; // @[ifu_compress_ctl.scala 12:83]
|
|
wire _T_831 = io_din[14] & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_834 = _T_831 & _T_147; // @[ifu_compress_ctl.scala 68:76]
|
|
wire rdprs1 = _T_827 | _T_834; // @[ifu_compress_ctl.scala 68:57]
|
|
wire _T_846 = _T_128 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_847 = _T_846 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_851 = io_din[15] & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_854 = _T_851 & _T_147; // @[ifu_compress_ctl.scala 70:66]
|
|
wire rs2prs2 = _T_847 | _T_854; // @[ifu_compress_ctl.scala 70:47]
|
|
wire _T_859 = _T_190 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire rs2prd = _T_859 & _T_147; // @[ifu_compress_ctl.scala 72:33]
|
|
wire _T_866 = _T_2 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire uimm9_2 = _T_866 & _T_147; // @[ifu_compress_ctl.scala 74:34]
|
|
wire _T_875 = _T_317 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire ulwimm6_2 = _T_875 & _T_147; // @[ifu_compress_ctl.scala 76:39]
|
|
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_897 = _T_317 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_898 = _T_897 & _T_23; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_899 = _T_898 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_900 = _T_899 & _T_40; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_901 = _T_900 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire rdeq2 = _T_901 & _T_44; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1027 = _T_194 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire rdeq1 = _T_482 | _T_1027; // @[ifu_compress_ctl.scala 84:42]
|
|
wire _T_1050 = io_din[14] & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1051 = rdeq2 | _T_1050; // @[ifu_compress_ctl.scala 86:53]
|
|
wire rs1eq2 = _T_1051 | uimm9_2; // @[ifu_compress_ctl.scala 86:71]
|
|
wire _T_1092 = _T_357 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1093 = _T_1092 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1094 = _T_1093 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire simm5_0 = _T_1094 | _T_643; // @[ifu_compress_ctl.scala 92:45]
|
|
wire _T_1112 = _T_897 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1121 = _T_897 & _T_42; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1122 = _T_1112 | _T_1121; // @[ifu_compress_ctl.scala 96:44]
|
|
wire _T_1130 = _T_897 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1131 = _T_1122 | _T_1130; // @[ifu_compress_ctl.scala 96:70]
|
|
wire _T_1139 = _T_897 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1140 = _T_1131 | _T_1139; // @[ifu_compress_ctl.scala 96:95]
|
|
wire _T_1148 = _T_897 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire sluimm17_12 = _T_1140 | _T_1148; // @[ifu_compress_ctl.scala 96:121]
|
|
wire uimm5_0 = _T_79 | _T_195; // @[ifu_compress_ctl.scala 98:45]
|
|
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
|
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[ifu_compress_ctl.scala 114:67]
|
|
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
|
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
|
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
|
wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
|
wire [19:0] sjald = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],sjald_1}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_1296 = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12]}; // @[Cat.scala 29:58]
|
|
wire [19:0] sluimmd = {_T_1296,io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1314 = {simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[4:0]}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1317 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1325 = {simm9d[5],simm9d[5],simm9d[5],simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1328 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1331 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1333 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1339 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1342 = simm5_0 ? _T_1314 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1343 = uimm9_2 ? _T_1317 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1344 = rdeq2 ? _T_1325 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1345 = ulwimm6_2 ? _T_1328 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1346 = ulwspimm7_2 ? _T_1331 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1347 = uimm5_0 ? _T_1333 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1348 = _T_228 ? _T_1339 : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1349 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1350 = _T_1342 | _T_1343; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1351 = _T_1350 | _T_1344; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1352 = _T_1351 | _T_1345; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1353 = _T_1352 | _T_1346; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1354 = _T_1353 | _T_1347; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1355 = _T_1354 | _T_1348; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1356 = _T_1355 | _T_1349; // @[Mux.scala 27:72]
|
|
wire [11:0] l2_31 = l1[31:20] | _T_1356; // @[ifu_compress_ctl.scala 133:25]
|
|
wire [7:0] _T_1363 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1364 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1365 = _T_1363 | _T_1364; // @[Mux.scala 27:72]
|
|
wire [7:0] l2_19 = l1[19:12] | _T_1365; // @[ifu_compress_ctl.scala 143:25]
|
|
wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
|
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
|
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1400 = {sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[7:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1403 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1406 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1407 = _T_234 ? _T_1400 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1408 = _T_854 ? _T_1403 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1409 = _T_807 ? _T_1406 : 7'h0; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1410 = _T_1407 | _T_1408; // @[Mux.scala 27:72]
|
|
wire [6:0] _T_1411 = _T_1410 | _T_1409; // @[Mux.scala 27:72]
|
|
wire [6:0] l3_31 = l2[31:25] | _T_1411; // @[ifu_compress_ctl.scala 151:25]
|
|
wire [12:0] l3_24 = l2[24:12]; // @[ifu_compress_ctl.scala 154:17]
|
|
wire [4:0] _T_1417 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_1422 = _T_234 ? _T_1417 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1423 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1424 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1425 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1426 = _T_1425 | _T_1424; // @[Mux.scala 27:72]
|
|
wire [4:0] l3_11 = l2[11:7] | _T_1426; // @[ifu_compress_ctl.scala 156:24]
|
|
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
|
wire _T_1437 = _T_4 & _T_487; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1438 = _T_1437 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1439 = _T_1438 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1442 = _T_1439 & _T_147; // @[ifu_compress_ctl.scala 162:39]
|
|
wire _T_1450 = _T_1437 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1451 = _T_1450 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1454 = _T_1451 & _T_147; // @[ifu_compress_ctl.scala 162:79]
|
|
wire _T_1455 = _T_1442 | _T_1454; // @[ifu_compress_ctl.scala 162:54]
|
|
wire _T_1464 = _T_642 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1465 = _T_1464 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1466 = _T_1455 | _T_1465; // @[ifu_compress_ctl.scala 162:94]
|
|
wire _T_1474 = _T_1437 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1475 = _T_1474 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1478 = _T_1475 & _T_147; // @[ifu_compress_ctl.scala 163:55]
|
|
wire _T_1479 = _T_1466 | _T_1478; // @[ifu_compress_ctl.scala 163:30]
|
|
wire _T_1487 = _T_1437 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1488 = _T_1487 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1491 = _T_1488 & _T_147; // @[ifu_compress_ctl.scala 163:96]
|
|
wire _T_1492 = _T_1479 | _T_1491; // @[ifu_compress_ctl.scala 163:70]
|
|
wire _T_1501 = _T_642 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1502 = _T_1501 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1503 = _T_1492 | _T_1502; // @[ifu_compress_ctl.scala 163:111]
|
|
wire _T_1510 = io_din[15] & _T_487; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1511 = _T_1510 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1512 = _T_1511 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1513 = _T_1503 | _T_1512; // @[ifu_compress_ctl.scala 164:29]
|
|
wire _T_1521 = _T_1437 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1522 = _T_1521 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1525 = _T_1522 & _T_147; // @[ifu_compress_ctl.scala 164:79]
|
|
wire _T_1526 = _T_1513 | _T_1525; // @[ifu_compress_ctl.scala 164:54]
|
|
wire _T_1533 = _T_487 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1534 = _T_1533 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1535 = _T_1534 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1536 = _T_1526 | _T_1535; // @[ifu_compress_ctl.scala 164:94]
|
|
wire _T_1545 = _T_642 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1546 = _T_1545 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1547 = _T_1536 | _T_1546; // @[ifu_compress_ctl.scala 164:118]
|
|
wire _T_1555 = _T_1437 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1556 = _T_1555 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1559 = _T_1556 & _T_147; // @[ifu_compress_ctl.scala 165:28]
|
|
wire _T_1560 = _T_1547 | _T_1559; // @[ifu_compress_ctl.scala 164:144]
|
|
wire _T_1567 = _T_487 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1568 = _T_1567 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1569 = _T_1568 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1570 = _T_1560 | _T_1569; // @[ifu_compress_ctl.scala 165:43]
|
|
wire _T_1579 = _T_642 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1580 = _T_1579 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1581 = _T_1570 | _T_1580; // @[ifu_compress_ctl.scala 165:67]
|
|
wire _T_1589 = _T_1437 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1590 = _T_1589 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1593 = _T_1590 & _T_147; // @[ifu_compress_ctl.scala 166:28]
|
|
wire _T_1594 = _T_1581 | _T_1593; // @[ifu_compress_ctl.scala 165:94]
|
|
wire _T_1602 = io_din[12] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1603 = _T_1602 & _T_38; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1604 = _T_1603 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1605 = _T_1604 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1606 = _T_1594 | _T_1605; // @[ifu_compress_ctl.scala 166:43]
|
|
wire _T_1615 = _T_642 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1616 = _T_1615 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1617 = _T_1606 | _T_1616; // @[ifu_compress_ctl.scala 166:71]
|
|
wire _T_1625 = _T_1437 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1626 = _T_1625 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1629 = _T_1626 & _T_147; // @[ifu_compress_ctl.scala 167:28]
|
|
wire _T_1630 = _T_1617 | _T_1629; // @[ifu_compress_ctl.scala 166:97]
|
|
wire _T_1636 = io_din[13] & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1637 = _T_1636 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1638 = _T_1637 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1639 = _T_1630 | _T_1638; // @[ifu_compress_ctl.scala 167:43]
|
|
wire _T_1648 = _T_642 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1649 = _T_1648 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1650 = _T_1639 | _T_1649; // @[ifu_compress_ctl.scala 167:67]
|
|
wire _T_1658 = _T_1437 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1659 = _T_1658 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1662 = _T_1659 & _T_147; // @[ifu_compress_ctl.scala 168:28]
|
|
wire _T_1663 = _T_1650 | _T_1662; // @[ifu_compress_ctl.scala 167:93]
|
|
wire _T_1669 = io_din[13] & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1670 = _T_1669 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1671 = _T_1670 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1672 = _T_1663 | _T_1671; // @[ifu_compress_ctl.scala 168:43]
|
|
wire _T_1680 = _T_1437 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1681 = _T_1680 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1684 = _T_1681 & _T_147; // @[ifu_compress_ctl.scala 168:91]
|
|
wire _T_1685 = _T_1672 | _T_1684; // @[ifu_compress_ctl.scala 168:66]
|
|
wire _T_1694 = _T_642 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1695 = _T_1694 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1696 = _T_1685 | _T_1695; // @[ifu_compress_ctl.scala 168:106]
|
|
wire _T_1702 = io_din[13] & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1703 = _T_1702 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1704 = _T_1703 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1705 = _T_1696 | _T_1704; // @[ifu_compress_ctl.scala 169:29]
|
|
wire _T_1711 = io_din[13] & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1712 = _T_1711 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1713 = _T_1712 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1714 = _T_1705 | _T_1713; // @[ifu_compress_ctl.scala 169:52]
|
|
wire _T_1720 = io_din[14] & _T_4; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1721 = _T_1720 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1722 = _T_1714 | _T_1721; // @[ifu_compress_ctl.scala 169:75]
|
|
wire _T_1731 = _T_703 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1732 = _T_1731 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1733 = _T_1722 | _T_1732; // @[ifu_compress_ctl.scala 169:98]
|
|
wire _T_1740 = _T_820 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1741 = _T_1740 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1744 = _T_1741 & _T_147; // @[ifu_compress_ctl.scala 170:54]
|
|
wire _T_1745 = _T_1733 | _T_1744; // @[ifu_compress_ctl.scala 170:29]
|
|
wire _T_1754 = _T_642 & _T_487; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1755 = _T_1754 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1758 = _T_1755 & _T_147; // @[ifu_compress_ctl.scala 170:96]
|
|
wire _T_1759 = _T_1745 | _T_1758; // @[ifu_compress_ctl.scala 170:69]
|
|
wire _T_1768 = _T_642 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1769 = _T_1768 & _T_830; // @[ifu_compress_ctl.scala 12:110]
|
|
wire _T_1770 = _T_1759 | _T_1769; // @[ifu_compress_ctl.scala 170:111]
|
|
wire _T_1777 = _T_1720 & _T_147; // @[ifu_compress_ctl.scala 171:50]
|
|
wire legal = _T_1770 | _T_1777; // @[ifu_compress_ctl.scala 171:30]
|
|
wire [9:0] _T_1787 = {legal,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_1796 = {_T_1787,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_1805 = {_T_1796,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1809 = {_T_1805,legal,legal,legal,legal}; // @[Cat.scala 29:58]
|
|
assign io_dout = l3 & _T_1809; // @[ifu_compress_ctl.scala 173:10]
|
|
endmodule
|
|
module ifu_aln_ctl(
|
|
input clk,
|
|
input reset,
|
|
input io_active_clk,
|
|
input io_ifu_async_error_start,
|
|
input [1:0] io_iccm_rd_ecc_double_err,
|
|
input [1:0] io_ic_access_fault_f,
|
|
input [1:0] io_ic_access_fault_type_f,
|
|
input io_dec_i0_decode_d,
|
|
output [15:0] io_dec_aln_aln_dec_ifu_i0_cinst,
|
|
output io_dec_aln_aln_ib_ifu_i0_icaf,
|
|
output [1:0] io_dec_aln_aln_ib_ifu_i0_icaf_type,
|
|
output io_dec_aln_aln_ib_ifu_i0_icaf_second,
|
|
output io_dec_aln_aln_ib_ifu_i0_dbecc,
|
|
output [7:0] io_dec_aln_aln_ib_ifu_i0_bp_index,
|
|
output [7:0] io_dec_aln_aln_ib_ifu_i0_bp_fghr,
|
|
output [4:0] io_dec_aln_aln_ib_ifu_i0_bp_btag,
|
|
output io_dec_aln_aln_ib_ifu_i0_valid,
|
|
output [31:0] io_dec_aln_aln_ib_ifu_i0_instr,
|
|
output [30:0] io_dec_aln_aln_ib_ifu_i0_pc,
|
|
output io_dec_aln_aln_ib_ifu_i0_pc4,
|
|
output io_dec_aln_aln_ib_i0_brp_valid,
|
|
output [11:0] io_dec_aln_aln_ib_i0_brp_bits_toffset,
|
|
output [1:0] io_dec_aln_aln_ib_i0_brp_bits_hist,
|
|
output io_dec_aln_aln_ib_i0_brp_bits_br_error,
|
|
output io_dec_aln_aln_ib_i0_brp_bits_br_start_error,
|
|
output [30:0] io_dec_aln_aln_ib_i0_brp_bits_prett,
|
|
output io_dec_aln_aln_ib_i0_brp_bits_way,
|
|
output io_dec_aln_aln_ib_i0_brp_bits_ret,
|
|
output io_dec_aln_ifu_pmu_instr_aligned,
|
|
input [7:0] io_ifu_bp_fghr_f,
|
|
input [30:0] io_ifu_bp_btb_target_f,
|
|
input [11:0] io_ifu_bp_poffset_f,
|
|
input [1:0] io_ifu_bp_hist0_f,
|
|
input [1:0] io_ifu_bp_hist1_f,
|
|
input [1:0] io_ifu_bp_pc4_f,
|
|
input [1:0] io_ifu_bp_way_f,
|
|
input [1:0] io_ifu_bp_valid_f,
|
|
input [1:0] io_ifu_bp_ret_f,
|
|
input io_exu_flush_final,
|
|
input [31:0] io_ifu_fetch_data_f,
|
|
input [1:0] io_ifu_fetch_val,
|
|
input [30:0] io_ifu_fetch_pc,
|
|
output io_ifu_fb_consume1,
|
|
output io_ifu_fb_consume2
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [63:0] _RAND_15;
|
|
reg [63:0] _RAND_16;
|
|
reg [63:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire [15:0] decompressed_io_din; // @[ifu_aln_ctl.scala 444:28]
|
|
wire [31:0] decompressed_io_dout; // @[ifu_aln_ctl.scala 444:28]
|
|
reg error_stall; // @[Reg.scala 27:20]
|
|
wire _T = error_stall | io_ifu_async_error_start; // @[ifu_aln_ctl.scala 119:37]
|
|
wire _T_1 = ~io_exu_flush_final; // @[ifu_aln_ctl.scala 119:67]
|
|
wire error_stall_in = _T & _T_1; // @[ifu_aln_ctl.scala 119:65]
|
|
reg [1:0] wrptr; // @[ifu_aln_ctl.scala 120:48]
|
|
reg [1:0] rdptr; // @[ifu_aln_ctl.scala 121:48]
|
|
reg q2off; // @[ifu_aln_ctl.scala 122:48]
|
|
reg q1off; // @[ifu_aln_ctl.scala 123:48]
|
|
reg q0off; // @[ifu_aln_ctl.scala 124:48]
|
|
wire _T_3 = error_stall_in ^ error_stall; // @[lib.scala 466:21]
|
|
wire _T_4 = |_T_3; // @[lib.scala 466:29]
|
|
wire _T_821 = ~error_stall; // @[ifu_aln_ctl.scala 504:39]
|
|
wire i0_shift = io_dec_i0_decode_d & _T_821; // @[ifu_aln_ctl.scala 504:37]
|
|
reg [1:0] f0val; // @[Reg.scala 27:20]
|
|
wire _T_191 = rdptr == 2'h0; // @[ifu_aln_ctl.scala 192:31]
|
|
wire _T_194 = _T_191 & q0off; // @[Mux.scala 27:72]
|
|
wire _T_192 = rdptr == 2'h1; // @[ifu_aln_ctl.scala 193:11]
|
|
wire _T_195 = _T_192 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_197 = _T_194 | _T_195; // @[Mux.scala 27:72]
|
|
wire _T_193 = rdptr == 2'h2; // @[ifu_aln_ctl.scala 194:11]
|
|
wire _T_196 = _T_193 & q2off; // @[Mux.scala 27:72]
|
|
wire q0ptr = _T_197 | _T_196; // @[Mux.scala 27:72]
|
|
wire _T_207 = ~q0ptr; // @[ifu_aln_ctl.scala 198:26]
|
|
wire [1:0] q0sel = {q0ptr,_T_207}; // @[Cat.scala 29:58]
|
|
wire [2:0] qren = {_T_193,_T_192,_T_191}; // @[Cat.scala 29:58]
|
|
reg [31:0] q1; // @[Reg.scala 27:20]
|
|
reg [31:0] q0; // @[Reg.scala 27:20]
|
|
wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] q2; // @[Reg.scala 27:20]
|
|
wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_485 = {q0,q2}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_488 = qren[2] ? _T_485 : 64'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] qeff = _T_489 | _T_488; // @[Mux.scala 27:72]
|
|
wire [31:0] q0eff = qeff[31:0]; // @[ifu_aln_ctl.scala 370:42]
|
|
wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _GEN_16 = {{16'd0}, _T_497}; // @[Mux.scala 27:72]
|
|
wire [31:0] q0final = _T_496 | _GEN_16; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_541 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_534 = ~f0val[1]; // @[ifu_aln_ctl.scala 384:58]
|
|
wire _T_536 = _T_534 & f0val[0]; // @[ifu_aln_ctl.scala 384:68]
|
|
wire _T_202 = _T_191 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_203 = _T_192 & q2off; // @[Mux.scala 27:72]
|
|
wire _T_205 = _T_202 | _T_203; // @[Mux.scala 27:72]
|
|
wire _T_204 = _T_193 & q0off; // @[Mux.scala 27:72]
|
|
wire q1ptr = _T_205 | _T_204; // @[Mux.scala 27:72]
|
|
wire _T_208 = ~q1ptr; // @[ifu_aln_ctl.scala 200:26]
|
|
wire [1:0] q1sel = {q1ptr,_T_208}; // @[Cat.scala 29:58]
|
|
wire [31:0] q1eff = qeff[63:32]; // @[ifu_aln_ctl.scala 370:29]
|
|
wire [15:0] _T_506 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_507 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] q1final = _T_506 | _T_507; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_540 = {q1final,q0final[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_542 = _T_536 ? _T_540 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] aligndata = _T_541 | _T_542; // @[Mux.scala 27:72]
|
|
wire first4B = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 426:29]
|
|
wire first2B = ~first4B; // @[ifu_aln_ctl.scala 428:17]
|
|
wire shift_2B = i0_shift & first2B; // @[ifu_aln_ctl.scala 508:24]
|
|
wire [1:0] _T_443 = {1'h0,f0val[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_448 = shift_2B ? _T_443 : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_444 = ~shift_2B; // @[ifu_aln_ctl.scala 360:6]
|
|
wire shift_4B = i0_shift & first4B; // @[ifu_aln_ctl.scala 509:24]
|
|
wire _T_445 = ~shift_4B; // @[ifu_aln_ctl.scala 360:18]
|
|
wire _T_446 = _T_444 & _T_445; // @[ifu_aln_ctl.scala 360:16]
|
|
wire [1:0] _T_449 = _T_446 ? f0val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] sf0val = _T_448 | _T_449; // @[Mux.scala 27:72]
|
|
wire sf0_valid = sf0val[0]; // @[ifu_aln_ctl.scala 326:22]
|
|
wire _T_389 = ~sf0_valid; // @[ifu_aln_ctl.scala 347:26]
|
|
wire _T_838 = f0val[0] & _T_534; // @[ifu_aln_ctl.scala 512:28]
|
|
wire f1_shift_2B = _T_838 & shift_4B; // @[ifu_aln_ctl.scala 512:40]
|
|
reg [1:0] f1val; // @[Reg.scala 27:20]
|
|
wire _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
|
|
wire _T_416 = ~f1_shift_2B; // @[ifu_aln_ctl.scala 353:53]
|
|
wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_17 = {{1'd0}, _T_417}; // @[Mux.scala 27:72]
|
|
wire [1:0] sf1val = _GEN_17 | _T_418; // @[Mux.scala 27:72]
|
|
wire sf1_valid = sf1val[0]; // @[ifu_aln_ctl.scala 325:22]
|
|
wire _T_390 = _T_389 & sf1_valid; // @[ifu_aln_ctl.scala 347:37]
|
|
reg [1:0] f2val; // @[Reg.scala 27:20]
|
|
wire f2_valid = f2val[0]; // @[ifu_aln_ctl.scala 324:20]
|
|
wire _T_391 = _T_390 & f2_valid; // @[ifu_aln_ctl.scala 347:50]
|
|
wire ifvalid = io_ifu_fetch_val[0]; // @[ifu_aln_ctl.scala 335:30]
|
|
wire _T_392 = _T_391 & ifvalid; // @[ifu_aln_ctl.scala 347:62]
|
|
wire _T_393 = sf0_valid & sf1_valid; // @[ifu_aln_ctl.scala 348:17]
|
|
wire _T_394 = ~f2_valid; // @[ifu_aln_ctl.scala 348:32]
|
|
wire _T_395 = _T_393 & _T_394; // @[ifu_aln_ctl.scala 348:30]
|
|
wire _T_396 = _T_395 & ifvalid; // @[ifu_aln_ctl.scala 348:42]
|
|
wire fetch_to_f2 = _T_392 | _T_396; // @[ifu_aln_ctl.scala 347:74]
|
|
wire _T_399 = fetch_to_f2 & _T_1; // @[ifu_aln_ctl.scala 350:38]
|
|
wire [1:0] _T_409 = _T_399 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_401 = ~fetch_to_f2; // @[ifu_aln_ctl.scala 351:6]
|
|
wire _T_402 = ~_T_391; // @[ifu_aln_ctl.scala 351:21]
|
|
wire _T_403 = _T_401 & _T_402; // @[ifu_aln_ctl.scala 351:19]
|
|
wire _T_360 = ~sf1_valid; // @[ifu_aln_ctl.scala 339:31]
|
|
wire _T_361 = _T_389 & _T_360; // @[ifu_aln_ctl.scala 339:29]
|
|
wire shift_f2_f0 = _T_361 & f2_valid; // @[ifu_aln_ctl.scala 339:42]
|
|
wire _T_404 = ~shift_f2_f0; // @[ifu_aln_ctl.scala 351:36]
|
|
wire _T_405 = _T_403 & _T_404; // @[ifu_aln_ctl.scala 351:34]
|
|
wire _T_407 = _T_405 & _T_1; // @[ifu_aln_ctl.scala 351:49]
|
|
wire [1:0] _T_410 = _T_407 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] f2val_in = _T_409 | _T_410; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_6 = f2val_in ^ f2val; // @[lib.scala 466:21]
|
|
wire _T_7 = |_T_6; // @[lib.scala 466:29]
|
|
wire _T_376 = shift_f2_f0 & ifvalid; // @[ifu_aln_ctl.scala 343:62]
|
|
wire _T_380 = _T_390 & _T_394; // @[ifu_aln_ctl.scala 344:30]
|
|
wire _T_381 = _T_380 & ifvalid; // @[ifu_aln_ctl.scala 344:42]
|
|
wire _T_382 = _T_376 | _T_381; // @[ifu_aln_ctl.scala 343:74]
|
|
wire _T_384 = sf0_valid & _T_360; // @[ifu_aln_ctl.scala 345:17]
|
|
wire _T_386 = _T_384 & _T_394; // @[ifu_aln_ctl.scala 345:30]
|
|
wire _T_387 = _T_386 & ifvalid; // @[ifu_aln_ctl.scala 345:42]
|
|
wire fetch_to_f1 = _T_382 | _T_387; // @[ifu_aln_ctl.scala 344:54]
|
|
wire _T_422 = fetch_to_f1 & _T_1; // @[ifu_aln_ctl.scala 355:39]
|
|
wire [1:0] _T_435 = _T_422 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_425 = _T_391 & _T_1; // @[ifu_aln_ctl.scala 356:34]
|
|
wire [1:0] _T_436 = _T_425 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_438 = _T_435 | _T_436; // @[Mux.scala 27:72]
|
|
wire _T_427 = ~fetch_to_f1; // @[ifu_aln_ctl.scala 357:6]
|
|
wire _T_429 = _T_427 & _T_402; // @[ifu_aln_ctl.scala 357:19]
|
|
wire _T_430 = ~_T_390; // @[ifu_aln_ctl.scala 357:36]
|
|
wire _T_431 = _T_429 & _T_430; // @[ifu_aln_ctl.scala 357:34]
|
|
wire _T_433 = _T_431 & _T_1; // @[ifu_aln_ctl.scala 357:49]
|
|
wire [1:0] _T_437 = _T_433 ? sf1val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] f1val_in = _T_438 | _T_437; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_9 = f1val_in ^ f1val; // @[lib.scala 466:21]
|
|
wire _T_10 = |_T_9; // @[lib.scala 466:29]
|
|
wire _T_370 = _T_361 & _T_394; // @[ifu_aln_ctl.scala 342:50]
|
|
wire fetch_to_f0 = _T_370 & ifvalid; // @[ifu_aln_ctl.scala 342:62]
|
|
wire _T_453 = fetch_to_f0 & _T_1; // @[ifu_aln_ctl.scala 362:38]
|
|
wire [1:0] _T_469 = _T_453 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
|
|
wire _T_456 = shift_f2_f0 & _T_1; // @[ifu_aln_ctl.scala 363:34]
|
|
wire [1:0] _T_470 = _T_456 ? f2val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_473 = _T_469 | _T_470; // @[Mux.scala 27:72]
|
|
wire _T_459 = _T_390 & _T_1; // @[ifu_aln_ctl.scala 364:49]
|
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wire [1:0] _T_471 = _T_459 ? sf1val : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_474 = _T_473 | _T_471; // @[Mux.scala 27:72]
|
|
wire _T_461 = ~fetch_to_f0; // @[ifu_aln_ctl.scala 365:6]
|
|
wire _T_463 = _T_461 & _T_404; // @[ifu_aln_ctl.scala 365:19]
|
|
wire _T_465 = _T_463 & _T_430; // @[ifu_aln_ctl.scala 365:34]
|
|
wire _T_467 = _T_465 & _T_1; // @[ifu_aln_ctl.scala 365:49]
|
|
wire [1:0] _T_472 = _T_467 ? sf0val : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] f0val_in = _T_474 | _T_472; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_12 = f0val_in ^ f0val; // @[lib.scala 466:21]
|
|
wire _T_13 = |_T_12; // @[lib.scala 466:29]
|
|
wire _T_40 = wrptr == 2'h2; // @[ifu_aln_ctl.scala 162:22]
|
|
wire _T_41 = _T_40 & ifvalid; // @[ifu_aln_ctl.scala 162:31]
|
|
wire _T_42 = wrptr == 2'h1; // @[ifu_aln_ctl.scala 162:49]
|
|
wire _T_43 = _T_42 & ifvalid; // @[ifu_aln_ctl.scala 162:58]
|
|
wire _T_44 = wrptr == 2'h0; // @[ifu_aln_ctl.scala 162:76]
|
|
wire _T_45 = _T_44 & ifvalid; // @[ifu_aln_ctl.scala 162:85]
|
|
wire [2:0] qwen = {_T_41,_T_43,_T_45}; // @[Cat.scala 29:58]
|
|
reg [15:0] brdata2; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_283 = {io_iccm_rd_ecc_double_err[0],io_ic_access_fault_f[0],io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
|
|
wire [15:0] brdata_in = {io_iccm_rd_ecc_double_err[1],io_ic_access_fault_f[1],io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_283}; // @[Cat.scala 29:58]
|
|
reg [15:0] brdata1; // @[Reg.scala 27:20]
|
|
reg [15:0] brdata0; // @[Reg.scala 27:20]
|
|
reg [52:0] misc2; // @[Reg.scala 27:20]
|
|
wire [52:0] misc_data_in = {io_ic_access_fault_type_f,io_ifu_bp_btb_target_f,io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
|
|
reg [52:0] misc1; // @[Reg.scala 27:20]
|
|
reg [52:0] misc0; // @[Reg.scala 27:20]
|
|
reg [30:0] q2pc; // @[Reg.scala 27:20]
|
|
reg [30:0] q1pc; // @[Reg.scala 27:20]
|
|
reg [30:0] q0pc; // @[Reg.scala 27:20]
|
|
wire _T_49 = qren[0] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 164:34]
|
|
wire _T_51 = _T_49 & _T_1; // @[ifu_aln_ctl.scala 164:55]
|
|
wire _T_54 = qren[1] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 165:14]
|
|
wire _T_56 = _T_54 & _T_1; // @[ifu_aln_ctl.scala 165:35]
|
|
wire _T_64 = qren[0] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 167:14]
|
|
wire _T_66 = _T_64 & _T_1; // @[ifu_aln_ctl.scala 167:35]
|
|
wire _T_74 = qren[2] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 169:14]
|
|
wire _T_76 = _T_74 & _T_1; // @[ifu_aln_ctl.scala 169:35]
|
|
wire _T_78 = ~io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 170:6]
|
|
wire _T_79 = ~io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 170:28]
|
|
wire _T_80 = _T_78 & _T_79; // @[ifu_aln_ctl.scala 170:26]
|
|
wire _T_82 = _T_80 & _T_1; // @[ifu_aln_ctl.scala 170:48]
|
|
wire [1:0] _T_85 = _T_56 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_87 = _T_66 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_90 = _T_82 ? rdptr : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_18 = {{1'd0}, _T_51}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_91 = _GEN_18 | _T_85; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_93 = _T_91 | _T_87; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_19 = {{1'd0}, _T_76}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_95 = _T_93 | _GEN_19; // @[Mux.scala 27:72]
|
|
wire _T_100 = qwen[0] & _T_1; // @[ifu_aln_ctl.scala 173:34]
|
|
wire _T_104 = qwen[1] & _T_1; // @[ifu_aln_ctl.scala 174:14]
|
|
wire _T_110 = ~ifvalid; // @[ifu_aln_ctl.scala 176:6]
|
|
wire _T_112 = _T_110 & _T_1; // @[ifu_aln_ctl.scala 176:15]
|
|
wire [1:0] _T_115 = _T_104 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_117 = _T_112 ? wrptr : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_20 = {{1'd0}, _T_100}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_118 = _GEN_20 | _T_115; // @[Mux.scala 27:72]
|
|
wire _T_123 = ~qwen[2]; // @[ifu_aln_ctl.scala 178:26]
|
|
wire _T_125 = _T_123 & _T_193; // @[ifu_aln_ctl.scala 178:35]
|
|
wire _T_831 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
|
|
wire _T_832 = shift_4B & _T_838; // @[Mux.scala 27:72]
|
|
wire f0_shift_2B = _T_831 | _T_832; // @[Mux.scala 27:72]
|
|
wire _T_127 = q2off | f0_shift_2B; // @[ifu_aln_ctl.scala 178:76]
|
|
wire _T_131 = _T_123 & _T_192; // @[ifu_aln_ctl.scala 179:15]
|
|
wire _T_133 = q2off | f1_shift_2B; // @[ifu_aln_ctl.scala 179:56]
|
|
wire _T_137 = _T_123 & _T_191; // @[ifu_aln_ctl.scala 180:15]
|
|
wire _T_139 = _T_125 & _T_127; // @[Mux.scala 27:72]
|
|
wire _T_140 = _T_131 & _T_133; // @[Mux.scala 27:72]
|
|
wire _T_141 = _T_137 & q2off; // @[Mux.scala 27:72]
|
|
wire _T_142 = _T_139 | _T_140; // @[Mux.scala 27:72]
|
|
wire _T_146 = ~qwen[1]; // @[ifu_aln_ctl.scala 182:26]
|
|
wire _T_148 = _T_146 & _T_192; // @[ifu_aln_ctl.scala 182:35]
|
|
wire _T_150 = q1off | f0_shift_2B; // @[ifu_aln_ctl.scala 182:76]
|
|
wire _T_154 = _T_146 & _T_191; // @[ifu_aln_ctl.scala 183:15]
|
|
wire _T_156 = q1off | f1_shift_2B; // @[ifu_aln_ctl.scala 183:56]
|
|
wire _T_160 = _T_146 & _T_193; // @[ifu_aln_ctl.scala 184:15]
|
|
wire _T_162 = _T_148 & _T_150; // @[Mux.scala 27:72]
|
|
wire _T_163 = _T_154 & _T_156; // @[Mux.scala 27:72]
|
|
wire _T_164 = _T_160 & q1off; // @[Mux.scala 27:72]
|
|
wire _T_165 = _T_162 | _T_163; // @[Mux.scala 27:72]
|
|
wire _T_169 = ~qwen[0]; // @[ifu_aln_ctl.scala 186:26]
|
|
wire _T_171 = _T_169 & _T_191; // @[ifu_aln_ctl.scala 186:35]
|
|
wire _T_173 = q0off | f0_shift_2B; // @[ifu_aln_ctl.scala 186:76]
|
|
wire _T_177 = _T_169 & _T_193; // @[ifu_aln_ctl.scala 187:15]
|
|
wire _T_179 = q0off | f1_shift_2B; // @[ifu_aln_ctl.scala 187:56]
|
|
wire _T_183 = _T_169 & _T_192; // @[ifu_aln_ctl.scala 188:15]
|
|
wire _T_185 = _T_171 & _T_173; // @[Mux.scala 27:72]
|
|
wire _T_186 = _T_177 & _T_179; // @[Mux.scala 27:72]
|
|
wire _T_187 = _T_183 & q0off; // @[Mux.scala 27:72]
|
|
wire _T_188 = _T_185 | _T_186; // @[Mux.scala 27:72]
|
|
wire [105:0] _T_214 = {misc1,misc0}; // @[Cat.scala 29:58]
|
|
wire [105:0] _T_217 = {misc2,misc1}; // @[Cat.scala 29:58]
|
|
wire [105:0] _T_220 = {misc0,misc2}; // @[Cat.scala 29:58]
|
|
wire [105:0] _T_221 = qren[0] ? _T_214 : 106'h0; // @[Mux.scala 27:72]
|
|
wire [105:0] _T_222 = qren[1] ? _T_217 : 106'h0; // @[Mux.scala 27:72]
|
|
wire [105:0] _T_223 = qren[2] ? _T_220 : 106'h0; // @[Mux.scala 27:72]
|
|
wire [105:0] _T_224 = _T_221 | _T_222; // @[Mux.scala 27:72]
|
|
wire [105:0] misceff = _T_224 | _T_223; // @[Mux.scala 27:72]
|
|
wire [52:0] misc1eff = misceff[105:53]; // @[ifu_aln_ctl.scala 214:25]
|
|
wire [52:0] misc0eff = misceff[52:0]; // @[ifu_aln_ctl.scala 215:25]
|
|
wire [1:0] f1ictype = misc1eff[52:51]; // @[ifu_aln_ctl.scala 218:43]
|
|
wire [30:0] f1prett = misc1eff[50:20]; // @[ifu_aln_ctl.scala 219:43]
|
|
wire [11:0] f1poffset = misc1eff[19:8]; // @[ifu_aln_ctl.scala 220:43]
|
|
wire [7:0] f1fghr = misc1eff[7:0]; // @[ifu_aln_ctl.scala 221:43]
|
|
wire [1:0] f0ictype = misc0eff[52:51]; // @[ifu_aln_ctl.scala 223:43]
|
|
wire [30:0] f0prett = misc0eff[50:20]; // @[ifu_aln_ctl.scala 224:43]
|
|
wire [11:0] f0poffset = misc0eff[19:8]; // @[ifu_aln_ctl.scala 225:43]
|
|
wire [7:0] f0fghr = misc0eff[7:0]; // @[ifu_aln_ctl.scala 226:43]
|
|
wire [31:0] _T_228 = {brdata1,brdata0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_231 = {brdata2,brdata1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_234 = {brdata0,brdata2}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_235 = qren[0] ? _T_228 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_236 = qren[1] ? _T_231 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_237 = qren[2] ? _T_234 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_238 = _T_235 | _T_236; // @[Mux.scala 27:72]
|
|
wire [31:0] brdataeff = _T_238 | _T_237; // @[Mux.scala 27:72]
|
|
wire [15:0] brdata1eff = brdataeff[31:16]; // @[ifu_aln_ctl.scala 254:26]
|
|
wire [15:0] brdata0eff = brdataeff[15:0]; // @[ifu_aln_ctl.scala 255:26]
|
|
wire [15:0] _T_249 = q0sel[0] ? brdata0eff : 16'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_250 = q0sel[1] ? brdata0eff[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _GEN_21 = {{8'd0}, _T_250}; // @[Mux.scala 27:72]
|
|
wire [15:0] brdata0final = _T_249 | _GEN_21; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_258 = q1sel[0] ? brdata1eff : 16'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_259 = q1sel[1] ? brdata1eff[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _GEN_22 = {{8'd0}, _T_259}; // @[Mux.scala 27:72]
|
|
wire [15:0] brdata1final = _T_258 | _GEN_22; // @[Mux.scala 27:72]
|
|
wire [1:0] f0ret = {brdata0final[8],brdata0final[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0brend = {brdata0final[9],brdata0final[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0way = {brdata0final[10],brdata0final[2]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0pc4 = {brdata0final[11],brdata0final[3]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0hist0 = {brdata0final[12],brdata0final[4]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0hist1 = {brdata0final[13],brdata0final[5]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0icaf = {brdata0final[14],brdata0final[6]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f0dbecc = {brdata0final[15],brdata0final[7]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1ret = {brdata1final[8],brdata1final[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1brend = {brdata1final[9],brdata1final[1]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1way = {brdata1final[10],brdata1final[2]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1pc4 = {brdata1final[11],brdata1final[3]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1hist0 = {brdata1final[12],brdata1final[4]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1hist1 = {brdata1final[13],brdata1final[5]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1icaf = {brdata1final[14],brdata1final[6]}; // @[Cat.scala 29:58]
|
|
wire [1:0] f1dbecc = {brdata1final[15],brdata1final[7]}; // @[Cat.scala 29:58]
|
|
wire consume_fb0 = _T_389 & f0val[0]; // @[ifu_aln_ctl.scala 328:32]
|
|
wire consume_fb1 = _T_360 & f1val[0]; // @[ifu_aln_ctl.scala 329:32]
|
|
wire _T_349 = ~consume_fb1; // @[ifu_aln_ctl.scala 332:39]
|
|
wire _T_350 = consume_fb0 & _T_349; // @[ifu_aln_ctl.scala 332:37]
|
|
wire _T_353 = consume_fb0 & consume_fb1; // @[ifu_aln_ctl.scala 333:37]
|
|
wire [61:0] _T_512 = {q1pc,q0pc}; // @[Cat.scala 29:58]
|
|
wire [61:0] _T_515 = {q2pc,q1pc}; // @[Cat.scala 29:58]
|
|
wire [61:0] _T_518 = {q0pc,q2pc}; // @[Cat.scala 29:58]
|
|
wire [61:0] _T_519 = qren[0] ? _T_512 : 62'h0; // @[Mux.scala 27:72]
|
|
wire [61:0] _T_520 = qren[1] ? _T_515 : 62'h0; // @[Mux.scala 27:72]
|
|
wire [61:0] _T_521 = qren[2] ? _T_518 : 62'h0; // @[Mux.scala 27:72]
|
|
wire [61:0] _T_522 = _T_519 | _T_520; // @[Mux.scala 27:72]
|
|
wire [61:0] qpceff = _T_522 | _T_521; // @[Mux.scala 27:72]
|
|
wire [30:0] q1pceff = qpceff[61:31]; // @[ifu_aln_ctl.scala 380:23]
|
|
wire [30:0] q0pceff = qpceff[30:0]; // @[ifu_aln_ctl.scala 381:23]
|
|
wire [30:0] _T_527 = q0pceff + 31'h1; // @[ifu_aln_ctl.scala 382:70]
|
|
wire [30:0] _T_528 = q0sel[0] ? q0pceff : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_529 = q0sel[1] ? _T_527 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] firstpc = _T_528 | _T_529; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_551 = {f1val[0],1'h1}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_552 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_553 = _T_536 ? _T_551 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignval = _T_552 | _T_553; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_565 = {f1icaf[0],f0icaf[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_566 = f0val[1] ? f0icaf : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_567 = _T_536 ? _T_565 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignicaf = _T_566 | _T_567; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_578 = {f1dbecc[0],f0dbecc[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_579 = f0val[1] ? f0dbecc : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_580 = _T_536 ? _T_578 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] aligndbecc = _T_579 | _T_580; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_591 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_592 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_593 = _T_536 ? _T_591 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignbrend = _T_592 | _T_593; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_604 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_605 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_606 = _T_536 ? _T_604 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignpc4 = _T_605 | _T_606; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_617 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_618 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_619 = _T_536 ? _T_617 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignret = _T_618 | _T_619; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_630 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_631 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_632 = _T_536 ? _T_630 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignway = _T_631 | _T_632; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_643 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_644 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_645 = _T_536 ? _T_643 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignhist1 = _T_644 | _T_645; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_656 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_657 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_658 = _T_536 ? _T_656 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] alignhist0 = _T_657 | _T_658; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_669 = f0val[1] ? _T_527 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_670 = _T_536 ? q1pceff : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] secondpc = _T_669 | _T_670; // @[Mux.scala 27:72]
|
|
wire _T_682 = first4B & alignval[1]; // @[Mux.scala 27:72]
|
|
wire _T_683 = first2B & alignval[0]; // @[Mux.scala 27:72]
|
|
wire _T_687 = |alignicaf; // @[ifu_aln_ctl.scala 432:74]
|
|
wire _T_690 = first4B & _T_687; // @[Mux.scala 27:72]
|
|
wire _T_691 = first2B & alignicaf[0]; // @[Mux.scala 27:72]
|
|
wire _T_696 = first4B & _T_534; // @[ifu_aln_ctl.scala 434:54]
|
|
wire _T_698 = _T_696 & f0val[0]; // @[ifu_aln_ctl.scala 434:66]
|
|
wire _T_700 = ~alignicaf[0]; // @[ifu_aln_ctl.scala 434:79]
|
|
wire _T_701 = _T_698 & _T_700; // @[ifu_aln_ctl.scala 434:77]
|
|
wire _T_703 = ~aligndbecc[0]; // @[ifu_aln_ctl.scala 434:95]
|
|
wire _T_704 = _T_701 & _T_703; // @[ifu_aln_ctl.scala 434:93]
|
|
wire [1:0] icaf_eff = alignicaf | aligndbecc; // @[ifu_aln_ctl.scala 436:28]
|
|
wire _T_708 = ~icaf_eff[0]; // @[ifu_aln_ctl.scala 438:53]
|
|
wire _T_709 = first4B & _T_708; // @[ifu_aln_ctl.scala 438:51]
|
|
wire _T_713 = |aligndbecc; // @[ifu_aln_ctl.scala 440:74]
|
|
wire _T_716 = first4B & _T_713; // @[Mux.scala 27:72]
|
|
wire _T_717 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_726 = _T_682 ? aligndata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_727 = _T_683 ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_732 = firstpc[8:1] ^ firstpc[16:9]; // @[lib.scala 57:47]
|
|
wire [7:0] firstpc_hash = _T_732 ^ firstpc[24:17]; // @[lib.scala 57:85]
|
|
wire [7:0] _T_736 = secondpc[8:1] ^ secondpc[16:9]; // @[lib.scala 57:47]
|
|
wire [7:0] secondpc_hash = _T_736 ^ secondpc[24:17]; // @[lib.scala 57:85]
|
|
wire [4:0] _T_742 = firstpc[13:9] ^ firstpc[18:14]; // @[lib.scala 48:111]
|
|
wire [4:0] firstbrtag_hash = _T_742 ^ firstpc[23:19]; // @[lib.scala 48:111]
|
|
wire [4:0] _T_748 = secondpc[13:9] ^ secondpc[18:14]; // @[lib.scala 48:111]
|
|
wire [4:0] secondbrtag_hash = _T_748 ^ secondpc[23:19]; // @[lib.scala 48:111]
|
|
wire _T_751 = first2B & alignbrend[0]; // @[ifu_aln_ctl.scala 462:48]
|
|
wire _T_753 = first4B & alignbrend[1]; // @[ifu_aln_ctl.scala 462:76]
|
|
wire _T_754 = _T_751 | _T_753; // @[ifu_aln_ctl.scala 462:65]
|
|
wire _T_758 = _T_682 & alignbrend[0]; // @[ifu_aln_ctl.scala 462:118]
|
|
wire _T_761 = first2B & alignpc4[0]; // @[ifu_aln_ctl.scala 464:31]
|
|
wire _T_763 = first4B & alignpc4[1]; // @[ifu_aln_ctl.scala 464:57]
|
|
wire _T_764 = _T_761 | _T_763; // @[ifu_aln_ctl.scala 464:46]
|
|
wire _T_766 = first2B & alignret[0]; // @[ifu_aln_ctl.scala 466:51]
|
|
wire _T_768 = first4B & alignret[1]; // @[ifu_aln_ctl.scala 466:77]
|
|
wire _T_771 = first2B | alignbrend[0]; // @[ifu_aln_ctl.scala 468:55]
|
|
wire _T_777 = first2B & alignhist1[0]; // @[ifu_aln_ctl.scala 470:56]
|
|
wire _T_779 = first4B & alignhist1[1]; // @[ifu_aln_ctl.scala 470:84]
|
|
wire _T_780 = _T_777 | _T_779; // @[ifu_aln_ctl.scala 470:73]
|
|
wire _T_782 = first2B & alignhist0[0]; // @[ifu_aln_ctl.scala 471:16]
|
|
wire _T_784 = first4B & alignhist0[1]; // @[ifu_aln_ctl.scala 471:44]
|
|
wire _T_785 = _T_782 | _T_784; // @[ifu_aln_ctl.scala 471:33]
|
|
wire _T_787 = first4B & _T_536; // @[ifu_aln_ctl.scala 473:30]
|
|
wire _T_802 = io_dec_aln_aln_ib_i0_brp_valid & _T_764; // @[ifu_aln_ctl.scala 482:79]
|
|
wire _T_803 = _T_802 & first2B; // @[ifu_aln_ctl.scala 482:93]
|
|
wire _T_804 = ~_T_764; // @[ifu_aln_ctl.scala 482:141]
|
|
wire _T_805 = io_dec_aln_aln_ib_i0_brp_valid & _T_804; // @[ifu_aln_ctl.scala 482:139]
|
|
wire _T_806 = _T_805 & first4B; // @[ifu_aln_ctl.scala 482:153]
|
|
wire [31:0] _T_820 = first2B ? aligndata : 32'h0; // @[ifu_aln_ctl.scala 502:29]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
ifu_compress_ctl decompressed ( // @[ifu_aln_ctl.scala 444:28]
|
|
.io_din(decompressed_io_din),
|
|
.io_dout(decompressed_io_dout)
|
|
);
|
|
assign io_dec_aln_aln_dec_ifu_i0_cinst = aligndata[15:0]; // @[ifu_aln_ctl.scala 423:35]
|
|
assign io_dec_aln_aln_ib_ifu_i0_icaf = _T_690 | _T_691; // @[ifu_aln_ctl.scala 432:33]
|
|
assign io_dec_aln_aln_ib_ifu_i0_icaf_type = _T_704 ? f1ictype : f0ictype; // @[ifu_aln_ctl.scala 434:38]
|
|
assign io_dec_aln_aln_ib_ifu_i0_icaf_second = _T_709 & icaf_eff[1]; // @[ifu_aln_ctl.scala 438:40]
|
|
assign io_dec_aln_aln_ib_ifu_i0_dbecc = _T_716 | _T_717; // @[ifu_aln_ctl.scala 440:34]
|
|
assign io_dec_aln_aln_ib_ifu_i0_bp_index = _T_771 ? firstpc_hash : secondpc_hash; // @[ifu_aln_ctl.scala 484:39]
|
|
assign io_dec_aln_aln_ib_ifu_i0_bp_fghr = _T_787 ? f1fghr : f0fghr; // @[ifu_aln_ctl.scala 485:38]
|
|
assign io_dec_aln_aln_ib_ifu_i0_bp_btag = _T_771 ? firstbrtag_hash : secondbrtag_hash; // @[ifu_aln_ctl.scala 486:38]
|
|
assign io_dec_aln_aln_ib_ifu_i0_valid = _T_682 | _T_683; // @[ifu_aln_ctl.scala 430:34]
|
|
assign io_dec_aln_aln_ib_ifu_i0_instr = _T_726 | _T_727; // @[ifu_aln_ctl.scala 446:34]
|
|
assign io_dec_aln_aln_ib_ifu_i0_pc = _T_528 | _T_529; // @[ifu_aln_ctl.scala 419:31]
|
|
assign io_dec_aln_aln_ib_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 421:32]
|
|
assign io_dec_aln_aln_ib_i0_brp_valid = _T_754 | _T_758; // @[ifu_aln_ctl.scala 462:36]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_toffset = _T_787 ? f1poffset : f0poffset; // @[ifu_aln_ctl.scala 474:43]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_hist = {_T_780,_T_785}; // @[ifu_aln_ctl.scala 470:40]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_br_error = _T_803 | _T_806; // @[ifu_aln_ctl.scala 482:44]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_br_start_error = _T_682 & alignbrend[0]; // @[ifu_aln_ctl.scala 478:51]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_prett = _T_787 ? f1prett : f0prett; // @[ifu_aln_ctl.scala 476:41]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_way = _T_771 ? alignway[0] : alignway[1]; // @[ifu_aln_ctl.scala 468:39]
|
|
assign io_dec_aln_aln_ib_i0_brp_bits_ret = _T_766 | _T_768; // @[ifu_aln_ctl.scala 466:39]
|
|
assign io_dec_aln_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_821; // @[ifu_aln_ctl.scala 506:36]
|
|
assign io_ifu_fb_consume1 = _T_350 & _T_1; // @[ifu_aln_ctl.scala 332:22]
|
|
assign io_ifu_fb_consume2 = _T_353 & _T_1; // @[ifu_aln_ctl.scala 333:22]
|
|
assign rvclkhdr_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = qwen[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = qwen[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = qwen[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = qwen[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = qwen[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = qwen[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = qwen[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = qwen[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = qwen[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = qwen[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = qwen[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = qwen[0]; // @[lib.scala 425:17]
|
|
assign decompressed_io_din = _T_820[15:0]; // @[ifu_aln_ctl.scala 502:23]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
error_stall = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
wrptr = _RAND_1[1:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
rdptr = _RAND_2[1:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
q2off = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
q1off = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
q0off = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
f0val = _RAND_6[1:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
q1 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
q0 = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
q2 = _RAND_9[31:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
f1val = _RAND_10[1:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
f2val = _RAND_11[1:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
brdata2 = _RAND_12[15:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
brdata1 = _RAND_13[15:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
brdata0 = _RAND_14[15:0];
|
|
_RAND_15 = {2{`RANDOM}};
|
|
misc2 = _RAND_15[52:0];
|
|
_RAND_16 = {2{`RANDOM}};
|
|
misc1 = _RAND_16[52:0];
|
|
_RAND_17 = {2{`RANDOM}};
|
|
misc0 = _RAND_17[52:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
q2pc = _RAND_18[30:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
q1pc = _RAND_19[30:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
q0pc = _RAND_20[30:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
error_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrptr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
rdptr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
q2off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q1off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
q0off = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
f0val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
q1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
q0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
q2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
f1val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
f2val = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata2 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata1 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
brdata0 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
misc2 = 53'h0;
|
|
end
|
|
if (reset) begin
|
|
misc1 = 53'h0;
|
|
end
|
|
if (reset) begin
|
|
misc0 = 53'h0;
|
|
end
|
|
if (reset) begin
|
|
q2pc = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
q1pc = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
q0pc = 31'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
error_stall <= 1'h0;
|
|
end else if (_T_4) begin
|
|
error_stall <= error_stall_in;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
wrptr <= 2'h0;
|
|
end else begin
|
|
wrptr <= _T_118 | _T_117;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
rdptr <= 2'h0;
|
|
end else begin
|
|
rdptr <= _T_95 | _T_90;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q2off <= 1'h0;
|
|
end else begin
|
|
q2off <= _T_142 | _T_141;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q1off <= 1'h0;
|
|
end else begin
|
|
q1off <= _T_165 | _T_164;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
q0off <= 1'h0;
|
|
end else begin
|
|
q0off <= _T_188 | _T_187;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
f0val <= 2'h0;
|
|
end else if (_T_13) begin
|
|
f0val <= f0val_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q1 <= 32'h0;
|
|
end else if (qwen[1]) begin
|
|
q1 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q0 <= 32'h0;
|
|
end else if (qwen[0]) begin
|
|
q0 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q2 <= 32'h0;
|
|
end else if (qwen[2]) begin
|
|
q2 <= io_ifu_fetch_data_f;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
f1val <= 2'h0;
|
|
end else if (_T_10) begin
|
|
f1val <= f1val_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
f2val <= 2'h0;
|
|
end else if (_T_7) begin
|
|
f2val <= f2val_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata2 <= 16'h0;
|
|
end else if (qwen[2]) begin
|
|
brdata2 <= brdata_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata1 <= 16'h0;
|
|
end else if (qwen[1]) begin
|
|
brdata1 <= brdata_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
brdata0 <= 16'h0;
|
|
end else if (qwen[0]) begin
|
|
brdata0 <= brdata_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc2 <= 53'h0;
|
|
end else if (qwen[2]) begin
|
|
misc2 <= misc_data_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc1 <= 53'h0;
|
|
end else if (qwen[1]) begin
|
|
misc1 <= misc_data_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
misc0 <= 53'h0;
|
|
end else if (qwen[0]) begin
|
|
misc0 <= misc_data_in;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q2pc <= 31'h0;
|
|
end else if (qwen[2]) begin
|
|
q2pc <= io_ifu_fetch_pc;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q1pc <= 31'h0;
|
|
end else if (qwen[1]) begin
|
|
q1pc <= io_ifu_fetch_pc;
|
|
end
|
|
end
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
q0pc <= 31'h0;
|
|
end else if (qwen[0]) begin
|
|
q0pc <= io_ifu_fetch_pc;
|
|
end
|
|
end
|
|
endmodule
|
|
module ifu_ifc_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_exu_flush_path_final,
|
|
input io_free_l2clk,
|
|
input io_ic_hit_f,
|
|
input io_ifu_ic_mb_empty,
|
|
input io_ifu_fb_consume1,
|
|
input io_ifu_fb_consume2,
|
|
input io_ifu_bp_hit_taken_f,
|
|
input [30:0] io_ifu_bp_btb_target_f,
|
|
input io_ic_dma_active,
|
|
input io_ic_write_stall,
|
|
input io_dec_ifc_dec_tlu_flush_noredir_wb,
|
|
input [31:0] io_dec_ifc_dec_tlu_mrac_ff,
|
|
output io_dec_ifc_ifu_pmu_fetch_stall,
|
|
input io_dma_ifc_dma_iccm_stall_any,
|
|
output [30:0] io_ifc_fetch_addr_f,
|
|
output [30:0] io_ifc_fetch_addr_bf,
|
|
output io_ifc_fetch_req_f,
|
|
output io_ifc_fetch_uncacheable_bf,
|
|
output io_ifc_fetch_req_bf,
|
|
output io_ifc_fetch_req_bf_raw,
|
|
output io_ifc_iccm_access_bf,
|
|
output io_ifc_region_acc_fault_bf,
|
|
output io_ifc_dma_access_ok
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
reg dma_iccm_stall_any_f; // @[Reg.scala 27:20]
|
|
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 62:36]
|
|
wire _T_1 = io_dma_ifc_dma_iccm_stall_any ^ dma_iccm_stall_any_f; // @[lib.scala 488:21]
|
|
wire _T_2 = |_T_1; // @[lib.scala 488:29]
|
|
wire _T_56 = ~io_ic_hit_f; // @[ifu_ifc_ctl.scala 97:34]
|
|
wire _T_57 = io_ifc_fetch_req_f & _T_56; // @[ifu_ifc_ctl.scala 97:32]
|
|
wire _T_58 = ~io_exu_flush_final; // @[ifu_ifc_ctl.scala 97:49]
|
|
wire miss_f = _T_57 & _T_58; // @[ifu_ifc_ctl.scala 97:47]
|
|
reg miss_a; // @[Reg.scala 27:20]
|
|
wire _T_5 = miss_f ^ miss_a; // @[lib.scala 466:21]
|
|
wire _T_6 = |_T_5; // @[lib.scala 466:29]
|
|
wire _T_9 = ~io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 67:51]
|
|
wire _T_11 = _T_9 | _T_56; // @[ifu_ifc_ctl.scala 67:71]
|
|
wire _T_12 = _T_58 & _T_11; // @[ifu_ifc_ctl.scala 67:48]
|
|
wire _T_14 = _T_58 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 68:47]
|
|
wire _T_15 = _T_14 & io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 68:68]
|
|
wire _T_16 = _T_15 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 68:92]
|
|
wire _T_19 = ~io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 69:71]
|
|
wire _T_20 = _T_14 & _T_19; // @[ifu_ifc_ctl.scala 69:69]
|
|
wire _T_21 = _T_20 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 69:94]
|
|
wire [30:0] _T_26 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_27 = _T_12 ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_28 = _T_16 ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_ifc_ctl.scala 84:48]
|
|
wire _T_38 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[ifu_ifc_ctl.scala 85:63]
|
|
wire _T_39 = ~_T_38; // @[ifu_ifc_ctl.scala 85:24]
|
|
wire fetch_addr_next_0 = _T_39 & io_ifc_fetch_addr_f[0]; // @[ifu_ifc_ctl.scala 85:109]
|
|
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_29 = _T_21 ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_30 = _T_26 | _T_27; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_31 = _T_30 | _T_28; // @[Mux.scala 27:72]
|
|
reg [1:0] state; // @[Reg.scala 27:20]
|
|
wire idle = state == 2'h0; // @[ifu_ifc_ctl.scala 129:17]
|
|
wire _T_44 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[ifu_ifc_ctl.scala 92:91]
|
|
wire _T_45 = ~_T_44; // @[ifu_ifc_ctl.scala 92:70]
|
|
wire [3:0] _T_133 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire _T_93 = ~io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 115:38]
|
|
wire _T_94 = io_ifu_fb_consume1 & _T_93; // @[ifu_ifc_ctl.scala 115:36]
|
|
wire _T_96 = _T_9 | miss_f; // @[ifu_ifc_ctl.scala 115:81]
|
|
wire _T_97 = _T_94 & _T_96; // @[ifu_ifc_ctl.scala 115:58]
|
|
wire _T_98 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 116:25]
|
|
wire fb_right = _T_97 | _T_98; // @[ifu_ifc_ctl.scala 115:92]
|
|
wire _T_110 = _T_58 & fb_right; // @[ifu_ifc_ctl.scala 123:16]
|
|
reg [3:0] fb_write_f; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_113 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_134 = _T_110 ? _T_113 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_138 = _T_133 | _T_134; // @[Mux.scala 27:72]
|
|
wire fb_right2 = io_ifu_fb_consume2 & _T_96; // @[ifu_ifc_ctl.scala 118:36]
|
|
wire _T_115 = _T_58 & fb_right2; // @[ifu_ifc_ctl.scala 124:16]
|
|
wire [3:0] _T_118 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_135 = _T_115 ? _T_118 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_139 = _T_138 | _T_135; // @[Mux.scala 27:72]
|
|
wire _T_103 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 119:56]
|
|
wire _T_104 = ~_T_103; // @[ifu_ifc_ctl.scala 119:35]
|
|
wire _T_105 = io_ifc_fetch_req_f & _T_104; // @[ifu_ifc_ctl.scala 119:33]
|
|
wire _T_106 = ~miss_f; // @[ifu_ifc_ctl.scala 119:80]
|
|
wire fb_left = _T_105 & _T_106; // @[ifu_ifc_ctl.scala 119:78]
|
|
wire _T_120 = _T_58 & fb_left; // @[ifu_ifc_ctl.scala 125:16]
|
|
wire [3:0] _T_123 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_136 = _T_120 ? _T_123 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_140 = _T_139 | _T_136; // @[Mux.scala 27:72]
|
|
wire _T_125 = ~fb_right; // @[ifu_ifc_ctl.scala 126:18]
|
|
wire _T_126 = _T_58 & _T_125; // @[ifu_ifc_ctl.scala 126:16]
|
|
wire _T_127 = ~fb_right2; // @[ifu_ifc_ctl.scala 126:30]
|
|
wire _T_128 = _T_126 & _T_127; // @[ifu_ifc_ctl.scala 126:28]
|
|
wire _T_129 = ~fb_left; // @[ifu_ifc_ctl.scala 126:43]
|
|
wire _T_130 = _T_128 & _T_129; // @[ifu_ifc_ctl.scala 126:41]
|
|
wire [3:0] _T_137 = _T_130 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] fb_write_ns = _T_140 | _T_137; // @[Mux.scala 27:72]
|
|
wire fb_full_f_ns = fb_write_ns[3]; // @[ifu_ifc_ctl.scala 132:30]
|
|
wire _T_46 = fb_full_f_ns & _T_45; // @[ifu_ifc_ctl.scala 92:68]
|
|
wire _T_47 = ~_T_46; // @[ifu_ifc_ctl.scala 92:53]
|
|
wire _T_48 = io_ifc_fetch_req_bf_raw & _T_47; // @[ifu_ifc_ctl.scala 92:51]
|
|
wire _T_49 = ~dma_stall; // @[ifu_ifc_ctl.scala 93:5]
|
|
wire _T_50 = _T_48 & _T_49; // @[ifu_ifc_ctl.scala 92:114]
|
|
wire _T_51 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 93:18]
|
|
wire _T_52 = _T_50 & _T_51; // @[ifu_ifc_ctl.scala 93:16]
|
|
wire _T_53 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 93:39]
|
|
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 95:37]
|
|
wire _T_60 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 99:39]
|
|
wire _T_62 = _T_60 & _T_49; // @[ifu_ifc_ctl.scala 99:61]
|
|
wire _T_64 = _T_62 & _T_106; // @[ifu_ifc_ctl.scala 99:74]
|
|
wire _T_65 = ~miss_a; // @[ifu_ifc_ctl.scala 99:86]
|
|
wire mb_empty_mod = _T_64 & _T_65; // @[ifu_ifc_ctl.scala 99:84]
|
|
wire goto_idle = io_exu_flush_final & io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 101:35]
|
|
wire _T_69 = io_exu_flush_final & _T_53; // @[ifu_ifc_ctl.scala 103:36]
|
|
wire leave_idle = _T_69 & idle; // @[ifu_ifc_ctl.scala 103:75]
|
|
wire _T_72 = ~state[1]; // @[ifu_ifc_ctl.scala 105:23]
|
|
wire _T_74 = _T_72 & state[0]; // @[ifu_ifc_ctl.scala 105:33]
|
|
wire _T_75 = _T_74 & miss_f; // @[ifu_ifc_ctl.scala 105:44]
|
|
wire _T_76 = ~goto_idle; // @[ifu_ifc_ctl.scala 105:55]
|
|
wire _T_77 = _T_75 & _T_76; // @[ifu_ifc_ctl.scala 105:53]
|
|
wire _T_79 = ~mb_empty_mod; // @[ifu_ifc_ctl.scala 106:17]
|
|
wire _T_80 = state[1] & _T_79; // @[ifu_ifc_ctl.scala 106:15]
|
|
wire _T_82 = _T_80 & _T_76; // @[ifu_ifc_ctl.scala 106:31]
|
|
wire next_state_1 = _T_77 | _T_82; // @[ifu_ifc_ctl.scala 105:67]
|
|
wire _T_84 = _T_76 & leave_idle; // @[ifu_ifc_ctl.scala 108:34]
|
|
wire _T_87 = state[0] & _T_76; // @[ifu_ifc_ctl.scala 108:60]
|
|
wire next_state_0 = _T_84 | _T_87; // @[ifu_ifc_ctl.scala 108:48]
|
|
wire [1:0] _T_88 = {next_state_1,next_state_0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_90 = _T_88 ^ state; // @[lib.scala 466:21]
|
|
wire _T_91 = |_T_90; // @[lib.scala 466:29]
|
|
wire wfm = state == 2'h3; // @[ifu_ifc_ctl.scala 130:16]
|
|
reg fb_full_f; // @[Reg.scala 27:20]
|
|
wire _T_146 = fb_full_f_ns ^ fb_full_f; // @[lib.scala 466:21]
|
|
wire _T_147 = |_T_146; // @[lib.scala 466:29]
|
|
wire [3:0] _T_150 = fb_write_ns ^ fb_write_f; // @[lib.scala 466:21]
|
|
wire _T_151 = |_T_150; // @[lib.scala 466:29]
|
|
wire _T_154 = _T_44 | io_exu_flush_final; // @[ifu_ifc_ctl.scala 137:61]
|
|
wire _T_155 = ~_T_154; // @[ifu_ifc_ctl.scala 137:19]
|
|
wire _T_156 = fb_full_f & _T_155; // @[ifu_ifc_ctl.scala 137:17]
|
|
wire _T_157 = _T_156 | dma_stall; // @[ifu_ifc_ctl.scala 137:84]
|
|
wire _T_158 = io_ifc_fetch_req_bf_raw & _T_157; // @[ifu_ifc_ctl.scala 136:68]
|
|
wire [31:0] _T_160 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
|
wire iccm_acc_in_region_bf = _T_160[31:28] == 4'he; // @[lib.scala 90:47]
|
|
wire iccm_acc_in_range_bf = _T_160[31:16] == 16'hee00; // @[lib.scala 93:29]
|
|
wire _T_163 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 143:30]
|
|
wire _T_166 = fb_full_f & _T_45; // @[ifu_ifc_ctl.scala 144:16]
|
|
wire _T_167 = _T_163 | _T_166; // @[ifu_ifc_ctl.scala 143:53]
|
|
wire _T_168 = ~io_ifc_fetch_req_bf; // @[ifu_ifc_ctl.scala 145:13]
|
|
wire _T_169 = wfm & _T_168; // @[ifu_ifc_ctl.scala 145:11]
|
|
wire _T_170 = _T_167 | _T_169; // @[ifu_ifc_ctl.scala 144:62]
|
|
wire _T_171 = _T_170 | idle; // @[ifu_ifc_ctl.scala 145:35]
|
|
wire _T_173 = _T_171 & _T_58; // @[ifu_ifc_ctl.scala 145:44]
|
|
wire _T_175 = ~iccm_acc_in_range_bf; // @[ifu_ifc_ctl.scala 147:33]
|
|
wire [4:0] _T_178 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_179 = io_dec_ifc_dec_tlu_mrac_ff >> _T_178; // @[ifu_ifc_ctl.scala 148:61]
|
|
reg _T_185; // @[Reg.scala 27:20]
|
|
wire _T_183 = io_ifc_fetch_req_bf ^ _T_185; // @[lib.scala 488:21]
|
|
wire _T_184 = |_T_183; // @[lib.scala 488:29]
|
|
reg [30:0] _T_188; // @[Reg.scala 27:20]
|
|
assign io_dec_ifc_ifu_pmu_fetch_stall = wfm | _T_158; // @[ifu_ifc_ctl.scala 136:34]
|
|
assign io_ifc_fetch_addr_f = _T_188; // @[ifu_ifc_ctl.scala 152:23]
|
|
assign io_ifc_fetch_addr_bf = _T_31 | _T_29; // @[ifu_ifc_ctl.scala 71:26]
|
|
assign io_ifc_fetch_req_f = _T_185; // @[ifu_ifc_ctl.scala 150:22]
|
|
assign io_ifc_fetch_uncacheable_bf = ~_T_179[0]; // @[ifu_ifc_ctl.scala 148:31]
|
|
assign io_ifc_fetch_req_bf = _T_52 & _T_53; // @[ifu_ifc_ctl.scala 92:23]
|
|
assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 90:27]
|
|
assign io_ifc_iccm_access_bf = _T_160[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 142:25]
|
|
assign io_ifc_region_acc_fault_bf = _T_175 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 147:30]
|
|
assign io_ifc_dma_access_ok = _T_173 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 143:24]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dma_iccm_stall_any_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
miss_a = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
state = _RAND_2[1:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
fb_write_f = _RAND_3[3:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
fb_full_f = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_185 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_188 = _RAND_6[30:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
dma_iccm_stall_any_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
miss_a = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
state = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fb_write_f = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
fb_full_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_185 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_188 = 31'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_iccm_stall_any_f <= 1'h0;
|
|
end else if (_T_2) begin
|
|
dma_iccm_stall_any_f <= io_dma_ifc_dma_iccm_stall_any;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
miss_a <= 1'h0;
|
|
end else if (_T_6) begin
|
|
miss_a <= miss_f;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
state <= 2'h0;
|
|
end else if (_T_91) begin
|
|
state <= _T_88;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
fb_write_f <= 4'h0;
|
|
end else if (_T_151) begin
|
|
fb_write_f <= fb_write_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
fb_full_f <= 1'h0;
|
|
end else if (_T_147) begin
|
|
fb_full_f <= fb_full_f_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_185 <= 1'h0;
|
|
end else if (_T_184) begin
|
|
_T_185 <= io_ifc_fetch_req_bf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_188 <= 31'h0;
|
|
end else if (fetch_bf_en) begin
|
|
_T_188 <= io_ifc_fetch_addr_bf;
|
|
end
|
|
end
|
|
endmodule
|
|
module ifu(
|
|
input clock,
|
|
input reset,
|
|
input io_dec_i0_decode_d,
|
|
input io_exu_flush_final,
|
|
input [30:0] io_exu_flush_path_final,
|
|
input io_free_l2clk,
|
|
input io_active_clk,
|
|
output [15:0] io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst,
|
|
output io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf,
|
|
output [1:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type,
|
|
output io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second,
|
|
output io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc,
|
|
output [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index,
|
|
output [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr,
|
|
output [4:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag,
|
|
output io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid,
|
|
output [31:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr,
|
|
output [30:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc,
|
|
output io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4,
|
|
output io_ifu_dec_dec_aln_aln_ib_i0_brp_valid,
|
|
output [11:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset,
|
|
output [1:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist,
|
|
output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error,
|
|
output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error,
|
|
output [30:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett,
|
|
output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way,
|
|
output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret,
|
|
output io_ifu_dec_dec_aln_ifu_pmu_instr_aligned,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb,
|
|
input [70:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
input [16:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
input io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
|
|
output [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid,
|
|
output io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle,
|
|
input io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb,
|
|
input [31:0] io_ifu_dec_dec_ifc_dec_tlu_mrac_ff,
|
|
output io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall,
|
|
input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid,
|
|
input [1:0] io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist,
|
|
input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error,
|
|
input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error,
|
|
input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way,
|
|
input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle,
|
|
input io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb,
|
|
input io_ifu_dec_dec_bp_dec_tlu_bpred_disable,
|
|
input [7:0] io_exu_ifu_exu_bp_exu_i0_br_index_r,
|
|
input [7:0] io_exu_ifu_exu_bp_exu_i0_br_fghr_r,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_valid,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4,
|
|
input [1:0] io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist,
|
|
input [11:0] io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_way,
|
|
input io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret,
|
|
input [7:0] io_exu_ifu_exu_bp_exu_mp_eghr,
|
|
input [7:0] io_exu_ifu_exu_bp_exu_mp_fghr,
|
|
input [7:0] io_exu_ifu_exu_bp_exu_mp_index,
|
|
input [4:0] io_exu_ifu_exu_bp_exu_mp_btag,
|
|
output [14:0] io_iccm_rw_addr,
|
|
output io_iccm_buf_correct_ecc,
|
|
output io_iccm_correction_state,
|
|
output io_iccm_wren,
|
|
output io_iccm_rden,
|
|
output [2:0] io_iccm_wr_size,
|
|
output [77:0] io_iccm_wr_data,
|
|
input [63:0] io_iccm_rd_data,
|
|
input [77:0] io_iccm_rd_data_ecc,
|
|
output [30:0] io_ic_rw_addr,
|
|
output [1:0] io_ic_tag_valid,
|
|
output [1:0] io_ic_wr_en,
|
|
output io_ic_rd_en,
|
|
output [70:0] io_ic_wr_data_0,
|
|
output [70:0] io_ic_wr_data_1,
|
|
output [70:0] io_ic_debug_wr_data,
|
|
output [9:0] io_ic_debug_addr,
|
|
input [63:0] io_ic_rd_data,
|
|
input [70:0] io_ic_debug_rd_data,
|
|
input [25:0] io_ic_tag_debug_rd_data,
|
|
input [1:0] io_ic_eccerr,
|
|
input [1:0] io_ic_rd_hit,
|
|
input io_ic_tag_perr,
|
|
output io_ic_debug_rd_en,
|
|
output io_ic_debug_wr_en,
|
|
output io_ic_debug_tag_array,
|
|
output [1:0] io_ic_debug_way,
|
|
output [63:0] io_ic_premux_data,
|
|
output io_ic_sel_premux_data,
|
|
input io_ifu_ar_ready,
|
|
output io_ifu_ar_valid,
|
|
output [2:0] io_ifu_ar_bits_id,
|
|
output [31:0] io_ifu_ar_bits_addr,
|
|
output [3:0] io_ifu_ar_bits_region,
|
|
input io_ifu_r_valid,
|
|
input [2:0] io_ifu_r_bits_id,
|
|
input [63:0] io_ifu_r_bits_data,
|
|
input [1:0] io_ifu_r_bits_resp,
|
|
input io_ifu_bus_clk_en,
|
|
input io_ifu_dma_dma_ifc_dma_iccm_stall_any,
|
|
input io_ifu_dma_dma_mem_ctl_dma_iccm_req,
|
|
input [31:0] io_ifu_dma_dma_mem_ctl_dma_mem_addr,
|
|
input [2:0] io_ifu_dma_dma_mem_ctl_dma_mem_sz,
|
|
input io_ifu_dma_dma_mem_ctl_dma_mem_write,
|
|
input [63:0] io_ifu_dma_dma_mem_ctl_dma_mem_wdata,
|
|
input [2:0] io_ifu_dma_dma_mem_ctl_dma_mem_tag,
|
|
output io_iccm_dma_ecc_error,
|
|
output io_iccm_dma_rvalid,
|
|
output [63:0] io_iccm_dma_rdata,
|
|
output [2:0] io_iccm_dma_rtag,
|
|
output io_iccm_ready,
|
|
output io_iccm_dma_sb_error,
|
|
input io_dec_tlu_flush_lower_wb
|
|
);
|
|
wire mem_ctl_clock; // @[ifu.scala 39:23]
|
|
wire mem_ctl_reset; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_free_l2clk; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_active_clk; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_exu_flush_final; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 39:23]
|
|
wire [16:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 39:23]
|
|
wire [30:0] mem_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 39:23]
|
|
wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 39:23]
|
|
wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 39:23]
|
|
wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dma_mem_ctl_dma_mem_write; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 39:23]
|
|
wire [14:0] mem_ctl_io_iccm_rw_addr; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_correction_state; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_wren; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_rden; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_iccm_wr_size; // @[ifu.scala 39:23]
|
|
wire [77:0] mem_ctl_io_iccm_wr_data; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_iccm_rd_data; // @[ifu.scala 39:23]
|
|
wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 39:23]
|
|
wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_rd_en; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 39:23]
|
|
wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 39:23]
|
|
wire [70:0] mem_ctl_io_ic_debug_rd_data; // @[ifu.scala 39:23]
|
|
wire [25:0] mem_ctl_io_ic_tag_debug_rd_data; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_eccerr; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_rd_hit; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_tag_perr; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_debug_way; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_ic_premux_data; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_dma_active; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_write_stall; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 39:23]
|
|
wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 39:23]
|
|
wire [2:0] mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_ready; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ic_hit_f; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_access_fault_f; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 39:23]
|
|
wire mem_ctl_io_ifu_async_error_start; // @[ifu.scala 39:23]
|
|
wire [1:0] mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 39:23]
|
|
wire [31:0] mem_ctl_io_ic_data_f; // @[ifu.scala 39:23]
|
|
wire bp_ctl_clock; // @[ifu.scala 40:22]
|
|
wire bp_ctl_reset; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_ic_hit_f; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_flush_final; // @[ifu.scala 40:22]
|
|
wire [30:0] bp_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_ifc_fetch_req_f; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_index_r; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_valid; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 40:22]
|
|
wire [11:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_exu_bp_exu_mp_eghr; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_exu_bp_exu_mp_fghr; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_exu_bp_exu_mp_index; // @[ifu.scala 40:22]
|
|
wire [4:0] bp_ctl_io_exu_bp_exu_mp_btag; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 40:22]
|
|
wire [30:0] bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 40:22]
|
|
wire bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 40:22]
|
|
wire [7:0] bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 40:22]
|
|
wire [1:0] bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 40:22]
|
|
wire [11:0] bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 40:22]
|
|
wire aln_ctl_clk; // @[ifu.scala 41:23]
|
|
wire aln_ctl_reset; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_active_clk; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_ifu_async_error_start; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ic_access_fault_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ic_access_fault_type_f; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_i0_decode_d; // @[ifu.scala 41:23]
|
|
wire [15:0] aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_second; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 41:23]
|
|
wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 41:23]
|
|
wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 41:23]
|
|
wire [4:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 41:23]
|
|
wire [31:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 41:23]
|
|
wire [30:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 41:23]
|
|
wire [11:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 41:23]
|
|
wire [30:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 41:23]
|
|
wire [7:0] aln_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 41:23]
|
|
wire [30:0] aln_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 41:23]
|
|
wire [11:0] aln_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_way_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_valid_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_bp_ret_f; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_exu_flush_final; // @[ifu.scala 41:23]
|
|
wire [31:0] aln_ctl_io_ifu_fetch_data_f; // @[ifu.scala 41:23]
|
|
wire [1:0] aln_ctl_io_ifu_fetch_val; // @[ifu.scala 41:23]
|
|
wire [30:0] aln_ctl_io_ifu_fetch_pc; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 41:23]
|
|
wire aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 41:23]
|
|
wire ifc_ctl_clock; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_reset; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_exu_flush_final; // @[ifu.scala 42:23]
|
|
wire [30:0] ifc_ctl_io_exu_flush_path_final; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_free_l2clk; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ic_hit_f; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifu_fb_consume1; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifu_fb_consume2; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 42:23]
|
|
wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ic_dma_active; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ic_write_stall; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 42:23]
|
|
wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 42:23]
|
|
wire [30:0] ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 42:23]
|
|
wire [30:0] ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 42:23]
|
|
wire ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 42:23]
|
|
ifu_mem_ctl mem_ctl ( // @[ifu.scala 39:23]
|
|
.clock(mem_ctl_clock),
|
|
.reset(mem_ctl_reset),
|
|
.io_free_l2clk(mem_ctl_io_free_l2clk),
|
|
.io_active_clk(mem_ctl_io_active_clk),
|
|
.io_exu_flush_final(mem_ctl_io_exu_flush_final),
|
|
.io_dec_mem_ctrl_dec_tlu_flush_err_wb(mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb),
|
|
.io_dec_mem_ctrl_dec_tlu_i0_commit_cmt(mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt),
|
|
.io_dec_mem_ctrl_dec_tlu_force_halt(mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt),
|
|
.io_dec_mem_ctrl_dec_tlu_fence_i_wb(mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb),
|
|
.io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata(mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics(mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid(mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid(mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_dec_mem_ctrl_dec_tlu_core_ecc_disable(mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable),
|
|
.io_dec_mem_ctrl_ifu_pmu_ic_miss(mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss),
|
|
.io_dec_mem_ctrl_ifu_pmu_ic_hit(mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit),
|
|
.io_dec_mem_ctrl_ifu_pmu_bus_error(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error),
|
|
.io_dec_mem_ctrl_ifu_pmu_bus_busy(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy),
|
|
.io_dec_mem_ctrl_ifu_pmu_bus_trxn(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn),
|
|
.io_dec_mem_ctrl_ifu_ic_error_start(mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start),
|
|
.io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
|
|
.io_dec_mem_ctrl_ifu_ic_debug_rd_data(mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data),
|
|
.io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid(mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid),
|
|
.io_dec_mem_ctrl_ifu_miss_state_idle(mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle),
|
|
.io_ifc_fetch_addr_bf(mem_ctl_io_ifc_fetch_addr_bf),
|
|
.io_ifc_fetch_uncacheable_bf(mem_ctl_io_ifc_fetch_uncacheable_bf),
|
|
.io_ifc_fetch_req_bf(mem_ctl_io_ifc_fetch_req_bf),
|
|
.io_ifc_fetch_req_bf_raw(mem_ctl_io_ifc_fetch_req_bf_raw),
|
|
.io_ifc_iccm_access_bf(mem_ctl_io_ifc_iccm_access_bf),
|
|
.io_ifc_region_acc_fault_bf(mem_ctl_io_ifc_region_acc_fault_bf),
|
|
.io_ifc_dma_access_ok(mem_ctl_io_ifc_dma_access_ok),
|
|
.io_ifu_bp_hit_taken_f(mem_ctl_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_inst_mask_f(mem_ctl_io_ifu_bp_inst_mask_f),
|
|
.io_ifu_axi_ar_ready(mem_ctl_io_ifu_axi_ar_ready),
|
|
.io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid),
|
|
.io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id),
|
|
.io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr),
|
|
.io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region),
|
|
.io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready),
|
|
.io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid),
|
|
.io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id),
|
|
.io_ifu_axi_r_bits_data(mem_ctl_io_ifu_axi_r_bits_data),
|
|
.io_ifu_axi_r_bits_resp(mem_ctl_io_ifu_axi_r_bits_resp),
|
|
.io_ifu_bus_clk_en(mem_ctl_io_ifu_bus_clk_en),
|
|
.io_dma_mem_ctl_dma_iccm_req(mem_ctl_io_dma_mem_ctl_dma_iccm_req),
|
|
.io_dma_mem_ctl_dma_mem_addr(mem_ctl_io_dma_mem_ctl_dma_mem_addr),
|
|
.io_dma_mem_ctl_dma_mem_sz(mem_ctl_io_dma_mem_ctl_dma_mem_sz),
|
|
.io_dma_mem_ctl_dma_mem_write(mem_ctl_io_dma_mem_ctl_dma_mem_write),
|
|
.io_dma_mem_ctl_dma_mem_wdata(mem_ctl_io_dma_mem_ctl_dma_mem_wdata),
|
|
.io_dma_mem_ctl_dma_mem_tag(mem_ctl_io_dma_mem_ctl_dma_mem_tag),
|
|
.io_iccm_rw_addr(mem_ctl_io_iccm_rw_addr),
|
|
.io_iccm_buf_correct_ecc(mem_ctl_io_iccm_buf_correct_ecc),
|
|
.io_iccm_correction_state(mem_ctl_io_iccm_correction_state),
|
|
.io_iccm_wren(mem_ctl_io_iccm_wren),
|
|
.io_iccm_rden(mem_ctl_io_iccm_rden),
|
|
.io_iccm_wr_size(mem_ctl_io_iccm_wr_size),
|
|
.io_iccm_wr_data(mem_ctl_io_iccm_wr_data),
|
|
.io_iccm_rd_data(mem_ctl_io_iccm_rd_data),
|
|
.io_iccm_rd_data_ecc(mem_ctl_io_iccm_rd_data_ecc),
|
|
.io_ic_rw_addr(mem_ctl_io_ic_rw_addr),
|
|
.io_ic_tag_valid(mem_ctl_io_ic_tag_valid),
|
|
.io_ic_wr_en(mem_ctl_io_ic_wr_en),
|
|
.io_ic_rd_en(mem_ctl_io_ic_rd_en),
|
|
.io_ic_wr_data_0(mem_ctl_io_ic_wr_data_0),
|
|
.io_ic_wr_data_1(mem_ctl_io_ic_wr_data_1),
|
|
.io_ic_debug_wr_data(mem_ctl_io_ic_debug_wr_data),
|
|
.io_ic_debug_addr(mem_ctl_io_ic_debug_addr),
|
|
.io_ic_rd_data(mem_ctl_io_ic_rd_data),
|
|
.io_ic_debug_rd_data(mem_ctl_io_ic_debug_rd_data),
|
|
.io_ic_tag_debug_rd_data(mem_ctl_io_ic_tag_debug_rd_data),
|
|
.io_ic_eccerr(mem_ctl_io_ic_eccerr),
|
|
.io_ic_rd_hit(mem_ctl_io_ic_rd_hit),
|
|
.io_ic_tag_perr(mem_ctl_io_ic_tag_perr),
|
|
.io_ic_debug_rd_en(mem_ctl_io_ic_debug_rd_en),
|
|
.io_ic_debug_wr_en(mem_ctl_io_ic_debug_wr_en),
|
|
.io_ic_debug_tag_array(mem_ctl_io_ic_debug_tag_array),
|
|
.io_ic_debug_way(mem_ctl_io_ic_debug_way),
|
|
.io_ic_premux_data(mem_ctl_io_ic_premux_data),
|
|
.io_ic_sel_premux_data(mem_ctl_io_ic_sel_premux_data),
|
|
.io_ifu_fetch_val(mem_ctl_io_ifu_fetch_val),
|
|
.io_ifu_ic_mb_empty(mem_ctl_io_ifu_ic_mb_empty),
|
|
.io_ic_dma_active(mem_ctl_io_ic_dma_active),
|
|
.io_ic_write_stall(mem_ctl_io_ic_write_stall),
|
|
.io_iccm_dma_ecc_error(mem_ctl_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rvalid(mem_ctl_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_rdata(mem_ctl_io_iccm_dma_rdata),
|
|
.io_iccm_dma_rtag(mem_ctl_io_iccm_dma_rtag),
|
|
.io_iccm_ready(mem_ctl_io_iccm_ready),
|
|
.io_dec_tlu_flush_lower_wb(mem_ctl_io_dec_tlu_flush_lower_wb),
|
|
.io_iccm_rd_ecc_double_err(mem_ctl_io_iccm_rd_ecc_double_err),
|
|
.io_iccm_dma_sb_error(mem_ctl_io_iccm_dma_sb_error),
|
|
.io_ic_hit_f(mem_ctl_io_ic_hit_f),
|
|
.io_ic_access_fault_f(mem_ctl_io_ic_access_fault_f),
|
|
.io_ic_access_fault_type_f(mem_ctl_io_ic_access_fault_type_f),
|
|
.io_ifu_async_error_start(mem_ctl_io_ifu_async_error_start),
|
|
.io_ic_fetch_val_f(mem_ctl_io_ic_fetch_val_f),
|
|
.io_ic_data_f(mem_ctl_io_ic_data_f)
|
|
);
|
|
ifu_bp_ctl bp_ctl ( // @[ifu.scala 40:22]
|
|
.clock(bp_ctl_clock),
|
|
.reset(bp_ctl_reset),
|
|
.io_ic_hit_f(bp_ctl_io_ic_hit_f),
|
|
.io_exu_flush_final(bp_ctl_io_exu_flush_final),
|
|
.io_ifc_fetch_addr_f(bp_ctl_io_ifc_fetch_addr_f),
|
|
.io_ifc_fetch_req_f(bp_ctl_io_ifc_fetch_req_f),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_valid(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_bits_way(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way),
|
|
.io_dec_bp_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle),
|
|
.io_dec_bp_dec_tlu_flush_leak_one_wb(bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb),
|
|
.io_dec_bp_dec_tlu_bpred_disable(bp_ctl_io_dec_bp_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_flush_lower_wb(bp_ctl_io_dec_tlu_flush_lower_wb),
|
|
.io_exu_bp_exu_i0_br_index_r(bp_ctl_io_exu_bp_exu_i0_br_index_r),
|
|
.io_exu_bp_exu_i0_br_fghr_r(bp_ctl_io_exu_bp_exu_i0_br_fghr_r),
|
|
.io_exu_bp_exu_mp_pkt_valid(bp_ctl_io_exu_bp_exu_mp_pkt_valid),
|
|
.io_exu_bp_exu_mp_pkt_bits_misp(bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp),
|
|
.io_exu_bp_exu_mp_pkt_bits_ataken(bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken),
|
|
.io_exu_bp_exu_mp_pkt_bits_boffset(bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset),
|
|
.io_exu_bp_exu_mp_pkt_bits_pc4(bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4),
|
|
.io_exu_bp_exu_mp_pkt_bits_hist(bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist),
|
|
.io_exu_bp_exu_mp_pkt_bits_toffset(bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset),
|
|
.io_exu_bp_exu_mp_pkt_bits_pcall(bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall),
|
|
.io_exu_bp_exu_mp_pkt_bits_pja(bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja),
|
|
.io_exu_bp_exu_mp_pkt_bits_way(bp_ctl_io_exu_bp_exu_mp_pkt_bits_way),
|
|
.io_exu_bp_exu_mp_pkt_bits_pret(bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret),
|
|
.io_exu_bp_exu_mp_eghr(bp_ctl_io_exu_bp_exu_mp_eghr),
|
|
.io_exu_bp_exu_mp_fghr(bp_ctl_io_exu_bp_exu_mp_fghr),
|
|
.io_exu_bp_exu_mp_index(bp_ctl_io_exu_bp_exu_mp_index),
|
|
.io_exu_bp_exu_mp_btag(bp_ctl_io_exu_bp_exu_mp_btag),
|
|
.io_ifu_bp_hit_taken_f(bp_ctl_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_btb_target_f(bp_ctl_io_ifu_bp_btb_target_f),
|
|
.io_ifu_bp_inst_mask_f(bp_ctl_io_ifu_bp_inst_mask_f),
|
|
.io_ifu_bp_fghr_f(bp_ctl_io_ifu_bp_fghr_f),
|
|
.io_ifu_bp_way_f(bp_ctl_io_ifu_bp_way_f),
|
|
.io_ifu_bp_ret_f(bp_ctl_io_ifu_bp_ret_f),
|
|
.io_ifu_bp_hist1_f(bp_ctl_io_ifu_bp_hist1_f),
|
|
.io_ifu_bp_hist0_f(bp_ctl_io_ifu_bp_hist0_f),
|
|
.io_ifu_bp_pc4_f(bp_ctl_io_ifu_bp_pc4_f),
|
|
.io_ifu_bp_valid_f(bp_ctl_io_ifu_bp_valid_f),
|
|
.io_ifu_bp_poffset_f(bp_ctl_io_ifu_bp_poffset_f)
|
|
);
|
|
ifu_aln_ctl aln_ctl ( // @[ifu.scala 41:23]
|
|
.clk(aln_ctl_clk),
|
|
.reset(aln_ctl_reset),
|
|
.io_active_clk(aln_ctl_io_active_clk),
|
|
.io_ifu_async_error_start(aln_ctl_io_ifu_async_error_start),
|
|
.io_iccm_rd_ecc_double_err(aln_ctl_io_iccm_rd_ecc_double_err),
|
|
.io_ic_access_fault_f(aln_ctl_io_ic_access_fault_f),
|
|
.io_ic_access_fault_type_f(aln_ctl_io_ic_access_fault_type_f),
|
|
.io_dec_i0_decode_d(aln_ctl_io_dec_i0_decode_d),
|
|
.io_dec_aln_aln_dec_ifu_i0_cinst(aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst),
|
|
.io_dec_aln_aln_ib_ifu_i0_icaf(aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf),
|
|
.io_dec_aln_aln_ib_ifu_i0_icaf_type(aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type),
|
|
.io_dec_aln_aln_ib_ifu_i0_icaf_second(aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_second),
|
|
.io_dec_aln_aln_ib_ifu_i0_dbecc(aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc),
|
|
.io_dec_aln_aln_ib_ifu_i0_bp_index(aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index),
|
|
.io_dec_aln_aln_ib_ifu_i0_bp_fghr(aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr),
|
|
.io_dec_aln_aln_ib_ifu_i0_bp_btag(aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag),
|
|
.io_dec_aln_aln_ib_ifu_i0_valid(aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid),
|
|
.io_dec_aln_aln_ib_ifu_i0_instr(aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr),
|
|
.io_dec_aln_aln_ib_ifu_i0_pc(aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc),
|
|
.io_dec_aln_aln_ib_ifu_i0_pc4(aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4),
|
|
.io_dec_aln_aln_ib_i0_brp_valid(aln_ctl_io_dec_aln_aln_ib_i0_brp_valid),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_toffset(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_hist(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_br_error(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_br_start_error(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_prett(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_way(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way),
|
|
.io_dec_aln_aln_ib_i0_brp_bits_ret(aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret),
|
|
.io_dec_aln_ifu_pmu_instr_aligned(aln_ctl_io_dec_aln_ifu_pmu_instr_aligned),
|
|
.io_ifu_bp_fghr_f(aln_ctl_io_ifu_bp_fghr_f),
|
|
.io_ifu_bp_btb_target_f(aln_ctl_io_ifu_bp_btb_target_f),
|
|
.io_ifu_bp_poffset_f(aln_ctl_io_ifu_bp_poffset_f),
|
|
.io_ifu_bp_hist0_f(aln_ctl_io_ifu_bp_hist0_f),
|
|
.io_ifu_bp_hist1_f(aln_ctl_io_ifu_bp_hist1_f),
|
|
.io_ifu_bp_pc4_f(aln_ctl_io_ifu_bp_pc4_f),
|
|
.io_ifu_bp_way_f(aln_ctl_io_ifu_bp_way_f),
|
|
.io_ifu_bp_valid_f(aln_ctl_io_ifu_bp_valid_f),
|
|
.io_ifu_bp_ret_f(aln_ctl_io_ifu_bp_ret_f),
|
|
.io_exu_flush_final(aln_ctl_io_exu_flush_final),
|
|
.io_ifu_fetch_data_f(aln_ctl_io_ifu_fetch_data_f),
|
|
.io_ifu_fetch_val(aln_ctl_io_ifu_fetch_val),
|
|
.io_ifu_fetch_pc(aln_ctl_io_ifu_fetch_pc),
|
|
.io_ifu_fb_consume1(aln_ctl_io_ifu_fb_consume1),
|
|
.io_ifu_fb_consume2(aln_ctl_io_ifu_fb_consume2)
|
|
);
|
|
ifu_ifc_ctl ifc_ctl ( // @[ifu.scala 42:23]
|
|
.clock(ifc_ctl_clock),
|
|
.reset(ifc_ctl_reset),
|
|
.io_exu_flush_final(ifc_ctl_io_exu_flush_final),
|
|
.io_exu_flush_path_final(ifc_ctl_io_exu_flush_path_final),
|
|
.io_free_l2clk(ifc_ctl_io_free_l2clk),
|
|
.io_ic_hit_f(ifc_ctl_io_ic_hit_f),
|
|
.io_ifu_ic_mb_empty(ifc_ctl_io_ifu_ic_mb_empty),
|
|
.io_ifu_fb_consume1(ifc_ctl_io_ifu_fb_consume1),
|
|
.io_ifu_fb_consume2(ifc_ctl_io_ifu_fb_consume2),
|
|
.io_ifu_bp_hit_taken_f(ifc_ctl_io_ifu_bp_hit_taken_f),
|
|
.io_ifu_bp_btb_target_f(ifc_ctl_io_ifu_bp_btb_target_f),
|
|
.io_ic_dma_active(ifc_ctl_io_ic_dma_active),
|
|
.io_ic_write_stall(ifc_ctl_io_ic_write_stall),
|
|
.io_dec_ifc_dec_tlu_flush_noredir_wb(ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb),
|
|
.io_dec_ifc_dec_tlu_mrac_ff(ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff),
|
|
.io_dec_ifc_ifu_pmu_fetch_stall(ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall),
|
|
.io_dma_ifc_dma_iccm_stall_any(ifc_ctl_io_dma_ifc_dma_iccm_stall_any),
|
|
.io_ifc_fetch_addr_f(ifc_ctl_io_ifc_fetch_addr_f),
|
|
.io_ifc_fetch_addr_bf(ifc_ctl_io_ifc_fetch_addr_bf),
|
|
.io_ifc_fetch_req_f(ifc_ctl_io_ifc_fetch_req_f),
|
|
.io_ifc_fetch_uncacheable_bf(ifc_ctl_io_ifc_fetch_uncacheable_bf),
|
|
.io_ifc_fetch_req_bf(ifc_ctl_io_ifc_fetch_req_bf),
|
|
.io_ifc_fetch_req_bf_raw(ifc_ctl_io_ifc_fetch_req_bf_raw),
|
|
.io_ifc_iccm_access_bf(ifc_ctl_io_ifc_iccm_access_bf),
|
|
.io_ifc_region_acc_fault_bf(ifc_ctl_io_ifc_region_acc_fault_bf),
|
|
.io_ifc_dma_access_ok(ifc_ctl_io_ifc_dma_access_ok)
|
|
);
|
|
assign io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_second; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 77:22]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 101:27]
|
|
assign io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 50:22]
|
|
assign io_iccm_rw_addr = mem_ctl_io_iccm_rw_addr; // @[ifu.scala 115:19]
|
|
assign io_iccm_buf_correct_ecc = mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 115:19]
|
|
assign io_iccm_correction_state = mem_ctl_io_iccm_correction_state; // @[ifu.scala 115:19]
|
|
assign io_iccm_wren = mem_ctl_io_iccm_wren; // @[ifu.scala 115:19]
|
|
assign io_iccm_rden = mem_ctl_io_iccm_rden; // @[ifu.scala 115:19]
|
|
assign io_iccm_wr_size = mem_ctl_io_iccm_wr_size; // @[ifu.scala 115:19]
|
|
assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 115:19]
|
|
assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 114:17]
|
|
assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 114:17]
|
|
assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 114:17]
|
|
assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 114:17]
|
|
assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 114:17]
|
|
assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_wr_en = mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_tag_array = mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 114:17]
|
|
assign io_ic_debug_way = mem_ctl_io_ic_debug_way; // @[ifu.scala 114:17]
|
|
assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 114:17]
|
|
assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 114:17]
|
|
assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 111:22]
|
|
assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 111:22]
|
|
assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 111:22]
|
|
assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 111:22]
|
|
assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 121:25]
|
|
assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 122:22]
|
|
assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 123:21]
|
|
assign io_iccm_dma_rtag = mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 124:20]
|
|
assign io_iccm_ready = mem_ctl_io_iccm_ready; // @[ifu.scala 125:17]
|
|
assign io_iccm_dma_sb_error = mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 126:24]
|
|
assign mem_ctl_clock = clock;
|
|
assign mem_ctl_reset = reset;
|
|
assign mem_ctl_io_free_l2clk = io_free_l2clk; // @[ifu.scala 98:25]
|
|
assign mem_ctl_io_active_clk = io_active_clk; // @[ifu.scala 99:25]
|
|
assign mem_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 100:30]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt = io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt = io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable = io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 101:27]
|
|
assign mem_ctl_io_ifc_fetch_addr_bf = ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 102:32]
|
|
assign mem_ctl_io_ifc_fetch_uncacheable_bf = ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 103:39]
|
|
assign mem_ctl_io_ifc_fetch_req_bf = ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 104:31]
|
|
assign mem_ctl_io_ifc_fetch_req_bf_raw = ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 105:35]
|
|
assign mem_ctl_io_ifc_iccm_access_bf = ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 106:33]
|
|
assign mem_ctl_io_ifc_region_acc_fault_bf = ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 107:38]
|
|
assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 108:32]
|
|
assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 109:33]
|
|
assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 110:33]
|
|
assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 111:22]
|
|
assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 111:22]
|
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assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 111:22]
|
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assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 111:22]
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assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 111:22]
|
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assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 112:29]
|
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assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_dma_mem_ctl_dma_mem_sz = io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_dma_mem_ctl_dma_mem_write = io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_dma_mem_ctl_dma_mem_wdata = io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_dma_mem_ctl_dma_mem_tag = io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 113:26]
|
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assign mem_ctl_io_iccm_rd_data = io_iccm_rd_data; // @[ifu.scala 115:19]
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assign mem_ctl_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[ifu.scala 115:19]
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assign mem_ctl_io_ic_rd_data = io_ic_rd_data; // @[ifu.scala 114:17]
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assign mem_ctl_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[ifu.scala 114:17]
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assign mem_ctl_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[ifu.scala 114:17]
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assign mem_ctl_io_ic_eccerr = io_ic_eccerr; // @[ifu.scala 114:17]
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assign mem_ctl_io_ic_rd_hit = io_ic_rd_hit; // @[ifu.scala 114:17]
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assign mem_ctl_io_ic_tag_perr = io_ic_tag_perr; // @[ifu.scala 114:17]
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assign mem_ctl_io_ifu_fetch_val = mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 116:28]
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assign mem_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 117:37]
|
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assign bp_ctl_clock = clock;
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assign bp_ctl_reset = reset;
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assign bp_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 88:22]
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assign bp_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 93:29]
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assign bp_ctl_io_ifc_fetch_addr_f = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 89:30]
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assign bp_ctl_io_ifc_fetch_req_f = ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 90:29]
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 91:20]
|
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb = io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_bp_dec_tlu_bpred_disable = io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 91:20]
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assign bp_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 94:36]
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assign bp_ctl_io_exu_bp_exu_i0_br_index_r = io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_i0_br_fghr_r = io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_valid = io_exu_ifu_exu_bp_exu_mp_pkt_valid; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp = io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken = io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4 = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist = io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 92:20]
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_way = io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 92:20]
|
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assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 92:20]
|
|
assign bp_ctl_io_exu_bp_exu_mp_eghr = io_exu_ifu_exu_bp_exu_mp_eghr; // @[ifu.scala 92:20]
|
|
assign bp_ctl_io_exu_bp_exu_mp_fghr = io_exu_ifu_exu_bp_exu_mp_fghr; // @[ifu.scala 92:20]
|
|
assign bp_ctl_io_exu_bp_exu_mp_index = io_exu_ifu_exu_bp_exu_mp_index; // @[ifu.scala 92:20]
|
|
assign bp_ctl_io_exu_bp_exu_mp_btag = io_exu_ifu_exu_bp_exu_mp_btag; // @[ifu.scala 92:20]
|
|
assign aln_ctl_clk = clock;
|
|
assign aln_ctl_reset = reset;
|
|
assign aln_ctl_io_active_clk = io_active_clk; // @[ifu.scala 62:25]
|
|
assign aln_ctl_io_ifu_async_error_start = mem_ctl_io_ifu_async_error_start; // @[ifu.scala 63:36]
|
|
assign aln_ctl_io_iccm_rd_ecc_double_err = mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 64:37]
|
|
assign aln_ctl_io_ic_access_fault_f = mem_ctl_io_ic_access_fault_f; // @[ifu.scala 65:32]
|
|
assign aln_ctl_io_ic_access_fault_type_f = mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 66:37]
|
|
assign aln_ctl_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[ifu.scala 79:30]
|
|
assign aln_ctl_io_ifu_bp_fghr_f = bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 67:28]
|
|
assign aln_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 68:34]
|
|
assign aln_ctl_io_ifu_bp_poffset_f = bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 69:31]
|
|
assign aln_ctl_io_ifu_bp_hist0_f = bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 70:29]
|
|
assign aln_ctl_io_ifu_bp_hist1_f = bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 71:29]
|
|
assign aln_ctl_io_ifu_bp_pc4_f = bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 72:27]
|
|
assign aln_ctl_io_ifu_bp_way_f = bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 73:27]
|
|
assign aln_ctl_io_ifu_bp_valid_f = bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 74:29]
|
|
assign aln_ctl_io_ifu_bp_ret_f = bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 75:27]
|
|
assign aln_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 76:30]
|
|
assign aln_ctl_io_ifu_fetch_data_f = mem_ctl_io_ic_data_f; // @[ifu.scala 82:31]
|
|
assign aln_ctl_io_ifu_fetch_val = mem_ctl_io_ifu_fetch_val; // @[ifu.scala 83:28]
|
|
assign aln_ctl_io_ifu_fetch_pc = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 84:27]
|
|
assign ifc_ctl_clock = clock;
|
|
assign ifc_ctl_reset = reset;
|
|
assign ifc_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 51:30]
|
|
assign ifc_ctl_io_exu_flush_path_final = io_exu_flush_path_final; // @[ifu.scala 58:35]
|
|
assign ifc_ctl_io_free_l2clk = io_free_l2clk; // @[ifu.scala 45:25]
|
|
assign ifc_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 47:23]
|
|
assign ifc_ctl_io_ifu_ic_mb_empty = mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 57:30]
|
|
assign ifc_ctl_io_ifu_fb_consume1 = aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 48:30]
|
|
assign ifc_ctl_io_ifu_fb_consume2 = aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 49:30]
|
|
assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 52:33]
|
|
assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 53:34]
|
|
assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 54:28]
|
|
assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 55:29]
|
|
assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 50:22]
|
|
assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 50:22]
|
|
assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 56:22]
|
|
endmodule
|
|
module dec_ib_ctl(
|
|
input io_ifu_ib_ifu_i0_icaf,
|
|
input [1:0] io_ifu_ib_ifu_i0_icaf_type,
|
|
input io_ifu_ib_ifu_i0_icaf_second,
|
|
input io_ifu_ib_ifu_i0_dbecc,
|
|
input [7:0] io_ifu_ib_ifu_i0_bp_index,
|
|
input [7:0] io_ifu_ib_ifu_i0_bp_fghr,
|
|
input [4:0] io_ifu_ib_ifu_i0_bp_btag,
|
|
input io_ifu_ib_ifu_i0_valid,
|
|
input [31:0] io_ifu_ib_ifu_i0_instr,
|
|
input [30:0] io_ifu_ib_ifu_i0_pc,
|
|
input io_ifu_ib_ifu_i0_pc4,
|
|
input io_ifu_ib_i0_brp_valid,
|
|
input [11:0] io_ifu_ib_i0_brp_bits_toffset,
|
|
input [1:0] io_ifu_ib_i0_brp_bits_hist,
|
|
input io_ifu_ib_i0_brp_bits_br_error,
|
|
input io_ifu_ib_i0_brp_bits_br_start_error,
|
|
input [30:0] io_ifu_ib_i0_brp_bits_prett,
|
|
input io_ifu_ib_i0_brp_bits_way,
|
|
input io_ifu_ib_i0_brp_bits_ret,
|
|
output [30:0] io_ib_exu_dec_i0_pc_d,
|
|
output io_ib_exu_dec_debug_wdata_rs1_d,
|
|
input io_dbg_ib_dbg_cmd_valid,
|
|
input io_dbg_ib_dbg_cmd_write,
|
|
input [1:0] io_dbg_ib_dbg_cmd_type,
|
|
input [31:0] io_dbg_ib_dbg_cmd_addr,
|
|
output io_dec_debug_valid_d,
|
|
output io_dec_ib0_valid_d,
|
|
output [1:0] io_dec_i0_icaf_type_d,
|
|
output [31:0] io_dec_i0_instr_d,
|
|
output io_dec_i0_pc4_d,
|
|
output io_dec_i0_brp_valid,
|
|
output [11:0] io_dec_i0_brp_bits_toffset,
|
|
output [1:0] io_dec_i0_brp_bits_hist,
|
|
output io_dec_i0_brp_bits_br_error,
|
|
output io_dec_i0_brp_bits_br_start_error,
|
|
output [30:0] io_dec_i0_brp_bits_prett,
|
|
output io_dec_i0_brp_bits_way,
|
|
output io_dec_i0_brp_bits_ret,
|
|
output [7:0] io_dec_i0_bp_index,
|
|
output [7:0] io_dec_i0_bp_fghr,
|
|
output [4:0] io_dec_i0_bp_btag,
|
|
output io_dec_i0_icaf_d,
|
|
output io_dec_i0_icaf_second_d,
|
|
output io_dec_i0_dbecc_d,
|
|
output io_dec_debug_fence_d
|
|
);
|
|
wire _T = io_dbg_ib_dbg_cmd_type != 2'h2; // @[dec_ib_ctl.scala 58:74]
|
|
wire debug_valid = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 58:48]
|
|
wire _T_1 = ~io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 59:38]
|
|
wire debug_read = debug_valid & _T_1; // @[dec_ib_ctl.scala 59:36]
|
|
wire debug_write = debug_valid & io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 60:36]
|
|
wire _T_2 = io_dbg_ib_dbg_cmd_type == 2'h0; // @[dec_ib_ctl.scala 62:62]
|
|
wire debug_read_gpr = debug_read & _T_2; // @[dec_ib_ctl.scala 62:37]
|
|
wire debug_write_gpr = debug_write & _T_2; // @[dec_ib_ctl.scala 63:37]
|
|
wire _T_4 = io_dbg_ib_dbg_cmd_type == 2'h1; // @[dec_ib_ctl.scala 64:62]
|
|
wire debug_read_csr = debug_read & _T_4; // @[dec_ib_ctl.scala 64:37]
|
|
wire debug_write_csr = debug_write & _T_4; // @[dec_ib_ctl.scala 65:37]
|
|
wire [4:0] dreg = io_dbg_ib_dbg_cmd_addr[4:0]; // @[dec_ib_ctl.scala 67:47]
|
|
wire [11:0] dcsr = io_dbg_ib_dbg_cmd_addr[11:0]; // @[dec_ib_ctl.scala 68:47]
|
|
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
|
wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72]
|
|
wire _T_25 = dcsr == 12'h7c4; // @[dec_ib_ctl.scala 81:51]
|
|
assign io_ib_exu_dec_i0_pc_d = io_ifu_ib_ifu_i0_pc; // @[dec_ib_ctl.scala 37:31]
|
|
assign io_ib_exu_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[dec_ib_ctl.scala 78:35]
|
|
assign io_dec_debug_valid_d = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 61:24]
|
|
assign io_dec_ib0_valid_d = io_ifu_ib_ifu_i0_valid | debug_valid; // @[dec_ib_ctl.scala 83:22]
|
|
assign io_dec_i0_icaf_type_d = io_ifu_ib_ifu_i0_icaf_type; // @[dec_ib_ctl.scala 39:31]
|
|
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_ib_ifu_i0_instr; // @[dec_ib_ctl.scala 84:22]
|
|
assign io_dec_i0_pc4_d = io_ifu_ib_ifu_i0_pc4; // @[dec_ib_ctl.scala 38:31]
|
|
assign io_dec_i0_brp_valid = io_ifu_ib_i0_brp_valid; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_toffset = io_ifu_ib_i0_brp_bits_toffset; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_hist = io_ifu_ib_i0_brp_bits_hist; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_br_error = io_ifu_ib_i0_brp_bits_br_error; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_br_start_error = io_ifu_ib_i0_brp_bits_br_start_error; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_prett = io_ifu_ib_i0_brp_bits_prett; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_way = io_ifu_ib_i0_brp_bits_way; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_brp_bits_ret = io_ifu_ib_i0_brp_bits_ret; // @[dec_ib_ctl.scala 40:31]
|
|
assign io_dec_i0_bp_index = io_ifu_ib_ifu_i0_bp_index; // @[dec_ib_ctl.scala 41:31]
|
|
assign io_dec_i0_bp_fghr = io_ifu_ib_ifu_i0_bp_fghr; // @[dec_ib_ctl.scala 42:31]
|
|
assign io_dec_i0_bp_btag = io_ifu_ib_ifu_i0_bp_btag; // @[dec_ib_ctl.scala 43:31]
|
|
assign io_dec_i0_icaf_d = io_ifu_ib_ifu_i0_icaf; // @[dec_ib_ctl.scala 36:31]
|
|
assign io_dec_i0_icaf_second_d = io_ifu_ib_ifu_i0_icaf_second; // @[dec_ib_ctl.scala 34:35]
|
|
assign io_dec_i0_dbecc_d = io_ifu_ib_ifu_i0_dbecc; // @[dec_ib_ctl.scala 35:31]
|
|
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[dec_ib_ctl.scala 81:24]
|
|
endmodule
|
|
module dec_dec_ctl(
|
|
input [31:0] io_ins,
|
|
output io_out_clz,
|
|
output io_out_ctz,
|
|
output io_out_pcnt,
|
|
output io_out_sext_b,
|
|
output io_out_sext_h,
|
|
output io_out_min,
|
|
output io_out_max,
|
|
output io_out_pack,
|
|
output io_out_packu,
|
|
output io_out_packh,
|
|
output io_out_rol,
|
|
output io_out_ror,
|
|
output io_out_grev,
|
|
output io_out_gorc,
|
|
output io_out_zbb,
|
|
output io_out_sbset,
|
|
output io_out_sbclr,
|
|
output io_out_sbinv,
|
|
output io_out_sbext,
|
|
output io_out_zbs,
|
|
output io_out_zbe,
|
|
output io_out_zbc,
|
|
output io_out_zbp,
|
|
output io_out_zbr,
|
|
output io_out_zbf,
|
|
output io_out_zba,
|
|
output io_out_alu,
|
|
output io_out_rs1,
|
|
output io_out_rs2,
|
|
output io_out_imm12,
|
|
output io_out_rd,
|
|
output io_out_shimm5,
|
|
output io_out_imm20,
|
|
output io_out_pc,
|
|
output io_out_load,
|
|
output io_out_store,
|
|
output io_out_lsu,
|
|
output io_out_add,
|
|
output io_out_sub,
|
|
output io_out_land,
|
|
output io_out_lor,
|
|
output io_out_lxor,
|
|
output io_out_sll,
|
|
output io_out_sra,
|
|
output io_out_srl,
|
|
output io_out_slt,
|
|
output io_out_unsign,
|
|
output io_out_condbr,
|
|
output io_out_beq,
|
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output io_out_bne,
|
|
output io_out_bge,
|
|
output io_out_blt,
|
|
output io_out_jal,
|
|
output io_out_by,
|
|
output io_out_half,
|
|
output io_out_word,
|
|
output io_out_csr_read,
|
|
output io_out_csr_clr,
|
|
output io_out_csr_set,
|
|
output io_out_csr_write,
|
|
output io_out_csr_imm,
|
|
output io_out_presync,
|
|
output io_out_postsync,
|
|
output io_out_ebreak,
|
|
output io_out_ecall,
|
|
output io_out_mret,
|
|
output io_out_mul,
|
|
output io_out_rs1_sign,
|
|
output io_out_rs2_sign,
|
|
output io_out_low,
|
|
output io_out_div,
|
|
output io_out_rem,
|
|
output io_out_fence,
|
|
output io_out_fence_i,
|
|
output io_out_pm_alu,
|
|
output io_out_legal
|
|
);
|
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wire _T_4 = ~io_ins[22]; // @[dec_dec_ctl.scala 15:46]
|
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wire _T_6 = ~io_ins[21]; // @[dec_dec_ctl.scala 15:46]
|
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wire _T_8 = ~io_ins[20]; // @[dec_dec_ctl.scala 15:46]
|
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wire _T_11 = ~io_ins[5]; // @[dec_dec_ctl.scala 15:46]
|
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wire _T_13 = io_ins[30] & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_14 = _T_13 & io_ins[23]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_15 = _T_14 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_16 = _T_15 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_17 = _T_16 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_18 = _T_17 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_19 = _T_18 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_20 = _T_19 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_23 = ~io_ins[27]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_25 = ~io_ins[24]; // @[dec_dec_ctl.scala 15:46]
|
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wire _T_27 = io_ins[29] & _T_23; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_28 = _T_27 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_29 = _T_28 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_30 = _T_20 | _T_29; // @[dec_dec_ctl.scala 20:62]
|
|
wire _T_32 = ~io_ins[25]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_34 = ~io_ins[13]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_36 = ~io_ins[12]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_38 = _T_32 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_39 = _T_38 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_40 = _T_39 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_41 = _T_30 | _T_40; // @[dec_dec_ctl.scala 20:92]
|
|
wire _T_43 = ~io_ins[30]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_48 = _T_43 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_49 = _T_48 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_50 = _T_49 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_51 = _T_41 | _T_50; // @[dec_dec_ctl.scala 21:34]
|
|
wire _T_56 = io_ins[27] & io_ins[25]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_57 = _T_56 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_58 = _T_57 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_59 = _T_51 | _T_58; // @[dec_dec_ctl.scala 21:66]
|
|
wire _T_63 = ~io_ins[14]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_65 = io_ins[29] & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_66 = _T_65 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_67 = _T_66 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_68 = _T_59 | _T_67; // @[dec_dec_ctl.scala 21:94]
|
|
wire _T_74 = io_ins[29] & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_75 = _T_74 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_76 = _T_75 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_77 = _T_68 | _T_76; // @[dec_dec_ctl.scala 22:32]
|
|
wire _T_84 = _T_23 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_85 = _T_84 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_86 = _T_85 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_87 = _T_77 | _T_86; // @[dec_dec_ctl.scala 22:60]
|
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wire _T_90 = ~io_ins[29]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_94 = io_ins[30] & _T_90; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_95 = _T_94 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_96 = _T_95 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_97 = _T_87 | _T_96; // @[dec_dec_ctl.scala 22:90]
|
|
wire _T_105 = _T_43 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_106 = _T_105 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_107 = _T_106 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_108 = _T_97 | _T_107; // @[dec_dec_ctl.scala 23:33]
|
|
wire _T_113 = io_ins[13] & _T_11; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_114 = _T_113 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_115 = _T_108 | _T_114; // @[dec_dec_ctl.scala 23:64]
|
|
wire _T_121 = _T_36 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_122 = _T_121 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_123 = _T_115 | _T_122; // @[dec_dec_ctl.scala 23:89]
|
|
wire _T_125 = _T_123 | io_ins[2]; // @[dec_dec_ctl.scala 24:29]
|
|
wire _T_127 = _T_125 | io_ins[6]; // @[dec_dec_ctl.scala 24:48]
|
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wire _T_139 = _T_14 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_140 = _T_139 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_141 = _T_140 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_142 = _T_141 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_143 = _T_142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_144 = _T_127 | _T_143; // @[dec_dec_ctl.scala 24:67]
|
|
wire _T_151 = ~io_ins[23]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_158 = _T_43 & io_ins[29]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_159 = _T_158 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_160 = _T_159 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_161 = _T_160 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_162 = _T_161 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
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wire _T_163 = _T_162 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_164 = _T_163 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_165 = _T_164 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_166 = _T_144 | _T_165; // @[dec_dec_ctl.scala 24:107]
|
|
wire _T_181 = _T_43 & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_182 = _T_181 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_183 = _T_182 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_184 = _T_183 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_185 = _T_184 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_186 = _T_185 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_187 = _T_186 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_194 = ~io_ins[2]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_195 = _T_63 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_196 = _T_195 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_202 = _T_34 & io_ins[11]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_203 = _T_202 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_204 = _T_196 | _T_203; // @[dec_dec_ctl.scala 27:43]
|
|
wire _T_209 = io_ins[19] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_210 = _T_209 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_211 = _T_204 | _T_210; // @[dec_dec_ctl.scala 27:70]
|
|
wire _T_217 = _T_34 & io_ins[10]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_218 = _T_217 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_219 = _T_211 | _T_218; // @[dec_dec_ctl.scala 27:96]
|
|
wire _T_224 = io_ins[18] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_225 = _T_224 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_226 = _T_219 | _T_225; // @[dec_dec_ctl.scala 28:30]
|
|
wire _T_232 = _T_34 & io_ins[9]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_233 = _T_232 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_234 = _T_226 | _T_233; // @[dec_dec_ctl.scala 28:57]
|
|
wire _T_239 = io_ins[17] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_240 = _T_239 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_241 = _T_234 | _T_240; // @[dec_dec_ctl.scala 28:83]
|
|
wire _T_247 = _T_34 & io_ins[8]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_248 = _T_247 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_249 = _T_241 | _T_248; // @[dec_dec_ctl.scala 28:109]
|
|
wire _T_254 = io_ins[16] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_255 = _T_254 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_256 = _T_249 | _T_255; // @[dec_dec_ctl.scala 29:29]
|
|
wire _T_262 = _T_34 & io_ins[7]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_263 = _T_262 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_264 = _T_256 | _T_263; // @[dec_dec_ctl.scala 29:55]
|
|
wire _T_269 = io_ins[15] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_270 = _T_269 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_271 = _T_264 | _T_270; // @[dec_dec_ctl.scala 29:81]
|
|
wire _T_273 = ~io_ins[4]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_275 = ~io_ins[3]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_276 = _T_273 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_277 = _T_271 | _T_276; // @[dec_dec_ctl.scala 30:29]
|
|
wire _T_279 = ~io_ins[6]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_282 = _T_279 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_289 = io_ins[5] & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_290 = _T_289 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_296 = _T_279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_297 = _T_296 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_305 = _T_276 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_314 = _T_114 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_315 = _T_305 | _T_314; // @[dec_dec_ctl.scala 34:42]
|
|
wire _T_322 = _T_34 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_323 = _T_322 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_324 = _T_323 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_325 = _T_315 | _T_324; // @[dec_dec_ctl.scala 34:70]
|
|
wire _T_335 = _T_122 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_341 = _T_11 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_344 = io_ins[5] & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_345 = _T_341 | _T_344; // @[dec_dec_ctl.scala 36:37]
|
|
wire _T_357 = io_ins[27] & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_358 = _T_357 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_359 = _T_358 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_360 = _T_359 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_361 = _T_360 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_372 = _T_43 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_373 = _T_372 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_374 = _T_373 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_375 = _T_374 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_376 = _T_375 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_377 = _T_361 | _T_376; // @[dec_dec_ctl.scala 38:53]
|
|
wire _T_387 = io_ins[14] & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_388 = _T_387 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_389 = _T_388 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_390 = _T_389 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_391 = _T_390 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_395 = io_ins[5] & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_398 = io_ins[4] & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_405 = _T_11 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_406 = _T_405 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_417 = _T_11 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_432 = _T_279 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_444 = _T_195 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_445 = _T_444 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_446 = _T_445 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_454 = _T_446 | _T_406; // @[dec_dec_ctl.scala 50:49]
|
|
wire _T_471 = _T_48 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_472 = _T_471 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_473 = _T_472 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_474 = _T_473 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_475 = _T_474 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_476 = _T_475 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_489 = io_ins[30] & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_490 = _T_489 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_491 = _T_490 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_492 = _T_491 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_493 = _T_492 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_494 = _T_493 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_507 = _T_90 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_508 = _T_507 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_509 = _T_508 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_510 = _T_509 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_511 = _T_510 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_512 = _T_511 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_513 = _T_494 | _T_512; // @[dec_dec_ctl.scala 52:53]
|
|
wire _T_524 = _T_57 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_525 = _T_524 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_526 = _T_525 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_527 = _T_513 | _T_526; // @[dec_dec_ctl.scala 52:93]
|
|
wire _T_536 = _T_63 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_537 = _T_536 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_538 = _T_537 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_539 = _T_538 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_540 = _T_527 | _T_539; // @[dec_dec_ctl.scala 53:37]
|
|
wire _T_546 = io_ins[6] & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_547 = _T_546 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_562 = _T_85 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_563 = _T_562 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_564 = _T_563 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_565 = _T_564 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_573 = io_ins[14] & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_574 = _T_573 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_575 = _T_574 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_576 = _T_575 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_581 = _T_279 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_596 = _T_90 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_597 = _T_596 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_598 = _T_597 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_599 = _T_598 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_600 = _T_599 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_601 = _T_600 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_602 = _T_601 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_603 = _T_581 | _T_602; // @[dec_dec_ctl.scala 57:37]
|
|
wire _T_607 = io_ins[5] & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_608 = _T_607 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_609 = _T_603 | _T_608; // @[dec_dec_ctl.scala 57:82]
|
|
wire _T_619 = _T_609 | _T_324; // @[dec_dec_ctl.scala 57:105]
|
|
wire _T_629 = _T_573 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_630 = _T_629 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_631 = _T_630 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_650 = _T_598 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_651 = _T_650 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_652 = _T_651 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_653 = _T_652 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_665 = _T_387 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_666 = _T_665 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_667 = _T_666 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_668 = _T_667 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_688 = _T_597 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_689 = _T_688 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_690 = _T_689 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_691 = _T_690 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_692 = _T_691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_708 = _T_94 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_709 = _T_708 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_710 = _T_709 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_711 = _T_710 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_712 = _T_711 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_731 = _T_43 & _T_90; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_732 = _T_731 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_733 = _T_732 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_734 = _T_733 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_735 = _T_734 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_736 = _T_735 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_737 = _T_736 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_738 = _T_737 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_781 = _T_23 & io_ins[25]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_782 = _T_781 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_783 = _T_782 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_784 = _T_783 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_785 = _T_784 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_786 = _T_785 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_796 = _T_536 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_797 = _T_796 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_798 = _T_797 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_799 = _T_786 | _T_798; // @[dec_dec_ctl.scala 70:56]
|
|
wire _T_806 = io_ins[13] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_807 = _T_806 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_808 = _T_807 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_809 = _T_799 | _T_808; // @[dec_dec_ctl.scala 70:89]
|
|
wire _T_815 = io_ins[14] & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_816 = _T_815 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_817 = _T_809 | _T_816; // @[dec_dec_ctl.scala 71:31]
|
|
wire _T_828 = _T_32 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_829 = _T_828 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_830 = _T_829 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_831 = _T_830 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_832 = _T_831 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_833 = _T_817 | _T_832; // @[dec_dec_ctl.scala 71:57]
|
|
wire _T_845 = _T_57 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_846 = _T_845 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_847 = _T_846 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_848 = _T_847 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_866 = _T_63 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_867 = _T_866 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_868 = _T_867 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_878 = _T_63 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_879 = _T_878 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_880 = _T_879 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_889 = io_ins[14] & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_890 = _T_889 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_891 = _T_890 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_901 = io_ins[14] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_902 = _T_901 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_903 = _T_902 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_919 = _T_322 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_920 = _T_919 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_929 = io_ins[12] & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_930 = _T_929 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_937 = io_ins[13] & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_943 = _T_806 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_947 = io_ins[7] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_948 = _T_947 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_949 = _T_943 | _T_948; // @[dec_dec_ctl.scala 92:44]
|
|
wire _T_953 = io_ins[8] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_954 = _T_953 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_955 = _T_949 | _T_954; // @[dec_dec_ctl.scala 92:67]
|
|
wire _T_959 = io_ins[9] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_960 = _T_959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_961 = _T_955 | _T_960; // @[dec_dec_ctl.scala 92:90]
|
|
wire _T_965 = io_ins[10] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_966 = _T_965 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_967 = _T_961 | _T_966; // @[dec_dec_ctl.scala 93:26]
|
|
wire _T_971 = io_ins[11] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_972 = _T_971 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_980 = _T_269 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_981 = _T_980 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_982 = _T_981 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_989 = _T_254 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_990 = _T_989 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_991 = _T_990 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_992 = _T_982 | _T_991; // @[dec_dec_ctl.scala 95:49]
|
|
wire _T_999 = _T_239 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1000 = _T_999 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1001 = _T_1000 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1002 = _T_992 | _T_1001; // @[dec_dec_ctl.scala 95:79]
|
|
wire _T_1009 = _T_224 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1010 = _T_1009 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1011 = _T_1010 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1012 = _T_1002 | _T_1011; // @[dec_dec_ctl.scala 96:33]
|
|
wire _T_1019 = _T_209 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1020 = _T_1019 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1021 = _T_1020 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1028 = io_ins[15] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1029 = _T_1028 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1030 = _T_1029 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1036 = io_ins[16] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1037 = _T_1036 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1038 = _T_1037 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1039 = _T_1030 | _T_1038; // @[dec_dec_ctl.scala 98:47]
|
|
wire _T_1045 = io_ins[17] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1046 = _T_1045 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1047 = _T_1046 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1048 = _T_1039 | _T_1047; // @[dec_dec_ctl.scala 98:75]
|
|
wire _T_1054 = io_ins[18] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1055 = _T_1054 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1056 = _T_1055 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1057 = _T_1048 | _T_1056; // @[dec_dec_ctl.scala 98:103]
|
|
wire _T_1063 = io_ins[19] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1064 = _T_1063 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1065 = _T_1064 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1072 = _T_34 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1073 = _T_1072 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1081 = _T_387 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1082 = _T_1081 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1087 = io_ins[15] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1088 = _T_1087 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1089 = _T_1088 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1090 = _T_1082 | _T_1089; // @[dec_dec_ctl.scala 103:47]
|
|
wire _T_1095 = io_ins[16] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1096 = _T_1095 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1097 = _T_1096 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1098 = _T_1090 | _T_1097; // @[dec_dec_ctl.scala 103:74]
|
|
wire _T_1103 = io_ins[17] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1104 = _T_1103 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1105 = _T_1104 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1106 = _T_1098 | _T_1105; // @[dec_dec_ctl.scala 103:101]
|
|
wire _T_1111 = io_ins[18] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1112 = _T_1111 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1113 = _T_1112 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1114 = _T_1106 | _T_1113; // @[dec_dec_ctl.scala 104:30]
|
|
wire _T_1119 = io_ins[19] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1120 = _T_1119 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1121 = _T_1120 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1126 = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1133 = _T_262 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1134 = _T_1133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1135 = _T_1126 | _T_1134; // @[dec_dec_ctl.scala 106:41]
|
|
wire _T_1142 = _T_247 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1143 = _T_1142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1144 = _T_1135 | _T_1143; // @[dec_dec_ctl.scala 106:68]
|
|
wire _T_1151 = _T_232 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1152 = _T_1151 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1153 = _T_1144 | _T_1152; // @[dec_dec_ctl.scala 106:95]
|
|
wire _T_1160 = _T_217 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1161 = _T_1160 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1162 = _T_1153 | _T_1161; // @[dec_dec_ctl.scala 107:30]
|
|
wire _T_1169 = _T_202 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1170 = _T_1169 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1171 = _T_1162 | _T_1170; // @[dec_dec_ctl.scala 107:58]
|
|
wire _T_1177 = _T_269 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1178 = _T_1177 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1179 = _T_1171 | _T_1178; // @[dec_dec_ctl.scala 107:86]
|
|
wire _T_1185 = _T_254 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1186 = _T_1185 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1187 = _T_1179 | _T_1186; // @[dec_dec_ctl.scala 108:30]
|
|
wire _T_1193 = _T_239 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1194 = _T_1193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1195 = _T_1187 | _T_1194; // @[dec_dec_ctl.scala 108:57]
|
|
wire _T_1201 = _T_224 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1202 = _T_1201 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1203 = _T_1195 | _T_1202; // @[dec_dec_ctl.scala 108:84]
|
|
wire _T_1209 = _T_209 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1210 = _T_1209 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1216 = io_ins[12] & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1217 = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1226 = _T_4 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1227 = _T_1226 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1228 = _T_1227 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1229 = _T_1228 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1230 = _T_1217 | _T_1229; // @[dec_dec_ctl.scala 111:45]
|
|
wire _T_1239 = _T_1230 | _T_1134; // @[dec_dec_ctl.scala 111:78]
|
|
wire _T_1248 = _T_1239 | _T_1143; // @[dec_dec_ctl.scala 112:30]
|
|
wire _T_1257 = _T_1248 | _T_1152; // @[dec_dec_ctl.scala 112:57]
|
|
wire _T_1266 = _T_1257 | _T_1161; // @[dec_dec_ctl.scala 112:84]
|
|
wire _T_1275 = _T_1266 | _T_1170; // @[dec_dec_ctl.scala 112:112]
|
|
wire _T_1283 = _T_1275 | _T_1178; // @[dec_dec_ctl.scala 113:31]
|
|
wire _T_1291 = _T_1283 | _T_1186; // @[dec_dec_ctl.scala 113:58]
|
|
wire _T_1299 = _T_1291 | _T_1194; // @[dec_dec_ctl.scala 113:85]
|
|
wire _T_1307 = _T_1299 | _T_1202; // @[dec_dec_ctl.scala 113:112]
|
|
wire _T_1325 = _T_4 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1326 = _T_1325 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1327 = _T_1326 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1328 = _T_1327 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1340 = _T_6 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1341 = _T_1340 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1342 = _T_1341 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1343 = _T_1342 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1352 = io_ins[29] & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1353 = _T_1352 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1354 = _T_1353 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1370 = _T_43 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1371 = _T_1370 & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1372 = _T_1371 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1373 = _T_1372 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1374 = _T_1373 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1375 = _T_1374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1376 = _T_1375 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1377 = _T_1376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1378 = _T_1377 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1394 = _T_65 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1395 = _T_1394 & io_ins[23]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1396 = _T_1395 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1397 = _T_1396 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1398 = _T_1397 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1399 = _T_1398 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1400 = _T_1399 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1401 = _T_1400 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1402 = _T_1378 | _T_1401; // @[dec_dec_ctl.scala 122:63]
|
|
wire _T_1420 = _T_1394 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1421 = _T_1420 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1422 = _T_1421 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1423 = _T_1422 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1424 = _T_1423 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1425 = _T_1424 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1426 = _T_1425 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1427 = _T_1402 | _T_1426; // @[dec_dec_ctl.scala 122:111]
|
|
wire _T_1440 = io_ins[27] & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1441 = _T_1440 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1442 = _T_1441 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1443 = _T_1442 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1444 = _T_1443 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1445 = _T_1444 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1446 = _T_1445 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1447 = _T_1427 | _T_1446; // @[dec_dec_ctl.scala 123:52]
|
|
wire _T_1457 = io_ins[30] & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1458 = _T_1457 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1459 = _T_1458 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1460 = _T_1459 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1461 = _T_1460 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1462 = _T_1461 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1463 = _T_1447 | _T_1462; // @[dec_dec_ctl.scala 123:93]
|
|
wire _T_1479 = _T_65 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1480 = _T_1479 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1481 = _T_1480 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1482 = _T_1481 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1483 = _T_1482 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1484 = _T_1483 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1485 = _T_1484 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1486 = _T_1485 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1487 = _T_1463 | _T_1486; // @[dec_dec_ctl.scala 124:39]
|
|
wire _T_1503 = _T_65 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1504 = _T_1503 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1505 = _T_1504 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1506 = _T_1505 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1507 = _T_1506 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1508 = _T_1507 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1509 = _T_1508 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1510 = _T_1509 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1511 = _T_1487 | _T_1510; // @[dec_dec_ctl.scala 124:87]
|
|
wire _T_1527 = _T_65 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1528 = _T_1527 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1529 = _T_1528 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1530 = _T_1529 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1531 = _T_1530 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1532 = _T_1531 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1533 = _T_1532 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1534 = _T_1533 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1535 = _T_1511 | _T_1534; // @[dec_dec_ctl.scala 125:51]
|
|
wire _T_1550 = io_ins[30] & io_ins[29]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1551 = _T_1550 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1552 = _T_1551 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1553 = _T_1552 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1554 = _T_1553 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1555 = _T_1554 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1556 = _T_1555 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1557 = _T_1556 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1558 = _T_1557 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1559 = _T_1535 | _T_1558; // @[dec_dec_ctl.scala 125:99]
|
|
wire _T_1574 = _T_1370 & io_ins[23]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1575 = _T_1574 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1576 = _T_1575 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1577 = _T_1576 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1578 = _T_1577 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1579 = _T_1578 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1580 = _T_1579 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1581 = _T_1559 | _T_1580; // @[dec_dec_ctl.scala 126:51]
|
|
wire _T_1598 = _T_731 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1599 = _T_1598 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1600 = _T_1599 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1601 = _T_1600 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1602 = _T_1601 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1603 = _T_1602 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1604 = _T_1603 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1605 = _T_1581 | _T_1604; // @[dec_dec_ctl.scala 126:96]
|
|
wire _T_1615 = io_ins[25] & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1616 = _T_1615 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1617 = _T_1616 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1618 = _T_1617 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1619 = _T_1618 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1620 = _T_1605 | _T_1619; // @[dec_dec_ctl.scala 127:50]
|
|
wire _T_1635 = io_ins[30] & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1636 = _T_1635 & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1637 = _T_1636 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1638 = _T_1637 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1639 = _T_1638 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1640 = _T_1639 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1641 = _T_1640 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1642 = _T_1641 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1643 = _T_1620 | _T_1642; // @[dec_dec_ctl.scala 127:84]
|
|
wire _T_1653 = _T_65 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1654 = _T_1653 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1655 = _T_1654 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1656 = _T_1655 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1673 = _T_781 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1674 = _T_1673 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1675 = _T_1674 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1676 = _T_1675 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1677 = _T_1676 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1678 = _T_1677 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1679 = _T_1678 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1695 = _T_1673 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1696 = _T_1695 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1697 = _T_1696 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1698 = _T_1697 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1699 = _T_1698 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1733 = _T_1615 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1734 = _T_1733 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1735 = _T_1734 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1736 = _T_1735 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1749 = _T_782 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1750 = _T_1749 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1764 = _T_782 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1765 = _T_1764 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1766 = _T_1765 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1800 = _T_1635 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1801 = _T_1800 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1802 = _T_1801 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1803 = _T_1802 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1804 = _T_1803 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1805 = _T_1804 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1806 = _T_1805 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1807 = _T_1806 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1808 = _T_1807 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1831 = _T_1801 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1832 = _T_1831 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1833 = _T_1832 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1834 = _T_1833 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1835 = _T_1834 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1836 = _T_1835 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1856 = _T_1800 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1857 = _T_1856 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1858 = _T_1857 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1859 = _T_1858 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1860 = _T_1859 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1861 = _T_1860 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1880 = _T_1635 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1881 = _T_1880 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1882 = _T_1881 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1883 = _T_1882 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1884 = _T_1883 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1885 = _T_1884 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1886 = _T_1885 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1905 = _T_1880 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1906 = _T_1905 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1907 = _T_1906 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1908 = _T_1907 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1909 = _T_1908 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1910 = _T_1909 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1928 = _T_158 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1969 = _T_57 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1970 = _T_1969 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1971 = _T_1970 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1984 = _T_57 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1985 = _T_1984 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_1986 = _T_1985 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2002 = _T_1370 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2003 = _T_2002 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2004 = _T_2003 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2005 = _T_2004 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2006 = _T_2005 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2019 = _T_1457 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2020 = _T_2019 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2021 = _T_2020 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2022 = _T_2021 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2038 = _T_2002 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2039 = _T_2038 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2040 = _T_2039 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2041 = _T_2040 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2056 = _T_1635 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2057 = _T_2056 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2058 = _T_2057 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2059 = _T_2058 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2060 = _T_2059 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2076 = _T_1550 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2077 = _T_2076 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2078 = _T_2077 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2079 = _T_2078 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2080 = _T_2079 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2081 = _T_2080 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2100 = _T_1800 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2101 = _T_2100 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2102 = _T_2101 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2103 = _T_2102 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2104 = _T_2103 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2105 = _T_2104 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2118 = _T_1370 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2119 = _T_2118 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2120 = _T_2119 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2121 = _T_2120 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2122 = _T_2121 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2123 = _T_2122 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2124 = _T_2105 | _T_2123; // @[dec_dec_ctl.scala 172:62]
|
|
wire _T_2143 = _T_2079 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2144 = _T_2143 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2145 = _T_2144 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2146 = _T_2124 | _T_2145; // @[dec_dec_ctl.scala 172:103]
|
|
wire _T_2157 = _T_357 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2158 = _T_2157 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2159 = _T_2158 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2160 = _T_2159 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2161 = _T_2146 | _T_2160; // @[dec_dec_ctl.scala 173:48]
|
|
wire _T_2173 = io_ins[30] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2174 = _T_2173 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2175 = _T_2174 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2176 = _T_2175 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2177 = _T_2176 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2178 = _T_2177 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2179 = _T_2161 | _T_2178; // @[dec_dec_ctl.scala 173:83]
|
|
wire _T_2191 = _T_1635 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2192 = _T_2191 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2193 = _T_2192 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2194 = _T_2193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2195 = _T_2194 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2196 = _T_2179 | _T_2195; // @[dec_dec_ctl.scala 174:42]
|
|
wire _T_2209 = _T_2076 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2210 = _T_2209 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2211 = _T_2210 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2212 = _T_2211 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2213 = _T_2196 | _T_2212; // @[dec_dec_ctl.scala 174:79]
|
|
wire _T_2231 = _T_1550 & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2232 = _T_2231 & io_ins[23]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2233 = _T_2232 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2234 = _T_2233 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2235 = _T_2234 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2236 = _T_2235 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2237 = _T_2236 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2238 = _T_2237 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2239 = _T_2238 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2240 = _T_2239 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2241 = _T_2240 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2242 = _T_2213 | _T_2241; // @[dec_dec_ctl.scala 175:40]
|
|
wire _T_2264 = _T_158 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2265 = _T_2264 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2266 = _T_2265 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2267 = _T_2266 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2268 = _T_2267 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2269 = _T_2268 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2270 = _T_2269 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2271 = _T_2270 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2272 = _T_2271 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2273 = _T_2272 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2274 = _T_2273 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2275 = _T_2274 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2276 = _T_2242 | _T_2275; // @[dec_dec_ctl.scala 175:96]
|
|
wire _T_2300 = _T_1371 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2301 = _T_2300 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2302 = _T_2301 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2303 = _T_2302 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2304 = _T_2303 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2305 = _T_2304 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2306 = _T_2305 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2307 = _T_2306 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2308 = _T_2307 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2309 = _T_2308 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2310 = _T_2276 | _T_2309; // @[dec_dec_ctl.scala 176:65]
|
|
wire _T_2333 = _T_2232 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2334 = _T_2333 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2335 = _T_2334 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2336 = _T_2335 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2337 = _T_2336 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2338 = _T_2337 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2339 = _T_2338 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2340 = _T_2339 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2341 = _T_2340 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2342 = _T_2310 | _T_2341; // @[dec_dec_ctl.scala 177:64]
|
|
wire _T_2373 = _T_2264 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2374 = _T_2373 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2375 = _T_2374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2376 = _T_2375 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2377 = _T_2376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2393 = _T_94 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2394 = _T_2393 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2395 = _T_2394 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2396 = _T_2395 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2397 = _T_2396 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2414 = _T_1551 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2415 = _T_2414 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2416 = _T_2415 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2417 = _T_2416 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2418 = _T_2417 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2434 = _T_94 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2435 = _T_2434 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2436 = _T_2435 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2437 = _T_2436 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2438 = _T_2437 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2439 = _T_2438 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2455 = _T_66 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2456 = _T_2455 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2457 = _T_2456 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2458 = _T_2457 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2459 = _T_2458 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2474 = _T_2434 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2475 = _T_2474 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2476 = _T_2475 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2477 = _T_2476 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2478 = _T_2477 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2552 = _T_56 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2603 = _T_2552 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2604 = _T_2603 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2605 = _T_2604 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2621 = _T_1551 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2622 = _T_2621 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2623 = _T_2622 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2624 = _T_2623 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2625 = _T_2624 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2642 = _T_2264 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2643 = _T_2642 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2644 = _T_2643 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2645 = _T_2644 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2646 = _T_2645 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2714 = _T_1928 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2715 = _T_2714 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2716 = _T_2715 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2717 = _T_2716 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2718 = _T_2717 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2734 = _T_1598 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2735 = _T_2734 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2736 = _T_2735 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2737 = _T_2736 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2738 = _T_2737 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2739 = _T_2718 | _T_2738; // @[dec_dec_ctl.scala 212:58]
|
|
wire _T_2756 = _T_2739 | _T_2195; // @[dec_dec_ctl.scala 212:101]
|
|
wire _T_2769 = _T_1440 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2770 = _T_2769 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2771 = _T_2770 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2772 = _T_2771 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2773 = _T_2772 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2774 = _T_2756 | _T_2773; // @[dec_dec_ctl.scala 213:40]
|
|
wire _T_2788 = _T_2175 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2789 = _T_2788 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2790 = _T_2789 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2791 = _T_2774 | _T_2790; // @[dec_dec_ctl.scala 213:79]
|
|
wire _T_2803 = _T_27 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2804 = _T_2803 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2805 = _T_2804 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2806 = _T_2805 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2807 = _T_2806 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2808 = _T_2791 | _T_2807; // @[dec_dec_ctl.scala 214:41]
|
|
wire _T_2826 = _T_1599 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2827 = _T_2826 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2828 = _T_2827 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2829 = _T_2828 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2830 = _T_2829 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2831 = _T_2808 | _T_2830; // @[dec_dec_ctl.scala 214:78]
|
|
wire _T_2842 = io_ins[29] & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2843 = _T_2842 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2844 = _T_2843 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2845 = _T_2844 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2846 = _T_2845 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_2847 = _T_2846 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3043 = _T_1458 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3044 = _T_3043 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3045 = _T_3044 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3117 = io_ins[29] & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3118 = _T_3117 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3119 = _T_3118 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3120 = _T_3119 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3129 = io_ins[28] & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3130 = _T_3129 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3131 = _T_3130 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3132 = _T_3131 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3147 = _T_733 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3148 = _T_3147 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3149 = _T_3132 | _T_3148; // @[dec_dec_ctl.scala 243:51]
|
|
wire _T_3164 = _T_597 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3165 = _T_3164 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3166 = _T_3165 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3167 = _T_3166 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3168 = _T_3149 | _T_3167; // @[dec_dec_ctl.scala 243:89]
|
|
wire _T_3183 = _T_688 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3184 = _T_3183 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3185 = _T_3168 | _T_3184; // @[dec_dec_ctl.scala 244:44]
|
|
wire _T_3192 = _T_3185 | _T_114; // @[dec_dec_ctl.scala 244:82]
|
|
wire _T_3196 = _T_3192 | _T_398; // @[dec_dec_ctl.scala 245:28]
|
|
wire _T_3206 = ~io_ins[31]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3215 = ~io_ins[26]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3227 = ~io_ins[19]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3229 = ~io_ins[18]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3231 = ~io_ins[17]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3233 = ~io_ins[16]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3235 = ~io_ins[15]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3239 = ~io_ins[11]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3241 = ~io_ins[10]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3243 = ~io_ins[9]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3245 = ~io_ins[8]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3247 = ~io_ins[7]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3257 = _T_3206 & _T_43; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3258 = _T_3257 & _T_90; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3259 = _T_3258 & io_ins[28]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3260 = _T_3259 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3261 = _T_3260 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3262 = _T_3261 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3263 = _T_3262 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3264 = _T_3263 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3265 = _T_3264 & io_ins[22]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3266 = _T_3265 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3267 = _T_3266 & io_ins[20]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3268 = _T_3267 & _T_3227; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3269 = _T_3268 & _T_3229; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3270 = _T_3269 & _T_3231; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3271 = _T_3270 & _T_3233; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3272 = _T_3271 & _T_3235; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3273 = _T_3272 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3274 = _T_3273 & _T_3239; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3275 = _T_3274 & _T_3241; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3276 = _T_3275 & _T_3243; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3277 = _T_3276 & _T_3245; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3278 = _T_3277 & _T_3247; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3279 = _T_3278 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3280 = _T_3279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3281 = _T_3280 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3282 = _T_3281 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3283 = _T_3282 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3284 = _T_3283 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3285 = _T_3284 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3339 = _T_3257 & io_ins[29]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3340 = _T_3339 & io_ins[28]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3341 = _T_3340 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3342 = _T_3341 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3343 = _T_3342 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3344 = _T_3343 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3345 = _T_3344 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3346 = _T_3345 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3347 = _T_3346 & io_ins[21]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3348 = _T_3347 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3349 = _T_3348 & _T_3227; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3350 = _T_3349 & _T_3229; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3351 = _T_3350 & _T_3231; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3352 = _T_3351 & _T_3233; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3353 = _T_3352 & _T_3235; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3354 = _T_3353 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3355 = _T_3354 & _T_3239; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3356 = _T_3355 & _T_3241; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3357 = _T_3356 & _T_3243; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3358 = _T_3357 & _T_3245; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3359 = _T_3358 & _T_3247; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3360 = _T_3359 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3361 = _T_3360 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3362 = _T_3361 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3363 = _T_3362 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3364 = _T_3363 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3365 = _T_3364 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3366 = _T_3365 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3367 = _T_3285 | _T_3366; // @[dec_dec_ctl.scala 248:136]
|
|
wire _T_3375 = ~io_ins[28]; // @[dec_dec_ctl.scala 15:46]
|
|
wire _T_3422 = _T_3258 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3423 = _T_3422 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3424 = _T_3423 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3425 = _T_3424 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3426 = _T_3425 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3427 = _T_3426 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3428 = _T_3427 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3429 = _T_3428 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3430 = _T_3429 & _T_3227; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3431 = _T_3430 & _T_3229; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3432 = _T_3431 & _T_3231; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3433 = _T_3432 & _T_3233; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3434 = _T_3433 & _T_3235; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3435 = _T_3434 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3436 = _T_3435 & _T_3239; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3437 = _T_3436 & _T_3241; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3438 = _T_3437 & _T_3243; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3439 = _T_3438 & _T_3245; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3440 = _T_3439 & _T_3247; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3441 = _T_3440 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3442 = _T_3441 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3443 = _T_3442 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3444 = _T_3443 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3445 = _T_3444 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3446 = _T_3445 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3447 = _T_3367 | _T_3446; // @[dec_dec_ctl.scala 249:122]
|
|
wire _T_3471 = _T_3206 & io_ins[29]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3472 = _T_3471 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3473 = _T_3472 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3474 = _T_3473 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3475 = _T_3474 & io_ins[24]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3476 = _T_3475 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3477 = _T_3476 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3478 = _T_3477 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3479 = _T_3478 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3480 = _T_3479 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3481 = _T_3480 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3482 = _T_3481 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3483 = _T_3482 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3484 = _T_3447 | _T_3483; // @[dec_dec_ctl.scala 250:119]
|
|
wire _T_3514 = _T_3476 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3515 = _T_3514 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3516 = _T_3515 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3517 = _T_3516 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3518 = _T_3517 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3519 = _T_3518 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3520 = _T_3519 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3521 = _T_3484 | _T_3520; // @[dec_dec_ctl.scala 251:65]
|
|
wire _T_3550 = _T_3474 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3551 = _T_3550 & _T_4; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3552 = _T_3551 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3553 = _T_3552 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3554 = _T_3553 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3555 = _T_3554 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3556 = _T_3555 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3557 = _T_3556 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3558 = _T_3557 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3559 = _T_3521 | _T_3558; // @[dec_dec_ctl.scala 251:127]
|
|
wire _T_3588 = _T_3474 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3589 = _T_3588 & _T_151; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3590 = _T_3589 & _T_6; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3591 = _T_3590 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3592 = _T_3591 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3593 = _T_3592 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3594 = _T_3593 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3595 = _T_3594 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3596 = _T_3595 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3597 = _T_3559 | _T_3596; // @[dec_dec_ctl.scala 252:66]
|
|
wire _T_3620 = _T_3422 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3621 = _T_3620 & io_ins[25]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3622 = _T_3621 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3623 = _T_3622 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3624 = _T_3623 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3625 = _T_3624 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3626 = _T_3625 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3627 = _T_3626 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3628 = _T_3597 | _T_3627; // @[dec_dec_ctl.scala 252:129]
|
|
wire _T_3651 = _T_3257 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3652 = _T_3651 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3653 = _T_3652 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3654 = _T_3653 & _T_25; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3655 = _T_3654 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3656 = _T_3655 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3657 = _T_3656 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3658 = _T_3657 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3659 = _T_3658 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3660 = _T_3659 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3661 = _T_3628 | _T_3660; // @[dec_dec_ctl.scala 253:58]
|
|
wire _T_3686 = _T_3651 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3687 = _T_3686 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3688 = _T_3687 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3689 = _T_3688 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3690 = _T_3689 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3691 = _T_3690 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3692 = _T_3691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3693 = _T_3692 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3694 = _T_3693 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3695 = _T_3694 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3696 = _T_3661 | _T_3695; // @[dec_dec_ctl.scala 253:114]
|
|
wire _T_3724 = _T_3688 & io_ins[13]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3725 = _T_3724 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3726 = _T_3725 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3727 = _T_3726 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3728 = _T_3727 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3729 = _T_3728 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3730 = _T_3729 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3731 = _T_3696 | _T_3730; // @[dec_dec_ctl.scala 254:63]
|
|
wire _T_3755 = _T_3206 & _T_90; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3756 = _T_3755 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3757 = _T_3756 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3758 = _T_3757 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3759 = _T_3758 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3760 = _T_3759 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3761 = _T_3760 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3762 = _T_3761 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3763 = _T_3762 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3764 = _T_3763 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3765 = _T_3764 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3766 = _T_3765 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3767 = _T_3731 | _T_3766; // @[dec_dec_ctl.scala 254:123]
|
|
wire _T_3788 = _T_3206 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3789 = _T_3788 & _T_23; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3790 = _T_3789 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3791 = _T_3790 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3792 = _T_3791 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3793 = _T_3792 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3794 = _T_3793 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3795 = _T_3794 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3796 = _T_3795 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3797 = _T_3796 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3798 = _T_3797 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3799 = _T_3767 | _T_3798; // @[dec_dec_ctl.scala 255:64]
|
|
wire _T_3825 = _T_3620 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3826 = _T_3825 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3827 = _T_3826 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3828 = _T_3827 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3829 = _T_3828 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3830 = _T_3829 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3831 = _T_3830 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3832 = _T_3831 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3833 = _T_3799 | _T_3832; // @[dec_dec_ctl.scala 255:119]
|
|
wire _T_3857 = _T_3620 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3858 = _T_3857 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3859 = _T_3858 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3860 = _T_3859 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3861 = _T_3860 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3862 = _T_3861 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3863 = _T_3862 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3864 = _T_3833 | _T_3863; // @[dec_dec_ctl.scala 256:61]
|
|
wire _T_3885 = _T_3206 & io_ins[30]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3886 = _T_3885 & _T_3375; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3887 = _T_3886 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3888 = _T_3887 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3889 = _T_3888 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3890 = _T_3889 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3891 = _T_3890 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3892 = _T_3891 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3893 = _T_3892 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3894 = _T_3893 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3895 = _T_3894 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3896 = _T_3895 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3897 = _T_3864 | _T_3896; // @[dec_dec_ctl.scala 256:115]
|
|
wire _T_3919 = _T_3472 & io_ins[27]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3920 = _T_3919 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3921 = _T_3920 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3922 = _T_3921 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3923 = _T_3922 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3924 = _T_3923 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3925 = _T_3924 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3926 = _T_3925 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3927 = _T_3926 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3928 = _T_3897 | _T_3927; // @[dec_dec_ctl.scala 257:61]
|
|
wire _T_3955 = _T_3688 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3956 = _T_3955 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3957 = _T_3956 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3958 = _T_3957 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3959 = _T_3958 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3960 = _T_3959 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3961 = _T_3928 | _T_3960; // @[dec_dec_ctl.scala 257:116]
|
|
wire _T_3987 = _T_3424 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3988 = _T_3987 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3989 = _T_3988 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3990 = _T_3989 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3991 = _T_3990 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3992 = _T_3991 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_3993 = _T_3961 | _T_3992; // @[dec_dec_ctl.scala 258:59]
|
|
wire _T_4010 = _T_444 & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4011 = _T_4010 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4012 = _T_4011 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4013 = _T_4012 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4014 = _T_4013 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4015 = _T_4014 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4016 = _T_3993 | _T_4015; // @[dec_dec_ctl.scala 258:114]
|
|
wire _T_4038 = _T_3756 & _T_3215; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4039 = _T_4038 & _T_32; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4040 = _T_4039 & io_ins[14]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4041 = _T_4040 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4042 = _T_4041 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4043 = _T_4042 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4044 = _T_4043 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4045 = _T_4044 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4046 = _T_4045 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4047 = _T_4016 | _T_4046; // @[dec_dec_ctl.scala 259:46]
|
|
wire _T_4072 = _T_3474 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4073 = _T_4072 & io_ins[12]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4074 = _T_4073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4075 = _T_4074 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4076 = _T_4075 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4077 = _T_4076 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4078 = _T_4077 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4079 = _T_4078 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4080 = _T_4047 | _T_4079; // @[dec_dec_ctl.scala 259:100]
|
|
wire _T_4092 = io_ins[14] & io_ins[6]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4093 = _T_4092 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4094 = _T_4093 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4095 = _T_4094 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4096 = _T_4095 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4097 = _T_4096 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4098 = _T_4097 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4099 = _T_4080 | _T_4098; // @[dec_dec_ctl.scala 260:60]
|
|
wire _T_4114 = _T_195 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4115 = _T_4114 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4116 = _T_4115 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4117 = _T_4116 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4118 = _T_4117 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4119 = _T_4118 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4120 = _T_4099 | _T_4119; // @[dec_dec_ctl.scala 260:97]
|
|
wire _T_4132 = _T_36 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4133 = _T_4132 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4134 = _T_4133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4135 = _T_4134 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4136 = _T_4135 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4137 = _T_4136 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4138 = _T_4120 | _T_4137; // @[dec_dec_ctl.scala 261:43]
|
|
wire _T_4152 = _T_1073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4153 = _T_4152 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4154 = _T_4153 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4155 = _T_4154 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4156 = _T_4155 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4157 = _T_4138 | _T_4156; // @[dec_dec_ctl.scala 261:79]
|
|
wire _T_4226 = _T_3429 & _T_8; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4227 = _T_4226 & _T_3227; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4228 = _T_4227 & _T_3229; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4229 = _T_4228 & _T_3231; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4230 = _T_4229 & _T_3233; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4231 = _T_4230 & _T_3235; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4232 = _T_4231 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4233 = _T_4232 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4234 = _T_4233 & _T_3239; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4235 = _T_4234 & _T_3241; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4236 = _T_4235 & _T_3243; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4237 = _T_4236 & _T_3245; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4238 = _T_4237 & _T_3247; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4239 = _T_4238 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4240 = _T_4239 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4241 = _T_4240 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4242 = _T_4241 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4243 = _T_4242 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4244 = _T_4243 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4245 = _T_4244 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4246 = _T_4157 | _T_4245; // @[dec_dec_ctl.scala 261:117]
|
|
wire _T_4294 = _T_3422 & _T_3227; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4295 = _T_4294 & _T_3229; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4296 = _T_4295 & _T_3231; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4297 = _T_4296 & _T_3233; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4298 = _T_4297 & _T_3235; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4299 = _T_4298 & _T_63; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4300 = _T_4299 & _T_34; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4301 = _T_4300 & _T_36; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4302 = _T_4301 & _T_3239; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4303 = _T_4302 & _T_3241; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4304 = _T_4303 & _T_3243; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4305 = _T_4304 & _T_3245; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4306 = _T_4305 & _T_3247; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4307 = _T_4306 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4308 = _T_4307 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4309 = _T_4308 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4310 = _T_4309 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4311 = _T_4310 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4312 = _T_4311 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4313 = _T_4312 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4314 = _T_4246 | _T_4313; // @[dec_dec_ctl.scala 262:130]
|
|
wire _T_4326 = _T_806 & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4327 = _T_4326 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4328 = _T_4327 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4329 = _T_4328 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4330 = _T_4329 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4331 = _T_4330 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4332 = _T_4314 | _T_4331; // @[dec_dec_ctl.scala 263:102]
|
|
wire _T_4341 = io_ins[6] & io_ins[5]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4342 = _T_4341 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4343 = _T_4342 & io_ins[3]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4344 = _T_4343 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4345 = _T_4344 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4346 = _T_4345 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4347 = _T_4332 | _T_4346; // @[dec_dec_ctl.scala 264:39]
|
|
wire _T_4363 = _T_866 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4364 = _T_4363 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4365 = _T_4364 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4366 = _T_4365 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4367 = _T_4366 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4368 = _T_4367 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4369 = _T_4347 | _T_4368; // @[dec_dec_ctl.scala 264:71]
|
|
wire _T_4384 = _T_34 & _T_279; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4385 = _T_4384 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4386 = _T_4385 & _T_273; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4387 = _T_4386 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4388 = _T_4387 & _T_194; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4389 = _T_4388 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4390 = _T_4389 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4391 = _T_4369 | _T_4390; // @[dec_dec_ctl.scala 264:112]
|
|
wire _T_4403 = _T_937 & _T_11; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4404 = _T_4403 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4405 = _T_4404 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4406 = _T_4405 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4407 = _T_4406 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4408 = _T_4391 | _T_4407; // @[dec_dec_ctl.scala 265:43]
|
|
wire _T_4417 = _T_279 & io_ins[4]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4418 = _T_4417 & _T_275; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4419 = _T_4418 & io_ins[2]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4420 = _T_4419 & io_ins[1]; // @[dec_dec_ctl.scala 17:17]
|
|
wire _T_4421 = _T_4420 & io_ins[0]; // @[dec_dec_ctl.scala 17:17]
|
|
assign io_out_clz = _T_1808 & _T_194; // @[dec_dec_ctl.scala 144:14]
|
|
assign io_out_ctz = _T_1836 & _T_194; // @[dec_dec_ctl.scala 146:14]
|
|
assign io_out_pcnt = _T_1861 & _T_194; // @[dec_dec_ctl.scala 148:15]
|
|
assign io_out_sext_b = _T_1886 & _T_194; // @[dec_dec_ctl.scala 150:17]
|
|
assign io_out_sext_h = _T_1910 & _T_194; // @[dec_dec_ctl.scala 152:17]
|
|
assign io_out_min = _T_1971 & _T_194; // @[dec_dec_ctl.scala 158:14]
|
|
assign io_out_max = _T_1986 & _T_194; // @[dec_dec_ctl.scala 160:14]
|
|
assign io_out_pack = _T_2006 & _T_194; // @[dec_dec_ctl.scala 162:15]
|
|
assign io_out_packu = _T_2022 & _T_194; // @[dec_dec_ctl.scala 164:16]
|
|
assign io_out_packh = _T_2041 & _T_194; // @[dec_dec_ctl.scala 166:16]
|
|
assign io_out_rol = _T_2060 & _T_194; // @[dec_dec_ctl.scala 168:14]
|
|
assign io_out_ror = _T_2081 & _T_194; // @[dec_dec_ctl.scala 170:14]
|
|
assign io_out_grev = _T_2625 & _T_194; // @[dec_dec_ctl.scala 204:15]
|
|
assign io_out_gorc = _T_2646 & _T_194; // @[dec_dec_ctl.scala 206:15]
|
|
assign io_out_zbb = _T_2342 | _T_526; // @[dec_dec_ctl.scala 172:14]
|
|
assign io_out_sbset = _T_2377 & _T_194; // @[dec_dec_ctl.scala 180:16]
|
|
assign io_out_sbclr = _T_2397 & _T_194; // @[dec_dec_ctl.scala 182:16]
|
|
assign io_out_sbinv = _T_2418 & _T_194; // @[dec_dec_ctl.scala 184:16]
|
|
assign io_out_sbext = _T_2439 & _T_194; // @[dec_dec_ctl.scala 186:16]
|
|
assign io_out_zbs = _T_2459 | _T_2478; // @[dec_dec_ctl.scala 188:14]
|
|
assign io_out_zbe = _T_1445 & _T_194; // @[dec_dec_ctl.scala 194:14]
|
|
assign io_out_zbc = _T_2605 & _T_194; // @[dec_dec_ctl.scala 202:14]
|
|
assign io_out_zbp = _T_2831 | _T_2847; // @[dec_dec_ctl.scala 212:14]
|
|
assign io_out_zbr = _T_1641 & _T_194; // @[dec_dec_ctl.scala 229:14]
|
|
assign io_out_zbf = _T_3045 & _T_194; // @[dec_dec_ctl.scala 233:14]
|
|
assign io_out_zba = _T_3120 & _T_194; // @[dec_dec_ctl.scala 241:14]
|
|
assign io_out_alu = _T_166 | _T_187; // @[dec_dec_ctl.scala 20:14]
|
|
assign io_out_rs1 = _T_277 | _T_282; // @[dec_dec_ctl.scala 27:14]
|
|
assign io_out_rs2 = _T_290 | _T_297; // @[dec_dec_ctl.scala 32:14]
|
|
assign io_out_imm12 = _T_325 | _T_335; // @[dec_dec_ctl.scala 34:16]
|
|
assign io_out_rd = _T_345 | io_ins[4]; // @[dec_dec_ctl.scala 36:13]
|
|
assign io_out_shimm5 = _T_377 | _T_391; // @[dec_dec_ctl.scala 38:17]
|
|
assign io_out_imm20 = _T_395 | _T_398; // @[dec_dec_ctl.scala 40:16]
|
|
assign io_out_pc = _T_406 | _T_395; // @[dec_dec_ctl.scala 42:13]
|
|
assign io_out_load = _T_417 & _T_194; // @[dec_dec_ctl.scala 44:15]
|
|
assign io_out_store = _T_296 & _T_273; // @[dec_dec_ctl.scala 46:16]
|
|
assign io_out_lsu = _T_432 & _T_194; // @[dec_dec_ctl.scala 48:14]
|
|
assign io_out_add = _T_454 | _T_476; // @[dec_dec_ctl.scala 50:14]
|
|
assign io_out_sub = _T_540 | _T_547; // @[dec_dec_ctl.scala 52:14]
|
|
assign io_out_land = _T_565 | _T_576; // @[dec_dec_ctl.scala 55:15]
|
|
assign io_out_lor = _T_619 | _T_631; // @[dec_dec_ctl.scala 57:14]
|
|
assign io_out_lxor = _T_653 | _T_668; // @[dec_dec_ctl.scala 60:15]
|
|
assign io_out_sll = _T_692 & _T_194; // @[dec_dec_ctl.scala 62:14]
|
|
assign io_out_sra = _T_712 & _T_194; // @[dec_dec_ctl.scala 64:14]
|
|
assign io_out_srl = _T_738 & _T_194; // @[dec_dec_ctl.scala 66:14]
|
|
assign io_out_slt = _T_512 | _T_539; // @[dec_dec_ctl.scala 68:14]
|
|
assign io_out_unsign = _T_833 | _T_848; // @[dec_dec_ctl.scala 70:17]
|
|
assign io_out_condbr = _T_546 & _T_194; // @[dec_dec_ctl.scala 74:17]
|
|
assign io_out_beq = _T_868 & _T_194; // @[dec_dec_ctl.scala 76:14]
|
|
assign io_out_bne = _T_880 & _T_194; // @[dec_dec_ctl.scala 78:14]
|
|
assign io_out_bge = _T_891 & _T_194; // @[dec_dec_ctl.scala 80:14]
|
|
assign io_out_blt = _T_903 & _T_194; // @[dec_dec_ctl.scala 82:14]
|
|
assign io_out_jal = io_ins[6] & io_ins[2]; // @[dec_dec_ctl.scala 84:14]
|
|
assign io_out_by = _T_920 & _T_194; // @[dec_dec_ctl.scala 86:13]
|
|
assign io_out_half = _T_930 & _T_194; // @[dec_dec_ctl.scala 88:15]
|
|
assign io_out_word = _T_937 & _T_273; // @[dec_dec_ctl.scala 90:15]
|
|
assign io_out_csr_read = _T_967 | _T_972; // @[dec_dec_ctl.scala 92:19]
|
|
assign io_out_csr_clr = _T_1012 | _T_1021; // @[dec_dec_ctl.scala 95:18]
|
|
assign io_out_csr_set = _T_1057 | _T_1065; // @[dec_dec_ctl.scala 98:18]
|
|
assign io_out_csr_write = _T_1073 & io_ins[4]; // @[dec_dec_ctl.scala 101:20]
|
|
assign io_out_csr_imm = _T_1114 | _T_1121; // @[dec_dec_ctl.scala 103:18]
|
|
assign io_out_presync = _T_1203 | _T_1210; // @[dec_dec_ctl.scala 106:18]
|
|
assign io_out_postsync = _T_1307 | _T_1210; // @[dec_dec_ctl.scala 111:19]
|
|
assign io_out_ebreak = _T_1328 & io_ins[4]; // @[dec_dec_ctl.scala 116:17]
|
|
assign io_out_ecall = _T_1343 & io_ins[4]; // @[dec_dec_ctl.scala 118:16]
|
|
assign io_out_mret = _T_1354 & io_ins[4]; // @[dec_dec_ctl.scala 120:15]
|
|
assign io_out_mul = _T_1643 | _T_1656; // @[dec_dec_ctl.scala 122:14]
|
|
assign io_out_rs1_sign = _T_1679 | _T_1699; // @[dec_dec_ctl.scala 130:19]
|
|
assign io_out_rs2_sign = _T_1698 & _T_194; // @[dec_dec_ctl.scala 132:19]
|
|
assign io_out_low = _T_1736 & _T_194; // @[dec_dec_ctl.scala 134:14]
|
|
assign io_out_div = _T_1750 & _T_194; // @[dec_dec_ctl.scala 136:14]
|
|
assign io_out_rem = _T_1766 & _T_194; // @[dec_dec_ctl.scala 138:14]
|
|
assign io_out_fence = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 140:16]
|
|
assign io_out_fence_i = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 142:18]
|
|
assign io_out_pm_alu = _T_3196 | _T_122; // @[dec_dec_ctl.scala 243:17]
|
|
assign io_out_legal = _T_4408 | _T_4421; // @[dec_dec_ctl.scala 248:16]
|
|
endmodule
|
|
module dec_decode_ctl(
|
|
input clock,
|
|
input reset,
|
|
output [1:0] io_decode_exu_dec_data_en,
|
|
output [1:0] io_decode_exu_dec_ctl_en,
|
|
output io_decode_exu_i0_ap_clz,
|
|
output io_decode_exu_i0_ap_ctz,
|
|
output io_decode_exu_i0_ap_pcnt,
|
|
output io_decode_exu_i0_ap_sext_b,
|
|
output io_decode_exu_i0_ap_sext_h,
|
|
output io_decode_exu_i0_ap_min,
|
|
output io_decode_exu_i0_ap_max,
|
|
output io_decode_exu_i0_ap_pack,
|
|
output io_decode_exu_i0_ap_packu,
|
|
output io_decode_exu_i0_ap_packh,
|
|
output io_decode_exu_i0_ap_rol,
|
|
output io_decode_exu_i0_ap_ror,
|
|
output io_decode_exu_i0_ap_grev,
|
|
output io_decode_exu_i0_ap_gorc,
|
|
output io_decode_exu_i0_ap_zbb,
|
|
output io_decode_exu_i0_ap_sbset,
|
|
output io_decode_exu_i0_ap_sbclr,
|
|
output io_decode_exu_i0_ap_sbinv,
|
|
output io_decode_exu_i0_ap_sbext,
|
|
output io_decode_exu_i0_ap_land,
|
|
output io_decode_exu_i0_ap_lor,
|
|
output io_decode_exu_i0_ap_lxor,
|
|
output io_decode_exu_i0_ap_sll,
|
|
output io_decode_exu_i0_ap_srl,
|
|
output io_decode_exu_i0_ap_sra,
|
|
output io_decode_exu_i0_ap_beq,
|
|
output io_decode_exu_i0_ap_bne,
|
|
output io_decode_exu_i0_ap_blt,
|
|
output io_decode_exu_i0_ap_bge,
|
|
output io_decode_exu_i0_ap_add,
|
|
output io_decode_exu_i0_ap_sub,
|
|
output io_decode_exu_i0_ap_slt,
|
|
output io_decode_exu_i0_ap_unsign,
|
|
output io_decode_exu_i0_ap_jal,
|
|
output io_decode_exu_i0_ap_predict_t,
|
|
output io_decode_exu_i0_ap_predict_nt,
|
|
output io_decode_exu_i0_ap_csr_write,
|
|
output io_decode_exu_i0_ap_csr_imm,
|
|
output io_decode_exu_dec_i0_predict_p_d_valid,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_pc4,
|
|
output [1:0] io_decode_exu_dec_i0_predict_p_d_bits_hist,
|
|
output [11:0] io_decode_exu_dec_i0_predict_p_d_bits_toffset,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_br_error,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_br_start_error,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_pcall,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_pja,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_way,
|
|
output io_decode_exu_dec_i0_predict_p_d_bits_pret,
|
|
output [30:0] io_decode_exu_dec_i0_predict_p_d_bits_prett,
|
|
output [7:0] io_decode_exu_i0_predict_fghr_d,
|
|
output [7:0] io_decode_exu_i0_predict_index_d,
|
|
output [4:0] io_decode_exu_i0_predict_btag_d,
|
|
output io_decode_exu_dec_i0_rs1_en_d,
|
|
output io_decode_exu_dec_i0_branch_d,
|
|
output io_decode_exu_dec_i0_rs2_en_d,
|
|
output [31:0] io_decode_exu_dec_i0_immed_d,
|
|
output [31:0] io_decode_exu_dec_i0_result_r,
|
|
output io_decode_exu_dec_qual_lsu_d,
|
|
output io_decode_exu_dec_i0_select_pc_d,
|
|
output [3:0] io_decode_exu_dec_i0_rs1_bypass_en_d,
|
|
output [3:0] io_decode_exu_dec_i0_rs2_bypass_en_d,
|
|
output io_decode_exu_mul_p_valid,
|
|
output io_decode_exu_mul_p_bits_rs1_sign,
|
|
output io_decode_exu_mul_p_bits_rs2_sign,
|
|
output io_decode_exu_mul_p_bits_low,
|
|
output [30:0] io_decode_exu_pred_correct_npc_x,
|
|
output io_decode_exu_dec_extint_stall,
|
|
input [31:0] io_decode_exu_exu_i0_result_x,
|
|
input [31:0] io_decode_exu_exu_csr_rs1_x,
|
|
output io_dec_alu_dec_i0_alu_decode_d,
|
|
output io_dec_alu_dec_csr_ren_d,
|
|
output [11:0] io_dec_alu_dec_i0_br_immed_d,
|
|
input [30:0] io_dec_alu_exu_i0_pc_x,
|
|
output io_dec_div_div_p_valid,
|
|
output io_dec_div_div_p_bits_unsign,
|
|
output io_dec_div_div_p_bits_rem,
|
|
output io_dec_div_dec_div_cancel,
|
|
input io_dctl_busbuff_lsu_nonblock_load_valid_m,
|
|
input [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m,
|
|
input io_dctl_busbuff_lsu_nonblock_load_inv_r,
|
|
input [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r,
|
|
input io_dctl_busbuff_lsu_nonblock_load_data_valid,
|
|
input io_dctl_busbuff_lsu_nonblock_load_data_error,
|
|
input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag,
|
|
input io_dctl_dma_dma_dccm_stall_any,
|
|
input [15:0] io_dec_aln_ifu_i0_cinst,
|
|
input [31:0] io_dbg_dctl_dbg_cmd_wrdata,
|
|
input io_dec_tlu_trace_disable,
|
|
input io_dec_debug_valid_d,
|
|
input io_dec_tlu_flush_extint,
|
|
input io_dec_tlu_force_halt,
|
|
output [31:0] io_dec_i0_inst_wb,
|
|
output [30:0] io_dec_i0_pc_wb,
|
|
input [3:0] io_dec_i0_trigger_match_d,
|
|
input io_dec_tlu_wr_pause_r,
|
|
input io_dec_tlu_pipelining_disable,
|
|
input [3:0] io_lsu_trigger_match_m,
|
|
input io_lsu_pmu_misaligned_m,
|
|
input io_dec_tlu_debug_stall,
|
|
input io_dec_tlu_flush_leak_one_r,
|
|
input io_dec_debug_fence_d,
|
|
input io_dec_i0_icaf_d,
|
|
input io_dec_i0_icaf_second_d,
|
|
input [1:0] io_dec_i0_icaf_type_d,
|
|
input io_dec_i0_dbecc_d,
|
|
input io_dec_i0_brp_valid,
|
|
input [11:0] io_dec_i0_brp_bits_toffset,
|
|
input [1:0] io_dec_i0_brp_bits_hist,
|
|
input io_dec_i0_brp_bits_br_error,
|
|
input io_dec_i0_brp_bits_br_start_error,
|
|
input [30:0] io_dec_i0_brp_bits_prett,
|
|
input io_dec_i0_brp_bits_way,
|
|
input io_dec_i0_brp_bits_ret,
|
|
input [7:0] io_dec_i0_bp_index,
|
|
input [7:0] io_dec_i0_bp_fghr,
|
|
input [4:0] io_dec_i0_bp_btag,
|
|
input io_lsu_idle_any,
|
|
input io_lsu_load_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_exu_div_wren,
|
|
input io_dec_tlu_i0_kill_writeb_wb,
|
|
input io_dec_tlu_flush_lower_wb,
|
|
input io_dec_tlu_i0_kill_writeb_r,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input io_dec_tlu_flush_pause_r,
|
|
input io_dec_tlu_presync_d,
|
|
input io_dec_tlu_postsync_d,
|
|
input io_dec_i0_pc4_d,
|
|
input [31:0] io_dec_csr_rddata_d,
|
|
input io_dec_csr_legal_d,
|
|
input [31:0] io_lsu_result_m,
|
|
input [31:0] io_lsu_result_corr_r,
|
|
input io_exu_flush_final,
|
|
input [31:0] io_dec_i0_instr_d,
|
|
input io_dec_ib0_valid_d,
|
|
input io_active_clk,
|
|
input io_free_l2clk,
|
|
input io_clk_override,
|
|
output [4:0] io_dec_i0_rs1_d,
|
|
output [4:0] io_dec_i0_rs2_d,
|
|
output [4:0] io_dec_i0_waddr_r,
|
|
output io_dec_i0_wen_r,
|
|
output [31:0] io_dec_i0_wdata_r,
|
|
output io_lsu_p_valid,
|
|
output io_lsu_p_bits_fast_int,
|
|
output io_lsu_p_bits_by,
|
|
output io_lsu_p_bits_half,
|
|
output io_lsu_p_bits_word,
|
|
output io_lsu_p_bits_load,
|
|
output io_lsu_p_bits_store,
|
|
output io_lsu_p_bits_unsign,
|
|
output io_lsu_p_bits_store_data_bypass_d,
|
|
output io_lsu_p_bits_load_ldst_bypass_d,
|
|
output [4:0] io_div_waddr_wb,
|
|
output io_dec_lsu_valid_raw_d,
|
|
output [11:0] io_dec_lsu_offset_d,
|
|
output io_dec_csr_wen_unq_d,
|
|
output io_dec_csr_any_unq_d,
|
|
output [11:0] io_dec_csr_rdaddr_d,
|
|
output io_dec_csr_wen_r,
|
|
output [11:0] io_dec_csr_wraddr_r,
|
|
output [31:0] io_dec_csr_wrdata_r,
|
|
output io_dec_csr_stall_int_ff,
|
|
output io_dec_tlu_i0_valid_r,
|
|
output io_dec_tlu_packet_r_legal,
|
|
output io_dec_tlu_packet_r_icaf,
|
|
output io_dec_tlu_packet_r_icaf_second,
|
|
output [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
output io_dec_tlu_packet_r_fence_i,
|
|
output [3:0] io_dec_tlu_packet_r_i0trigger,
|
|
output [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
output io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
output io_dec_tlu_packet_r_pmu_divide,
|
|
output io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
output [30:0] io_dec_tlu_i0_pc_r,
|
|
output [31:0] io_dec_illegal_inst,
|
|
output io_dec_pmu_instr_decoded,
|
|
output io_dec_pmu_decode_stall,
|
|
output io_dec_pmu_presync_stall,
|
|
output io_dec_pmu_postsync_stall,
|
|
output io_dec_nonblock_load_wen,
|
|
output [4:0] io_dec_nonblock_load_waddr,
|
|
output io_dec_pause_state,
|
|
output io_dec_div_active,
|
|
output io_dec_i0_decode_d
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_clz; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_min; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_max; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_pack; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_packu; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_packh; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rol; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_ror; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_grev; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_zba; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 440:22]
|
|
wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 440:22]
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
reg leak1_i1_stall; // @[Reg.scala 27:20]
|
|
wire _T_367 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 447:73]
|
|
wire _T_368 = leak1_i1_stall & _T_367; // @[dec_decode_ctl.scala 447:71]
|
|
wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_368; // @[dec_decode_ctl.scala 447:53]
|
|
wire _T_2 = leak1_i1_stall_in ^ leak1_i1_stall; // @[lib.scala 466:21]
|
|
wire _T_3 = |_T_2; // @[lib.scala 466:29]
|
|
wire _T_370 = io_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 449:45]
|
|
reg leak1_i0_stall; // @[Reg.scala 27:20]
|
|
wire _T_372 = leak1_i0_stall & _T_367; // @[dec_decode_ctl.scala 449:81]
|
|
wire leak1_i0_stall_in = _T_370 | _T_372; // @[dec_decode_ctl.scala 449:63]
|
|
wire _T_6 = leak1_i0_stall_in ^ leak1_i0_stall; // @[lib.scala 466:21]
|
|
wire _T_7 = |_T_6; // @[lib.scala 466:29]
|
|
reg _T_12; // @[Reg.scala 27:20]
|
|
wire _T_10 = io_dec_tlu_flush_extint ^ _T_12; // @[lib.scala 488:21]
|
|
wire _T_11 = |_T_10; // @[lib.scala 488:29]
|
|
reg pause_stall; // @[Reg.scala 27:20]
|
|
wire _T_514 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 561:44]
|
|
wire _T_507 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 560:49]
|
|
wire _T_508 = io_dec_tlu_flush_lower_r & _T_507; // @[dec_decode_ctl.scala 560:47]
|
|
reg [31:0] write_csr_data; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_511 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58]
|
|
wire _T_512 = write_csr_data == _T_511; // @[dec_decode_ctl.scala 560:109]
|
|
wire _T_513 = pause_stall & _T_512; // @[dec_decode_ctl.scala 560:91]
|
|
wire clear_pause = _T_508 | _T_513; // @[dec_decode_ctl.scala 560:76]
|
|
wire _T_515 = ~clear_pause; // @[dec_decode_ctl.scala 561:61]
|
|
wire pause_state_in = _T_514 & _T_515; // @[dec_decode_ctl.scala 561:59]
|
|
wire _T_14 = pause_state_in ^ pause_stall; // @[lib.scala 488:21]
|
|
wire _T_15 = |_T_14; // @[lib.scala 488:29]
|
|
wire _T_50 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 224:82]
|
|
wire _T_51 = io_dec_i0_brp_valid & _T_50; // @[dec_decode_ctl.scala 224:80]
|
|
wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 222:43]
|
|
wire _T_52 = ~i0_icaf_d; // @[dec_decode_ctl.scala 224:96]
|
|
wire i0_brp_valid = _T_51 & _T_52; // @[dec_decode_ctl.scala 224:94]
|
|
wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58]
|
|
wire _T_383 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 454:79]
|
|
wire _T_385 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 454:112]
|
|
wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 454:33]
|
|
wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 455:47]
|
|
wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16]
|
|
wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 455:76]
|
|
wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 455:98]
|
|
wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 455:89]
|
|
wire i0_pcall_case = _T_386 & _T_389; // @[dec_decode_ctl.scala 455:65]
|
|
wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 457:38]
|
|
wire _T_55 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 235:94]
|
|
wire _T_394 = ~_T_389; // @[dec_decode_ctl.scala 456:67]
|
|
wire i0_pja_case = _T_386 & _T_394; // @[dec_decode_ctl.scala 456:65]
|
|
wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 459:38]
|
|
wire _T_56 = _T_55 | i0_pja_raw; // @[dec_decode_ctl.scala 235:109]
|
|
wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 463:37]
|
|
wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 463:65]
|
|
wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 463:55]
|
|
wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16]
|
|
wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 463:89]
|
|
wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 463:111]
|
|
wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 463:101]
|
|
wire i0_pret_case = _T_412 & _T_415; // @[dec_decode_ctl.scala 463:79]
|
|
wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 464:32]
|
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wire _T_57 = _T_56 | i0_pret_raw; // @[dec_decode_ctl.scala 235:122]
|
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wire _T_58 = ~_T_57; // @[dec_decode_ctl.scala 235:75]
|
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wire _T_59 = i0_brp_valid & _T_58; // @[dec_decode_ctl.scala 235:73]
|
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wire _T_68 = io_dec_i0_brp_bits_br_error | _T_59; // @[dec_decode_ctl.scala 240:89]
|
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wire _T_61 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 238:74]
|
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wire _T_399 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 461:41]
|
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wire [11:0] _T_408 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
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wire [11:0] i0_br_offset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 461:26]
|
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wire _T_62 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 238:133]
|
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wire _T_63 = _T_61 & _T_62; // @[dec_decode_ctl.scala 238:103]
|
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wire _T_64 = ~i0_pret_raw; // @[dec_decode_ctl.scala 238:153]
|
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wire _T_65 = _T_63 & _T_64; // @[dec_decode_ctl.scala 238:151]
|
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wire _T_69 = _T_68 | _T_65; // @[dec_decode_ctl.scala 240:106]
|
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wire _T_66 = io_dec_i0_brp_bits_ret ^ i0_pret_raw; // @[dec_decode_ctl.scala 239:100]
|
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wire _T_67 = i0_brp_valid & _T_66; // @[dec_decode_ctl.scala 239:74]
|
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wire _T_70 = _T_69 | _T_67; // @[dec_decode_ctl.scala 240:128]
|
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wire _T_77 = _T_70 | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 245:74]
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wire i0_br_error_all = _T_77 & _T_50; // @[dec_decode_ctl.scala 245:111]
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wire _T_80 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 282:25]
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wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_legal = _T_80 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_csr_read = _T_80 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_csr_write = _T_80 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 282:50]
|
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wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 521:42]
|
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wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 521:40]
|
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wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 529:34]
|
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wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40]
|
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wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51]
|
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wire _T_546 = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37]
|
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wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50]
|
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wire bitmanip_zbe_legal = ~i0_dp_zbe; // @[dec_decode_ctl.scala 723:32]
|
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wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50]
|
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wire bitmanip_zbc_legal = ~i0_dp_zbc; // @[dec_decode_ctl.scala 728:32]
|
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wire _T_801 = bitmanip_zbe_legal & bitmanip_zbc_legal; // @[dec_decode_ctl.scala 755:83]
|
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wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50]
|
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wire _T_793 = ~i0_dp_zbb; // @[dec_decode_ctl.scala 733:46]
|
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wire _T_794 = i0_dp_zbp & _T_793; // @[dec_decode_ctl.scala 733:44]
|
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wire bitmanip_zbp_legal = ~_T_794; // @[dec_decode_ctl.scala 733:32]
|
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wire _T_802 = _T_801 & bitmanip_zbp_legal; // @[dec_decode_ctl.scala 755:104]
|
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wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50]
|
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wire bitmanip_zbr_legal = ~i0_dp_zbr; // @[dec_decode_ctl.scala 738:32]
|
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wire _T_803 = _T_802 & bitmanip_zbr_legal; // @[dec_decode_ctl.scala 755:125]
|
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wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50]
|
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wire bitmanip_zbf_legal = ~i0_dp_zbf; // @[dec_decode_ctl.scala 743:32]
|
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wire _T_804 = _T_803 & bitmanip_zbf_legal; // @[dec_decode_ctl.scala 755:146]
|
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wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50]
|
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wire bitmanip_zba_legal = ~i0_dp_zba; // @[dec_decode_ctl.scala 748:32]
|
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wire bitmanip_legal = _T_804 & bitmanip_zba_legal; // @[dec_decode_ctl.scala 755:167]
|
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wire i0_legal = _T_546 & bitmanip_legal; // @[dec_decode_ctl.scala 590:73]
|
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wire _T_564 = ~i0_legal; // @[dec_decode_ctl.scala 594:49]
|
|
wire shift_illegal = io_dec_i0_decode_d & _T_564; // @[dec_decode_ctl.scala 594:47]
|
|
reg illegal_lockout; // @[Reg.scala 27:20]
|
|
wire _T_567 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40]
|
|
reg flush_final_r; // @[Reg.scala 27:20]
|
|
wire _T_568 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61]
|
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wire illegal_lockout_in = _T_567 & _T_568; // @[dec_decode_ctl.scala 597:59]
|
|
wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 466:21]
|
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wire _T_27 = |_T_26; // @[lib.scala 466:29]
|
|
wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_postsync = _T_80 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 282:50]
|
|
wire _T_539 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 588:36]
|
|
wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 580:48]
|
|
wire _T_540 = _T_539 | debug_fence_i; // @[dec_decode_ctl.scala 588:60]
|
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wire _T_433 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 526:41]
|
|
wire i0_csr_write_only_d = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 526:39]
|
|
wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 588:112]
|
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wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 588:99]
|
|
wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 588:76]
|
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wire _T_606 = i0_postsync | _T_564; // @[dec_decode_ctl.scala 628:54]
|
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wire _T_607 = io_dec_i0_decode_d & _T_606; // @[dec_decode_ctl.scala 628:39]
|
|
reg postsync_stall; // @[Reg.scala 27:20]
|
|
reg x_d_valid; // @[Reg.scala 27:20]
|
|
wire _T_608 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:88]
|
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wire ps_stall_in = _T_607 | _T_608; // @[dec_decode_ctl.scala 628:69]
|
|
wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 466:21]
|
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wire _T_31 = |_T_30; // @[lib.scala 466:29]
|
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reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_33 = io_lsu_trigger_match_m ^ lsu_trigger_match_r; // @[lib.scala 466:21]
|
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wire _T_34 = |_T_33; // @[lib.scala 466:29]
|
|
reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20]
|
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wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 488:21]
|
|
wire _T_37 = |_T_36; // @[lib.scala 488:29]
|
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wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:46]
|
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wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55]
|
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wire _T_935 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59]
|
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wire _T_936 = io_dec_div_active & _T_935; // @[dec_decode_ctl.scala 845:57]
|
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reg x_d_bits_i0div; // @[Reg.scala 27:20]
|
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wire _T_919 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48]
|
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reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20]
|
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wire _T_920 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77]
|
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wire _T_921 = _T_919 & _T_920; // @[dec_decode_ctl.scala 833:60]
|
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wire _T_923 = _T_919 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33]
|
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wire _T_924 = _T_921 | _T_923; // @[dec_decode_ctl.scala 833:94]
|
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reg r_d_bits_i0div; // @[Reg.scala 27:20]
|
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reg r_d_valid; // @[Reg.scala 27:20]
|
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wire _T_925 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21]
|
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wire _T_926 = _T_925 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33]
|
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wire _T_927 = _T_926 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60]
|
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wire div_flush = _T_924 | _T_927; // @[dec_decode_ctl.scala 834:62]
|
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wire _T_928 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51]
|
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wire div_e1_to_r = _T_919 | _T_925; // @[dec_decode_ctl.scala 831:58]
|
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wire _T_929 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26]
|
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wire _T_930 = io_dec_div_active & _T_929; // @[dec_decode_ctl.scala 840:24]
|
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reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20]
|
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wire _T_931 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56]
|
|
wire _T_932 = _T_930 & _T_931; // @[dec_decode_ctl.scala 840:39]
|
|
reg r_d_bits_i0v; // @[Reg.scala 27:20]
|
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wire _T_858 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51]
|
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wire r_d_in_bits_i0v = r_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 798:49]
|
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wire _T_869 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47]
|
|
wire i0_wen_r = r_d_in_bits_i0v & _T_869; // @[dec_decode_ctl.scala 806:45]
|
|
wire _T_933 = _T_932 & i0_wen_r; // @[dec_decode_ctl.scala 840:77]
|
|
wire nonblock_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 839:65]
|
|
wire _T_937 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78]
|
|
wire _T_938 = _T_936 & _T_937; // @[dec_decode_ctl.scala 845:76]
|
|
wire div_active_in = i0_div_decode_d | _T_938; // @[dec_decode_ctl.scala 845:36]
|
|
reg _T_42; // @[Reg.scala 27:20]
|
|
wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 488:21]
|
|
wire _T_41 = |_T_40; // @[lib.scala 488:29]
|
|
wire _T_44 = io_exu_flush_final ^ flush_final_r; // @[lib.scala 488:21]
|
|
wire _T_45 = |_T_44; // @[lib.scala 488:29]
|
|
reg debug_valid_x; // @[Reg.scala 27:20]
|
|
wire _T_47 = io_dec_debug_valid_d ^ debug_valid_x; // @[lib.scala 488:21]
|
|
wire _T_48 = |_T_47; // @[lib.scala 488:29]
|
|
wire _T_71 = _T_70 & i0_legal_decode_d; // @[dec_decode_ctl.scala 241:74]
|
|
wire _T_74 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 242:96]
|
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wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_pm_alu = _T_80 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_fence_i = _T_80 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_fence = _T_80 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_mul = _T_80 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_mret = _T_80 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_ecall = _T_80 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_ebreak = _T_80 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_presync = _T_80 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_csr_set = _T_80 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_csr_clr = _T_80 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_word = _T_80 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_half = _T_80 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_by = _T_80 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_jal = _T_80 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_condbr = _T_80 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
|
wire i0_dp_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 282:50]
|
|
wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_lsu = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_store = _T_80 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_load = _T_80 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 282:50]
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wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_imm20 = _T_80 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 282:50]
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wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
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wire i0_dp_shimm5 = _T_80 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 282:50]
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wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_rd = _T_80 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 282:50]
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wire i0_dp_imm12 = _T_80 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 282:50]
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wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_rs2 = _T_80 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_zbs = _T_80 ? 1'h0 : i0_dp_raw_zbs; // @[dec_decode_ctl.scala 282:50]
|
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wire i0_dp_raw_sbext = i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_rol = i0_dec_io_out_rol; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_packh = i0_dec_io_out_packh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_packu = i0_dec_io_out_packu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_pack = i0_dec_io_out_pack; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_max = i0_dec_io_out_max; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_min = i0_dec_io_out_min; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sext_h = i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_sext_b = i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_pcnt = i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_ctz = i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_dp_raw_clz = i0_dec_io_out_clz; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
|
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wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 458:38]
|
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wire _T_83 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 296:54]
|
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wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 460:38]
|
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wire _T_84 = _T_83 | i0_pja; // @[dec_decode_ctl.scala 296:65]
|
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wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 465:32]
|
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wire i0_predict_br = _T_84 | i0_pret; // @[dec_decode_ctl.scala 296:74]
|
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wire _T_86 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 297:69]
|
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wire _T_87 = ~_T_86; // @[dec_decode_ctl.scala 297:40]
|
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wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 299:40]
|
|
wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 358:76]
|
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reg [2:0] cam_raw_0_bits_tag; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_256 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 369:67]
|
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wire _T_133 = _GEN_256 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 369:67]
|
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wire _T_134 = cam_data_reset & _T_133; // @[dec_decode_ctl.scala 369:45]
|
|
reg cam_raw_0_valid; // @[Reg.scala 27:20]
|
|
wire cam_data_reset_val_0 = _T_134 & cam_raw_0_valid; // @[dec_decode_ctl.scala 369:88]
|
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wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 373:39]
|
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wire _T_90 = ~cam_0_valid; // @[dec_decode_ctl.scala 350:78]
|
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reg [2:0] cam_raw_1_bits_tag; // @[Reg.scala 27:20]
|
|
wire _T_169 = _GEN_256 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 369:67]
|
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wire _T_170 = cam_data_reset & _T_169; // @[dec_decode_ctl.scala 369:45]
|
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reg cam_raw_1_valid; // @[Reg.scala 27:20]
|
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wire cam_data_reset_val_1 = _T_170 & cam_raw_1_valid; // @[dec_decode_ctl.scala 369:88]
|
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wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 373:39]
|
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wire _T_93 = ~cam_1_valid; // @[dec_decode_ctl.scala 350:78]
|
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wire _T_96 = cam_0_valid & _T_93; // @[dec_decode_ctl.scala 350:126]
|
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wire [1:0] _T_98 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 350:158]
|
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reg [2:0] cam_raw_2_bits_tag; // @[Reg.scala 27:20]
|
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wire _T_205 = _GEN_256 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 369:67]
|
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wire _T_206 = cam_data_reset & _T_205; // @[dec_decode_ctl.scala 369:45]
|
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reg cam_raw_2_valid; // @[Reg.scala 27:20]
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wire cam_data_reset_val_2 = _T_206 & cam_raw_2_valid; // @[dec_decode_ctl.scala 369:88]
|
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wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 373:39]
|
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wire _T_99 = ~cam_2_valid; // @[dec_decode_ctl.scala 350:78]
|
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wire _T_102 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 350:126]
|
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wire _T_105 = _T_102 & _T_99; // @[dec_decode_ctl.scala 350:126]
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wire [2:0] _T_107 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 350:158]
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reg [2:0] cam_raw_3_bits_tag; // @[Reg.scala 27:20]
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wire _T_241 = _GEN_256 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 369:67]
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wire _T_242 = cam_data_reset & _T_241; // @[dec_decode_ctl.scala 369:45]
|
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reg cam_raw_3_valid; // @[Reg.scala 27:20]
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wire cam_data_reset_val_3 = _T_242 & cam_raw_3_valid; // @[dec_decode_ctl.scala 369:88]
|
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wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 373:39]
|
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wire _T_108 = ~cam_3_valid; // @[dec_decode_ctl.scala 350:78]
|
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wire _T_114 = _T_102 & cam_2_valid; // @[dec_decode_ctl.scala 350:126]
|
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wire _T_117 = _T_114 & _T_108; // @[dec_decode_ctl.scala 350:126]
|
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wire [3:0] _T_119 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 350:158]
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wire _T_120 = _T_90 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72]
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wire [1:0] _T_121 = _T_96 ? _T_98 : 2'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_122 = _T_105 ? _T_107 : 3'h0; // @[Mux.scala 27:72]
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wire [3:0] _T_123 = _T_117 ? _T_119 : 4'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _GEN_260 = {{1'd0}, _T_120}; // @[Mux.scala 27:72]
|
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wire [1:0] _T_124 = _GEN_260 | _T_121; // @[Mux.scala 27:72]
|
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wire [2:0] _GEN_261 = {{1'd0}, _T_124}; // @[Mux.scala 27:72]
|
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wire [2:0] _T_125 = _GEN_261 | _T_122; // @[Mux.scala 27:72]
|
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wire [3:0] _GEN_262 = {{1'd0}, _T_125}; // @[Mux.scala 27:72]
|
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wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72]
|
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reg x_d_bits_i0load; // @[Reg.scala 27:20]
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wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 361:31]
|
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reg [2:0] _T_816; // @[dec_decode_ctl.scala 764:72]
|
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wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_816}; // @[Cat.scala 29:58]
|
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wire _T_822 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49]
|
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wire i0_r_ctl_en = _T_822 | io_clk_override; // @[dec_decode_ctl.scala 767:53]
|
|
reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
|
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reg r_d_bits_i0load; // @[Reg.scala 27:20]
|
|
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 366:56]
|
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wire [2:0] _GEN_263 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 368:66]
|
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wire _T_130 = _GEN_263 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 368:66]
|
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wire _T_131 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_130; // @[dec_decode_ctl.scala 368:45]
|
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wire cam_inv_reset_val_0 = _T_131 & cam_0_valid; // @[dec_decode_ctl.scala 368:87]
|
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reg [4:0] cam_raw_0_bits_rd; // @[Reg.scala 27:20]
|
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wire _T_142 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 381:85]
|
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wire _T_143 = i0_wen_r & _T_142; // @[dec_decode_ctl.scala 381:64]
|
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reg cam_raw_0_bits_wb; // @[Reg.scala 27:20]
|
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wire _T_145 = _T_143 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 381:105]
|
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wire _T_146 = cam_inv_reset_val_0 | _T_145; // @[dec_decode_ctl.scala 381:44]
|
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wire _GEN_110 = _T_146 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 381:131]
|
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wire [4:0] _GEN_111 = _T_146 ? 5'h0 : cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 381:131]
|
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wire [2:0] _GEN_112 = _T_146 ? 3'h0 : cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_113 = _T_146 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_114 = cam_wen[0] | _GEN_110; // @[dec_decode_ctl.scala 376:28]
|
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wire _GEN_115 = cam_wen[0] ? 1'h0 : _GEN_113; // @[dec_decode_ctl.scala 376:28]
|
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wire [2:0] cam_in_0_bits_tag = cam_wen[0] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_112; // @[dec_decode_ctl.scala 376:28]
|
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wire [4:0] cam_in_0_bits_rd = cam_wen[0] ? nonblock_load_rd : _GEN_111; // @[dec_decode_ctl.scala 376:28]
|
|
wire _T_149 = nonblock_load_valid_m_delay & _T_130; // @[dec_decode_ctl.scala 386:44]
|
|
wire _T_151 = _T_149 & cam_0_valid; // @[dec_decode_ctl.scala 386:113]
|
|
wire cam_in_0_bits_wb = _T_151 | _GEN_115; // @[dec_decode_ctl.scala 386:135]
|
|
wire cam_in_0_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_114; // @[dec_decode_ctl.scala 390:32]
|
|
wire [8:0] _T_154 = {cam_in_0_bits_wb,cam_in_0_bits_tag,cam_in_0_bits_rd}; // @[lib.scala 512:61]
|
|
wire [8:0] _T_156 = {cam_raw_0_bits_wb,cam_raw_0_bits_tag,cam_raw_0_bits_rd}; // @[lib.scala 512:74]
|
|
wire [8:0] _T_157 = _T_154 ^ _T_156; // @[lib.scala 512:68]
|
|
wire _T_158 = |_T_157; // @[lib.scala 512:82]
|
|
wire _T_159 = cam_in_0_valid ^ cam_raw_0_valid; // @[lib.scala 512:68]
|
|
wire _T_160 = |_T_159; // @[lib.scala 512:82]
|
|
wire _T_161 = _T_158 | _T_160; // @[lib.scala 512:97]
|
|
wire nonblock_load_write_0 = _T_133 & cam_raw_0_valid; // @[dec_decode_ctl.scala 395:71]
|
|
wire _T_166 = _GEN_263 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 368:66]
|
|
wire _T_167 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_166; // @[dec_decode_ctl.scala 368:45]
|
|
wire cam_inv_reset_val_1 = _T_167 & cam_1_valid; // @[dec_decode_ctl.scala 368:87]
|
|
reg [4:0] cam_raw_1_bits_rd; // @[Reg.scala 27:20]
|
|
wire _T_178 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 381:85]
|
|
wire _T_179 = i0_wen_r & _T_178; // @[dec_decode_ctl.scala 381:64]
|
|
reg cam_raw_1_bits_wb; // @[Reg.scala 27:20]
|
|
wire _T_181 = _T_179 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 381:105]
|
|
wire _T_182 = cam_inv_reset_val_1 | _T_181; // @[dec_decode_ctl.scala 381:44]
|
|
wire _GEN_125 = _T_182 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 381:131]
|
|
wire [4:0] _GEN_126 = _T_182 ? 5'h0 : cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 381:131]
|
|
wire [2:0] _GEN_127 = _T_182 ? 3'h0 : cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 381:131]
|
|
wire _GEN_128 = _T_182 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 381:131]
|
|
wire _GEN_129 = cam_wen[1] | _GEN_125; // @[dec_decode_ctl.scala 376:28]
|
|
wire _GEN_130 = cam_wen[1] ? 1'h0 : _GEN_128; // @[dec_decode_ctl.scala 376:28]
|
|
wire [2:0] cam_in_1_bits_tag = cam_wen[1] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_127; // @[dec_decode_ctl.scala 376:28]
|
|
wire [4:0] cam_in_1_bits_rd = cam_wen[1] ? nonblock_load_rd : _GEN_126; // @[dec_decode_ctl.scala 376:28]
|
|
wire _T_185 = nonblock_load_valid_m_delay & _T_166; // @[dec_decode_ctl.scala 386:44]
|
|
wire _T_187 = _T_185 & cam_1_valid; // @[dec_decode_ctl.scala 386:113]
|
|
wire cam_in_1_bits_wb = _T_187 | _GEN_130; // @[dec_decode_ctl.scala 386:135]
|
|
wire cam_in_1_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_129; // @[dec_decode_ctl.scala 390:32]
|
|
wire [8:0] _T_190 = {cam_in_1_bits_wb,cam_in_1_bits_tag,cam_in_1_bits_rd}; // @[lib.scala 512:61]
|
|
wire [8:0] _T_192 = {cam_raw_1_bits_wb,cam_raw_1_bits_tag,cam_raw_1_bits_rd}; // @[lib.scala 512:74]
|
|
wire [8:0] _T_193 = _T_190 ^ _T_192; // @[lib.scala 512:68]
|
|
wire _T_194 = |_T_193; // @[lib.scala 512:82]
|
|
wire _T_195 = cam_in_1_valid ^ cam_raw_1_valid; // @[lib.scala 512:68]
|
|
wire _T_196 = |_T_195; // @[lib.scala 512:82]
|
|
wire _T_197 = _T_194 | _T_196; // @[lib.scala 512:97]
|
|
wire nonblock_load_write_1 = _T_169 & cam_raw_1_valid; // @[dec_decode_ctl.scala 395:71]
|
|
wire _T_202 = _GEN_263 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 368:66]
|
|
wire _T_203 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_202; // @[dec_decode_ctl.scala 368:45]
|
|
wire cam_inv_reset_val_2 = _T_203 & cam_2_valid; // @[dec_decode_ctl.scala 368:87]
|
|
reg [4:0] cam_raw_2_bits_rd; // @[Reg.scala 27:20]
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wire _T_214 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 381:85]
|
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wire _T_215 = i0_wen_r & _T_214; // @[dec_decode_ctl.scala 381:64]
|
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reg cam_raw_2_bits_wb; // @[Reg.scala 27:20]
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wire _T_217 = _T_215 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 381:105]
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wire _T_218 = cam_inv_reset_val_2 | _T_217; // @[dec_decode_ctl.scala 381:44]
|
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wire _GEN_140 = _T_218 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 381:131]
|
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wire [4:0] _GEN_141 = _T_218 ? 5'h0 : cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 381:131]
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wire [2:0] _GEN_142 = _T_218 ? 3'h0 : cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_143 = _T_218 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_144 = cam_wen[2] | _GEN_140; // @[dec_decode_ctl.scala 376:28]
|
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wire _GEN_145 = cam_wen[2] ? 1'h0 : _GEN_143; // @[dec_decode_ctl.scala 376:28]
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wire [2:0] cam_in_2_bits_tag = cam_wen[2] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_142; // @[dec_decode_ctl.scala 376:28]
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wire [4:0] cam_in_2_bits_rd = cam_wen[2] ? nonblock_load_rd : _GEN_141; // @[dec_decode_ctl.scala 376:28]
|
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wire _T_221 = nonblock_load_valid_m_delay & _T_202; // @[dec_decode_ctl.scala 386:44]
|
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wire _T_223 = _T_221 & cam_2_valid; // @[dec_decode_ctl.scala 386:113]
|
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wire cam_in_2_bits_wb = _T_223 | _GEN_145; // @[dec_decode_ctl.scala 386:135]
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wire cam_in_2_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_144; // @[dec_decode_ctl.scala 390:32]
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wire [8:0] _T_226 = {cam_in_2_bits_wb,cam_in_2_bits_tag,cam_in_2_bits_rd}; // @[lib.scala 512:61]
|
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wire [8:0] _T_228 = {cam_raw_2_bits_wb,cam_raw_2_bits_tag,cam_raw_2_bits_rd}; // @[lib.scala 512:74]
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wire [8:0] _T_229 = _T_226 ^ _T_228; // @[lib.scala 512:68]
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wire _T_230 = |_T_229; // @[lib.scala 512:82]
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wire _T_231 = cam_in_2_valid ^ cam_raw_2_valid; // @[lib.scala 512:68]
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wire _T_232 = |_T_231; // @[lib.scala 512:82]
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wire _T_233 = _T_230 | _T_232; // @[lib.scala 512:97]
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wire nonblock_load_write_2 = _T_205 & cam_raw_2_valid; // @[dec_decode_ctl.scala 395:71]
|
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wire _T_238 = _GEN_263 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 368:66]
|
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wire _T_239 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_238; // @[dec_decode_ctl.scala 368:45]
|
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wire cam_inv_reset_val_3 = _T_239 & cam_3_valid; // @[dec_decode_ctl.scala 368:87]
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reg [4:0] cam_raw_3_bits_rd; // @[Reg.scala 27:20]
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wire _T_250 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 381:85]
|
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wire _T_251 = i0_wen_r & _T_250; // @[dec_decode_ctl.scala 381:64]
|
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reg cam_raw_3_bits_wb; // @[Reg.scala 27:20]
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wire _T_253 = _T_251 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 381:105]
|
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wire _T_254 = cam_inv_reset_val_3 | _T_253; // @[dec_decode_ctl.scala 381:44]
|
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wire _GEN_155 = _T_254 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 381:131]
|
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wire [4:0] _GEN_156 = _T_254 ? 5'h0 : cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 381:131]
|
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wire [2:0] _GEN_157 = _T_254 ? 3'h0 : cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_158 = _T_254 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 381:131]
|
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wire _GEN_159 = cam_wen[3] | _GEN_155; // @[dec_decode_ctl.scala 376:28]
|
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wire _GEN_160 = cam_wen[3] ? 1'h0 : _GEN_158; // @[dec_decode_ctl.scala 376:28]
|
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wire [2:0] cam_in_3_bits_tag = cam_wen[3] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_157; // @[dec_decode_ctl.scala 376:28]
|
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wire [4:0] cam_in_3_bits_rd = cam_wen[3] ? nonblock_load_rd : _GEN_156; // @[dec_decode_ctl.scala 376:28]
|
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wire _T_257 = nonblock_load_valid_m_delay & _T_238; // @[dec_decode_ctl.scala 386:44]
|
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wire _T_259 = _T_257 & cam_3_valid; // @[dec_decode_ctl.scala 386:113]
|
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wire cam_in_3_bits_wb = _T_259 | _GEN_160; // @[dec_decode_ctl.scala 386:135]
|
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wire cam_in_3_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_159; // @[dec_decode_ctl.scala 390:32]
|
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wire [8:0] _T_262 = {cam_in_3_bits_wb,cam_in_3_bits_tag,cam_in_3_bits_rd}; // @[lib.scala 512:61]
|
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wire [8:0] _T_264 = {cam_raw_3_bits_wb,cam_raw_3_bits_tag,cam_raw_3_bits_rd}; // @[lib.scala 512:74]
|
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wire [8:0] _T_265 = _T_262 ^ _T_264; // @[lib.scala 512:68]
|
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wire _T_266 = |_T_265; // @[lib.scala 512:82]
|
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wire _T_267 = cam_in_3_valid ^ cam_raw_3_valid; // @[lib.scala 512:68]
|
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wire _T_268 = |_T_267; // @[lib.scala 512:82]
|
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wire _T_269 = _T_266 | _T_268; // @[lib.scala 512:97]
|
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wire nonblock_load_write_3 = _T_241 & cam_raw_3_valid; // @[dec_decode_ctl.scala 395:71]
|
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wire _T_274 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 400:49]
|
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wire nonblock_load_cancel = _T_274 & i0_wen_r; // @[dec_decode_ctl.scala 400:81]
|
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wire _T_275 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 401:108]
|
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wire _T_276 = _T_275 | nonblock_load_write_2; // @[dec_decode_ctl.scala 401:108]
|
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wire _T_277 = _T_276 | nonblock_load_write_3; // @[dec_decode_ctl.scala 401:108]
|
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wire _T_279 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_277; // @[dec_decode_ctl.scala 401:77]
|
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wire _T_280 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 401:122]
|
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wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 402:54]
|
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wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:66]
|
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wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 402:110]
|
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wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16]
|
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wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 402:161]
|
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wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:173]
|
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wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 402:217]
|
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wire i0_nonblock_boundary_stall = _T_284 | _T_287; // @[dec_decode_ctl.scala 402:142]
|
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wire [4:0] _T_289 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
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wire [4:0] _T_290 = _T_289 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 406:88]
|
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wire _T_291 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 406:137]
|
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wire _T_292 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
|
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wire _T_293 = _T_291 & _T_292; // @[dec_decode_ctl.scala 406:152]
|
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wire _T_294 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 406:214]
|
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wire _T_295 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
|
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wire _T_296 = _T_294 & _T_295; // @[dec_decode_ctl.scala 406:229]
|
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wire [4:0] _T_298 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
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wire [4:0] _T_299 = _T_298 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 406:88]
|
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wire _T_300 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 406:137]
|
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wire _T_301 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
|
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wire _T_302 = _T_300 & _T_301; // @[dec_decode_ctl.scala 406:152]
|
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wire _T_303 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 406:214]
|
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wire _T_304 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
|
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wire _T_305 = _T_303 & _T_304; // @[dec_decode_ctl.scala 406:229]
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wire [4:0] _T_307 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
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wire [4:0] _T_308 = _T_307 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 406:88]
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wire _T_309 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 406:137]
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wire _T_310 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
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wire _T_311 = _T_309 & _T_310; // @[dec_decode_ctl.scala 406:152]
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wire _T_312 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 406:214]
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wire _T_313 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
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wire _T_314 = _T_312 & _T_313; // @[dec_decode_ctl.scala 406:229]
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wire [4:0] _T_316 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
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wire [4:0] _T_317 = _T_316 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 406:88]
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wire _T_318 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 406:137]
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wire _T_319 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
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wire _T_320 = _T_318 & _T_319; // @[dec_decode_ctl.scala 406:152]
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wire _T_321 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 406:214]
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wire _T_322 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
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wire _T_323 = _T_321 & _T_322; // @[dec_decode_ctl.scala 406:229]
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wire [4:0] _T_324 = _T_290 | _T_299; // @[dec_decode_ctl.scala 407:69]
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wire [4:0] _T_325 = _T_324 | _T_308; // @[dec_decode_ctl.scala 407:69]
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wire _T_326 = _T_293 | _T_302; // @[dec_decode_ctl.scala 407:102]
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wire _T_327 = _T_326 | _T_311; // @[dec_decode_ctl.scala 407:102]
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wire ld_stall_1 = _T_327 | _T_320; // @[dec_decode_ctl.scala 407:102]
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wire _T_328 = _T_296 | _T_305; // @[dec_decode_ctl.scala 407:134]
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wire _T_329 = _T_328 | _T_314; // @[dec_decode_ctl.scala 407:134]
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wire ld_stall_2 = _T_329 | _T_323; // @[dec_decode_ctl.scala 407:134]
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wire _T_330 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 409:38]
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wire i0_nonblock_load_stall = _T_330 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 409:51]
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wire _T_332 = ~i0_predict_br; // @[dec_decode_ctl.scala 418:34]
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wire i0_br_unpred = i0_dp_jal & _T_332; // @[dec_decode_ctl.scala 418:32]
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wire [3:0] _T_334 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
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wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 519:36]
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wire _T_335 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 430:16]
|
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wire _T_337 = ~csr_read; // @[dec_decode_ctl.scala 431:6]
|
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wire _T_338 = _T_337 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 431:16]
|
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wire _T_340 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 432:18]
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wire _T_341 = csr_read & _T_340; // @[dec_decode_ctl.scala 432:16]
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wire _T_343 = i0_dp_zbb | i0_dp_zbs; // @[dec_decode_ctl.scala 433:16]
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wire _T_344 = _T_343 | i0_dp_zbe; // @[dec_decode_ctl.scala 433:28]
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wire _T_345 = _T_344 | i0_dp_zbc; // @[dec_decode_ctl.scala 433:40]
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wire _T_346 = _T_345 | i0_dp_zbp; // @[dec_decode_ctl.scala 433:52]
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wire _T_347 = _T_346 | i0_dp_zbr; // @[dec_decode_ctl.scala 433:65]
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wire _T_348 = _T_347 | i0_dp_zbf; // @[dec_decode_ctl.scala 433:77]
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wire _T_349 = _T_348 | i0_dp_zba; // @[dec_decode_ctl.scala 433:89]
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wire [3:0] _T_350 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16]
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wire [3:0] _T_351 = i0_dp_load ? 4'h2 : _T_350; // @[Mux.scala 98:16]
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wire [3:0] _T_352 = i0_dp_store ? 4'h3 : _T_351; // @[Mux.scala 98:16]
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wire [3:0] _T_353 = i0_dp_pm_alu ? 4'h4 : _T_352; // @[Mux.scala 98:16]
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wire [3:0] _T_354 = _T_349 ? 4'hf : _T_353; // @[Mux.scala 98:16]
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wire [3:0] _T_355 = _T_341 ? 4'h5 : _T_354; // @[Mux.scala 98:16]
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wire [3:0] _T_356 = _T_338 ? 4'h6 : _T_355; // @[Mux.scala 98:16]
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wire [3:0] _T_357 = _T_335 ? 4'h7 : _T_356; // @[Mux.scala 98:16]
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wire [3:0] _T_358 = i0_dp_ebreak ? 4'h8 : _T_357; // @[Mux.scala 98:16]
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wire [3:0] _T_359 = i0_dp_ecall ? 4'h9 : _T_358; // @[Mux.scala 98:16]
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wire [3:0] _T_360 = i0_dp_fence ? 4'ha : _T_359; // @[Mux.scala 98:16]
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wire [3:0] _T_361 = i0_dp_fence_i ? 4'hb : _T_360; // @[Mux.scala 98:16]
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wire [3:0] _T_362 = i0_dp_mret ? 4'hc : _T_361; // @[Mux.scala 98:16]
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wire [3:0] _T_363 = i0_dp_condbr ? 4'hd : _T_362; // @[Mux.scala 98:16]
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wire [3:0] _T_364 = i0_dp_jal ? 4'he : _T_363; // @[Mux.scala 98:16]
|
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wire [3:0] d_t_pmu_i0_itype = _T_334 & _T_364; // @[dec_decode_ctl.scala 422:49]
|
|
reg lsu_idle; // @[dec_decode_ctl.scala 444:45]
|
|
wire _T_418 = ~i0_pcall_case; // @[dec_decode_ctl.scala 466:35]
|
|
wire _T_419 = i0_dp_jal & _T_418; // @[dec_decode_ctl.scala 466:32]
|
|
wire _T_420 = ~i0_pja_case; // @[dec_decode_ctl.scala 466:52]
|
|
wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 466:50]
|
|
wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 466:67]
|
|
wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40]
|
|
wire _T_1019 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43]
|
|
reg x_d_bits_i0v; // @[Reg.scala 27:20]
|
|
wire _T_993 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59]
|
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wire _T_994 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91]
|
|
wire i0_rs1_depend_i0_x = _T_993 & _T_994; // @[dec_decode_ctl.scala 881:74]
|
|
wire _T_995 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59]
|
|
wire _T_996 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91]
|
|
wire i0_rs1_depend_i0_r = _T_995 & _T_996; // @[dec_decode_ctl.scala 882:74]
|
|
wire [1:0] _T_1008 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63]
|
|
wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1008; // @[dec_decode_ctl.scala 888:24]
|
|
wire _T_1021 = _T_1019 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58]
|
|
reg i0_x_c_load; // @[Reg.scala 27:20]
|
|
reg i0_r_c_load; // @[Reg.scala 27:20]
|
|
wire _T_1004_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61]
|
|
wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1004_load; // @[dec_decode_ctl.scala 887:24]
|
|
wire load_ldst_bypass_d = _T_1021 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78]
|
|
wire _T_997 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59]
|
|
wire _T_998 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91]
|
|
wire i0_rs2_depend_i0_x = _T_997 & _T_998; // @[dec_decode_ctl.scala 884:74]
|
|
wire _T_999 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59]
|
|
wire _T_1000 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91]
|
|
wire i0_rs2_depend_i0_r = _T_999 & _T_1000; // @[dec_decode_ctl.scala 885:74]
|
|
wire [1:0] _T_1017 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63]
|
|
wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1017; // @[dec_decode_ctl.scala 890:24]
|
|
wire _T_1024 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43]
|
|
wire _T_1013_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61]
|
|
wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1013_load; // @[dec_decode_ctl.scala 889:24]
|
|
wire store_data_bypass_d = _T_1024 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63]
|
|
wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 527:42]
|
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wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 527:58]
|
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wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
|
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reg r_d_bits_csrwen; // @[Reg.scala 27:20]
|
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wire _T_443 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 532:53]
|
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wire [11:0] _T_445 = _T_443 ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
|
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reg [11:0] r_d_bits_csrwaddr; // @[Reg.scala 27:20]
|
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wire _T_450 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 539:50]
|
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wire _T_451 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 539:85]
|
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wire _T_452 = _T_450 | _T_451; // @[dec_decode_ctl.scala 539:64]
|
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wire _T_453 = _T_452 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 539:100]
|
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wire _T_454 = _T_453 & r_d_valid; // @[dec_decode_ctl.scala 539:118]
|
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wire _T_455 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 539:132]
|
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reg csr_read_x; // @[dec_decode_ctl.scala 541:52]
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reg csr_clr_x; // @[dec_decode_ctl.scala 542:51]
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reg csr_set_x; // @[dec_decode_ctl.scala 543:51]
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reg csr_write_x; // @[dec_decode_ctl.scala 544:53]
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reg csr_imm_x; // @[dec_decode_ctl.scala 545:51]
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wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50]
|
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wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 548:48]
|
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reg [4:0] csrimm_x; // @[Reg.scala 27:20]
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reg [31:0] csr_rddata_x; // @[Reg.scala 27:20]
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wire [31:0] _T_493 = {27'h0,csrimm_x}; // @[Cat.scala 29:58]
|
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wire _T_495 = ~csr_imm_x; // @[dec_decode_ctl.scala 553:5]
|
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wire [31:0] _T_496 = csr_imm_x ? _T_493 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_497 = _T_495 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] csr_mask_x = _T_496 | _T_497; // @[Mux.scala 27:72]
|
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wire [31:0] _T_499 = ~csr_mask_x; // @[dec_decode_ctl.scala 556:38]
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wire [31:0] _T_500 = csr_rddata_x & _T_499; // @[dec_decode_ctl.scala 556:35]
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wire [31:0] _T_501 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 557:35]
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wire [31:0] _T_502 = csr_clr_x ? _T_500 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_503 = csr_set_x ? _T_501 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_504 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_505 = _T_502 | _T_503; // @[Mux.scala 27:72]
|
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wire [31:0] write_csr_data_x = _T_505 | _T_504; // @[Mux.scala 27:72]
|
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wire [31:0] _T_522 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 567:59]
|
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wire _T_524 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 569:34]
|
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wire _T_525 = _T_524 | csr_write_x; // @[dec_decode_ctl.scala 569:46]
|
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wire _T_526 = _T_525 & csr_read_x; // @[dec_decode_ctl.scala 569:61]
|
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wire _T_527 = _T_526 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 569:75]
|
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wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 569:99]
|
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reg r_d_bits_csrwonly; // @[Reg.scala 27:20]
|
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wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 576:50]
|
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wire _T_882 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42]
|
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reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20]
|
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wire [31:0] i0_result_corr_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27]
|
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reg x_d_bits_csrwonly; // @[Reg.scala 27:20]
|
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wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 578:43]
|
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reg wbd_bits_csrwonly; // @[Reg.scala 27:20]
|
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wire prior_csr_write = _T_532 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 578:63]
|
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wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 581:48]
|
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wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 582:40]
|
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wire _T_536 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 585:34]
|
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wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 585:57]
|
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wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 585:73]
|
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wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 585:91]
|
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wire [31:0] _T_563 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58]
|
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wire _T_565 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44]
|
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wire illegal_inst_en = shift_illegal & _T_565; // @[dec_decode_ctl.scala 595:42]
|
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reg [31:0] _T_566; // @[Reg.scala 27:20]
|
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wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42]
|
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wire _T_570 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40]
|
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wire _T_571 = _T_570 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59]
|
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wire _T_572 = _T_571 | pause_stall; // @[dec_decode_ctl.scala 600:92]
|
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wire _T_573 = _T_572 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106]
|
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wire _T_574 = _T_573 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20]
|
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wire _T_575 = _T_574 | postsync_stall; // @[dec_decode_ctl.scala 601:45]
|
|
wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41]
|
|
wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31]
|
|
wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37]
|
|
wire _T_576 = _T_575 | presync_stall; // @[dec_decode_ctl.scala 601:62]
|
|
wire _T_577 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19]
|
|
wire _T_578 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36]
|
|
wire _T_579 = _T_577 & _T_578; // @[dec_decode_ctl.scala 602:34]
|
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wire _T_580 = _T_576 | _T_579; // @[dec_decode_ctl.scala 601:79]
|
|
wire _T_581 = _T_580 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47]
|
|
wire _T_940 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60]
|
|
wire _T_941 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99]
|
|
wire _T_942 = _T_940 & _T_941; // @[dec_decode_ctl.scala 850:80]
|
|
wire _T_943 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36]
|
|
wire _T_944 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75]
|
|
wire _T_945 = _T_943 & _T_944; // @[dec_decode_ctl.scala 851:56]
|
|
wire i0_nonblock_div_stall = _T_942 | _T_945; // @[dec_decode_ctl.scala 850:113]
|
|
wire _T_583 = _T_581 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21]
|
|
wire i0_block_raw_d = _T_583 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45]
|
|
wire _T_584 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65]
|
|
wire i0_store_stall_d = i0_dp_store & _T_584; // @[dec_decode_ctl.scala 605:39]
|
|
wire _T_585 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63]
|
|
wire i0_load_stall_d = i0_dp_load & _T_585; // @[dec_decode_ctl.scala 606:38]
|
|
wire _T_586 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38]
|
|
wire i0_block_d = _T_586 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57]
|
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wire _T_587 = ~i0_block_d; // @[dec_decode_ctl.scala 611:46]
|
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wire _T_588 = io_dec_ib0_valid_d & _T_587; // @[dec_decode_ctl.scala 611:44]
|
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wire _T_590 = _T_588 & _T_367; // @[dec_decode_ctl.scala 611:61]
|
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wire _T_593 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46]
|
|
wire _T_594 = io_dec_ib0_valid_d & _T_593; // @[dec_decode_ctl.scala 612:44]
|
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wire _T_596 = _T_594 & _T_367; // @[dec_decode_ctl.scala 612:61]
|
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wire i0_exudecode_d = _T_596 & _T_568; // @[dec_decode_ctl.scala 612:89]
|
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wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46]
|
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wire _T_598 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51]
|
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wire _T_611 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53]
|
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wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40]
|
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wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58]
|
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wire _T_620 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44]
|
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wire d_t_fence_i = _T_620 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61]
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wire [3:0] _T_625 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58]
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wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_625; // @[dec_decode_ctl.scala 652:56]
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wire _T_819 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49]
|
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wire i0_x_ctl_en = _T_819 | io_clk_override; // @[dec_decode_ctl.scala 766:53]
|
|
reg x_t_legal; // @[Reg.scala 27:20]
|
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reg x_t_icaf; // @[Reg.scala 27:20]
|
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reg x_t_icaf_second; // @[Reg.scala 27:20]
|
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reg [1:0] x_t_icaf_type; // @[Reg.scala 27:20]
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reg x_t_fence_i; // @[Reg.scala 27:20]
|
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reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20]
|
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reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20]
|
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reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
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wire [3:0] _T_633 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58]
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wire [3:0] _T_634 = ~_T_633; // @[dec_decode_ctl.scala 658:39]
|
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wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_634; // @[dec_decode_ctl.scala 658:37]
|
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reg r_t_legal; // @[Reg.scala 27:20]
|
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reg r_t_icaf; // @[Reg.scala 27:20]
|
|
reg r_t_icaf_second; // @[Reg.scala 27:20]
|
|
reg [1:0] r_t_icaf_type; // @[Reg.scala 27:20]
|
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reg r_t_fence_i; // @[Reg.scala 27:20]
|
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reg [3:0] r_t_i0trigger; // @[Reg.scala 27:20]
|
|
reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20]
|
|
reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
|
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reg r_d_bits_i0store; // @[Reg.scala 27:20]
|
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wire _T_639 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61]
|
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wire [3:0] _T_643 = {_T_639,_T_639,_T_639,_T_639}; // @[Cat.scala 29:58]
|
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wire [3:0] _T_644 = _T_643 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82]
|
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wire [3:0] _T_645 = _T_644 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105]
|
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wire _T_658 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60]
|
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wire _T_660 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60]
|
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wire _T_662 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48]
|
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wire i0_rd_en_d = i0_dp_rd & _T_662; // @[dec_decode_ctl.scala 682:37]
|
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wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38]
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wire _T_663 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27]
|
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wire i0_uiimm20 = _T_663 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38]
|
|
wire [9:0] _T_674 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
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wire [18:0] _T_683 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_686 = {_T_683,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_715 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_735 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_749 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58]
|
|
wire _T_750 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26]
|
|
wire [31:0] _T_780 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_781 = i0_dp_imm12 ? _T_686 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_782 = i0_dp_shimm5 ? _T_715 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_783 = i0_jalimm20 ? _T_735 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_784 = i0_uiimm20 ? _T_749 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_785 = _T_750 ? _T_780 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_786 = _T_781 | _T_782; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_788 = _T_787 | _T_784; // @[Mux.scala 27:72]
|
|
wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44]
|
|
wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44]
|
|
wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44]
|
|
reg i0_x_c_mul; // @[Reg.scala 27:20]
|
|
reg i0_x_c_alu; // @[Reg.scala 27:20]
|
|
reg i0_r_c_mul; // @[Reg.scala 27:20]
|
|
reg i0_r_c_alu; // @[Reg.scala 27:20]
|
|
wire _T_825 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49]
|
|
wire i0_wb_ctl_en = _T_825 | io_clk_override; // @[dec_decode_ctl.scala 768:53]
|
|
wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50]
|
|
wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50]
|
|
wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50]
|
|
wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50]
|
|
wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50]
|
|
wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61]
|
|
wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58]
|
|
reg x_d_bits_i0store; // @[Reg.scala 27:20]
|
|
reg x_d_bits_csrwen; // @[Reg.scala 27:20]
|
|
reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20]
|
|
wire _T_848 = x_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 791:47]
|
|
wire x_d_in_bits_i0v = _T_848 & _T_367; // @[dec_decode_ctl.scala 791:76]
|
|
wire _T_852 = x_d_valid & _T_858; // @[dec_decode_ctl.scala 792:33]
|
|
wire x_d_in_valid = _T_852 & _T_367; // @[dec_decode_ctl.scala 792:62]
|
|
wire _T_871 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49]
|
|
wire _T_872 = i0_wen_r & _T_871; // @[dec_decode_ctl.scala 807:47]
|
|
wire _T_873 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70]
|
|
wire _T_875 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74]
|
|
wire _T_876 = _T_875 | debug_valid_x; // @[dec_decode_ctl.scala 811:92]
|
|
wire _T_877 = i0_r_data_en & _T_876; // @[dec_decode_ctl.scala 811:58]
|
|
wire _T_879 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47]
|
|
wire _T_886 = io_decode_exu_i0_ap_predict_nt & _T_663; // @[dec_decode_ctl.scala 823:71]
|
|
wire [11:0] _T_899 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
|
|
reg [11:0] last_br_immed_x; // @[Reg.scala 27:20]
|
|
wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22]
|
|
reg [4:0] _T_948; // @[Reg.scala 27:20]
|
|
wire _T_949 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50]
|
|
reg [31:0] i0_inst_x; // @[Reg.scala 27:20]
|
|
wire _T_951 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50]
|
|
reg [31:0] i0_inst_r; // @[Reg.scala 27:20]
|
|
wire _T_953 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51]
|
|
reg [31:0] i0_inst_wb; // @[Reg.scala 27:20]
|
|
reg [30:0] i0_pc_wb; // @[Reg.scala 27:20]
|
|
reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_959 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_960 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_963 = _T_959[12:1] + _T_960[12:1]; // @[lib.scala 74:31]
|
|
wire [18:0] _T_966 = _T_959[31:13] + 19'h1; // @[lib.scala 75:27]
|
|
wire [18:0] _T_969 = _T_959[31:13] - 19'h1; // @[lib.scala 76:27]
|
|
wire _T_972 = ~_T_963[12]; // @[lib.scala 78:28]
|
|
wire _T_973 = _T_960[12] ^ _T_972; // @[lib.scala 78:26]
|
|
wire _T_976 = ~_T_960[12]; // @[lib.scala 79:8]
|
|
wire _T_978 = _T_976 & _T_963[12]; // @[lib.scala 79:14]
|
|
wire _T_982 = _T_960[12] & _T_972; // @[lib.scala 80:14]
|
|
wire [18:0] _T_984 = _T_973 ? _T_959[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_985 = _T_978 ? _T_966 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_986 = _T_982 ? _T_969 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_988 = _T_987 | _T_986; // @[Mux.scala 27:72]
|
|
wire [31:0] temp_pred_correct_npc_x = {_T_988,_T_963[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_1004_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61]
|
|
wire _T_1004_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61]
|
|
wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1004_mul; // @[dec_decode_ctl.scala 887:24]
|
|
wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1004_alu; // @[dec_decode_ctl.scala 887:24]
|
|
wire _T_1013_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61]
|
|
wire _T_1013_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61]
|
|
wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1013_mul; // @[dec_decode_ctl.scala 889:24]
|
|
wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1013_alu; // @[dec_decode_ctl.scala 889:24]
|
|
wire _T_1026 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73]
|
|
wire _T_1027 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130]
|
|
wire i0_rs1_nonblock_load_bypass_en_d = _T_1026 & _T_1027; // @[dec_decode_ctl.scala 907:100]
|
|
wire _T_1028 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73]
|
|
wire _T_1029 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130]
|
|
wire i0_rs2_nonblock_load_bypass_en_d = _T_1028 & _T_1029; // @[dec_decode_ctl.scala 909:100]
|
|
wire _T_1031 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66]
|
|
wire _T_1032 = i0_rs1_depth_d[0] & _T_1031; // @[dec_decode_ctl.scala 912:45]
|
|
wire _T_1034 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108]
|
|
wire _T_1037 = _T_1031 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196]
|
|
wire _T_1038 = i0_rs1_depth_d[1] & _T_1037; // @[dec_decode_ctl.scala 912:153]
|
|
wire [2:0] i0_rs1bypass = {_T_1032,_T_1034,_T_1038}; // @[Cat.scala 29:58]
|
|
wire _T_1042 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67]
|
|
wire _T_1043 = i0_rs2_depth_d[0] & _T_1042; // @[dec_decode_ctl.scala 914:45]
|
|
wire _T_1045 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109]
|
|
wire _T_1048 = _T_1042 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196]
|
|
wire _T_1049 = i0_rs2_depth_d[1] & _T_1048; // @[dec_decode_ctl.scala 914:153]
|
|
wire [2:0] i0_rs2bypass = {_T_1043,_T_1045,_T_1049}; // @[Cat.scala 29:58]
|
|
wire _T_1053 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53]
|
|
wire _T_1055 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72]
|
|
wire _T_1056 = _T_1053 & _T_1055; // @[dec_decode_ctl.scala 916:70]
|
|
wire _T_1058 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91]
|
|
wire _T_1059 = _T_1056 & _T_1058; // @[dec_decode_ctl.scala 916:89]
|
|
wire _T_1060 = _T_1059 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108]
|
|
wire [1:0] _T_1064 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_1065 = {_T_1060,i0_rs1bypass[2]}; // @[Cat.scala 29:58]
|
|
wire _T_1068 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53]
|
|
wire _T_1070 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72]
|
|
wire _T_1071 = _T_1068 & _T_1070; // @[dec_decode_ctl.scala 917:70]
|
|
wire _T_1073 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91]
|
|
wire _T_1074 = _T_1071 & _T_1073; // @[dec_decode_ctl.scala 917:89]
|
|
wire _T_1075 = _T_1074 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108]
|
|
wire [1:0] _T_1079 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_1080 = {_T_1075,i0_rs2bypass[2]}; // @[Cat.scala 29:58]
|
|
wire _T_1082 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68]
|
|
wire _T_1083 = io_dec_ib0_valid_d & _T_1082; // @[dec_decode_ctl.scala 921:50]
|
|
wire _T_1084 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89]
|
|
wire _T_1085 = _T_1083 & _T_1084; // @[dec_decode_ctl.scala 921:87]
|
|
wire _T_1087 = _T_1085 & _T_593; // @[dec_decode_ctl.scala 921:121]
|
|
wire _T_1089 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6]
|
|
wire _T_1090 = _T_1089 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38]
|
|
wire _T_1091 = _T_1090 & i0_dp_load; // @[dec_decode_ctl.scala 923:50]
|
|
wire _T_1096 = _T_1090 & i0_dp_store; // @[dec_decode_ctl.scala 924:50]
|
|
wire [11:0] _T_1100 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
|
|
wire [11:0] _T_1101 = _T_1091 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
|
|
wire [11:0] _T_1102 = _T_1096 ? _T_1100 : 12'h0; // @[Mux.scala 27:72]
|
|
dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 440:22]
|
|
.io_ins(i0_dec_io_ins),
|
|
.io_out_clz(i0_dec_io_out_clz),
|
|
.io_out_ctz(i0_dec_io_out_ctz),
|
|
.io_out_pcnt(i0_dec_io_out_pcnt),
|
|
.io_out_sext_b(i0_dec_io_out_sext_b),
|
|
.io_out_sext_h(i0_dec_io_out_sext_h),
|
|
.io_out_min(i0_dec_io_out_min),
|
|
.io_out_max(i0_dec_io_out_max),
|
|
.io_out_pack(i0_dec_io_out_pack),
|
|
.io_out_packu(i0_dec_io_out_packu),
|
|
.io_out_packh(i0_dec_io_out_packh),
|
|
.io_out_rol(i0_dec_io_out_rol),
|
|
.io_out_ror(i0_dec_io_out_ror),
|
|
.io_out_grev(i0_dec_io_out_grev),
|
|
.io_out_gorc(i0_dec_io_out_gorc),
|
|
.io_out_zbb(i0_dec_io_out_zbb),
|
|
.io_out_sbset(i0_dec_io_out_sbset),
|
|
.io_out_sbclr(i0_dec_io_out_sbclr),
|
|
.io_out_sbinv(i0_dec_io_out_sbinv),
|
|
.io_out_sbext(i0_dec_io_out_sbext),
|
|
.io_out_zbs(i0_dec_io_out_zbs),
|
|
.io_out_zbe(i0_dec_io_out_zbe),
|
|
.io_out_zbc(i0_dec_io_out_zbc),
|
|
.io_out_zbp(i0_dec_io_out_zbp),
|
|
.io_out_zbr(i0_dec_io_out_zbr),
|
|
.io_out_zbf(i0_dec_io_out_zbf),
|
|
.io_out_zba(i0_dec_io_out_zba),
|
|
.io_out_alu(i0_dec_io_out_alu),
|
|
.io_out_rs1(i0_dec_io_out_rs1),
|
|
.io_out_rs2(i0_dec_io_out_rs2),
|
|
.io_out_imm12(i0_dec_io_out_imm12),
|
|
.io_out_rd(i0_dec_io_out_rd),
|
|
.io_out_shimm5(i0_dec_io_out_shimm5),
|
|
.io_out_imm20(i0_dec_io_out_imm20),
|
|
.io_out_pc(i0_dec_io_out_pc),
|
|
.io_out_load(i0_dec_io_out_load),
|
|
.io_out_store(i0_dec_io_out_store),
|
|
.io_out_lsu(i0_dec_io_out_lsu),
|
|
.io_out_add(i0_dec_io_out_add),
|
|
.io_out_sub(i0_dec_io_out_sub),
|
|
.io_out_land(i0_dec_io_out_land),
|
|
.io_out_lor(i0_dec_io_out_lor),
|
|
.io_out_lxor(i0_dec_io_out_lxor),
|
|
.io_out_sll(i0_dec_io_out_sll),
|
|
.io_out_sra(i0_dec_io_out_sra),
|
|
.io_out_srl(i0_dec_io_out_srl),
|
|
.io_out_slt(i0_dec_io_out_slt),
|
|
.io_out_unsign(i0_dec_io_out_unsign),
|
|
.io_out_condbr(i0_dec_io_out_condbr),
|
|
.io_out_beq(i0_dec_io_out_beq),
|
|
.io_out_bne(i0_dec_io_out_bne),
|
|
.io_out_bge(i0_dec_io_out_bge),
|
|
.io_out_blt(i0_dec_io_out_blt),
|
|
.io_out_jal(i0_dec_io_out_jal),
|
|
.io_out_by(i0_dec_io_out_by),
|
|
.io_out_half(i0_dec_io_out_half),
|
|
.io_out_word(i0_dec_io_out_word),
|
|
.io_out_csr_read(i0_dec_io_out_csr_read),
|
|
.io_out_csr_clr(i0_dec_io_out_csr_clr),
|
|
.io_out_csr_set(i0_dec_io_out_csr_set),
|
|
.io_out_csr_write(i0_dec_io_out_csr_write),
|
|
.io_out_csr_imm(i0_dec_io_out_csr_imm),
|
|
.io_out_presync(i0_dec_io_out_presync),
|
|
.io_out_postsync(i0_dec_io_out_postsync),
|
|
.io_out_ebreak(i0_dec_io_out_ebreak),
|
|
.io_out_ecall(i0_dec_io_out_ecall),
|
|
.io_out_mret(i0_dec_io_out_mret),
|
|
.io_out_mul(i0_dec_io_out_mul),
|
|
.io_out_rs1_sign(i0_dec_io_out_rs1_sign),
|
|
.io_out_rs2_sign(i0_dec_io_out_rs2_sign),
|
|
.io_out_low(i0_dec_io_out_low),
|
|
.io_out_div(i0_dec_io_out_div),
|
|
.io_out_rem(i0_dec_io_out_rem),
|
|
.io_out_fence(i0_dec_io_out_fence),
|
|
.io_out_fence_i(i0_dec_io_out_fence_i),
|
|
.io_out_pm_alu(i0_dec_io_out_pm_alu),
|
|
.io_out_legal(i0_dec_io_out_legal)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38]
|
|
assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38]
|
|
assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 319:33]
|
|
assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 320:33]
|
|
assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 321:33]
|
|
assign io_decode_exu_i0_ap_sext_b = _T_80 ? 1'h0 : i0_dp_raw_sext_b; // @[dec_decode_ctl.scala 322:33]
|
|
assign io_decode_exu_i0_ap_sext_h = _T_80 ? 1'h0 : i0_dp_raw_sext_h; // @[dec_decode_ctl.scala 323:33]
|
|
assign io_decode_exu_i0_ap_min = _T_80 ? 1'h0 : i0_dp_raw_min; // @[dec_decode_ctl.scala 330:33]
|
|
assign io_decode_exu_i0_ap_max = _T_80 ? 1'h0 : i0_dp_raw_max; // @[dec_decode_ctl.scala 331:33]
|
|
assign io_decode_exu_i0_ap_pack = _T_80 ? 1'h0 : i0_dp_raw_pack; // @[dec_decode_ctl.scala 332:33]
|
|
assign io_decode_exu_i0_ap_packu = _T_80 ? 1'h0 : i0_dp_raw_packu; // @[dec_decode_ctl.scala 333:33]
|
|
assign io_decode_exu_i0_ap_packh = _T_80 ? 1'h0 : i0_dp_raw_packh; // @[dec_decode_ctl.scala 334:33]
|
|
assign io_decode_exu_i0_ap_rol = _T_80 ? 1'h0 : i0_dp_raw_rol; // @[dec_decode_ctl.scala 335:33]
|
|
assign io_decode_exu_i0_ap_ror = _T_80 ? 1'h0 : i0_dp_raw_ror; // @[dec_decode_ctl.scala 336:33]
|
|
assign io_decode_exu_i0_ap_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 337:33]
|
|
assign io_decode_exu_i0_ap_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 338:33]
|
|
assign io_decode_exu_i0_ap_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 339:33]
|
|
assign io_decode_exu_i0_ap_sbset = _T_80 ? 1'h0 : i0_dp_raw_sbset; // @[dec_decode_ctl.scala 340:33]
|
|
assign io_decode_exu_i0_ap_sbclr = _T_80 ? 1'h0 : i0_dp_raw_sbclr; // @[dec_decode_ctl.scala 341:33]
|
|
assign io_decode_exu_i0_ap_sbinv = _T_80 ? 1'h0 : i0_dp_raw_sbinv; // @[dec_decode_ctl.scala 342:33]
|
|
assign io_decode_exu_i0_ap_sbext = _T_80 ? 1'h0 : i0_dp_raw_sbext; // @[dec_decode_ctl.scala 343:33]
|
|
assign io_decode_exu_i0_ap_land = _T_80 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 307:33]
|
|
assign io_decode_exu_i0_ap_lor = _T_80 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 308:33]
|
|
assign io_decode_exu_i0_ap_lxor = _T_80 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 309:33]
|
|
assign io_decode_exu_i0_ap_sll = _T_80 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 310:33]
|
|
assign io_decode_exu_i0_ap_srl = _T_80 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 311:33]
|
|
assign io_decode_exu_i0_ap_sra = _T_80 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 312:33]
|
|
assign io_decode_exu_i0_ap_beq = _T_80 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 315:33]
|
|
assign io_decode_exu_i0_ap_bne = _T_80 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 316:33]
|
|
assign io_decode_exu_i0_ap_blt = _T_80 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 317:33]
|
|
assign io_decode_exu_i0_ap_bge = _T_80 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 318:33]
|
|
assign io_decode_exu_i0_ap_add = _T_80 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 305:33]
|
|
assign io_decode_exu_i0_ap_sub = _T_80 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 306:33]
|
|
assign io_decode_exu_i0_ap_slt = _T_80 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 313:33]
|
|
assign io_decode_exu_i0_ap_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 314:33]
|
|
assign io_decode_exu_i0_ap_jal = _T_421 & _T_422; // @[dec_decode_ctl.scala 346:33]
|
|
assign io_decode_exu_i0_ap_predict_t = _T_86 & i0_predict_br; // @[dec_decode_ctl.scala 302:37]
|
|
assign io_decode_exu_i0_ap_predict_nt = _T_87 & i0_predict_br; // @[dec_decode_ctl.scala 301:37]
|
|
assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 344:33]
|
|
assign io_decode_exu_i0_ap_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 345:33]
|
|
assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 234:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 232:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 233:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 246:58]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_71 & _T_50; // @[dec_decode_ctl.scala 241:58]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_74 & _T_50; // @[dec_decode_ctl.scala 242:58]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 228:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 229:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 248:58]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 230:57]
|
|
assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 231:57]
|
|
assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 247:58]
|
|
assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 243:58]
|
|
assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 244:58]
|
|
assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_658; // @[dec_decode_ctl.scala 680:35]
|
|
assign io_decode_exu_dec_i0_branch_d = _T_611 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37]
|
|
assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_660; // @[dec_decode_ctl.scala 681:35]
|
|
assign io_decode_exu_dec_i0_immed_d = _T_788 | _T_785; // @[dec_decode_ctl.scala 693:32]
|
|
assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41]
|
|
assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:32]
|
|
assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 293:36]
|
|
assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1065,_T_1064}; // @[dec_decode_ctl.scala 916:45]
|
|
assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1080,_T_1079}; // @[dec_decode_ctl.scala 917:45]
|
|
assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 473:32]
|
|
assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 474:37]
|
|
assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 475:37]
|
|
assign io_decode_exu_mul_p_bits_low = _T_80 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 476:37]
|
|
assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36]
|
|
assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 210:35]
|
|
assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34]
|
|
assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 518:29]
|
|
assign io_dec_alu_dec_i0_br_immed_d = _T_886 ? i0_br_offset : _T_899; // @[dec_decode_ctl.scala 823:32]
|
|
assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 469:29]
|
|
assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 470:34]
|
|
assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 471:34]
|
|
assign io_dec_div_dec_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 842:37]
|
|
assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21]
|
|
assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19]
|
|
assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19]
|
|
assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19]
|
|
assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27]
|
|
assign io_dec_i0_wen_r = _T_872 & _T_873; // @[dec_decode_ctl.scala 807:32]
|
|
assign io_dec_i0_wdata_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26]
|
|
assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 500:24 dec_decode_ctl.scala 504:35]
|
|
assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 499:29]
|
|
assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 507:40]
|
|
assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 508:40]
|
|
assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 498:29 dec_decode_ctl.scala 509:40]
|
|
assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 497:29 dec_decode_ctl.scala 505:40]
|
|
assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 506:40]
|
|
assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 514:40]
|
|
assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 512:40]
|
|
assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 511:40]
|
|
assign io_div_waddr_wb = _T_948; // @[dec_decode_ctl.scala 860:19]
|
|
assign io_dec_lsu_valid_raw_d = _T_1087 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26]
|
|
assign io_dec_lsu_offset_d = _T_1101 | _T_1102; // @[dec_decode_ctl.scala 922:23]
|
|
assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 527:24]
|
|
assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 530:24]
|
|
assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 531:24]
|
|
assign io_dec_csr_wen_r = _T_443 & _T_869; // @[dec_decode_ctl.scala 536:20]
|
|
assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 532:24]
|
|
assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 576:24]
|
|
assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 539:27]
|
|
assign io_dec_tlu_i0_valid_r = r_d_valid & _T_858; // @[dec_decode_ctl.scala 637:29]
|
|
assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_645; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39]
|
|
assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39]
|
|
assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27]
|
|
assign io_dec_illegal_inst = _T_566; // @[dec_decode_ctl.scala 596:23]
|
|
assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28]
|
|
assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_598; // @[dec_decode_ctl.scala 617:27]
|
|
assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29]
|
|
assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29]
|
|
assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 401:28]
|
|
assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 398:29 dec_decode_ctl.scala 408:29]
|
|
assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 562:22]
|
|
assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 219:35]
|
|
assign io_dec_i0_decode_d = _T_590 & _T_568; // @[dec_decode_ctl.scala 611:22 dec_decode_ctl.scala 674:22]
|
|
assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 441:16]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = shift_illegal & _T_565; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = i0_r_data_en & _T_876; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = i0_legal_decode_d & i0_dp_div; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = i0_x_data_en & trace_enable; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = i0_r_data_en & trace_enable; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
leak1_i1_stall = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
leak1_i0_stall = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_12 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
pause_stall = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
write_csr_data = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
illegal_lockout = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
flush_final_r = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
postsync_stall = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
x_d_valid = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
lsu_trigger_match_r = _RAND_9[3:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
lsu_pmu_misaligned_r = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
x_d_bits_i0div = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
x_d_bits_i0rd = _RAND_12[4:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
r_d_bits_i0div = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
r_d_valid = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
r_d_bits_i0rd = _RAND_15[4:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
r_d_bits_i0v = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_42 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
debug_valid_x = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
cam_raw_0_bits_tag = _RAND_19[2:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
cam_raw_0_valid = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
cam_raw_1_bits_tag = _RAND_21[2:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
cam_raw_1_valid = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
cam_raw_2_bits_tag = _RAND_23[2:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
cam_raw_2_valid = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
cam_raw_3_bits_tag = _RAND_25[2:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
cam_raw_3_valid = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
x_d_bits_i0load = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
_T_816 = _RAND_28[2:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
nonblock_load_valid_m_delay = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
r_d_bits_i0load = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
cam_raw_0_bits_rd = _RAND_31[4:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
cam_raw_0_bits_wb = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
cam_raw_1_bits_rd = _RAND_33[4:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
cam_raw_1_bits_wb = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
cam_raw_2_bits_rd = _RAND_35[4:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
cam_raw_2_bits_wb = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
cam_raw_3_bits_rd = _RAND_37[4:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
cam_raw_3_bits_wb = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
lsu_idle = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
x_d_bits_i0v = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
i0_x_c_load = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
i0_r_c_load = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
r_d_bits_csrwen = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
r_d_bits_csrwaddr = _RAND_44[11:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
csr_read_x = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
csr_clr_x = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
csr_set_x = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
csr_write_x = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
csr_imm_x = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
csrimm_x = _RAND_50[4:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
csr_rddata_x = _RAND_51[31:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
r_d_bits_csrwonly = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
i0_result_r_raw = _RAND_53[31:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
x_d_bits_csrwonly = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
wbd_bits_csrwonly = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
_T_566 = _RAND_56[31:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
x_t_legal = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
x_t_icaf = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
x_t_icaf_second = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
x_t_icaf_type = _RAND_60[1:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
x_t_fence_i = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
x_t_i0trigger = _RAND_62[3:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
x_t_pmu_i0_itype = _RAND_63[3:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
x_t_pmu_i0_br_unpred = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
r_t_legal = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
r_t_icaf = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
r_t_icaf_second = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
r_t_icaf_type = _RAND_68[1:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
r_t_fence_i = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
r_t_i0trigger = _RAND_70[3:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
r_t_pmu_i0_itype = _RAND_71[3:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
r_t_pmu_i0_br_unpred = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
r_d_bits_i0store = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
i0_x_c_mul = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
i0_x_c_alu = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
i0_r_c_mul = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
i0_r_c_alu = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
x_d_bits_i0store = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
x_d_bits_csrwen = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
x_d_bits_csrwaddr = _RAND_80[11:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
last_br_immed_x = _RAND_81[11:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
_T_948 = _RAND_82[4:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
i0_inst_x = _RAND_83[31:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
i0_inst_r = _RAND_84[31:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
i0_inst_wb = _RAND_85[31:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
i0_pc_wb = _RAND_86[30:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
dec_i0_pc_r = _RAND_87[30:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
leak1_i1_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
leak1_i0_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pause_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
write_csr_data = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
illegal_lockout = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
flush_final_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
postsync_stall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_trigger_match_r = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_misaligned_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_i0div = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_i0rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_i0div = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_i0rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_i0v = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_valid_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_bits_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_bits_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_bits_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_bits_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_i0load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_816 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
nonblock_load_valid_m_delay = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_i0load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_bits_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_0_bits_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_bits_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_1_bits_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_bits_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_2_bits_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_bits_rd = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
cam_raw_3_bits_wb = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_idle = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_i0v = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_x_c_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_r_c_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_csrwen = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_csrwaddr = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_read_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_clr_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_set_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_write_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_imm_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
csrimm_x = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
csr_rddata_x = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_result_r_raw = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wbd_bits_csrwonly = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_566 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_legal = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf_second = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_icaf_type = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_fence_i = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_i0trigger = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_pmu_i0_itype = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
x_t_pmu_i0_br_unpred = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_legal = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf_second = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_icaf_type = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_fence_i = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_i0trigger = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_pmu_i0_itype = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
r_t_pmu_i0_br_unpred = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_d_bits_i0store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_x_c_mul = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_x_c_alu = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_r_c_mul = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_r_c_alu = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_i0store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_csrwen = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
x_d_bits_csrwaddr = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
last_br_immed_x = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_948 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_x = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_r = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_inst_wb = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pc_wb = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_i0_pc_r = 31'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
leak1_i1_stall <= 1'h0;
|
|
end else if (_T_3) begin
|
|
leak1_i1_stall <= leak1_i1_stall_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
leak1_i0_stall <= 1'h0;
|
|
end else if (_T_7) begin
|
|
leak1_i0_stall <= leak1_i0_stall_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12 <= 1'h0;
|
|
end else if (_T_11) begin
|
|
_T_12 <= io_dec_tlu_flush_extint;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
pause_stall <= 1'h0;
|
|
end else if (_T_15) begin
|
|
pause_stall <= pause_state_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
write_csr_data <= 32'h0;
|
|
end else if (csr_data_wen) begin
|
|
if (pause_stall) begin
|
|
write_csr_data <= _T_522;
|
|
end else if (io_dec_tlu_wr_pause_r) begin
|
|
write_csr_data <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
write_csr_data <= write_csr_data_x;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
illegal_lockout <= 1'h0;
|
|
end else if (_T_27) begin
|
|
illegal_lockout <= illegal_lockout_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
flush_final_r <= 1'h0;
|
|
end else if (_T_45) begin
|
|
flush_final_r <= io_exu_flush_final;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
postsync_stall <= 1'h0;
|
|
end else if (_T_31) begin
|
|
postsync_stall <= ps_stall_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_valid <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_valid <= io_dec_i0_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_trigger_match_r <= 4'h0;
|
|
end else if (_T_34) begin
|
|
lsu_trigger_match_r <= io_lsu_trigger_match_m;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_misaligned_r <= 1'h0;
|
|
end else if (_T_37) begin
|
|
lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_i0div <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_i0div <= d_d_bits_i0div;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_i0rd <= 5'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_i0rd <= i0r_rd;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_i0div <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_i0div <= x_d_bits_i0div;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_valid <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_valid <= x_d_in_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_i0rd <= 5'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_i0rd <= x_d_bits_i0rd;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_i0v <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_i0v <= x_d_in_bits_i0v;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_42 <= 1'h0;
|
|
end else if (_T_41) begin
|
|
_T_42 <= div_active_in;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_valid_x <= 1'h0;
|
|
end else if (_T_48) begin
|
|
debug_valid_x <= io_dec_debug_valid_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_bits_tag <= 3'h0;
|
|
end else if (_T_161) begin
|
|
if (cam_wen[0]) begin
|
|
cam_raw_0_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m};
|
|
end else if (_T_146) begin
|
|
cam_raw_0_bits_tag <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_valid <= 1'h0;
|
|
end else if (_T_161) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
cam_raw_0_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_0_valid <= _GEN_114;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_bits_tag <= 3'h0;
|
|
end else if (_T_197) begin
|
|
if (cam_wen[1]) begin
|
|
cam_raw_1_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m};
|
|
end else if (_T_182) begin
|
|
cam_raw_1_bits_tag <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_valid <= 1'h0;
|
|
end else if (_T_197) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
cam_raw_1_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_1_valid <= _GEN_129;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_bits_tag <= 3'h0;
|
|
end else if (_T_233) begin
|
|
if (cam_wen[2]) begin
|
|
cam_raw_2_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m};
|
|
end else if (_T_218) begin
|
|
cam_raw_2_bits_tag <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_valid <= 1'h0;
|
|
end else if (_T_233) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
cam_raw_2_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_2_valid <= _GEN_144;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_bits_tag <= 3'h0;
|
|
end else if (_T_269) begin
|
|
if (cam_wen[3]) begin
|
|
cam_raw_3_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m};
|
|
end else if (_T_254) begin
|
|
cam_raw_3_bits_tag <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_valid <= 1'h0;
|
|
end else if (_T_269) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
cam_raw_3_valid <= 1'h0;
|
|
end else begin
|
|
cam_raw_3_valid <= _GEN_159;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_i0load <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_i0load <= i0_d_c_load;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_816 <= 3'h0;
|
|
end else begin
|
|
_T_816 <= i0_pipe_en[3:1];
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
nonblock_load_valid_m_delay <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
nonblock_load_valid_m_delay <= io_dctl_busbuff_lsu_nonblock_load_valid_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_i0load <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_i0load <= x_d_bits_i0load;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_bits_rd <= 5'h0;
|
|
end else if (_T_161) begin
|
|
if (cam_wen[0]) begin
|
|
if (x_d_bits_i0load) begin
|
|
cam_raw_0_bits_rd <= x_d_bits_i0rd;
|
|
end else begin
|
|
cam_raw_0_bits_rd <= 5'h0;
|
|
end
|
|
end else if (_T_146) begin
|
|
cam_raw_0_bits_rd <= 5'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_0_bits_wb <= 1'h0;
|
|
end else if (_T_161) begin
|
|
cam_raw_0_bits_wb <= cam_in_0_bits_wb;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_bits_rd <= 5'h0;
|
|
end else if (_T_197) begin
|
|
if (cam_wen[1]) begin
|
|
if (x_d_bits_i0load) begin
|
|
cam_raw_1_bits_rd <= x_d_bits_i0rd;
|
|
end else begin
|
|
cam_raw_1_bits_rd <= 5'h0;
|
|
end
|
|
end else if (_T_182) begin
|
|
cam_raw_1_bits_rd <= 5'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_1_bits_wb <= 1'h0;
|
|
end else if (_T_197) begin
|
|
cam_raw_1_bits_wb <= cam_in_1_bits_wb;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_bits_rd <= 5'h0;
|
|
end else if (_T_233) begin
|
|
if (cam_wen[2]) begin
|
|
if (x_d_bits_i0load) begin
|
|
cam_raw_2_bits_rd <= x_d_bits_i0rd;
|
|
end else begin
|
|
cam_raw_2_bits_rd <= 5'h0;
|
|
end
|
|
end else if (_T_218) begin
|
|
cam_raw_2_bits_rd <= 5'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_2_bits_wb <= 1'h0;
|
|
end else if (_T_233) begin
|
|
cam_raw_2_bits_wb <= cam_in_2_bits_wb;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_bits_rd <= 5'h0;
|
|
end else if (_T_269) begin
|
|
if (cam_wen[3]) begin
|
|
if (x_d_bits_i0load) begin
|
|
cam_raw_3_bits_rd <= x_d_bits_i0rd;
|
|
end else begin
|
|
cam_raw_3_bits_rd <= 5'h0;
|
|
end
|
|
end else if (_T_254) begin
|
|
cam_raw_3_bits_rd <= 5'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
cam_raw_3_bits_wb <= 1'h0;
|
|
end else if (_T_269) begin
|
|
cam_raw_3_bits_wb <= cam_in_3_bits_wb;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_idle <= 1'h0;
|
|
end else begin
|
|
lsu_idle <= io_lsu_idle_any;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_i0v <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_i0v <= d_d_bits_i0v;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_x_c_load <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
i0_x_c_load <= i0_d_c_load;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_r_c_load <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
i0_r_c_load <= i0_x_c_load;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_csrwen <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_csrwen <= x_d_bits_csrwen;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_csrwaddr <= 12'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_csrwaddr <= x_d_bits_csrwaddr;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_read_x <= 1'h0;
|
|
end else begin
|
|
csr_read_x <= i0_dp_csr_read & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_clr_x <= 1'h0;
|
|
end else begin
|
|
csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_set_x <= 1'h0;
|
|
end else begin
|
|
csr_set_x <= i0_dp_csr_set & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_write_x <= 1'h0;
|
|
end else begin
|
|
csr_write_x <= i0_csr_write & i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
csr_imm_x <= 1'h0;
|
|
end else if (_T_80) begin
|
|
csr_imm_x <= 1'h0;
|
|
end else begin
|
|
csr_imm_x <= i0_dp_raw_csr_imm;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
csrimm_x <= 5'h0;
|
|
end else if (_T_459) begin
|
|
csrimm_x <= i0r_rs1;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
csr_rddata_x <= 32'h0;
|
|
end else if (_T_459) begin
|
|
csr_rddata_x <= io_dec_csr_rddata_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_csrwonly <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_csrwonly <= x_d_bits_csrwonly;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_result_r_raw <= 32'h0;
|
|
end else if (_T_877) begin
|
|
if (_T_879) begin
|
|
i0_result_r_raw <= io_lsu_result_m;
|
|
end else begin
|
|
i0_result_r_raw <= io_decode_exu_exu_i0_result_x;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_csrwonly <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_csrwonly <= d_d_bits_csrwonly;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wbd_bits_csrwonly <= 1'h0;
|
|
end else if (i0_wb_ctl_en) begin
|
|
wbd_bits_csrwonly <= r_d_bits_csrwonly;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_566 <= 32'h0;
|
|
end else if (illegal_inst_en) begin
|
|
if (io_dec_i0_pc4_d) begin
|
|
_T_566 <= io_dec_i0_instr_d;
|
|
end else begin
|
|
_T_566 <= _T_563;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_legal <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_legal <= i0_legal_decode_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_icaf <= d_t_icaf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf_second <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_icaf_second <= d_t_icaf_second;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_icaf_type <= 2'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_icaf_type <= io_dec_i0_icaf_type_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_fence_i <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_fence_i <= d_t_fence_i;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_i0trigger <= 4'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_i0trigger <= d_t_i0trigger;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_pmu_i0_itype <= 4'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_pmu_i0_itype <= d_t_pmu_i0_itype;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_t_pmu_i0_br_unpred <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_t_pmu_i0_br_unpred <= i0_br_unpred;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_legal <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_legal <= x_t_legal;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_icaf <= x_t_icaf;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf_second <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_icaf_second <= x_t_icaf_second;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_icaf_type <= 2'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_icaf_type <= x_t_icaf_type;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_fence_i <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_fence_i <= x_t_fence_i;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_i0trigger <= 4'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_i0trigger <= x_t_in_i0trigger;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_pmu_i0_itype <= 4'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_pmu_i0_itype <= x_t_pmu_i0_itype;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_t_pmu_i0_br_unpred <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_d_bits_i0store <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
r_d_bits_i0store <= x_d_bits_i0store;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_x_c_mul <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
i0_x_c_mul <= i0_d_c_mul;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_x_c_alu <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
i0_x_c_alu <= i0_d_c_alu;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_r_c_mul <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
i0_r_c_mul <= i0_x_c_mul;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
i0_r_c_alu <= 1'h0;
|
|
end else if (i0_r_ctl_en) begin
|
|
i0_r_c_alu <= i0_x_c_alu;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_i0store <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_i0store <= d_d_bits_i0store;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_csrwen <= 1'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
x_d_bits_csrwen <= d_d_bits_csrwen;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
x_d_bits_csrwaddr <= 12'h0;
|
|
end else if (i0_x_ctl_en) begin
|
|
if (d_d_bits_csrwen) begin
|
|
x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20];
|
|
end else begin
|
|
x_d_bits_csrwaddr <= 12'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
last_br_immed_x <= 12'h0;
|
|
end else if (i0_x_data_en) begin
|
|
if (io_decode_exu_i0_ap_predict_nt) begin
|
|
last_br_immed_x <= _T_899;
|
|
end else if (_T_399) begin
|
|
last_br_immed_x <= i0_pcall_imm[11:0];
|
|
end else begin
|
|
last_br_immed_x <= _T_408;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_948 <= 5'h0;
|
|
end else if (i0_div_decode_d) begin
|
|
_T_948 <= i0r_rd;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_x <= 32'h0;
|
|
end else if (_T_949) begin
|
|
if (io_dec_i0_pc4_d) begin
|
|
i0_inst_x <= io_dec_i0_instr_d;
|
|
end else begin
|
|
i0_inst_x <= _T_563;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_r <= 32'h0;
|
|
end else if (_T_951) begin
|
|
i0_inst_r <= i0_inst_x;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_inst_wb <= 32'h0;
|
|
end else if (_T_953) begin
|
|
i0_inst_wb <= i0_inst_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pc_wb <= 31'h0;
|
|
end else if (_T_953) begin
|
|
i0_pc_wb <= io_dec_tlu_i0_pc_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dec_i0_pc_r <= 31'h0;
|
|
end else if (i0_r_data_en) begin
|
|
dec_i0_pc_r <= io_dec_alu_exu_i0_pc_x;
|
|
end
|
|
end
|
|
endmodule
|
|
module dec_gpr_ctl(
|
|
input clock,
|
|
input reset,
|
|
input [4:0] io_raddr0,
|
|
input [4:0] io_raddr1,
|
|
input io_wen0,
|
|
input [4:0] io_waddr0,
|
|
input [31:0] io_wd0,
|
|
input io_wen1,
|
|
input [4:0] io_waddr1,
|
|
input [31:0] io_wd1,
|
|
input io_wen2,
|
|
input [4:0] io_waddr2,
|
|
input [31:0] io_wd2,
|
|
output [31:0] io_gpr_exu_gpr_i0_rs1_d,
|
|
output [31:0] io_gpr_exu_gpr_i0_rs2_d
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_en; // @[lib.scala 422:23]
|
|
wire _T = io_waddr0 == 5'h1; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_1 = io_wen0 & _T; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_2 = io_waddr1 == 5'h1; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_1 = io_wen1 & _T_2; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_4 = io_waddr2 == 5'h1; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_1 = io_wen2 & _T_4; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_8 = _T_7 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_11 = _T_10 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_12 = _T_8 | _T_11; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_15 = _T_14 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_1 = _T_12 | _T_15; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_17 = io_waddr0 == 5'h2; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_2 = io_wen0 & _T_17; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_19 = io_waddr1 == 5'h2; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_2 = io_wen1 & _T_19; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_21 = io_waddr2 == 5'h2; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_2 = io_wen2 & _T_21; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_25 = _T_24 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_28 = _T_27 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_29 = _T_25 | _T_28; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_32 = _T_31 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_2 = _T_29 | _T_32; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_34 = io_waddr0 == 5'h3; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_3 = io_wen0 & _T_34; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_36 = io_waddr1 == 5'h3; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_3 = io_wen1 & _T_36; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_38 = io_waddr2 == 5'h3; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_3 = io_wen2 & _T_38; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_42 = _T_41 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_45 = _T_44 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_46 = _T_42 | _T_45; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_49 = _T_48 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_3 = _T_46 | _T_49; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_51 = io_waddr0 == 5'h4; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_4 = io_wen0 & _T_51; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_53 = io_waddr1 == 5'h4; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_4 = io_wen1 & _T_53; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_55 = io_waddr2 == 5'h4; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_4 = io_wen2 & _T_55; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_59 = _T_58 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_62 = _T_61 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_63 = _T_59 | _T_62; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_66 = _T_65 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_4 = _T_63 | _T_66; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_68 = io_waddr0 == 5'h5; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_5 = io_wen0 & _T_68; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_70 = io_waddr1 == 5'h5; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_5 = io_wen1 & _T_70; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_72 = io_waddr2 == 5'h5; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_5 = io_wen2 & _T_72; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_76 = _T_75 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_79 = _T_78 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_80 = _T_76 | _T_79; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_83 = _T_82 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_5 = _T_80 | _T_83; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_85 = io_waddr0 == 5'h6; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_6 = io_wen0 & _T_85; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_87 = io_waddr1 == 5'h6; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_6 = io_wen1 & _T_87; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_89 = io_waddr2 == 5'h6; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_6 = io_wen2 & _T_89; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_93 = _T_92 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_96 = _T_95 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_97 = _T_93 | _T_96; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_100 = _T_99 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_6 = _T_97 | _T_100; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_102 = io_waddr0 == 5'h7; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_7 = io_wen0 & _T_102; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_104 = io_waddr1 == 5'h7; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_7 = io_wen1 & _T_104; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_106 = io_waddr2 == 5'h7; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_7 = io_wen2 & _T_106; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_110 = _T_109 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_113 = _T_112 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_114 = _T_110 | _T_113; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_117 = _T_116 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_7 = _T_114 | _T_117; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_119 = io_waddr0 == 5'h8; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_8 = io_wen0 & _T_119; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_121 = io_waddr1 == 5'h8; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_8 = io_wen1 & _T_121; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_123 = io_waddr2 == 5'h8; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_8 = io_wen2 & _T_123; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_127 = _T_126 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_130 = _T_129 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_131 = _T_127 | _T_130; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_134 = _T_133 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_8 = _T_131 | _T_134; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_136 = io_waddr0 == 5'h9; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_9 = io_wen0 & _T_136; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_138 = io_waddr1 == 5'h9; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_9 = io_wen1 & _T_138; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_140 = io_waddr2 == 5'h9; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_9 = io_wen2 & _T_140; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_144 = _T_143 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_147 = _T_146 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_148 = _T_144 | _T_147; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_151 = _T_150 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_9 = _T_148 | _T_151; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_153 = io_waddr0 == 5'ha; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_10 = io_wen0 & _T_153; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_155 = io_waddr1 == 5'ha; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_10 = io_wen1 & _T_155; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_157 = io_waddr2 == 5'ha; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_10 = io_wen2 & _T_157; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_161 = _T_160 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_164 = _T_163 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_165 = _T_161 | _T_164; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_168 = _T_167 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_10 = _T_165 | _T_168; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_170 = io_waddr0 == 5'hb; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_11 = io_wen0 & _T_170; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_172 = io_waddr1 == 5'hb; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_11 = io_wen1 & _T_172; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_174 = io_waddr2 == 5'hb; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_11 = io_wen2 & _T_174; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_178 = _T_177 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_181 = _T_180 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_182 = _T_178 | _T_181; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_185 = _T_184 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_11 = _T_182 | _T_185; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_187 = io_waddr0 == 5'hc; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_12 = io_wen0 & _T_187; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_189 = io_waddr1 == 5'hc; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_12 = io_wen1 & _T_189; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_191 = io_waddr2 == 5'hc; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_12 = io_wen2 & _T_191; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_195 = _T_194 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_198 = _T_197 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_199 = _T_195 | _T_198; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_202 = _T_201 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_12 = _T_199 | _T_202; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_204 = io_waddr0 == 5'hd; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_13 = io_wen0 & _T_204; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_206 = io_waddr1 == 5'hd; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_13 = io_wen1 & _T_206; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_208 = io_waddr2 == 5'hd; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_13 = io_wen2 & _T_208; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_212 = _T_211 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_215 = _T_214 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_216 = _T_212 | _T_215; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_219 = _T_218 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_13 = _T_216 | _T_219; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_221 = io_waddr0 == 5'he; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_14 = io_wen0 & _T_221; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_223 = io_waddr1 == 5'he; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_14 = io_wen1 & _T_223; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_225 = io_waddr2 == 5'he; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_14 = io_wen2 & _T_225; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_229 = _T_228 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_232 = _T_231 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_233 = _T_229 | _T_232; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_236 = _T_235 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_14 = _T_233 | _T_236; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_238 = io_waddr0 == 5'hf; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_15 = io_wen0 & _T_238; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_240 = io_waddr1 == 5'hf; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_15 = io_wen1 & _T_240; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_242 = io_waddr2 == 5'hf; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_15 = io_wen2 & _T_242; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_246 = _T_245 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_249 = _T_248 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_250 = _T_246 | _T_249; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_253 = _T_252 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_15 = _T_250 | _T_253; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_255 = io_waddr0 == 5'h10; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_16 = io_wen0 & _T_255; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_257 = io_waddr1 == 5'h10; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_16 = io_wen1 & _T_257; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_259 = io_waddr2 == 5'h10; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_16 = io_wen2 & _T_259; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_263 = _T_262 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_266 = _T_265 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_267 = _T_263 | _T_266; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_270 = _T_269 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_16 = _T_267 | _T_270; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_272 = io_waddr0 == 5'h11; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_17 = io_wen0 & _T_272; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_274 = io_waddr1 == 5'h11; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_17 = io_wen1 & _T_274; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_276 = io_waddr2 == 5'h11; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_17 = io_wen2 & _T_276; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_280 = _T_279 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_283 = _T_282 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_284 = _T_280 | _T_283; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_287 = _T_286 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_17 = _T_284 | _T_287; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_289 = io_waddr0 == 5'h12; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_18 = io_wen0 & _T_289; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_291 = io_waddr1 == 5'h12; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_18 = io_wen1 & _T_291; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_293 = io_waddr2 == 5'h12; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_18 = io_wen2 & _T_293; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_297 = _T_296 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_300 = _T_299 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_301 = _T_297 | _T_300; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_304 = _T_303 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_18 = _T_301 | _T_304; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_306 = io_waddr0 == 5'h13; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_19 = io_wen0 & _T_306; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_308 = io_waddr1 == 5'h13; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_19 = io_wen1 & _T_308; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_310 = io_waddr2 == 5'h13; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_19 = io_wen2 & _T_310; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_314 = _T_313 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_317 = _T_316 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_318 = _T_314 | _T_317; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_321 = _T_320 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_19 = _T_318 | _T_321; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_323 = io_waddr0 == 5'h14; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_20 = io_wen0 & _T_323; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_325 = io_waddr1 == 5'h14; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_20 = io_wen1 & _T_325; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_327 = io_waddr2 == 5'h14; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_20 = io_wen2 & _T_327; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_331 = _T_330 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_334 = _T_333 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_335 = _T_331 | _T_334; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_338 = _T_337 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_20 = _T_335 | _T_338; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_340 = io_waddr0 == 5'h15; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_21 = io_wen0 & _T_340; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_342 = io_waddr1 == 5'h15; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_21 = io_wen1 & _T_342; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_344 = io_waddr2 == 5'h15; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_21 = io_wen2 & _T_344; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_348 = _T_347 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_351 = _T_350 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_352 = _T_348 | _T_351; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_355 = _T_354 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_21 = _T_352 | _T_355; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_357 = io_waddr0 == 5'h16; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_22 = io_wen0 & _T_357; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_359 = io_waddr1 == 5'h16; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_22 = io_wen1 & _T_359; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_361 = io_waddr2 == 5'h16; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_22 = io_wen2 & _T_361; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_365 = _T_364 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_368 = _T_367 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_369 = _T_365 | _T_368; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_372 = _T_371 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_22 = _T_369 | _T_372; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_374 = io_waddr0 == 5'h17; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_23 = io_wen0 & _T_374; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_376 = io_waddr1 == 5'h17; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_23 = io_wen1 & _T_376; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_378 = io_waddr2 == 5'h17; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_23 = io_wen2 & _T_378; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_382 = _T_381 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_385 = _T_384 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_386 = _T_382 | _T_385; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_389 = _T_388 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_23 = _T_386 | _T_389; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_391 = io_waddr0 == 5'h18; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_24 = io_wen0 & _T_391; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_393 = io_waddr1 == 5'h18; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_24 = io_wen1 & _T_393; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_395 = io_waddr2 == 5'h18; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_24 = io_wen2 & _T_395; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_399 = _T_398 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_402 = _T_401 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_403 = _T_399 | _T_402; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_406 = _T_405 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_24 = _T_403 | _T_406; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_408 = io_waddr0 == 5'h19; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_25 = io_wen0 & _T_408; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_410 = io_waddr1 == 5'h19; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_25 = io_wen1 & _T_410; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_412 = io_waddr2 == 5'h19; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_25 = io_wen2 & _T_412; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_416 = _T_415 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_419 = _T_418 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_420 = _T_416 | _T_419; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_423 = _T_422 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_25 = _T_420 | _T_423; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_425 = io_waddr0 == 5'h1a; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_26 = io_wen0 & _T_425; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_427 = io_waddr1 == 5'h1a; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_26 = io_wen1 & _T_427; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_429 = io_waddr2 == 5'h1a; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_26 = io_wen2 & _T_429; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_433 = _T_432 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_436 = _T_435 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_437 = _T_433 | _T_436; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_440 = _T_439 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_26 = _T_437 | _T_440; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_442 = io_waddr0 == 5'h1b; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_27 = io_wen0 & _T_442; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_444 = io_waddr1 == 5'h1b; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_27 = io_wen1 & _T_444; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_446 = io_waddr2 == 5'h1b; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_27 = io_wen2 & _T_446; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_450 = _T_449 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_453 = _T_452 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_454 = _T_450 | _T_453; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_457 = _T_456 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_27 = _T_454 | _T_457; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_459 = io_waddr0 == 5'h1c; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_28 = io_wen0 & _T_459; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_461 = io_waddr1 == 5'h1c; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_28 = io_wen1 & _T_461; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_463 = io_waddr2 == 5'h1c; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_28 = io_wen2 & _T_463; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_467 = _T_466 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_470 = _T_469 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_471 = _T_467 | _T_470; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_474 = _T_473 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_28 = _T_471 | _T_474; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_476 = io_waddr0 == 5'h1d; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_29 = io_wen0 & _T_476; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_478 = io_waddr1 == 5'h1d; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_29 = io_wen1 & _T_478; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_480 = io_waddr2 == 5'h1d; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_29 = io_wen2 & _T_480; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_484 = _T_483 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_487 = _T_486 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_488 = _T_484 | _T_487; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_491 = _T_490 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_29 = _T_488 | _T_491; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_493 = io_waddr0 == 5'h1e; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_30 = io_wen0 & _T_493; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_495 = io_waddr1 == 5'h1e; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_30 = io_wen1 & _T_495; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_497 = io_waddr2 == 5'h1e; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_30 = io_wen2 & _T_497; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_501 = _T_500 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_504 = _T_503 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_505 = _T_501 | _T_504; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_508 = _T_507 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_30 = _T_505 | _T_508; // @[dec_gpr_ctl.scala 55:88]
|
|
wire _T_510 = io_waddr0 == 5'h1f; // @[dec_gpr_ctl.scala 52:52]
|
|
wire w0v_31 = io_wen0 & _T_510; // @[dec_gpr_ctl.scala 52:40]
|
|
wire _T_512 = io_waddr1 == 5'h1f; // @[dec_gpr_ctl.scala 53:52]
|
|
wire w1v_31 = io_wen1 & _T_512; // @[dec_gpr_ctl.scala 53:40]
|
|
wire _T_514 = io_waddr2 == 5'h1f; // @[dec_gpr_ctl.scala 54:52]
|
|
wire w2v_31 = io_wen2 & _T_514; // @[dec_gpr_ctl.scala 54:40]
|
|
wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_518 = _T_517 & io_wd0; // @[dec_gpr_ctl.scala 55:49]
|
|
wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_521 = _T_520 & io_wd1; // @[dec_gpr_ctl.scala 55:78]
|
|
wire [31:0] _T_522 = _T_518 | _T_521; // @[dec_gpr_ctl.scala 55:59]
|
|
wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_525 = _T_524 & io_wd2; // @[dec_gpr_ctl.scala 55:107]
|
|
wire [31:0] gpr_in_31 = _T_522 | _T_525; // @[dec_gpr_ctl.scala 55:88]
|
|
wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_589 = _T_557 | _T_588; // @[dec_gpr_ctl.scala 57:57]
|
|
wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58]
|
|
wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[dec_gpr_ctl.scala 57:95]
|
|
reg [31:0] gpr_out_1; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_2; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_3; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_4; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_5; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_6; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_7; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_8; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_9; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_10; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_11; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_12; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_13; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_14; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_15; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_16; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_17; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_18; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_19; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_20; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_21; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_22; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_23; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_24; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_25; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_26; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_27; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_28; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_29; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_30; // @[Reg.scala 27:20]
|
|
reg [31:0] gpr_out_31; // @[Reg.scala 27:20]
|
|
wire _T_684 = io_raddr0 == 5'h1; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_686 = io_raddr0 == 5'h2; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_688 = io_raddr0 == 5'h3; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_690 = io_raddr0 == 5'h4; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_692 = io_raddr0 == 5'h5; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_694 = io_raddr0 == 5'h6; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_696 = io_raddr0 == 5'h7; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_698 = io_raddr0 == 5'h8; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_700 = io_raddr0 == 5'h9; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_702 = io_raddr0 == 5'ha; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_704 = io_raddr0 == 5'hb; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_706 = io_raddr0 == 5'hc; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_708 = io_raddr0 == 5'hd; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_710 = io_raddr0 == 5'he; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_712 = io_raddr0 == 5'hf; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_714 = io_raddr0 == 5'h10; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_716 = io_raddr0 == 5'h11; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_718 = io_raddr0 == 5'h12; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_720 = io_raddr0 == 5'h13; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_722 = io_raddr0 == 5'h14; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_724 = io_raddr0 == 5'h15; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_726 = io_raddr0 == 5'h16; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_728 = io_raddr0 == 5'h17; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_730 = io_raddr0 == 5'h18; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_732 = io_raddr0 == 5'h19; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_734 = io_raddr0 == 5'h1a; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_736 = io_raddr0 == 5'h1b; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_738 = io_raddr0 == 5'h1c; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_740 = io_raddr0 == 5'h1d; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_742 = io_raddr0 == 5'h1e; // @[dec_gpr_ctl.scala 64:72]
|
|
wire _T_744 = io_raddr0 == 5'h1f; // @[dec_gpr_ctl.scala 64:72]
|
|
wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72]
|
|
wire _T_808 = io_raddr1 == 5'h1; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_810 = io_raddr1 == 5'h2; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_812 = io_raddr1 == 5'h3; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_814 = io_raddr1 == 5'h4; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_816 = io_raddr1 == 5'h5; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_818 = io_raddr1 == 5'h6; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_820 = io_raddr1 == 5'h7; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_822 = io_raddr1 == 5'h8; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_824 = io_raddr1 == 5'h9; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_826 = io_raddr1 == 5'ha; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_828 = io_raddr1 == 5'hb; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_830 = io_raddr1 == 5'hc; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_832 = io_raddr1 == 5'hd; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_834 = io_raddr1 == 5'he; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_836 = io_raddr1 == 5'hf; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_838 = io_raddr1 == 5'h10; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_840 = io_raddr1 == 5'h11; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_842 = io_raddr1 == 5'h12; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_844 = io_raddr1 == 5'h13; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_846 = io_raddr1 == 5'h14; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_848 = io_raddr1 == 5'h15; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_850 = io_raddr1 == 5'h16; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_852 = io_raddr1 == 5'h17; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_854 = io_raddr1 == 5'h18; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_856 = io_raddr1 == 5'h19; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_858 = io_raddr1 == 5'h1a; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_860 = io_raddr1 == 5'h1b; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_862 = io_raddr1 == 5'h1c; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_864 = io_raddr1 == 5'h1d; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_866 = io_raddr1 == 5'h1e; // @[dec_gpr_ctl.scala 65:72]
|
|
wire _T_868 = io_raddr1 == 5'h1f; // @[dec_gpr_ctl.scala 65:72]
|
|
wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en)
|
|
);
|
|
assign io_gpr_exu_gpr_i0_rs1_d = _T_805 | _T_776; // @[dec_gpr_ctl.scala 48:32 dec_gpr_ctl.scala 64:32]
|
|
assign io_gpr_exu_gpr_i0_rs2_d = _T_929 | _T_900; // @[dec_gpr_ctl.scala 49:32 dec_gpr_ctl.scala 65:32]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = gpr_wr_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_16_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_17_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_18_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_19_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_20_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_21_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_22_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_23_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_24_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_25_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_26_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_27_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_28_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_29_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_30_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
gpr_out_1 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
gpr_out_2 = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
gpr_out_3 = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
gpr_out_4 = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
gpr_out_5 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
gpr_out_6 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
gpr_out_7 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
gpr_out_8 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
gpr_out_9 = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
gpr_out_10 = _RAND_9[31:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
gpr_out_11 = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
gpr_out_12 = _RAND_11[31:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
gpr_out_13 = _RAND_12[31:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
gpr_out_14 = _RAND_13[31:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
gpr_out_15 = _RAND_14[31:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
gpr_out_16 = _RAND_15[31:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
gpr_out_17 = _RAND_16[31:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
gpr_out_18 = _RAND_17[31:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
gpr_out_19 = _RAND_18[31:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
gpr_out_20 = _RAND_19[31:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
gpr_out_21 = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
gpr_out_22 = _RAND_21[31:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
gpr_out_23 = _RAND_22[31:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
gpr_out_24 = _RAND_23[31:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
gpr_out_25 = _RAND_24[31:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
gpr_out_26 = _RAND_25[31:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
gpr_out_27 = _RAND_26[31:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
gpr_out_28 = _RAND_27[31:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
gpr_out_29 = _RAND_28[31:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
gpr_out_30 = _RAND_29[31:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
gpr_out_31 = _RAND_30[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
gpr_out_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_7 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_8 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_9 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_10 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_11 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_12 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_13 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_14 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_15 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_16 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_17 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_18 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_19 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_20 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_21 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_22 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_23 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_24 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_25 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_26 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_27 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_28 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_29 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_30 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gpr_out_31 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_1 <= 32'h0;
|
|
end else if (gpr_wr_en[1]) begin
|
|
gpr_out_1 <= gpr_in_1;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_2 <= 32'h0;
|
|
end else if (gpr_wr_en[2]) begin
|
|
gpr_out_2 <= gpr_in_2;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_3 <= 32'h0;
|
|
end else if (gpr_wr_en[3]) begin
|
|
gpr_out_3 <= gpr_in_3;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_4 <= 32'h0;
|
|
end else if (gpr_wr_en[4]) begin
|
|
gpr_out_4 <= gpr_in_4;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_5 <= 32'h0;
|
|
end else if (gpr_wr_en[5]) begin
|
|
gpr_out_5 <= gpr_in_5;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_6 <= 32'h0;
|
|
end else if (gpr_wr_en[6]) begin
|
|
gpr_out_6 <= gpr_in_6;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_7 <= 32'h0;
|
|
end else if (gpr_wr_en[7]) begin
|
|
gpr_out_7 <= gpr_in_7;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_8 <= 32'h0;
|
|
end else if (gpr_wr_en[8]) begin
|
|
gpr_out_8 <= gpr_in_8;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_9 <= 32'h0;
|
|
end else if (gpr_wr_en[9]) begin
|
|
gpr_out_9 <= gpr_in_9;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_10 <= 32'h0;
|
|
end else if (gpr_wr_en[10]) begin
|
|
gpr_out_10 <= gpr_in_10;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_11 <= 32'h0;
|
|
end else if (gpr_wr_en[11]) begin
|
|
gpr_out_11 <= gpr_in_11;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_12 <= 32'h0;
|
|
end else if (gpr_wr_en[12]) begin
|
|
gpr_out_12 <= gpr_in_12;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_13 <= 32'h0;
|
|
end else if (gpr_wr_en[13]) begin
|
|
gpr_out_13 <= gpr_in_13;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_14 <= 32'h0;
|
|
end else if (gpr_wr_en[14]) begin
|
|
gpr_out_14 <= gpr_in_14;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_15 <= 32'h0;
|
|
end else if (gpr_wr_en[15]) begin
|
|
gpr_out_15 <= gpr_in_15;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_16 <= 32'h0;
|
|
end else if (gpr_wr_en[16]) begin
|
|
gpr_out_16 <= gpr_in_16;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_17 <= 32'h0;
|
|
end else if (gpr_wr_en[17]) begin
|
|
gpr_out_17 <= gpr_in_17;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_18 <= 32'h0;
|
|
end else if (gpr_wr_en[18]) begin
|
|
gpr_out_18 <= gpr_in_18;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_19 <= 32'h0;
|
|
end else if (gpr_wr_en[19]) begin
|
|
gpr_out_19 <= gpr_in_19;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_20 <= 32'h0;
|
|
end else if (gpr_wr_en[20]) begin
|
|
gpr_out_20 <= gpr_in_20;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_21 <= 32'h0;
|
|
end else if (gpr_wr_en[21]) begin
|
|
gpr_out_21 <= gpr_in_21;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_22 <= 32'h0;
|
|
end else if (gpr_wr_en[22]) begin
|
|
gpr_out_22 <= gpr_in_22;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_23 <= 32'h0;
|
|
end else if (gpr_wr_en[23]) begin
|
|
gpr_out_23 <= gpr_in_23;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_24 <= 32'h0;
|
|
end else if (gpr_wr_en[24]) begin
|
|
gpr_out_24 <= gpr_in_24;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_25 <= 32'h0;
|
|
end else if (gpr_wr_en[25]) begin
|
|
gpr_out_25 <= gpr_in_25;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_26 <= 32'h0;
|
|
end else if (gpr_wr_en[26]) begin
|
|
gpr_out_26 <= gpr_in_26;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_27 <= 32'h0;
|
|
end else if (gpr_wr_en[27]) begin
|
|
gpr_out_27 <= gpr_in_27;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_28 <= 32'h0;
|
|
end else if (gpr_wr_en[28]) begin
|
|
gpr_out_28 <= gpr_in_28;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_29 <= 32'h0;
|
|
end else if (gpr_wr_en[29]) begin
|
|
gpr_out_29 <= gpr_in_29;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_30 <= 32'h0;
|
|
end else if (gpr_wr_en[30]) begin
|
|
gpr_out_30 <= gpr_in_30;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gpr_out_31 <= 32'h0;
|
|
end else if (gpr_wr_en[31]) begin
|
|
gpr_out_31 <= gpr_in_31;
|
|
end
|
|
end
|
|
endmodule
|
|
module int_exc(
|
|
input clock,
|
|
input reset,
|
|
output io_mhwakeup_ready,
|
|
output io_ext_int_ready,
|
|
output io_ce_int_ready,
|
|
output io_soft_int_ready,
|
|
output io_timer_int_ready,
|
|
output io_int_timer0_int_hold,
|
|
output io_int_timer1_int_hold,
|
|
output io_internal_dbg_halt_timers,
|
|
output io_take_ext_int_start,
|
|
input io_ext_int_freeze_d1,
|
|
input io_take_ext_int_start_d1,
|
|
input io_take_ext_int_start_d2,
|
|
input io_take_ext_int_start_d3,
|
|
output io_ext_int_freeze,
|
|
output io_take_ext_int,
|
|
output io_fast_int_meicpct,
|
|
output io_ignore_ext_int_due_to_lsu_stall,
|
|
output io_take_ce_int,
|
|
output io_take_soft_int,
|
|
output io_take_timer_int,
|
|
output io_take_int_timer0_int,
|
|
output io_take_int_timer1_int,
|
|
output io_take_reset,
|
|
output io_take_nmi,
|
|
output io_synchronous_flush_r,
|
|
output io_tlu_flush_lower_r,
|
|
output io_dec_tlu_flush_lower_wb,
|
|
output io_dec_tlu_flush_lower_r,
|
|
output [30:0] io_dec_tlu_flush_path_r,
|
|
output io_interrupt_valid_r_d1,
|
|
output io_i0_exception_valid_r_d1,
|
|
output io_exc_or_int_valid_r_d1,
|
|
output [4:0] io_exc_cause_wb,
|
|
output io_i0_valid_wb,
|
|
output io_trigger_hit_r_d1,
|
|
output io_take_nmi_r_d1,
|
|
output io_interrupt_valid_r,
|
|
output [4:0] io_exc_cause_r,
|
|
output io_i0_exception_valid_r,
|
|
output [30:0] io_tlu_flush_path_r_d1,
|
|
output io_exc_or_int_valid_r,
|
|
input io_dec_csr_stall_int_ff,
|
|
input io_mstatus_mie_ns,
|
|
input [5:0] io_mip,
|
|
input [5:0] io_mie_ns,
|
|
input io_mret_r,
|
|
input io_pmu_fw_tlu_halted_f,
|
|
input io_int_timer0_int_hold_f,
|
|
input io_int_timer1_int_hold_f,
|
|
input io_internal_dbg_halt_mode_f,
|
|
input io_dcsr_single_step_running,
|
|
input io_internal_dbg_halt_mode,
|
|
input io_dec_tlu_i0_valid_r,
|
|
input io_internal_pmu_fw_halt_mode,
|
|
input io_i_cpu_halt_req_d1,
|
|
input io_ebreak_to_debug_mode_r,
|
|
input [1:0] io_lsu_fir_error,
|
|
input io_csr_pkt_csr_meicpct,
|
|
input io_dec_csr_any_unq_d,
|
|
input io_lsu_fastint_stall_any,
|
|
input io_reset_delayed,
|
|
input io_mpc_reset_run_req,
|
|
input io_nmi_int_detected,
|
|
input io_dcsr_single_step_running_f,
|
|
input io_dcsr_single_step_done_f,
|
|
input [15:0] io_dcsr,
|
|
input [30:0] io_mtvec,
|
|
input io_tlu_i0_commit_cmt,
|
|
input io_i0_trigger_hit_r,
|
|
input io_pause_expired_r,
|
|
input [30:0] io_nmi_vec,
|
|
input io_lsu_i0_rfnpc_r,
|
|
input io_fence_i_r,
|
|
input io_iccm_repair_state_rfnpc,
|
|
input io_i_cpu_run_req_d1,
|
|
input io_rfpc_i0_r,
|
|
input io_lsu_exc_valid_r,
|
|
input io_trigger_hit_dmode_r,
|
|
input io_take_halt,
|
|
input [30:0] io_rst_vec,
|
|
input [30:0] io_lsu_fir_addr,
|
|
input [30:0] io_dec_tlu_i0_pc_r,
|
|
input [30:0] io_npc_r,
|
|
input [30:0] io_mepc,
|
|
input io_debug_resume_req_f,
|
|
input [30:0] io_dpc,
|
|
input [30:0] io_npc_r_d1,
|
|
input io_tlu_flush_lower_r_d1,
|
|
input io_dec_tlu_dbg_halted,
|
|
input io_ebreak_r,
|
|
input io_ecall_r,
|
|
input io_illegal_r,
|
|
input io_inst_acc_r,
|
|
input io_lsu_i0_exc_r,
|
|
input io_lsu_error_pkt_r_bits_inst_type,
|
|
input io_lsu_error_pkt_r_bits_exc_type,
|
|
input io_dec_tlu_wr_pause_r_d1
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire _T = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3017:48]
|
|
wire lsu_exc_ma_r = io_lsu_i0_exc_r & _T; // @[dec_tlu_ctl.scala 3017:46]
|
|
wire lsu_exc_acc_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3018:46]
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wire lsu_exc_st_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 3019:46]
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wire _T_1 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 3031:49]
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wire _T_2 = _T_1 | io_illegal_r; // @[dec_tlu_ctl.scala 3031:62]
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wire _T_3 = _T_2 | io_inst_acc_r; // @[dec_tlu_ctl.scala 3031:77]
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wire _T_4 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3031:96]
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wire _T_5 = _T_3 & _T_4; // @[dec_tlu_ctl.scala 3031:94]
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wire _T_6 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 3031:112]
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wire [4:0] _T_9 = io_take_nmi ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
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wire [4:0] _T_10 = ~_T_9; // @[dec_tlu_ctl.scala 3039:27]
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wire _T_20 = io_ebreak_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3049:31]
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wire _T_22 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 3050:33]
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wire _T_23 = lsu_exc_ma_r & _T_22; // @[dec_tlu_ctl.scala 3050:31]
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wire _T_26 = lsu_exc_acc_r & _T_22; // @[dec_tlu_ctl.scala 3051:32]
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wire _T_28 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3052:31]
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wire _T_30 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3053:32]
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wire [4:0] _T_32 = io_take_ext_int ? 5'hb : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_33 = io_take_timer_int ? 5'h7 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_34 = io_take_soft_int ? 5'h3 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_35 = io_take_int_timer0_int ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_36 = io_take_int_timer1_int ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_37 = io_take_ce_int ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_38 = io_illegal_r ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_39 = io_ecall_r ? 5'hb : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_40 = io_inst_acc_r ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_41 = _T_20 ? 5'h3 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_42 = _T_23 ? 5'h4 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_43 = _T_26 ? 5'h5 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_44 = _T_28 ? 5'h6 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_45 = _T_30 ? 5'h7 : 5'h0; // @[Mux.scala 27:72]
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wire [4:0] _T_46 = _T_32 | _T_33; // @[Mux.scala 27:72]
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wire [4:0] _T_47 = _T_46 | _T_34; // @[Mux.scala 27:72]
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wire [4:0] _T_48 = _T_47 | _T_35; // @[Mux.scala 27:72]
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wire [4:0] _T_49 = _T_48 | _T_36; // @[Mux.scala 27:72]
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wire [4:0] _T_50 = _T_49 | _T_37; // @[Mux.scala 27:72]
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wire [4:0] _T_51 = _T_50 | _T_38; // @[Mux.scala 27:72]
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wire [4:0] _T_52 = _T_51 | _T_39; // @[Mux.scala 27:72]
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wire [4:0] _T_53 = _T_52 | _T_40; // @[Mux.scala 27:72]
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wire [4:0] _T_54 = _T_53 | _T_41; // @[Mux.scala 27:72]
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wire [4:0] _T_55 = _T_54 | _T_42; // @[Mux.scala 27:72]
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wire [4:0] _T_56 = _T_55 | _T_43; // @[Mux.scala 27:72]
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wire [4:0] _T_57 = _T_56 | _T_44; // @[Mux.scala 27:72]
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wire [4:0] _T_58 = _T_57 | _T_45; // @[Mux.scala 27:72]
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wire _T_61 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 3064:31]
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wire _T_62 = _T_61 & io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 3064:56]
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wire _T_64 = _T_62 & io_mip[2]; // @[dec_tlu_ctl.scala 3064:76]
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wire _T_66 = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:97]
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wire _T_73 = ~io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 3065:121]
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wire [5:0] _T_77 = {{5'd0}, io_mip[5]}; // @[dec_tlu_ctl.scala 3066:84]
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wire _T_79 = _T_62 & _T_77[0]; // @[dec_tlu_ctl.scala 3066:76]
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wire _T_85 = _T_62 & io_mip[0]; // @[dec_tlu_ctl.scala 3067:76]
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wire _T_91 = _T_62 & io_mip[1]; // @[dec_tlu_ctl.scala 3068:76]
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wire int_timer0_int_possible = io_mstatus_mie_ns & io_mie_ns[4]; // @[dec_tlu_ctl.scala 3071:57]
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wire [5:0] _T_95 = {{4'd0}, io_mip[5:4]}; // @[dec_tlu_ctl.scala 3072:42]
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wire int_timer0_int_ready = _T_95[0] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3072:55]
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wire int_timer1_int_possible = io_mstatus_mie_ns & io_mie_ns[3]; // @[dec_tlu_ctl.scala 3073:57]
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wire [5:0] _T_98 = {{3'd0}, io_mip[5:3]}; // @[dec_tlu_ctl.scala 3074:42]
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wire int_timer1_int_ready = _T_98[0] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3074:55]
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wire _T_100 = io_dec_csr_stall_int_ff | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3078:57]
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wire _T_101 = _T_100 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3078:82]
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wire int_timer_stalled = _T_101 | io_mret_r; // @[dec_tlu_ctl.scala 3078:109]
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wire _T_102 = io_pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 3080:83]
|
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wire _T_103 = int_timer0_int_ready & _T_102; // @[dec_tlu_ctl.scala 3080:57]
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wire _T_104 = int_timer0_int_possible & io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3080:132]
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wire _T_105 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3080:161]
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wire _T_106 = _T_104 & _T_105; // @[dec_tlu_ctl.scala 3080:159]
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wire _T_107 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 3080:185]
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wire _T_108 = _T_106 & _T_107; // @[dec_tlu_ctl.scala 3080:183]
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wire _T_109 = ~io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 3080:210]
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wire _T_110 = _T_108 & _T_109; // @[dec_tlu_ctl.scala 3080:208]
|
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wire _T_113 = int_timer1_int_ready & _T_102; // @[dec_tlu_ctl.scala 3081:57]
|
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wire _T_114 = int_timer1_int_possible & io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3081:132]
|
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wire _T_116 = _T_114 & _T_105; // @[dec_tlu_ctl.scala 3081:159]
|
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wire _T_118 = _T_116 & _T_107; // @[dec_tlu_ctl.scala 3081:183]
|
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wire _T_120 = _T_118 & _T_109; // @[dec_tlu_ctl.scala 3081:208]
|
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wire _T_122 = ~io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 3083:70]
|
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wire _T_125 = _T_122 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3085:92]
|
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wire _T_126 = io_internal_dbg_halt_mode & _T_125; // @[dec_tlu_ctl.scala 3085:60]
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wire _T_127 = _T_126 | io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3085:118]
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wire _T_128 = _T_127 | io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 3085:149]
|
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wire _T_129 = _T_128 | io_take_nmi; // @[dec_tlu_ctl.scala 3085:172]
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wire _T_130 = _T_129 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3085:186]
|
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wire _T_131 = _T_130 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3085:214]
|
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wire _T_132 = _T_131 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3085:240]
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wire _T_133 = _T_132 | io_mret_r; // @[dec_tlu_ctl.scala 3085:267]
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wire block_interrupts = _T_133 | io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3085:279]
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wire _T_134 = ~block_interrupts; // @[dec_tlu_ctl.scala 3093:61]
|
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wire _T_136 = io_take_ext_int_start | io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 3094:60]
|
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wire _T_137 = _T_136 | io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 3094:87]
|
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wire _T_139 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 3095:81]
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wire _T_140 = ~_T_139; // @[dec_tlu_ctl.scala 3095:63]
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wire _T_141 = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:61]
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wire _T_143 = ~io_ext_int_ready; // @[dec_tlu_ctl.scala 3110:46]
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wire _T_144 = io_ce_int_ready & _T_143; // @[dec_tlu_ctl.scala 3110:44]
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wire _T_148 = io_soft_int_ready & _T_143; // @[dec_tlu_ctl.scala 3111:47]
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wire _T_149 = ~io_ce_int_ready; // @[dec_tlu_ctl.scala 3111:69]
|
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wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 3111:67]
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wire _T_153 = ~io_soft_int_ready; // @[dec_tlu_ctl.scala 3112:51]
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wire _T_154 = io_timer_int_ready & _T_153; // @[dec_tlu_ctl.scala 3112:49]
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wire _T_156 = _T_154 & _T_143; // @[dec_tlu_ctl.scala 3112:70]
|
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wire _T_158 = _T_156 & _T_149; // @[dec_tlu_ctl.scala 3112:90]
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wire _T_161 = int_timer0_int_ready | io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3113:57]
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wire _T_162 = _T_161 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3113:85]
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wire _T_164 = _T_162 & _T_61; // @[dec_tlu_ctl.scala 3113:111]
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wire _T_165 = ~io_timer_int_ready; // @[dec_tlu_ctl.scala 3113:140]
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wire _T_166 = _T_164 & _T_165; // @[dec_tlu_ctl.scala 3113:138]
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wire _T_168 = _T_166 & _T_153; // @[dec_tlu_ctl.scala 3113:160]
|
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wire _T_170 = _T_168 & _T_143; // @[dec_tlu_ctl.scala 3113:181]
|
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wire _T_172 = _T_170 & _T_149; // @[dec_tlu_ctl.scala 3113:201]
|
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wire _T_175 = int_timer1_int_ready | io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3114:57]
|
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wire _T_176 = _T_175 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3114:85]
|
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wire _T_178 = _T_176 & _T_61; // @[dec_tlu_ctl.scala 3114:111]
|
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wire _T_180 = ~_T_161; // @[dec_tlu_ctl.scala 3114:140]
|
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wire _T_181 = _T_178 & _T_180; // @[dec_tlu_ctl.scala 3114:138]
|
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wire _T_183 = _T_181 & _T_165; // @[dec_tlu_ctl.scala 3114:191]
|
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wire _T_185 = _T_183 & _T_153; // @[dec_tlu_ctl.scala 3114:213]
|
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wire _T_187 = _T_185 & _T_143; // @[dec_tlu_ctl.scala 3114:234]
|
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wire _T_189 = _T_187 & _T_149; // @[dec_tlu_ctl.scala 3114:254]
|
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wire _T_193 = ~io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3116:46]
|
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wire _T_194 = io_nmi_int_detected & _T_193; // @[dec_tlu_ctl.scala 3116:44]
|
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wire _T_195 = ~io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 3116:79]
|
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wire _T_197 = io_dcsr_single_step_running_f & io_dcsr[11]; // @[dec_tlu_ctl.scala 3116:139]
|
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wire _T_198 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3116:164]
|
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wire _T_199 = _T_197 & _T_198; // @[dec_tlu_ctl.scala 3116:162]
|
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wire _T_200 = ~io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 3116:189]
|
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wire _T_201 = _T_199 & _T_200; // @[dec_tlu_ctl.scala 3116:187]
|
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wire _T_202 = _T_195 | _T_201; // @[dec_tlu_ctl.scala 3116:106]
|
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wire _T_203 = _T_194 & _T_202; // @[dec_tlu_ctl.scala 3116:76]
|
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wire _T_204 = ~io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3116:220]
|
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wire _T_205 = _T_203 & _T_204; // @[dec_tlu_ctl.scala 3116:218]
|
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wire _T_206 = ~io_mret_r; // @[dec_tlu_ctl.scala 3116:246]
|
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wire _T_207 = _T_205 & _T_206; // @[dec_tlu_ctl.scala 3116:244]
|
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wire _T_208 = ~io_take_reset; // @[dec_tlu_ctl.scala 3116:259]
|
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wire _T_209 = _T_207 & _T_208; // @[dec_tlu_ctl.scala 3116:257]
|
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wire _T_210 = ~io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3116:276]
|
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wire _T_211 = _T_209 & _T_210; // @[dec_tlu_ctl.scala 3116:274]
|
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wire _T_212 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3116:306]
|
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wire _T_214 = io_take_ext_int_start_d3 & _T_139; // @[dec_tlu_ctl.scala 3116:356]
|
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wire _T_215 = _T_212 | _T_214; // @[dec_tlu_ctl.scala 3116:328]
|
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wire _T_217 = io_take_ext_int | io_take_timer_int; // @[dec_tlu_ctl.scala 3120:49]
|
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wire _T_218 = _T_217 | io_take_soft_int; // @[dec_tlu_ctl.scala 3120:69]
|
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wire _T_219 = _T_218 | io_take_nmi; // @[dec_tlu_ctl.scala 3120:88]
|
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wire _T_220 = _T_219 | io_take_ce_int; // @[dec_tlu_ctl.scala 3120:102]
|
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wire _T_221 = _T_220 | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 3120:119]
|
|
wire [30:0] _T_224 = {io_mtvec[30:1],1'h0}; // @[Cat.scala 29:58]
|
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wire [30:0] _T_226 = {25'h0,io_exc_cause_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [30:0] vectored_path = _T_224 + _T_226; // @[dec_tlu_ctl.scala 3125:59]
|
|
wire [30:0] _T_233 = io_mtvec[0] ? vectored_path : _T_224; // @[dec_tlu_ctl.scala 3126:69]
|
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wire [30:0] interrupt_path = io_take_nmi ? io_nmi_vec : _T_233; // @[dec_tlu_ctl.scala 3126:33]
|
|
wire _T_234 = io_lsu_i0_rfnpc_r | io_fence_i_r; // @[dec_tlu_ctl.scala 3127:44]
|
|
wire _T_235 = _T_234 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3127:59]
|
|
wire _T_237 = io_i_cpu_run_req_d1 & _T_105; // @[dec_tlu_ctl.scala 3127:111]
|
|
wire _T_238 = _T_235 | _T_237; // @[dec_tlu_ctl.scala 3127:88]
|
|
wire _T_240 = io_rfpc_i0_r & _T_198; // @[dec_tlu_ctl.scala 3127:152]
|
|
wire sel_npc_r = _T_238 | _T_240; // @[dec_tlu_ctl.scala 3127:136]
|
|
wire _T_241 = io_i_cpu_run_req_d1 & io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 3128:51]
|
|
wire sel_npc_resume = _T_241 | io_pause_expired_r; // @[dec_tlu_ctl.scala 3128:77]
|
|
wire _T_244 = io_i0_exception_valid_r | io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3130:60]
|
|
wire _T_245 = _T_244 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3130:75]
|
|
wire _T_246 = _T_245 | io_fence_i_r; // @[dec_tlu_ctl.scala 3130:96]
|
|
wire _T_247 = _T_246 | io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 3130:111]
|
|
wire _T_248 = _T_247 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3130:131]
|
|
wire _T_249 = _T_248 | io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3130:161]
|
|
wire _T_250 = _T_249 | sel_npc_resume; // @[dec_tlu_ctl.scala 3130:186]
|
|
wire _T_251 = _T_250 | io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 3130:204]
|
|
wire _T_253 = io_interrupt_valid_r | io_mret_r; // @[dec_tlu_ctl.scala 3131:54]
|
|
wire _T_254 = _T_253 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3131:66]
|
|
wire _T_255 = _T_254 | io_take_halt; // @[dec_tlu_ctl.scala 3131:91]
|
|
wire _T_256 = _T_255 | io_take_reset; // @[dec_tlu_ctl.scala 3131:106]
|
|
wire _T_260 = ~io_take_nmi; // @[dec_tlu_ctl.scala 3135:29]
|
|
wire _T_262 = _T_260 & sel_npc_r; // @[dec_tlu_ctl.scala 3135:36]
|
|
wire _T_265 = _T_260 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3136:36]
|
|
wire _T_267 = _T_265 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3136:57]
|
|
wire _T_268 = ~sel_npc_r; // @[dec_tlu_ctl.scala 3136:98]
|
|
wire _T_269 = _T_267 & _T_268; // @[dec_tlu_ctl.scala 3136:87]
|
|
wire _T_271 = ~_T_141; // @[dec_tlu_ctl.scala 3137:59]
|
|
wire _T_272 = io_interrupt_valid_r & _T_271; // @[dec_tlu_ctl.scala 3137:45]
|
|
wire _T_273 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3138:43]
|
|
wire _T_274 = ~io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 3138:89]
|
|
wire _T_275 = io_i0_trigger_hit_r & _T_274; // @[dec_tlu_ctl.scala 3138:87]
|
|
wire _T_276 = _T_273 | _T_275; // @[dec_tlu_ctl.scala 3138:64]
|
|
wire _T_278 = _T_276 & _T_105; // @[dec_tlu_ctl.scala 3138:115]
|
|
wire _T_280 = _T_278 & _T_271; // @[dec_tlu_ctl.scala 3138:139]
|
|
wire _T_285 = _T_260 & io_mret_r; // @[dec_tlu_ctl.scala 3139:31]
|
|
wire _T_288 = _T_260 & io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3140:31]
|
|
wire _T_291 = _T_260 & sel_npc_resume; // @[dec_tlu_ctl.scala 3141:31]
|
|
wire [30:0] _T_293 = _T_141 ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_294 = _T_262 ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_295 = _T_269 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_296 = _T_272 ? interrupt_path : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_297 = _T_280 ? _T_224 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_298 = _T_285 ? io_mepc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_299 = _T_288 ? io_dpc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_300 = _T_291 ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_301 = _T_293 | _T_294; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_302 = _T_301 | _T_295; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_303 = _T_302 | _T_296; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_304 = _T_303 | _T_297; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_305 = _T_304 | _T_298; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_306 = _T_305 | _T_299; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_307 = _T_306 | _T_300; // @[Mux.scala 27:72]
|
|
reg [30:0] _T_311; // @[Reg.scala 27:20]
|
|
wire _T_312 = io_lsu_exc_valid_r | io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 3152:53]
|
|
wire _T_313 = _T_312 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3152:79]
|
|
reg _T_320; // @[Reg.scala 27:20]
|
|
wire _T_318 = io_interrupt_valid_r ^ _T_320; // @[lib.scala 466:21]
|
|
wire _T_319 = |_T_318; // @[lib.scala 466:29]
|
|
reg _T_324; // @[Reg.scala 27:20]
|
|
wire _T_322 = io_i0_exception_valid_r ^ _T_324; // @[lib.scala 466:21]
|
|
wire _T_323 = |_T_322; // @[lib.scala 466:29]
|
|
reg _T_328; // @[Reg.scala 27:20]
|
|
wire _T_326 = io_exc_or_int_valid_r ^ _T_328; // @[lib.scala 466:21]
|
|
wire _T_327 = |_T_326; // @[lib.scala 466:29]
|
|
reg [4:0] _T_332; // @[Reg.scala 27:20]
|
|
wire [4:0] _T_330 = io_exc_cause_r ^ _T_332; // @[lib.scala 466:21]
|
|
wire _T_331 = |_T_330; // @[lib.scala 466:29]
|
|
wire _T_333 = ~io_illegal_r; // @[dec_tlu_ctl.scala 3158:104]
|
|
wire _T_334 = io_tlu_i0_commit_cmt & _T_333; // @[dec_tlu_ctl.scala 3158:102]
|
|
reg _T_338; // @[Reg.scala 27:20]
|
|
wire _T_336 = _T_334 ^ _T_338; // @[lib.scala 466:21]
|
|
wire _T_337 = |_T_336; // @[lib.scala 466:29]
|
|
reg _T_342; // @[Reg.scala 27:20]
|
|
wire _T_340 = io_i0_trigger_hit_r ^ _T_342; // @[lib.scala 466:21]
|
|
wire _T_341 = |_T_340; // @[lib.scala 466:29]
|
|
reg _T_346; // @[Reg.scala 27:20]
|
|
wire _T_344 = io_take_nmi ^ _T_346; // @[lib.scala 466:21]
|
|
wire _T_345 = |_T_344; // @[lib.scala 466:29]
|
|
assign io_mhwakeup_ready = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:28]
|
|
assign io_ext_int_ready = _T_66 & _T_73; // @[dec_tlu_ctl.scala 3065:28]
|
|
assign io_ce_int_ready = _T_79 & io_mie_ns[5]; // @[dec_tlu_ctl.scala 3066:28]
|
|
assign io_soft_int_ready = _T_85 & io_mie_ns[0]; // @[dec_tlu_ctl.scala 3067:28]
|
|
assign io_timer_int_ready = _T_91 & io_mie_ns[1]; // @[dec_tlu_ctl.scala 3068:28]
|
|
assign io_int_timer0_int_hold = _T_103 | _T_110; // @[dec_tlu_ctl.scala 3080:32]
|
|
assign io_int_timer1_int_hold = _T_113 | _T_120; // @[dec_tlu_ctl.scala 3081:32]
|
|
assign io_internal_dbg_halt_timers = io_internal_dbg_halt_mode_f & _T_122; // @[dec_tlu_ctl.scala 3083:37]
|
|
assign io_take_ext_int_start = io_ext_int_ready & _T_134; // @[dec_tlu_ctl.scala 3093:39]
|
|
assign io_ext_int_freeze = _T_137 | io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 3094:35]
|
|
assign io_take_ext_int = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:33]
|
|
assign io_fast_int_meicpct = io_csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 3096:37]
|
|
assign io_ignore_ext_int_due_to_lsu_stall = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 3097:52]
|
|
assign io_take_ce_int = _T_144 & _T_134; // @[dec_tlu_ctl.scala 3110:25]
|
|
assign io_take_soft_int = _T_150 & _T_134; // @[dec_tlu_ctl.scala 3111:26]
|
|
assign io_take_timer_int = _T_158 & _T_134; // @[dec_tlu_ctl.scala 3112:27]
|
|
assign io_take_int_timer0_int = _T_172 & _T_134; // @[dec_tlu_ctl.scala 3113:32]
|
|
assign io_take_int_timer1_int = _T_189 & _T_134; // @[dec_tlu_ctl.scala 3114:32]
|
|
assign io_take_reset = io_reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 3115:23]
|
|
assign io_take_nmi = _T_211 & _T_215; // @[dec_tlu_ctl.scala 3116:21]
|
|
assign io_synchronous_flush_r = _T_251 | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3130:33]
|
|
assign io_tlu_flush_lower_r = _T_256 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 3131:30]
|
|
assign io_dec_tlu_flush_lower_wb = io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 3146:41]
|
|
assign io_dec_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 3148:41]
|
|
assign io_dec_tlu_flush_path_r = io_take_reset ? io_rst_vec : _T_307; // @[dec_tlu_ctl.scala 3149:41]
|
|
assign io_interrupt_valid_r_d1 = _T_320; // @[dec_tlu_ctl.scala 3154:59]
|
|
assign io_i0_exception_valid_r_d1 = _T_324; // @[dec_tlu_ctl.scala 3155:51]
|
|
assign io_exc_or_int_valid_r_d1 = _T_328; // @[dec_tlu_ctl.scala 3156:53]
|
|
assign io_exc_cause_wb = _T_332; // @[dec_tlu_ctl.scala 3157:65]
|
|
assign io_i0_valid_wb = _T_338; // @[dec_tlu_ctl.scala 3158:71]
|
|
assign io_trigger_hit_r_d1 = _T_342; // @[dec_tlu_ctl.scala 3159:63]
|
|
assign io_take_nmi_r_d1 = _T_346; // @[dec_tlu_ctl.scala 3160:73]
|
|
assign io_interrupt_valid_r = _T_221 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 3120:30]
|
|
assign io_exc_cause_r = _T_10 & _T_58; // @[dec_tlu_ctl.scala 3039:24]
|
|
assign io_i0_exception_valid_r = _T_5 & _T_6; // @[dec_tlu_ctl.scala 3031:33]
|
|
assign io_tlu_flush_path_r_d1 = _T_311; // @[dec_tlu_ctl.scala 3144:31]
|
|
assign io_exc_or_int_valid_r = _T_313 | _T_275; // @[dec_tlu_ctl.scala 3152:31]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_311 = _RAND_0[30:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_320 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_324 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_328 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_332 = _RAND_4[4:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_338 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_342 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_346 = _RAND_7[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_311 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_320 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_324 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_328 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_332 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_338 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_342 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_346 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_311 <= 31'h0;
|
|
end else if (io_tlu_flush_lower_r) begin
|
|
if (io_take_reset) begin
|
|
_T_311 <= io_rst_vec;
|
|
end else begin
|
|
_T_311 <= _T_307;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_320 <= 1'h0;
|
|
end else if (_T_319) begin
|
|
_T_320 <= io_interrupt_valid_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_324 <= 1'h0;
|
|
end else if (_T_323) begin
|
|
_T_324 <= io_i0_exception_valid_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_328 <= 1'h0;
|
|
end else if (_T_327) begin
|
|
_T_328 <= io_exc_or_int_valid_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_332 <= 5'h0;
|
|
end else if (_T_331) begin
|
|
_T_332 <= io_exc_cause_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_338 <= 1'h0;
|
|
end else if (_T_337) begin
|
|
_T_338 <= _T_334;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_342 <= 1'h0;
|
|
end else if (_T_341) begin
|
|
_T_342 <= io_i0_trigger_hit_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_346 <= 1'h0;
|
|
end else if (_T_345) begin
|
|
_T_346 <= io_take_nmi;
|
|
end
|
|
end
|
|
endmodule
|
|
module perf_mux_and_flops(
|
|
input reset,
|
|
output io_mhpmc_inc_r_0,
|
|
output io_mhpmc_inc_r_1,
|
|
output io_mhpmc_inc_r_2,
|
|
output io_mhpmc_inc_r_3,
|
|
input [6:0] io_mcountinhibit,
|
|
input [9:0] io_mhpme_vec_0,
|
|
input [9:0] io_mhpme_vec_1,
|
|
input [9:0] io_mhpme_vec_2,
|
|
input [9:0] io_mhpme_vec_3,
|
|
input io_ifu_pmu_ic_hit,
|
|
input io_ifu_pmu_ic_miss,
|
|
input io_tlu_i0_commit_cmt,
|
|
input io_illegal_r,
|
|
input io_exu_pmu_i0_pc4,
|
|
input io_ifu_pmu_instr_aligned,
|
|
input io_dec_pmu_instr_decoded,
|
|
input [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
input io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
input io_dec_tlu_packet_r_pmu_divide,
|
|
input io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
input io_exu_pmu_i0_br_misp,
|
|
input io_dec_pmu_decode_stall,
|
|
input io_exu_pmu_i0_br_ataken,
|
|
input io_ifu_pmu_fetch_stall,
|
|
input io_dec_pmu_postsync_stall,
|
|
input io_dec_pmu_presync_stall,
|
|
input io_lsu_store_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_dma_iccm_stall_any,
|
|
input io_i0_exception_valid_r,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input io_dma_pmu_any_read,
|
|
input io_dma_pmu_any_write,
|
|
input io_dma_pmu_dccm_read,
|
|
input io_dma_pmu_dccm_write,
|
|
input io_lsu_pmu_load_external_r,
|
|
input io_lsu_pmu_store_external_r,
|
|
output [1:0] io_mstatus,
|
|
input [5:0] io_mie,
|
|
input io_ifu_pmu_bus_trxn,
|
|
input io_lsu_pmu_bus_trxn,
|
|
input io_lsu_pmu_bus_misaligned,
|
|
input io_ifu_pmu_bus_error,
|
|
input io_lsu_pmu_bus_error,
|
|
input io_ifu_pmu_bus_busy,
|
|
input io_lsu_pmu_bus_busy,
|
|
input io_i0_trigger_hit_r,
|
|
input io_lsu_exc_valid_r,
|
|
input io_take_timer_int,
|
|
input io_take_int_timer0_int,
|
|
input io_take_int_timer1_int,
|
|
input io_take_ext_int,
|
|
input io_tlu_flush_lower_r,
|
|
input io_dec_tlu_br0_error_r,
|
|
input io_rfpc_i0_r,
|
|
input io_dec_tlu_br0_start_error_r,
|
|
output io_mcyclel_cout_f,
|
|
output io_minstret_enable_f,
|
|
output io_minstretl_cout_f,
|
|
output [3:0] io_meicidpl,
|
|
output io_icache_rd_valid_f,
|
|
output io_icache_wr_valid_f,
|
|
output io_mhpmc_inc_r_d1_0,
|
|
output io_mhpmc_inc_r_d1_1,
|
|
output io_mhpmc_inc_r_d1_2,
|
|
output io_mhpmc_inc_r_d1_3,
|
|
output io_perfcnt_halted_d1,
|
|
output io_mdseac_locked_f,
|
|
output io_lsu_single_ecc_error_r_d1,
|
|
output io_lsu_i0_exc_r_d1,
|
|
output io_take_ext_int_start_d1,
|
|
output io_take_ext_int_start_d2,
|
|
output io_take_ext_int_start_d3,
|
|
output io_ext_int_freeze_d1,
|
|
output [5:0] io_mip,
|
|
input io_mdseac_locked_ns,
|
|
input io_lsu_single_ecc_error_r,
|
|
input io_lsu_i0_exc_r,
|
|
input io_take_ext_int_start,
|
|
input io_ext_int_freeze,
|
|
input [5:0] io_mip_ns,
|
|
input io_mcyclel_cout,
|
|
input io_wr_mcycleh_r,
|
|
input io_mcyclel_cout_in,
|
|
input io_minstret_enable,
|
|
input io_minstretl_cout_ns,
|
|
input [3:0] io_meicidpl_ns,
|
|
input io_icache_rd_valid,
|
|
input io_icache_wr_valid,
|
|
input io_perfcnt_halted,
|
|
input [1:0] io_mstatus_ns,
|
|
input io_free_l2clk
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire [3:0] _T_1 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1; // @[dec_tlu_ctl.scala 2795:66]
|
|
wire _T_3 = ~io_mcountinhibit[3]; // @[dec_tlu_ctl.scala 2797:40]
|
|
wire _T_4 = io_mhpme_vec_0 == 10'h1; // @[dec_tlu_ctl.scala 2798:42]
|
|
wire _T_6 = io_mhpme_vec_0 == 10'h2; // @[dec_tlu_ctl.scala 2799:42]
|
|
wire _T_8 = io_mhpme_vec_0 == 10'h3; // @[dec_tlu_ctl.scala 2800:42]
|
|
wire _T_10 = io_mhpme_vec_0 == 10'h4; // @[dec_tlu_ctl.scala 2801:42]
|
|
wire _T_12 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2801:104]
|
|
wire _T_13 = io_tlu_i0_commit_cmt & _T_12; // @[dec_tlu_ctl.scala 2801:102]
|
|
wire _T_14 = io_mhpme_vec_0 == 10'h5; // @[dec_tlu_ctl.scala 2802:42]
|
|
wire _T_16 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2802:104]
|
|
wire _T_17 = io_tlu_i0_commit_cmt & _T_16; // @[dec_tlu_ctl.scala 2802:102]
|
|
wire _T_19 = _T_17 & _T_12; // @[dec_tlu_ctl.scala 2802:123]
|
|
wire _T_20 = io_mhpme_vec_0 == 10'h6; // @[dec_tlu_ctl.scala 2803:42]
|
|
wire _T_22 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2803:102]
|
|
wire _T_24 = _T_22 & _T_12; // @[dec_tlu_ctl.scala 2803:123]
|
|
wire _T_25 = io_mhpme_vec_0 == 10'h7; // @[dec_tlu_ctl.scala 2805:42]
|
|
wire _T_27 = io_mhpme_vec_0 == 10'h8; // @[dec_tlu_ctl.scala 2806:42]
|
|
wire _T_29 = io_mhpme_vec_0 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42]
|
|
wire _T_31 = io_mhpme_vec_0 == 10'h9; // @[dec_tlu_ctl.scala 2808:42]
|
|
wire _T_33 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2808:99]
|
|
wire _T_34 = io_mhpme_vec_0 == 10'ha; // @[dec_tlu_ctl.scala 2809:42]
|
|
wire _T_36 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2809:113]
|
|
wire _T_38 = _T_36 & _T_12; // @[dec_tlu_ctl.scala 2809:136]
|
|
wire _T_39 = io_mhpme_vec_0 == 10'hb; // @[dec_tlu_ctl.scala 2810:42]
|
|
wire _T_41 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2810:99]
|
|
wire _T_42 = io_mhpme_vec_0 == 10'hc; // @[dec_tlu_ctl.scala 2811:42]
|
|
wire _T_44 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2811:99]
|
|
wire _T_45 = io_mhpme_vec_0 == 10'hd; // @[dec_tlu_ctl.scala 2812:42]
|
|
wire _T_48 = _T_41 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2812:108]
|
|
wire _T_49 = io_mhpme_vec_0 == 10'he; // @[dec_tlu_ctl.scala 2813:42]
|
|
wire _T_53 = _T_44 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2813:109]
|
|
wire _T_54 = io_mhpme_vec_0 == 10'hf; // @[dec_tlu_ctl.scala 2815:42]
|
|
wire _T_56 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2815:97]
|
|
wire _T_57 = io_mhpme_vec_0 == 10'h10; // @[dec_tlu_ctl.scala 2816:42]
|
|
wire _T_59 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2816:97]
|
|
wire _T_60 = io_mhpme_vec_0 == 10'h12; // @[dec_tlu_ctl.scala 2817:42]
|
|
wire _T_62 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2817:97]
|
|
wire _T_63 = io_mhpme_vec_0 == 10'h11; // @[dec_tlu_ctl.scala 2818:42]
|
|
wire _T_65 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2818:97]
|
|
wire _T_66 = io_mhpme_vec_0 == 10'h13; // @[dec_tlu_ctl.scala 2819:42]
|
|
wire _T_68 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2819:97]
|
|
wire _T_69 = io_mhpme_vec_0 == 10'h14; // @[dec_tlu_ctl.scala 2820:42]
|
|
wire _T_71 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2820:97]
|
|
wire _T_72 = io_mhpme_vec_0 == 10'h15; // @[dec_tlu_ctl.scala 2821:42]
|
|
wire _T_74 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2821:97]
|
|
wire _T_75 = io_mhpme_vec_0 == 10'h16; // @[dec_tlu_ctl.scala 2822:42]
|
|
wire _T_77 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2822:97]
|
|
wire _T_78 = io_mhpme_vec_0 == 10'h17; // @[dec_tlu_ctl.scala 2823:42]
|
|
wire _T_80 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2823:97]
|
|
wire _T_81 = io_mhpme_vec_0 == 10'h18; // @[dec_tlu_ctl.scala 2824:42]
|
|
wire _T_83 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2824:97]
|
|
wire _T_84 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2824:130]
|
|
wire _T_85 = _T_83 | _T_84; // @[dec_tlu_ctl.scala 2824:109]
|
|
wire _T_86 = io_mhpme_vec_0 == 10'h19; // @[dec_tlu_ctl.scala 2826:42]
|
|
wire _T_88 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2826:103]
|
|
wire _T_90 = _T_88 & _T_12; // @[dec_tlu_ctl.scala 2826:126]
|
|
wire _T_91 = io_mhpme_vec_0 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42]
|
|
wire _T_93 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2827:105]
|
|
wire _T_95 = _T_93 & _T_12; // @[dec_tlu_ctl.scala 2827:128]
|
|
wire _T_96 = io_mhpme_vec_0 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42]
|
|
wire _T_98 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2828:118]
|
|
wire _T_100 = _T_98 & _T_12; // @[dec_tlu_ctl.scala 2828:141]
|
|
wire _T_101 = io_mhpme_vec_0 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42]
|
|
wire _T_105 = io_mhpme_vec_0 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42]
|
|
wire _T_107 = io_mhpme_vec_0 == 10'h20; // @[dec_tlu_ctl.scala 2832:42]
|
|
wire _T_109 = io_mhpme_vec_0 == 10'h22; // @[dec_tlu_ctl.scala 2833:42]
|
|
wire _T_111 = io_mhpme_vec_0 == 10'h23; // @[dec_tlu_ctl.scala 2834:42]
|
|
wire _T_113 = io_mhpme_vec_0 == 10'h24; // @[dec_tlu_ctl.scala 2835:42]
|
|
wire _T_115 = io_mhpme_vec_0 == 10'h25; // @[dec_tlu_ctl.scala 2836:42]
|
|
wire _T_117 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2836:106]
|
|
wire _T_118 = _T_117 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2836:128]
|
|
wire _T_119 = io_mhpme_vec_0 == 10'h26; // @[dec_tlu_ctl.scala 2837:42]
|
|
wire _T_121 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2837:100]
|
|
wire _T_122 = _T_121 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2837:125]
|
|
wire _T_123 = io_mhpme_vec_0 == 10'h27; // @[dec_tlu_ctl.scala 2838:42]
|
|
wire _T_125 = io_mhpme_vec_0 == 10'h28; // @[dec_tlu_ctl.scala 2839:42]
|
|
wire _T_127 = io_mhpme_vec_0 == 10'h29; // @[dec_tlu_ctl.scala 2840:42]
|
|
wire _T_129 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2840:105]
|
|
wire _T_130 = _T_129 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2840:137]
|
|
wire _T_131 = io_mhpme_vec_0 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42]
|
|
wire _T_133 = io_mhpme_vec_0 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42]
|
|
wire _T_135 = io_mhpme_vec_0 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42]
|
|
wire _T_137 = io_mhpme_vec_0 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42]
|
|
wire _T_139 = io_mhpme_vec_0 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42]
|
|
wire _T_141 = io_mhpme_vec_0 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42]
|
|
wire _T_143 = io_mhpme_vec_0 == 10'h30; // @[dec_tlu_ctl.scala 2848:42]
|
|
wire _T_145 = io_mhpme_vec_0 == 10'h31; // @[dec_tlu_ctl.scala 2849:42]
|
|
wire _T_149 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2849:81]
|
|
wire _T_150 = io_mhpme_vec_0 == 10'h32; // @[dec_tlu_ctl.scala 2850:42]
|
|
wire [5:0] _T_157 = io_mip & io_mie; // @[dec_tlu_ctl.scala 2850:121]
|
|
wire _T_158 = |_T_157; // @[dec_tlu_ctl.scala 2850:136]
|
|
wire _T_159 = _T_149 & _T_158; // @[dec_tlu_ctl.scala 2850:106]
|
|
wire _T_160 = io_mhpme_vec_0 == 10'h36; // @[dec_tlu_ctl.scala 2851:42]
|
|
wire _T_162 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2851:99]
|
|
wire _T_163 = io_mhpme_vec_0 == 10'h37; // @[dec_tlu_ctl.scala 2852:42]
|
|
wire _T_165 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2852:102]
|
|
wire _T_167 = _T_165 & _T_12; // @[dec_tlu_ctl.scala 2852:131]
|
|
wire _T_168 = io_mhpme_vec_0 == 10'h38; // @[dec_tlu_ctl.scala 2853:42]
|
|
wire _T_170 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2853:102]
|
|
wire _T_172 = _T_170 & _T_12; // @[dec_tlu_ctl.scala 2853:132]
|
|
wire _T_173 = io_mhpme_vec_0 == 10'h200; // @[dec_tlu_ctl.scala 2855:42]
|
|
wire _T_175 = io_mhpme_vec_0 == 10'h201; // @[dec_tlu_ctl.scala 2856:42]
|
|
wire _T_177 = io_mhpme_vec_0 == 10'h202; // @[dec_tlu_ctl.scala 2857:42]
|
|
wire _T_179 = io_mhpme_vec_0 == 10'h203; // @[dec_tlu_ctl.scala 2858:42]
|
|
wire _T_181 = io_mhpme_vec_0 == 10'h204; // @[dec_tlu_ctl.scala 2859:42]
|
|
wire _T_184 = _T_6 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_185 = _T_8 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_186 = _T_10 & _T_13; // @[Mux.scala 27:72]
|
|
wire _T_187 = _T_14 & _T_19; // @[Mux.scala 27:72]
|
|
wire _T_188 = _T_20 & _T_24; // @[Mux.scala 27:72]
|
|
wire _T_189 = _T_25 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_190 = _T_27 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_191 = _T_29 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_192 = _T_31 & _T_33; // @[Mux.scala 27:72]
|
|
wire _T_193 = _T_34 & _T_38; // @[Mux.scala 27:72]
|
|
wire _T_194 = _T_39 & _T_41; // @[Mux.scala 27:72]
|
|
wire _T_195 = _T_42 & _T_44; // @[Mux.scala 27:72]
|
|
wire _T_196 = _T_45 & _T_48; // @[Mux.scala 27:72]
|
|
wire _T_197 = _T_49 & _T_53; // @[Mux.scala 27:72]
|
|
wire _T_198 = _T_54 & _T_56; // @[Mux.scala 27:72]
|
|
wire _T_199 = _T_57 & _T_59; // @[Mux.scala 27:72]
|
|
wire _T_200 = _T_60 & _T_62; // @[Mux.scala 27:72]
|
|
wire _T_201 = _T_63 & _T_65; // @[Mux.scala 27:72]
|
|
wire _T_202 = _T_66 & _T_68; // @[Mux.scala 27:72]
|
|
wire _T_203 = _T_69 & _T_71; // @[Mux.scala 27:72]
|
|
wire _T_204 = _T_72 & _T_74; // @[Mux.scala 27:72]
|
|
wire _T_205 = _T_75 & _T_77; // @[Mux.scala 27:72]
|
|
wire _T_206 = _T_78 & _T_80; // @[Mux.scala 27:72]
|
|
wire _T_207 = _T_81 & _T_85; // @[Mux.scala 27:72]
|
|
wire _T_208 = _T_86 & _T_90; // @[Mux.scala 27:72]
|
|
wire _T_209 = _T_91 & _T_95; // @[Mux.scala 27:72]
|
|
wire _T_210 = _T_96 & _T_100; // @[Mux.scala 27:72]
|
|
wire _T_211 = _T_101 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_213 = _T_105 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_214 = _T_107 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_215 = _T_109 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_216 = _T_111 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_217 = _T_113 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_218 = _T_115 & _T_118; // @[Mux.scala 27:72]
|
|
wire _T_219 = _T_119 & _T_122; // @[Mux.scala 27:72]
|
|
wire _T_220 = _T_123 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_221 = _T_125 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_222 = _T_127 & _T_130; // @[Mux.scala 27:72]
|
|
wire _T_223 = _T_131 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_224 = _T_133 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_225 = _T_135 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_226 = _T_137 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_227 = _T_139 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_228 = _T_141 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_229 = _T_143 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_230 = _T_145 & _T_149; // @[Mux.scala 27:72]
|
|
wire _T_231 = _T_150 & _T_159; // @[Mux.scala 27:72]
|
|
wire _T_232 = _T_160 & _T_162; // @[Mux.scala 27:72]
|
|
wire _T_233 = _T_163 & _T_167; // @[Mux.scala 27:72]
|
|
wire _T_234 = _T_168 & _T_172; // @[Mux.scala 27:72]
|
|
wire _T_235 = _T_173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_236 = _T_175 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_237 = _T_177 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_238 = _T_179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_239 = _T_181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_240 = _T_4 | _T_184; // @[Mux.scala 27:72]
|
|
wire _T_241 = _T_240 | _T_185; // @[Mux.scala 27:72]
|
|
wire _T_242 = _T_241 | _T_186; // @[Mux.scala 27:72]
|
|
wire _T_243 = _T_242 | _T_187; // @[Mux.scala 27:72]
|
|
wire _T_244 = _T_243 | _T_188; // @[Mux.scala 27:72]
|
|
wire _T_245 = _T_244 | _T_189; // @[Mux.scala 27:72]
|
|
wire _T_246 = _T_245 | _T_190; // @[Mux.scala 27:72]
|
|
wire _T_247 = _T_246 | _T_191; // @[Mux.scala 27:72]
|
|
wire _T_248 = _T_247 | _T_192; // @[Mux.scala 27:72]
|
|
wire _T_249 = _T_248 | _T_193; // @[Mux.scala 27:72]
|
|
wire _T_250 = _T_249 | _T_194; // @[Mux.scala 27:72]
|
|
wire _T_251 = _T_250 | _T_195; // @[Mux.scala 27:72]
|
|
wire _T_252 = _T_251 | _T_196; // @[Mux.scala 27:72]
|
|
wire _T_253 = _T_252 | _T_197; // @[Mux.scala 27:72]
|
|
wire _T_254 = _T_253 | _T_198; // @[Mux.scala 27:72]
|
|
wire _T_255 = _T_254 | _T_199; // @[Mux.scala 27:72]
|
|
wire _T_256 = _T_255 | _T_200; // @[Mux.scala 27:72]
|
|
wire _T_257 = _T_256 | _T_201; // @[Mux.scala 27:72]
|
|
wire _T_258 = _T_257 | _T_202; // @[Mux.scala 27:72]
|
|
wire _T_259 = _T_258 | _T_203; // @[Mux.scala 27:72]
|
|
wire _T_260 = _T_259 | _T_204; // @[Mux.scala 27:72]
|
|
wire _T_261 = _T_260 | _T_205; // @[Mux.scala 27:72]
|
|
wire _T_262 = _T_261 | _T_206; // @[Mux.scala 27:72]
|
|
wire _T_263 = _T_262 | _T_207; // @[Mux.scala 27:72]
|
|
wire _T_264 = _T_263 | _T_208; // @[Mux.scala 27:72]
|
|
wire _T_265 = _T_264 | _T_209; // @[Mux.scala 27:72]
|
|
wire _T_266 = _T_265 | _T_210; // @[Mux.scala 27:72]
|
|
wire _T_267 = _T_266 | _T_211; // @[Mux.scala 27:72]
|
|
wire _T_268 = _T_267 | _T_191; // @[Mux.scala 27:72]
|
|
wire _T_269 = _T_268 | _T_213; // @[Mux.scala 27:72]
|
|
wire _T_270 = _T_269 | _T_214; // @[Mux.scala 27:72]
|
|
wire _T_271 = _T_270 | _T_215; // @[Mux.scala 27:72]
|
|
wire _T_272 = _T_271 | _T_216; // @[Mux.scala 27:72]
|
|
wire _T_273 = _T_272 | _T_217; // @[Mux.scala 27:72]
|
|
wire _T_274 = _T_273 | _T_218; // @[Mux.scala 27:72]
|
|
wire _T_275 = _T_274 | _T_219; // @[Mux.scala 27:72]
|
|
wire _T_276 = _T_275 | _T_220; // @[Mux.scala 27:72]
|
|
wire _T_277 = _T_276 | _T_221; // @[Mux.scala 27:72]
|
|
wire _T_278 = _T_277 | _T_222; // @[Mux.scala 27:72]
|
|
wire _T_279 = _T_278 | _T_223; // @[Mux.scala 27:72]
|
|
wire _T_280 = _T_279 | _T_224; // @[Mux.scala 27:72]
|
|
wire _T_281 = _T_280 | _T_225; // @[Mux.scala 27:72]
|
|
wire _T_282 = _T_281 | _T_226; // @[Mux.scala 27:72]
|
|
wire _T_283 = _T_282 | _T_227; // @[Mux.scala 27:72]
|
|
wire _T_284 = _T_283 | _T_228; // @[Mux.scala 27:72]
|
|
wire _T_285 = _T_284 | _T_229; // @[Mux.scala 27:72]
|
|
wire _T_286 = _T_285 | _T_230; // @[Mux.scala 27:72]
|
|
wire _T_287 = _T_286 | _T_231; // @[Mux.scala 27:72]
|
|
wire _T_288 = _T_287 | _T_232; // @[Mux.scala 27:72]
|
|
wire _T_289 = _T_288 | _T_233; // @[Mux.scala 27:72]
|
|
wire _T_290 = _T_289 | _T_234; // @[Mux.scala 27:72]
|
|
wire _T_291 = _T_290 | _T_235; // @[Mux.scala 27:72]
|
|
wire _T_292 = _T_291 | _T_236; // @[Mux.scala 27:72]
|
|
wire _T_293 = _T_292 | _T_237; // @[Mux.scala 27:72]
|
|
wire _T_294 = _T_293 | _T_238; // @[Mux.scala 27:72]
|
|
wire _T_295 = _T_294 | _T_239; // @[Mux.scala 27:72]
|
|
wire _T_299 = ~io_mcountinhibit[4]; // @[dec_tlu_ctl.scala 2797:40]
|
|
wire _T_300 = io_mhpme_vec_1 == 10'h1; // @[dec_tlu_ctl.scala 2798:42]
|
|
wire _T_302 = io_mhpme_vec_1 == 10'h2; // @[dec_tlu_ctl.scala 2799:42]
|
|
wire _T_304 = io_mhpme_vec_1 == 10'h3; // @[dec_tlu_ctl.scala 2800:42]
|
|
wire _T_306 = io_mhpme_vec_1 == 10'h4; // @[dec_tlu_ctl.scala 2801:42]
|
|
wire _T_310 = io_mhpme_vec_1 == 10'h5; // @[dec_tlu_ctl.scala 2802:42]
|
|
wire _T_316 = io_mhpme_vec_1 == 10'h6; // @[dec_tlu_ctl.scala 2803:42]
|
|
wire _T_321 = io_mhpme_vec_1 == 10'h7; // @[dec_tlu_ctl.scala 2805:42]
|
|
wire _T_323 = io_mhpme_vec_1 == 10'h8; // @[dec_tlu_ctl.scala 2806:42]
|
|
wire _T_325 = io_mhpme_vec_1 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42]
|
|
wire _T_327 = io_mhpme_vec_1 == 10'h9; // @[dec_tlu_ctl.scala 2808:42]
|
|
wire _T_330 = io_mhpme_vec_1 == 10'ha; // @[dec_tlu_ctl.scala 2809:42]
|
|
wire _T_335 = io_mhpme_vec_1 == 10'hb; // @[dec_tlu_ctl.scala 2810:42]
|
|
wire _T_338 = io_mhpme_vec_1 == 10'hc; // @[dec_tlu_ctl.scala 2811:42]
|
|
wire _T_341 = io_mhpme_vec_1 == 10'hd; // @[dec_tlu_ctl.scala 2812:42]
|
|
wire _T_345 = io_mhpme_vec_1 == 10'he; // @[dec_tlu_ctl.scala 2813:42]
|
|
wire _T_350 = io_mhpme_vec_1 == 10'hf; // @[dec_tlu_ctl.scala 2815:42]
|
|
wire _T_353 = io_mhpme_vec_1 == 10'h10; // @[dec_tlu_ctl.scala 2816:42]
|
|
wire _T_356 = io_mhpme_vec_1 == 10'h12; // @[dec_tlu_ctl.scala 2817:42]
|
|
wire _T_359 = io_mhpme_vec_1 == 10'h11; // @[dec_tlu_ctl.scala 2818:42]
|
|
wire _T_362 = io_mhpme_vec_1 == 10'h13; // @[dec_tlu_ctl.scala 2819:42]
|
|
wire _T_365 = io_mhpme_vec_1 == 10'h14; // @[dec_tlu_ctl.scala 2820:42]
|
|
wire _T_368 = io_mhpme_vec_1 == 10'h15; // @[dec_tlu_ctl.scala 2821:42]
|
|
wire _T_371 = io_mhpme_vec_1 == 10'h16; // @[dec_tlu_ctl.scala 2822:42]
|
|
wire _T_374 = io_mhpme_vec_1 == 10'h17; // @[dec_tlu_ctl.scala 2823:42]
|
|
wire _T_377 = io_mhpme_vec_1 == 10'h18; // @[dec_tlu_ctl.scala 2824:42]
|
|
wire _T_382 = io_mhpme_vec_1 == 10'h19; // @[dec_tlu_ctl.scala 2826:42]
|
|
wire _T_387 = io_mhpme_vec_1 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42]
|
|
wire _T_392 = io_mhpme_vec_1 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42]
|
|
wire _T_397 = io_mhpme_vec_1 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42]
|
|
wire _T_401 = io_mhpme_vec_1 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42]
|
|
wire _T_403 = io_mhpme_vec_1 == 10'h20; // @[dec_tlu_ctl.scala 2832:42]
|
|
wire _T_405 = io_mhpme_vec_1 == 10'h22; // @[dec_tlu_ctl.scala 2833:42]
|
|
wire _T_407 = io_mhpme_vec_1 == 10'h23; // @[dec_tlu_ctl.scala 2834:42]
|
|
wire _T_409 = io_mhpme_vec_1 == 10'h24; // @[dec_tlu_ctl.scala 2835:42]
|
|
wire _T_411 = io_mhpme_vec_1 == 10'h25; // @[dec_tlu_ctl.scala 2836:42]
|
|
wire _T_415 = io_mhpme_vec_1 == 10'h26; // @[dec_tlu_ctl.scala 2837:42]
|
|
wire _T_419 = io_mhpme_vec_1 == 10'h27; // @[dec_tlu_ctl.scala 2838:42]
|
|
wire _T_421 = io_mhpme_vec_1 == 10'h28; // @[dec_tlu_ctl.scala 2839:42]
|
|
wire _T_423 = io_mhpme_vec_1 == 10'h29; // @[dec_tlu_ctl.scala 2840:42]
|
|
wire _T_427 = io_mhpme_vec_1 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42]
|
|
wire _T_429 = io_mhpme_vec_1 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42]
|
|
wire _T_431 = io_mhpme_vec_1 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42]
|
|
wire _T_433 = io_mhpme_vec_1 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42]
|
|
wire _T_435 = io_mhpme_vec_1 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42]
|
|
wire _T_437 = io_mhpme_vec_1 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42]
|
|
wire _T_439 = io_mhpme_vec_1 == 10'h30; // @[dec_tlu_ctl.scala 2848:42]
|
|
wire _T_441 = io_mhpme_vec_1 == 10'h31; // @[dec_tlu_ctl.scala 2849:42]
|
|
wire _T_446 = io_mhpme_vec_1 == 10'h32; // @[dec_tlu_ctl.scala 2850:42]
|
|
wire _T_456 = io_mhpme_vec_1 == 10'h36; // @[dec_tlu_ctl.scala 2851:42]
|
|
wire _T_459 = io_mhpme_vec_1 == 10'h37; // @[dec_tlu_ctl.scala 2852:42]
|
|
wire _T_464 = io_mhpme_vec_1 == 10'h38; // @[dec_tlu_ctl.scala 2853:42]
|
|
wire _T_469 = io_mhpme_vec_1 == 10'h200; // @[dec_tlu_ctl.scala 2855:42]
|
|
wire _T_471 = io_mhpme_vec_1 == 10'h201; // @[dec_tlu_ctl.scala 2856:42]
|
|
wire _T_473 = io_mhpme_vec_1 == 10'h202; // @[dec_tlu_ctl.scala 2857:42]
|
|
wire _T_475 = io_mhpme_vec_1 == 10'h203; // @[dec_tlu_ctl.scala 2858:42]
|
|
wire _T_477 = io_mhpme_vec_1 == 10'h204; // @[dec_tlu_ctl.scala 2859:42]
|
|
wire _T_480 = _T_302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_481 = _T_304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_482 = _T_306 & _T_13; // @[Mux.scala 27:72]
|
|
wire _T_483 = _T_310 & _T_19; // @[Mux.scala 27:72]
|
|
wire _T_484 = _T_316 & _T_24; // @[Mux.scala 27:72]
|
|
wire _T_485 = _T_321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_486 = _T_323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_487 = _T_325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_488 = _T_327 & _T_33; // @[Mux.scala 27:72]
|
|
wire _T_489 = _T_330 & _T_38; // @[Mux.scala 27:72]
|
|
wire _T_490 = _T_335 & _T_41; // @[Mux.scala 27:72]
|
|
wire _T_491 = _T_338 & _T_44; // @[Mux.scala 27:72]
|
|
wire _T_492 = _T_341 & _T_48; // @[Mux.scala 27:72]
|
|
wire _T_493 = _T_345 & _T_53; // @[Mux.scala 27:72]
|
|
wire _T_494 = _T_350 & _T_56; // @[Mux.scala 27:72]
|
|
wire _T_495 = _T_353 & _T_59; // @[Mux.scala 27:72]
|
|
wire _T_496 = _T_356 & _T_62; // @[Mux.scala 27:72]
|
|
wire _T_497 = _T_359 & _T_65; // @[Mux.scala 27:72]
|
|
wire _T_498 = _T_362 & _T_68; // @[Mux.scala 27:72]
|
|
wire _T_499 = _T_365 & _T_71; // @[Mux.scala 27:72]
|
|
wire _T_500 = _T_368 & _T_74; // @[Mux.scala 27:72]
|
|
wire _T_501 = _T_371 & _T_77; // @[Mux.scala 27:72]
|
|
wire _T_502 = _T_374 & _T_80; // @[Mux.scala 27:72]
|
|
wire _T_503 = _T_377 & _T_85; // @[Mux.scala 27:72]
|
|
wire _T_504 = _T_382 & _T_90; // @[Mux.scala 27:72]
|
|
wire _T_505 = _T_387 & _T_95; // @[Mux.scala 27:72]
|
|
wire _T_506 = _T_392 & _T_100; // @[Mux.scala 27:72]
|
|
wire _T_507 = _T_397 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_509 = _T_401 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_510 = _T_403 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_511 = _T_405 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_512 = _T_407 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_513 = _T_409 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_514 = _T_411 & _T_118; // @[Mux.scala 27:72]
|
|
wire _T_515 = _T_415 & _T_122; // @[Mux.scala 27:72]
|
|
wire _T_516 = _T_419 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_517 = _T_421 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_518 = _T_423 & _T_130; // @[Mux.scala 27:72]
|
|
wire _T_519 = _T_427 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_520 = _T_429 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_521 = _T_431 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_522 = _T_433 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_523 = _T_435 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_524 = _T_437 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_525 = _T_439 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_526 = _T_441 & _T_149; // @[Mux.scala 27:72]
|
|
wire _T_527 = _T_446 & _T_159; // @[Mux.scala 27:72]
|
|
wire _T_528 = _T_456 & _T_162; // @[Mux.scala 27:72]
|
|
wire _T_529 = _T_459 & _T_167; // @[Mux.scala 27:72]
|
|
wire _T_530 = _T_464 & _T_172; // @[Mux.scala 27:72]
|
|
wire _T_531 = _T_469 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_532 = _T_471 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_533 = _T_473 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_534 = _T_475 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_535 = _T_477 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_536 = _T_300 | _T_480; // @[Mux.scala 27:72]
|
|
wire _T_537 = _T_536 | _T_481; // @[Mux.scala 27:72]
|
|
wire _T_538 = _T_537 | _T_482; // @[Mux.scala 27:72]
|
|
wire _T_539 = _T_538 | _T_483; // @[Mux.scala 27:72]
|
|
wire _T_540 = _T_539 | _T_484; // @[Mux.scala 27:72]
|
|
wire _T_541 = _T_540 | _T_485; // @[Mux.scala 27:72]
|
|
wire _T_542 = _T_541 | _T_486; // @[Mux.scala 27:72]
|
|
wire _T_543 = _T_542 | _T_487; // @[Mux.scala 27:72]
|
|
wire _T_544 = _T_543 | _T_488; // @[Mux.scala 27:72]
|
|
wire _T_545 = _T_544 | _T_489; // @[Mux.scala 27:72]
|
|
wire _T_546 = _T_545 | _T_490; // @[Mux.scala 27:72]
|
|
wire _T_547 = _T_546 | _T_491; // @[Mux.scala 27:72]
|
|
wire _T_548 = _T_547 | _T_492; // @[Mux.scala 27:72]
|
|
wire _T_549 = _T_548 | _T_493; // @[Mux.scala 27:72]
|
|
wire _T_550 = _T_549 | _T_494; // @[Mux.scala 27:72]
|
|
wire _T_551 = _T_550 | _T_495; // @[Mux.scala 27:72]
|
|
wire _T_552 = _T_551 | _T_496; // @[Mux.scala 27:72]
|
|
wire _T_553 = _T_552 | _T_497; // @[Mux.scala 27:72]
|
|
wire _T_554 = _T_553 | _T_498; // @[Mux.scala 27:72]
|
|
wire _T_555 = _T_554 | _T_499; // @[Mux.scala 27:72]
|
|
wire _T_556 = _T_555 | _T_500; // @[Mux.scala 27:72]
|
|
wire _T_557 = _T_556 | _T_501; // @[Mux.scala 27:72]
|
|
wire _T_558 = _T_557 | _T_502; // @[Mux.scala 27:72]
|
|
wire _T_559 = _T_558 | _T_503; // @[Mux.scala 27:72]
|
|
wire _T_560 = _T_559 | _T_504; // @[Mux.scala 27:72]
|
|
wire _T_561 = _T_560 | _T_505; // @[Mux.scala 27:72]
|
|
wire _T_562 = _T_561 | _T_506; // @[Mux.scala 27:72]
|
|
wire _T_563 = _T_562 | _T_507; // @[Mux.scala 27:72]
|
|
wire _T_564 = _T_563 | _T_487; // @[Mux.scala 27:72]
|
|
wire _T_565 = _T_564 | _T_509; // @[Mux.scala 27:72]
|
|
wire _T_566 = _T_565 | _T_510; // @[Mux.scala 27:72]
|
|
wire _T_567 = _T_566 | _T_511; // @[Mux.scala 27:72]
|
|
wire _T_568 = _T_567 | _T_512; // @[Mux.scala 27:72]
|
|
wire _T_569 = _T_568 | _T_513; // @[Mux.scala 27:72]
|
|
wire _T_570 = _T_569 | _T_514; // @[Mux.scala 27:72]
|
|
wire _T_571 = _T_570 | _T_515; // @[Mux.scala 27:72]
|
|
wire _T_572 = _T_571 | _T_516; // @[Mux.scala 27:72]
|
|
wire _T_573 = _T_572 | _T_517; // @[Mux.scala 27:72]
|
|
wire _T_574 = _T_573 | _T_518; // @[Mux.scala 27:72]
|
|
wire _T_575 = _T_574 | _T_519; // @[Mux.scala 27:72]
|
|
wire _T_576 = _T_575 | _T_520; // @[Mux.scala 27:72]
|
|
wire _T_577 = _T_576 | _T_521; // @[Mux.scala 27:72]
|
|
wire _T_578 = _T_577 | _T_522; // @[Mux.scala 27:72]
|
|
wire _T_579 = _T_578 | _T_523; // @[Mux.scala 27:72]
|
|
wire _T_580 = _T_579 | _T_524; // @[Mux.scala 27:72]
|
|
wire _T_581 = _T_580 | _T_525; // @[Mux.scala 27:72]
|
|
wire _T_582 = _T_581 | _T_526; // @[Mux.scala 27:72]
|
|
wire _T_583 = _T_582 | _T_527; // @[Mux.scala 27:72]
|
|
wire _T_584 = _T_583 | _T_528; // @[Mux.scala 27:72]
|
|
wire _T_585 = _T_584 | _T_529; // @[Mux.scala 27:72]
|
|
wire _T_586 = _T_585 | _T_530; // @[Mux.scala 27:72]
|
|
wire _T_587 = _T_586 | _T_531; // @[Mux.scala 27:72]
|
|
wire _T_588 = _T_587 | _T_532; // @[Mux.scala 27:72]
|
|
wire _T_589 = _T_588 | _T_533; // @[Mux.scala 27:72]
|
|
wire _T_590 = _T_589 | _T_534; // @[Mux.scala 27:72]
|
|
wire _T_591 = _T_590 | _T_535; // @[Mux.scala 27:72]
|
|
wire _T_595 = ~io_mcountinhibit[5]; // @[dec_tlu_ctl.scala 2797:40]
|
|
wire _T_596 = io_mhpme_vec_2 == 10'h1; // @[dec_tlu_ctl.scala 2798:42]
|
|
wire _T_598 = io_mhpme_vec_2 == 10'h2; // @[dec_tlu_ctl.scala 2799:42]
|
|
wire _T_600 = io_mhpme_vec_2 == 10'h3; // @[dec_tlu_ctl.scala 2800:42]
|
|
wire _T_602 = io_mhpme_vec_2 == 10'h4; // @[dec_tlu_ctl.scala 2801:42]
|
|
wire _T_606 = io_mhpme_vec_2 == 10'h5; // @[dec_tlu_ctl.scala 2802:42]
|
|
wire _T_612 = io_mhpme_vec_2 == 10'h6; // @[dec_tlu_ctl.scala 2803:42]
|
|
wire _T_617 = io_mhpme_vec_2 == 10'h7; // @[dec_tlu_ctl.scala 2805:42]
|
|
wire _T_619 = io_mhpme_vec_2 == 10'h8; // @[dec_tlu_ctl.scala 2806:42]
|
|
wire _T_621 = io_mhpme_vec_2 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42]
|
|
wire _T_623 = io_mhpme_vec_2 == 10'h9; // @[dec_tlu_ctl.scala 2808:42]
|
|
wire _T_626 = io_mhpme_vec_2 == 10'ha; // @[dec_tlu_ctl.scala 2809:42]
|
|
wire _T_631 = io_mhpme_vec_2 == 10'hb; // @[dec_tlu_ctl.scala 2810:42]
|
|
wire _T_634 = io_mhpme_vec_2 == 10'hc; // @[dec_tlu_ctl.scala 2811:42]
|
|
wire _T_637 = io_mhpme_vec_2 == 10'hd; // @[dec_tlu_ctl.scala 2812:42]
|
|
wire _T_641 = io_mhpme_vec_2 == 10'he; // @[dec_tlu_ctl.scala 2813:42]
|
|
wire _T_646 = io_mhpme_vec_2 == 10'hf; // @[dec_tlu_ctl.scala 2815:42]
|
|
wire _T_649 = io_mhpme_vec_2 == 10'h10; // @[dec_tlu_ctl.scala 2816:42]
|
|
wire _T_652 = io_mhpme_vec_2 == 10'h12; // @[dec_tlu_ctl.scala 2817:42]
|
|
wire _T_655 = io_mhpme_vec_2 == 10'h11; // @[dec_tlu_ctl.scala 2818:42]
|
|
wire _T_658 = io_mhpme_vec_2 == 10'h13; // @[dec_tlu_ctl.scala 2819:42]
|
|
wire _T_661 = io_mhpme_vec_2 == 10'h14; // @[dec_tlu_ctl.scala 2820:42]
|
|
wire _T_664 = io_mhpme_vec_2 == 10'h15; // @[dec_tlu_ctl.scala 2821:42]
|
|
wire _T_667 = io_mhpme_vec_2 == 10'h16; // @[dec_tlu_ctl.scala 2822:42]
|
|
wire _T_670 = io_mhpme_vec_2 == 10'h17; // @[dec_tlu_ctl.scala 2823:42]
|
|
wire _T_673 = io_mhpme_vec_2 == 10'h18; // @[dec_tlu_ctl.scala 2824:42]
|
|
wire _T_678 = io_mhpme_vec_2 == 10'h19; // @[dec_tlu_ctl.scala 2826:42]
|
|
wire _T_683 = io_mhpme_vec_2 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42]
|
|
wire _T_688 = io_mhpme_vec_2 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42]
|
|
wire _T_693 = io_mhpme_vec_2 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42]
|
|
wire _T_697 = io_mhpme_vec_2 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42]
|
|
wire _T_699 = io_mhpme_vec_2 == 10'h20; // @[dec_tlu_ctl.scala 2832:42]
|
|
wire _T_701 = io_mhpme_vec_2 == 10'h22; // @[dec_tlu_ctl.scala 2833:42]
|
|
wire _T_703 = io_mhpme_vec_2 == 10'h23; // @[dec_tlu_ctl.scala 2834:42]
|
|
wire _T_705 = io_mhpme_vec_2 == 10'h24; // @[dec_tlu_ctl.scala 2835:42]
|
|
wire _T_707 = io_mhpme_vec_2 == 10'h25; // @[dec_tlu_ctl.scala 2836:42]
|
|
wire _T_711 = io_mhpme_vec_2 == 10'h26; // @[dec_tlu_ctl.scala 2837:42]
|
|
wire _T_715 = io_mhpme_vec_2 == 10'h27; // @[dec_tlu_ctl.scala 2838:42]
|
|
wire _T_717 = io_mhpme_vec_2 == 10'h28; // @[dec_tlu_ctl.scala 2839:42]
|
|
wire _T_719 = io_mhpme_vec_2 == 10'h29; // @[dec_tlu_ctl.scala 2840:42]
|
|
wire _T_723 = io_mhpme_vec_2 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42]
|
|
wire _T_725 = io_mhpme_vec_2 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42]
|
|
wire _T_727 = io_mhpme_vec_2 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42]
|
|
wire _T_729 = io_mhpme_vec_2 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42]
|
|
wire _T_731 = io_mhpme_vec_2 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42]
|
|
wire _T_733 = io_mhpme_vec_2 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42]
|
|
wire _T_735 = io_mhpme_vec_2 == 10'h30; // @[dec_tlu_ctl.scala 2848:42]
|
|
wire _T_737 = io_mhpme_vec_2 == 10'h31; // @[dec_tlu_ctl.scala 2849:42]
|
|
wire _T_742 = io_mhpme_vec_2 == 10'h32; // @[dec_tlu_ctl.scala 2850:42]
|
|
wire _T_752 = io_mhpme_vec_2 == 10'h36; // @[dec_tlu_ctl.scala 2851:42]
|
|
wire _T_755 = io_mhpme_vec_2 == 10'h37; // @[dec_tlu_ctl.scala 2852:42]
|
|
wire _T_760 = io_mhpme_vec_2 == 10'h38; // @[dec_tlu_ctl.scala 2853:42]
|
|
wire _T_765 = io_mhpme_vec_2 == 10'h200; // @[dec_tlu_ctl.scala 2855:42]
|
|
wire _T_767 = io_mhpme_vec_2 == 10'h201; // @[dec_tlu_ctl.scala 2856:42]
|
|
wire _T_769 = io_mhpme_vec_2 == 10'h202; // @[dec_tlu_ctl.scala 2857:42]
|
|
wire _T_771 = io_mhpme_vec_2 == 10'h203; // @[dec_tlu_ctl.scala 2858:42]
|
|
wire _T_773 = io_mhpme_vec_2 == 10'h204; // @[dec_tlu_ctl.scala 2859:42]
|
|
wire _T_776 = _T_598 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_777 = _T_600 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_778 = _T_602 & _T_13; // @[Mux.scala 27:72]
|
|
wire _T_779 = _T_606 & _T_19; // @[Mux.scala 27:72]
|
|
wire _T_780 = _T_612 & _T_24; // @[Mux.scala 27:72]
|
|
wire _T_781 = _T_617 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_782 = _T_619 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_783 = _T_621 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_784 = _T_623 & _T_33; // @[Mux.scala 27:72]
|
|
wire _T_785 = _T_626 & _T_38; // @[Mux.scala 27:72]
|
|
wire _T_786 = _T_631 & _T_41; // @[Mux.scala 27:72]
|
|
wire _T_787 = _T_634 & _T_44; // @[Mux.scala 27:72]
|
|
wire _T_788 = _T_637 & _T_48; // @[Mux.scala 27:72]
|
|
wire _T_789 = _T_641 & _T_53; // @[Mux.scala 27:72]
|
|
wire _T_790 = _T_646 & _T_56; // @[Mux.scala 27:72]
|
|
wire _T_791 = _T_649 & _T_59; // @[Mux.scala 27:72]
|
|
wire _T_792 = _T_652 & _T_62; // @[Mux.scala 27:72]
|
|
wire _T_793 = _T_655 & _T_65; // @[Mux.scala 27:72]
|
|
wire _T_794 = _T_658 & _T_68; // @[Mux.scala 27:72]
|
|
wire _T_795 = _T_661 & _T_71; // @[Mux.scala 27:72]
|
|
wire _T_796 = _T_664 & _T_74; // @[Mux.scala 27:72]
|
|
wire _T_797 = _T_667 & _T_77; // @[Mux.scala 27:72]
|
|
wire _T_798 = _T_670 & _T_80; // @[Mux.scala 27:72]
|
|
wire _T_799 = _T_673 & _T_85; // @[Mux.scala 27:72]
|
|
wire _T_800 = _T_678 & _T_90; // @[Mux.scala 27:72]
|
|
wire _T_801 = _T_683 & _T_95; // @[Mux.scala 27:72]
|
|
wire _T_802 = _T_688 & _T_100; // @[Mux.scala 27:72]
|
|
wire _T_803 = _T_693 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_805 = _T_697 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_806 = _T_699 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_807 = _T_701 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_808 = _T_703 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_809 = _T_705 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_810 = _T_707 & _T_118; // @[Mux.scala 27:72]
|
|
wire _T_811 = _T_711 & _T_122; // @[Mux.scala 27:72]
|
|
wire _T_812 = _T_715 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_813 = _T_717 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_814 = _T_719 & _T_130; // @[Mux.scala 27:72]
|
|
wire _T_815 = _T_723 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_816 = _T_725 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_817 = _T_727 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_818 = _T_729 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_819 = _T_731 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_820 = _T_733 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_821 = _T_735 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_822 = _T_737 & _T_149; // @[Mux.scala 27:72]
|
|
wire _T_823 = _T_742 & _T_159; // @[Mux.scala 27:72]
|
|
wire _T_824 = _T_752 & _T_162; // @[Mux.scala 27:72]
|
|
wire _T_825 = _T_755 & _T_167; // @[Mux.scala 27:72]
|
|
wire _T_826 = _T_760 & _T_172; // @[Mux.scala 27:72]
|
|
wire _T_827 = _T_765 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_828 = _T_767 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_829 = _T_769 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_830 = _T_771 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_831 = _T_773 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_832 = _T_596 | _T_776; // @[Mux.scala 27:72]
|
|
wire _T_833 = _T_832 | _T_777; // @[Mux.scala 27:72]
|
|
wire _T_834 = _T_833 | _T_778; // @[Mux.scala 27:72]
|
|
wire _T_835 = _T_834 | _T_779; // @[Mux.scala 27:72]
|
|
wire _T_836 = _T_835 | _T_780; // @[Mux.scala 27:72]
|
|
wire _T_837 = _T_836 | _T_781; // @[Mux.scala 27:72]
|
|
wire _T_838 = _T_837 | _T_782; // @[Mux.scala 27:72]
|
|
wire _T_839 = _T_838 | _T_783; // @[Mux.scala 27:72]
|
|
wire _T_840 = _T_839 | _T_784; // @[Mux.scala 27:72]
|
|
wire _T_841 = _T_840 | _T_785; // @[Mux.scala 27:72]
|
|
wire _T_842 = _T_841 | _T_786; // @[Mux.scala 27:72]
|
|
wire _T_843 = _T_842 | _T_787; // @[Mux.scala 27:72]
|
|
wire _T_844 = _T_843 | _T_788; // @[Mux.scala 27:72]
|
|
wire _T_845 = _T_844 | _T_789; // @[Mux.scala 27:72]
|
|
wire _T_846 = _T_845 | _T_790; // @[Mux.scala 27:72]
|
|
wire _T_847 = _T_846 | _T_791; // @[Mux.scala 27:72]
|
|
wire _T_848 = _T_847 | _T_792; // @[Mux.scala 27:72]
|
|
wire _T_849 = _T_848 | _T_793; // @[Mux.scala 27:72]
|
|
wire _T_850 = _T_849 | _T_794; // @[Mux.scala 27:72]
|
|
wire _T_851 = _T_850 | _T_795; // @[Mux.scala 27:72]
|
|
wire _T_852 = _T_851 | _T_796; // @[Mux.scala 27:72]
|
|
wire _T_853 = _T_852 | _T_797; // @[Mux.scala 27:72]
|
|
wire _T_854 = _T_853 | _T_798; // @[Mux.scala 27:72]
|
|
wire _T_855 = _T_854 | _T_799; // @[Mux.scala 27:72]
|
|
wire _T_856 = _T_855 | _T_800; // @[Mux.scala 27:72]
|
|
wire _T_857 = _T_856 | _T_801; // @[Mux.scala 27:72]
|
|
wire _T_858 = _T_857 | _T_802; // @[Mux.scala 27:72]
|
|
wire _T_859 = _T_858 | _T_803; // @[Mux.scala 27:72]
|
|
wire _T_860 = _T_859 | _T_783; // @[Mux.scala 27:72]
|
|
wire _T_861 = _T_860 | _T_805; // @[Mux.scala 27:72]
|
|
wire _T_862 = _T_861 | _T_806; // @[Mux.scala 27:72]
|
|
wire _T_863 = _T_862 | _T_807; // @[Mux.scala 27:72]
|
|
wire _T_864 = _T_863 | _T_808; // @[Mux.scala 27:72]
|
|
wire _T_865 = _T_864 | _T_809; // @[Mux.scala 27:72]
|
|
wire _T_866 = _T_865 | _T_810; // @[Mux.scala 27:72]
|
|
wire _T_867 = _T_866 | _T_811; // @[Mux.scala 27:72]
|
|
wire _T_868 = _T_867 | _T_812; // @[Mux.scala 27:72]
|
|
wire _T_869 = _T_868 | _T_813; // @[Mux.scala 27:72]
|
|
wire _T_870 = _T_869 | _T_814; // @[Mux.scala 27:72]
|
|
wire _T_871 = _T_870 | _T_815; // @[Mux.scala 27:72]
|
|
wire _T_872 = _T_871 | _T_816; // @[Mux.scala 27:72]
|
|
wire _T_873 = _T_872 | _T_817; // @[Mux.scala 27:72]
|
|
wire _T_874 = _T_873 | _T_818; // @[Mux.scala 27:72]
|
|
wire _T_875 = _T_874 | _T_819; // @[Mux.scala 27:72]
|
|
wire _T_876 = _T_875 | _T_820; // @[Mux.scala 27:72]
|
|
wire _T_877 = _T_876 | _T_821; // @[Mux.scala 27:72]
|
|
wire _T_878 = _T_877 | _T_822; // @[Mux.scala 27:72]
|
|
wire _T_879 = _T_878 | _T_823; // @[Mux.scala 27:72]
|
|
wire _T_880 = _T_879 | _T_824; // @[Mux.scala 27:72]
|
|
wire _T_881 = _T_880 | _T_825; // @[Mux.scala 27:72]
|
|
wire _T_882 = _T_881 | _T_826; // @[Mux.scala 27:72]
|
|
wire _T_883 = _T_882 | _T_827; // @[Mux.scala 27:72]
|
|
wire _T_884 = _T_883 | _T_828; // @[Mux.scala 27:72]
|
|
wire _T_885 = _T_884 | _T_829; // @[Mux.scala 27:72]
|
|
wire _T_886 = _T_885 | _T_830; // @[Mux.scala 27:72]
|
|
wire _T_887 = _T_886 | _T_831; // @[Mux.scala 27:72]
|
|
wire _T_891 = ~io_mcountinhibit[6]; // @[dec_tlu_ctl.scala 2797:40]
|
|
wire _T_892 = io_mhpme_vec_3 == 10'h1; // @[dec_tlu_ctl.scala 2798:42]
|
|
wire _T_894 = io_mhpme_vec_3 == 10'h2; // @[dec_tlu_ctl.scala 2799:42]
|
|
wire _T_896 = io_mhpme_vec_3 == 10'h3; // @[dec_tlu_ctl.scala 2800:42]
|
|
wire _T_898 = io_mhpme_vec_3 == 10'h4; // @[dec_tlu_ctl.scala 2801:42]
|
|
wire _T_902 = io_mhpme_vec_3 == 10'h5; // @[dec_tlu_ctl.scala 2802:42]
|
|
wire _T_908 = io_mhpme_vec_3 == 10'h6; // @[dec_tlu_ctl.scala 2803:42]
|
|
wire _T_913 = io_mhpme_vec_3 == 10'h7; // @[dec_tlu_ctl.scala 2805:42]
|
|
wire _T_915 = io_mhpme_vec_3 == 10'h8; // @[dec_tlu_ctl.scala 2806:42]
|
|
wire _T_917 = io_mhpme_vec_3 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42]
|
|
wire _T_919 = io_mhpme_vec_3 == 10'h9; // @[dec_tlu_ctl.scala 2808:42]
|
|
wire _T_922 = io_mhpme_vec_3 == 10'ha; // @[dec_tlu_ctl.scala 2809:42]
|
|
wire _T_927 = io_mhpme_vec_3 == 10'hb; // @[dec_tlu_ctl.scala 2810:42]
|
|
wire _T_930 = io_mhpme_vec_3 == 10'hc; // @[dec_tlu_ctl.scala 2811:42]
|
|
wire _T_933 = io_mhpme_vec_3 == 10'hd; // @[dec_tlu_ctl.scala 2812:42]
|
|
wire _T_937 = io_mhpme_vec_3 == 10'he; // @[dec_tlu_ctl.scala 2813:42]
|
|
wire _T_942 = io_mhpme_vec_3 == 10'hf; // @[dec_tlu_ctl.scala 2815:42]
|
|
wire _T_945 = io_mhpme_vec_3 == 10'h10; // @[dec_tlu_ctl.scala 2816:42]
|
|
wire _T_948 = io_mhpme_vec_3 == 10'h12; // @[dec_tlu_ctl.scala 2817:42]
|
|
wire _T_951 = io_mhpme_vec_3 == 10'h11; // @[dec_tlu_ctl.scala 2818:42]
|
|
wire _T_954 = io_mhpme_vec_3 == 10'h13; // @[dec_tlu_ctl.scala 2819:42]
|
|
wire _T_957 = io_mhpme_vec_3 == 10'h14; // @[dec_tlu_ctl.scala 2820:42]
|
|
wire _T_960 = io_mhpme_vec_3 == 10'h15; // @[dec_tlu_ctl.scala 2821:42]
|
|
wire _T_963 = io_mhpme_vec_3 == 10'h16; // @[dec_tlu_ctl.scala 2822:42]
|
|
wire _T_966 = io_mhpme_vec_3 == 10'h17; // @[dec_tlu_ctl.scala 2823:42]
|
|
wire _T_969 = io_mhpme_vec_3 == 10'h18; // @[dec_tlu_ctl.scala 2824:42]
|
|
wire _T_974 = io_mhpme_vec_3 == 10'h19; // @[dec_tlu_ctl.scala 2826:42]
|
|
wire _T_979 = io_mhpme_vec_3 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42]
|
|
wire _T_984 = io_mhpme_vec_3 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42]
|
|
wire _T_989 = io_mhpme_vec_3 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42]
|
|
wire _T_993 = io_mhpme_vec_3 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42]
|
|
wire _T_995 = io_mhpme_vec_3 == 10'h20; // @[dec_tlu_ctl.scala 2832:42]
|
|
wire _T_997 = io_mhpme_vec_3 == 10'h22; // @[dec_tlu_ctl.scala 2833:42]
|
|
wire _T_999 = io_mhpme_vec_3 == 10'h23; // @[dec_tlu_ctl.scala 2834:42]
|
|
wire _T_1001 = io_mhpme_vec_3 == 10'h24; // @[dec_tlu_ctl.scala 2835:42]
|
|
wire _T_1003 = io_mhpme_vec_3 == 10'h25; // @[dec_tlu_ctl.scala 2836:42]
|
|
wire _T_1007 = io_mhpme_vec_3 == 10'h26; // @[dec_tlu_ctl.scala 2837:42]
|
|
wire _T_1011 = io_mhpme_vec_3 == 10'h27; // @[dec_tlu_ctl.scala 2838:42]
|
|
wire _T_1013 = io_mhpme_vec_3 == 10'h28; // @[dec_tlu_ctl.scala 2839:42]
|
|
wire _T_1015 = io_mhpme_vec_3 == 10'h29; // @[dec_tlu_ctl.scala 2840:42]
|
|
wire _T_1019 = io_mhpme_vec_3 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42]
|
|
wire _T_1021 = io_mhpme_vec_3 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42]
|
|
wire _T_1023 = io_mhpme_vec_3 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42]
|
|
wire _T_1025 = io_mhpme_vec_3 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42]
|
|
wire _T_1027 = io_mhpme_vec_3 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42]
|
|
wire _T_1029 = io_mhpme_vec_3 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42]
|
|
wire _T_1031 = io_mhpme_vec_3 == 10'h30; // @[dec_tlu_ctl.scala 2848:42]
|
|
wire _T_1033 = io_mhpme_vec_3 == 10'h31; // @[dec_tlu_ctl.scala 2849:42]
|
|
wire _T_1038 = io_mhpme_vec_3 == 10'h32; // @[dec_tlu_ctl.scala 2850:42]
|
|
wire _T_1048 = io_mhpme_vec_3 == 10'h36; // @[dec_tlu_ctl.scala 2851:42]
|
|
wire _T_1051 = io_mhpme_vec_3 == 10'h37; // @[dec_tlu_ctl.scala 2852:42]
|
|
wire _T_1056 = io_mhpme_vec_3 == 10'h38; // @[dec_tlu_ctl.scala 2853:42]
|
|
wire _T_1061 = io_mhpme_vec_3 == 10'h200; // @[dec_tlu_ctl.scala 2855:42]
|
|
wire _T_1063 = io_mhpme_vec_3 == 10'h201; // @[dec_tlu_ctl.scala 2856:42]
|
|
wire _T_1065 = io_mhpme_vec_3 == 10'h202; // @[dec_tlu_ctl.scala 2857:42]
|
|
wire _T_1067 = io_mhpme_vec_3 == 10'h203; // @[dec_tlu_ctl.scala 2858:42]
|
|
wire _T_1069 = io_mhpme_vec_3 == 10'h204; // @[dec_tlu_ctl.scala 2859:42]
|
|
wire _T_1072 = _T_894 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
|
|
wire _T_1073 = _T_896 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
|
|
wire _T_1074 = _T_898 & _T_13; // @[Mux.scala 27:72]
|
|
wire _T_1075 = _T_902 & _T_19; // @[Mux.scala 27:72]
|
|
wire _T_1076 = _T_908 & _T_24; // @[Mux.scala 27:72]
|
|
wire _T_1077 = _T_913 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
|
|
wire _T_1078 = _T_915 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
|
|
wire _T_1079 = _T_917 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
|
|
wire _T_1080 = _T_919 & _T_33; // @[Mux.scala 27:72]
|
|
wire _T_1081 = _T_922 & _T_38; // @[Mux.scala 27:72]
|
|
wire _T_1082 = _T_927 & _T_41; // @[Mux.scala 27:72]
|
|
wire _T_1083 = _T_930 & _T_44; // @[Mux.scala 27:72]
|
|
wire _T_1084 = _T_933 & _T_48; // @[Mux.scala 27:72]
|
|
wire _T_1085 = _T_937 & _T_53; // @[Mux.scala 27:72]
|
|
wire _T_1086 = _T_942 & _T_56; // @[Mux.scala 27:72]
|
|
wire _T_1087 = _T_945 & _T_59; // @[Mux.scala 27:72]
|
|
wire _T_1088 = _T_948 & _T_62; // @[Mux.scala 27:72]
|
|
wire _T_1089 = _T_951 & _T_65; // @[Mux.scala 27:72]
|
|
wire _T_1090 = _T_954 & _T_68; // @[Mux.scala 27:72]
|
|
wire _T_1091 = _T_957 & _T_71; // @[Mux.scala 27:72]
|
|
wire _T_1092 = _T_960 & _T_74; // @[Mux.scala 27:72]
|
|
wire _T_1093 = _T_963 & _T_77; // @[Mux.scala 27:72]
|
|
wire _T_1094 = _T_966 & _T_80; // @[Mux.scala 27:72]
|
|
wire _T_1095 = _T_969 & _T_85; // @[Mux.scala 27:72]
|
|
wire _T_1096 = _T_974 & _T_90; // @[Mux.scala 27:72]
|
|
wire _T_1097 = _T_979 & _T_95; // @[Mux.scala 27:72]
|
|
wire _T_1098 = _T_984 & _T_100; // @[Mux.scala 27:72]
|
|
wire _T_1099 = _T_989 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
|
|
wire _T_1101 = _T_993 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1102 = _T_995 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
|
|
wire _T_1103 = _T_997 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1104 = _T_999 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1105 = _T_1001 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
|
|
wire _T_1106 = _T_1003 & _T_118; // @[Mux.scala 27:72]
|
|
wire _T_1107 = _T_1007 & _T_122; // @[Mux.scala 27:72]
|
|
wire _T_1108 = _T_1011 & io_take_ext_int; // @[Mux.scala 27:72]
|
|
wire _T_1109 = _T_1013 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
|
|
wire _T_1110 = _T_1015 & _T_130; // @[Mux.scala 27:72]
|
|
wire _T_1111 = _T_1019 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1112 = _T_1021 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
|
|
wire _T_1113 = _T_1023 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
|
|
wire _T_1114 = _T_1025 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1115 = _T_1027 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
|
|
wire _T_1116 = _T_1029 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1117 = _T_1031 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
|
|
wire _T_1118 = _T_1033 & _T_149; // @[Mux.scala 27:72]
|
|
wire _T_1119 = _T_1038 & _T_159; // @[Mux.scala 27:72]
|
|
wire _T_1120 = _T_1048 & _T_162; // @[Mux.scala 27:72]
|
|
wire _T_1121 = _T_1051 & _T_167; // @[Mux.scala 27:72]
|
|
wire _T_1122 = _T_1056 & _T_172; // @[Mux.scala 27:72]
|
|
wire _T_1123 = _T_1061 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
|
|
wire _T_1124 = _T_1063 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
|
|
wire _T_1125 = _T_1065 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
|
|
wire _T_1126 = _T_1067 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
|
|
wire _T_1127 = _T_1069 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
|
|
wire _T_1128 = _T_892 | _T_1072; // @[Mux.scala 27:72]
|
|
wire _T_1129 = _T_1128 | _T_1073; // @[Mux.scala 27:72]
|
|
wire _T_1130 = _T_1129 | _T_1074; // @[Mux.scala 27:72]
|
|
wire _T_1131 = _T_1130 | _T_1075; // @[Mux.scala 27:72]
|
|
wire _T_1132 = _T_1131 | _T_1076; // @[Mux.scala 27:72]
|
|
wire _T_1133 = _T_1132 | _T_1077; // @[Mux.scala 27:72]
|
|
wire _T_1134 = _T_1133 | _T_1078; // @[Mux.scala 27:72]
|
|
wire _T_1135 = _T_1134 | _T_1079; // @[Mux.scala 27:72]
|
|
wire _T_1136 = _T_1135 | _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1137 = _T_1136 | _T_1081; // @[Mux.scala 27:72]
|
|
wire _T_1138 = _T_1137 | _T_1082; // @[Mux.scala 27:72]
|
|
wire _T_1139 = _T_1138 | _T_1083; // @[Mux.scala 27:72]
|
|
wire _T_1140 = _T_1139 | _T_1084; // @[Mux.scala 27:72]
|
|
wire _T_1141 = _T_1140 | _T_1085; // @[Mux.scala 27:72]
|
|
wire _T_1142 = _T_1141 | _T_1086; // @[Mux.scala 27:72]
|
|
wire _T_1143 = _T_1142 | _T_1087; // @[Mux.scala 27:72]
|
|
wire _T_1144 = _T_1143 | _T_1088; // @[Mux.scala 27:72]
|
|
wire _T_1145 = _T_1144 | _T_1089; // @[Mux.scala 27:72]
|
|
wire _T_1146 = _T_1145 | _T_1090; // @[Mux.scala 27:72]
|
|
wire _T_1147 = _T_1146 | _T_1091; // @[Mux.scala 27:72]
|
|
wire _T_1148 = _T_1147 | _T_1092; // @[Mux.scala 27:72]
|
|
wire _T_1149 = _T_1148 | _T_1093; // @[Mux.scala 27:72]
|
|
wire _T_1150 = _T_1149 | _T_1094; // @[Mux.scala 27:72]
|
|
wire _T_1151 = _T_1150 | _T_1095; // @[Mux.scala 27:72]
|
|
wire _T_1152 = _T_1151 | _T_1096; // @[Mux.scala 27:72]
|
|
wire _T_1153 = _T_1152 | _T_1097; // @[Mux.scala 27:72]
|
|
wire _T_1154 = _T_1153 | _T_1098; // @[Mux.scala 27:72]
|
|
wire _T_1155 = _T_1154 | _T_1099; // @[Mux.scala 27:72]
|
|
wire _T_1156 = _T_1155 | _T_1079; // @[Mux.scala 27:72]
|
|
wire _T_1157 = _T_1156 | _T_1101; // @[Mux.scala 27:72]
|
|
wire _T_1158 = _T_1157 | _T_1102; // @[Mux.scala 27:72]
|
|
wire _T_1159 = _T_1158 | _T_1103; // @[Mux.scala 27:72]
|
|
wire _T_1160 = _T_1159 | _T_1104; // @[Mux.scala 27:72]
|
|
wire _T_1161 = _T_1160 | _T_1105; // @[Mux.scala 27:72]
|
|
wire _T_1162 = _T_1161 | _T_1106; // @[Mux.scala 27:72]
|
|
wire _T_1163 = _T_1162 | _T_1107; // @[Mux.scala 27:72]
|
|
wire _T_1164 = _T_1163 | _T_1108; // @[Mux.scala 27:72]
|
|
wire _T_1165 = _T_1164 | _T_1109; // @[Mux.scala 27:72]
|
|
wire _T_1166 = _T_1165 | _T_1110; // @[Mux.scala 27:72]
|
|
wire _T_1167 = _T_1166 | _T_1111; // @[Mux.scala 27:72]
|
|
wire _T_1168 = _T_1167 | _T_1112; // @[Mux.scala 27:72]
|
|
wire _T_1169 = _T_1168 | _T_1113; // @[Mux.scala 27:72]
|
|
wire _T_1170 = _T_1169 | _T_1114; // @[Mux.scala 27:72]
|
|
wire _T_1171 = _T_1170 | _T_1115; // @[Mux.scala 27:72]
|
|
wire _T_1172 = _T_1171 | _T_1116; // @[Mux.scala 27:72]
|
|
wire _T_1173 = _T_1172 | _T_1117; // @[Mux.scala 27:72]
|
|
wire _T_1174 = _T_1173 | _T_1118; // @[Mux.scala 27:72]
|
|
wire _T_1175 = _T_1174 | _T_1119; // @[Mux.scala 27:72]
|
|
wire _T_1176 = _T_1175 | _T_1120; // @[Mux.scala 27:72]
|
|
wire _T_1177 = _T_1176 | _T_1121; // @[Mux.scala 27:72]
|
|
wire _T_1178 = _T_1177 | _T_1122; // @[Mux.scala 27:72]
|
|
wire _T_1179 = _T_1178 | _T_1123; // @[Mux.scala 27:72]
|
|
wire _T_1180 = _T_1179 | _T_1124; // @[Mux.scala 27:72]
|
|
wire _T_1181 = _T_1180 | _T_1125; // @[Mux.scala 27:72]
|
|
wire _T_1182 = _T_1181 | _T_1126; // @[Mux.scala 27:72]
|
|
wire _T_1183 = _T_1182 | _T_1127; // @[Mux.scala 27:72]
|
|
reg _T_1189; // @[Reg.scala 27:20]
|
|
wire _T_1187 = io_mdseac_locked_ns ^ _T_1189; // @[lib.scala 488:21]
|
|
wire _T_1188 = |_T_1187; // @[lib.scala 488:29]
|
|
reg _T_1193; // @[Reg.scala 27:20]
|
|
wire _T_1191 = io_lsu_single_ecc_error_r ^ _T_1193; // @[lib.scala 488:21]
|
|
wire _T_1192 = |_T_1191; // @[lib.scala 488:29]
|
|
reg _T_1201; // @[Reg.scala 27:20]
|
|
wire _T_1199 = io_lsu_i0_exc_r ^ _T_1201; // @[lib.scala 488:21]
|
|
wire _T_1200 = |_T_1199; // @[lib.scala 488:29]
|
|
reg _T_1205; // @[Reg.scala 27:20]
|
|
wire _T_1203 = io_take_ext_int_start ^ _T_1205; // @[lib.scala 488:21]
|
|
wire _T_1204 = |_T_1203; // @[lib.scala 488:29]
|
|
reg _T_1209; // @[Reg.scala 27:20]
|
|
wire _T_1207 = io_take_ext_int_start_d1 ^ _T_1209; // @[lib.scala 488:21]
|
|
wire _T_1208 = |_T_1207; // @[lib.scala 488:29]
|
|
reg _T_1213; // @[Reg.scala 27:20]
|
|
wire _T_1211 = io_take_ext_int_start_d2 ^ _T_1213; // @[lib.scala 488:21]
|
|
wire _T_1212 = |_T_1211; // @[lib.scala 488:29]
|
|
reg _T_1217; // @[Reg.scala 27:20]
|
|
wire _T_1215 = io_ext_int_freeze ^ _T_1217; // @[lib.scala 488:21]
|
|
wire _T_1216 = |_T_1215; // @[lib.scala 488:29]
|
|
reg [5:0] _T_1221; // @[Reg.scala 27:20]
|
|
wire [5:0] _T_1219 = io_mip_ns ^ _T_1221; // @[lib.scala 466:21]
|
|
wire _T_1220 = |_T_1219; // @[lib.scala 466:29]
|
|
wire _T_1222 = ~io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 2879:80]
|
|
wire _T_1223 = io_mcyclel_cout & _T_1222; // @[dec_tlu_ctl.scala 2879:78]
|
|
wire _T_1224 = _T_1223 & io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 2879:97]
|
|
reg _T_1228; // @[Reg.scala 27:20]
|
|
wire _T_1226 = _T_1224 ^ _T_1228; // @[lib.scala 488:21]
|
|
wire _T_1227 = |_T_1226; // @[lib.scala 488:29]
|
|
reg _T_1232; // @[Reg.scala 27:20]
|
|
wire _T_1230 = io_minstret_enable ^ _T_1232; // @[lib.scala 488:21]
|
|
wire _T_1231 = |_T_1230; // @[lib.scala 488:29]
|
|
reg _T_1236; // @[Reg.scala 27:20]
|
|
wire _T_1234 = io_minstretl_cout_ns ^ _T_1236; // @[lib.scala 488:21]
|
|
wire _T_1235 = |_T_1234; // @[lib.scala 488:29]
|
|
reg [3:0] _T_1244; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1242 = io_meicidpl_ns ^ _T_1244; // @[lib.scala 466:21]
|
|
wire _T_1243 = |_T_1242; // @[lib.scala 466:29]
|
|
reg _T_1248; // @[Reg.scala 27:20]
|
|
wire _T_1246 = io_icache_rd_valid ^ _T_1248; // @[lib.scala 488:21]
|
|
wire _T_1247 = |_T_1246; // @[lib.scala 488:29]
|
|
reg _T_1252; // @[Reg.scala 27:20]
|
|
wire _T_1250 = io_icache_wr_valid ^ _T_1252; // @[lib.scala 488:21]
|
|
wire _T_1251 = |_T_1250; // @[lib.scala 488:29]
|
|
reg _T_1266_0; // @[Reg.scala 27:20]
|
|
wire _T_1254 = io_mhpmc_inc_r_0 ^ _T_1266_0; // @[lib.scala 536:68]
|
|
wire _T_1255 = |_T_1254; // @[lib.scala 536:82]
|
|
reg _T_1266_1; // @[Reg.scala 27:20]
|
|
wire _T_1256 = io_mhpmc_inc_r_1 ^ _T_1266_1; // @[lib.scala 536:68]
|
|
wire _T_1257 = |_T_1256; // @[lib.scala 536:82]
|
|
reg _T_1266_2; // @[Reg.scala 27:20]
|
|
wire _T_1258 = io_mhpmc_inc_r_2 ^ _T_1266_2; // @[lib.scala 536:68]
|
|
wire _T_1259 = |_T_1258; // @[lib.scala 536:82]
|
|
reg _T_1266_3; // @[Reg.scala 27:20]
|
|
wire _T_1260 = io_mhpmc_inc_r_3 ^ _T_1266_3; // @[lib.scala 536:68]
|
|
wire _T_1261 = |_T_1260; // @[lib.scala 536:82]
|
|
wire _T_1262 = _T_1255 | _T_1257; // @[lib.scala 536:97]
|
|
wire _T_1263 = _T_1262 | _T_1259; // @[lib.scala 536:97]
|
|
wire _T_1264 = _T_1263 | _T_1261; // @[lib.scala 536:97]
|
|
reg _T_1270; // @[Reg.scala 27:20]
|
|
wire _T_1268 = io_perfcnt_halted ^ _T_1270; // @[lib.scala 488:21]
|
|
wire _T_1269 = |_T_1268; // @[lib.scala 488:29]
|
|
reg [1:0] _T_1274; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1272 = io_mstatus_ns ^ _T_1274; // @[lib.scala 466:21]
|
|
wire _T_1273 = |_T_1272; // @[lib.scala 466:29]
|
|
assign io_mhpmc_inc_r_0 = _T_3 & _T_295; // @[dec_tlu_ctl.scala 2797:35]
|
|
assign io_mhpmc_inc_r_1 = _T_299 & _T_591; // @[dec_tlu_ctl.scala 2797:35]
|
|
assign io_mhpmc_inc_r_2 = _T_595 & _T_887; // @[dec_tlu_ctl.scala 2797:35]
|
|
assign io_mhpmc_inc_r_3 = _T_891 & _T_1183; // @[dec_tlu_ctl.scala 2797:35]
|
|
assign io_mstatus = _T_1274; // @[dec_tlu_ctl.scala 2888:52]
|
|
assign io_mcyclel_cout_f = _T_1228; // @[dec_tlu_ctl.scala 2879:52]
|
|
assign io_minstret_enable_f = _T_1232; // @[dec_tlu_ctl.scala 2880:52]
|
|
assign io_minstretl_cout_f = _T_1236; // @[dec_tlu_ctl.scala 2881:52]
|
|
assign io_meicidpl = _T_1244; // @[dec_tlu_ctl.scala 2883:52]
|
|
assign io_icache_rd_valid_f = _T_1248; // @[dec_tlu_ctl.scala 2884:52]
|
|
assign io_icache_wr_valid_f = _T_1252; // @[dec_tlu_ctl.scala 2885:52]
|
|
assign io_mhpmc_inc_r_d1_0 = _T_1266_0; // @[dec_tlu_ctl.scala 2886:52]
|
|
assign io_mhpmc_inc_r_d1_1 = _T_1266_1; // @[dec_tlu_ctl.scala 2886:52]
|
|
assign io_mhpmc_inc_r_d1_2 = _T_1266_2; // @[dec_tlu_ctl.scala 2886:52]
|
|
assign io_mhpmc_inc_r_d1_3 = _T_1266_3; // @[dec_tlu_ctl.scala 2886:52]
|
|
assign io_perfcnt_halted_d1 = _T_1270; // @[dec_tlu_ctl.scala 2887:52]
|
|
assign io_mdseac_locked_f = _T_1189; // @[dec_tlu_ctl.scala 2870:52]
|
|
assign io_lsu_single_ecc_error_r_d1 = _T_1193; // @[dec_tlu_ctl.scala 2871:52]
|
|
assign io_lsu_i0_exc_r_d1 = _T_1201; // @[dec_tlu_ctl.scala 2873:52]
|
|
assign io_take_ext_int_start_d1 = _T_1205; // @[dec_tlu_ctl.scala 2874:52]
|
|
assign io_take_ext_int_start_d2 = _T_1209; // @[dec_tlu_ctl.scala 2875:52]
|
|
assign io_take_ext_int_start_d3 = _T_1213; // @[dec_tlu_ctl.scala 2876:52]
|
|
assign io_ext_int_freeze_d1 = _T_1217; // @[dec_tlu_ctl.scala 2877:52]
|
|
assign io_mip = _T_1221; // @[dec_tlu_ctl.scala 2878:52]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_1189 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_1193 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_1201 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_1205 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_1209 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_1213 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_1217 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_1221 = _RAND_7[5:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_1228 = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_1232 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_1236 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_1244 = _RAND_11[3:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_1248 = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
_T_1252 = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
_T_1266_0 = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
_T_1266_1 = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
_T_1266_2 = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_1266_3 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_1270 = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
_T_1274 = _RAND_19[1:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_1189 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1193 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1201 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1205 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1209 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1213 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1217 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1221 = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1228 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1232 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1236 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1244 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1248 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1252 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1266_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1266_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1266_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1266_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1270 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1274 = 2'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1189 <= 1'h0;
|
|
end else if (_T_1188) begin
|
|
_T_1189 <= io_mdseac_locked_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1193 <= 1'h0;
|
|
end else if (_T_1192) begin
|
|
_T_1193 <= io_lsu_single_ecc_error_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1201 <= 1'h0;
|
|
end else if (_T_1200) begin
|
|
_T_1201 <= io_lsu_i0_exc_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1205 <= 1'h0;
|
|
end else if (_T_1204) begin
|
|
_T_1205 <= io_take_ext_int_start;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1209 <= 1'h0;
|
|
end else if (_T_1208) begin
|
|
_T_1209 <= io_take_ext_int_start_d1;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1213 <= 1'h0;
|
|
end else if (_T_1212) begin
|
|
_T_1213 <= io_take_ext_int_start_d2;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1217 <= 1'h0;
|
|
end else if (_T_1216) begin
|
|
_T_1217 <= io_ext_int_freeze;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1221 <= 6'h0;
|
|
end else if (_T_1220) begin
|
|
_T_1221 <= io_mip_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1228 <= 1'h0;
|
|
end else if (_T_1227) begin
|
|
_T_1228 <= _T_1224;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1232 <= 1'h0;
|
|
end else if (_T_1231) begin
|
|
_T_1232 <= io_minstret_enable;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1236 <= 1'h0;
|
|
end else if (_T_1235) begin
|
|
_T_1236 <= io_minstretl_cout_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1244 <= 4'h0;
|
|
end else if (_T_1243) begin
|
|
_T_1244 <= io_meicidpl_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1248 <= 1'h0;
|
|
end else if (_T_1247) begin
|
|
_T_1248 <= io_icache_rd_valid;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1252 <= 1'h0;
|
|
end else if (_T_1251) begin
|
|
_T_1252 <= io_icache_wr_valid;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1266_0 <= 1'h0;
|
|
end else if (_T_1264) begin
|
|
_T_1266_0 <= io_mhpmc_inc_r_0;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1266_1 <= 1'h0;
|
|
end else if (_T_1264) begin
|
|
_T_1266_1 <= io_mhpmc_inc_r_1;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1266_2 <= 1'h0;
|
|
end else if (_T_1264) begin
|
|
_T_1266_2 <= io_mhpmc_inc_r_2;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1266_3 <= 1'h0;
|
|
end else if (_T_1264) begin
|
|
_T_1266_3 <= io_mhpmc_inc_r_3;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1270 <= 1'h0;
|
|
end else if (_T_1269) begin
|
|
_T_1270 <= io_perfcnt_halted;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1274 <= 2'h0;
|
|
end else if (_T_1273) begin
|
|
_T_1274 <= io_mstatus_ns;
|
|
end
|
|
end
|
|
endmodule
|
|
module perf_csr(
|
|
input clock,
|
|
input reset,
|
|
input io_free_l2clk,
|
|
input io_dec_tlu_dbg_halted,
|
|
input [15:0] io_dcsr,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input [9:0] io_mhpme_vec_0,
|
|
input [9:0] io_mhpme_vec_1,
|
|
input [9:0] io_mhpme_vec_2,
|
|
input [9:0] io_mhpme_vec_3,
|
|
input io_dec_csr_wen_r_mod,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input io_mhpmc_inc_r_0,
|
|
input io_mhpmc_inc_r_1,
|
|
input io_mhpmc_inc_r_2,
|
|
input io_mhpmc_inc_r_3,
|
|
input io_mhpmc_inc_r_d1_0,
|
|
input io_mhpmc_inc_r_d1_1,
|
|
input io_mhpmc_inc_r_d1_2,
|
|
input io_mhpmc_inc_r_d1_3,
|
|
input io_perfcnt_halted_d1,
|
|
output [31:0] io_mhpmc3h,
|
|
output [31:0] io_mhpmc3,
|
|
output [31:0] io_mhpmc4h,
|
|
output [31:0] io_mhpmc4,
|
|
output [31:0] io_mhpmc5h,
|
|
output [31:0] io_mhpmc5,
|
|
output [31:0] io_mhpmc6h,
|
|
output [31:0] io_mhpmc6,
|
|
output [9:0] io_mhpme3,
|
|
output [9:0] io_mhpme4,
|
|
output [9:0] io_mhpme5,
|
|
output [9:0] io_mhpme6,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire _T_1 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 2578:54]
|
|
wire perfcnt_halted = _T_1 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2578:77]
|
|
wire _T_4 = ~_T_1; // @[dec_tlu_ctl.scala 2579:44]
|
|
wire [3:0] _T_6 = _T_4 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_13 = {io_mhpme_vec_3[9],io_mhpme_vec_2[9],io_mhpme_vec_1[9],io_mhpme_vec_0[9]}; // @[Cat.scala 29:58]
|
|
wire [3:0] perfcnt_during_sleep = _T_6 & _T_13; // @[dec_tlu_ctl.scala 2579:93]
|
|
wire _T_15 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2582:80]
|
|
wire _T_16 = io_perfcnt_halted_d1 & _T_15; // @[dec_tlu_ctl.scala 2582:78]
|
|
wire _T_17 = ~_T_16; // @[dec_tlu_ctl.scala 2582:55]
|
|
wire _T_20 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2583:80]
|
|
wire _T_21 = io_perfcnt_halted_d1 & _T_20; // @[dec_tlu_ctl.scala 2583:78]
|
|
wire _T_22 = ~_T_21; // @[dec_tlu_ctl.scala 2583:55]
|
|
wire _T_25 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2584:80]
|
|
wire _T_26 = io_perfcnt_halted_d1 & _T_25; // @[dec_tlu_ctl.scala 2584:78]
|
|
wire _T_27 = ~_T_26; // @[dec_tlu_ctl.scala 2584:55]
|
|
wire _T_30 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2585:80]
|
|
wire _T_31 = io_perfcnt_halted_d1 & _T_30; // @[dec_tlu_ctl.scala 2585:78]
|
|
wire _T_32 = ~_T_31; // @[dec_tlu_ctl.scala 2585:55]
|
|
wire _T_35 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2591:79]
|
|
wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 2591:50]
|
|
wire _T_36 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2592:30]
|
|
wire _T_38 = _T_36 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2592:46]
|
|
wire _T_39 = |io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2592:96]
|
|
wire mhpmc3_wr_en1 = _T_38 & _T_39; // @[dec_tlu_ctl.scala 2592:73]
|
|
wire mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2593:43]
|
|
wire [63:0] _T_42 = {io_mhpmc3h,io_mhpmc3}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc3_incr = _T_42 + 64'h1; // @[dec_tlu_ctl.scala 2596:65]
|
|
reg [31:0] _T_48; // @[Reg.scala 27:20]
|
|
wire _T_50 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2601:80]
|
|
wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_50; // @[dec_tlu_ctl.scala 2601:51]
|
|
wire mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2602:45]
|
|
reg [31:0] _T_54; // @[Reg.scala 27:20]
|
|
wire _T_56 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2612:79]
|
|
wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_56; // @[dec_tlu_ctl.scala 2612:50]
|
|
wire _T_59 = _T_36 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2613:46]
|
|
wire _T_60 = |io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2613:96]
|
|
wire mhpmc4_wr_en1 = _T_59 & _T_60; // @[dec_tlu_ctl.scala 2613:73]
|
|
wire mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2614:43]
|
|
wire [63:0] _T_63 = {io_mhpmc4h,io_mhpmc4}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc4_incr = _T_63 + 64'h1; // @[dec_tlu_ctl.scala 2618:65]
|
|
reg [31:0] _T_70; // @[Reg.scala 27:20]
|
|
wire _T_72 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2622:80]
|
|
wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_72; // @[dec_tlu_ctl.scala 2622:51]
|
|
wire mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2623:45]
|
|
reg [31:0] _T_76; // @[Reg.scala 27:20]
|
|
wire _T_78 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2631:79]
|
|
wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 2631:50]
|
|
wire _T_81 = _T_36 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2632:46]
|
|
wire _T_82 = |io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2632:96]
|
|
wire mhpmc5_wr_en1 = _T_81 & _T_82; // @[dec_tlu_ctl.scala 2632:73]
|
|
wire mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2633:43]
|
|
wire [63:0] _T_85 = {io_mhpmc5h,io_mhpmc5}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc5_incr = _T_85 + 64'h1; // @[dec_tlu_ctl.scala 2635:65]
|
|
reg [31:0] _T_91; // @[Reg.scala 27:20]
|
|
wire _T_93 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2640:80]
|
|
wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 2640:51]
|
|
wire mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2641:45]
|
|
reg [31:0] _T_97; // @[Reg.scala 27:20]
|
|
wire _T_99 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2651:79]
|
|
wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_99; // @[dec_tlu_ctl.scala 2651:50]
|
|
wire _T_102 = _T_36 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2652:46]
|
|
wire _T_103 = |io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2652:96]
|
|
wire mhpmc6_wr_en1 = _T_102 & _T_103; // @[dec_tlu_ctl.scala 2652:73]
|
|
wire mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2653:43]
|
|
wire [63:0] _T_106 = {io_mhpmc6h,io_mhpmc6}; // @[Cat.scala 29:58]
|
|
wire [63:0] mhpmc6_incr = _T_106 + 64'h1; // @[dec_tlu_ctl.scala 2655:65]
|
|
reg [31:0] _T_112; // @[Reg.scala 27:20]
|
|
wire _T_114 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2661:80]
|
|
wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_114; // @[dec_tlu_ctl.scala 2661:51]
|
|
wire mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2662:45]
|
|
reg [31:0] _T_118; // @[Reg.scala 27:20]
|
|
wire _T_120 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2671:56]
|
|
wire _T_122 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2671:102]
|
|
wire _T_123 = _T_120 | _T_122; // @[dec_tlu_ctl.scala 2671:72]
|
|
wire _T_125 = io_dec_csr_wrdata_r[9:0] < 10'h200; // @[dec_tlu_ctl.scala 2672:44]
|
|
wire _T_127 = io_dec_csr_wrdata_r[9:0] > 10'h38; // @[dec_tlu_ctl.scala 2672:88]
|
|
wire _T_128 = _T_125 & _T_127; // @[dec_tlu_ctl.scala 2672:60]
|
|
wire _T_129 = _T_123 | _T_128; // @[dec_tlu_ctl.scala 2671:107]
|
|
wire _T_131 = io_dec_csr_wrdata_r[9:0] < 10'h36; // @[dec_tlu_ctl.scala 2673:44]
|
|
wire _T_133 = io_dec_csr_wrdata_r[9:0] > 10'h32; // @[dec_tlu_ctl.scala 2673:88]
|
|
wire _T_134 = _T_131 & _T_133; // @[dec_tlu_ctl.scala 2673:60]
|
|
wire _T_135 = _T_129 | _T_134; // @[dec_tlu_ctl.scala 2672:103]
|
|
wire _T_137 = io_dec_csr_wrdata_r[9:0] == 10'h1d; // @[dec_tlu_ctl.scala 2674:43]
|
|
wire _T_138 = _T_135 | _T_137; // @[dec_tlu_ctl.scala 2673:103]
|
|
wire _T_140 = io_dec_csr_wrdata_r[9:0] == 10'h21; // @[dec_tlu_ctl.scala 2674:87]
|
|
wire zero_event_r = _T_138 | _T_140; // @[dec_tlu_ctl.scala 2674:59]
|
|
wire _T_143 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2677:77]
|
|
wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_143; // @[dec_tlu_ctl.scala 2677:48]
|
|
reg [9:0] _T_145; // @[Reg.scala 27:20]
|
|
wire _T_147 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2684:77]
|
|
wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_147; // @[dec_tlu_ctl.scala 2684:48]
|
|
reg [9:0] _T_149; // @[Reg.scala 27:20]
|
|
wire _T_151 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2691:77]
|
|
wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_151; // @[dec_tlu_ctl.scala 2691:48]
|
|
reg [9:0] _T_153; // @[Reg.scala 27:20]
|
|
wire _T_155 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2698:77]
|
|
wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_155; // @[dec_tlu_ctl.scala 2698:48]
|
|
reg [9:0] _T_157; // @[Reg.scala 27:20]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
assign io_mhpmc3h = _T_54; // @[dec_tlu_ctl.scala 2605:20]
|
|
assign io_mhpmc3 = _T_48; // @[dec_tlu_ctl.scala 2599:19]
|
|
assign io_mhpmc4h = _T_76; // @[dec_tlu_ctl.scala 2625:20]
|
|
assign io_mhpmc4 = _T_70; // @[dec_tlu_ctl.scala 2620:19]
|
|
assign io_mhpmc5h = _T_97; // @[dec_tlu_ctl.scala 2644:20]
|
|
assign io_mhpmc5 = _T_91; // @[dec_tlu_ctl.scala 2638:19]
|
|
assign io_mhpmc6h = _T_118; // @[dec_tlu_ctl.scala 2665:20]
|
|
assign io_mhpmc6 = _T_112; // @[dec_tlu_ctl.scala 2659:19]
|
|
assign io_mhpme3 = _T_145; // @[dec_tlu_ctl.scala 2679:19]
|
|
assign io_mhpme4 = _T_149; // @[dec_tlu_ctl.scala 2685:19]
|
|
assign io_mhpme5 = _T_153; // @[dec_tlu_ctl.scala 2692:19]
|
|
assign io_mhpme6 = _T_157; // @[dec_tlu_ctl.scala 2699:19]
|
|
assign io_dec_tlu_perfcnt0 = io_mhpmc_inc_r_d1_0 & _T_17; // @[dec_tlu_ctl.scala 2582:29]
|
|
assign io_dec_tlu_perfcnt1 = io_mhpmc_inc_r_d1_1 & _T_22; // @[dec_tlu_ctl.scala 2583:29]
|
|
assign io_dec_tlu_perfcnt2 = io_mhpmc_inc_r_d1_2 & _T_27; // @[dec_tlu_ctl.scala 2584:29]
|
|
assign io_dec_tlu_perfcnt3 = io_mhpmc_inc_r_d1_3 & _T_32; // @[dec_tlu_ctl.scala 2585:29]
|
|
assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_143; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_147; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_151; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_155; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_48 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_54 = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_70 = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_76 = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_91 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_97 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_112 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_118 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_145 = _RAND_8[9:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_149 = _RAND_9[9:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_153 = _RAND_10[9:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_157 = _RAND_11[9:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_48 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_54 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_70 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_76 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_91 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_97 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_112 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_118 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_145 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_149 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_153 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_157 = 10'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_48 <= 32'h0;
|
|
end else if (mhpmc3_wr_en) begin
|
|
if (mhpmc3_wr_en0) begin
|
|
_T_48 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_48 <= mhpmc3_incr[31:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_54 <= 32'h0;
|
|
end else if (mhpmc3h_wr_en) begin
|
|
if (mhpmc3h_wr_en0) begin
|
|
_T_54 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_54 <= mhpmc3_incr[63:32];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_70 <= 32'h0;
|
|
end else if (mhpmc4_wr_en) begin
|
|
if (mhpmc4_wr_en0) begin
|
|
_T_70 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_70 <= mhpmc4_incr[31:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_76 <= 32'h0;
|
|
end else if (mhpmc4h_wr_en) begin
|
|
if (mhpmc4h_wr_en0) begin
|
|
_T_76 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_76 <= mhpmc4_incr[63:32];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_91 <= 32'h0;
|
|
end else if (mhpmc5_wr_en) begin
|
|
if (mhpmc5_wr_en0) begin
|
|
_T_91 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_91 <= mhpmc5_incr[31:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_97 <= 32'h0;
|
|
end else if (mhpmc5h_wr_en) begin
|
|
if (mhpmc5h_wr_en0) begin
|
|
_T_97 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_97 <= mhpmc5_incr[63:32];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_112 <= 32'h0;
|
|
end else if (mhpmc6_wr_en) begin
|
|
if (mhpmc6_wr_en0) begin
|
|
_T_112 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_112 <= mhpmc6_incr[31:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_118 <= 32'h0;
|
|
end else if (mhpmc6h_wr_en) begin
|
|
if (mhpmc6h_wr_en0) begin
|
|
_T_118 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
_T_118 <= mhpmc6_incr[63:32];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_145 <= 10'h0;
|
|
end else if (wr_mhpme3_r) begin
|
|
if (zero_event_r) begin
|
|
_T_145 <= 10'h0;
|
|
end else begin
|
|
_T_145 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_149 <= 10'h0;
|
|
end else if (wr_mhpme4_r) begin
|
|
if (zero_event_r) begin
|
|
_T_149 <= 10'h0;
|
|
end else begin
|
|
_T_149 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_153 <= 10'h0;
|
|
end else if (wr_mhpme5_r) begin
|
|
if (zero_event_r) begin
|
|
_T_153 <= 10'h0;
|
|
end else begin
|
|
_T_153 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_157 <= 10'h0;
|
|
end else if (wr_mhpme6_r) begin
|
|
if (zero_event_r) begin
|
|
_T_157 <= 10'h0;
|
|
end else begin
|
|
_T_157 <= io_dec_csr_wrdata_r[9:0];
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
module csr_tlu(
|
|
input clock,
|
|
input reset,
|
|
input io_free_l2clk,
|
|
input io_free_clk,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
input io_dec_csr_wen_unq_d,
|
|
input io_dec_i0_decode_d,
|
|
output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
input io_ifu_ic_debug_rd_data_valid,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output io_trigger_pkt_any_0_execute,
|
|
output io_trigger_pkt_any_0_m,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output io_trigger_pkt_any_1_execute,
|
|
output io_trigger_pkt_any_1_m,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output io_trigger_pkt_any_2_execute,
|
|
output io_trigger_pkt_any_2_m,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output io_trigger_pkt_any_3_execute,
|
|
output io_trigger_pkt_any_3_m,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_ifu_pmu_bus_trxn,
|
|
input io_dma_iccm_stall_any,
|
|
input io_dma_dccm_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_dec_pmu_presync_stall,
|
|
input io_dec_pmu_postsync_stall,
|
|
input io_dec_pmu_decode_stall,
|
|
input io_ifu_pmu_fetch_stall,
|
|
input [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
input [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
input io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
input io_dec_tlu_packet_r_pmu_divide,
|
|
input io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
input io_exu_pmu_i0_br_ataken,
|
|
input io_exu_pmu_i0_br_misp,
|
|
input io_dec_pmu_instr_decoded,
|
|
input io_ifu_pmu_instr_aligned,
|
|
input io_exu_pmu_i0_pc4,
|
|
input io_ifu_pmu_ic_miss,
|
|
input io_ifu_pmu_ic_hit,
|
|
output io_dec_tlu_int_valid_wb1,
|
|
output io_dec_tlu_i0_exc_valid_wb1,
|
|
output io_dec_tlu_i0_valid_wb1,
|
|
input io_dec_csr_wen_r,
|
|
output [31:0] io_dec_tlu_mtval_wb1,
|
|
output [4:0] io_dec_tlu_exc_cause_wb1,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
input io_dec_tlu_dbg_halted,
|
|
input io_dma_pmu_dccm_write,
|
|
input io_dma_pmu_dccm_read,
|
|
input io_dma_pmu_any_write,
|
|
input io_dma_pmu_any_read,
|
|
input io_lsu_pmu_bus_busy,
|
|
input [30:0] io_dec_tlu_i0_pc_r,
|
|
input io_dec_tlu_i0_valid_r,
|
|
input io_dec_csr_any_unq_d,
|
|
output io_dec_tlu_picio_clk_override,
|
|
output io_dec_tlu_dec_clk_override,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override,
|
|
output [31:0] io_dec_csr_rddata_d,
|
|
output io_dec_tlu_pipelining_disable,
|
|
output io_dec_tlu_wr_pause_r,
|
|
input io_ifu_pmu_bus_busy,
|
|
input io_lsu_pmu_bus_error,
|
|
input io_ifu_pmu_bus_error,
|
|
input io_lsu_pmu_bus_misaligned,
|
|
input io_lsu_pmu_bus_trxn,
|
|
input [70:0] io_ifu_ic_debug_rd_data,
|
|
output [3:0] io_dec_tlu_meipt,
|
|
input [3:0] io_pic_pl,
|
|
output [3:0] io_dec_tlu_meicurpl,
|
|
output [29:0] io_dec_tlu_meihap,
|
|
input [7:0] io_pic_claimid,
|
|
input io_iccm_dma_sb_error,
|
|
input [31:0] io_lsu_imprecise_error_addr_any,
|
|
input io_lsu_imprecise_error_load_any,
|
|
input io_lsu_imprecise_error_store_any,
|
|
output [31:0] io_dec_tlu_mrac_ff,
|
|
output io_dec_tlu_wb_coalescing_disable,
|
|
output io_dec_tlu_bpred_disable,
|
|
output io_dec_tlu_sideeffect_posted_disable,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
output io_dec_tlu_external_ldfwd_disable,
|
|
output [2:0] io_dec_tlu_dma_qos_prty,
|
|
output io_dec_tlu_trace_disable,
|
|
input [31:0] io_dec_illegal_inst,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input io_mexintpend,
|
|
input [30:0] io_exu_npc_r,
|
|
input io_mpc_reset_run_req,
|
|
input [30:0] io_rst_vec,
|
|
input [27:0] io_core_id,
|
|
input [31:0] io_dec_timer_rddata_d,
|
|
input io_dec_timer_read_d,
|
|
output io_dec_csr_wen_r_mod,
|
|
input io_rfpc_i0_r,
|
|
input io_i0_trigger_hit_r,
|
|
output io_fw_halt_req,
|
|
output [1:0] io_mstatus,
|
|
input io_exc_or_int_valid_r,
|
|
input io_mret_r,
|
|
output io_mstatus_mie_ns,
|
|
input io_dcsr_single_step_running_f,
|
|
output [15:0] io_dcsr,
|
|
output [30:0] io_mtvec,
|
|
output [5:0] io_mip,
|
|
input io_dec_timer_t0_pulse,
|
|
input io_dec_timer_t1_pulse,
|
|
input io_timer_int_sync,
|
|
input io_soft_int_sync,
|
|
output [5:0] io_mie_ns,
|
|
input io_csr_wr_clk,
|
|
input io_ebreak_to_debug_mode_r,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input [1:0] io_lsu_fir_error,
|
|
output [30:0] io_npc_r,
|
|
input io_tlu_flush_lower_r_d1,
|
|
input io_dec_tlu_flush_noredir_r_d1,
|
|
input [30:0] io_tlu_flush_path_r_d1,
|
|
output [30:0] io_npc_r_d1,
|
|
input io_reset_delayed,
|
|
output [30:0] io_mepc,
|
|
input io_interrupt_valid_r,
|
|
input io_i0_exception_valid_r,
|
|
input io_lsu_exc_valid_r,
|
|
input io_mepc_trigger_hit_sel_pc_r,
|
|
input io_lsu_single_ecc_error_r,
|
|
input io_e4e5_int_clk,
|
|
input io_lsu_i0_exc_r,
|
|
input io_inst_acc_r,
|
|
input io_inst_acc_second_r,
|
|
input io_take_nmi,
|
|
input [31:0] io_lsu_error_pkt_addr_r,
|
|
input [4:0] io_exc_cause_r,
|
|
input io_i0_valid_wb,
|
|
input io_interrupt_valid_r_d1,
|
|
input io_i0_exception_valid_r_d1,
|
|
input [4:0] io_exc_cause_wb,
|
|
input io_nmi_lsu_store_type,
|
|
input io_nmi_lsu_load_type,
|
|
input io_tlu_i0_commit_cmt,
|
|
input io_ebreak_r,
|
|
input io_ecall_r,
|
|
input io_illegal_r,
|
|
output io_mdseac_locked_ns,
|
|
output io_mdseac_locked_f,
|
|
input io_nmi_int_detected_f,
|
|
input io_internal_dbg_halt_mode_f2,
|
|
input io_ext_int_freeze,
|
|
output io_ext_int_freeze_d1,
|
|
output io_take_ext_int_start_d1,
|
|
output io_take_ext_int_start_d2,
|
|
output io_take_ext_int_start_d3,
|
|
input io_ic_perr_r,
|
|
input io_iccm_sbecc_r,
|
|
input io_ifu_miss_state_idle_f,
|
|
input io_lsu_idle_any_f,
|
|
input io_dbg_tlu_halted_f,
|
|
input io_dbg_tlu_halted,
|
|
input io_debug_halt_req_f,
|
|
output io_force_halt,
|
|
input io_take_ext_int_start,
|
|
input io_trigger_hit_dmode_r_d1,
|
|
input io_trigger_hit_r_d1,
|
|
input io_dcsr_single_step_done_f,
|
|
input io_ebreak_to_debug_mode_r_d1,
|
|
input io_debug_halt_req,
|
|
input io_allow_dbg_halt_csr_write,
|
|
input io_internal_dbg_halt_mode_f,
|
|
input io_enter_debug_halt_req,
|
|
input io_internal_dbg_halt_mode,
|
|
input io_request_debug_mode_done,
|
|
input io_request_debug_mode_r,
|
|
output [30:0] io_dpc,
|
|
input [3:0] io_update_hit_bit_r,
|
|
input io_take_timer_int,
|
|
input io_take_int_timer0_int,
|
|
input io_take_int_timer1_int,
|
|
input io_take_ext_int,
|
|
input io_tlu_flush_lower_r,
|
|
input io_dec_tlu_br0_error_r,
|
|
input io_dec_tlu_br0_start_error_r,
|
|
input io_lsu_pmu_load_external_r,
|
|
input io_lsu_pmu_store_external_r,
|
|
input io_csr_pkt_csr_misa,
|
|
input io_csr_pkt_csr_mvendorid,
|
|
input io_csr_pkt_csr_marchid,
|
|
input io_csr_pkt_csr_mimpid,
|
|
input io_csr_pkt_csr_mhartid,
|
|
input io_csr_pkt_csr_mstatus,
|
|
input io_csr_pkt_csr_mtvec,
|
|
input io_csr_pkt_csr_mip,
|
|
input io_csr_pkt_csr_mie,
|
|
input io_csr_pkt_csr_mcyclel,
|
|
input io_csr_pkt_csr_mcycleh,
|
|
input io_csr_pkt_csr_minstretl,
|
|
input io_csr_pkt_csr_minstreth,
|
|
input io_csr_pkt_csr_mscratch,
|
|
input io_csr_pkt_csr_mepc,
|
|
input io_csr_pkt_csr_mcause,
|
|
input io_csr_pkt_csr_mscause,
|
|
input io_csr_pkt_csr_mtval,
|
|
input io_csr_pkt_csr_mrac,
|
|
input io_csr_pkt_csr_mdseac,
|
|
input io_csr_pkt_csr_meihap,
|
|
input io_csr_pkt_csr_meivt,
|
|
input io_csr_pkt_csr_meipt,
|
|
input io_csr_pkt_csr_meicurpl,
|
|
input io_csr_pkt_csr_meicidpl,
|
|
input io_csr_pkt_csr_dcsr,
|
|
input io_csr_pkt_csr_mcgc,
|
|
input io_csr_pkt_csr_mfdc,
|
|
input io_csr_pkt_csr_dpc,
|
|
input io_csr_pkt_csr_mtsel,
|
|
input io_csr_pkt_csr_mtdata1,
|
|
input io_csr_pkt_csr_mtdata2,
|
|
input io_csr_pkt_csr_mhpmc3,
|
|
input io_csr_pkt_csr_mhpmc4,
|
|
input io_csr_pkt_csr_mhpmc5,
|
|
input io_csr_pkt_csr_mhpmc6,
|
|
input io_csr_pkt_csr_mhpmc3h,
|
|
input io_csr_pkt_csr_mhpmc4h,
|
|
input io_csr_pkt_csr_mhpmc5h,
|
|
input io_csr_pkt_csr_mhpmc6h,
|
|
input io_csr_pkt_csr_mhpme3,
|
|
input io_csr_pkt_csr_mhpme4,
|
|
input io_csr_pkt_csr_mhpme5,
|
|
input io_csr_pkt_csr_mhpme6,
|
|
input io_csr_pkt_csr_mcountinhibit,
|
|
input io_csr_pkt_csr_mpmc,
|
|
input io_csr_pkt_csr_micect,
|
|
input io_csr_pkt_csr_miccmect,
|
|
input io_csr_pkt_csr_mdccmect,
|
|
input io_csr_pkt_csr_mfdht,
|
|
input io_csr_pkt_csr_mfdhs,
|
|
input io_csr_pkt_csr_dicawics,
|
|
input io_csr_pkt_csr_dicad0h,
|
|
input io_csr_pkt_csr_dicad0,
|
|
input io_csr_pkt_csr_dicad1,
|
|
output [9:0] io_mtdata1_t_0,
|
|
output [9:0] io_mtdata1_t_1,
|
|
output [9:0] io_mtdata1_t_2,
|
|
output [9:0] io_mtdata1_t_3,
|
|
input [3:0] io_trigger_enabled
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire perfmux_flop_reset; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [6:0] perfmux_flop_io_mcountinhibit; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [9:0] perfmux_flop_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [9:0] perfmux_flop_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [9:0] perfmux_flop_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [9:0] perfmux_flop_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_illegal_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [3:0] perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [1:0] perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [5:0] perfmux_flop_io_mie; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_timer_int; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_ext_int; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_minstret_enable_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [3:0] perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [5:0] perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_take_ext_int_start; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_ext_int_freeze; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [5:0] perfmux_flop_io_mip_ns; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mcyclel_cout; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_minstret_enable; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_minstretl_cout_ns; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [3:0] perfmux_flop_io_meicidpl_ns; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_icache_rd_valid; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_icache_wr_valid; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_perfcnt_halted; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire [1:0] perfmux_flop_io_mstatus_ns; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perfmux_flop_io_free_l2clk; // @[dec_tlu_ctl.scala 1455:34]
|
|
wire perf_csrs_clock; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_reset; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_free_l2clk; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [15:0] perf_csrs_io_dcsr; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [11:0] perf_csrs_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [31:0] perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire [9:0] perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 1456:31]
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_en; // @[lib.scala 422:23]
|
|
wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1472:52]
|
|
wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1472:50]
|
|
wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1472:75]
|
|
wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1473:78]
|
|
wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1473:49]
|
|
wire _T_553 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1883:69]
|
|
wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_553; // @[dec_tlu_ctl.scala 1883:46]
|
|
wire _T_565 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1891:44]
|
|
reg mpmc_b; // @[dec_tlu_ctl.scala 1893:51]
|
|
wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1896:17]
|
|
wire _T_566 = ~mpmc; // @[dec_tlu_ctl.scala 1891:69]
|
|
wire mpmc_b_ns = wr_mpmc_r ? _T_565 : _T_566; // @[dec_tlu_ctl.scala 1891:25]
|
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wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1476:35]
|
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wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1476:46]
|
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wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1479:18]
|
|
wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1479:32]
|
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wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58]
|
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wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1480:31]
|
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wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58]
|
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wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1481:30]
|
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wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1481:28]
|
|
wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58]
|
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wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58]
|
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wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1483:31]
|
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wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58]
|
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wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1484:32]
|
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wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1484:59]
|
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wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1484:57]
|
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wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1484:72]
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wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1484:70]
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wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_42 = set_mie_pmu_fw_halt ? _T_24 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_43 = _T_26 ? _T_30 : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_44 = _T_37 ? io_mstatus : 2'h0; // @[Mux.scala 27:72]
|
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wire [1:0] _T_45 = _T_39 | _T_40; // @[Mux.scala 27:72]
|
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wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72]
|
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wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72]
|
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wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72]
|
|
wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1489:57]
|
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wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1489:88]
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wire _T_57 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1500:76]
|
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wire wr_mtvec_r = io_dec_csr_wen_r_mod & _T_57; // @[dec_tlu_ctl.scala 1500:47]
|
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wire [30:0] mtvec_ns = {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; // @[Cat.scala 29:58]
|
|
reg [30:0] _T_61; // @[Reg.scala 27:20]
|
|
reg [31:0] mdccmect; // @[Reg.scala 27:20]
|
|
wire [62:0] _T_629 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1942:48]
|
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wire [31:0] _T_631 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58]
|
|
wire [62:0] _GEN_43 = {{31'd0}, _T_631}; // @[dec_tlu_ctl.scala 1942:68]
|
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wire [62:0] _T_632 = _T_629 & _GEN_43; // @[dec_tlu_ctl.scala 1942:68]
|
|
wire mdccme_ce_req = |_T_632; // @[dec_tlu_ctl.scala 1942:101]
|
|
reg [31:0] miccmect; // @[Reg.scala 27:20]
|
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wire [62:0] _T_609 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1928:48]
|
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wire [31:0] _T_611 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58]
|
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wire [62:0] _GEN_44 = {{31'd0}, _T_611}; // @[dec_tlu_ctl.scala 1928:68]
|
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wire [62:0] _T_612 = _T_609 & _GEN_44; // @[dec_tlu_ctl.scala 1928:68]
|
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wire miccme_ce_req = |_T_612; // @[dec_tlu_ctl.scala 1928:101]
|
|
wire _T_62 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1514:37]
|
|
reg [31:0] micect; // @[Reg.scala 27:20]
|
|
wire [62:0] _T_587 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1913:46]
|
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wire [31:0] _T_589 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58]
|
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wire [62:0] _GEN_45 = {{31'd0}, _T_589}; // @[dec_tlu_ctl.scala 1913:64]
|
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wire [62:0] _T_590 = _T_587 & _GEN_45; // @[dec_tlu_ctl.scala 1913:64]
|
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wire mice_ce_req = |_T_590; // @[dec_tlu_ctl.scala 1913:95]
|
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wire ce_int = _T_62 | mice_ce_req; // @[dec_tlu_ctl.scala 1514:53]
|
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wire [2:0] _T_64 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58]
|
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wire [2:0] _T_66 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58]
|
|
wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1530:74]
|
|
wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[dec_tlu_ctl.scala 1530:45]
|
|
wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58]
|
|
reg [5:0] mie; // @[dec_tlu_ctl.scala 1533:24]
|
|
wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1539:61]
|
|
wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1541:78]
|
|
wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[dec_tlu_ctl.scala 1541:49]
|
|
wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1543:78]
|
|
wire _T_84 = kill_ebreak_count_r | _T_83; // @[dec_tlu_ctl.scala 1543:53]
|
|
wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1543:101]
|
|
reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20]
|
|
wire [5:0] _T_1138 = {temp_ncount6_2,1'h0}; // @[Cat.scala 29:58]
|
|
reg temp_ncount0; // @[Reg.scala 27:20]
|
|
wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
|
|
wire _T_87 = _T_85 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1543:128]
|
|
wire mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 1543:31]
|
|
reg [23:0] _T_106; // @[Reg.scala 27:20]
|
|
reg [7:0] _T_110; // @[Reg.scala 27:20]
|
|
wire [31:0] mcyclel = {_T_106,_T_110}; // @[Cat.scala 29:58]
|
|
wire [8:0] mcyclel_inc1 = mcyclel[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1548:38]
|
|
wire [23:0] _T_93 = {23'h0,mcyclel_inc1[8]}; // @[Cat.scala 29:58]
|
|
wire [24:0] mcyclel_inc2 = mcyclel[31:8] + _T_93; // @[dec_tlu_ctl.scala 1549:39]
|
|
wire [31:0] mcyclel_inc = {mcyclel_inc2[23:0],mcyclel_inc1[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] mcyclel_ns = wr_mcyclel_r ? io_dec_csr_wrdata_r : mcyclel_inc; // @[dec_tlu_ctl.scala 1551:29]
|
|
wire _T_102 = mcyclel_inc1[8] & mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:82]
|
|
wire _T_104 = wr_mcyclel_r | _T_102; // @[dec_tlu_ctl.scala 1553:63]
|
|
wire _T_108 = wr_mcyclel_r | mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:184]
|
|
wire _T_113 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1560:78]
|
|
wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 1560:49]
|
|
wire [31:0] _T_114 = {31'h0,perfmux_flop_io_mcyclel_cout_f}; // @[Cat.scala 29:58]
|
|
reg [31:0] mcycleh; // @[Reg.scala 27:20]
|
|
wire [31:0] mcycleh_inc = mcycleh + _T_114; // @[dec_tlu_ctl.scala 1562:35]
|
|
wire _T_117 = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1565:53]
|
|
wire _T_120 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1579:81]
|
|
wire _T_121 = _T_120 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1579:94]
|
|
wire _T_122 = _T_121 | io_illegal_r; // @[dec_tlu_ctl.scala 1579:122]
|
|
wire _T_124 = _T_122 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1579:137]
|
|
wire _T_125 = ~_T_124; // @[dec_tlu_ctl.scala 1579:67]
|
|
wire i0_valid_no_ebreak_ecall_r = io_dec_tlu_i0_valid_r & _T_125; // @[dec_tlu_ctl.scala 1579:65]
|
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wire _T_128 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1581:80]
|
|
wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1581:51]
|
|
reg [23:0] _T_150; // @[Reg.scala 27:20]
|
|
reg [7:0] _T_153; // @[Reg.scala 27:20]
|
|
wire [31:0] minstretl = {_T_150,_T_153}; // @[Cat.scala 29:58]
|
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wire [8:0] minstretl_inc1 = minstretl[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1585:42]
|
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wire [23:0] _T_134 = {23'h0,minstretl_inc1[8]}; // @[Cat.scala 29:58]
|
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wire [24:0] minstretl_inc2 = minstretl[31:8] + _T_134; // @[dec_tlu_ctl.scala 1586:43]
|
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wire minstretl_cout = minstretl_inc2[24]; // @[dec_tlu_ctl.scala 1587:44]
|
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wire [31:0] minstretl_inc = {minstretl_inc2[23:0],minstretl_inc1[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_138 = i0_valid_no_ebreak_ecall_r & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1589:59]
|
|
wire minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 1589:83]
|
|
wire _T_156 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1605:78]
|
|
wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_156; // @[dec_tlu_ctl.scala 1605:49]
|
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wire _T_139 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1590:50]
|
|
wire _T_140 = minstretl_cout & _T_139; // @[dec_tlu_ctl.scala 1590:48]
|
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wire _T_141 = _T_140 & i0_valid_no_ebreak_ecall_r; // @[dec_tlu_ctl.scala 1590:66]
|
|
wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1590:97]
|
|
wire [31:0] minstretl_ns = wr_minstretl_r ? io_dec_csr_wrdata_r : minstretl_inc; // @[dec_tlu_ctl.scala 1593:31]
|
|
wire _T_147 = minstretl_inc1[8] & minstret_enable; // @[dec_tlu_ctl.scala 1595:88]
|
|
wire _T_148 = wr_minstretl_r | _T_147; // @[dec_tlu_ctl.scala 1595:67]
|
|
wire [31:0] _T_159 = {31'h0,perfmux_flop_io_minstretl_cout_f}; // @[Cat.scala 29:58]
|
|
reg [31:0] minstreth; // @[Reg.scala 27:20]
|
|
wire [31:0] minstreth_inc = minstreth + _T_159; // @[dec_tlu_ctl.scala 1609:39]
|
|
wire _T_162 = perfmux_flop_io_minstret_enable_f & perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1612:79]
|
|
wire _T_163 = _T_162 | wr_minstreth_r; // @[dec_tlu_ctl.scala 1612:116]
|
|
wire _T_167 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1620:79]
|
|
wire wr_mscratch_r = io_dec_csr_wen_r_mod & _T_167; // @[dec_tlu_ctl.scala 1620:50]
|
|
reg [31:0] mscratch; // @[Reg.scala 27:20]
|
|
wire _T_171 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1631:54]
|
|
wire _T_172 = _T_142 & _T_171; // @[dec_tlu_ctl.scala 1631:52]
|
|
wire sel_exu_npc_r = _T_172 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1631:79]
|
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wire _T_174 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1632:54]
|
|
wire _T_175 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1632:82]
|
|
wire sel_flush_npc_r = _T_174 & _T_175; // @[dec_tlu_ctl.scala 1632:80]
|
|
wire _T_176 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1633:30]
|
|
wire _T_177 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1633:47]
|
|
wire sel_hold_npc_r = _T_176 & _T_177; // @[dec_tlu_ctl.scala 1633:45]
|
|
wire _T_179 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1637:18]
|
|
wire _T_180 = _T_179 & io_reset_delayed; // @[dec_tlu_ctl.scala 1637:40]
|
|
wire [30:0] _T_184 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_185 = _T_180 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_186 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_187 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_188 = _T_184 | _T_185; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_189 = _T_188 | _T_186; // @[Mux.scala 27:72]
|
|
wire _T_192 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1641:58]
|
|
wire _T_193 = _T_192 | io_reset_delayed; // @[dec_tlu_ctl.scala 1641:76]
|
|
reg [30:0] _T_196; // @[Reg.scala 27:20]
|
|
wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1644:51]
|
|
wire _T_199 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1648:17]
|
|
wire [30:0] _T_200 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
reg [30:0] pc_r_d1; // @[Reg.scala 27:20]
|
|
wire [30:0] _T_201 = _T_199 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] pc_r = _T_200 | _T_201; // @[Mux.scala 27:72]
|
|
wire _T_206 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1652:75]
|
|
wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_206; // @[dec_tlu_ctl.scala 1652:46]
|
|
wire _T_207 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1655:42]
|
|
wire _T_208 = _T_207 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1655:63]
|
|
wire _T_212 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1657:28]
|
|
wire _T_215 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1658:18]
|
|
wire _T_217 = _T_215 & _T_17; // @[dec_tlu_ctl.scala 1658:29]
|
|
wire [30:0] _T_219 = _T_208 ? pc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_220 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_221 = _T_212 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_222 = _T_217 ? io_mepc : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_223 = _T_219 | _T_220; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_224 = _T_223 | _T_221; // @[Mux.scala 27:72]
|
|
wire [30:0] mepc_ns = _T_224 | _T_222; // @[Mux.scala 27:72]
|
|
wire _T_228 = _T_208 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1660:111]
|
|
wire _T_229 = _T_228 | wr_mepc_r; // @[dec_tlu_ctl.scala 1660:134]
|
|
reg [30:0] _T_231; // @[Reg.scala 27:20]
|
|
wire _T_233 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1668:77]
|
|
wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_233; // @[dec_tlu_ctl.scala 1668:48]
|
|
wire _T_234 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1669:58]
|
|
wire mcause_sel_nmi_store = _T_234 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1669:72]
|
|
wire mcause_sel_nmi_load = _T_234 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1670:71]
|
|
wire _T_237 = _T_234 & io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1671:69]
|
|
wire _T_238 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1671:115]
|
|
wire _T_239 = _T_237 & _T_238; // @[dec_tlu_ctl.scala 1671:96]
|
|
wire _T_240 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1671:121]
|
|
wire mcause_sel_nmi_ext = _T_239 & _T_240; // @[dec_tlu_ctl.scala 1671:119]
|
|
wire _T_241 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1678:58]
|
|
wire _T_244 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1678:87]
|
|
wire _T_245 = io_lsu_fir_error[1] & _T_244; // @[dec_tlu_ctl.scala 1678:85]
|
|
wire [31:0] _T_250 = {30'h3c000400,_T_241,_T_245}; // @[Cat.scala 29:58]
|
|
wire _T_251 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1684:42]
|
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wire _T_252 = io_exc_or_int_valid_r & _T_251; // @[dec_tlu_ctl.scala 1684:40]
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wire [31:0] _T_255 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58]
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wire _T_257 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1685:30]
|
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wire _T_259 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1686:18]
|
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wire _T_261 = _T_259 & _T_17; // @[dec_tlu_ctl.scala 1686:31]
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wire [31:0] _T_263 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_264 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_265 = mcause_sel_nmi_ext ? _T_250 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_266 = _T_252 ? _T_255 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_267 = _T_257 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] mcause; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_268 = _T_261 ? mcause : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_269 = _T_263 | _T_264; // @[Mux.scala 27:72]
|
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wire [31:0] _T_270 = _T_269 | _T_265; // @[Mux.scala 27:72]
|
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wire [31:0] _T_271 = _T_270 | _T_266; // @[Mux.scala 27:72]
|
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wire [31:0] _T_272 = _T_271 | _T_267; // @[Mux.scala 27:72]
|
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wire [31:0] mcause_ns = _T_272 | _T_268; // @[Mux.scala 27:72]
|
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wire _T_274 = io_exc_or_int_valid_r | wr_mcause_r; // @[dec_tlu_ctl.scala 1688:58]
|
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wire _T_278 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1695:78]
|
|
wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_278; // @[dec_tlu_ctl.scala 1695:49]
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wire _T_279 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1697:63]
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wire [3:0] _T_280 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58]
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wire [3:0] ifu_mscause = _T_279 ? 4'h9 : _T_280; // @[dec_tlu_ctl.scala 1697:31]
|
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wire [3:0] _T_285 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_286 = io_i0_trigger_hit_r ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_287 = io_ebreak_r ? 4'h2 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_288 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72]
|
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wire [3:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72]
|
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wire [3:0] mscause_type = _T_290 | _T_288; // @[Mux.scala 27:72]
|
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wire _T_294 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1708:31]
|
|
wire _T_297 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1709:18]
|
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wire _T_299 = _T_297 & _T_17; // @[dec_tlu_ctl.scala 1709:32]
|
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wire [3:0] _T_301 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_302 = _T_294 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72]
|
|
reg [3:0] mscause; // @[dec_tlu_ctl.scala 1711:54]
|
|
wire [3:0] _T_303 = _T_299 ? mscause : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_304 = _T_301 | _T_302; // @[Mux.scala 27:72]
|
|
wire _T_308 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1718:76]
|
|
wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_308; // @[dec_tlu_ctl.scala 1718:47]
|
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wire _T_309 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1719:90]
|
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wire _T_310 = io_inst_acc_r & _T_309; // @[dec_tlu_ctl.scala 1719:88]
|
|
wire _T_311 = io_ebreak_r | _T_310; // @[dec_tlu_ctl.scala 1719:71]
|
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wire _T_312 = _T_311 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1719:113]
|
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wire _T_313 = io_exc_or_int_valid_r & _T_312; // @[dec_tlu_ctl.scala 1719:56]
|
|
wire mtval_capture_pc_r = _T_313 & _T_251; // @[dec_tlu_ctl.scala 1719:145]
|
|
wire _T_315 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1720:79]
|
|
wire _T_316 = io_exc_or_int_valid_r & _T_315; // @[dec_tlu_ctl.scala 1720:62]
|
|
wire mtval_capture_pc_plus2_r = _T_316 & _T_251; // @[dec_tlu_ctl.scala 1720:103]
|
|
wire _T_318 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1721:58]
|
|
wire mtval_capture_inst_r = _T_318 & _T_251; // @[dec_tlu_ctl.scala 1721:73]
|
|
wire _T_320 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1722:57]
|
|
wire mtval_capture_lsu_r = _T_320 & _T_251; // @[dec_tlu_ctl.scala 1722:78]
|
|
wire _T_322 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1723:53]
|
|
wire _T_323 = io_exc_or_int_valid_r & _T_322; // @[dec_tlu_ctl.scala 1723:51]
|
|
wire _T_324 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1723:75]
|
|
wire _T_325 = _T_323 & _T_324; // @[dec_tlu_ctl.scala 1723:73]
|
|
wire _T_326 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1723:99]
|
|
wire _T_327 = _T_325 & _T_326; // @[dec_tlu_ctl.scala 1723:97]
|
|
wire _T_328 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1723:122]
|
|
wire mtval_clear_r = _T_327 & _T_328; // @[dec_tlu_ctl.scala 1723:120]
|
|
wire [31:0] _T_330 = {pc_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [30:0] _T_333 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1728:96]
|
|
wire [31:0] _T_334 = {_T_333,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_337 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1731:31]
|
|
wire _T_338 = wr_mtval_r & _T_337; // @[dec_tlu_ctl.scala 1731:29]
|
|
wire _T_341 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1732:33]
|
|
wire _T_342 = _T_251 & _T_341; // @[dec_tlu_ctl.scala 1732:31]
|
|
wire _T_344 = _T_342 & _T_322; // @[dec_tlu_ctl.scala 1732:45]
|
|
wire _T_346 = _T_344 & _T_324; // @[dec_tlu_ctl.scala 1732:67]
|
|
wire _T_347 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1732:93]
|
|
wire _T_348 = _T_346 & _T_347; // @[dec_tlu_ctl.scala 1732:91]
|
|
wire _T_350 = _T_348 & _T_326; // @[dec_tlu_ctl.scala 1732:108]
|
|
wire [31:0] _T_352 = mtval_capture_pc_r ? _T_330 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_353 = mtval_capture_pc_plus2_r ? _T_334 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_354 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_355 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_356 = _T_338 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72]
|
|
reg [31:0] mtval; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_357 = _T_350 ? mtval : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_361 = _T_360 | _T_356; // @[Mux.scala 27:72]
|
|
wire [31:0] mtval_ns = _T_361 | _T_357; // @[Mux.scala 27:72]
|
|
wire _T_363 = io_tlu_flush_lower_r | wr_mtval_r; // @[dec_tlu_ctl.scala 1734:55]
|
|
wire _T_367 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1752:75]
|
|
wire wr_mcgc_r = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1752:46]
|
|
wire _T_370 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1753:42]
|
|
wire [9:0] _T_372 = {_T_370,io_dec_csr_wrdata_r[8:0]}; // @[Cat.scala 29:58]
|
|
reg [9:0] mcgc_int; // @[Reg.scala 27:20]
|
|
wire _T_376 = ~mcgc_int[9]; // @[dec_tlu_ctl.scala 1755:24]
|
|
wire [9:0] mcgc = {_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58]
|
|
wire _T_388 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1785:75]
|
|
wire wr_mfdc_r = io_dec_csr_wen_r_mod & _T_388; // @[dec_tlu_ctl.scala 1785:46]
|
|
reg [15:0] mfdc_int; // @[Reg.scala 27:20]
|
|
wire [2:0] _T_392 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1795:32]
|
|
wire _T_396 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1795:111]
|
|
wire [15:0] mfdc_ns = {_T_392,io_dec_csr_wrdata_r[12],io_dec_csr_wrdata_r[11:7],_T_396,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58]
|
|
wire [2:0] _T_403 = ~mfdc_int[15:13]; // @[dec_tlu_ctl.scala 1796:32]
|
|
wire _T_407 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1796:88]
|
|
wire [18:0] mfdc = {_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58]
|
|
wire _T_423 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1822:84]
|
|
wire _T_424 = io_dec_csr_wen_r_mod & _T_423; // @[dec_tlu_ctl.scala 1822:55]
|
|
wire _T_426 = _T_424 & _T_337; // @[dec_tlu_ctl.scala 1822:94]
|
|
wire _T_427 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1822:120]
|
|
wire _T_430 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1829:75]
|
|
wire wr_mrac_r = io_dec_csr_wen_r_mod & _T_430; // @[dec_tlu_ctl.scala 1829:46]
|
|
wire _T_434 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1832:78]
|
|
wire _T_435 = io_dec_csr_wrdata_r[30] & _T_434; // @[dec_tlu_ctl.scala 1832:76]
|
|
wire _T_439 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1833:68]
|
|
wire _T_440 = io_dec_csr_wrdata_r[28] & _T_439; // @[dec_tlu_ctl.scala 1833:66]
|
|
wire _T_444 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1834:68]
|
|
wire _T_445 = io_dec_csr_wrdata_r[26] & _T_444; // @[dec_tlu_ctl.scala 1834:66]
|
|
wire _T_449 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1835:68]
|
|
wire _T_450 = io_dec_csr_wrdata_r[24] & _T_449; // @[dec_tlu_ctl.scala 1835:66]
|
|
wire _T_454 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1836:68]
|
|
wire _T_455 = io_dec_csr_wrdata_r[22] & _T_454; // @[dec_tlu_ctl.scala 1836:66]
|
|
wire _T_459 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1837:68]
|
|
wire _T_460 = io_dec_csr_wrdata_r[20] & _T_459; // @[dec_tlu_ctl.scala 1837:66]
|
|
wire _T_464 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1838:68]
|
|
wire _T_465 = io_dec_csr_wrdata_r[18] & _T_464; // @[dec_tlu_ctl.scala 1838:66]
|
|
wire _T_469 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1839:68]
|
|
wire _T_470 = io_dec_csr_wrdata_r[16] & _T_469; // @[dec_tlu_ctl.scala 1839:66]
|
|
wire _T_474 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1840:68]
|
|
wire _T_475 = io_dec_csr_wrdata_r[14] & _T_474; // @[dec_tlu_ctl.scala 1840:66]
|
|
wire _T_479 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1841:68]
|
|
wire _T_480 = io_dec_csr_wrdata_r[12] & _T_479; // @[dec_tlu_ctl.scala 1841:66]
|
|
wire _T_484 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1842:68]
|
|
wire _T_485 = io_dec_csr_wrdata_r[10] & _T_484; // @[dec_tlu_ctl.scala 1842:66]
|
|
wire _T_490 = io_dec_csr_wrdata_r[8] & _T_370; // @[dec_tlu_ctl.scala 1843:65]
|
|
wire _T_494 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1844:68]
|
|
wire _T_495 = io_dec_csr_wrdata_r[6] & _T_494; // @[dec_tlu_ctl.scala 1844:65]
|
|
wire _T_499 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1845:68]
|
|
wire _T_500 = io_dec_csr_wrdata_r[4] & _T_499; // @[dec_tlu_ctl.scala 1845:65]
|
|
wire _T_504 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1846:68]
|
|
wire _T_505 = io_dec_csr_wrdata_r[2] & _T_504; // @[dec_tlu_ctl.scala 1846:65]
|
|
wire _T_510 = io_dec_csr_wrdata_r[0] & _T_565; // @[dec_tlu_ctl.scala 1847:65]
|
|
wire [7:0] _T_517 = {io_dec_csr_wrdata_r[7],_T_495,io_dec_csr_wrdata_r[5],_T_500,io_dec_csr_wrdata_r[3],_T_505,io_dec_csr_wrdata_r[1],_T_510}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_525 = {io_dec_csr_wrdata_r[15],_T_475,io_dec_csr_wrdata_r[13],_T_480,io_dec_csr_wrdata_r[11],_T_485,io_dec_csr_wrdata_r[9],_T_490,_T_517}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_532 = {io_dec_csr_wrdata_r[23],_T_455,io_dec_csr_wrdata_r[21],_T_460,io_dec_csr_wrdata_r[19],_T_465,io_dec_csr_wrdata_r[17],_T_470}; // @[Cat.scala 29:58]
|
|
wire [31:0] mrac_in = {io_dec_csr_wrdata_r[31],_T_435,io_dec_csr_wrdata_r[29],_T_440,io_dec_csr_wrdata_r[27],_T_445,io_dec_csr_wrdata_r[25],_T_450,_T_532,_T_525}; // @[Cat.scala 29:58]
|
|
reg [31:0] mrac; // @[Reg.scala 27:20]
|
|
wire _T_543 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1860:76]
|
|
wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_543; // @[dec_tlu_ctl.scala 1860:47]
|
|
wire _T_544 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1870:66]
|
|
wire _T_545 = io_mdseac_locked_f & _T_544; // @[dec_tlu_ctl.scala 1870:64]
|
|
wire _T_547 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1872:56]
|
|
wire _T_549 = _T_547 & _T_240; // @[dec_tlu_ctl.scala 1872:91]
|
|
wire _T_550 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1872:118]
|
|
wire mdseac_en = _T_549 & _T_550; // @[dec_tlu_ctl.scala 1872:116]
|
|
reg [31:0] mdseac; // @[Reg.scala 27:20]
|
|
wire _T_555 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1887:37]
|
|
wire _T_556 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1887:64]
|
|
wire _T_557 = _T_555 & _T_556; // @[dec_tlu_ctl.scala 1887:62]
|
|
wire _T_558 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1887:96]
|
|
wire _T_571 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1905:55]
|
|
wire [4:0] csr_sat = _T_571 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1905:26]
|
|
wire _T_573 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1907:71]
|
|
wire wr_micect_r = io_dec_csr_wen_r_mod & _T_573; // @[dec_tlu_ctl.scala 1907:48]
|
|
wire [26:0] _T_575 = {26'h0,io_ic_perr_r}; // @[Cat.scala 29:58]
|
|
wire [26:0] micect_inc = micect[26:0] + _T_575; // @[dec_tlu_ctl.scala 1908:36]
|
|
wire [31:0] _T_580 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_582 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58]
|
|
wire _T_583 = wr_micect_r | io_ic_perr_r; // @[dec_tlu_ctl.scala 1911:49]
|
|
wire _T_593 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1922:83]
|
|
wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_593; // @[dec_tlu_ctl.scala 1922:54]
|
|
wire _T_595 = io_iccm_sbecc_r | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1923:74]
|
|
wire [26:0] _T_596 = {26'h0,_T_595}; // @[Cat.scala 29:58]
|
|
wire [26:0] miccmect_inc = miccmect[26:0] + _T_596; // @[dec_tlu_ctl.scala 1923:40]
|
|
wire [31:0] _T_603 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58]
|
|
wire _T_604 = wr_miccmect_r | io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 1926:55]
|
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wire _T_605 = _T_604 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1926:73]
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wire _T_615 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1937:83]
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wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_615; // @[dec_tlu_ctl.scala 1937:54]
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wire [26:0] _T_617 = {26'h0,perfmux_flop_io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58]
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wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_617; // @[dec_tlu_ctl.scala 1938:40]
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wire [31:0] _T_624 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58]
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wire _T_625 = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1941:56]
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wire _T_635 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1952:76]
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wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1952:47]
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reg [5:0] mfdht; // @[Reg.scala 27:20]
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wire _T_641 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1965:76]
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wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_641; // @[dec_tlu_ctl.scala 1965:47]
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wire _T_644 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1968:42]
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wire _T_645 = io_dbg_tlu_halted & _T_644; // @[dec_tlu_ctl.scala 1968:40]
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wire _T_647 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1968:77]
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wire _T_648 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1968:97]
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wire [1:0] _T_649 = {_T_647,_T_648}; // @[Cat.scala 29:58]
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reg [1:0] mfdhs; // @[Reg.scala 27:20]
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wire _T_651 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1970:76]
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reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20]
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wire [31:0] _T_656 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1972:81]
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wire [62:0] _T_663 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1977:78]
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wire [62:0] _GEN_46 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1977:55]
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wire [62:0] _T_664 = _GEN_46 & _T_663; // @[dec_tlu_ctl.scala 1977:55]
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wire _T_665 = |_T_664; // @[dec_tlu_ctl.scala 1977:94]
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wire _T_668 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1985:76]
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wire wr_meivt_r = io_dec_csr_wen_r_mod & _T_668; // @[dec_tlu_ctl.scala 1985:47]
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reg [21:0] meivt; // @[Reg.scala 27:20]
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wire _T_686 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 2036:76]
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wire _T_687 = io_dec_csr_wen_r_mod & _T_686; // @[dec_tlu_ctl.scala 2036:47]
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wire wr_meicpct_r = _T_687 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2036:90]
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reg [7:0] meihap; // @[Reg.scala 27:20]
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wire _T_674 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 2009:79]
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wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_674; // @[dec_tlu_ctl.scala 2009:50]
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reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 2012:53]
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wire _T_679 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 2024:80]
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wire _T_680 = io_dec_csr_wen_r_mod & _T_679; // @[dec_tlu_ctl.scala 2024:51]
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wire wr_meicidpl_r = _T_680 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2024:95]
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wire [3:0] _T_684 = wr_meicidpl_r ? io_dec_csr_wrdata_r[3:0] : perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2027:20]
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wire _T_690 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2045:76]
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wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_690; // @[dec_tlu_ctl.scala 2045:47]
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reg [3:0] meipt; // @[dec_tlu_ctl.scala 2048:50]
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wire _T_694 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2076:96]
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wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_694; // @[dec_tlu_ctl.scala 2076:73]
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wire _T_695 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2079:47]
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wire _T_696 = io_dcsr_single_step_done_f & _T_695; // @[dec_tlu_ctl.scala 2079:45]
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wire _T_697 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2079:79]
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wire _T_698 = _T_696 & _T_697; // @[dec_tlu_ctl.scala 2079:77]
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wire _T_699 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2079:114]
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wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2079:112]
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wire _T_703 = io_debug_halt_req & _T_695; // @[dec_tlu_ctl.scala 2080:36]
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wire _T_705 = _T_703 & _T_697; // @[dec_tlu_ctl.scala 2080:68]
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wire _T_708 = io_ebreak_to_debug_mode_r_d1 & _T_697; // @[dec_tlu_ctl.scala 2081:47]
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wire [2:0] _T_711 = _T_700 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_712 = _T_705 ? 3'h3 : 3'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_713 = _T_708 ? 3'h1 : 3'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_714 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_715 = _T_711 | _T_712; // @[Mux.scala 27:72]
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wire [2:0] _T_716 = _T_715 | _T_713; // @[Mux.scala 27:72]
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wire [2:0] dcsr_cause = _T_716 | _T_714; // @[Mux.scala 27:72]
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wire _T_718 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2084:53]
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wire _T_720 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2084:105]
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wire wr_dcsr_r = _T_718 & _T_720; // @[dec_tlu_ctl.scala 2084:76]
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wire _T_722 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2090:82]
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wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_722; // @[dec_tlu_ctl.scala 2090:66]
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wire _T_723 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2091:66]
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wire _T_724 = _T_723 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2091:85]
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wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_724; // @[dec_tlu_ctl.scala 2091:63]
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wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2093:55]
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wire [15:0] _T_730 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58]
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wire _T_736 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2095:158]
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wire [15:0] _T_745 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_736,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58]
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wire [15:0] _T_750 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58]
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wire _T_752 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2098:61]
|
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wire _T_753 = _T_752 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2098:73]
|
|
wire _T_754 = _T_753 | io_take_nmi; // @[dec_tlu_ctl.scala 2098:101]
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|
reg [15:0] _T_756; // @[Reg.scala 27:20]
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|
wire _T_759 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2106:104]
|
|
wire wr_dpc_r = _T_718 & _T_759; // @[dec_tlu_ctl.scala 2106:75]
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wire _T_762 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2107:74]
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wire dpc_capture_npc = _T_645 & _T_762; // @[dec_tlu_ctl.scala 2107:72]
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wire _T_763 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2111:18]
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wire _T_764 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2111:36]
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wire _T_765 = _T_763 & _T_764; // @[dec_tlu_ctl.scala 2111:34]
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wire _T_766 = _T_765 & wr_dpc_r; // @[dec_tlu_ctl.scala 2111:53]
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wire _T_771 = _T_763 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2113:34]
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wire [30:0] _T_773 = _T_766 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_774 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_775 = _T_771 ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_776 = _T_773 | _T_774; // @[Mux.scala 27:72]
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wire [30:0] dpc_ns = _T_776 | _T_775; // @[Mux.scala 27:72]
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wire _T_778 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2115:43]
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wire _T_779 = _T_778 | dpc_capture_npc; // @[dec_tlu_ctl.scala 2115:60]
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reg [30:0] _T_781; // @[Reg.scala 27:20]
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wire [16:0] dicawics_ns = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20],io_dec_csr_wrdata_r[16:3]}; // @[Cat.scala 29:58]
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wire _T_788 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2130:109]
|
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wire wr_dicawics_r = _T_718 & _T_788; // @[dec_tlu_ctl.scala 2130:80]
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reg [16:0] dicawics; // @[Reg.scala 27:20]
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wire _T_792 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2148:107]
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wire wr_dicad0_r = _T_718 & _T_792; // @[dec_tlu_ctl.scala 2148:78]
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wire _T_795 = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2151:53]
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reg [31:0] dicad0; // @[Reg.scala 27:20]
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wire _T_799 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2161:108]
|
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wire wr_dicad0h_r = _T_718 & _T_799; // @[dec_tlu_ctl.scala 2161:79]
|
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wire _T_802 = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2165:55]
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reg [31:0] dicad0h; // @[Reg.scala 27:20]
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wire _T_807 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2173:115]
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wire _T_808 = _T_718 & _T_807; // @[dec_tlu_ctl.scala 2173:86]
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wire _T_813 = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2177:61]
|
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reg [6:0] _T_815; // @[Reg.scala 27:20]
|
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wire [31:0] dicad1 = {25'h0,_T_815}; // @[Cat.scala 29:58]
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wire [38:0] _T_820 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58]
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wire _T_822 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2205:59]
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wire _T_823 = _T_822 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2205:82]
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wire _T_824 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2205:105]
|
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wire _T_825 = _T_823 & _T_824; // @[dec_tlu_ctl.scala 2205:103]
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wire _T_827 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2205:156]
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wire _T_830 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2206:111]
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wire _T_832 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2220:76]
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wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_832; // @[dec_tlu_ctl.scala 2220:47]
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reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2223:50]
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wire tdata_load = io_dec_csr_wrdata_r[0] & _T_464; // @[dec_tlu_ctl.scala 2258:49]
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wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_464; // @[dec_tlu_ctl.scala 2260:51]
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wire _T_843 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2262:53]
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wire tdata_action = _T_843 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2262:76]
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wire _T_851 = io_mtdata1_t_3[9] & _T_444; // @[dec_tlu_ctl.scala 2266:91]
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wire _T_852 = ~_T_851; // @[dec_tlu_ctl.scala 2266:58]
|
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wire _T_853 = io_dec_csr_wrdata_r[11] & _T_852; // @[dec_tlu_ctl.scala 2266:56]
|
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wire _T_858 = io_mtdata1_t_1[9] & _T_444; // @[dec_tlu_ctl.scala 2267:84]
|
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wire _T_859 = ~_T_858; // @[dec_tlu_ctl.scala 2267:51]
|
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wire _T_860 = io_dec_csr_wrdata_r[11] & _T_859; // @[dec_tlu_ctl.scala 2267:49]
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wire _T_861 = mtsel[1] ? _T_853 : _T_860; // @[dec_tlu_ctl.scala 2266:20]
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wire tdata_chain = mtsel[0] ? 1'h0 : _T_861; // @[dec_tlu_ctl.scala 2265:30]
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wire _T_865 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2270:73]
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wire _T_867 = _T_865 & io_mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 2270:105]
|
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wire _T_868 = io_dec_csr_wrdata_r[27] & _T_867; // @[dec_tlu_ctl.scala 2270:70]
|
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wire _T_871 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2271:44]
|
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wire _T_873 = _T_871 & io_mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 2271:76]
|
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wire _T_874 = io_dec_csr_wrdata_r[27] & _T_873; // @[dec_tlu_ctl.scala 2271:41]
|
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wire tdata_kill_write = mtsel[1] ? _T_868 : _T_874; // @[dec_tlu_ctl.scala 2270:35]
|
|
wire [9:0] tdata_wrdata_r = {_T_843,io_dec_csr_wrdata_r[20:19],tdata_action,tdata_chain,io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58]
|
|
wire _T_887 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2276:127]
|
|
wire _T_888 = io_dec_csr_wen_r_mod & _T_887; // @[dec_tlu_ctl.scala 2276:98]
|
|
wire _T_889 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2276:149]
|
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wire _T_890 = _T_888 & _T_889; // @[dec_tlu_ctl.scala 2276:140]
|
|
wire _T_893 = _T_871 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198]
|
|
wire wr_mtdata1_t_r_0 = _T_890 & _T_893; // @[dec_tlu_ctl.scala 2276:163]
|
|
wire _T_898 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2276:298]
|
|
wire _T_899 = _T_888 & _T_898; // @[dec_tlu_ctl.scala 2276:289]
|
|
wire _T_901 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2276:315]
|
|
wire _T_902 = _T_901 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347]
|
|
wire _T_903 = _T_899 & _T_902; // @[dec_tlu_ctl.scala 2276:312]
|
|
wire _T_904 = ~tdata_kill_write; // @[dec_tlu_ctl.scala 2276:373]
|
|
wire wr_mtdata1_t_r_1 = _T_903 & _T_904; // @[dec_tlu_ctl.scala 2276:371]
|
|
wire _T_909 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2276:149]
|
|
wire _T_910 = _T_888 & _T_909; // @[dec_tlu_ctl.scala 2276:140]
|
|
wire _T_913 = _T_865 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198]
|
|
wire wr_mtdata1_t_r_2 = _T_910 & _T_913; // @[dec_tlu_ctl.scala 2276:163]
|
|
wire _T_918 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2276:298]
|
|
wire _T_919 = _T_888 & _T_918; // @[dec_tlu_ctl.scala 2276:289]
|
|
wire _T_921 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2276:315]
|
|
wire _T_922 = _T_921 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347]
|
|
wire _T_923 = _T_919 & _T_922; // @[dec_tlu_ctl.scala 2276:312]
|
|
wire wr_mtdata1_t_r_3 = _T_923 & _T_904; // @[dec_tlu_ctl.scala 2276:371]
|
|
wire _T_930 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2278:148]
|
|
wire [9:0] _T_933 = {io_mtdata1_t_0[9],_T_930,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_939 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2278:148]
|
|
wire [9:0] _T_942 = {io_mtdata1_t_1[9],_T_939,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_948 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2278:148]
|
|
wire [9:0] _T_951 = {io_mtdata1_t_2[9],_T_948,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_957 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2278:148]
|
|
wire [9:0] _T_960 = {io_mtdata1_t_3[9],_T_957,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_963 = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[dec_tlu_ctl.scala 2282:95]
|
|
reg [9:0] _T_965; // @[Reg.scala 27:20]
|
|
wire _T_967 = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[dec_tlu_ctl.scala 2282:95]
|
|
reg [9:0] _T_969; // @[Reg.scala 27:20]
|
|
wire _T_971 = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[dec_tlu_ctl.scala 2282:95]
|
|
reg [9:0] _T_973; // @[Reg.scala 27:20]
|
|
wire _T_975 = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[dec_tlu_ctl.scala 2282:95]
|
|
reg [9:0] _T_977; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_992 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1007 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58]
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|
wire [31:0] _T_1022 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1037 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58]
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|
wire [31:0] _T_1038 = _T_889 ? _T_992 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1039 = _T_898 ? _T_1007 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1040 = _T_909 ? _T_1022 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1041 = _T_918 ? _T_1037 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1042 = _T_1038 | _T_1039; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1043 = _T_1042 | _T_1040; // @[Mux.scala 27:72]
|
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wire [31:0] mtdata1_tsel_out = _T_1043 | _T_1041; // @[Mux.scala 27:72]
|
|
wire _T_1070 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2299:105]
|
|
wire _T_1071 = io_dec_csr_wen_r_mod & _T_1070; // @[dec_tlu_ctl.scala 2299:76]
|
|
wire _T_1073 = _T_1071 & _T_889; // @[dec_tlu_ctl.scala 2299:118]
|
|
wire wr_mtdata2_t_r_0 = _T_1073 & _T_893; // @[dec_tlu_ctl.scala 2299:141]
|
|
wire _T_1082 = _T_1071 & _T_898; // @[dec_tlu_ctl.scala 2299:118]
|
|
wire wr_mtdata2_t_r_1 = _T_1082 & _T_902; // @[dec_tlu_ctl.scala 2299:141]
|
|
wire _T_1091 = _T_1071 & _T_909; // @[dec_tlu_ctl.scala 2299:118]
|
|
wire wr_mtdata2_t_r_2 = _T_1091 & _T_913; // @[dec_tlu_ctl.scala 2299:141]
|
|
wire _T_1100 = _T_1071 & _T_918; // @[dec_tlu_ctl.scala 2299:118]
|
|
wire wr_mtdata2_t_r_3 = _T_1100 & _T_922; // @[dec_tlu_ctl.scala 2299:141]
|
|
reg [31:0] mtdata2_t_0; // @[Reg.scala 27:20]
|
|
reg [31:0] mtdata2_t_1; // @[Reg.scala 27:20]
|
|
reg [31:0] mtdata2_t_2; // @[Reg.scala 27:20]
|
|
reg [31:0] mtdata2_t_3; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_1117 = _T_889 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1118 = _T_898 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1119 = _T_909 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1120 = _T_918 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1121 = _T_1117 | _T_1118; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1122 = _T_1121 | _T_1119; // @[Mux.scala 27:72]
|
|
wire [31:0] mtdata2_tsel_out = _T_1122 | _T_1120; // @[Mux.scala 27:72]
|
|
wire _T_1128 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2455:84]
|
|
wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_1128; // @[dec_tlu_ctl.scala 2455:55]
|
|
wire _T_1140 = ~io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 2468:42]
|
|
wire _T_1143 = io_i0_exception_valid_r_d1 | perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2469:98]
|
|
wire _T_1144 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2469:158]
|
|
wire _T_1145 = io_trigger_hit_r_d1 & _T_1144; // @[dec_tlu_ctl.scala 2469:156]
|
|
wire _T_1146 = _T_1143 | _T_1145; // @[dec_tlu_ctl.scala 2469:133]
|
|
wire [4:0] _T_1150 = _T_1140 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
|
wire [4:0] dec_tlu_exc_cause_wb1_raw = _T_1150 & io_exc_cause_wb; // @[dec_tlu_ctl.scala 2470:77]
|
|
wire dec_tlu_int_valid_wb1_raw = _T_1140 & io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2471:68]
|
|
reg [4:0] dec_tlu_exc_cause_wb2; // @[Reg.scala 27:20]
|
|
wire [4:0] _T_1152 = dec_tlu_exc_cause_wb1_raw ^ dec_tlu_exc_cause_wb2; // @[lib.scala 466:21]
|
|
wire _T_1153 = |_T_1152; // @[lib.scala 466:29]
|
|
reg dec_tlu_int_valid_wb2; // @[Reg.scala 27:20]
|
|
wire _T_1155 = dec_tlu_int_valid_wb1_raw ^ dec_tlu_int_valid_wb2; // @[lib.scala 488:21]
|
|
wire _T_1156 = |_T_1155; // @[lib.scala 488:29]
|
|
wire [31:0] _T_1164 = {io_core_id,4'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1173 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1178 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1191 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1204 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1216 = {io_mepc,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1221 = {28'h0,mscause}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1229 = {meivt,10'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1232 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1235 = {28'h0,meicurpl}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_1237 = perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2509:97]
|
|
wire [31:0] _T_1238 = {28'h0,_T_1237}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1241 = {28'h0,meipt}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1244 = {22'h0,_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1247 = {13'h0,_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1251 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1253 = {io_dpc,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1269 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1272 = {30'h0,mtsel}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1284 = perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 2525:77]
|
|
wire [31:0] _T_1286 = perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 2526:77]
|
|
wire [31:0] _T_1288 = perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 2527:77]
|
|
wire [31:0] _T_1290 = perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 2528:77]
|
|
wire [31:0] _T_1292 = perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 2529:78]
|
|
wire [31:0] _T_1294 = perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 2530:78]
|
|
wire [31:0] _T_1296 = perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 2531:78]
|
|
wire [31:0] _T_1298 = perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 2532:78]
|
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wire [31:0] _T_1301 = {26'h0,mfdht}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_1304 = {30'h0,mfdhs}; // @[Cat.scala 29:58]
|
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wire [9:0] _T_1306 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2535:92]
|
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wire [31:0] _T_1307 = {22'h0,_T_1306}; // @[Cat.scala 29:58]
|
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wire [9:0] _T_1309 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2536:92]
|
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wire [31:0] _T_1310 = {22'h0,_T_1309}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_1312 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2537:91]
|
|
wire [31:0] _T_1313 = {22'h0,_T_1312}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_1315 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2538:91]
|
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wire [31:0] _T_1316 = {22'h0,_T_1315}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_1319 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_1322 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58]
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wire [31:0] _T_1325 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1326 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1327 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1328 = io_csr_pkt_csr_mimpid ? 32'h3 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1329 = io_csr_pkt_csr_mhartid ? _T_1164 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1330 = io_csr_pkt_csr_mstatus ? _T_1173 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1331 = io_csr_pkt_csr_mtvec ? _T_1178 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1332 = io_csr_pkt_csr_mip ? _T_1191 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1333 = io_csr_pkt_csr_mie ? _T_1204 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1334 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1335 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1336 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1337 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1338 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1339 = io_csr_pkt_csr_mepc ? _T_1216 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1340 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1341 = io_csr_pkt_csr_mscause ? _T_1221 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1342 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1343 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1344 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1345 = io_csr_pkt_csr_meivt ? _T_1229 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1346 = io_csr_pkt_csr_meihap ? _T_1232 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1347 = io_csr_pkt_csr_meicurpl ? _T_1235 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1348 = io_csr_pkt_csr_meicidpl ? _T_1238 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1349 = io_csr_pkt_csr_meipt ? _T_1241 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1350 = io_csr_pkt_csr_mcgc ? _T_1244 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1351 = io_csr_pkt_csr_mfdc ? _T_1247 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1352 = io_csr_pkt_csr_dcsr ? _T_1251 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1353 = io_csr_pkt_csr_dpc ? _T_1253 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1354 = io_csr_pkt_csr_dicad0 ? dicad0 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1355 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1356 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_1357 = io_csr_pkt_csr_dicawics ? _T_1269 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1358 = io_csr_pkt_csr_mtsel ? _T_1272 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1359 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1360 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1361 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1362 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1363 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1364 = io_csr_pkt_csr_mhpmc3 ? _T_1284 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1365 = io_csr_pkt_csr_mhpmc4 ? _T_1286 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1366 = io_csr_pkt_csr_mhpmc5 ? _T_1288 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1367 = io_csr_pkt_csr_mhpmc6 ? _T_1290 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1368 = io_csr_pkt_csr_mhpmc3h ? _T_1292 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1369 = io_csr_pkt_csr_mhpmc4h ? _T_1294 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1370 = io_csr_pkt_csr_mhpmc5h ? _T_1296 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1371 = io_csr_pkt_csr_mhpmc6h ? _T_1298 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1372 = io_csr_pkt_csr_mfdht ? _T_1301 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1373 = io_csr_pkt_csr_mfdhs ? _T_1304 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1374 = io_csr_pkt_csr_mhpme3 ? _T_1307 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1375 = io_csr_pkt_csr_mhpme4 ? _T_1310 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1376 = io_csr_pkt_csr_mhpme5 ? _T_1313 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1377 = io_csr_pkt_csr_mhpme6 ? _T_1316 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1378 = io_csr_pkt_csr_mcountinhibit ? _T_1319 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1379 = io_csr_pkt_csr_mpmc ? _T_1322 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1380 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1381 = _T_1325 | _T_1326; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1382 = _T_1381 | _T_1327; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1383 = _T_1382 | _T_1328; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1384 = _T_1383 | _T_1329; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1385 = _T_1384 | _T_1330; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1386 = _T_1385 | _T_1331; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1387 = _T_1386 | _T_1332; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1388 = _T_1387 | _T_1333; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1389 = _T_1388 | _T_1334; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1390 = _T_1389 | _T_1335; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1391 = _T_1390 | _T_1336; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1392 = _T_1391 | _T_1337; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1393 = _T_1392 | _T_1338; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1394 = _T_1393 | _T_1339; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1395 = _T_1394 | _T_1340; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1396 = _T_1395 | _T_1341; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1397 = _T_1396 | _T_1342; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1398 = _T_1397 | _T_1343; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1399 = _T_1398 | _T_1344; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1400 = _T_1399 | _T_1345; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1401 = _T_1400 | _T_1346; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1402 = _T_1401 | _T_1347; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1403 = _T_1402 | _T_1348; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1404 = _T_1403 | _T_1349; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1405 = _T_1404 | _T_1350; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1406 = _T_1405 | _T_1351; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1407 = _T_1406 | _T_1352; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1408 = _T_1407 | _T_1353; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1409 = _T_1408 | _T_1354; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1410 = _T_1409 | _T_1355; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1411 = _T_1410 | _T_1356; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1412 = _T_1411 | _T_1357; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1413 = _T_1412 | _T_1358; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1414 = _T_1413 | _T_1359; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1415 = _T_1414 | _T_1360; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1416 = _T_1415 | _T_1361; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1417 = _T_1416 | _T_1362; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1418 = _T_1417 | _T_1363; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1419 = _T_1418 | _T_1364; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1420 = _T_1419 | _T_1365; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1421 = _T_1420 | _T_1366; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1422 = _T_1421 | _T_1367; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1423 = _T_1422 | _T_1368; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1424 = _T_1423 | _T_1369; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1425 = _T_1424 | _T_1370; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1426 = _T_1425 | _T_1371; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1427 = _T_1426 | _T_1372; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1428 = _T_1427 | _T_1373; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1429 = _T_1428 | _T_1374; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1430 = _T_1429 | _T_1375; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1431 = _T_1430 | _T_1376; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1432 = _T_1431 | _T_1377; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1433 = _T_1432 | _T_1378; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1434 = _T_1433 | _T_1379; // @[Mux.scala 27:72]
|
|
perf_mux_and_flops perfmux_flop ( // @[dec_tlu_ctl.scala 1455:34]
|
|
.reset(perfmux_flop_reset),
|
|
.io_mhpmc_inc_r_0(perfmux_flop_io_mhpmc_inc_r_0),
|
|
.io_mhpmc_inc_r_1(perfmux_flop_io_mhpmc_inc_r_1),
|
|
.io_mhpmc_inc_r_2(perfmux_flop_io_mhpmc_inc_r_2),
|
|
.io_mhpmc_inc_r_3(perfmux_flop_io_mhpmc_inc_r_3),
|
|
.io_mcountinhibit(perfmux_flop_io_mcountinhibit),
|
|
.io_mhpme_vec_0(perfmux_flop_io_mhpme_vec_0),
|
|
.io_mhpme_vec_1(perfmux_flop_io_mhpme_vec_1),
|
|
.io_mhpme_vec_2(perfmux_flop_io_mhpme_vec_2),
|
|
.io_mhpme_vec_3(perfmux_flop_io_mhpme_vec_3),
|
|
.io_ifu_pmu_ic_hit(perfmux_flop_io_ifu_pmu_ic_hit),
|
|
.io_ifu_pmu_ic_miss(perfmux_flop_io_ifu_pmu_ic_miss),
|
|
.io_tlu_i0_commit_cmt(perfmux_flop_io_tlu_i0_commit_cmt),
|
|
.io_illegal_r(perfmux_flop_io_illegal_r),
|
|
.io_exu_pmu_i0_pc4(perfmux_flop_io_exu_pmu_i0_pc4),
|
|
.io_ifu_pmu_instr_aligned(perfmux_flop_io_ifu_pmu_instr_aligned),
|
|
.io_dec_pmu_instr_decoded(perfmux_flop_io_dec_pmu_instr_decoded),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(perfmux_flop_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_exu_pmu_i0_br_misp(perfmux_flop_io_exu_pmu_i0_br_misp),
|
|
.io_dec_pmu_decode_stall(perfmux_flop_io_dec_pmu_decode_stall),
|
|
.io_exu_pmu_i0_br_ataken(perfmux_flop_io_exu_pmu_i0_br_ataken),
|
|
.io_ifu_pmu_fetch_stall(perfmux_flop_io_ifu_pmu_fetch_stall),
|
|
.io_dec_pmu_postsync_stall(perfmux_flop_io_dec_pmu_postsync_stall),
|
|
.io_dec_pmu_presync_stall(perfmux_flop_io_dec_pmu_presync_stall),
|
|
.io_lsu_store_stall_any(perfmux_flop_io_lsu_store_stall_any),
|
|
.io_dma_dccm_stall_any(perfmux_flop_io_dma_dccm_stall_any),
|
|
.io_dma_iccm_stall_any(perfmux_flop_io_dma_iccm_stall_any),
|
|
.io_i0_exception_valid_r(perfmux_flop_io_i0_exception_valid_r),
|
|
.io_dec_tlu_pmu_fw_halted(perfmux_flop_io_dec_tlu_pmu_fw_halted),
|
|
.io_dma_pmu_any_read(perfmux_flop_io_dma_pmu_any_read),
|
|
.io_dma_pmu_any_write(perfmux_flop_io_dma_pmu_any_write),
|
|
.io_dma_pmu_dccm_read(perfmux_flop_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_dccm_write(perfmux_flop_io_dma_pmu_dccm_write),
|
|
.io_lsu_pmu_load_external_r(perfmux_flop_io_lsu_pmu_load_external_r),
|
|
.io_lsu_pmu_store_external_r(perfmux_flop_io_lsu_pmu_store_external_r),
|
|
.io_mstatus(perfmux_flop_io_mstatus),
|
|
.io_mie(perfmux_flop_io_mie),
|
|
.io_ifu_pmu_bus_trxn(perfmux_flop_io_ifu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_trxn(perfmux_flop_io_lsu_pmu_bus_trxn),
|
|
.io_lsu_pmu_bus_misaligned(perfmux_flop_io_lsu_pmu_bus_misaligned),
|
|
.io_ifu_pmu_bus_error(perfmux_flop_io_ifu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_error(perfmux_flop_io_lsu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_busy(perfmux_flop_io_ifu_pmu_bus_busy),
|
|
.io_lsu_pmu_bus_busy(perfmux_flop_io_lsu_pmu_bus_busy),
|
|
.io_i0_trigger_hit_r(perfmux_flop_io_i0_trigger_hit_r),
|
|
.io_lsu_exc_valid_r(perfmux_flop_io_lsu_exc_valid_r),
|
|
.io_take_timer_int(perfmux_flop_io_take_timer_int),
|
|
.io_take_int_timer0_int(perfmux_flop_io_take_int_timer0_int),
|
|
.io_take_int_timer1_int(perfmux_flop_io_take_int_timer1_int),
|
|
.io_take_ext_int(perfmux_flop_io_take_ext_int),
|
|
.io_tlu_flush_lower_r(perfmux_flop_io_tlu_flush_lower_r),
|
|
.io_dec_tlu_br0_error_r(perfmux_flop_io_dec_tlu_br0_error_r),
|
|
.io_rfpc_i0_r(perfmux_flop_io_rfpc_i0_r),
|
|
.io_dec_tlu_br0_start_error_r(perfmux_flop_io_dec_tlu_br0_start_error_r),
|
|
.io_mcyclel_cout_f(perfmux_flop_io_mcyclel_cout_f),
|
|
.io_minstret_enable_f(perfmux_flop_io_minstret_enable_f),
|
|
.io_minstretl_cout_f(perfmux_flop_io_minstretl_cout_f),
|
|
.io_meicidpl(perfmux_flop_io_meicidpl),
|
|
.io_icache_rd_valid_f(perfmux_flop_io_icache_rd_valid_f),
|
|
.io_icache_wr_valid_f(perfmux_flop_io_icache_wr_valid_f),
|
|
.io_mhpmc_inc_r_d1_0(perfmux_flop_io_mhpmc_inc_r_d1_0),
|
|
.io_mhpmc_inc_r_d1_1(perfmux_flop_io_mhpmc_inc_r_d1_1),
|
|
.io_mhpmc_inc_r_d1_2(perfmux_flop_io_mhpmc_inc_r_d1_2),
|
|
.io_mhpmc_inc_r_d1_3(perfmux_flop_io_mhpmc_inc_r_d1_3),
|
|
.io_perfcnt_halted_d1(perfmux_flop_io_perfcnt_halted_d1),
|
|
.io_mdseac_locked_f(perfmux_flop_io_mdseac_locked_f),
|
|
.io_lsu_single_ecc_error_r_d1(perfmux_flop_io_lsu_single_ecc_error_r_d1),
|
|
.io_lsu_i0_exc_r_d1(perfmux_flop_io_lsu_i0_exc_r_d1),
|
|
.io_take_ext_int_start_d1(perfmux_flop_io_take_ext_int_start_d1),
|
|
.io_take_ext_int_start_d2(perfmux_flop_io_take_ext_int_start_d2),
|
|
.io_take_ext_int_start_d3(perfmux_flop_io_take_ext_int_start_d3),
|
|
.io_ext_int_freeze_d1(perfmux_flop_io_ext_int_freeze_d1),
|
|
.io_mip(perfmux_flop_io_mip),
|
|
.io_mdseac_locked_ns(perfmux_flop_io_mdseac_locked_ns),
|
|
.io_lsu_single_ecc_error_r(perfmux_flop_io_lsu_single_ecc_error_r),
|
|
.io_lsu_i0_exc_r(perfmux_flop_io_lsu_i0_exc_r),
|
|
.io_take_ext_int_start(perfmux_flop_io_take_ext_int_start),
|
|
.io_ext_int_freeze(perfmux_flop_io_ext_int_freeze),
|
|
.io_mip_ns(perfmux_flop_io_mip_ns),
|
|
.io_mcyclel_cout(perfmux_flop_io_mcyclel_cout),
|
|
.io_wr_mcycleh_r(perfmux_flop_io_wr_mcycleh_r),
|
|
.io_mcyclel_cout_in(perfmux_flop_io_mcyclel_cout_in),
|
|
.io_minstret_enable(perfmux_flop_io_minstret_enable),
|
|
.io_minstretl_cout_ns(perfmux_flop_io_minstretl_cout_ns),
|
|
.io_meicidpl_ns(perfmux_flop_io_meicidpl_ns),
|
|
.io_icache_rd_valid(perfmux_flop_io_icache_rd_valid),
|
|
.io_icache_wr_valid(perfmux_flop_io_icache_wr_valid),
|
|
.io_perfcnt_halted(perfmux_flop_io_perfcnt_halted),
|
|
.io_mstatus_ns(perfmux_flop_io_mstatus_ns),
|
|
.io_free_l2clk(perfmux_flop_io_free_l2clk)
|
|
);
|
|
perf_csr perf_csrs ( // @[dec_tlu_ctl.scala 1456:31]
|
|
.clock(perf_csrs_clock),
|
|
.reset(perf_csrs_reset),
|
|
.io_free_l2clk(perf_csrs_io_free_l2clk),
|
|
.io_dec_tlu_dbg_halted(perf_csrs_io_dec_tlu_dbg_halted),
|
|
.io_dcsr(perf_csrs_io_dcsr),
|
|
.io_dec_tlu_pmu_fw_halted(perf_csrs_io_dec_tlu_pmu_fw_halted),
|
|
.io_mhpme_vec_0(perf_csrs_io_mhpme_vec_0),
|
|
.io_mhpme_vec_1(perf_csrs_io_mhpme_vec_1),
|
|
.io_mhpme_vec_2(perf_csrs_io_mhpme_vec_2),
|
|
.io_mhpme_vec_3(perf_csrs_io_mhpme_vec_3),
|
|
.io_dec_csr_wen_r_mod(perf_csrs_io_dec_csr_wen_r_mod),
|
|
.io_dec_csr_wraddr_r(perf_csrs_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(perf_csrs_io_dec_csr_wrdata_r),
|
|
.io_mhpmc_inc_r_0(perf_csrs_io_mhpmc_inc_r_0),
|
|
.io_mhpmc_inc_r_1(perf_csrs_io_mhpmc_inc_r_1),
|
|
.io_mhpmc_inc_r_2(perf_csrs_io_mhpmc_inc_r_2),
|
|
.io_mhpmc_inc_r_3(perf_csrs_io_mhpmc_inc_r_3),
|
|
.io_mhpmc_inc_r_d1_0(perf_csrs_io_mhpmc_inc_r_d1_0),
|
|
.io_mhpmc_inc_r_d1_1(perf_csrs_io_mhpmc_inc_r_d1_1),
|
|
.io_mhpmc_inc_r_d1_2(perf_csrs_io_mhpmc_inc_r_d1_2),
|
|
.io_mhpmc_inc_r_d1_3(perf_csrs_io_mhpmc_inc_r_d1_3),
|
|
.io_perfcnt_halted_d1(perf_csrs_io_perfcnt_halted_d1),
|
|
.io_mhpmc3h(perf_csrs_io_mhpmc3h),
|
|
.io_mhpmc3(perf_csrs_io_mhpmc3),
|
|
.io_mhpmc4h(perf_csrs_io_mhpmc4h),
|
|
.io_mhpmc4(perf_csrs_io_mhpmc4),
|
|
.io_mhpmc5h(perf_csrs_io_mhpmc5h),
|
|
.io_mhpmc5(perf_csrs_io_mhpmc5),
|
|
.io_mhpmc6h(perf_csrs_io_mhpmc6h),
|
|
.io_mhpmc6(perf_csrs_io_mhpmc6),
|
|
.io_mhpme3(perf_csrs_io_mhpme3),
|
|
.io_mhpme4(perf_csrs_io_mhpme4),
|
|
.io_mhpme5(perf_csrs_io_mhpme5),
|
|
.io_mhpme6(perf_csrs_io_mhpme6),
|
|
.io_dec_tlu_perfcnt0(perf_csrs_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(perf_csrs_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(perf_csrs_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(perf_csrs_io_dec_tlu_perfcnt3)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en)
|
|
);
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_820,dicad0}; // @[dec_tlu_ctl.scala 2200:63]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2203:48]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 2211:48]
|
|
assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 2212:48]
|
|
assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2287:48]
|
|
assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2288:51]
|
|
assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2289:48]
|
|
assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2290:48]
|
|
assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2291:48]
|
|
assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2292:48]
|
|
assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2305:59]
|
|
assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2287:48]
|
|
assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2288:51]
|
|
assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2289:48]
|
|
assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2290:48]
|
|
assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2291:48]
|
|
assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2292:48]
|
|
assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2305:59]
|
|
assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2287:48]
|
|
assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2288:51]
|
|
assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2289:48]
|
|
assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2290:48]
|
|
assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2291:48]
|
|
assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2292:48]
|
|
assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2305:59]
|
|
assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2287:48]
|
|
assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2288:51]
|
|
assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2289:48]
|
|
assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2290:48]
|
|
assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2291:48]
|
|
assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2292:48]
|
|
assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2305:59]
|
|
assign io_dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2; // @[dec_tlu_ctl.scala 2478:34]
|
|
assign io_dec_tlu_i0_exc_valid_wb1 = _T_1140 & _T_1146; // @[dec_tlu_ctl.scala 2469:39]
|
|
assign io_dec_tlu_i0_valid_wb1 = _T_1140 & io_i0_valid_wb; // @[dec_tlu_ctl.scala 2468:39]
|
|
assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2479:31]
|
|
assign io_dec_tlu_exc_cause_wb1 = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2 : dec_tlu_exc_cause_wb1_raw; // @[dec_tlu_ctl.scala 2477:34]
|
|
assign io_dec_tlu_perfcnt0 = perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 2436:29]
|
|
assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29]
|
|
assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29]
|
|
assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29]
|
|
assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39]
|
|
assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:39]
|
|
assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:39]
|
|
assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:39]
|
|
assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:39]
|
|
assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28]
|
|
assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46]
|
|
assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31]
|
|
assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2050:26]
|
|
assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 2014:29]
|
|
assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 2000:27]
|
|
assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1852:28]
|
|
assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1812:46]
|
|
assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1811:46]
|
|
assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1810:46]
|
|
assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1809:46]
|
|
assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1808:46]
|
|
assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1806:46]
|
|
assign io_dec_tlu_trace_disable = mfdc[12]; // @[dec_tlu_ctl.scala 1807:46]
|
|
assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1472:30]
|
|
assign io_fw_halt_req = _T_557 & _T_558; // @[dec_tlu_ctl.scala 1887:24]
|
|
assign io_mstatus = perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 2348:26]
|
|
assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1489:27]
|
|
assign io_dcsr = _T_756; // @[dec_tlu_ctl.scala 2098:17]
|
|
assign io_mtvec = _T_61; // @[dec_tlu_ctl.scala 1502:18]
|
|
assign io_mip = perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 2349:18]
|
|
assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[dec_tlu_ctl.scala 1531:19]
|
|
assign io_npc_r = _T_189 | _T_187; // @[dec_tlu_ctl.scala 1635:18]
|
|
assign io_npc_r_d1 = _T_196; // @[dec_tlu_ctl.scala 1641:21]
|
|
assign io_mepc = _T_231; // @[dec_tlu_ctl.scala 1660:17]
|
|
assign io_mdseac_locked_ns = mdseac_en | _T_545; // @[dec_tlu_ctl.scala 1870:29]
|
|
assign io_mdseac_locked_f = perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 2378:42]
|
|
assign io_ext_int_freeze_d1 = perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 2385:42]
|
|
assign io_take_ext_int_start_d1 = perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 2382:42]
|
|
assign io_take_ext_int_start_d2 = perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 2383:42]
|
|
assign io_take_ext_int_start_d3 = perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 2384:42]
|
|
assign io_force_halt = mfdht[0] & _T_665; // @[dec_tlu_ctl.scala 1977:23]
|
|
assign io_dpc = _T_781; // @[dec_tlu_ctl.scala 2115:16]
|
|
assign io_mtdata1_t_0 = _T_965; // @[dec_tlu_ctl.scala 2282:47]
|
|
assign io_mtdata1_t_1 = _T_969; // @[dec_tlu_ctl.scala 2282:47]
|
|
assign io_mtdata1_t_2 = _T_973; // @[dec_tlu_ctl.scala 2282:47]
|
|
assign io_mtdata1_t_3 = _T_977; // @[dec_tlu_ctl.scala 2282:47]
|
|
assign perfmux_flop_reset = reset;
|
|
assign perfmux_flop_io_mcountinhibit = {_T_1138,temp_ncount0}; // @[dec_tlu_ctl.scala 2321:57]
|
|
assign perfmux_flop_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2322:57]
|
|
assign perfmux_flop_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2322:57]
|
|
assign perfmux_flop_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2322:57]
|
|
assign perfmux_flop_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2322:57]
|
|
assign perfmux_flop_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 2323:57]
|
|
assign perfmux_flop_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 2324:57]
|
|
assign perfmux_flop_io_tlu_i0_commit_cmt = io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2325:57]
|
|
assign perfmux_flop_io_illegal_r = io_illegal_r; // @[dec_tlu_ctl.scala 2326:57]
|
|
assign perfmux_flop_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2327:57]
|
|
assign perfmux_flop_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 2328:57]
|
|
assign perfmux_flop_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 2329:57]
|
|
assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 2330:57]
|
|
assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 2330:57]
|
|
assign perfmux_flop_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 2330:57]
|
|
assign perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2330:57]
|
|
assign perfmux_flop_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 2331:57]
|
|
assign perfmux_flop_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 2332:57]
|
|
assign perfmux_flop_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 2333:57]
|
|
assign perfmux_flop_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 2334:57]
|
|
assign perfmux_flop_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 2335:57]
|
|
assign perfmux_flop_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 2336:57]
|
|
assign perfmux_flop_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 2337:57]
|
|
assign perfmux_flop_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 2338:57]
|
|
assign perfmux_flop_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 2339:57]
|
|
assign perfmux_flop_io_i0_exception_valid_r = io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 2340:57]
|
|
assign perfmux_flop_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:57]
|
|
assign perfmux_flop_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 2342:57]
|
|
assign perfmux_flop_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 2343:57]
|
|
assign perfmux_flop_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 2344:57]
|
|
assign perfmux_flop_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 2345:57]
|
|
assign perfmux_flop_io_lsu_pmu_load_external_r = io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2346:57]
|
|
assign perfmux_flop_io_lsu_pmu_store_external_r = io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2347:57]
|
|
assign perfmux_flop_io_mie = mie; // @[dec_tlu_ctl.scala 2350:57]
|
|
assign perfmux_flop_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2351:57]
|
|
assign perfmux_flop_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2352:57]
|
|
assign perfmux_flop_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 2353:57]
|
|
assign perfmux_flop_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 2354:57]
|
|
assign perfmux_flop_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 2355:57]
|
|
assign perfmux_flop_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2356:57]
|
|
assign perfmux_flop_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2357:57]
|
|
assign perfmux_flop_io_i0_trigger_hit_r = io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2358:57]
|
|
assign perfmux_flop_io_lsu_exc_valid_r = io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2359:57]
|
|
assign perfmux_flop_io_take_timer_int = io_take_timer_int; // @[dec_tlu_ctl.scala 2360:57]
|
|
assign perfmux_flop_io_take_int_timer0_int = io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2361:57]
|
|
assign perfmux_flop_io_take_int_timer1_int = io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2362:57]
|
|
assign perfmux_flop_io_take_ext_int = io_take_ext_int; // @[dec_tlu_ctl.scala 2363:57]
|
|
assign perfmux_flop_io_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 2364:57]
|
|
assign perfmux_flop_io_dec_tlu_br0_error_r = io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 2365:57]
|
|
assign perfmux_flop_io_rfpc_i0_r = io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2366:57]
|
|
assign perfmux_flop_io_dec_tlu_br0_start_error_r = io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2367:57]
|
|
assign perfmux_flop_io_mdseac_locked_ns = io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 2389:55]
|
|
assign perfmux_flop_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 2390:55]
|
|
assign perfmux_flop_io_lsu_i0_exc_r = io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 2391:55]
|
|
assign perfmux_flop_io_take_ext_int_start = io_take_ext_int_start; // @[dec_tlu_ctl.scala 2392:55]
|
|
assign perfmux_flop_io_ext_int_freeze = io_ext_int_freeze; // @[dec_tlu_ctl.scala 2393:55]
|
|
assign perfmux_flop_io_mip_ns = {_T_66,_T_64}; // @[dec_tlu_ctl.scala 2394:55]
|
|
assign perfmux_flop_io_mcyclel_cout = mcyclel_inc2[24]; // @[dec_tlu_ctl.scala 2395:55]
|
|
assign perfmux_flop_io_wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 2396:55]
|
|
assign perfmux_flop_io_mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 2397:55]
|
|
assign perfmux_flop_io_minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 2398:55]
|
|
assign perfmux_flop_io_minstretl_cout_ns = _T_141 & _T_142; // @[dec_tlu_ctl.scala 2399:55]
|
|
assign perfmux_flop_io_meicidpl_ns = wr_meicpct_r ? io_pic_pl : _T_684; // @[dec_tlu_ctl.scala 2401:55]
|
|
assign perfmux_flop_io_icache_rd_valid = _T_825 & _T_827; // @[dec_tlu_ctl.scala 2402:55]
|
|
assign perfmux_flop_io_icache_wr_valid = _T_718 & _T_830; // @[dec_tlu_ctl.scala 2403:55]
|
|
assign perfmux_flop_io_perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2404:55]
|
|
assign perfmux_flop_io_mstatus_ns = _T_48 | _T_44; // @[dec_tlu_ctl.scala 2405:55]
|
|
assign perfmux_flop_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2407:56]
|
|
assign perf_csrs_clock = clock;
|
|
assign perf_csrs_reset = reset;
|
|
assign perf_csrs_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2411:50]
|
|
assign perf_csrs_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 2413:50]
|
|
assign perf_csrs_io_dcsr = io_dcsr; // @[dec_tlu_ctl.scala 2414:50]
|
|
assign perf_csrs_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2415:50]
|
|
assign perf_csrs_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2416:50]
|
|
assign perf_csrs_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2416:50]
|
|
assign perf_csrs_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2416:50]
|
|
assign perf_csrs_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2416:50]
|
|
assign perf_csrs_io_dec_csr_wen_r_mod = io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2417:50]
|
|
assign perf_csrs_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 2418:50]
|
|
assign perf_csrs_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 2419:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_0 = perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2420:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_1 = perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2420:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_2 = perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2420:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_3 = perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2420:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_d1_0 = perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2421:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_d1_1 = perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2421:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_d1_2 = perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2421:50]
|
|
assign perf_csrs_io_mhpmc_inc_r_d1_3 = perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2421:50]
|
|
assign perf_csrs_io_perfcnt_halted_d1 = perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2422:50]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_57; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = wr_mcyclel_r | _T_102; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = wr_minstretl_r | _T_147; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = _T_138 | wr_minstretl_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = _T_162 | wr_minstreth_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = io_dec_csr_wen_r_mod & _T_167; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = _T_228 | wr_mepc_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = io_exc_or_int_valid_r | wr_mcause_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = io_tlu_flush_lower_r | wr_mtval_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_367; // @[lib.scala 425:17]
|
|
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_12_io_en = io_dec_csr_wen_r_mod & _T_388; // @[lib.scala 425:17]
|
|
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_13_io_en = io_dec_csr_wen_r_mod & _T_430; // @[lib.scala 425:17]
|
|
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_14_io_en = _T_549 & _T_550; // @[lib.scala 425:17]
|
|
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_15_io_en = wr_micect_r | io_ic_perr_r; // @[lib.scala 425:17]
|
|
assign rvclkhdr_16_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_16_io_en = _T_604 | io_iccm_dma_sb_error; // @[lib.scala 425:17]
|
|
assign rvclkhdr_17_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_17_io_en = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_18_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_18_io_en = mfdht[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_19_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_19_io_en = io_dec_csr_wen_r_mod & _T_668; // @[lib.scala 425:17]
|
|
assign rvclkhdr_20_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_20_io_en = _T_687 | io_take_ext_int_start; // @[lib.scala 425:17]
|
|
assign rvclkhdr_21_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_21_io_en = _T_753 | io_take_nmi; // @[lib.scala 425:17]
|
|
assign rvclkhdr_22_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_22_io_en = _T_778 | dpc_capture_npc; // @[lib.scala 425:17]
|
|
assign rvclkhdr_23_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_23_io_en = _T_718 & _T_788; // @[lib.scala 425:17]
|
|
assign rvclkhdr_24_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_24_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_25_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_25_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_26_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_26_io_en = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_27_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_27_io_en = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[lib.scala 425:17]
|
|
assign rvclkhdr_28_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_28_io_en = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_29_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_29_io_en = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[lib.scala 425:17]
|
|
assign rvclkhdr_30_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_30_io_en = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[lib.scala 425:17]
|
|
assign rvclkhdr_31_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_31_io_en = _T_1073 & _T_893; // @[lib.scala 425:17]
|
|
assign rvclkhdr_32_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_32_io_en = _T_1082 & _T_902; // @[lib.scala 425:17]
|
|
assign rvclkhdr_33_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_33_io_en = _T_1091 & _T_913; // @[lib.scala 425:17]
|
|
assign rvclkhdr_34_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_34_io_en = _T_1100 & _T_922; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
mpmc_b = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_61 = _RAND_1[30:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
mdccmect = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
miccmect = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
micect = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
mie = _RAND_5[5:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
temp_ncount6_2 = _RAND_6[4:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
temp_ncount0 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_106 = _RAND_8[23:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_110 = _RAND_9[7:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
mcycleh = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_150 = _RAND_11[23:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_153 = _RAND_12[7:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
minstreth = _RAND_13[31:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
mscratch = _RAND_14[31:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
_T_196 = _RAND_15[30:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
pc_r_d1 = _RAND_16[30:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_231 = _RAND_17[30:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
mcause = _RAND_18[31:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
mscause = _RAND_19[3:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
mtval = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
mcgc_int = _RAND_21[9:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
mfdc_int = _RAND_22[15:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
mrac = _RAND_23[31:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
mdseac = _RAND_24[31:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
mfdht = _RAND_25[5:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
mfdhs = _RAND_26[1:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
force_halt_ctr_f = _RAND_27[31:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
meivt = _RAND_28[21:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
meihap = _RAND_29[7:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
meicurpl = _RAND_30[3:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
meipt = _RAND_31[3:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
_T_756 = _RAND_32[15:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
_T_781 = _RAND_33[30:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
dicawics = _RAND_34[16:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
dicad0 = _RAND_35[31:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
dicad0h = _RAND_36[31:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_815 = _RAND_37[6:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
mtsel = _RAND_38[1:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
_T_965 = _RAND_39[9:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
_T_969 = _RAND_40[9:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
_T_973 = _RAND_41[9:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
_T_977 = _RAND_42[9:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
mtdata2_t_0 = _RAND_43[31:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
mtdata2_t_1 = _RAND_44[31:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
mtdata2_t_2 = _RAND_45[31:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
mtdata2_t_3 = _RAND_46[31:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
dec_tlu_exc_cause_wb2 = _RAND_47[4:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
dec_tlu_int_valid_wb2 = _RAND_48[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
mpmc_b = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_61 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
mdccmect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
miccmect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
micect = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mie = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
temp_ncount6_2 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
temp_ncount0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_106 = 24'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
mcycleh = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_150 = 24'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_153 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
minstreth = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mscratch = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_196 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
pc_r_d1 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_231 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
mcause = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mscause = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
mtval = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mcgc_int = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdc_int = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
mrac = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mdseac = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdht = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
mfdhs = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
force_halt_ctr_f = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
meivt = 22'h0;
|
|
end
|
|
if (reset) begin
|
|
meihap = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
meicurpl = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
meipt = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_756 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_781 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
dicawics = 17'h0;
|
|
end
|
|
if (reset) begin
|
|
dicad0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
dicad0h = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_815 = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
mtsel = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_965 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_969 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_973 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_977 = 10'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
mtdata2_t_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_exc_cause_wb2 = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_int_valid_wb2 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpmc_b <= 1'h0;
|
|
end else if (wr_mpmc_r) begin
|
|
mpmc_b <= _T_565;
|
|
end else begin
|
|
mpmc_b <= _T_566;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_61 <= 31'h0;
|
|
end else if (wr_mtvec_r) begin
|
|
_T_61 <= mtvec_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mdccmect <= 32'h0;
|
|
end else if (_T_625) begin
|
|
if (wr_mdccmect_r) begin
|
|
mdccmect <= _T_580;
|
|
end else begin
|
|
mdccmect <= _T_624;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
miccmect <= 32'h0;
|
|
end else if (_T_605) begin
|
|
if (wr_miccmect_r) begin
|
|
miccmect <= _T_580;
|
|
end else begin
|
|
miccmect <= _T_603;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
micect <= 32'h0;
|
|
end else if (_T_583) begin
|
|
if (wr_micect_r) begin
|
|
micect <= _T_580;
|
|
end else begin
|
|
micect <= _T_582;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mie <= 6'h0;
|
|
end else begin
|
|
mie <= io_mie_ns;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
temp_ncount6_2 <= 5'h0;
|
|
end else if (wr_mcountinhibit_r) begin
|
|
temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2];
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
temp_ncount0 <= 1'h0;
|
|
end else if (wr_mcountinhibit_r) begin
|
|
temp_ncount0 <= io_dec_csr_wrdata_r[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_106 <= 24'h0;
|
|
end else if (_T_104) begin
|
|
_T_106 <= mcyclel_ns[31:8];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110 <= 8'h0;
|
|
end else if (_T_108) begin
|
|
_T_110 <= mcyclel_ns[7:0];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mcycleh <= 32'h0;
|
|
end else if (_T_117) begin
|
|
if (wr_mcycleh_r) begin
|
|
mcycleh <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
mcycleh <= mcycleh_inc;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_150 <= 24'h0;
|
|
end else if (_T_148) begin
|
|
_T_150 <= minstretl_ns[31:8];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_153 <= 8'h0;
|
|
end else if (minstret_enable) begin
|
|
_T_153 <= minstretl_ns[7:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
minstreth <= 32'h0;
|
|
end else if (_T_163) begin
|
|
if (wr_minstreth_r) begin
|
|
minstreth <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
minstreth <= minstreth_inc;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mscratch <= 32'h0;
|
|
end else if (wr_mscratch_r) begin
|
|
mscratch <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_196 <= 31'h0;
|
|
end else if (_T_193) begin
|
|
_T_196 <= io_npc_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
pc_r_d1 <= 31'h0;
|
|
end else if (pc0_valid_r) begin
|
|
pc_r_d1 <= pc_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_231 <= 31'h0;
|
|
end else if (_T_229) begin
|
|
_T_231 <= mepc_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mcause <= 32'h0;
|
|
end else if (_T_274) begin
|
|
mcause <= mcause_ns;
|
|
end
|
|
end
|
|
always @(posedge io_e4e5_int_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mscause <= 4'h0;
|
|
end else begin
|
|
mscause <= _T_304 | _T_303;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mtval <= 32'h0;
|
|
end else if (_T_363) begin
|
|
mtval <= mtval_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mcgc_int <= 10'h0;
|
|
end else if (wr_mcgc_r) begin
|
|
if (wr_mcgc_r) begin
|
|
mcgc_int <= _T_372;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mfdc_int <= 16'h0;
|
|
end else if (wr_mfdc_r) begin
|
|
mfdc_int <= mfdc_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mrac <= 32'h0;
|
|
end else if (wr_mrac_r) begin
|
|
mrac <= mrac_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mdseac <= 32'h0;
|
|
end else if (mdseac_en) begin
|
|
mdseac <= io_lsu_imprecise_error_addr_any;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mfdht <= 6'h0;
|
|
end else if (wr_mfdht_r) begin
|
|
if (wr_mfdht_r) begin
|
|
mfdht <= io_dec_csr_wrdata_r[5:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mfdhs <= 2'h0;
|
|
end else if (_T_651) begin
|
|
if (wr_mfdhs_r) begin
|
|
mfdhs <= io_dec_csr_wrdata_r[1:0];
|
|
end else if (_T_645) begin
|
|
mfdhs <= _T_649;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
force_halt_ctr_f <= 32'h0;
|
|
end else if (mfdht[0]) begin
|
|
if (io_debug_halt_req_f) begin
|
|
force_halt_ctr_f <= _T_656;
|
|
end else if (io_dbg_tlu_halted_f) begin
|
|
force_halt_ctr_f <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
meivt <= 22'h0;
|
|
end else if (wr_meivt_r) begin
|
|
meivt <= io_dec_csr_wrdata_r[31:10];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
meihap <= 8'h0;
|
|
end else if (wr_meicpct_r) begin
|
|
meihap <= io_pic_claimid;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
meicurpl <= 4'h0;
|
|
end else if (wr_meicurpl_r) begin
|
|
meicurpl <= io_dec_csr_wrdata_r[3:0];
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
meipt <= 4'h0;
|
|
end else if (wr_meipt_r) begin
|
|
meipt <= io_dec_csr_wrdata_r[3:0];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_756 <= 16'h0;
|
|
end else if (_T_754) begin
|
|
if (enter_debug_halt_req_le) begin
|
|
_T_756 <= _T_730;
|
|
end else if (wr_dcsr_r) begin
|
|
_T_756 <= _T_745;
|
|
end else begin
|
|
_T_756 <= _T_750;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_781 <= 31'h0;
|
|
end else if (_T_779) begin
|
|
_T_781 <= dpc_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dicawics <= 17'h0;
|
|
end else if (wr_dicawics_r) begin
|
|
dicawics <= dicawics_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dicad0 <= 32'h0;
|
|
end else if (_T_795) begin
|
|
if (wr_dicad0_r) begin
|
|
dicad0 <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
dicad0 <= io_ifu_ic_debug_rd_data[31:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dicad0h <= 32'h0;
|
|
end else if (_T_802) begin
|
|
if (wr_dicad0h_r) begin
|
|
dicad0h <= io_dec_csr_wrdata_r;
|
|
end else begin
|
|
dicad0h <= io_ifu_ic_debug_rd_data[63:32];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_815 <= 7'h0;
|
|
end else if (_T_813) begin
|
|
if (_T_808) begin
|
|
_T_815 <= io_dec_csr_wrdata_r[6:0];
|
|
end else begin
|
|
_T_815 <= io_ifu_ic_debug_rd_data[70:64];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mtsel <= 2'h0;
|
|
end else if (wr_mtsel_r) begin
|
|
mtsel <= io_dec_csr_wrdata_r[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_965 <= 10'h0;
|
|
end else if (_T_963) begin
|
|
if (wr_mtdata1_t_r_0) begin
|
|
_T_965 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_965 <= _T_933;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_969 <= 10'h0;
|
|
end else if (_T_967) begin
|
|
if (wr_mtdata1_t_r_1) begin
|
|
_T_969 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_969 <= _T_942;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_973 <= 10'h0;
|
|
end else if (_T_971) begin
|
|
if (wr_mtdata1_t_r_2) begin
|
|
_T_973 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_973 <= _T_951;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_977 <= 10'h0;
|
|
end else if (_T_975) begin
|
|
if (wr_mtdata1_t_r_3) begin
|
|
_T_977 <= tdata_wrdata_r;
|
|
end else begin
|
|
_T_977 <= _T_960;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_0 <= 32'h0;
|
|
end else if (wr_mtdata2_t_r_0) begin
|
|
mtdata2_t_0 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_1 <= 32'h0;
|
|
end else if (wr_mtdata2_t_r_1) begin
|
|
mtdata2_t_1 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_2 <= 32'h0;
|
|
end else if (wr_mtdata2_t_r_2) begin
|
|
mtdata2_t_2 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mtdata2_t_3 <= 32'h0;
|
|
end else if (wr_mtdata2_t_r_3) begin
|
|
mtdata2_t_3 <= io_dec_csr_wrdata_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_exc_cause_wb2 <= 5'h0;
|
|
end else if (_T_1153) begin
|
|
dec_tlu_exc_cause_wb2 <= dec_tlu_exc_cause_wb1_raw;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_int_valid_wb2 <= 1'h0;
|
|
end else if (_T_1156) begin
|
|
dec_tlu_int_valid_wb2 <= dec_tlu_int_valid_wb1_raw;
|
|
end
|
|
end
|
|
endmodule
|
|
module dec_timer_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_l2clk,
|
|
input io_csr_wr_clk,
|
|
input io_dec_csr_wen_r_mod,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input io_csr_mitctl0,
|
|
input io_csr_mitctl1,
|
|
input io_csr_mitb0,
|
|
input io_csr_mitb1,
|
|
input io_csr_mitcnt0,
|
|
input io_csr_mitcnt1,
|
|
input io_dec_pause_state,
|
|
input io_dec_tlu_pmu_fw_halted,
|
|
input io_internal_dbg_halt_timers,
|
|
output [31:0] io_dec_timer_rddata_d,
|
|
output io_dec_timer_read_d,
|
|
output io_dec_timer_t0_pulse,
|
|
output io_dec_timer_t1_pulse
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
reg [23:0] _T_28; // @[Reg.scala 27:20]
|
|
reg [7:0] _T_33; // @[Reg.scala 27:20]
|
|
wire [31:0] mitcnt0 = {_T_28,_T_33}; // @[Cat.scala 29:58]
|
|
reg [31:0] mitb0_b; // @[Reg.scala 27:20]
|
|
wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 3335:22]
|
|
wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3277:36]
|
|
reg [23:0] _T_67; // @[Reg.scala 27:20]
|
|
reg [7:0] _T_72; // @[Reg.scala 27:20]
|
|
wire [31:0] mitcnt1 = {_T_67,_T_72}; // @[Cat.scala 29:58]
|
|
reg [31:0] mitb1_b; // @[Reg.scala 27:20]
|
|
wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 3344:18]
|
|
wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3278:36]
|
|
wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 3288:72]
|
|
wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 3288:49]
|
|
reg [1:0] _T_90; // @[Reg.scala 27:20]
|
|
reg mitctl0_0_b; // @[Reg.scala 27:20]
|
|
wire _T_91 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 3360:107]
|
|
wire [2:0] mitctl0 = {_T_90,_T_91}; // @[Cat.scala 29:58]
|
|
wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 3290:56]
|
|
wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 3290:76]
|
|
wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 3290:53]
|
|
wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 3290:112]
|
|
wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 3290:138]
|
|
wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 3290:109]
|
|
wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 3290:173]
|
|
wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 3290:171]
|
|
wire [7:0] _T_14 = mitcnt0[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3293:38]
|
|
wire [8:0] mitcnt0_inc1 = {{1'd0}, _T_14}; // @[dec_tlu_ctl.scala 3293:22]
|
|
wire mitcnt0_inc_cout = mitcnt0_inc1[8]; // @[dec_tlu_ctl.scala 3294:44]
|
|
wire [23:0] _T_16 = {23'h0,mitcnt0_inc_cout}; // @[Cat.scala 29:58]
|
|
wire [23:0] mitcnt0_inc2 = mitcnt0[31:8] + _T_16; // @[dec_tlu_ctl.scala 3295:39]
|
|
wire [31:0] mitcnt0_inc = {mitcnt0_inc2,mitcnt0_inc1[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_22 = mit0_match_ns ? 32'h0 : mitcnt0_inc; // @[dec_tlu_ctl.scala 3298:69]
|
|
wire [31:0] mitcnt0_ns = wr_mitcnt0_r ? io_dec_csr_wrdata_r : _T_22; // @[dec_tlu_ctl.scala 3298:30]
|
|
wire _T_24 = mitcnt0_inc_ok & mitcnt0_inc_cout; // @[dec_tlu_ctl.scala 3301:87]
|
|
wire _T_25 = wr_mitcnt0_r | _T_24; // @[dec_tlu_ctl.scala 3301:69]
|
|
wire _T_26 = _T_25 | mit0_match_ns; // @[dec_tlu_ctl.scala 3301:107]
|
|
wire _T_30 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 3302:54]
|
|
wire _T_31 = _T_30 | mit0_match_ns; // @[dec_tlu_ctl.scala 3302:71]
|
|
wire _T_35 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 3309:72]
|
|
wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 3309:49]
|
|
reg [2:0] _T_101; // @[Reg.scala 27:20]
|
|
reg mitctl1_0_b; // @[Reg.scala 27:20]
|
|
wire _T_102 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 3374:92]
|
|
wire [3:0] mitctl1 = {_T_101,_T_102}; // @[Cat.scala 29:58]
|
|
wire _T_39 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 3311:76]
|
|
wire _T_40 = mitctl1[0] & _T_39; // @[dec_tlu_ctl.scala 3311:53]
|
|
wire _T_43 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 3311:138]
|
|
wire _T_44 = _T_40 & _T_43; // @[dec_tlu_ctl.scala 3311:109]
|
|
wire _T_46 = _T_44 & _T_10; // @[dec_tlu_ctl.scala 3311:171]
|
|
wire _T_48 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 3311:205]
|
|
wire _T_49 = _T_48 | mit0_match_ns; // @[dec_tlu_ctl.scala 3311:217]
|
|
wire mitcnt1_inc_ok = _T_46 & _T_49; // @[dec_tlu_ctl.scala 3311:202]
|
|
wire [7:0] _T_53 = mitcnt1[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3316:38]
|
|
wire [8:0] mitcnt1_inc1 = {{1'd0}, _T_53}; // @[dec_tlu_ctl.scala 3316:22]
|
|
wire mitcnt1_inc_cout = mitcnt1_inc1[8]; // @[dec_tlu_ctl.scala 3317:44]
|
|
wire [23:0] _T_55 = {23'h0,mitcnt1_inc_cout}; // @[Cat.scala 29:58]
|
|
wire [23:0] mitcnt1_inc2 = mitcnt1[31:8] + _T_55; // @[dec_tlu_ctl.scala 3318:39]
|
|
wire [31:0] mitcnt1_inc = {mitcnt1_inc2,mitcnt1_inc1[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_61 = mit1_match_ns ? 32'h0 : mitcnt1_inc; // @[dec_tlu_ctl.scala 3321:75]
|
|
wire [31:0] mitcnt1_ns = wr_mitcnt1_r ? io_dec_csr_wrdata_r : _T_61; // @[dec_tlu_ctl.scala 3321:29]
|
|
wire _T_63 = mitcnt1_inc_ok & mitcnt1_inc_cout; // @[dec_tlu_ctl.scala 3323:87]
|
|
wire _T_64 = wr_mitcnt1_r | _T_63; // @[dec_tlu_ctl.scala 3323:69]
|
|
wire _T_65 = _T_64 | mit1_match_ns; // @[dec_tlu_ctl.scala 3323:107]
|
|
wire _T_69 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 3324:54]
|
|
wire _T_70 = _T_69 | mit1_match_ns; // @[dec_tlu_ctl.scala 3324:71]
|
|
wire _T_74 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 3333:70]
|
|
wire wr_mitb0_r = io_dec_csr_wen_r_mod & _T_74; // @[dec_tlu_ctl.scala 3333:47]
|
|
wire [31:0] _T_75 = ~io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 3334:38]
|
|
wire _T_78 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 3342:69]
|
|
wire wr_mitb1_r = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 3342:47]
|
|
wire _T_82 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 3355:72]
|
|
wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_82; // @[dec_tlu_ctl.scala 3355:49]
|
|
wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 3356:31]
|
|
wire mitctl0_0_b_ns = ~mitctl0_ns[0]; // @[dec_tlu_ctl.scala 3358:30]
|
|
wire _T_93 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 3370:71]
|
|
wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 3370:49]
|
|
wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 3371:31]
|
|
wire mitctl1_0_b_ns = ~mitctl1_ns[0]; // @[dec_tlu_ctl.scala 3372:29]
|
|
wire _T_104 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 3376:51]
|
|
wire _T_105 = _T_104 | io_csr_mitb1; // @[dec_tlu_ctl.scala 3376:68]
|
|
wire _T_106 = _T_105 | io_csr_mitb0; // @[dec_tlu_ctl.scala 3376:83]
|
|
wire _T_107 = _T_106 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 3376:98]
|
|
wire [31:0] _T_116 = {29'h0,_T_90,_T_91}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_119 = {28'h0,_T_101,_T_102}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_120 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_121 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_122 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_123 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_124 = io_csr_mitctl0 ? _T_116 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_125 = io_csr_mitctl1 ? _T_119 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_126 = _T_120 | _T_121; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_127 = _T_126 | _T_122; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_128 = _T_127 | _T_123; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_129 = _T_128 | _T_124; // @[Mux.scala 27:72]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
assign io_dec_timer_rddata_d = _T_129 | _T_125; // @[dec_tlu_ctl.scala 3377:33]
|
|
assign io_dec_timer_read_d = _T_107 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 3376:33]
|
|
assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3280:31]
|
|
assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3281:31]
|
|
assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = _T_25 | mit0_match_ns; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = _T_30 | mit0_match_ns; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = _T_64 | mit1_match_ns; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = _T_69 | mit1_match_ns; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = io_dec_csr_wen_r_mod & _T_74; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_78; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_28 = _RAND_0[23:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_33 = _RAND_1[7:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
mitb0_b = _RAND_2[31:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_67 = _RAND_3[23:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_72 = _RAND_4[7:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
mitb1_b = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_90 = _RAND_6[1:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
mitctl0_0_b = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_101 = _RAND_8[2:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
mitctl1_0_b = _RAND_9[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_28 = 24'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_33 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
mitb0_b = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_67 = 24'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_72 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
mitb1_b = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_90 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
mitctl0_0_b = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_101 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
mitctl1_0_b = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_28 <= 24'h0;
|
|
end else if (_T_26) begin
|
|
_T_28 <= mitcnt0_ns[31:8];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_33 <= 8'h0;
|
|
end else if (_T_31) begin
|
|
_T_33 <= mitcnt0_ns[7:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mitb0_b <= 32'h0;
|
|
end else if (wr_mitb0_r) begin
|
|
mitb0_b <= _T_75;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_67 <= 24'h0;
|
|
end else if (_T_65) begin
|
|
_T_67 <= mitcnt1_ns[31:8];
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_72 <= 8'h0;
|
|
end else if (_T_70) begin
|
|
_T_72 <= mitcnt1_ns[7:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mitb1_b <= 32'h0;
|
|
end else if (wr_mitb1_r) begin
|
|
mitb1_b <= _T_75;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_90 <= 2'h0;
|
|
end else if (wr_mitctl0_r) begin
|
|
_T_90 <= mitctl0_ns[2:1];
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitctl0_0_b <= 1'h0;
|
|
end else if (wr_mitctl0_r) begin
|
|
mitctl0_0_b <= mitctl0_0_b_ns;
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_101 <= 3'h0;
|
|
end else if (wr_mitctl1_r) begin
|
|
_T_101 <= mitctl1_ns[3:1];
|
|
end
|
|
end
|
|
always @(posedge io_csr_wr_clk or posedge reset) begin
|
|
if (reset) begin
|
|
mitctl1_0_b <= 1'h0;
|
|
end else if (wr_mitctl1_r) begin
|
|
mitctl1_0_b <= mitctl1_0_b_ns;
|
|
end
|
|
end
|
|
endmodule
|
|
module dec_decode_csr_read(
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
output io_csr_pkt_csr_misa,
|
|
output io_csr_pkt_csr_mvendorid,
|
|
output io_csr_pkt_csr_marchid,
|
|
output io_csr_pkt_csr_mimpid,
|
|
output io_csr_pkt_csr_mhartid,
|
|
output io_csr_pkt_csr_mstatus,
|
|
output io_csr_pkt_csr_mtvec,
|
|
output io_csr_pkt_csr_mip,
|
|
output io_csr_pkt_csr_mie,
|
|
output io_csr_pkt_csr_mcyclel,
|
|
output io_csr_pkt_csr_mcycleh,
|
|
output io_csr_pkt_csr_minstretl,
|
|
output io_csr_pkt_csr_minstreth,
|
|
output io_csr_pkt_csr_mscratch,
|
|
output io_csr_pkt_csr_mepc,
|
|
output io_csr_pkt_csr_mcause,
|
|
output io_csr_pkt_csr_mscause,
|
|
output io_csr_pkt_csr_mtval,
|
|
output io_csr_pkt_csr_mrac,
|
|
output io_csr_pkt_csr_dmst,
|
|
output io_csr_pkt_csr_mdseac,
|
|
output io_csr_pkt_csr_meihap,
|
|
output io_csr_pkt_csr_meivt,
|
|
output io_csr_pkt_csr_meipt,
|
|
output io_csr_pkt_csr_meicurpl,
|
|
output io_csr_pkt_csr_meicidpl,
|
|
output io_csr_pkt_csr_dcsr,
|
|
output io_csr_pkt_csr_mcgc,
|
|
output io_csr_pkt_csr_mfdc,
|
|
output io_csr_pkt_csr_dpc,
|
|
output io_csr_pkt_csr_mtsel,
|
|
output io_csr_pkt_csr_mtdata1,
|
|
output io_csr_pkt_csr_mtdata2,
|
|
output io_csr_pkt_csr_mhpmc3,
|
|
output io_csr_pkt_csr_mhpmc4,
|
|
output io_csr_pkt_csr_mhpmc5,
|
|
output io_csr_pkt_csr_mhpmc6,
|
|
output io_csr_pkt_csr_mhpmc3h,
|
|
output io_csr_pkt_csr_mhpmc4h,
|
|
output io_csr_pkt_csr_mhpmc5h,
|
|
output io_csr_pkt_csr_mhpmc6h,
|
|
output io_csr_pkt_csr_mhpme3,
|
|
output io_csr_pkt_csr_mhpme4,
|
|
output io_csr_pkt_csr_mhpme5,
|
|
output io_csr_pkt_csr_mhpme6,
|
|
output io_csr_pkt_csr_mcountinhibit,
|
|
output io_csr_pkt_csr_mitctl0,
|
|
output io_csr_pkt_csr_mitctl1,
|
|
output io_csr_pkt_csr_mitb0,
|
|
output io_csr_pkt_csr_mitb1,
|
|
output io_csr_pkt_csr_mitcnt0,
|
|
output io_csr_pkt_csr_mitcnt1,
|
|
output io_csr_pkt_csr_mpmc,
|
|
output io_csr_pkt_csr_meicpct,
|
|
output io_csr_pkt_csr_micect,
|
|
output io_csr_pkt_csr_miccmect,
|
|
output io_csr_pkt_csr_mdccmect,
|
|
output io_csr_pkt_csr_mfdht,
|
|
output io_csr_pkt_csr_mfdhs,
|
|
output io_csr_pkt_csr_dicawics,
|
|
output io_csr_pkt_csr_dicad0h,
|
|
output io_csr_pkt_csr_dicad0,
|
|
output io_csr_pkt_csr_dicad1,
|
|
output io_csr_pkt_csr_dicago,
|
|
output io_csr_pkt_presync,
|
|
output io_csr_pkt_postsync,
|
|
output io_csr_pkt_legal
|
|
);
|
|
wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:165]
|
|
wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:129]
|
|
wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_645 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_646 = _T_645 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_662 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_670 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_671 = _T_670 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_672 = _T_671 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_680 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_693 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_695 = _T_694 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_696 = _T_695 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_703 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_704 = _T_703 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_714 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_715 = _T_714 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_725 = _T_703 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_726 = _T_725 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_764 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 3241:81]
|
|
wire _T_776 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_777 = _T_776 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_778 = _T_777 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_779 = _T_778 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_780 = _T_779 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_781 = _T_764 | _T_780; // @[dec_tlu_ctl.scala 3241:121]
|
|
wire _T_790 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_791 = _T_790 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_792 = _T_791 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_793 = _T_792 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_794 = _T_781 | _T_793; // @[dec_tlu_ctl.scala 3241:155]
|
|
wire _T_805 = _T_791 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_806 = _T_805 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_807 = _T_794 | _T_806; // @[dec_tlu_ctl.scala 3242:49]
|
|
wire _T_818 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_819 = _T_818 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_820 = _T_819 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_821 = _T_820 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_822 = _T_821 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_846 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 3243:81]
|
|
wire _T_856 = _T_846 | _T_183; // @[dec_tlu_ctl.scala 3243:121]
|
|
wire _T_866 = _T_856 | _T_342; // @[dec_tlu_ctl.scala 3243:162]
|
|
wire _T_881 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_882 = _T_881 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_883 = _T_882 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_884 = _T_883 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_885 = _T_884 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_886 = _T_885 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_887 = _T_866 | _T_886; // @[dec_tlu_ctl.scala 3244:57]
|
|
wire _T_899 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_900 = _T_899 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_901 = _T_900 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_902 = _T_901 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_903 = _T_887 | _T_902; // @[dec_tlu_ctl.scala 3244:97]
|
|
wire _T_914 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_915 = _T_914 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_932 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_933 = _T_932 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_934 = _T_933 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_935 = _T_934 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_936 = _T_935 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_937 = _T_936 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_938 = _T_937 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_939 = _T_938 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_940 = _T_939 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_941 = _T_940 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_960 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_961 = _T_960 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_962 = _T_961 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_963 = _T_962 & _T_15; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_964 = _T_963 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_965 = _T_964 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_966 = _T_965 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_967 = _T_966 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_968 = _T_967 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_969 = _T_941 | _T_968; // @[dec_tlu_ctl.scala 3246:81]
|
|
wire _T_990 = _T_964 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_992 = _T_991 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_993 = _T_969 | _T_992; // @[dec_tlu_ctl.scala 3246:129]
|
|
wire _T_1009 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1010 = _T_1009 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1011 = _T_1010 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1012 = _T_1011 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1013 = _T_1012 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1014 = _T_1013 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1015 = _T_1014 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1016 = _T_1015 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1017 = _T_1016 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1018 = _T_993 | _T_1017; // @[dec_tlu_ctl.scala 3247:73]
|
|
wire _T_1030 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1031 = _T_1030 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1032 = _T_1031 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1033 = _T_1032 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1034 = _T_1033 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1035 = _T_1034 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1036 = _T_1018 | _T_1035; // @[dec_tlu_ctl.scala 3247:121]
|
|
wire _T_1055 = _T_936 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1056 = _T_1055 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1057 = _T_1056 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1058 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1059 = _T_1058 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1060 = _T_1059 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1061 = _T_1036 | _T_1060; // @[dec_tlu_ctl.scala 3248:73]
|
|
wire _T_1082 = _T_1056 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1083 = _T_1082 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1084 = _T_1061 | _T_1083; // @[dec_tlu_ctl.scala 3248:121]
|
|
wire _T_1102 = _T_1010 & _T_15; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1103 = _T_1102 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1104 = _T_1103 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1105 = _T_1104 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1106 = _T_1105 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1107 = _T_1106 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1108 = _T_1107 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1109 = _T_1084 | _T_1108; // @[dec_tlu_ctl.scala 3249:73]
|
|
wire _T_1129 = _T_935 & _T_3; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1130 = _T_1129 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1131 = _T_1130 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1132 = _T_1131 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1133 = _T_1132 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1134 = _T_1109 | _T_1133; // @[dec_tlu_ctl.scala 3249:129]
|
|
wire _T_1153 = _T_990 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1154 = _T_1134 | _T_1153; // @[dec_tlu_ctl.scala 3250:73]
|
|
wire _T_1179 = _T_1106 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1180 = _T_1179 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1181 = _T_1180 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1182 = _T_1154 | _T_1181; // @[dec_tlu_ctl.scala 3250:129]
|
|
wire _T_1201 = _T_936 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1202 = _T_1201 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1203 = _T_1202 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1204 = _T_1203 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1205 = _T_1182 | _T_1204; // @[dec_tlu_ctl.scala 3251:65]
|
|
wire _T_1225 = _T_1201 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1226 = _T_1225 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 3251:121]
|
|
wire _T_1252 = _T_1107 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1253 = _T_1228 | _T_1252; // @[dec_tlu_ctl.scala 3252:73]
|
|
wire _T_1273 = _T_990 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1274 = _T_1273 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1275 = _T_1253 | _T_1274; // @[dec_tlu_ctl.scala 3252:129]
|
|
wire _T_1292 = _T_1032 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1293 = _T_1292 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1294 = _T_1293 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1295 = _T_1294 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1296 = _T_1295 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1297 = _T_1275 | _T_1296; // @[dec_tlu_ctl.scala 3253:73]
|
|
wire _T_1320 = _T_1295 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1321 = _T_1320 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1322 = _T_1297 | _T_1321; // @[dec_tlu_ctl.scala 3253:129]
|
|
wire _T_1338 = _T_1034 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1339 = _T_1322 | _T_1338; // @[dec_tlu_ctl.scala 3254:73]
|
|
wire _T_1361 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1362 = _T_1339 | _T_1361; // @[dec_tlu_ctl.scala 3254:129]
|
|
wire _T_1383 = _T_1202 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1384 = _T_1362 | _T_1383; // @[dec_tlu_ctl.scala 3255:73]
|
|
wire _T_1407 = _T_1203 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1408 = _T_1384 | _T_1407; // @[dec_tlu_ctl.scala 3255:129]
|
|
wire _T_1432 = _T_1130 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1433 = _T_1432 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1434 = _T_1433 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1435 = _T_1434 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1436 = _T_1408 | _T_1435; // @[dec_tlu_ctl.scala 3256:73]
|
|
wire _T_1452 = _T_1034 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1453 = _T_1436 | _T_1452; // @[dec_tlu_ctl.scala 3256:121]
|
|
wire _T_1475 = _T_963 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1476 = _T_1475 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1477 = _T_1476 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1478 = _T_1477 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1479 = _T_1478 & _T_7; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1480 = _T_1453 | _T_1479; // @[dec_tlu_ctl.scala 3257:81]
|
|
wire _T_1503 = _T_963 & _T_5; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1504 = _T_1503 & _T_94; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1505 = _T_1504 & _T_96; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1506 = _T_1505 & _T_17; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1507 = _T_1506 & _T_27; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1508 = _T_1480 | _T_1507; // @[dec_tlu_ctl.scala 3257:129]
|
|
wire _T_1527 = _T_990 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1528 = _T_1508 | _T_1527; // @[dec_tlu_ctl.scala 3258:65]
|
|
wire _T_1544 = _T_1034 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1545 = _T_1528 | _T_1544; // @[dec_tlu_ctl.scala 3258:121]
|
|
wire _T_1564 = _T_990 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
wire _T_1565 = _T_1545 | _T_1564; // @[dec_tlu_ctl.scala 3259:81]
|
|
wire _T_1581 = _T_1034 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198]
|
|
assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3175:57]
|
|
assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3176:57]
|
|
assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 3177:57]
|
|
assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3178:57]
|
|
assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3179:57]
|
|
assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 3180:57]
|
|
assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3181:57]
|
|
assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3182:65]
|
|
assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 3183:65]
|
|
assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 3184:57]
|
|
assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 3185:57]
|
|
assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 3186:57]
|
|
assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 3187:57]
|
|
assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 3188:57]
|
|
assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3189:57]
|
|
assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 3190:57]
|
|
assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3191:57]
|
|
assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3192:57]
|
|
assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 3193:57]
|
|
assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 3194:57]
|
|
assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 3195:57]
|
|
assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3196:57]
|
|
assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 3197:57]
|
|
assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3198:57]
|
|
assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3199:57]
|
|
assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3200:57]
|
|
assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 3201:57]
|
|
assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 3202:57]
|
|
assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3203:57]
|
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assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3204:65]
|
|
assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 3205:57]
|
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assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3206:57]
|
|
assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3207:57]
|
|
assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3208:57]
|
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assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 3209:57]
|
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assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3210:57]
|
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assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 3211:57]
|
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assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3212:57]
|
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assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 3213:57]
|
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assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3214:57]
|
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assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 3215:57]
|
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assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3216:57]
|
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assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 3217:57]
|
|
assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3218:57]
|
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assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 3219:57]
|
|
assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3220:49]
|
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assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 3221:57]
|
|
assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3222:57]
|
|
assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3223:57]
|
|
assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 3224:57]
|
|
assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 3225:57]
|
|
assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3226:57]
|
|
assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3227:57]
|
|
assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 3229:57]
|
|
assign io_csr_pkt_csr_micect = _T_646 & _T_27; // @[dec_tlu_ctl.scala 3231:57]
|
|
assign io_csr_pkt_csr_miccmect = _T_645 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3232:57]
|
|
assign io_csr_pkt_csr_mdccmect = _T_662 & _T_27; // @[dec_tlu_ctl.scala 3233:57]
|
|
assign io_csr_pkt_csr_mfdht = _T_672 & _T_27; // @[dec_tlu_ctl.scala 3234:57]
|
|
assign io_csr_pkt_csr_mfdhs = _T_680 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3235:57]
|
|
assign io_csr_pkt_csr_dicawics = _T_696 & _T_27; // @[dec_tlu_ctl.scala 3236:57]
|
|
assign io_csr_pkt_csr_dicad0h = _T_704 & _T_17; // @[dec_tlu_ctl.scala 3237:57]
|
|
assign io_csr_pkt_csr_dicad0 = _T_715 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3238:57]
|
|
assign io_csr_pkt_csr_dicad1 = _T_726 & _T_27; // @[dec_tlu_ctl.scala 3239:57]
|
|
assign io_csr_pkt_csr_dicago = _T_726 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3240:57]
|
|
assign io_csr_pkt_presync = _T_807 | _T_822; // @[dec_tlu_ctl.scala 3241:34]
|
|
assign io_csr_pkt_postsync = _T_903 | _T_915; // @[dec_tlu_ctl.scala 3243:30]
|
|
assign io_csr_pkt_legal = _T_1565 | _T_1581; // @[dec_tlu_ctl.scala 3246:26]
|
|
endmodule
|
|
module dec_tlu_ctl(
|
|
input clock,
|
|
input reset,
|
|
output [29:0] io_tlu_exu_dec_tlu_meihap,
|
|
output io_tlu_exu_dec_tlu_flush_lower_r,
|
|
output [30:0] io_tlu_exu_dec_tlu_flush_path_r,
|
|
input [1:0] io_tlu_exu_exu_i0_br_hist_r,
|
|
input io_tlu_exu_exu_i0_br_error_r,
|
|
input io_tlu_exu_exu_i0_br_start_error_r,
|
|
input io_tlu_exu_exu_i0_br_valid_r,
|
|
input io_tlu_exu_exu_i0_br_mp_r,
|
|
input io_tlu_exu_exu_i0_br_middle_r,
|
|
input io_tlu_exu_exu_pmu_i0_br_misp,
|
|
input io_tlu_exu_exu_pmu_i0_br_ataken,
|
|
input io_tlu_exu_exu_pmu_i0_pc4,
|
|
input [30:0] io_tlu_exu_exu_npc_r,
|
|
input io_tlu_dma_dma_pmu_dccm_read,
|
|
input io_tlu_dma_dma_pmu_dccm_write,
|
|
input io_tlu_dma_dma_pmu_any_read,
|
|
input io_tlu_dma_dma_pmu_any_write,
|
|
output [2:0] io_tlu_dma_dec_tlu_dma_qos_prty,
|
|
input io_tlu_dma_dma_dccm_stall_any,
|
|
input io_tlu_dma_dma_iccm_stall_any,
|
|
input io_free_clk,
|
|
input io_free_l2clk,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
input io_lsu_fastint_stall_any,
|
|
input io_lsu_idle_any,
|
|
input io_dec_pmu_instr_decoded,
|
|
input io_dec_pmu_decode_stall,
|
|
input io_dec_pmu_presync_stall,
|
|
input io_dec_pmu_postsync_stall,
|
|
input io_lsu_store_stall_any,
|
|
input [30:0] io_lsu_fir_addr,
|
|
input [1:0] io_lsu_fir_error,
|
|
input io_iccm_dma_sb_error,
|
|
input io_lsu_error_pkt_r_valid,
|
|
input io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
input io_lsu_error_pkt_r_bits_inst_type,
|
|
input io_lsu_error_pkt_r_bits_exc_type,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
input io_lsu_single_ecc_error_incr,
|
|
input io_dec_pause_state,
|
|
input io_dec_csr_wen_unq_d,
|
|
input io_dec_csr_any_unq_d,
|
|
input [11:0] io_dec_csr_rdaddr_d,
|
|
input io_dec_csr_wen_r,
|
|
input [11:0] io_dec_csr_wraddr_r,
|
|
input [31:0] io_dec_csr_wrdata_r,
|
|
input io_dec_csr_stall_int_ff,
|
|
input io_dec_tlu_i0_valid_r,
|
|
input [30:0] io_dec_tlu_i0_pc_r,
|
|
input io_dec_tlu_packet_r_legal,
|
|
input io_dec_tlu_packet_r_icaf,
|
|
input io_dec_tlu_packet_r_icaf_second,
|
|
input [1:0] io_dec_tlu_packet_r_icaf_type,
|
|
input io_dec_tlu_packet_r_fence_i,
|
|
input [3:0] io_dec_tlu_packet_r_i0trigger,
|
|
input [3:0] io_dec_tlu_packet_r_pmu_i0_itype,
|
|
input io_dec_tlu_packet_r_pmu_i0_br_unpred,
|
|
input io_dec_tlu_packet_r_pmu_divide,
|
|
input io_dec_tlu_packet_r_pmu_lsu_misaligned,
|
|
input [31:0] io_dec_illegal_inst,
|
|
input io_dec_i0_decode_d,
|
|
input io_exu_i0_br_way_r,
|
|
output io_dec_dbg_cmd_done,
|
|
output io_dec_dbg_cmd_fail,
|
|
output io_dec_tlu_dbg_halted,
|
|
output io_dec_tlu_debug_mode,
|
|
output io_dec_tlu_resume_ack,
|
|
output io_dec_tlu_debug_stall,
|
|
output io_dec_tlu_mpc_halted_only,
|
|
output io_dec_tlu_flush_extint,
|
|
input io_dbg_halt_req,
|
|
input io_dbg_resume_req,
|
|
input io_dec_div_active,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output io_trigger_pkt_any_0_execute,
|
|
output io_trigger_pkt_any_0_m,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output io_trigger_pkt_any_1_execute,
|
|
output io_trigger_pkt_any_1_m,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output io_trigger_pkt_any_2_execute,
|
|
output io_trigger_pkt_any_2_m,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output io_trigger_pkt_any_3_execute,
|
|
output io_trigger_pkt_any_3_m,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
output [31:0] io_dec_csr_rddata_d,
|
|
output io_dec_csr_legal_d,
|
|
output io_dec_tlu_i0_kill_writeb_wb,
|
|
output io_dec_tlu_i0_kill_writeb_r,
|
|
output io_dec_tlu_wr_pause_r,
|
|
output io_dec_tlu_flush_pause_r,
|
|
output io_dec_tlu_presync_d,
|
|
output io_dec_tlu_postsync_d,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dec_tlu_i0_exc_valid_wb1,
|
|
output io_dec_tlu_i0_valid_wb1,
|
|
output io_dec_tlu_int_valid_wb1,
|
|
output [4:0] io_dec_tlu_exc_cause_wb1,
|
|
output [31:0] io_dec_tlu_mtval_wb1,
|
|
output io_dec_tlu_pipelining_disable,
|
|
output io_dec_tlu_trace_disable,
|
|
output io_dec_tlu_dec_clk_override,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_picio_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override,
|
|
output io_dec_tlu_flush_lower_wb,
|
|
input io_ifu_pmu_instr_aligned,
|
|
output io_tlu_bp_dec_tlu_br0_r_pkt_valid,
|
|
output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist,
|
|
output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error,
|
|
output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error,
|
|
output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way,
|
|
output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle,
|
|
output io_tlu_bp_dec_tlu_flush_leak_one_wb,
|
|
output io_tlu_bp_dec_tlu_bpred_disable,
|
|
output io_tlu_ifc_dec_tlu_flush_noredir_wb,
|
|
output [31:0] io_tlu_ifc_dec_tlu_mrac_ff,
|
|
input io_tlu_ifc_ifu_pmu_fetch_stall,
|
|
output io_tlu_mem_dec_tlu_flush_err_wb,
|
|
output io_tlu_mem_dec_tlu_i0_commit_cmt,
|
|
output io_tlu_mem_dec_tlu_force_halt,
|
|
output io_tlu_mem_dec_tlu_fence_i_wb,
|
|
output [70:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
output io_tlu_mem_dec_tlu_core_ecc_disable,
|
|
input io_tlu_mem_ifu_pmu_ic_miss,
|
|
input io_tlu_mem_ifu_pmu_ic_hit,
|
|
input io_tlu_mem_ifu_pmu_bus_error,
|
|
input io_tlu_mem_ifu_pmu_bus_busy,
|
|
input io_tlu_mem_ifu_pmu_bus_trxn,
|
|
input io_tlu_mem_ifu_ic_error_start,
|
|
input io_tlu_mem_ifu_iccm_rd_ecc_single_err,
|
|
input [70:0] io_tlu_mem_ifu_ic_debug_rd_data,
|
|
input io_tlu_mem_ifu_ic_debug_rd_data_valid,
|
|
input io_tlu_mem_ifu_miss_state_idle,
|
|
input io_tlu_busbuff_lsu_pmu_bus_trxn,
|
|
input io_tlu_busbuff_lsu_pmu_bus_misaligned,
|
|
input io_tlu_busbuff_lsu_pmu_bus_error,
|
|
input io_tlu_busbuff_lsu_pmu_bus_busy,
|
|
output io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
|
|
output io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
|
|
output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
|
|
input io_tlu_busbuff_lsu_imprecise_error_load_any,
|
|
input io_tlu_busbuff_lsu_imprecise_error_store_any,
|
|
input [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any,
|
|
input io_lsu_tlu_lsu_pmu_load_external_m,
|
|
input io_lsu_tlu_lsu_pmu_store_external_m,
|
|
input [7:0] io_dec_pic_pic_claimid,
|
|
input [3:0] io_dec_pic_pic_pl,
|
|
input io_dec_pic_mhwakeup,
|
|
output [3:0] io_dec_pic_dec_tlu_meicurpl,
|
|
output [3:0] io_dec_pic_dec_tlu_meipt,
|
|
input io_dec_pic_mexintpend
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire int_exc_clock; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_reset; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_ce_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_soft_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_reset; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [4:0] int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [4:0] int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [5:0] int_exc_io_mip; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [5:0] int_exc_io_mie_ns; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_mret_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [1:0] int_exc_io_lsu_fir_error; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_reset_delayed; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_nmi_int_detected; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [15:0] int_exc_io_dcsr; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_mtvec; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_pause_expired_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_nmi_vec; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_fence_i_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_take_halt; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_rst_vec; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_lsu_fir_addr; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_npc_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_mepc; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_debug_resume_req_f; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_dpc; // @[dec_tlu_ctl.scala 282:29]
|
|
wire [30:0] int_exc_io_npc_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ebreak_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_ecall_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_illegal_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_inst_acc_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 282:29]
|
|
wire int_exc_io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 282:29]
|
|
wire csr_clock; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_reset; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_free_l2clk; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_free_clk; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mret_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ext_int_freeze; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ic_perr_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_force_halt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 283:23]
|
|
wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 283:23]
|
|
wire [3:0] csr_io_trigger_enabled; // @[dec_tlu_ctl.scala 283:23]
|
|
wire int_timers_clock; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_reset; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_free_l2clk; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_wr_clk; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 284:30]
|
|
wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 284:30]
|
|
wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 284:30]
|
|
wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 284:30]
|
|
wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 284:30]
|
|
wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1017:28]
|
|
wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1017:28]
|
|
reg dbg_halt_state_f; // @[Reg.scala 27:20]
|
|
wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 281:39]
|
|
reg mpc_halt_state_f; // @[Reg.scala 27:20]
|
|
wire _T_1 = _T & mpc_halt_state_f; // @[dec_tlu_ctl.scala 281:57]
|
|
wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58]
|
|
reg [6:0] _T_8; // @[lib.scala 37:81]
|
|
reg [6:0] syncro_ff; // @[lib.scala 37:58]
|
|
wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 311:75]
|
|
wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 314:59]
|
|
wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 315:59]
|
|
wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 316:51]
|
|
wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 317:59]
|
|
wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1010:37]
|
|
reg debug_mode_status; // @[Reg.scala 27:20]
|
|
reg i_cpu_run_req_d1_raw; // @[Reg.scala 27:20]
|
|
reg nmi_int_delayed; // @[Reg.scala 27:20]
|
|
wire _T_76 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 360:45]
|
|
wire _T_77 = nmi_int_sync & _T_76; // @[dec_tlu_ctl.scala 360:43]
|
|
wire mdseac_locked_f = csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 965:27]
|
|
wire _T_72 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 357:32]
|
|
wire _T_73 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 357:96]
|
|
wire _T_74 = _T_72 & _T_73; // @[dec_tlu_ctl.scala 357:49]
|
|
reg nmi_int_detected_f; // @[Reg.scala 27:20]
|
|
wire _T_99 = ~nmi_int_detected_f; // @[dec_tlu_ctl.scala 365:25]
|
|
wire _T_100 = _T_99 & csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 365:45]
|
|
wire _T_101 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 365:95]
|
|
wire nmi_fir_type = _T_100 & _T_101; // @[dec_tlu_ctl.scala 365:76]
|
|
wire _T_75 = ~nmi_fir_type; // @[dec_tlu_ctl.scala 357:146]
|
|
wire nmi_lsu_detected = _T_74 & _T_75; // @[dec_tlu_ctl.scala 357:144]
|
|
wire _T_78 = _T_77 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 360:63]
|
|
wire take_nmi_r_d1 = int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 814:43]
|
|
wire _T_79 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 360:106]
|
|
wire _T_80 = nmi_int_detected_f & _T_79; // @[dec_tlu_ctl.scala 360:104]
|
|
wire _T_81 = _T_78 | _T_80; // @[dec_tlu_ctl.scala 360:82]
|
|
wire nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 360:122]
|
|
wire timer_int_ready = int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 784:43]
|
|
wire _T_576 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 633:71]
|
|
wire soft_int_ready = int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 783:43]
|
|
wire _T_577 = _T_576 | soft_int_ready; // @[dec_tlu_ctl.scala 633:89]
|
|
reg int_timer0_int_hold_f; // @[Reg.scala 27:20]
|
|
wire _T_578 = _T_577 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 633:106]
|
|
reg int_timer1_int_hold_f; // @[Reg.scala 27:20]
|
|
wire _T_579 = _T_578 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 633:130]
|
|
wire mhwakeup_ready = int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 780:43]
|
|
wire _T_580 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 633:177]
|
|
wire _T_581 = _T_579 | _T_580; // @[dec_tlu_ctl.scala 633:154]
|
|
wire _T_582 = _T_581 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 633:196]
|
|
reg i_cpu_halt_req_d1; // @[Reg.scala 27:20]
|
|
wire _T_583 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 633:221]
|
|
wire _T_584 = _T_582 & _T_583; // @[dec_tlu_ctl.scala 633:219]
|
|
wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 633:50]
|
|
wire interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 816:43]
|
|
wire interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 812:43]
|
|
reg reset_detect; // @[Reg.scala 27:20]
|
|
reg reset_detected; // @[Reg.scala 27:20]
|
|
wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 369:64]
|
|
wire _T_345 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 504:28]
|
|
reg dec_pause_state_f; // @[Reg.scala 27:20]
|
|
wire _T_346 = _T_345 & dec_pause_state_f; // @[dec_tlu_ctl.scala 504:48]
|
|
wire ext_int_ready = int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 781:43]
|
|
wire ce_int_ready = int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 782:43]
|
|
wire _T_347 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 504:86]
|
|
wire _T_348 = _T_347 | timer_int_ready; // @[dec_tlu_ctl.scala 504:101]
|
|
wire _T_349 = _T_348 | soft_int_ready; // @[dec_tlu_ctl.scala 504:119]
|
|
wire _T_350 = _T_349 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 504:136]
|
|
wire _T_351 = _T_350 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 504:160]
|
|
wire _T_352 = _T_351 | nmi_int_detected; // @[dec_tlu_ctl.scala 504:184]
|
|
wire _T_353 = _T_352 | csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 504:203]
|
|
wire _T_354 = ~_T_353; // @[dec_tlu_ctl.scala 504:70]
|
|
wire _T_355 = _T_346 & _T_354; // @[dec_tlu_ctl.scala 504:68]
|
|
wire _T_356 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 504:233]
|
|
wire _T_357 = _T_355 & _T_356; // @[dec_tlu_ctl.scala 504:231]
|
|
reg debug_halt_req_f; // @[Reg.scala 27:20]
|
|
wire _T_358 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 504:257]
|
|
wire _T_359 = _T_357 & _T_358; // @[dec_tlu_ctl.scala 504:255]
|
|
reg pmu_fw_halt_req_f; // @[Reg.scala 27:20]
|
|
wire _T_360 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 504:277]
|
|
wire _T_361 = _T_359 & _T_360; // @[dec_tlu_ctl.scala 504:275]
|
|
reg halt_taken_f; // @[Reg.scala 27:20]
|
|
wire _T_362 = ~halt_taken_f; // @[dec_tlu_ctl.scala 504:298]
|
|
reg ifu_ic_error_start_f; // @[Reg.scala 27:20]
|
|
wire _T_680 = ~csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 709:49]
|
|
wire _T_681 = ifu_ic_error_start_f & _T_680; // @[dec_tlu_ctl.scala 709:47]
|
|
wire _T_682 = ~debug_mode_status; // @[dec_tlu_ctl.scala 709:78]
|
|
reg debug_resume_req_f_raw; // @[Reg.scala 27:20]
|
|
wire _T_333 = ~io_dbg_halt_req; // @[dec_tlu_ctl.scala 489:56]
|
|
wire debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 489:54]
|
|
wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1013:37]
|
|
wire _T_255 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 459:60]
|
|
reg dcsr_single_step_running_f; // @[Reg.scala 27:20]
|
|
reg dcsr_single_step_done_f; // @[Reg.scala 27:20]
|
|
wire _T_256 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 459:111]
|
|
wire _T_257 = dcsr_single_step_running_f & _T_256; // @[dec_tlu_ctl.scala 459:109]
|
|
wire dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 459:79]
|
|
wire _T_683 = _T_682 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 709:104]
|
|
wire _T_684 = _T_681 & _T_683; // @[dec_tlu_ctl.scala 709:75]
|
|
reg internal_pmu_fw_halt_mode_f; // @[Reg.scala 27:20]
|
|
wire _T_685 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 709:134]
|
|
wire ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 709:132]
|
|
reg ifu_iccm_rd_ecc_single_err_f; // @[Reg.scala 27:20]
|
|
wire _T_688 = ifu_iccm_rd_ecc_single_err_f & _T_680; // @[dec_tlu_ctl.scala 710:55]
|
|
wire _T_691 = _T_688 & _T_683; // @[dec_tlu_ctl.scala 710:83]
|
|
wire iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 710:140]
|
|
wire _T_23 = io_tlu_mem_ifu_ic_error_start ^ ifu_ic_error_start_f; // @[lib.scala 488:21]
|
|
wire _T_24 = |_T_23; // @[lib.scala 488:29]
|
|
wire _T_26 = io_tlu_mem_ifu_iccm_rd_ecc_single_err ^ ifu_iccm_rd_ecc_single_err_f; // @[lib.scala 488:21]
|
|
wire _T_27 = |_T_26; // @[lib.scala 488:29]
|
|
reg iccm_repair_state_d1; // @[Reg.scala 27:20]
|
|
wire _T_623 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 666:72]
|
|
wire _T_624 = iccm_repair_state_d1 & _T_623; // @[dec_tlu_ctl.scala 666:70]
|
|
wire iccm_repair_state_ns = iccm_sbecc_r | _T_624; // @[dec_tlu_ctl.scala 666:46]
|
|
wire _T_29 = iccm_repair_state_ns ^ iccm_repair_state_d1; // @[lib.scala 466:21]
|
|
wire _T_30 = |_T_29; // @[lib.scala 466:29]
|
|
reg dbg_halt_req_held; // @[Reg.scala 27:20]
|
|
wire _T_184 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 418:48]
|
|
wire dbg_halt_req_final = _T_184 & _T_680; // @[dec_tlu_ctl.scala 418:69]
|
|
wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_680; // @[dec_tlu_ctl.scala 376:67]
|
|
wire _T_187 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 421:50]
|
|
wire _T_188 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 421:95]
|
|
wire _T_189 = reset_delayed & _T_188; // @[dec_tlu_ctl.scala 421:93]
|
|
wire _T_190 = _T_187 | _T_189; // @[dec_tlu_ctl.scala 421:76]
|
|
wire _T_192 = _T_190 & _T_682; // @[dec_tlu_ctl.scala 421:119]
|
|
wire debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 421:147]
|
|
wire _T_231 = _T_682 & debug_halt_req; // @[dec_tlu_ctl.scala 441:63]
|
|
wire _T_232 = _T_231 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 441:81]
|
|
reg trigger_hit_dmode_r_d1; // @[Reg.scala 27:20]
|
|
wire _T_233 = _T_232 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 441:107]
|
|
reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 718:64]
|
|
wire enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 441:132]
|
|
wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1007:37]
|
|
reg lsu_idle_any_f; // @[Reg.scala 27:20]
|
|
wire _T_220 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 435:53]
|
|
wire _T_221 = _T_220 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 435:70]
|
|
reg ifu_miss_state_idle_f; // @[Reg.scala 27:20]
|
|
wire _T_222 = _T_221 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 435:103]
|
|
wire _T_223 = ~debug_halt_req; // @[dec_tlu_ctl.scala 435:129]
|
|
wire _T_224 = _T_222 & _T_223; // @[dec_tlu_ctl.scala 435:127]
|
|
reg debug_halt_req_d1; // @[Reg.scala 27:20]
|
|
wire _T_225 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 435:147]
|
|
wire _T_226 = _T_224 & _T_225; // @[dec_tlu_ctl.scala 435:145]
|
|
wire _T_227 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 435:168]
|
|
wire _T_228 = _T_226 & _T_227; // @[dec_tlu_ctl.scala 435:166]
|
|
wire core_empty = force_halt | _T_228; // @[dec_tlu_ctl.scala 435:34]
|
|
wire _T_241 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 452:48]
|
|
reg dec_tlu_flush_noredir_r_d1; // @[Reg.scala 27:20]
|
|
reg dec_tlu_flush_pause_r_d1; // @[Reg.scala 27:20]
|
|
wire _T_210 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 431:56]
|
|
wire _T_211 = dec_tlu_flush_noredir_r_d1 & _T_210; // @[dec_tlu_ctl.scala 431:54]
|
|
wire _T_212 = ~csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 431:84]
|
|
wire _T_213 = _T_211 & _T_212; // @[dec_tlu_ctl.scala 431:82]
|
|
reg dbg_tlu_halted_f; // @[Reg.scala 27:20]
|
|
wire _T_214 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 431:133]
|
|
wire _T_215 = halt_taken_f & _T_214; // @[dec_tlu_ctl.scala 431:131]
|
|
reg pmu_fw_tlu_halted_f; // @[Reg.scala 27:20]
|
|
wire _T_216 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 431:153]
|
|
wire _T_217 = _T_215 & _T_216; // @[dec_tlu_ctl.scala 431:151]
|
|
wire _T_219 = _T_217 & _T_356; // @[dec_tlu_ctl.scala 431:174]
|
|
wire halt_taken = _T_213 | _T_219; // @[dec_tlu_ctl.scala 431:115]
|
|
wire _T_242 = _T_241 & halt_taken; // @[dec_tlu_ctl.scala 452:61]
|
|
wire _T_243 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 452:97]
|
|
wire _T_244 = dbg_tlu_halted_f & _T_243; // @[dec_tlu_ctl.scala 452:95]
|
|
wire dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 452:75]
|
|
wire _T_245 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 454:73]
|
|
wire _T_246 = debug_halt_req_f & _T_245; // @[dec_tlu_ctl.scala 454:71]
|
|
wire debug_halt_req_ns = enter_debug_halt_req | _T_246; // @[dec_tlu_ctl.scala 454:51]
|
|
wire _T_235 = ~dcsr[2]; // @[dec_tlu_ctl.scala 444:106]
|
|
wire _T_236 = debug_resume_req_f & _T_235; // @[dec_tlu_ctl.scala 444:104]
|
|
wire _T_237 = ~_T_236; // @[dec_tlu_ctl.scala 444:83]
|
|
wire _T_238 = debug_mode_status & _T_237; // @[dec_tlu_ctl.scala 444:81]
|
|
wire internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 444:53]
|
|
wire _T_37 = internal_dbg_halt_mode ^ debug_mode_status; // @[lib.scala 466:21]
|
|
wire _T_38 = |_T_37; // @[lib.scala 466:29]
|
|
reg lsu_pmu_load_external_r; // @[Reg.scala 27:20]
|
|
wire _T_40 = io_lsu_tlu_lsu_pmu_load_external_m ^ lsu_pmu_load_external_r; // @[lib.scala 488:21]
|
|
wire _T_41 = |_T_40; // @[lib.scala 488:29]
|
|
reg lsu_pmu_store_external_r; // @[Reg.scala 27:20]
|
|
wire _T_43 = io_lsu_tlu_lsu_pmu_store_external_m ^ lsu_pmu_store_external_r; // @[lib.scala 488:21]
|
|
wire _T_44 = |_T_43; // @[lib.scala 488:29]
|
|
wire tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 808:43]
|
|
reg tlu_flush_lower_r_d1; // @[Reg.scala 27:20]
|
|
wire _T_46 = tlu_flush_lower_r ^ tlu_flush_lower_r_d1; // @[lib.scala 466:21]
|
|
wire _T_47 = |_T_46; // @[lib.scala 466:29]
|
|
wire _T_611 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 663:49]
|
|
wire _T_612 = io_dec_tlu_i0_valid_r & _T_611; // @[dec_tlu_ctl.scala 663:47]
|
|
wire _T_613 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 663:103]
|
|
wire _T_614 = _T_612 & _T_613; // @[dec_tlu_ctl.scala 663:71]
|
|
wire _T_615 = ic_perr_r | iccm_sbecc_r; // @[dec_tlu_ctl.scala 663:156]
|
|
wire _T_617 = _T_615 & _T_680; // @[dec_tlu_ctl.scala 663:172]
|
|
wire _T_618 = _T_614 | _T_617; // @[dec_tlu_ctl.scala 663:142]
|
|
wire _T_431 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 545:64]
|
|
wire [3:0] _T_433 = _T_431 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_434 = ~_T_433; // @[dec_tlu_ctl.scala 545:29]
|
|
wire [3:0] _T_426 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_428 = _T_426 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 543:58]
|
|
wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39]
|
|
wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39]
|
|
wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39]
|
|
wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39]
|
|
wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_413 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 535:62]
|
|
wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 712:54]
|
|
wire [3:0] _T_415 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_416 = _T_413 & _T_415; // @[dec_tlu_ctl.scala 535:77]
|
|
wire [3:0] _T_419 = _T_613 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_420 = _T_416 | _T_419; // @[dec_tlu_ctl.scala 535:103]
|
|
wire [3:0] i0_iside_trigger_has_pri_r = ~_T_420; // @[dec_tlu_ctl.scala 535:43]
|
|
wire [3:0] _T_429 = _T_428 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:95]
|
|
wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_421 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 538:56]
|
|
wire [3:0] _T_423 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_424 = _T_421 & _T_423; // @[dec_tlu_ctl.scala 538:71]
|
|
wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_424; // @[dec_tlu_ctl.scala 538:40]
|
|
wire [3:0] _T_430 = _T_429 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:124]
|
|
wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1012:37]
|
|
wire _T_393 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 529:70]
|
|
wire _T_395 = _T_393 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 529:94]
|
|
wire _T_398 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 530:47]
|
|
wire _T_400 = _T_398 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 530:71]
|
|
wire [1:0] _T_412 = {_T_395,_T_400}; // @[Cat.scala 29:58]
|
|
wire _T_403 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 531:47]
|
|
wire _T_405 = _T_403 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 531:71]
|
|
wire _T_408 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 532:47]
|
|
wire _T_410 = _T_408 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 532:71]
|
|
wire [1:0] _T_411 = {_T_405,_T_410}; // @[Cat.scala 29:58]
|
|
wire [3:0] trigger_enabled = {_T_395,_T_400,_T_405,_T_410}; // @[Cat.scala 29:58]
|
|
wire [3:0] i0trigger_qual_r = _T_430 & trigger_enabled; // @[dec_tlu_ctl.scala 543:151]
|
|
wire [3:0] i0_trigger_r = _T_434 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 545:90]
|
|
wire _T_437 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 548:65]
|
|
wire _T_439 = _T_437 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 548:94]
|
|
wire _T_440 = i0_trigger_r[3] & _T_439; // @[dec_tlu_ctl.scala 548:62]
|
|
wire _T_445 = _T_437 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 549:65]
|
|
wire _T_446 = i0_trigger_r[2] & _T_445; // @[dec_tlu_ctl.scala 549:33]
|
|
wire _T_449 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 550:36]
|
|
wire _T_451 = _T_449 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 550:65]
|
|
wire _T_452 = i0_trigger_r[1] & _T_451; // @[dec_tlu_ctl.scala 550:33]
|
|
wire _T_457 = _T_449 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 551:65]
|
|
wire _T_458 = i0_trigger_r[0] & _T_457; // @[dec_tlu_ctl.scala 551:33]
|
|
wire [3:0] i0_trigger_chain_masked_r = {_T_440,_T_446,_T_452,_T_458}; // @[Cat.scala 29:58]
|
|
wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 555:62]
|
|
wire _T_619 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 663:205]
|
|
wire _T_620 = _T_618 & _T_619; // @[dec_tlu_ctl.scala 663:202]
|
|
wire _T_592 = io_dec_tlu_i0_valid_r & _T_619; // @[dec_tlu_ctl.scala 651:52]
|
|
wire _T_593 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 651:75]
|
|
wire _T_594 = _T_593 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 651:110]
|
|
wire lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 651:72]
|
|
wire _T_621 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 663:226]
|
|
wire rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 663:223]
|
|
wire _T_586 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 642:62]
|
|
wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_586; // @[dec_tlu_ctl.scala 642:60]
|
|
wire _T_587 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 644:45]
|
|
wire _T_589 = _T_587 & _T_619; // @[dec_tlu_ctl.scala 644:67]
|
|
wire _T_590 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 644:89]
|
|
wire lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 644:87]
|
|
wire _T_606 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 657:43]
|
|
wire _T_696 = inst_acc_r_raw & _T_590; // @[dec_tlu_ctl.scala 713:38]
|
|
wire inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 713:51]
|
|
wire _T_607 = _T_606 | inst_acc_r; // @[dec_tlu_ctl.scala 657:58]
|
|
wire _T_663 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 705:23]
|
|
wire _T_664 = _T_663 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 705:52]
|
|
wire _T_666 = _T_664 & _T_619; // @[dec_tlu_ctl.scala 705:76]
|
|
wire illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 705:96]
|
|
wire _T_608 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 657:84]
|
|
wire _T_609 = _T_607 | _T_608; // @[dec_tlu_ctl.scala 657:71]
|
|
wire tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 657:109]
|
|
reg _T_52; // @[Reg.scala 27:20]
|
|
wire _T_50 = tlu_i0_kill_writeb_r ^ _T_52; // @[lib.scala 466:21]
|
|
wire _T_51 = |_T_50; // @[lib.scala 466:29]
|
|
reg internal_dbg_halt_mode_f2; // @[Reg.scala 27:20]
|
|
wire _T_53 = debug_mode_status ^ internal_dbg_halt_mode_f2; // @[lib.scala 466:21]
|
|
wire _T_54 = |_T_53; // @[lib.scala 466:29]
|
|
reg _T_59; // @[Reg.scala 27:20]
|
|
wire _T_57 = force_halt ^ _T_59; // @[lib.scala 466:21]
|
|
wire _T_58 = |_T_57; // @[lib.scala 466:29]
|
|
wire _T_60 = nmi_int_sync ^ nmi_int_delayed; // @[lib.scala 488:21]
|
|
wire _T_61 = |_T_60; // @[lib.scala 488:29]
|
|
wire _T_63 = nmi_int_detected ^ nmi_int_detected_f; // @[lib.scala 466:21]
|
|
wire _T_64 = |_T_63; // @[lib.scala 466:29]
|
|
wire _T_83 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 362:49]
|
|
wire _T_86 = ~_T_80; // @[dec_tlu_ctl.scala 362:98]
|
|
wire _T_87 = _T_83 & _T_86; // @[dec_tlu_ctl.scala 362:95]
|
|
reg nmi_lsu_load_type_f; // @[Reg.scala 27:20]
|
|
wire _T_89 = nmi_lsu_load_type_f & _T_79; // @[dec_tlu_ctl.scala 362:162]
|
|
wire nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 362:138]
|
|
wire _T_66 = nmi_lsu_load_type ^ nmi_lsu_load_type_f; // @[lib.scala 466:21]
|
|
wire _T_67 = |_T_66; // @[lib.scala 466:29]
|
|
wire _T_91 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 363:49]
|
|
wire _T_95 = _T_91 & _T_86; // @[dec_tlu_ctl.scala 363:96]
|
|
reg nmi_lsu_store_type_f; // @[Reg.scala 27:20]
|
|
wire _T_97 = nmi_lsu_store_type_f & _T_79; // @[dec_tlu_ctl.scala 363:162]
|
|
wire nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 363:138]
|
|
wire _T_69 = nmi_lsu_store_type ^ nmi_lsu_store_type_f; // @[lib.scala 466:21]
|
|
wire _T_70 = |_T_69; // @[lib.scala 466:29]
|
|
wire _T_103 = 1'h1 ^ reset_detect; // @[lib.scala 466:21]
|
|
wire _T_104 = |_T_103; // @[lib.scala 466:29]
|
|
wire _T_107 = |reset_delayed; // @[lib.scala 466:29]
|
|
reg mpc_debug_halt_req_sync_f; // @[Reg.scala 27:20]
|
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wire _T_111 = mpc_debug_halt_req_sync ^ mpc_debug_halt_req_sync_f; // @[lib.scala 488:21]
|
|
wire _T_112 = |_T_111; // @[lib.scala 488:29]
|
|
reg mpc_debug_run_req_sync_f; // @[Reg.scala 27:20]
|
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wire _T_114 = mpc_debug_run_req_sync ^ mpc_debug_run_req_sync_f; // @[lib.scala 488:21]
|
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wire _T_115 = |_T_114; // @[lib.scala 488:29]
|
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wire _T_144 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 390:71]
|
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wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_144; // @[dec_tlu_ctl.scala 390:69]
|
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wire _T_146 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 393:48]
|
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wire _T_149 = _T_146 | _T_189; // @[dec_tlu_ctl.scala 393:80]
|
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wire _T_150 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 393:125]
|
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wire mpc_halt_state_ns = _T_149 & _T_150; // @[dec_tlu_ctl.scala 393:123]
|
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wire _T_118 = mpc_halt_state_ns ^ mpc_halt_state_f; // @[lib.scala 466:21]
|
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wire _T_119 = |_T_118; // @[lib.scala 466:29]
|
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reg mpc_run_state_f; // @[Reg.scala 27:20]
|
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wire _T_145 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 391:70]
|
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wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_145; // @[dec_tlu_ctl.scala 391:68]
|
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reg mpc_debug_run_ack_f; // @[Reg.scala 27:20]
|
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wire _T_152 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 394:80]
|
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wire _T_153 = mpc_debug_run_req_sync_pulse & _T_152; // @[dec_tlu_ctl.scala 394:78]
|
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wire _T_154 = mpc_run_state_f | _T_153; // @[dec_tlu_ctl.scala 394:46]
|
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wire _T_155 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 394:133]
|
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wire _T_156 = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 394:131]
|
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wire mpc_run_state_ns = _T_154 & _T_156; // @[dec_tlu_ctl.scala 394:103]
|
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wire _T_121 = mpc_run_state_ns ^ mpc_run_state_f; // @[lib.scala 466:21]
|
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wire _T_122 = |_T_121; // @[lib.scala 466:29]
|
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wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 404:59]
|
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reg debug_brkpt_status_f; // @[Reg.scala 27:20]
|
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wire _T_170 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 405:53]
|
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wire _T_172 = internal_dbg_halt_mode & _T_155; // @[dec_tlu_ctl.scala 405:103]
|
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wire debug_brkpt_status_ns = _T_170 & _T_172; // @[dec_tlu_ctl.scala 405:77]
|
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wire _T_124 = debug_brkpt_status_ns ^ debug_brkpt_status_f; // @[lib.scala 466:21]
|
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wire _T_125 = |_T_124; // @[lib.scala 466:29]
|
|
wire _T_174 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 408:51]
|
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wire _T_175 = _T_174 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 408:78]
|
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wire mpc_debug_halt_ack_ns = _T_175 & core_empty; // @[dec_tlu_ctl.scala 408:104]
|
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reg mpc_debug_halt_ack_f; // @[Reg.scala 27:20]
|
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wire _T_127 = mpc_debug_halt_ack_ns ^ mpc_debug_halt_ack_f; // @[lib.scala 466:21]
|
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wire _T_128 = |_T_127; // @[lib.scala 466:29]
|
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wire _T_158 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 397:70]
|
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wire _T_159 = _T_158 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 397:96]
|
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wire _T_160 = _T_159 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 397:121]
|
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wire _T_161 = dbg_halt_state_f | _T_160; // @[dec_tlu_ctl.scala 397:48]
|
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wire _T_162 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 397:153]
|
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wire dbg_halt_state_ns = _T_161 & _T_162; // @[dec_tlu_ctl.scala 397:151]
|
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wire _T_177 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 409:59]
|
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wire _T_178 = mpc_debug_run_req_sync & _T_177; // @[dec_tlu_ctl.scala 409:57]
|
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wire _T_179 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 409:80]
|
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wire _T_180 = _T_178 & _T_179; // @[dec_tlu_ctl.scala 409:78]
|
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wire _T_181 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 409:129]
|
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wire mpc_debug_run_ack_ns = _T_180 | _T_181; // @[dec_tlu_ctl.scala 409:106]
|
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wire _T_130 = mpc_debug_run_ack_ns ^ mpc_debug_run_ack_f; // @[lib.scala 466:21]
|
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wire _T_131 = |_T_130; // @[lib.scala 466:29]
|
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wire _T_134 = dbg_halt_state_ns ^ dbg_halt_state_f; // @[lib.scala 466:21]
|
|
wire _T_135 = |_T_134; // @[lib.scala 466:29]
|
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reg dbg_run_state_f; // @[Reg.scala 27:20]
|
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wire _T_164 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 398:46]
|
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wire dbg_run_state_ns = _T_164 & _T_156; // @[dec_tlu_ctl.scala 398:67]
|
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wire _T_137 = dbg_run_state_ns ^ dbg_run_state_f; // @[lib.scala 466:21]
|
|
wire _T_138 = |_T_137; // @[lib.scala 466:29]
|
|
reg _T_143; // @[Reg.scala 27:20]
|
|
wire _T_141 = _T_1 ^ _T_143; // @[lib.scala 466:21]
|
|
wire _T_142 = |_T_141; // @[lib.scala 466:29]
|
|
wire dbg_halt_req_held_ns = _T_184 & csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 417:74]
|
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wire _T_196 = mpc_run_state_ns & _T_177; // @[dec_tlu_ctl.scala 423:73]
|
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wire _T_197 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 423:117]
|
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wire _T_198 = dbg_run_state_ns & _T_197; // @[dec_tlu_ctl.scala 423:115]
|
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wire _T_199 = _T_196 | _T_198; // @[dec_tlu_ctl.scala 423:95]
|
|
wire debug_resume_req = _T_243 & _T_199; // @[dec_tlu_ctl.scala 423:52]
|
|
wire _T_200 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 428:43]
|
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wire synchronous_flush_r = int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 807:43]
|
|
wire _T_201 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 428:66]
|
|
wire _T_202 = _T_200 & _T_201; // @[dec_tlu_ctl.scala 428:64]
|
|
wire _T_669 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 706:57]
|
|
wire _T_670 = _T_669 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 706:70]
|
|
wire _T_672 = _T_670 & _T_619; // @[dec_tlu_ctl.scala 706:94]
|
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wire mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 706:114]
|
|
wire _T_203 = ~mret_r; // @[dec_tlu_ctl.scala 428:89]
|
|
wire _T_204 = _T_202 & _T_203; // @[dec_tlu_ctl.scala 428:87]
|
|
wire _T_206 = _T_204 & _T_362; // @[dec_tlu_ctl.scala 428:97]
|
|
wire _T_207 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 428:115]
|
|
wire _T_208 = _T_206 & _T_207; // @[dec_tlu_ctl.scala 428:113]
|
|
wire take_reset = int_exc_io_take_reset; // @[dec_tlu_ctl.scala 805:43]
|
|
wire _T_209 = ~take_reset; // @[dec_tlu_ctl.scala 428:145]
|
|
wire take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 428:143]
|
|
wire _T_248 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 455:49]
|
|
wire resume_ack_ns = _T_248 & dbg_run_state_ns; // @[dec_tlu_ctl.scala 455:68]
|
|
wire _T_249 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 457:61]
|
|
wire _T_250 = io_dec_tlu_i0_valid_r & _T_249; // @[dec_tlu_ctl.scala 457:59]
|
|
wire _T_252 = _T_250 & dcsr[2]; // @[dec_tlu_ctl.scala 457:84]
|
|
wire dcsr_single_step_done = _T_252 & _T_590; // @[dec_tlu_ctl.scala 457:102]
|
|
wire _T_463 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 561:69]
|
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wire _T_466 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 562:46]
|
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wire _T_469 = _T_466 & _T_437; // @[dec_tlu_ctl.scala 562:76]
|
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wire _T_472 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 563:46]
|
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wire _T_475 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 564:46]
|
|
wire _T_478 = _T_475 & _T_449; // @[dec_tlu_ctl.scala 564:76]
|
|
wire [3:0] trigger_action = {_T_463,_T_469,_T_472,_T_478}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_493 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 570:62]
|
|
wire i0_trigger_action_r = |_T_493; // @[dec_tlu_ctl.scala 570:80]
|
|
wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 572:50]
|
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wire _T_699 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 716:69]
|
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wire _T_700 = _T_699 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 716:82]
|
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wire _T_702 = _T_700 & _T_619; // @[dec_tlu_ctl.scala 716:106]
|
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wire _T_704 = _T_702 & dcsr[15]; // @[dec_tlu_ctl.scala 716:126]
|
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wire ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 716:147]
|
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wire _T_258 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 464:57]
|
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reg request_debug_mode_r_d1; // @[Reg.scala 27:20]
|
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wire _T_260 = request_debug_mode_r_d1 & _T_586; // @[dec_tlu_ctl.scala 464:110]
|
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wire request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 464:83]
|
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reg request_debug_mode_done_f; // @[Reg.scala 27:20]
|
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wire _T_261 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 466:64]
|
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wire request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 466:93]
|
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wire _T_264 = io_tlu_ifc_dec_tlu_flush_noredir_wb ^ dec_tlu_flush_noredir_r_d1; // @[lib.scala 488:21]
|
|
wire _T_265 = |_T_264; // @[lib.scala 488:29]
|
|
wire _T_268 = halt_taken ^ halt_taken_f; // @[lib.scala 466:21]
|
|
wire _T_269 = |_T_268; // @[lib.scala 466:29]
|
|
wire _T_272 = io_lsu_idle_any ^ lsu_idle_any_f; // @[lib.scala 466:21]
|
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wire _T_273 = |_T_272; // @[lib.scala 466:29]
|
|
wire _T_276 = io_tlu_mem_ifu_miss_state_idle ^ ifu_miss_state_idle_f; // @[lib.scala 488:21]
|
|
wire _T_277 = |_T_276; // @[lib.scala 488:29]
|
|
wire _T_280 = dbg_tlu_halted ^ dbg_tlu_halted_f; // @[lib.scala 466:21]
|
|
wire _T_281 = |_T_280; // @[lib.scala 466:29]
|
|
reg _T_286; // @[Reg.scala 27:20]
|
|
wire _T_284 = resume_ack_ns ^ _T_286; // @[lib.scala 466:21]
|
|
wire _T_285 = |_T_284; // @[lib.scala 466:29]
|
|
wire _T_288 = debug_halt_req_ns ^ debug_halt_req_f; // @[lib.scala 466:21]
|
|
wire _T_289 = |_T_288; // @[lib.scala 466:29]
|
|
wire _T_292 = debug_resume_req ^ debug_resume_req_f_raw; // @[lib.scala 466:21]
|
|
wire _T_293 = |_T_292; // @[lib.scala 466:29]
|
|
wire _T_296 = trigger_hit_dmode_r ^ trigger_hit_dmode_r_d1; // @[lib.scala 466:21]
|
|
wire _T_297 = |_T_296; // @[lib.scala 466:29]
|
|
wire _T_300 = dcsr_single_step_done ^ dcsr_single_step_done_f; // @[lib.scala 466:21]
|
|
wire _T_301 = |_T_300; // @[lib.scala 466:29]
|
|
wire _T_304 = debug_halt_req ^ debug_halt_req_d1; // @[lib.scala 466:21]
|
|
wire _T_305 = |_T_304; // @[lib.scala 466:29]
|
|
reg dec_tlu_wr_pause_r_d1; // @[Reg.scala 27:20]
|
|
wire _T_307 = io_dec_tlu_wr_pause_r ^ dec_tlu_wr_pause_r_d1; // @[lib.scala 466:21]
|
|
wire _T_308 = |_T_307; // @[lib.scala 466:29]
|
|
wire _T_310 = io_dec_pause_state ^ dec_pause_state_f; // @[lib.scala 466:21]
|
|
wire _T_311 = |_T_310; // @[lib.scala 466:29]
|
|
wire _T_314 = request_debug_mode_r ^ request_debug_mode_r_d1; // @[lib.scala 466:21]
|
|
wire _T_315 = |_T_314; // @[lib.scala 466:29]
|
|
wire _T_318 = request_debug_mode_done ^ request_debug_mode_done_f; // @[lib.scala 466:21]
|
|
wire _T_319 = |_T_318; // @[lib.scala 466:29]
|
|
wire _T_322 = dcsr_single_step_running ^ dcsr_single_step_running_f; // @[lib.scala 466:21]
|
|
wire _T_323 = |_T_322; // @[lib.scala 466:29]
|
|
wire _T_326 = io_dec_tlu_flush_pause_r ^ dec_tlu_flush_pause_r_d1; // @[lib.scala 466:21]
|
|
wire _T_327 = |_T_326; // @[lib.scala 466:29]
|
|
wire _T_330 = dbg_halt_req_held_ns ^ dbg_halt_req_held; // @[lib.scala 466:21]
|
|
wire _T_331 = |_T_330; // @[lib.scala 466:29]
|
|
wire _T_675 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 708:55]
|
|
wire _T_677 = _T_675 & _T_619; // @[dec_tlu_ctl.scala 708:79]
|
|
wire fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 708:100]
|
|
wire _T_335 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 497:71]
|
|
wire _T_336 = take_halt | _T_335; // @[dec_tlu_ctl.scala 497:58]
|
|
wire _T_337 = _T_336 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 497:97]
|
|
wire _T_338 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 497:144]
|
|
wire _T_339 = _T_337 | _T_338; // @[dec_tlu_ctl.scala 497:124]
|
|
wire take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 788:43]
|
|
wire _T_341 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 502:61]
|
|
wire _T_342 = dec_tlu_wr_pause_r_d1 & _T_341; // @[dec_tlu_ctl.scala 502:59]
|
|
wire _T_343 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 502:82]
|
|
wire _T_365 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 506:82]
|
|
wire _T_366 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 506:125]
|
|
wire _T_367 = _T_365 & _T_366; // @[dec_tlu_ctl.scala 506:100]
|
|
wire _T_368 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 506:155]
|
|
wire _T_481 = |i0_trigger_r; // @[dec_tlu_ctl.scala 567:59]
|
|
wire _T_483 = _T_481 & _T_590; // @[dec_tlu_ctl.scala 567:63]
|
|
wire [3:0] _T_485 = _T_483 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_492 = {i0_trigger_chain_masked_r[3],i0_trigger_r[2],i0_trigger_chain_masked_r[1],i0_trigger_r[0]}; // @[Cat.scala 29:58]
|
|
wire _T_495 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 574:60]
|
|
wire _T_496 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 601:62]
|
|
wire _T_497 = i_cpu_halt_req_sync & _T_496; // @[dec_tlu_ctl.scala 601:60]
|
|
wire i_cpu_halt_req_sync_qual = _T_497 & _T_680; // @[dec_tlu_ctl.scala 601:85]
|
|
wire _T_500 = i_cpu_run_req_sync & _T_496; // @[dec_tlu_ctl.scala 602:58]
|
|
wire _T_501 = _T_500 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 602:83]
|
|
wire i_cpu_run_req_sync_qual = _T_501 & _T_680; // @[dec_tlu_ctl.scala 602:105]
|
|
wire _T_503 = i_cpu_halt_req_sync_qual ^ i_cpu_halt_req_d1; // @[lib.scala 466:21]
|
|
wire _T_504 = |_T_503; // @[lib.scala 466:29]
|
|
wire _T_506 = i_cpu_run_req_sync_qual ^ i_cpu_run_req_d1_raw; // @[lib.scala 466:21]
|
|
wire _T_507 = |_T_506; // @[lib.scala 466:29]
|
|
wire _T_563 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 626:51]
|
|
wire _T_564 = pmu_fw_tlu_halted_f & _T_563; // @[dec_tlu_ctl.scala 626:49]
|
|
wire _T_566 = io_o_cpu_halt_status & _T_563; // @[dec_tlu_ctl.scala 626:94]
|
|
wire _T_568 = _T_566 & _T_682; // @[dec_tlu_ctl.scala 626:114]
|
|
wire cpu_halt_status = _T_564 | _T_568; // @[dec_tlu_ctl.scala 626:70]
|
|
reg _T_512; // @[Reg.scala 27:20]
|
|
wire _T_510 = cpu_halt_status ^ _T_512; // @[lib.scala 466:21]
|
|
wire _T_511 = |_T_510; // @[lib.scala 466:29]
|
|
wire _T_560 = i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 625:44]
|
|
wire _T_561 = io_o_cpu_halt_ack & i_cpu_halt_req_sync; // @[dec_tlu_ctl.scala 625:88]
|
|
wire cpu_halt_ack = _T_560 | _T_561; // @[dec_tlu_ctl.scala 625:67]
|
|
reg _T_516; // @[Reg.scala 27:20]
|
|
wire _T_514 = cpu_halt_ack ^ _T_516; // @[lib.scala 466:21]
|
|
wire _T_515 = |_T_514; // @[lib.scala 466:29]
|
|
wire _T_571 = _T_216 & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:46]
|
|
wire _T_572 = io_o_cpu_halt_status & i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 627:92]
|
|
wire _T_573 = _T_571 | _T_572; // @[dec_tlu_ctl.scala 627:68]
|
|
wire _T_574 = io_o_cpu_run_ack & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:136]
|
|
wire cpu_run_ack = _T_573 | _T_574; // @[dec_tlu_ctl.scala 627:116]
|
|
reg _T_520; // @[Reg.scala 27:20]
|
|
wire _T_518 = cpu_run_ack ^ _T_520; // @[lib.scala 466:21]
|
|
wire _T_519 = |_T_518; // @[lib.scala 466:29]
|
|
wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_583; // @[dec_tlu_ctl.scala 617:55]
|
|
wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1011:37]
|
|
wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 618:53]
|
|
wire _T_551 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 623:50]
|
|
wire _T_552 = _T_551 & halt_taken; // @[dec_tlu_ctl.scala 623:63]
|
|
wire _T_553 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 623:78]
|
|
wire _T_554 = _T_552 & _T_553; // @[dec_tlu_ctl.scala 623:76]
|
|
wire _T_557 = _T_554 | _T_564; // @[dec_tlu_ctl.scala 623:101]
|
|
wire pmu_fw_tlu_halted = _T_557 & _T_358; // @[dec_tlu_ctl.scala 623:146]
|
|
wire _T_541 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 619:77]
|
|
wire _T_542 = pmu_fw_halt_req_f & _T_541; // @[dec_tlu_ctl.scala 619:75]
|
|
wire _T_543 = enter_pmu_fw_halt_req | _T_542; // @[dec_tlu_ctl.scala 619:54]
|
|
wire pmu_fw_halt_req_ns = _T_543 & _T_358; // @[dec_tlu_ctl.scala 619:98]
|
|
wire _T_547 = internal_pmu_fw_halt_mode_f & _T_563; // @[dec_tlu_ctl.scala 620:88]
|
|
wire _T_549 = _T_547 & _T_358; // @[dec_tlu_ctl.scala 620:108]
|
|
wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 620:57]
|
|
wire _T_521 = internal_pmu_fw_halt_mode ^ internal_pmu_fw_halt_mode_f; // @[lib.scala 466:21]
|
|
wire _T_522 = |_T_521; // @[lib.scala 466:29]
|
|
wire _T_525 = pmu_fw_halt_req_ns ^ pmu_fw_halt_req_f; // @[lib.scala 466:21]
|
|
wire _T_526 = |_T_525; // @[lib.scala 466:29]
|
|
wire _T_529 = pmu_fw_tlu_halted ^ pmu_fw_tlu_halted_f; // @[lib.scala 466:21]
|
|
wire _T_530 = |_T_529; // @[lib.scala 466:29]
|
|
wire int_timer0_int_hold = int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 785:43]
|
|
wire _T_533 = int_timer0_int_hold ^ int_timer0_int_hold_f; // @[lib.scala 466:21]
|
|
wire _T_534 = |_T_533; // @[lib.scala 466:29]
|
|
wire int_timer1_int_hold = int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 786:43]
|
|
wire _T_537 = int_timer1_int_hold ^ int_timer1_int_hold_f; // @[lib.scala 466:21]
|
|
wire _T_538 = |_T_537; // @[lib.scala 466:29]
|
|
wire _T_596 = io_dec_tlu_i0_valid_r & _T_590; // @[dec_tlu_ctl.scala 654:55]
|
|
wire _T_597 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 654:70]
|
|
wire _T_598 = _T_596 & _T_597; // @[dec_tlu_ctl.scala 654:68]
|
|
wire _T_599 = ~inst_acc_r; // @[dec_tlu_ctl.scala 654:87]
|
|
wire _T_600 = _T_598 & _T_599; // @[dec_tlu_ctl.scala 654:84]
|
|
wire _T_602 = _T_600 & _T_249; // @[dec_tlu_ctl.scala 654:99]
|
|
wire _T_603 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 654:126]
|
|
wire _T_604 = _T_602 & _T_603; // @[dec_tlu_ctl.scala 654:124]
|
|
wire tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 654:151]
|
|
wire _T_626 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 672:57]
|
|
wire _T_653 = ~dcsr[15]; // @[dec_tlu_ctl.scala 703:116]
|
|
wire _T_654 = _T_702 & _T_653; // @[dec_tlu_ctl.scala 703:114]
|
|
wire ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 703:136]
|
|
wire _T_657 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 704:57]
|
|
wire _T_658 = _T_657 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 704:70]
|
|
wire _T_660 = _T_658 & _T_619; // @[dec_tlu_ctl.scala 704:94]
|
|
wire ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 704:114]
|
|
wire _T_627 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 672:93]
|
|
wire _T_628 = _T_627 | mret_r; // @[dec_tlu_ctl.scala 672:103]
|
|
wire _T_629 = _T_628 | take_reset; // @[dec_tlu_ctl.scala 672:112]
|
|
wire _T_630 = _T_629 | illegal_r; // @[dec_tlu_ctl.scala 672:125]
|
|
wire _T_631 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 672:181]
|
|
wire _T_632 = dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 672:158]
|
|
wire _T_633 = _T_630 | _T_632; // @[dec_tlu_ctl.scala 672:137]
|
|
wire _T_634 = ~_T_633; // @[dec_tlu_ctl.scala 672:82]
|
|
wire _T_635 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 679:69]
|
|
wire _T_638 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 680:81]
|
|
wire _T_641 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 681:65]
|
|
wire _T_643 = _T_641 & _T_611; // @[dec_tlu_ctl.scala 681:89]
|
|
wire _T_644 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 681:116]
|
|
wire _T_645 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 681:145]
|
|
wire _T_646 = _T_644 | _T_645; // @[dec_tlu_ctl.scala 681:143]
|
|
wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_708 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1021:50]
|
|
wire _T_709 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1021:75]
|
|
wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_718 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1026:63]
|
|
wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_719 = _T_718 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1026:81]
|
|
wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_720 = _T_719 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1026:100]
|
|
wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_721 = _T_720 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1026:123]
|
|
wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_722 = _T_721 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1026:144]
|
|
wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_723 = _T_722 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1026:166]
|
|
wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_724 = _T_723 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1026:187]
|
|
wire _T_725 = ~_T_724; // @[dec_tlu_ctl.scala 1026:44]
|
|
wire _T_726 = _T_725 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1026:209]
|
|
wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_727 = csr_pkt_legal & _T_726; // @[dec_tlu_ctl.scala 1026:41]
|
|
wire fast_int_meicpct = int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 798:43]
|
|
wire _T_728 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1026:231]
|
|
wire valid_csr = _T_727 & _T_728; // @[dec_tlu_ctl.scala 1026:229]
|
|
wire _T_731 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1028:54]
|
|
wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_732 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1028:115]
|
|
wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_733 = _T_732 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1028:137]
|
|
wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_734 = _T_733 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1028:158]
|
|
wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_735 = _T_734 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1028:180]
|
|
wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16]
|
|
wire _T_736 = _T_735 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1028:201]
|
|
wire _T_737 = io_dec_csr_wen_unq_d & _T_736; // @[dec_tlu_ctl.scala 1028:90]
|
|
wire _T_738 = ~_T_737; // @[dec_tlu_ctl.scala 1028:67]
|
|
int_exc int_exc ( // @[dec_tlu_ctl.scala 282:29]
|
|
.clock(int_exc_clock),
|
|
.reset(int_exc_reset),
|
|
.io_mhwakeup_ready(int_exc_io_mhwakeup_ready),
|
|
.io_ext_int_ready(int_exc_io_ext_int_ready),
|
|
.io_ce_int_ready(int_exc_io_ce_int_ready),
|
|
.io_soft_int_ready(int_exc_io_soft_int_ready),
|
|
.io_timer_int_ready(int_exc_io_timer_int_ready),
|
|
.io_int_timer0_int_hold(int_exc_io_int_timer0_int_hold),
|
|
.io_int_timer1_int_hold(int_exc_io_int_timer1_int_hold),
|
|
.io_internal_dbg_halt_timers(int_exc_io_internal_dbg_halt_timers),
|
|
.io_take_ext_int_start(int_exc_io_take_ext_int_start),
|
|
.io_ext_int_freeze_d1(int_exc_io_ext_int_freeze_d1),
|
|
.io_take_ext_int_start_d1(int_exc_io_take_ext_int_start_d1),
|
|
.io_take_ext_int_start_d2(int_exc_io_take_ext_int_start_d2),
|
|
.io_take_ext_int_start_d3(int_exc_io_take_ext_int_start_d3),
|
|
.io_ext_int_freeze(int_exc_io_ext_int_freeze),
|
|
.io_take_ext_int(int_exc_io_take_ext_int),
|
|
.io_fast_int_meicpct(int_exc_io_fast_int_meicpct),
|
|
.io_ignore_ext_int_due_to_lsu_stall(int_exc_io_ignore_ext_int_due_to_lsu_stall),
|
|
.io_take_ce_int(int_exc_io_take_ce_int),
|
|
.io_take_soft_int(int_exc_io_take_soft_int),
|
|
.io_take_timer_int(int_exc_io_take_timer_int),
|
|
.io_take_int_timer0_int(int_exc_io_take_int_timer0_int),
|
|
.io_take_int_timer1_int(int_exc_io_take_int_timer1_int),
|
|
.io_take_reset(int_exc_io_take_reset),
|
|
.io_take_nmi(int_exc_io_take_nmi),
|
|
.io_synchronous_flush_r(int_exc_io_synchronous_flush_r),
|
|
.io_tlu_flush_lower_r(int_exc_io_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_lower_wb(int_exc_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_flush_lower_r(int_exc_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_path_r(int_exc_io_dec_tlu_flush_path_r),
|
|
.io_interrupt_valid_r_d1(int_exc_io_interrupt_valid_r_d1),
|
|
.io_i0_exception_valid_r_d1(int_exc_io_i0_exception_valid_r_d1),
|
|
.io_exc_or_int_valid_r_d1(int_exc_io_exc_or_int_valid_r_d1),
|
|
.io_exc_cause_wb(int_exc_io_exc_cause_wb),
|
|
.io_i0_valid_wb(int_exc_io_i0_valid_wb),
|
|
.io_trigger_hit_r_d1(int_exc_io_trigger_hit_r_d1),
|
|
.io_take_nmi_r_d1(int_exc_io_take_nmi_r_d1),
|
|
.io_interrupt_valid_r(int_exc_io_interrupt_valid_r),
|
|
.io_exc_cause_r(int_exc_io_exc_cause_r),
|
|
.io_i0_exception_valid_r(int_exc_io_i0_exception_valid_r),
|
|
.io_tlu_flush_path_r_d1(int_exc_io_tlu_flush_path_r_d1),
|
|
.io_exc_or_int_valid_r(int_exc_io_exc_or_int_valid_r),
|
|
.io_dec_csr_stall_int_ff(int_exc_io_dec_csr_stall_int_ff),
|
|
.io_mstatus_mie_ns(int_exc_io_mstatus_mie_ns),
|
|
.io_mip(int_exc_io_mip),
|
|
.io_mie_ns(int_exc_io_mie_ns),
|
|
.io_mret_r(int_exc_io_mret_r),
|
|
.io_pmu_fw_tlu_halted_f(int_exc_io_pmu_fw_tlu_halted_f),
|
|
.io_int_timer0_int_hold_f(int_exc_io_int_timer0_int_hold_f),
|
|
.io_int_timer1_int_hold_f(int_exc_io_int_timer1_int_hold_f),
|
|
.io_internal_dbg_halt_mode_f(int_exc_io_internal_dbg_halt_mode_f),
|
|
.io_dcsr_single_step_running(int_exc_io_dcsr_single_step_running),
|
|
.io_internal_dbg_halt_mode(int_exc_io_internal_dbg_halt_mode),
|
|
.io_dec_tlu_i0_valid_r(int_exc_io_dec_tlu_i0_valid_r),
|
|
.io_internal_pmu_fw_halt_mode(int_exc_io_internal_pmu_fw_halt_mode),
|
|
.io_i_cpu_halt_req_d1(int_exc_io_i_cpu_halt_req_d1),
|
|
.io_ebreak_to_debug_mode_r(int_exc_io_ebreak_to_debug_mode_r),
|
|
.io_lsu_fir_error(int_exc_io_lsu_fir_error),
|
|
.io_csr_pkt_csr_meicpct(int_exc_io_csr_pkt_csr_meicpct),
|
|
.io_dec_csr_any_unq_d(int_exc_io_dec_csr_any_unq_d),
|
|
.io_lsu_fastint_stall_any(int_exc_io_lsu_fastint_stall_any),
|
|
.io_reset_delayed(int_exc_io_reset_delayed),
|
|
.io_mpc_reset_run_req(int_exc_io_mpc_reset_run_req),
|
|
.io_nmi_int_detected(int_exc_io_nmi_int_detected),
|
|
.io_dcsr_single_step_running_f(int_exc_io_dcsr_single_step_running_f),
|
|
.io_dcsr_single_step_done_f(int_exc_io_dcsr_single_step_done_f),
|
|
.io_dcsr(int_exc_io_dcsr),
|
|
.io_mtvec(int_exc_io_mtvec),
|
|
.io_tlu_i0_commit_cmt(int_exc_io_tlu_i0_commit_cmt),
|
|
.io_i0_trigger_hit_r(int_exc_io_i0_trigger_hit_r),
|
|
.io_pause_expired_r(int_exc_io_pause_expired_r),
|
|
.io_nmi_vec(int_exc_io_nmi_vec),
|
|
.io_lsu_i0_rfnpc_r(int_exc_io_lsu_i0_rfnpc_r),
|
|
.io_fence_i_r(int_exc_io_fence_i_r),
|
|
.io_iccm_repair_state_rfnpc(int_exc_io_iccm_repair_state_rfnpc),
|
|
.io_i_cpu_run_req_d1(int_exc_io_i_cpu_run_req_d1),
|
|
.io_rfpc_i0_r(int_exc_io_rfpc_i0_r),
|
|
.io_lsu_exc_valid_r(int_exc_io_lsu_exc_valid_r),
|
|
.io_trigger_hit_dmode_r(int_exc_io_trigger_hit_dmode_r),
|
|
.io_take_halt(int_exc_io_take_halt),
|
|
.io_rst_vec(int_exc_io_rst_vec),
|
|
.io_lsu_fir_addr(int_exc_io_lsu_fir_addr),
|
|
.io_dec_tlu_i0_pc_r(int_exc_io_dec_tlu_i0_pc_r),
|
|
.io_npc_r(int_exc_io_npc_r),
|
|
.io_mepc(int_exc_io_mepc),
|
|
.io_debug_resume_req_f(int_exc_io_debug_resume_req_f),
|
|
.io_dpc(int_exc_io_dpc),
|
|
.io_npc_r_d1(int_exc_io_npc_r_d1),
|
|
.io_tlu_flush_lower_r_d1(int_exc_io_tlu_flush_lower_r_d1),
|
|
.io_dec_tlu_dbg_halted(int_exc_io_dec_tlu_dbg_halted),
|
|
.io_ebreak_r(int_exc_io_ebreak_r),
|
|
.io_ecall_r(int_exc_io_ecall_r),
|
|
.io_illegal_r(int_exc_io_illegal_r),
|
|
.io_inst_acc_r(int_exc_io_inst_acc_r),
|
|
.io_lsu_i0_exc_r(int_exc_io_lsu_i0_exc_r),
|
|
.io_lsu_error_pkt_r_bits_inst_type(int_exc_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(int_exc_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_dec_tlu_wr_pause_r_d1(int_exc_io_dec_tlu_wr_pause_r_d1)
|
|
);
|
|
csr_tlu csr ( // @[dec_tlu_ctl.scala 283:23]
|
|
.clock(csr_clock),
|
|
.reset(csr_reset),
|
|
.io_free_l2clk(csr_io_free_l2clk),
|
|
.io_free_clk(csr_io_free_clk),
|
|
.io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d),
|
|
.io_dec_i0_decode_d(csr_io_dec_i0_decode_d),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid),
|
|
.io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute),
|
|
.io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute),
|
|
.io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute),
|
|
.io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute),
|
|
.io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2),
|
|
.io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn),
|
|
.io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any),
|
|
.io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any),
|
|
.io_lsu_store_stall_any(csr_io_lsu_store_stall_any),
|
|
.io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall),
|
|
.io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall),
|
|
.io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall),
|
|
.io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken),
|
|
.io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp),
|
|
.io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded),
|
|
.io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned),
|
|
.io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4),
|
|
.io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss),
|
|
.io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit),
|
|
.io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1),
|
|
.io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1),
|
|
.io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1),
|
|
.io_dec_csr_wen_r(csr_io_dec_csr_wen_r),
|
|
.io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1),
|
|
.io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1),
|
|
.io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3),
|
|
.io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted),
|
|
.io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write),
|
|
.io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read),
|
|
.io_dma_pmu_any_write(csr_io_dma_pmu_any_write),
|
|
.io_dma_pmu_any_read(csr_io_dma_pmu_any_read),
|
|
.io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy),
|
|
.io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r),
|
|
.io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r),
|
|
.io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d),
|
|
.io_dec_tlu_picio_clk_override(csr_io_dec_tlu_picio_clk_override),
|
|
.io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override),
|
|
.io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override),
|
|
.io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override),
|
|
.io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override),
|
|
.io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d),
|
|
.io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable),
|
|
.io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r),
|
|
.io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy),
|
|
.io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error),
|
|
.io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error),
|
|
.io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned),
|
|
.io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn),
|
|
.io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data),
|
|
.io_dec_tlu_meipt(csr_io_dec_tlu_meipt),
|
|
.io_pic_pl(csr_io_pic_pl),
|
|
.io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl),
|
|
.io_dec_tlu_meihap(csr_io_dec_tlu_meihap),
|
|
.io_pic_claimid(csr_io_pic_claimid),
|
|
.io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error),
|
|
.io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any),
|
|
.io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any),
|
|
.io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any),
|
|
.io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff),
|
|
.io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable),
|
|
.io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable),
|
|
.io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable),
|
|
.io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable),
|
|
.io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty),
|
|
.io_dec_tlu_trace_disable(csr_io_dec_tlu_trace_disable),
|
|
.io_dec_illegal_inst(csr_io_dec_illegal_inst),
|
|
.io_lsu_error_pkt_r_bits_mscause(csr_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_mexintpend(csr_io_mexintpend),
|
|
.io_exu_npc_r(csr_io_exu_npc_r),
|
|
.io_mpc_reset_run_req(csr_io_mpc_reset_run_req),
|
|
.io_rst_vec(csr_io_rst_vec),
|
|
.io_core_id(csr_io_core_id),
|
|
.io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d),
|
|
.io_dec_timer_read_d(csr_io_dec_timer_read_d),
|
|
.io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod),
|
|
.io_rfpc_i0_r(csr_io_rfpc_i0_r),
|
|
.io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r),
|
|
.io_fw_halt_req(csr_io_fw_halt_req),
|
|
.io_mstatus(csr_io_mstatus),
|
|
.io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r),
|
|
.io_mret_r(csr_io_mret_r),
|
|
.io_mstatus_mie_ns(csr_io_mstatus_mie_ns),
|
|
.io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f),
|
|
.io_dcsr(csr_io_dcsr),
|
|
.io_mtvec(csr_io_mtvec),
|
|
.io_mip(csr_io_mip),
|
|
.io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse),
|
|
.io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse),
|
|
.io_timer_int_sync(csr_io_timer_int_sync),
|
|
.io_soft_int_sync(csr_io_soft_int_sync),
|
|
.io_mie_ns(csr_io_mie_ns),
|
|
.io_csr_wr_clk(csr_io_csr_wr_clk),
|
|
.io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r),
|
|
.io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted),
|
|
.io_lsu_fir_error(csr_io_lsu_fir_error),
|
|
.io_npc_r(csr_io_npc_r),
|
|
.io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1),
|
|
.io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1),
|
|
.io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1),
|
|
.io_npc_r_d1(csr_io_npc_r_d1),
|
|
.io_reset_delayed(csr_io_reset_delayed),
|
|
.io_mepc(csr_io_mepc),
|
|
.io_interrupt_valid_r(csr_io_interrupt_valid_r),
|
|
.io_i0_exception_valid_r(csr_io_i0_exception_valid_r),
|
|
.io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r),
|
|
.io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r),
|
|
.io_lsu_single_ecc_error_r(csr_io_lsu_single_ecc_error_r),
|
|
.io_e4e5_int_clk(csr_io_e4e5_int_clk),
|
|
.io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r),
|
|
.io_inst_acc_r(csr_io_inst_acc_r),
|
|
.io_inst_acc_second_r(csr_io_inst_acc_second_r),
|
|
.io_take_nmi(csr_io_take_nmi),
|
|
.io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r),
|
|
.io_exc_cause_r(csr_io_exc_cause_r),
|
|
.io_i0_valid_wb(csr_io_i0_valid_wb),
|
|
.io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1),
|
|
.io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1),
|
|
.io_exc_cause_wb(csr_io_exc_cause_wb),
|
|
.io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type),
|
|
.io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type),
|
|
.io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt),
|
|
.io_ebreak_r(csr_io_ebreak_r),
|
|
.io_ecall_r(csr_io_ecall_r),
|
|
.io_illegal_r(csr_io_illegal_r),
|
|
.io_mdseac_locked_ns(csr_io_mdseac_locked_ns),
|
|
.io_mdseac_locked_f(csr_io_mdseac_locked_f),
|
|
.io_nmi_int_detected_f(csr_io_nmi_int_detected_f),
|
|
.io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2),
|
|
.io_ext_int_freeze(csr_io_ext_int_freeze),
|
|
.io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1),
|
|
.io_take_ext_int_start_d1(csr_io_take_ext_int_start_d1),
|
|
.io_take_ext_int_start_d2(csr_io_take_ext_int_start_d2),
|
|
.io_take_ext_int_start_d3(csr_io_take_ext_int_start_d3),
|
|
.io_ic_perr_r(csr_io_ic_perr_r),
|
|
.io_iccm_sbecc_r(csr_io_iccm_sbecc_r),
|
|
.io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f),
|
|
.io_lsu_idle_any_f(csr_io_lsu_idle_any_f),
|
|
.io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f),
|
|
.io_dbg_tlu_halted(csr_io_dbg_tlu_halted),
|
|
.io_debug_halt_req_f(csr_io_debug_halt_req_f),
|
|
.io_force_halt(csr_io_force_halt),
|
|
.io_take_ext_int_start(csr_io_take_ext_int_start),
|
|
.io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1),
|
|
.io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1),
|
|
.io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f),
|
|
.io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1),
|
|
.io_debug_halt_req(csr_io_debug_halt_req),
|
|
.io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write),
|
|
.io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f),
|
|
.io_enter_debug_halt_req(csr_io_enter_debug_halt_req),
|
|
.io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode),
|
|
.io_request_debug_mode_done(csr_io_request_debug_mode_done),
|
|
.io_request_debug_mode_r(csr_io_request_debug_mode_r),
|
|
.io_dpc(csr_io_dpc),
|
|
.io_update_hit_bit_r(csr_io_update_hit_bit_r),
|
|
.io_take_timer_int(csr_io_take_timer_int),
|
|
.io_take_int_timer0_int(csr_io_take_int_timer0_int),
|
|
.io_take_int_timer1_int(csr_io_take_int_timer1_int),
|
|
.io_take_ext_int(csr_io_take_ext_int),
|
|
.io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r),
|
|
.io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r),
|
|
.io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r),
|
|
.io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r),
|
|
.io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r),
|
|
.io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa),
|
|
.io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid),
|
|
.io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid),
|
|
.io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid),
|
|
.io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid),
|
|
.io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus),
|
|
.io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec),
|
|
.io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip),
|
|
.io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie),
|
|
.io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel),
|
|
.io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh),
|
|
.io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl),
|
|
.io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth),
|
|
.io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch),
|
|
.io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc),
|
|
.io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause),
|
|
.io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause),
|
|
.io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval),
|
|
.io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac),
|
|
.io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac),
|
|
.io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap),
|
|
.io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt),
|
|
.io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt),
|
|
.io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl),
|
|
.io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl),
|
|
.io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr),
|
|
.io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc),
|
|
.io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc),
|
|
.io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc),
|
|
.io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel),
|
|
.io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1),
|
|
.io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2),
|
|
.io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3),
|
|
.io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4),
|
|
.io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5),
|
|
.io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6),
|
|
.io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h),
|
|
.io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h),
|
|
.io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h),
|
|
.io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h),
|
|
.io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3),
|
|
.io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4),
|
|
.io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5),
|
|
.io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6),
|
|
.io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit),
|
|
.io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc),
|
|
.io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect),
|
|
.io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect),
|
|
.io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect),
|
|
.io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht),
|
|
.io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs),
|
|
.io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics),
|
|
.io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h),
|
|
.io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0),
|
|
.io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1),
|
|
.io_mtdata1_t_0(csr_io_mtdata1_t_0),
|
|
.io_mtdata1_t_1(csr_io_mtdata1_t_1),
|
|
.io_mtdata1_t_2(csr_io_mtdata1_t_2),
|
|
.io_mtdata1_t_3(csr_io_mtdata1_t_3),
|
|
.io_trigger_enabled(csr_io_trigger_enabled)
|
|
);
|
|
dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 284:30]
|
|
.clock(int_timers_clock),
|
|
.reset(int_timers_reset),
|
|
.io_free_l2clk(int_timers_io_free_l2clk),
|
|
.io_csr_wr_clk(int_timers_io_csr_wr_clk),
|
|
.io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod),
|
|
.io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r),
|
|
.io_csr_mitctl0(int_timers_io_csr_mitctl0),
|
|
.io_csr_mitctl1(int_timers_io_csr_mitctl1),
|
|
.io_csr_mitb0(int_timers_io_csr_mitb0),
|
|
.io_csr_mitb1(int_timers_io_csr_mitb1),
|
|
.io_csr_mitcnt0(int_timers_io_csr_mitcnt0),
|
|
.io_csr_mitcnt1(int_timers_io_csr_mitcnt1),
|
|
.io_dec_pause_state(int_timers_io_dec_pause_state),
|
|
.io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted),
|
|
.io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers),
|
|
.io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d),
|
|
.io_dec_timer_read_d(int_timers_io_dec_timer_read_d),
|
|
.io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse),
|
|
.io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse)
|
|
);
|
|
dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1017:28]
|
|
.io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d),
|
|
.io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa),
|
|
.io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid),
|
|
.io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid),
|
|
.io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid),
|
|
.io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid),
|
|
.io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus),
|
|
.io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec),
|
|
.io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip),
|
|
.io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie),
|
|
.io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel),
|
|
.io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh),
|
|
.io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl),
|
|
.io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth),
|
|
.io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch),
|
|
.io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc),
|
|
.io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause),
|
|
.io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause),
|
|
.io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval),
|
|
.io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac),
|
|
.io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst),
|
|
.io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac),
|
|
.io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap),
|
|
.io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt),
|
|
.io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt),
|
|
.io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl),
|
|
.io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl),
|
|
.io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr),
|
|
.io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc),
|
|
.io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc),
|
|
.io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc),
|
|
.io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel),
|
|
.io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1),
|
|
.io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2),
|
|
.io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3),
|
|
.io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4),
|
|
.io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5),
|
|
.io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6),
|
|
.io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h),
|
|
.io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h),
|
|
.io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h),
|
|
.io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h),
|
|
.io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3),
|
|
.io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4),
|
|
.io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5),
|
|
.io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6),
|
|
.io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit),
|
|
.io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0),
|
|
.io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1),
|
|
.io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0),
|
|
.io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1),
|
|
.io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0),
|
|
.io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1),
|
|
.io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc),
|
|
.io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct),
|
|
.io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect),
|
|
.io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect),
|
|
.io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect),
|
|
.io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht),
|
|
.io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs),
|
|
.io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics),
|
|
.io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h),
|
|
.io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0),
|
|
.io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1),
|
|
.io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago),
|
|
.io_csr_pkt_presync(csr_read_io_csr_pkt_presync),
|
|
.io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync),
|
|
.io_csr_pkt_legal(csr_read_io_csr_pkt_legal)
|
|
);
|
|
assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 879:58]
|
|
assign io_tlu_exu_dec_tlu_flush_lower_r = int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 810:54]
|
|
assign io_tlu_exu_dec_tlu_flush_path_r = int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 811:54]
|
|
assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 910:54]
|
|
assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 510:29]
|
|
assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 511:29]
|
|
assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 492:41]
|
|
assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 493:41]
|
|
assign io_dec_tlu_resume_ack = _T_286; // @[dec_tlu_ctl.scala 473:53]
|
|
assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 491:41]
|
|
assign io_dec_tlu_mpc_halted_only = _T_143; // @[dec_tlu_ctl.scala 386:42]
|
|
assign io_dec_tlu_flush_extint = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 499:33]
|
|
assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 885:46]
|
|
assign io_o_cpu_halt_status = _T_512; // @[dec_tlu_ctl.scala 606:60]
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assign io_o_cpu_halt_ack = _T_516; // @[dec_tlu_ctl.scala 607:68]
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assign io_o_cpu_run_ack = _T_520; // @[dec_tlu_ctl.scala 608:68]
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assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 630:32]
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assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 412:31]
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assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 413:31]
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assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 414:31]
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assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 901:46]
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assign io_dec_csr_legal_d = _T_731 & _T_738; // @[dec_tlu_ctl.scala 1028:28]
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assign io_dec_tlu_i0_kill_writeb_wb = _T_52; // @[dec_tlu_ctl.scala 343:41]
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assign io_dec_tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 349:41]
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assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 903:46]
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assign io_dec_tlu_flush_pause_r = _T_342 & _T_343; // @[dec_tlu_ctl.scala 502:34]
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assign io_dec_tlu_presync_d = _T_708 & _T_709; // @[dec_tlu_ctl.scala 1021:31]
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assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1022:31]
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assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 888:46]
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assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 889:46]
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assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 890:46]
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assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 891:46]
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assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 882:50]
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assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 883:50]
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assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 881:50]
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assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 887:46]
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assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 886:46]
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assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 902:46]
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assign io_dec_tlu_trace_disable = csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 911:49]
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assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 894:46]
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assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46]
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assign io_dec_tlu_picio_clk_override = csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 893:46]
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assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 899:46]
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assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 900:46]
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assign io_dec_tlu_flush_lower_wb = int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 809:46]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_643 & _T_646; // @[dec_tlu_ctl.scala 687:73]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 684:73]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_635 & _T_611; // @[dec_tlu_ctl.scala 685:73]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_638 & _T_611; // @[dec_tlu_ctl.scala 686:73]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 688:73]
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assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 689:81]
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assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_367 & _T_368; // @[dec_tlu_ctl.scala 506:45]
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assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 906:53]
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assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_339 | take_ext_int_start; // @[dec_tlu_ctl.scala 497:45]
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assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 904:54]
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assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_615; // @[dec_tlu_ctl.scala 507:41]
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assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 658:42]
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assign io_tlu_mem_dec_tlu_force_halt = _T_59; // @[dec_tlu_ctl.scala 345:41]
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assign io_tlu_mem_dec_tlu_fence_i_wb = _T_677 & _T_590; // @[dec_tlu_ctl.scala 719:39]
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assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 884:58]
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assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 884:58]
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assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 884:58]
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assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 884:58]
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assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 908:54]
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assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 909:58]
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assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 905:58]
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assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 907:58]
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assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 878:58]
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assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 880:58]
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assign int_exc_clock = clock;
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assign int_exc_reset = reset;
|
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assign int_exc_io_ext_int_freeze_d1 = csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 789:42]
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assign int_exc_io_take_ext_int_start_d1 = csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 790:44]
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assign int_exc_io_take_ext_int_start_d2 = csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 791:44]
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assign int_exc_io_take_ext_int_start_d3 = csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 792:44]
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assign int_exc_io_dec_csr_stall_int_ff = io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 724:49]
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assign int_exc_io_mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 725:49]
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assign int_exc_io_mip = csr_io_mip; // @[dec_tlu_ctl.scala 726:49]
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assign int_exc_io_mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 727:49]
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assign int_exc_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 728:49]
|
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assign int_exc_io_pmu_fw_tlu_halted_f = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 729:49]
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assign int_exc_io_int_timer0_int_hold_f = int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 730:49]
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assign int_exc_io_int_timer1_int_hold_f = int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 731:49]
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assign int_exc_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 732:49]
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assign int_exc_io_dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 733:49]
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assign int_exc_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 734:49]
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assign int_exc_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 735:49]
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assign int_exc_io_internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 736:49]
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assign int_exc_io_i_cpu_halt_req_d1 = i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 737:49]
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assign int_exc_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 738:49]
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assign int_exc_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 739:49]
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assign int_exc_io_csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 740:49]
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assign int_exc_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 741:49]
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assign int_exc_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 742:49]
|
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assign int_exc_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 743:49]
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assign int_exc_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 744:49]
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assign int_exc_io_nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 745:49]
|
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assign int_exc_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 746:49]
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assign int_exc_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 747:49]
|
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assign int_exc_io_dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 748:49]
|
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assign int_exc_io_mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 749:49]
|
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assign int_exc_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 750:49]
|
|
assign int_exc_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 751:49]
|
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assign int_exc_io_pause_expired_r = _T_361 & _T_362; // @[dec_tlu_ctl.scala 752:49]
|
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assign int_exc_io_nmi_vec = io_nmi_vec; // @[dec_tlu_ctl.scala 753:49]
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assign int_exc_io_lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 754:49]
|
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assign int_exc_io_fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 755:49]
|
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assign int_exc_io_iccm_repair_state_rfnpc = _T_626 & _T_634; // @[dec_tlu_ctl.scala 756:49]
|
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assign int_exc_io_i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 757:49]
|
|
assign int_exc_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 758:49]
|
|
assign int_exc_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 759:49]
|
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assign int_exc_io_trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 760:49]
|
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assign int_exc_io_take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 761:49]
|
|
assign int_exc_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 762:49]
|
|
assign int_exc_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec_tlu_ctl.scala 763:49]
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assign int_exc_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 764:49]
|
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assign int_exc_io_npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 765:49]
|
|
assign int_exc_io_mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 766:49]
|
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assign int_exc_io_debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 767:49]
|
|
assign int_exc_io_dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 768:49]
|
|
assign int_exc_io_npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 769:49]
|
|
assign int_exc_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 770:49]
|
|
assign int_exc_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 771:49]
|
|
assign int_exc_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 772:49]
|
|
assign int_exc_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 773:49]
|
|
assign int_exc_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 774:49]
|
|
assign int_exc_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 775:49]
|
|
assign int_exc_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 776:49]
|
|
assign int_exc_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 777:49]
|
|
assign int_exc_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 777:49]
|
|
assign int_exc_io_dec_tlu_wr_pause_r_d1 = dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 778:42]
|
|
assign csr_clock = clock;
|
|
assign csr_reset = reset;
|
|
assign csr_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 822:50]
|
|
assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 821:50]
|
|
assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 824:50]
|
|
assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 825:50]
|
|
assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 826:50]
|
|
assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 827:50]
|
|
assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 828:50]
|
|
assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 829:50]
|
|
assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 830:50]
|
|
assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 831:50]
|
|
assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 832:50]
|
|
assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 833:50]
|
|
assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 834:50]
|
|
assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 835:50]
|
|
assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 836:50]
|
|
assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 837:50]
|
|
assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 838:50]
|
|
assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 838:50]
|
|
assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 838:50]
|
|
assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 838:50]
|
|
assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 838:50]
|
|
assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 839:50]
|
|
assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 840:50]
|
|
assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 841:50]
|
|
assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 842:50]
|
|
assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 843:50]
|
|
assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 844:50]
|
|
assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 845:50]
|
|
assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 846:50]
|
|
assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 847:50]
|
|
assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 848:50]
|
|
assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 849:50]
|
|
assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 850:50]
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assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 851:50]
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assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 852:50]
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assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 853:50]
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assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 854:50]
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assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 856:50]
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assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 857:50]
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assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 858:50]
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assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 859:50]
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assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 860:50]
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assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 861:50]
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assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 862:50]
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assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 863:50]
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assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 864:50]
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assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 865:50]
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assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 866:50]
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assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 867:50]
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assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 868:50]
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assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 869:50 dec_tlu_ctl.scala 912:50]
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assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 870:50 dec_tlu_ctl.scala 913:50]
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assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 871:50 dec_tlu_ctl.scala 914:50]
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assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 872:50 dec_tlu_ctl.scala 915:50]
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assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 873:50 dec_tlu_ctl.scala 916:50]
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assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 874:50 dec_tlu_ctl.scala 917:50]
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assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 875:50 dec_tlu_ctl.scala 918:50]
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assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 876:50 dec_tlu_ctl.scala 919:50]
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assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 877:50 dec_tlu_ctl.scala 920:50]
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assign csr_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 923:45]
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assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 924:45]
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assign csr_io_exc_or_int_valid_r = int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 925:45]
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assign csr_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 926:45]
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assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 927:45]
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assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 928:45]
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assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 929:45]
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assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 930:45]
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assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 931:45]
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assign csr_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 932:45]
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assign csr_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 933:45]
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assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 934:45]
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assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 935:45]
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assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 936:45]
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assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 937:45]
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assign csr_io_tlu_flush_path_r_d1 = int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 938:45]
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assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 939:45]
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assign csr_io_interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 940:45]
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assign csr_io_i0_exception_valid_r = int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 941:45]
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assign csr_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 942:45]
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assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_495; // @[dec_tlu_ctl.scala 943:45]
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assign csr_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_incr; // @[dec_tlu_ctl.scala 944:45]
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assign csr_io_e4e5_int_clk = clock; // @[dec_tlu_ctl.scala 945:45]
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assign csr_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 946:45]
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assign csr_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 947:45]
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assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_second; // @[dec_tlu_ctl.scala 948:45]
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assign csr_io_take_nmi = int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 949:45]
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assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 950:45]
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assign csr_io_exc_cause_r = int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 951:45]
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assign csr_io_i0_valid_wb = int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 952:45]
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assign csr_io_interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 954:45]
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assign csr_io_i0_exception_valid_r_d1 = int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 956:45]
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assign csr_io_exc_cause_wb = int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 958:45]
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assign csr_io_nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 959:45]
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assign csr_io_nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 960:45]
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assign csr_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 961:45]
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assign csr_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 962:45]
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assign csr_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 963:45]
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assign csr_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 964:45]
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assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 966:45]
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assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 967:45]
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assign csr_io_ext_int_freeze = int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 820:32]
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assign csr_io_ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 969:45]
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assign csr_io_iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 970:45]
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assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 972:45]
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assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 973:45]
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assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 974:45]
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assign csr_io_dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 975:45]
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assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 976:59]
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assign csr_io_take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 977:55]
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assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 978:43]
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assign csr_io_trigger_hit_r_d1 = int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 979:43]
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assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 980:43]
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assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 981:45]
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assign csr_io_debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 982:51]
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assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 983:45]
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assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 984:45]
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assign csr_io_enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 985:45]
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assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 986:45]
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assign csr_io_request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 987:45]
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assign csr_io_request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 988:45]
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assign csr_io_update_hit_bit_r = _T_485 & _T_492; // @[dec_tlu_ctl.scala 989:45]
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assign csr_io_take_timer_int = int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 990:45]
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assign csr_io_take_int_timer0_int = int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 991:45]
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assign csr_io_take_int_timer1_int = int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 992:45]
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assign csr_io_take_ext_int = int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 993:45]
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assign csr_io_tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 994:45]
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assign csr_io_dec_tlu_br0_error_r = _T_635 & _T_611; // @[dec_tlu_ctl.scala 995:45]
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assign csr_io_dec_tlu_br0_start_error_r = _T_638 & _T_611; // @[dec_tlu_ctl.scala 996:45]
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assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 997:45]
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assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 998:45]
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assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1000:45]
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|
assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1000:45]
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assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1000:45]
|
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assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1000:45]
|
|
assign csr_io_trigger_enabled = {_T_412,_T_411}; // @[dec_tlu_ctl.scala 999:45]
|
|
assign int_timers_clock = clock;
|
|
assign int_timers_reset = reset;
|
|
assign int_timers_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 285:65]
|
|
assign int_timers_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 321:52]
|
|
assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 287:49]
|
|
assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 289:49]
|
|
assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 290:49]
|
|
assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 291:57]
|
|
assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 292:57]
|
|
assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 293:57]
|
|
assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 294:57]
|
|
assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 295:57]
|
|
assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 296:57]
|
|
assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 297:49]
|
|
assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 298:49]
|
|
assign int_timers_io_internal_dbg_halt_timers = int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 299:47]
|
|
assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1018:37]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
dbg_halt_state_f = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
mpc_halt_state_f = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_8 = _RAND_2[6:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
syncro_ff = _RAND_3[6:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
debug_mode_status = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
i_cpu_run_req_d1_raw = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
nmi_int_delayed = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
nmi_int_detected_f = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
int_timer0_int_hold_f = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
int_timer1_int_hold_f = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
i_cpu_halt_req_d1 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
reset_detect = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
reset_detected = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
dec_pause_state_f = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
debug_halt_req_f = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
pmu_fw_halt_req_f = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
halt_taken_f = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
ifu_ic_error_start_f = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
debug_resume_req_f_raw = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
dcsr_single_step_running_f = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
dcsr_single_step_done_f = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
internal_pmu_fw_halt_mode_f = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
ifu_iccm_rd_ecc_single_err_f = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
iccm_repair_state_d1 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
dbg_halt_req_held = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
trigger_hit_dmode_r_d1 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
ebreak_to_debug_mode_r_d1 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
lsu_idle_any_f = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
ifu_miss_state_idle_f = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
debug_halt_req_d1 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
dec_tlu_flush_noredir_r_d1 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
dec_tlu_flush_pause_r_d1 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
dbg_tlu_halted_f = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
pmu_fw_tlu_halted_f = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
lsu_pmu_load_external_r = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
lsu_pmu_store_external_r = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
tlu_flush_lower_r_d1 = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_52 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
internal_dbg_halt_mode_f2 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
_T_59 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
nmi_lsu_load_type_f = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
nmi_lsu_store_type_f = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
mpc_debug_halt_req_sync_f = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
mpc_debug_run_req_sync_f = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
mpc_run_state_f = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
mpc_debug_run_ack_f = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
debug_brkpt_status_f = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
mpc_debug_halt_ack_f = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
dbg_run_state_f = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
_T_143 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
request_debug_mode_r_d1 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
request_debug_mode_done_f = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_286 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
dec_tlu_wr_pause_r_d1 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
_T_512 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
_T_516 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
_T_520 = _RAND_56[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
dbg_halt_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_halt_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_8 = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
syncro_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_mode_status = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i_cpu_run_req_d1_raw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_int_delayed = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_int_detected_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
int_timer0_int_hold_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
int_timer1_int_hold_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i_cpu_halt_req_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_detect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
reset_detected = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_pause_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_halt_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pmu_fw_halt_req_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
halt_taken_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_ic_error_start_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_resume_req_f_raw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dcsr_single_step_running_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dcsr_single_step_done_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
internal_pmu_fw_halt_mode_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_iccm_rd_ecc_single_err_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
iccm_repair_state_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_halt_req_held = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
trigger_hit_dmode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ebreak_to_debug_mode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_idle_any_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ifu_miss_state_idle_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_halt_req_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_flush_noredir_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_flush_pause_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_tlu_halted_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pmu_fw_tlu_halted_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_load_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_pmu_store_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
tlu_flush_lower_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
internal_dbg_halt_mode_f2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_lsu_load_type_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
nmi_lsu_store_type_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_halt_req_sync_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_run_req_sync_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_run_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_run_ack_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
debug_brkpt_status_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
mpc_debug_halt_ack_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_run_state_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_143 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
request_debug_mode_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
request_debug_mode_done_f = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_286 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dec_tlu_wr_pause_r_d1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_512 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_516 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_520 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_halt_state_f <= 1'h0;
|
|
end else if (_T_135) begin
|
|
dbg_halt_state_f <= dbg_halt_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_halt_state_f <= 1'h0;
|
|
end else if (_T_119) begin
|
|
mpc_halt_state_f <= mpc_halt_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_8 <= 7'h0;
|
|
end else begin
|
|
_T_8 <= {_T_6,_T_3};
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
syncro_ff <= 7'h0;
|
|
end else begin
|
|
syncro_ff <= _T_8;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_mode_status <= 1'h0;
|
|
end else if (_T_38) begin
|
|
debug_mode_status <= internal_dbg_halt_mode;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
i_cpu_run_req_d1_raw <= 1'h0;
|
|
end else if (_T_507) begin
|
|
i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_int_delayed <= 1'h0;
|
|
end else if (_T_61) begin
|
|
nmi_int_delayed <= nmi_int_sync;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_int_detected_f <= 1'h0;
|
|
end else if (_T_64) begin
|
|
nmi_int_detected_f <= nmi_int_detected;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
int_timer0_int_hold_f <= 1'h0;
|
|
end else if (_T_534) begin
|
|
int_timer0_int_hold_f <= int_timer0_int_hold;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
int_timer1_int_hold_f <= 1'h0;
|
|
end else if (_T_538) begin
|
|
int_timer1_int_hold_f <= int_timer1_int_hold;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
i_cpu_halt_req_d1 <= 1'h0;
|
|
end else if (_T_504) begin
|
|
i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_detect <= 1'h0;
|
|
end else begin
|
|
reset_detect <= _T_104 | reset_detect;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
reset_detected <= 1'h0;
|
|
end else if (_T_107) begin
|
|
reset_detected <= reset_detect;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_pause_state_f <= 1'h0;
|
|
end else if (_T_311) begin
|
|
dec_pause_state_f <= io_dec_pause_state;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_halt_req_f <= 1'h0;
|
|
end else if (_T_289) begin
|
|
debug_halt_req_f <= debug_halt_req_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
pmu_fw_halt_req_f <= 1'h0;
|
|
end else if (_T_526) begin
|
|
pmu_fw_halt_req_f <= pmu_fw_halt_req_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
halt_taken_f <= 1'h0;
|
|
end else if (_T_269) begin
|
|
halt_taken_f <= halt_taken;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_ic_error_start_f <= 1'h0;
|
|
end else if (_T_24) begin
|
|
ifu_ic_error_start_f <= io_tlu_mem_ifu_ic_error_start;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_resume_req_f_raw <= 1'h0;
|
|
end else if (_T_293) begin
|
|
debug_resume_req_f_raw <= debug_resume_req;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcsr_single_step_running_f <= 1'h0;
|
|
end else if (_T_323) begin
|
|
dcsr_single_step_running_f <= dcsr_single_step_running;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dcsr_single_step_done_f <= 1'h0;
|
|
end else if (_T_301) begin
|
|
dcsr_single_step_done_f <= dcsr_single_step_done;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
internal_pmu_fw_halt_mode_f <= 1'h0;
|
|
end else if (_T_522) begin
|
|
internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_iccm_rd_ecc_single_err_f <= 1'h0;
|
|
end else if (_T_27) begin
|
|
ifu_iccm_rd_ecc_single_err_f <= io_tlu_mem_ifu_iccm_rd_ecc_single_err;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
iccm_repair_state_d1 <= 1'h0;
|
|
end else if (_T_30) begin
|
|
iccm_repair_state_d1 <= iccm_repair_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_halt_req_held <= 1'h0;
|
|
end else if (_T_331) begin
|
|
dbg_halt_req_held <= dbg_halt_req_held_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
trigger_hit_dmode_r_d1 <= 1'h0;
|
|
end else if (_T_297) begin
|
|
trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ebreak_to_debug_mode_r_d1 <= 1'h0;
|
|
end else begin
|
|
ebreak_to_debug_mode_r_d1 <= _T_704 & _T_590;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_idle_any_f <= 1'h0;
|
|
end else if (_T_273) begin
|
|
lsu_idle_any_f <= io_lsu_idle_any;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
ifu_miss_state_idle_f <= 1'h0;
|
|
end else if (_T_277) begin
|
|
ifu_miss_state_idle_f <= io_tlu_mem_ifu_miss_state_idle;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_halt_req_d1 <= 1'h0;
|
|
end else if (_T_305) begin
|
|
debug_halt_req_d1 <= debug_halt_req;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_flush_noredir_r_d1 <= 1'h0;
|
|
end else if (_T_265) begin
|
|
dec_tlu_flush_noredir_r_d1 <= io_tlu_ifc_dec_tlu_flush_noredir_wb;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_flush_pause_r_d1 <= 1'h0;
|
|
end else if (_T_327) begin
|
|
dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_tlu_halted_f <= 1'h0;
|
|
end else if (_T_281) begin
|
|
dbg_tlu_halted_f <= dbg_tlu_halted;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
pmu_fw_tlu_halted_f <= 1'h0;
|
|
end else if (_T_530) begin
|
|
pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_load_external_r <= 1'h0;
|
|
end else if (_T_41) begin
|
|
lsu_pmu_load_external_r <= io_lsu_tlu_lsu_pmu_load_external_m;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_pmu_store_external_r <= 1'h0;
|
|
end else if (_T_44) begin
|
|
lsu_pmu_store_external_r <= io_lsu_tlu_lsu_pmu_store_external_m;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
tlu_flush_lower_r_d1 <= 1'h0;
|
|
end else if (_T_47) begin
|
|
tlu_flush_lower_r_d1 <= tlu_flush_lower_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_52 <= 1'h0;
|
|
end else if (_T_51) begin
|
|
_T_52 <= tlu_i0_kill_writeb_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
internal_dbg_halt_mode_f2 <= 1'h0;
|
|
end else if (_T_54) begin
|
|
internal_dbg_halt_mode_f2 <= debug_mode_status;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_59 <= 1'h0;
|
|
end else if (_T_58) begin
|
|
_T_59 <= force_halt;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_lsu_load_type_f <= 1'h0;
|
|
end else if (_T_67) begin
|
|
nmi_lsu_load_type_f <= nmi_lsu_load_type;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
nmi_lsu_store_type_f <= 1'h0;
|
|
end else if (_T_70) begin
|
|
nmi_lsu_store_type_f <= nmi_lsu_store_type;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_halt_req_sync_f <= 1'h0;
|
|
end else if (_T_112) begin
|
|
mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_run_req_sync_f <= 1'h0;
|
|
end else if (_T_115) begin
|
|
mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_run_state_f <= 1'h0;
|
|
end else if (_T_122) begin
|
|
mpc_run_state_f <= mpc_run_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_run_ack_f <= 1'h0;
|
|
end else if (_T_131) begin
|
|
mpc_debug_run_ack_f <= mpc_debug_run_ack_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
debug_brkpt_status_f <= 1'h0;
|
|
end else if (_T_125) begin
|
|
debug_brkpt_status_f <= debug_brkpt_status_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
mpc_debug_halt_ack_f <= 1'h0;
|
|
end else if (_T_128) begin
|
|
mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_run_state_f <= 1'h0;
|
|
end else if (_T_138) begin
|
|
dbg_run_state_f <= dbg_run_state_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_143 <= 1'h0;
|
|
end else if (_T_142) begin
|
|
_T_143 <= _T_1;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
request_debug_mode_r_d1 <= 1'h0;
|
|
end else if (_T_315) begin
|
|
request_debug_mode_r_d1 <= request_debug_mode_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
request_debug_mode_done_f <= 1'h0;
|
|
end else if (_T_319) begin
|
|
request_debug_mode_done_f <= request_debug_mode_done;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_286 <= 1'h0;
|
|
end else if (_T_285) begin
|
|
_T_286 <= resume_ack_ns;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
dec_tlu_wr_pause_r_d1 <= 1'h0;
|
|
end else if (_T_308) begin
|
|
dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_512 <= 1'h0;
|
|
end else if (_T_511) begin
|
|
_T_512 <= cpu_halt_status;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_516 <= 1'h0;
|
|
end else if (_T_515) begin
|
|
_T_516 <= cpu_halt_ack;
|
|
end
|
|
end
|
|
always @(posedge io_free_l2clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_520 <= 1'h0;
|
|
end else if (_T_519) begin
|
|
_T_520 <= cpu_run_ack;
|
|
end
|
|
end
|
|
endmodule
|
|
module dec_trigger(
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_execute,
|
|
input io_trigger_pkt_any_0_m,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_execute,
|
|
input io_trigger_pkt_any_1_m,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_execute,
|
|
input io_trigger_pkt_any_2_m,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_execute,
|
|
input io_trigger_pkt_any_3_m,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input [30:0] io_dec_i0_pc_d,
|
|
output [3:0] io_dec_i0_trigger_match_d
|
|
);
|
|
wire _T = ~io_trigger_pkt_any_0_select; // @[dec_trigger.scala 14:63]
|
|
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[dec_trigger.scala 14:93]
|
|
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[dec_trigger.scala 14:127]
|
|
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[dec_trigger.scala 14:63]
|
|
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[dec_trigger.scala 14:93]
|
|
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[dec_trigger.scala 14:127]
|
|
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[dec_trigger.scala 14:63]
|
|
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[dec_trigger.scala 14:93]
|
|
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[dec_trigger.scala 14:127]
|
|
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[dec_trigger.scala 14:63]
|
|
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[dec_trigger.scala 14:93]
|
|
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
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|
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
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|
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
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|
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[dec_trigger.scala 14:127]
|
|
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[dec_trigger.scala 15:83]
|
|
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 107:45]
|
|
wire _T_152 = ~_T_151; // @[lib.scala 107:39]
|
|
wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[lib.scala 107:37]
|
|
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[lib.scala 108:52]
|
|
wire _T_157 = _T_153 | _T_156; // @[lib.scala 108:41]
|
|
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_160 = _T_159 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[lib.scala 110:80]
|
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wire _T_164 = _T_160 | _T_163; // @[lib.scala 110:25]
|
|
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 110:38]
|
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wire _T_167 = _T_166 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[lib.scala 110:80]
|
|
wire _T_171 = _T_167 | _T_170; // @[lib.scala 110:25]
|
|
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_174 = _T_173 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[lib.scala 110:80]
|
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wire _T_178 = _T_174 | _T_177; // @[lib.scala 110:25]
|
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wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 110:38]
|
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wire _T_181 = _T_180 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[lib.scala 110:80]
|
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wire _T_185 = _T_181 | _T_184; // @[lib.scala 110:25]
|
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wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_188 = _T_187 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[lib.scala 110:80]
|
|
wire _T_192 = _T_188 | _T_191; // @[lib.scala 110:25]
|
|
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_195 = _T_194 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[lib.scala 110:80]
|
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wire _T_199 = _T_195 | _T_198; // @[lib.scala 110:25]
|
|
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_202 = _T_201 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[lib.scala 110:80]
|
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wire _T_206 = _T_202 | _T_205; // @[lib.scala 110:25]
|
|
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_209 = _T_208 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[lib.scala 110:80]
|
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wire _T_213 = _T_209 | _T_212; // @[lib.scala 110:25]
|
|
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_216 = _T_215 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[lib.scala 110:80]
|
|
wire _T_220 = _T_216 | _T_219; // @[lib.scala 110:25]
|
|
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_223 = _T_222 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[lib.scala 110:80]
|
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wire _T_227 = _T_223 | _T_226; // @[lib.scala 110:25]
|
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wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 110:38]
|
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wire _T_230 = _T_229 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[lib.scala 110:80]
|
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wire _T_234 = _T_230 | _T_233; // @[lib.scala 110:25]
|
|
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_237 = _T_236 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[lib.scala 110:80]
|
|
wire _T_241 = _T_237 | _T_240; // @[lib.scala 110:25]
|
|
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_244 = _T_243 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[lib.scala 110:80]
|
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wire _T_248 = _T_244 | _T_247; // @[lib.scala 110:25]
|
|
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_251 = _T_250 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[lib.scala 110:80]
|
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wire _T_255 = _T_251 | _T_254; // @[lib.scala 110:25]
|
|
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_258 = _T_257 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[lib.scala 110:80]
|
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wire _T_262 = _T_258 | _T_261; // @[lib.scala 110:25]
|
|
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_265 = _T_264 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[lib.scala 110:80]
|
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wire _T_269 = _T_265 | _T_268; // @[lib.scala 110:25]
|
|
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_272 = _T_271 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[lib.scala 110:80]
|
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wire _T_276 = _T_272 | _T_275; // @[lib.scala 110:25]
|
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wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 110:38]
|
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wire _T_279 = _T_278 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[lib.scala 110:80]
|
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wire _T_283 = _T_279 | _T_282; // @[lib.scala 110:25]
|
|
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_286 = _T_285 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[lib.scala 110:80]
|
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wire _T_290 = _T_286 | _T_289; // @[lib.scala 110:25]
|
|
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_293 = _T_292 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[lib.scala 110:80]
|
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wire _T_297 = _T_293 | _T_296; // @[lib.scala 110:25]
|
|
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_300 = _T_299 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[lib.scala 110:80]
|
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wire _T_304 = _T_300 | _T_303; // @[lib.scala 110:25]
|
|
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 110:38]
|
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wire _T_307 = _T_306 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[lib.scala 110:80]
|
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wire _T_311 = _T_307 | _T_310; // @[lib.scala 110:25]
|
|
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_314 = _T_313 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[lib.scala 110:80]
|
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wire _T_318 = _T_314 | _T_317; // @[lib.scala 110:25]
|
|
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_321 = _T_320 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[lib.scala 110:80]
|
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wire _T_325 = _T_321 | _T_324; // @[lib.scala 110:25]
|
|
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_328 = _T_327 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[lib.scala 110:80]
|
|
wire _T_332 = _T_328 | _T_331; // @[lib.scala 110:25]
|
|
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_335 = _T_334 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[lib.scala 110:80]
|
|
wire _T_339 = _T_335 | _T_338; // @[lib.scala 110:25]
|
|
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_342 = _T_341 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[lib.scala 110:80]
|
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wire _T_346 = _T_342 | _T_345; // @[lib.scala 110:25]
|
|
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_349 = _T_348 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[lib.scala 110:80]
|
|
wire _T_353 = _T_349 | _T_352; // @[lib.scala 110:25]
|
|
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_356 = _T_355 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[lib.scala 110:80]
|
|
wire _T_360 = _T_356 | _T_359; // @[lib.scala 110:25]
|
|
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_363 = _T_362 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[lib.scala 110:80]
|
|
wire _T_367 = _T_363 | _T_366; // @[lib.scala 110:25]
|
|
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_370 = _T_369 & _T_153; // @[lib.scala 110:43]
|
|
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[lib.scala 110:80]
|
|
wire _T_374 = _T_370 | _T_373; // @[lib.scala 110:25]
|
|
wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[lib.scala 111:14]
|
|
wire _T_406 = &_T_405; // @[lib.scala 111:25]
|
|
wire _T_407 = _T_148 & _T_406; // @[dec_trigger.scala 15:109]
|
|
wire _T_408 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83]
|
|
wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 107:45]
|
|
wire _T_412 = ~_T_411; // @[lib.scala 107:39]
|
|
wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[lib.scala 107:37]
|
|
wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 108:52]
|
|
wire _T_417 = _T_413 | _T_416; // @[lib.scala 108:41]
|
|
wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_420 = _T_419 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 110:80]
|
|
wire _T_424 = _T_420 | _T_423; // @[lib.scala 110:25]
|
|
wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_427 = _T_426 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 110:80]
|
|
wire _T_431 = _T_427 | _T_430; // @[lib.scala 110:25]
|
|
wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_434 = _T_433 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 110:80]
|
|
wire _T_438 = _T_434 | _T_437; // @[lib.scala 110:25]
|
|
wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_441 = _T_440 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 110:80]
|
|
wire _T_445 = _T_441 | _T_444; // @[lib.scala 110:25]
|
|
wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_448 = _T_447 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 110:80]
|
|
wire _T_452 = _T_448 | _T_451; // @[lib.scala 110:25]
|
|
wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_455 = _T_454 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 110:80]
|
|
wire _T_459 = _T_455 | _T_458; // @[lib.scala 110:25]
|
|
wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_462 = _T_461 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 110:80]
|
|
wire _T_466 = _T_462 | _T_465; // @[lib.scala 110:25]
|
|
wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_469 = _T_468 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 110:80]
|
|
wire _T_473 = _T_469 | _T_472; // @[lib.scala 110:25]
|
|
wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_476 = _T_475 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 110:80]
|
|
wire _T_480 = _T_476 | _T_479; // @[lib.scala 110:25]
|
|
wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_483 = _T_482 & _T_413; // @[lib.scala 110:43]
|
|
wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 110:80]
|
|
wire _T_487 = _T_483 | _T_486; // @[lib.scala 110:25]
|
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wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 110:38]
|
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wire _T_490 = _T_489 & _T_413; // @[lib.scala 110:43]
|
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wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 110:80]
|
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wire _T_494 = _T_490 | _T_493; // @[lib.scala 110:25]
|
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wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 110:38]
|
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wire _T_497 = _T_496 & _T_413; // @[lib.scala 110:43]
|
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wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 110:80]
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wire _T_501 = _T_497 | _T_500; // @[lib.scala 110:25]
|
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wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 110:38]
|
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wire _T_504 = _T_503 & _T_413; // @[lib.scala 110:43]
|
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wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 110:80]
|
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wire _T_508 = _T_504 | _T_507; // @[lib.scala 110:25]
|
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wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 110:38]
|
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wire _T_511 = _T_510 & _T_413; // @[lib.scala 110:43]
|
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wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 110:80]
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wire _T_515 = _T_511 | _T_514; // @[lib.scala 110:25]
|
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wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 110:38]
|
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wire _T_518 = _T_517 & _T_413; // @[lib.scala 110:43]
|
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wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 110:80]
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wire _T_522 = _T_518 | _T_521; // @[lib.scala 110:25]
|
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wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 110:38]
|
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wire _T_525 = _T_524 & _T_413; // @[lib.scala 110:43]
|
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wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 110:80]
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wire _T_529 = _T_525 | _T_528; // @[lib.scala 110:25]
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wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 110:38]
|
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wire _T_532 = _T_531 & _T_413; // @[lib.scala 110:43]
|
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wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 110:80]
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wire _T_536 = _T_532 | _T_535; // @[lib.scala 110:25]
|
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wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 110:38]
|
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wire _T_539 = _T_538 & _T_413; // @[lib.scala 110:43]
|
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wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 110:80]
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wire _T_543 = _T_539 | _T_542; // @[lib.scala 110:25]
|
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wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 110:38]
|
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wire _T_546 = _T_545 & _T_413; // @[lib.scala 110:43]
|
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wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 110:80]
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wire _T_550 = _T_546 | _T_549; // @[lib.scala 110:25]
|
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wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 110:38]
|
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wire _T_553 = _T_552 & _T_413; // @[lib.scala 110:43]
|
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wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 110:80]
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wire _T_557 = _T_553 | _T_556; // @[lib.scala 110:25]
|
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wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 110:38]
|
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wire _T_560 = _T_559 & _T_413; // @[lib.scala 110:43]
|
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wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 110:80]
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wire _T_564 = _T_560 | _T_563; // @[lib.scala 110:25]
|
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wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 110:38]
|
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wire _T_567 = _T_566 & _T_413; // @[lib.scala 110:43]
|
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wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 110:80]
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wire _T_571 = _T_567 | _T_570; // @[lib.scala 110:25]
|
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wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 110:38]
|
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wire _T_574 = _T_573 & _T_413; // @[lib.scala 110:43]
|
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wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 110:80]
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wire _T_578 = _T_574 | _T_577; // @[lib.scala 110:25]
|
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wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 110:38]
|
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wire _T_581 = _T_580 & _T_413; // @[lib.scala 110:43]
|
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wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 110:80]
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wire _T_585 = _T_581 | _T_584; // @[lib.scala 110:25]
|
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wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 110:38]
|
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wire _T_588 = _T_587 & _T_413; // @[lib.scala 110:43]
|
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wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 110:80]
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wire _T_592 = _T_588 | _T_591; // @[lib.scala 110:25]
|
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wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 110:38]
|
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wire _T_595 = _T_594 & _T_413; // @[lib.scala 110:43]
|
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wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 110:80]
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wire _T_599 = _T_595 | _T_598; // @[lib.scala 110:25]
|
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wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 110:38]
|
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wire _T_602 = _T_601 & _T_413; // @[lib.scala 110:43]
|
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wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 110:80]
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wire _T_606 = _T_602 | _T_605; // @[lib.scala 110:25]
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wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 110:38]
|
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wire _T_609 = _T_608 & _T_413; // @[lib.scala 110:43]
|
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wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 110:80]
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wire _T_613 = _T_609 | _T_612; // @[lib.scala 110:25]
|
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wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 110:38]
|
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wire _T_616 = _T_615 & _T_413; // @[lib.scala 110:43]
|
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wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 110:80]
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wire _T_620 = _T_616 | _T_619; // @[lib.scala 110:25]
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wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 110:38]
|
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wire _T_623 = _T_622 & _T_413; // @[lib.scala 110:43]
|
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wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 110:80]
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wire _T_627 = _T_623 | _T_626; // @[lib.scala 110:25]
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wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 110:38]
|
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wire _T_630 = _T_629 & _T_413; // @[lib.scala 110:43]
|
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wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 110:80]
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wire _T_634 = _T_630 | _T_633; // @[lib.scala 110:25]
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wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[lib.scala 111:14]
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wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[lib.scala 111:14]
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wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[lib.scala 111:14]
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wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[lib.scala 111:14]
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wire _T_666 = &_T_665; // @[lib.scala 111:25]
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wire _T_667 = _T_408 & _T_666; // @[dec_trigger.scala 15:109]
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wire _T_668 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83]
|
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wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 107:45]
|
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wire _T_672 = ~_T_671; // @[lib.scala 107:39]
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wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[lib.scala 107:37]
|
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wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 108:52]
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wire _T_677 = _T_673 | _T_676; // @[lib.scala 108:41]
|
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wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 110:38]
|
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wire _T_680 = _T_679 & _T_673; // @[lib.scala 110:43]
|
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wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 110:80]
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wire _T_684 = _T_680 | _T_683; // @[lib.scala 110:25]
|
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wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 110:38]
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wire _T_687 = _T_686 & _T_673; // @[lib.scala 110:43]
|
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wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 110:80]
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wire _T_691 = _T_687 | _T_690; // @[lib.scala 110:25]
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wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 110:38]
|
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wire _T_694 = _T_693 & _T_673; // @[lib.scala 110:43]
|
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wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 110:80]
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wire _T_698 = _T_694 | _T_697; // @[lib.scala 110:25]
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wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 110:38]
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wire _T_701 = _T_700 & _T_673; // @[lib.scala 110:43]
|
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wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 110:80]
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wire _T_705 = _T_701 | _T_704; // @[lib.scala 110:25]
|
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wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 110:38]
|
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wire _T_708 = _T_707 & _T_673; // @[lib.scala 110:43]
|
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wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 110:80]
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wire _T_712 = _T_708 | _T_711; // @[lib.scala 110:25]
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wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 110:38]
|
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wire _T_715 = _T_714 & _T_673; // @[lib.scala 110:43]
|
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wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 110:80]
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wire _T_719 = _T_715 | _T_718; // @[lib.scala 110:25]
|
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wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 110:38]
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wire _T_722 = _T_721 & _T_673; // @[lib.scala 110:43]
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wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 110:80]
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wire _T_726 = _T_722 | _T_725; // @[lib.scala 110:25]
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wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 110:38]
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wire _T_729 = _T_728 & _T_673; // @[lib.scala 110:43]
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wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 110:80]
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wire _T_733 = _T_729 | _T_732; // @[lib.scala 110:25]
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wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 110:38]
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wire _T_736 = _T_735 & _T_673; // @[lib.scala 110:43]
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wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 110:80]
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wire _T_740 = _T_736 | _T_739; // @[lib.scala 110:25]
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wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 110:38]
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wire _T_743 = _T_742 & _T_673; // @[lib.scala 110:43]
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wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 110:80]
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wire _T_747 = _T_743 | _T_746; // @[lib.scala 110:25]
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wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 110:38]
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wire _T_750 = _T_749 & _T_673; // @[lib.scala 110:43]
|
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wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 110:80]
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wire _T_754 = _T_750 | _T_753; // @[lib.scala 110:25]
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wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 110:38]
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wire _T_757 = _T_756 & _T_673; // @[lib.scala 110:43]
|
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wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 110:80]
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wire _T_761 = _T_757 | _T_760; // @[lib.scala 110:25]
|
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wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 110:38]
|
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wire _T_764 = _T_763 & _T_673; // @[lib.scala 110:43]
|
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wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 110:80]
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wire _T_768 = _T_764 | _T_767; // @[lib.scala 110:25]
|
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wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_771 = _T_770 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 110:80]
|
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wire _T_775 = _T_771 | _T_774; // @[lib.scala 110:25]
|
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wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_778 = _T_777 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 110:80]
|
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wire _T_782 = _T_778 | _T_781; // @[lib.scala 110:25]
|
|
wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_785 = _T_784 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 110:80]
|
|
wire _T_789 = _T_785 | _T_788; // @[lib.scala 110:25]
|
|
wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_792 = _T_791 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 110:80]
|
|
wire _T_796 = _T_792 | _T_795; // @[lib.scala 110:25]
|
|
wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_799 = _T_798 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 110:80]
|
|
wire _T_803 = _T_799 | _T_802; // @[lib.scala 110:25]
|
|
wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_806 = _T_805 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 110:80]
|
|
wire _T_810 = _T_806 | _T_809; // @[lib.scala 110:25]
|
|
wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_813 = _T_812 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 110:80]
|
|
wire _T_817 = _T_813 | _T_816; // @[lib.scala 110:25]
|
|
wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_820 = _T_819 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 110:80]
|
|
wire _T_824 = _T_820 | _T_823; // @[lib.scala 110:25]
|
|
wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_827 = _T_826 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 110:80]
|
|
wire _T_831 = _T_827 | _T_830; // @[lib.scala 110:25]
|
|
wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_834 = _T_833 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 110:80]
|
|
wire _T_838 = _T_834 | _T_837; // @[lib.scala 110:25]
|
|
wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_841 = _T_840 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 110:80]
|
|
wire _T_845 = _T_841 | _T_844; // @[lib.scala 110:25]
|
|
wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_848 = _T_847 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 110:80]
|
|
wire _T_852 = _T_848 | _T_851; // @[lib.scala 110:25]
|
|
wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_855 = _T_854 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 110:80]
|
|
wire _T_859 = _T_855 | _T_858; // @[lib.scala 110:25]
|
|
wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_862 = _T_861 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 110:80]
|
|
wire _T_866 = _T_862 | _T_865; // @[lib.scala 110:25]
|
|
wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_869 = _T_868 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 110:80]
|
|
wire _T_873 = _T_869 | _T_872; // @[lib.scala 110:25]
|
|
wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_876 = _T_875 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 110:80]
|
|
wire _T_880 = _T_876 | _T_879; // @[lib.scala 110:25]
|
|
wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_883 = _T_882 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 110:80]
|
|
wire _T_887 = _T_883 | _T_886; // @[lib.scala 110:25]
|
|
wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_890 = _T_889 & _T_673; // @[lib.scala 110:43]
|
|
wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 110:80]
|
|
wire _T_894 = _T_890 | _T_893; // @[lib.scala 110:25]
|
|
wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[lib.scala 111:14]
|
|
wire _T_926 = &_T_925; // @[lib.scala 111:25]
|
|
wire _T_927 = _T_668 & _T_926; // @[dec_trigger.scala 15:109]
|
|
wire _T_928 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83]
|
|
wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 107:45]
|
|
wire _T_932 = ~_T_931; // @[lib.scala 107:39]
|
|
wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[lib.scala 107:37]
|
|
wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 108:52]
|
|
wire _T_937 = _T_933 | _T_936; // @[lib.scala 108:41]
|
|
wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_940 = _T_939 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 110:80]
|
|
wire _T_944 = _T_940 | _T_943; // @[lib.scala 110:25]
|
|
wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_947 = _T_946 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 110:80]
|
|
wire _T_951 = _T_947 | _T_950; // @[lib.scala 110:25]
|
|
wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_954 = _T_953 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 110:80]
|
|
wire _T_958 = _T_954 | _T_957; // @[lib.scala 110:25]
|
|
wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_961 = _T_960 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 110:80]
|
|
wire _T_965 = _T_961 | _T_964; // @[lib.scala 110:25]
|
|
wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_968 = _T_967 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 110:80]
|
|
wire _T_972 = _T_968 | _T_971; // @[lib.scala 110:25]
|
|
wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_975 = _T_974 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 110:80]
|
|
wire _T_979 = _T_975 | _T_978; // @[lib.scala 110:25]
|
|
wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_982 = _T_981 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 110:80]
|
|
wire _T_986 = _T_982 | _T_985; // @[lib.scala 110:25]
|
|
wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_989 = _T_988 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 110:80]
|
|
wire _T_993 = _T_989 | _T_992; // @[lib.scala 110:25]
|
|
wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_996 = _T_995 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 110:80]
|
|
wire _T_1000 = _T_996 | _T_999; // @[lib.scala 110:25]
|
|
wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_1003 = _T_1002 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 110:80]
|
|
wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 110:25]
|
|
wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 110:38]
|
|
wire _T_1010 = _T_1009 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 110:80]
|
|
wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 110:25]
|
|
wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_1017 = _T_1016 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 110:80]
|
|
wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 110:25]
|
|
wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_1024 = _T_1023 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 110:80]
|
|
wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 110:25]
|
|
wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_1031 = _T_1030 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 110:80]
|
|
wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 110:25]
|
|
wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_1038 = _T_1037 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 110:80]
|
|
wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 110:25]
|
|
wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_1045 = _T_1044 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 110:80]
|
|
wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 110:25]
|
|
wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_1052 = _T_1051 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 110:80]
|
|
wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 110:25]
|
|
wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_1059 = _T_1058 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 110:80]
|
|
wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 110:25]
|
|
wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_1066 = _T_1065 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 110:80]
|
|
wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 110:25]
|
|
wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_1073 = _T_1072 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 110:80]
|
|
wire _T_1077 = _T_1073 | _T_1076; // @[lib.scala 110:25]
|
|
wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_1080 = _T_1079 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 110:80]
|
|
wire _T_1084 = _T_1080 | _T_1083; // @[lib.scala 110:25]
|
|
wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_1087 = _T_1086 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 110:80]
|
|
wire _T_1091 = _T_1087 | _T_1090; // @[lib.scala 110:25]
|
|
wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_1094 = _T_1093 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 110:80]
|
|
wire _T_1098 = _T_1094 | _T_1097; // @[lib.scala 110:25]
|
|
wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_1101 = _T_1100 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 110:80]
|
|
wire _T_1105 = _T_1101 | _T_1104; // @[lib.scala 110:25]
|
|
wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_1108 = _T_1107 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 110:80]
|
|
wire _T_1112 = _T_1108 | _T_1111; // @[lib.scala 110:25]
|
|
wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_1115 = _T_1114 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 110:80]
|
|
wire _T_1119 = _T_1115 | _T_1118; // @[lib.scala 110:25]
|
|
wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_1122 = _T_1121 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 110:80]
|
|
wire _T_1126 = _T_1122 | _T_1125; // @[lib.scala 110:25]
|
|
wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_1129 = _T_1128 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 110:80]
|
|
wire _T_1133 = _T_1129 | _T_1132; // @[lib.scala 110:25]
|
|
wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_1136 = _T_1135 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 110:80]
|
|
wire _T_1140 = _T_1136 | _T_1139; // @[lib.scala 110:25]
|
|
wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_1143 = _T_1142 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 110:80]
|
|
wire _T_1147 = _T_1143 | _T_1146; // @[lib.scala 110:25]
|
|
wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_1150 = _T_1149 & _T_933; // @[lib.scala 110:43]
|
|
wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 110:80]
|
|
wire _T_1154 = _T_1150 | _T_1153; // @[lib.scala 110:25]
|
|
wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[lib.scala 111:14]
|
|
wire _T_1186 = &_T_1185; // @[lib.scala 111:25]
|
|
wire _T_1187 = _T_928 & _T_1186; // @[dec_trigger.scala 15:109]
|
|
wire [2:0] _T_1189 = {_T_1187,_T_927,_T_667}; // @[Cat.scala 29:58]
|
|
assign io_dec_i0_trigger_match_d = {_T_1189,_T_407}; // @[dec_trigger.scala 15:29]
|
|
endmodule
|
|
module dec(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_active_clk,
|
|
input io_free_l2clk,
|
|
input io_lsu_fastint_stall_any,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
input [31:0] io_lsu_nonblock_load_data,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
input io_lsu_pmu_misaligned_m,
|
|
input [30:0] io_lsu_fir_addr,
|
|
input [1:0] io_lsu_fir_error,
|
|
input [3:0] io_lsu_trigger_match_m,
|
|
input io_lsu_idle_any,
|
|
input io_lsu_error_pkt_r_valid,
|
|
input io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
input io_lsu_error_pkt_r_bits_inst_type,
|
|
input io_lsu_error_pkt_r_bits_exc_type,
|
|
input [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
input [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
input io_lsu_single_ecc_error_incr,
|
|
input [31:0] io_exu_div_result,
|
|
input io_exu_div_wren,
|
|
input [31:0] io_lsu_result_m,
|
|
input [31:0] io_lsu_result_corr_r,
|
|
input io_lsu_load_stall_any,
|
|
input io_lsu_store_stall_any,
|
|
input io_iccm_dma_sb_error,
|
|
input io_exu_flush_final,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
input io_dbg_halt_req,
|
|
input io_dbg_resume_req,
|
|
output io_dec_tlu_dbg_halted,
|
|
output io_dec_tlu_resume_ack,
|
|
output io_dec_tlu_mpc_halted_only,
|
|
output [31:0] io_dec_dbg_rddata,
|
|
output [31:0] io_dec_csr_rddata_d,
|
|
output io_dec_dbg_cmd_done,
|
|
output io_dec_dbg_cmd_fail,
|
|
output io_trigger_pkt_any_0_select,
|
|
output io_trigger_pkt_any_0_match_pkt,
|
|
output io_trigger_pkt_any_0_store,
|
|
output io_trigger_pkt_any_0_load,
|
|
output io_trigger_pkt_any_0_m,
|
|
output [31:0] io_trigger_pkt_any_0_tdata2,
|
|
output io_trigger_pkt_any_1_select,
|
|
output io_trigger_pkt_any_1_match_pkt,
|
|
output io_trigger_pkt_any_1_store,
|
|
output io_trigger_pkt_any_1_load,
|
|
output io_trigger_pkt_any_1_m,
|
|
output [31:0] io_trigger_pkt_any_1_tdata2,
|
|
output io_trigger_pkt_any_2_select,
|
|
output io_trigger_pkt_any_2_match_pkt,
|
|
output io_trigger_pkt_any_2_store,
|
|
output io_trigger_pkt_any_2_load,
|
|
output io_trigger_pkt_any_2_m,
|
|
output [31:0] io_trigger_pkt_any_2_tdata2,
|
|
output io_trigger_pkt_any_3_select,
|
|
output io_trigger_pkt_any_3_match_pkt,
|
|
output io_trigger_pkt_any_3_store,
|
|
output io_trigger_pkt_any_3_load,
|
|
output io_trigger_pkt_any_3_m,
|
|
output [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_exu_i0_br_way_r,
|
|
output io_lsu_p_valid,
|
|
output io_lsu_p_bits_fast_int,
|
|
output io_lsu_p_bits_by,
|
|
output io_lsu_p_bits_half,
|
|
output io_lsu_p_bits_word,
|
|
output io_lsu_p_bits_load,
|
|
output io_lsu_p_bits_store,
|
|
output io_lsu_p_bits_unsign,
|
|
output io_lsu_p_bits_store_data_bypass_d,
|
|
output io_lsu_p_bits_load_ldst_bypass_d,
|
|
output [11:0] io_dec_lsu_offset_d,
|
|
output io_dec_tlu_i0_kill_writeb_r,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dec_lsu_valid_raw_d,
|
|
output io_trace_rv_trace_pkt_rv_i_valid_ip,
|
|
output [31:0] io_trace_rv_trace_pkt_rv_i_insn_ip,
|
|
output [31:0] io_trace_rv_trace_pkt_rv_i_address_ip,
|
|
output io_trace_rv_trace_pkt_rv_i_exception_ip,
|
|
output [4:0] io_trace_rv_trace_pkt_rv_i_ecause_ip,
|
|
output io_trace_rv_trace_pkt_rv_i_interrupt_ip,
|
|
output [31:0] io_trace_rv_trace_pkt_rv_i_tval_ip,
|
|
output io_dec_tlu_lsu_clk_override,
|
|
output io_dec_tlu_picio_clk_override,
|
|
output io_dec_tlu_dccm_clk_override,
|
|
output io_dec_tlu_icm_clk_override,
|
|
output io_dec_i0_decode_d,
|
|
input [15:0] io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst,
|
|
input io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf,
|
|
input [1:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type,
|
|
input io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second,
|
|
input io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc,
|
|
input [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index,
|
|
input [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr,
|
|
input [4:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag,
|
|
input io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid,
|
|
input [31:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr,
|
|
input [30:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc,
|
|
input io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4,
|
|
input io_ifu_dec_dec_aln_aln_ib_i0_brp_valid,
|
|
input [11:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset,
|
|
input [1:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist,
|
|
input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error,
|
|
input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error,
|
|
input [30:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett,
|
|
input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way,
|
|
input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret,
|
|
input io_ifu_dec_dec_aln_ifu_pmu_instr_aligned,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb,
|
|
output [70:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata,
|
|
output [16:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid,
|
|
output io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
|
|
input [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid,
|
|
input io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle,
|
|
output io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb,
|
|
output [31:0] io_ifu_dec_dec_ifc_dec_tlu_mrac_ff,
|
|
input io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall,
|
|
output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid,
|
|
output [1:0] io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist,
|
|
output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error,
|
|
output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error,
|
|
output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way,
|
|
output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle,
|
|
output io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb,
|
|
output io_ifu_dec_dec_bp_dec_tlu_bpred_disable,
|
|
output io_dec_exu_dec_alu_dec_i0_alu_decode_d,
|
|
output io_dec_exu_dec_alu_dec_csr_ren_d,
|
|
output [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d,
|
|
input [30:0] io_dec_exu_dec_alu_exu_i0_pc_x,
|
|
output io_dec_exu_dec_div_div_p_valid,
|
|
output io_dec_exu_dec_div_div_p_bits_unsign,
|
|
output io_dec_exu_dec_div_div_p_bits_rem,
|
|
output io_dec_exu_dec_div_dec_div_cancel,
|
|
output [1:0] io_dec_exu_decode_exu_dec_data_en,
|
|
output [1:0] io_dec_exu_decode_exu_dec_ctl_en,
|
|
output io_dec_exu_decode_exu_i0_ap_clz,
|
|
output io_dec_exu_decode_exu_i0_ap_ctz,
|
|
output io_dec_exu_decode_exu_i0_ap_pcnt,
|
|
output io_dec_exu_decode_exu_i0_ap_sext_b,
|
|
output io_dec_exu_decode_exu_i0_ap_sext_h,
|
|
output io_dec_exu_decode_exu_i0_ap_min,
|
|
output io_dec_exu_decode_exu_i0_ap_max,
|
|
output io_dec_exu_decode_exu_i0_ap_pack,
|
|
output io_dec_exu_decode_exu_i0_ap_packu,
|
|
output io_dec_exu_decode_exu_i0_ap_packh,
|
|
output io_dec_exu_decode_exu_i0_ap_rol,
|
|
output io_dec_exu_decode_exu_i0_ap_ror,
|
|
output io_dec_exu_decode_exu_i0_ap_grev,
|
|
output io_dec_exu_decode_exu_i0_ap_gorc,
|
|
output io_dec_exu_decode_exu_i0_ap_zbb,
|
|
output io_dec_exu_decode_exu_i0_ap_sbset,
|
|
output io_dec_exu_decode_exu_i0_ap_sbclr,
|
|
output io_dec_exu_decode_exu_i0_ap_sbinv,
|
|
output io_dec_exu_decode_exu_i0_ap_sbext,
|
|
output io_dec_exu_decode_exu_i0_ap_land,
|
|
output io_dec_exu_decode_exu_i0_ap_lor,
|
|
output io_dec_exu_decode_exu_i0_ap_lxor,
|
|
output io_dec_exu_decode_exu_i0_ap_sll,
|
|
output io_dec_exu_decode_exu_i0_ap_srl,
|
|
output io_dec_exu_decode_exu_i0_ap_sra,
|
|
output io_dec_exu_decode_exu_i0_ap_beq,
|
|
output io_dec_exu_decode_exu_i0_ap_bne,
|
|
output io_dec_exu_decode_exu_i0_ap_blt,
|
|
output io_dec_exu_decode_exu_i0_ap_bge,
|
|
output io_dec_exu_decode_exu_i0_ap_add,
|
|
output io_dec_exu_decode_exu_i0_ap_sub,
|
|
output io_dec_exu_decode_exu_i0_ap_slt,
|
|
output io_dec_exu_decode_exu_i0_ap_unsign,
|
|
output io_dec_exu_decode_exu_i0_ap_jal,
|
|
output io_dec_exu_decode_exu_i0_ap_predict_t,
|
|
output io_dec_exu_decode_exu_i0_ap_predict_nt,
|
|
output io_dec_exu_decode_exu_i0_ap_csr_write,
|
|
output io_dec_exu_decode_exu_i0_ap_csr_imm,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_valid,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4,
|
|
output [1:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist,
|
|
output [11:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way,
|
|
output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret,
|
|
output [30:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett,
|
|
output [7:0] io_dec_exu_decode_exu_i0_predict_fghr_d,
|
|
output [7:0] io_dec_exu_decode_exu_i0_predict_index_d,
|
|
output [4:0] io_dec_exu_decode_exu_i0_predict_btag_d,
|
|
output io_dec_exu_decode_exu_dec_i0_rs1_en_d,
|
|
output io_dec_exu_decode_exu_dec_i0_branch_d,
|
|
output io_dec_exu_decode_exu_dec_i0_rs2_en_d,
|
|
output [31:0] io_dec_exu_decode_exu_dec_i0_immed_d,
|
|
output [31:0] io_dec_exu_decode_exu_dec_i0_result_r,
|
|
output io_dec_exu_decode_exu_dec_qual_lsu_d,
|
|
output io_dec_exu_decode_exu_dec_i0_select_pc_d,
|
|
output [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d,
|
|
output [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d,
|
|
output io_dec_exu_decode_exu_mul_p_valid,
|
|
output io_dec_exu_decode_exu_mul_p_bits_rs1_sign,
|
|
output io_dec_exu_decode_exu_mul_p_bits_rs2_sign,
|
|
output io_dec_exu_decode_exu_mul_p_bits_low,
|
|
output [30:0] io_dec_exu_decode_exu_pred_correct_npc_x,
|
|
output io_dec_exu_decode_exu_dec_extint_stall,
|
|
input [31:0] io_dec_exu_decode_exu_exu_i0_result_x,
|
|
input [31:0] io_dec_exu_decode_exu_exu_csr_rs1_x,
|
|
output [29:0] io_dec_exu_tlu_exu_dec_tlu_meihap,
|
|
output io_dec_exu_tlu_exu_dec_tlu_flush_lower_r,
|
|
output [30:0] io_dec_exu_tlu_exu_dec_tlu_flush_path_r,
|
|
input [1:0] io_dec_exu_tlu_exu_exu_i0_br_hist_r,
|
|
input io_dec_exu_tlu_exu_exu_i0_br_error_r,
|
|
input io_dec_exu_tlu_exu_exu_i0_br_start_error_r,
|
|
input io_dec_exu_tlu_exu_exu_i0_br_valid_r,
|
|
input io_dec_exu_tlu_exu_exu_i0_br_mp_r,
|
|
input io_dec_exu_tlu_exu_exu_i0_br_middle_r,
|
|
input io_dec_exu_tlu_exu_exu_pmu_i0_br_misp,
|
|
input io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken,
|
|
input io_dec_exu_tlu_exu_exu_pmu_i0_pc4,
|
|
input [30:0] io_dec_exu_tlu_exu_exu_npc_r,
|
|
output [30:0] io_dec_exu_ib_exu_dec_i0_pc_d,
|
|
output io_dec_exu_ib_exu_dec_debug_wdata_rs1_d,
|
|
output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d,
|
|
output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d,
|
|
input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
|
|
input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
|
|
input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
|
|
input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
|
|
output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable,
|
|
output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable,
|
|
output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
|
|
input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any,
|
|
input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any,
|
|
input [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any,
|
|
input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m,
|
|
input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m,
|
|
input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r,
|
|
input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r,
|
|
input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid,
|
|
input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error,
|
|
input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag,
|
|
input io_lsu_tlu_lsu_pmu_load_external_m,
|
|
input io_lsu_tlu_lsu_pmu_store_external_m,
|
|
input io_dec_dbg_dbg_ib_dbg_cmd_valid,
|
|
input io_dec_dbg_dbg_ib_dbg_cmd_write,
|
|
input [1:0] io_dec_dbg_dbg_ib_dbg_cmd_type,
|
|
input [31:0] io_dec_dbg_dbg_ib_dbg_cmd_addr,
|
|
input [31:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata,
|
|
input io_dec_dma_dctl_dma_dma_dccm_stall_any,
|
|
input io_dec_dma_tlu_dma_dma_pmu_dccm_read,
|
|
input io_dec_dma_tlu_dma_dma_pmu_dccm_write,
|
|
input io_dec_dma_tlu_dma_dma_pmu_any_read,
|
|
input io_dec_dma_tlu_dma_dma_pmu_any_write,
|
|
output [2:0] io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty,
|
|
input io_dec_dma_tlu_dma_dma_dccm_stall_any,
|
|
input io_dec_dma_tlu_dma_dma_iccm_stall_any,
|
|
input [7:0] io_dec_pic_pic_claimid,
|
|
input [3:0] io_dec_pic_pic_pl,
|
|
input io_dec_pic_mhwakeup,
|
|
output [3:0] io_dec_pic_dec_tlu_meicurpl,
|
|
output [3:0] io_dec_pic_dec_tlu_meipt,
|
|
input io_dec_pic_mexintpend
|
|
);
|
|
wire instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 130:24]
|
|
wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_ifu_i0_icaf_second; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 130:24]
|
|
wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 130:24]
|
|
wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 130:24]
|
|
wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 130:24]
|
|
wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 130:24]
|
|
wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 130:24]
|
|
wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 130:24]
|
|
wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 130:24]
|
|
wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 130:24]
|
|
wire instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 130:24]
|
|
wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 130:24]
|
|
wire instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 130:24]
|
|
wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 130:24]
|
|
wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_debug_valid_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_ib0_valid_d; // @[dec.scala 130:24]
|
|
wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 130:24]
|
|
wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_pc4_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_brp_valid; // @[dec.scala 130:24]
|
|
wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 130:24]
|
|
wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 130:24]
|
|
wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 130:24]
|
|
wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 130:24]
|
|
wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 130:24]
|
|
wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_icaf_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_i0_dbecc_d; // @[dec.scala 130:24]
|
|
wire instbuff_io_dec_debug_fence_d; // @[dec.scala 130:24]
|
|
wire decode_clock; // @[dec.scala 131:22]
|
|
wire decode_reset; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_clz; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_min; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_max; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_pack; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_packu; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_packh; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_rol; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_ror; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_grev; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_land; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_lor; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sll; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_srl; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sra; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_beq; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_bne; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_blt; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_bge; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_add; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_sub; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_slt; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_jal; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 131:22]
|
|
wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 131:22]
|
|
wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_mul_p_valid; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 131:22]
|
|
wire decode_io_decode_exu_dec_extint_stall; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 131:22]
|
|
wire decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 131:22]
|
|
wire decode_io_dec_div_div_p_valid; // @[dec.scala 131:22]
|
|
wire decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 131:22]
|
|
wire decode_io_dec_div_div_p_bits_rem; // @[dec.scala 131:22]
|
|
wire decode_io_dec_div_dec_div_cancel; // @[dec.scala 131:22]
|
|
wire decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 131:22]
|
|
wire decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 131:22]
|
|
wire decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 131:22]
|
|
wire decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 131:22]
|
|
wire decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 131:22]
|
|
wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_trace_disable; // @[dec.scala 131:22]
|
|
wire decode_io_dec_debug_valid_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_flush_extint; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_force_halt; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_i0_inst_wb; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_dec_i0_pc_wb; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_wr_pause_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_pipelining_disable; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_pmu_misaligned_m; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_debug_stall; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_debug_fence_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_icaf_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_icaf_second_d; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_dbecc_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_brp_valid; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_brp_bits_way; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_brp_bits_ret; // @[dec.scala 131:22]
|
|
wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 131:22]
|
|
wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_idle_any; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_load_stall_any; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_store_stall_any; // @[dec.scala 131:22]
|
|
wire decode_io_exu_div_wren; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_flush_lower_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_flush_pause_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_presync_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_postsync_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_pc4_d; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_csr_legal_d; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_lsu_result_m; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 131:22]
|
|
wire decode_io_exu_flush_final; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_ib0_valid_d; // @[dec.scala 131:22]
|
|
wire decode_io_active_clk; // @[dec.scala 131:22]
|
|
wire decode_io_free_l2clk; // @[dec.scala 131:22]
|
|
wire decode_io_clk_override; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_wen_r; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_valid; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_fast_int; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_by; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_half; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_word; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_load; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_store; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_unsign; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 131:22]
|
|
wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 131:22]
|
|
wire decode_io_dec_lsu_valid_raw_d; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_csr_wen_unq_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_csr_any_unq_d; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 131:22]
|
|
wire decode_io_dec_csr_wen_r; // @[dec.scala 131:22]
|
|
wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_csr_stall_int_ff; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_i0_valid_r; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_legal; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 131:22]
|
|
wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 131:22]
|
|
wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 131:22]
|
|
wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 131:22]
|
|
wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 131:22]
|
|
wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 131:22]
|
|
wire decode_io_dec_pmu_instr_decoded; // @[dec.scala 131:22]
|
|
wire decode_io_dec_pmu_decode_stall; // @[dec.scala 131:22]
|
|
wire decode_io_dec_pmu_presync_stall; // @[dec.scala 131:22]
|
|
wire decode_io_dec_pmu_postsync_stall; // @[dec.scala 131:22]
|
|
wire decode_io_dec_nonblock_load_wen; // @[dec.scala 131:22]
|
|
wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 131:22]
|
|
wire decode_io_dec_pause_state; // @[dec.scala 131:22]
|
|
wire decode_io_dec_div_active; // @[dec.scala 131:22]
|
|
wire decode_io_dec_i0_decode_d; // @[dec.scala 131:22]
|
|
wire gpr_clock; // @[dec.scala 132:19]
|
|
wire gpr_reset; // @[dec.scala 132:19]
|
|
wire [4:0] gpr_io_raddr0; // @[dec.scala 132:19]
|
|
wire [4:0] gpr_io_raddr1; // @[dec.scala 132:19]
|
|
wire gpr_io_wen0; // @[dec.scala 132:19]
|
|
wire [4:0] gpr_io_waddr0; // @[dec.scala 132:19]
|
|
wire [31:0] gpr_io_wd0; // @[dec.scala 132:19]
|
|
wire gpr_io_wen1; // @[dec.scala 132:19]
|
|
wire [4:0] gpr_io_waddr1; // @[dec.scala 132:19]
|
|
wire [31:0] gpr_io_wd1; // @[dec.scala 132:19]
|
|
wire gpr_io_wen2; // @[dec.scala 132:19]
|
|
wire [4:0] gpr_io_waddr2; // @[dec.scala 132:19]
|
|
wire [31:0] gpr_io_wd2; // @[dec.scala 132:19]
|
|
wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 132:19]
|
|
wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 132:19]
|
|
wire tlu_clock; // @[dec.scala 133:19]
|
|
wire tlu_reset; // @[dec.scala 133:19]
|
|
wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 133:19]
|
|
wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_pmu_any_read; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_pmu_any_write; // @[dec.scala 133:19]
|
|
wire [2:0] tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_dccm_stall_any; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_dma_dma_iccm_stall_any; // @[dec.scala 133:19]
|
|
wire tlu_io_free_clk; // @[dec.scala 133:19]
|
|
wire tlu_io_free_l2clk; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_rst_vec; // @[dec.scala 133:19]
|
|
wire tlu_io_nmi_int; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_nmi_vec; // @[dec.scala 133:19]
|
|
wire tlu_io_i_cpu_halt_req; // @[dec.scala 133:19]
|
|
wire tlu_io_i_cpu_run_req; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_fastint_stall_any; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_idle_any; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pmu_instr_decoded; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pmu_decode_stall; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pmu_presync_stall; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pmu_postsync_stall; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_store_stall_any; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 133:19]
|
|
wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 133:19]
|
|
wire tlu_io_iccm_dma_sb_error; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pause_state; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_csr_wen_unq_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_csr_any_unq_d; // @[dec.scala 133:19]
|
|
wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_csr_wen_r; // @[dec.scala 133:19]
|
|
wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_csr_stall_int_ff; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 133:19]
|
|
wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 133:19]
|
|
wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_i0_decode_d; // @[dec.scala 133:19]
|
|
wire tlu_io_exu_i0_br_way_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_dbg_cmd_done; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_dbg_cmd_fail; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_dbg_halted; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_debug_mode; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_resume_ack; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_debug_stall; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_flush_extint; // @[dec.scala 133:19]
|
|
wire tlu_io_dbg_halt_req; // @[dec.scala 133:19]
|
|
wire tlu_io_dbg_resume_req; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_div_active; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_select; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_store; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_load; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_0_m; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_select; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_store; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_load; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_1_m; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_select; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_store; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_load; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_2_m; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_select; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_store; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_load; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 133:19]
|
|
wire tlu_io_trigger_pkt_any_3_m; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 133:19]
|
|
wire tlu_io_timer_int; // @[dec.scala 133:19]
|
|
wire tlu_io_soft_int; // @[dec.scala 133:19]
|
|
wire tlu_io_o_cpu_halt_status; // @[dec.scala 133:19]
|
|
wire tlu_io_o_cpu_halt_ack; // @[dec.scala 133:19]
|
|
wire tlu_io_o_cpu_run_ack; // @[dec.scala 133:19]
|
|
wire tlu_io_o_debug_mode_status; // @[dec.scala 133:19]
|
|
wire [27:0] tlu_io_core_id; // @[dec.scala 133:19]
|
|
wire tlu_io_mpc_debug_halt_req; // @[dec.scala 133:19]
|
|
wire tlu_io_mpc_debug_run_req; // @[dec.scala 133:19]
|
|
wire tlu_io_mpc_reset_run_req; // @[dec.scala 133:19]
|
|
wire tlu_io_mpc_debug_halt_ack; // @[dec.scala 133:19]
|
|
wire tlu_io_mpc_debug_run_ack; // @[dec.scala 133:19]
|
|
wire tlu_io_debug_brkpt_status; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_csr_legal_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_presync_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_postsync_d; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_perfcnt0; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_perfcnt1; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_perfcnt2; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_perfcnt3; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 133:19]
|
|
wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_trace_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 133:19]
|
|
wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 133:19]
|
|
wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 133:19]
|
|
wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 133:19]
|
|
wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 133:19]
|
|
wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 133:19]
|
|
wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 133:19]
|
|
wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 133:19]
|
|
wire tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 133:19]
|
|
wire [7:0] tlu_io_dec_pic_pic_claimid; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_dec_pic_pic_pl; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pic_mhwakeup; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 133:19]
|
|
wire [3:0] tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 133:19]
|
|
wire tlu_io_dec_pic_mexintpend; // @[dec.scala 133:19]
|
|
wire dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 134:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 134:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 134:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 134:27]
|
|
wire dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 134:27]
|
|
wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 134:27]
|
|
wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 134:27]
|
|
wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 134:27]
|
|
wire _T_1 = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 314:71]
|
|
dec_ib_ctl instbuff ( // @[dec.scala 130:24]
|
|
.io_ifu_ib_ifu_i0_icaf(instbuff_io_ifu_ib_ifu_i0_icaf),
|
|
.io_ifu_ib_ifu_i0_icaf_type(instbuff_io_ifu_ib_ifu_i0_icaf_type),
|
|
.io_ifu_ib_ifu_i0_icaf_second(instbuff_io_ifu_ib_ifu_i0_icaf_second),
|
|
.io_ifu_ib_ifu_i0_dbecc(instbuff_io_ifu_ib_ifu_i0_dbecc),
|
|
.io_ifu_ib_ifu_i0_bp_index(instbuff_io_ifu_ib_ifu_i0_bp_index),
|
|
.io_ifu_ib_ifu_i0_bp_fghr(instbuff_io_ifu_ib_ifu_i0_bp_fghr),
|
|
.io_ifu_ib_ifu_i0_bp_btag(instbuff_io_ifu_ib_ifu_i0_bp_btag),
|
|
.io_ifu_ib_ifu_i0_valid(instbuff_io_ifu_ib_ifu_i0_valid),
|
|
.io_ifu_ib_ifu_i0_instr(instbuff_io_ifu_ib_ifu_i0_instr),
|
|
.io_ifu_ib_ifu_i0_pc(instbuff_io_ifu_ib_ifu_i0_pc),
|
|
.io_ifu_ib_ifu_i0_pc4(instbuff_io_ifu_ib_ifu_i0_pc4),
|
|
.io_ifu_ib_i0_brp_valid(instbuff_io_ifu_ib_i0_brp_valid),
|
|
.io_ifu_ib_i0_brp_bits_toffset(instbuff_io_ifu_ib_i0_brp_bits_toffset),
|
|
.io_ifu_ib_i0_brp_bits_hist(instbuff_io_ifu_ib_i0_brp_bits_hist),
|
|
.io_ifu_ib_i0_brp_bits_br_error(instbuff_io_ifu_ib_i0_brp_bits_br_error),
|
|
.io_ifu_ib_i0_brp_bits_br_start_error(instbuff_io_ifu_ib_i0_brp_bits_br_start_error),
|
|
.io_ifu_ib_i0_brp_bits_prett(instbuff_io_ifu_ib_i0_brp_bits_prett),
|
|
.io_ifu_ib_i0_brp_bits_way(instbuff_io_ifu_ib_i0_brp_bits_way),
|
|
.io_ifu_ib_i0_brp_bits_ret(instbuff_io_ifu_ib_i0_brp_bits_ret),
|
|
.io_ib_exu_dec_i0_pc_d(instbuff_io_ib_exu_dec_i0_pc_d),
|
|
.io_ib_exu_dec_debug_wdata_rs1_d(instbuff_io_ib_exu_dec_debug_wdata_rs1_d),
|
|
.io_dbg_ib_dbg_cmd_valid(instbuff_io_dbg_ib_dbg_cmd_valid),
|
|
.io_dbg_ib_dbg_cmd_write(instbuff_io_dbg_ib_dbg_cmd_write),
|
|
.io_dbg_ib_dbg_cmd_type(instbuff_io_dbg_ib_dbg_cmd_type),
|
|
.io_dbg_ib_dbg_cmd_addr(instbuff_io_dbg_ib_dbg_cmd_addr),
|
|
.io_dec_debug_valid_d(instbuff_io_dec_debug_valid_d),
|
|
.io_dec_ib0_valid_d(instbuff_io_dec_ib0_valid_d),
|
|
.io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d),
|
|
.io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d),
|
|
.io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d),
|
|
.io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid),
|
|
.io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset),
|
|
.io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist),
|
|
.io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error),
|
|
.io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error),
|
|
.io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett),
|
|
.io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way),
|
|
.io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret),
|
|
.io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index),
|
|
.io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr),
|
|
.io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag),
|
|
.io_dec_i0_icaf_d(instbuff_io_dec_i0_icaf_d),
|
|
.io_dec_i0_icaf_second_d(instbuff_io_dec_i0_icaf_second_d),
|
|
.io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d),
|
|
.io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d)
|
|
);
|
|
dec_decode_ctl decode ( // @[dec.scala 131:22]
|
|
.clock(decode_clock),
|
|
.reset(decode_reset),
|
|
.io_decode_exu_dec_data_en(decode_io_decode_exu_dec_data_en),
|
|
.io_decode_exu_dec_ctl_en(decode_io_decode_exu_dec_ctl_en),
|
|
.io_decode_exu_i0_ap_clz(decode_io_decode_exu_i0_ap_clz),
|
|
.io_decode_exu_i0_ap_ctz(decode_io_decode_exu_i0_ap_ctz),
|
|
.io_decode_exu_i0_ap_pcnt(decode_io_decode_exu_i0_ap_pcnt),
|
|
.io_decode_exu_i0_ap_sext_b(decode_io_decode_exu_i0_ap_sext_b),
|
|
.io_decode_exu_i0_ap_sext_h(decode_io_decode_exu_i0_ap_sext_h),
|
|
.io_decode_exu_i0_ap_min(decode_io_decode_exu_i0_ap_min),
|
|
.io_decode_exu_i0_ap_max(decode_io_decode_exu_i0_ap_max),
|
|
.io_decode_exu_i0_ap_pack(decode_io_decode_exu_i0_ap_pack),
|
|
.io_decode_exu_i0_ap_packu(decode_io_decode_exu_i0_ap_packu),
|
|
.io_decode_exu_i0_ap_packh(decode_io_decode_exu_i0_ap_packh),
|
|
.io_decode_exu_i0_ap_rol(decode_io_decode_exu_i0_ap_rol),
|
|
.io_decode_exu_i0_ap_ror(decode_io_decode_exu_i0_ap_ror),
|
|
.io_decode_exu_i0_ap_grev(decode_io_decode_exu_i0_ap_grev),
|
|
.io_decode_exu_i0_ap_gorc(decode_io_decode_exu_i0_ap_gorc),
|
|
.io_decode_exu_i0_ap_zbb(decode_io_decode_exu_i0_ap_zbb),
|
|
.io_decode_exu_i0_ap_sbset(decode_io_decode_exu_i0_ap_sbset),
|
|
.io_decode_exu_i0_ap_sbclr(decode_io_decode_exu_i0_ap_sbclr),
|
|
.io_decode_exu_i0_ap_sbinv(decode_io_decode_exu_i0_ap_sbinv),
|
|
.io_decode_exu_i0_ap_sbext(decode_io_decode_exu_i0_ap_sbext),
|
|
.io_decode_exu_i0_ap_land(decode_io_decode_exu_i0_ap_land),
|
|
.io_decode_exu_i0_ap_lor(decode_io_decode_exu_i0_ap_lor),
|
|
.io_decode_exu_i0_ap_lxor(decode_io_decode_exu_i0_ap_lxor),
|
|
.io_decode_exu_i0_ap_sll(decode_io_decode_exu_i0_ap_sll),
|
|
.io_decode_exu_i0_ap_srl(decode_io_decode_exu_i0_ap_srl),
|
|
.io_decode_exu_i0_ap_sra(decode_io_decode_exu_i0_ap_sra),
|
|
.io_decode_exu_i0_ap_beq(decode_io_decode_exu_i0_ap_beq),
|
|
.io_decode_exu_i0_ap_bne(decode_io_decode_exu_i0_ap_bne),
|
|
.io_decode_exu_i0_ap_blt(decode_io_decode_exu_i0_ap_blt),
|
|
.io_decode_exu_i0_ap_bge(decode_io_decode_exu_i0_ap_bge),
|
|
.io_decode_exu_i0_ap_add(decode_io_decode_exu_i0_ap_add),
|
|
.io_decode_exu_i0_ap_sub(decode_io_decode_exu_i0_ap_sub),
|
|
.io_decode_exu_i0_ap_slt(decode_io_decode_exu_i0_ap_slt),
|
|
.io_decode_exu_i0_ap_unsign(decode_io_decode_exu_i0_ap_unsign),
|
|
.io_decode_exu_i0_ap_jal(decode_io_decode_exu_i0_ap_jal),
|
|
.io_decode_exu_i0_ap_predict_t(decode_io_decode_exu_i0_ap_predict_t),
|
|
.io_decode_exu_i0_ap_predict_nt(decode_io_decode_exu_i0_ap_predict_nt),
|
|
.io_decode_exu_i0_ap_csr_write(decode_io_decode_exu_i0_ap_csr_write),
|
|
.io_decode_exu_i0_ap_csr_imm(decode_io_decode_exu_i0_ap_csr_imm),
|
|
.io_decode_exu_dec_i0_predict_p_d_valid(decode_io_decode_exu_dec_i0_predict_p_d_valid),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_pc4(decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_hist(decode_io_decode_exu_dec_i0_predict_p_d_bits_hist),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_toffset(decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_br_error(decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_br_start_error(decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_pcall(decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_pja(decode_io_decode_exu_dec_i0_predict_p_d_bits_pja),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_way(decode_io_decode_exu_dec_i0_predict_p_d_bits_way),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_pret(decode_io_decode_exu_dec_i0_predict_p_d_bits_pret),
|
|
.io_decode_exu_dec_i0_predict_p_d_bits_prett(decode_io_decode_exu_dec_i0_predict_p_d_bits_prett),
|
|
.io_decode_exu_i0_predict_fghr_d(decode_io_decode_exu_i0_predict_fghr_d),
|
|
.io_decode_exu_i0_predict_index_d(decode_io_decode_exu_i0_predict_index_d),
|
|
.io_decode_exu_i0_predict_btag_d(decode_io_decode_exu_i0_predict_btag_d),
|
|
.io_decode_exu_dec_i0_rs1_en_d(decode_io_decode_exu_dec_i0_rs1_en_d),
|
|
.io_decode_exu_dec_i0_branch_d(decode_io_decode_exu_dec_i0_branch_d),
|
|
.io_decode_exu_dec_i0_rs2_en_d(decode_io_decode_exu_dec_i0_rs2_en_d),
|
|
.io_decode_exu_dec_i0_immed_d(decode_io_decode_exu_dec_i0_immed_d),
|
|
.io_decode_exu_dec_i0_result_r(decode_io_decode_exu_dec_i0_result_r),
|
|
.io_decode_exu_dec_qual_lsu_d(decode_io_decode_exu_dec_qual_lsu_d),
|
|
.io_decode_exu_dec_i0_select_pc_d(decode_io_decode_exu_dec_i0_select_pc_d),
|
|
.io_decode_exu_dec_i0_rs1_bypass_en_d(decode_io_decode_exu_dec_i0_rs1_bypass_en_d),
|
|
.io_decode_exu_dec_i0_rs2_bypass_en_d(decode_io_decode_exu_dec_i0_rs2_bypass_en_d),
|
|
.io_decode_exu_mul_p_valid(decode_io_decode_exu_mul_p_valid),
|
|
.io_decode_exu_mul_p_bits_rs1_sign(decode_io_decode_exu_mul_p_bits_rs1_sign),
|
|
.io_decode_exu_mul_p_bits_rs2_sign(decode_io_decode_exu_mul_p_bits_rs2_sign),
|
|
.io_decode_exu_mul_p_bits_low(decode_io_decode_exu_mul_p_bits_low),
|
|
.io_decode_exu_pred_correct_npc_x(decode_io_decode_exu_pred_correct_npc_x),
|
|
.io_decode_exu_dec_extint_stall(decode_io_decode_exu_dec_extint_stall),
|
|
.io_decode_exu_exu_i0_result_x(decode_io_decode_exu_exu_i0_result_x),
|
|
.io_decode_exu_exu_csr_rs1_x(decode_io_decode_exu_exu_csr_rs1_x),
|
|
.io_dec_alu_dec_i0_alu_decode_d(decode_io_dec_alu_dec_i0_alu_decode_d),
|
|
.io_dec_alu_dec_csr_ren_d(decode_io_dec_alu_dec_csr_ren_d),
|
|
.io_dec_alu_dec_i0_br_immed_d(decode_io_dec_alu_dec_i0_br_immed_d),
|
|
.io_dec_alu_exu_i0_pc_x(decode_io_dec_alu_exu_i0_pc_x),
|
|
.io_dec_div_div_p_valid(decode_io_dec_div_div_p_valid),
|
|
.io_dec_div_div_p_bits_unsign(decode_io_dec_div_div_p_bits_unsign),
|
|
.io_dec_div_div_p_bits_rem(decode_io_dec_div_div_p_bits_rem),
|
|
.io_dec_div_dec_div_cancel(decode_io_dec_div_dec_div_cancel),
|
|
.io_dctl_busbuff_lsu_nonblock_load_valid_m(decode_io_dctl_busbuff_lsu_nonblock_load_valid_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_tag_m(decode_io_dctl_busbuff_lsu_nonblock_load_tag_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_r(decode_io_dctl_busbuff_lsu_nonblock_load_inv_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_valid(decode_io_dctl_busbuff_lsu_nonblock_load_data_valid),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_error(decode_io_dctl_busbuff_lsu_nonblock_load_data_error),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag),
|
|
.io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any),
|
|
.io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst),
|
|
.io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata),
|
|
.io_dec_tlu_trace_disable(decode_io_dec_tlu_trace_disable),
|
|
.io_dec_debug_valid_d(decode_io_dec_debug_valid_d),
|
|
.io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint),
|
|
.io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt),
|
|
.io_dec_i0_inst_wb(decode_io_dec_i0_inst_wb),
|
|
.io_dec_i0_pc_wb(decode_io_dec_i0_pc_wb),
|
|
.io_dec_i0_trigger_match_d(decode_io_dec_i0_trigger_match_d),
|
|
.io_dec_tlu_wr_pause_r(decode_io_dec_tlu_wr_pause_r),
|
|
.io_dec_tlu_pipelining_disable(decode_io_dec_tlu_pipelining_disable),
|
|
.io_lsu_trigger_match_m(decode_io_lsu_trigger_match_m),
|
|
.io_lsu_pmu_misaligned_m(decode_io_lsu_pmu_misaligned_m),
|
|
.io_dec_tlu_debug_stall(decode_io_dec_tlu_debug_stall),
|
|
.io_dec_tlu_flush_leak_one_r(decode_io_dec_tlu_flush_leak_one_r),
|
|
.io_dec_debug_fence_d(decode_io_dec_debug_fence_d),
|
|
.io_dec_i0_icaf_d(decode_io_dec_i0_icaf_d),
|
|
.io_dec_i0_icaf_second_d(decode_io_dec_i0_icaf_second_d),
|
|
.io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d),
|
|
.io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d),
|
|
.io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid),
|
|
.io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset),
|
|
.io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist),
|
|
.io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error),
|
|
.io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error),
|
|
.io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett),
|
|
.io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way),
|
|
.io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret),
|
|
.io_dec_i0_bp_index(decode_io_dec_i0_bp_index),
|
|
.io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr),
|
|
.io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag),
|
|
.io_lsu_idle_any(decode_io_lsu_idle_any),
|
|
.io_lsu_load_stall_any(decode_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(decode_io_lsu_store_stall_any),
|
|
.io_exu_div_wren(decode_io_exu_div_wren),
|
|
.io_dec_tlu_i0_kill_writeb_wb(decode_io_dec_tlu_i0_kill_writeb_wb),
|
|
.io_dec_tlu_flush_lower_wb(decode_io_dec_tlu_flush_lower_wb),
|
|
.io_dec_tlu_i0_kill_writeb_r(decode_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_flush_lower_r(decode_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_flush_pause_r(decode_io_dec_tlu_flush_pause_r),
|
|
.io_dec_tlu_presync_d(decode_io_dec_tlu_presync_d),
|
|
.io_dec_tlu_postsync_d(decode_io_dec_tlu_postsync_d),
|
|
.io_dec_i0_pc4_d(decode_io_dec_i0_pc4_d),
|
|
.io_dec_csr_rddata_d(decode_io_dec_csr_rddata_d),
|
|
.io_dec_csr_legal_d(decode_io_dec_csr_legal_d),
|
|
.io_lsu_result_m(decode_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(decode_io_lsu_result_corr_r),
|
|
.io_exu_flush_final(decode_io_exu_flush_final),
|
|
.io_dec_i0_instr_d(decode_io_dec_i0_instr_d),
|
|
.io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d),
|
|
.io_active_clk(decode_io_active_clk),
|
|
.io_free_l2clk(decode_io_free_l2clk),
|
|
.io_clk_override(decode_io_clk_override),
|
|
.io_dec_i0_rs1_d(decode_io_dec_i0_rs1_d),
|
|
.io_dec_i0_rs2_d(decode_io_dec_i0_rs2_d),
|
|
.io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r),
|
|
.io_dec_i0_wen_r(decode_io_dec_i0_wen_r),
|
|
.io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r),
|
|
.io_lsu_p_valid(decode_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(decode_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(decode_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(decode_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(decode_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(decode_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(decode_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(decode_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(decode_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(decode_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_div_waddr_wb(decode_io_div_waddr_wb),
|
|
.io_dec_lsu_valid_raw_d(decode_io_dec_lsu_valid_raw_d),
|
|
.io_dec_lsu_offset_d(decode_io_dec_lsu_offset_d),
|
|
.io_dec_csr_wen_unq_d(decode_io_dec_csr_wen_unq_d),
|
|
.io_dec_csr_any_unq_d(decode_io_dec_csr_any_unq_d),
|
|
.io_dec_csr_rdaddr_d(decode_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_r(decode_io_dec_csr_wen_r),
|
|
.io_dec_csr_wraddr_r(decode_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(decode_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_stall_int_ff(decode_io_dec_csr_stall_int_ff),
|
|
.io_dec_tlu_i0_valid_r(decode_io_dec_tlu_i0_valid_r),
|
|
.io_dec_tlu_packet_r_legal(decode_io_dec_tlu_packet_r_legal),
|
|
.io_dec_tlu_packet_r_icaf(decode_io_dec_tlu_packet_r_icaf),
|
|
.io_dec_tlu_packet_r_icaf_second(decode_io_dec_tlu_packet_r_icaf_second),
|
|
.io_dec_tlu_packet_r_icaf_type(decode_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_fence_i(decode_io_dec_tlu_packet_r_fence_i),
|
|
.io_dec_tlu_packet_r_i0trigger(decode_io_dec_tlu_packet_r_i0trigger),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(decode_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(decode_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(decode_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(decode_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_dec_tlu_i0_pc_r(decode_io_dec_tlu_i0_pc_r),
|
|
.io_dec_illegal_inst(decode_io_dec_illegal_inst),
|
|
.io_dec_pmu_instr_decoded(decode_io_dec_pmu_instr_decoded),
|
|
.io_dec_pmu_decode_stall(decode_io_dec_pmu_decode_stall),
|
|
.io_dec_pmu_presync_stall(decode_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(decode_io_dec_pmu_postsync_stall),
|
|
.io_dec_nonblock_load_wen(decode_io_dec_nonblock_load_wen),
|
|
.io_dec_nonblock_load_waddr(decode_io_dec_nonblock_load_waddr),
|
|
.io_dec_pause_state(decode_io_dec_pause_state),
|
|
.io_dec_div_active(decode_io_dec_div_active),
|
|
.io_dec_i0_decode_d(decode_io_dec_i0_decode_d)
|
|
);
|
|
dec_gpr_ctl gpr ( // @[dec.scala 132:19]
|
|
.clock(gpr_clock),
|
|
.reset(gpr_reset),
|
|
.io_raddr0(gpr_io_raddr0),
|
|
.io_raddr1(gpr_io_raddr1),
|
|
.io_wen0(gpr_io_wen0),
|
|
.io_waddr0(gpr_io_waddr0),
|
|
.io_wd0(gpr_io_wd0),
|
|
.io_wen1(gpr_io_wen1),
|
|
.io_waddr1(gpr_io_waddr1),
|
|
.io_wd1(gpr_io_wd1),
|
|
.io_wen2(gpr_io_wen2),
|
|
.io_waddr2(gpr_io_waddr2),
|
|
.io_wd2(gpr_io_wd2),
|
|
.io_gpr_exu_gpr_i0_rs1_d(gpr_io_gpr_exu_gpr_i0_rs1_d),
|
|
.io_gpr_exu_gpr_i0_rs2_d(gpr_io_gpr_exu_gpr_i0_rs2_d)
|
|
);
|
|
dec_tlu_ctl tlu ( // @[dec.scala 133:19]
|
|
.clock(tlu_clock),
|
|
.reset(tlu_reset),
|
|
.io_tlu_exu_dec_tlu_meihap(tlu_io_tlu_exu_dec_tlu_meihap),
|
|
.io_tlu_exu_dec_tlu_flush_lower_r(tlu_io_tlu_exu_dec_tlu_flush_lower_r),
|
|
.io_tlu_exu_dec_tlu_flush_path_r(tlu_io_tlu_exu_dec_tlu_flush_path_r),
|
|
.io_tlu_exu_exu_i0_br_hist_r(tlu_io_tlu_exu_exu_i0_br_hist_r),
|
|
.io_tlu_exu_exu_i0_br_error_r(tlu_io_tlu_exu_exu_i0_br_error_r),
|
|
.io_tlu_exu_exu_i0_br_start_error_r(tlu_io_tlu_exu_exu_i0_br_start_error_r),
|
|
.io_tlu_exu_exu_i0_br_valid_r(tlu_io_tlu_exu_exu_i0_br_valid_r),
|
|
.io_tlu_exu_exu_i0_br_mp_r(tlu_io_tlu_exu_exu_i0_br_mp_r),
|
|
.io_tlu_exu_exu_i0_br_middle_r(tlu_io_tlu_exu_exu_i0_br_middle_r),
|
|
.io_tlu_exu_exu_pmu_i0_br_misp(tlu_io_tlu_exu_exu_pmu_i0_br_misp),
|
|
.io_tlu_exu_exu_pmu_i0_br_ataken(tlu_io_tlu_exu_exu_pmu_i0_br_ataken),
|
|
.io_tlu_exu_exu_pmu_i0_pc4(tlu_io_tlu_exu_exu_pmu_i0_pc4),
|
|
.io_tlu_exu_exu_npc_r(tlu_io_tlu_exu_exu_npc_r),
|
|
.io_tlu_dma_dma_pmu_dccm_read(tlu_io_tlu_dma_dma_pmu_dccm_read),
|
|
.io_tlu_dma_dma_pmu_dccm_write(tlu_io_tlu_dma_dma_pmu_dccm_write),
|
|
.io_tlu_dma_dma_pmu_any_read(tlu_io_tlu_dma_dma_pmu_any_read),
|
|
.io_tlu_dma_dma_pmu_any_write(tlu_io_tlu_dma_dma_pmu_any_write),
|
|
.io_tlu_dma_dec_tlu_dma_qos_prty(tlu_io_tlu_dma_dec_tlu_dma_qos_prty),
|
|
.io_tlu_dma_dma_dccm_stall_any(tlu_io_tlu_dma_dma_dccm_stall_any),
|
|
.io_tlu_dma_dma_iccm_stall_any(tlu_io_tlu_dma_dma_iccm_stall_any),
|
|
.io_free_clk(tlu_io_free_clk),
|
|
.io_free_l2clk(tlu_io_free_l2clk),
|
|
.io_rst_vec(tlu_io_rst_vec),
|
|
.io_nmi_int(tlu_io_nmi_int),
|
|
.io_nmi_vec(tlu_io_nmi_vec),
|
|
.io_i_cpu_halt_req(tlu_io_i_cpu_halt_req),
|
|
.io_i_cpu_run_req(tlu_io_i_cpu_run_req),
|
|
.io_lsu_fastint_stall_any(tlu_io_lsu_fastint_stall_any),
|
|
.io_lsu_idle_any(tlu_io_lsu_idle_any),
|
|
.io_dec_pmu_instr_decoded(tlu_io_dec_pmu_instr_decoded),
|
|
.io_dec_pmu_decode_stall(tlu_io_dec_pmu_decode_stall),
|
|
.io_dec_pmu_presync_stall(tlu_io_dec_pmu_presync_stall),
|
|
.io_dec_pmu_postsync_stall(tlu_io_dec_pmu_postsync_stall),
|
|
.io_lsu_store_stall_any(tlu_io_lsu_store_stall_any),
|
|
.io_lsu_fir_addr(tlu_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(tlu_io_lsu_fir_error),
|
|
.io_iccm_dma_sb_error(tlu_io_iccm_dma_sb_error),
|
|
.io_lsu_error_pkt_r_valid(tlu_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(tlu_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(tlu_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(tlu_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(tlu_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(tlu_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_single_ecc_error_incr(tlu_io_lsu_single_ecc_error_incr),
|
|
.io_dec_pause_state(tlu_io_dec_pause_state),
|
|
.io_dec_csr_wen_unq_d(tlu_io_dec_csr_wen_unq_d),
|
|
.io_dec_csr_any_unq_d(tlu_io_dec_csr_any_unq_d),
|
|
.io_dec_csr_rdaddr_d(tlu_io_dec_csr_rdaddr_d),
|
|
.io_dec_csr_wen_r(tlu_io_dec_csr_wen_r),
|
|
.io_dec_csr_wraddr_r(tlu_io_dec_csr_wraddr_r),
|
|
.io_dec_csr_wrdata_r(tlu_io_dec_csr_wrdata_r),
|
|
.io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff),
|
|
.io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r),
|
|
.io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r),
|
|
.io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal),
|
|
.io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf),
|
|
.io_dec_tlu_packet_r_icaf_second(tlu_io_dec_tlu_packet_r_icaf_second),
|
|
.io_dec_tlu_packet_r_icaf_type(tlu_io_dec_tlu_packet_r_icaf_type),
|
|
.io_dec_tlu_packet_r_fence_i(tlu_io_dec_tlu_packet_r_fence_i),
|
|
.io_dec_tlu_packet_r_i0trigger(tlu_io_dec_tlu_packet_r_i0trigger),
|
|
.io_dec_tlu_packet_r_pmu_i0_itype(tlu_io_dec_tlu_packet_r_pmu_i0_itype),
|
|
.io_dec_tlu_packet_r_pmu_i0_br_unpred(tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred),
|
|
.io_dec_tlu_packet_r_pmu_divide(tlu_io_dec_tlu_packet_r_pmu_divide),
|
|
.io_dec_tlu_packet_r_pmu_lsu_misaligned(tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned),
|
|
.io_dec_illegal_inst(tlu_io_dec_illegal_inst),
|
|
.io_dec_i0_decode_d(tlu_io_dec_i0_decode_d),
|
|
.io_exu_i0_br_way_r(tlu_io_exu_i0_br_way_r),
|
|
.io_dec_dbg_cmd_done(tlu_io_dec_dbg_cmd_done),
|
|
.io_dec_dbg_cmd_fail(tlu_io_dec_dbg_cmd_fail),
|
|
.io_dec_tlu_dbg_halted(tlu_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_debug_mode(tlu_io_dec_tlu_debug_mode),
|
|
.io_dec_tlu_resume_ack(tlu_io_dec_tlu_resume_ack),
|
|
.io_dec_tlu_debug_stall(tlu_io_dec_tlu_debug_stall),
|
|
.io_dec_tlu_mpc_halted_only(tlu_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_tlu_flush_extint(tlu_io_dec_tlu_flush_extint),
|
|
.io_dbg_halt_req(tlu_io_dbg_halt_req),
|
|
.io_dbg_resume_req(tlu_io_dbg_resume_req),
|
|
.io_dec_div_active(tlu_io_dec_div_active),
|
|
.io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute),
|
|
.io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute),
|
|
.io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute),
|
|
.io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute),
|
|
.io_trigger_pkt_any_3_m(tlu_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(tlu_io_trigger_pkt_any_3_tdata2),
|
|
.io_timer_int(tlu_io_timer_int),
|
|
.io_soft_int(tlu_io_soft_int),
|
|
.io_o_cpu_halt_status(tlu_io_o_cpu_halt_status),
|
|
.io_o_cpu_halt_ack(tlu_io_o_cpu_halt_ack),
|
|
.io_o_cpu_run_ack(tlu_io_o_cpu_run_ack),
|
|
.io_o_debug_mode_status(tlu_io_o_debug_mode_status),
|
|
.io_core_id(tlu_io_core_id),
|
|
.io_mpc_debug_halt_req(tlu_io_mpc_debug_halt_req),
|
|
.io_mpc_debug_run_req(tlu_io_mpc_debug_run_req),
|
|
.io_mpc_reset_run_req(tlu_io_mpc_reset_run_req),
|
|
.io_mpc_debug_halt_ack(tlu_io_mpc_debug_halt_ack),
|
|
.io_mpc_debug_run_ack(tlu_io_mpc_debug_run_ack),
|
|
.io_debug_brkpt_status(tlu_io_debug_brkpt_status),
|
|
.io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d),
|
|
.io_dec_csr_legal_d(tlu_io_dec_csr_legal_d),
|
|
.io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb),
|
|
.io_dec_tlu_i0_kill_writeb_r(tlu_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_wr_pause_r(tlu_io_dec_tlu_wr_pause_r),
|
|
.io_dec_tlu_flush_pause_r(tlu_io_dec_tlu_flush_pause_r),
|
|
.io_dec_tlu_presync_d(tlu_io_dec_tlu_presync_d),
|
|
.io_dec_tlu_postsync_d(tlu_io_dec_tlu_postsync_d),
|
|
.io_dec_tlu_perfcnt0(tlu_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(tlu_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(tlu_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(tlu_io_dec_tlu_perfcnt3),
|
|
.io_dec_tlu_i0_exc_valid_wb1(tlu_io_dec_tlu_i0_exc_valid_wb1),
|
|
.io_dec_tlu_i0_valid_wb1(tlu_io_dec_tlu_i0_valid_wb1),
|
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.io_dec_tlu_int_valid_wb1(tlu_io_dec_tlu_int_valid_wb1),
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.io_dec_tlu_exc_cause_wb1(tlu_io_dec_tlu_exc_cause_wb1),
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|
.io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1),
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|
.io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable),
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|
.io_dec_tlu_trace_disable(tlu_io_dec_tlu_trace_disable),
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|
.io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override),
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|
.io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override),
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|
.io_dec_tlu_picio_clk_override(tlu_io_dec_tlu_picio_clk_override),
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|
.io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override),
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|
.io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override),
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|
.io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
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|
.io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned),
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.io_tlu_bp_dec_tlu_br0_r_pkt_valid(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid),
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|
.io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist),
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|
.io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error),
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.io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error),
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|
.io_tlu_bp_dec_tlu_br0_r_pkt_bits_way(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way),
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.io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle),
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|
.io_tlu_bp_dec_tlu_flush_leak_one_wb(tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb),
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|
.io_tlu_bp_dec_tlu_bpred_disable(tlu_io_tlu_bp_dec_tlu_bpred_disable),
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.io_tlu_ifc_dec_tlu_flush_noredir_wb(tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb),
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.io_tlu_ifc_dec_tlu_mrac_ff(tlu_io_tlu_ifc_dec_tlu_mrac_ff),
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.io_tlu_ifc_ifu_pmu_fetch_stall(tlu_io_tlu_ifc_ifu_pmu_fetch_stall),
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.io_tlu_mem_dec_tlu_flush_err_wb(tlu_io_tlu_mem_dec_tlu_flush_err_wb),
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.io_tlu_mem_dec_tlu_i0_commit_cmt(tlu_io_tlu_mem_dec_tlu_i0_commit_cmt),
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.io_tlu_mem_dec_tlu_force_halt(tlu_io_tlu_mem_dec_tlu_force_halt),
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.io_tlu_mem_dec_tlu_fence_i_wb(tlu_io_tlu_mem_dec_tlu_fence_i_wb),
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.io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata),
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.io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics),
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|
.io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid),
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|
.io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid),
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.io_tlu_mem_dec_tlu_core_ecc_disable(tlu_io_tlu_mem_dec_tlu_core_ecc_disable),
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.io_tlu_mem_ifu_pmu_ic_miss(tlu_io_tlu_mem_ifu_pmu_ic_miss),
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.io_tlu_mem_ifu_pmu_ic_hit(tlu_io_tlu_mem_ifu_pmu_ic_hit),
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.io_tlu_mem_ifu_pmu_bus_error(tlu_io_tlu_mem_ifu_pmu_bus_error),
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.io_tlu_mem_ifu_pmu_bus_busy(tlu_io_tlu_mem_ifu_pmu_bus_busy),
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.io_tlu_mem_ifu_pmu_bus_trxn(tlu_io_tlu_mem_ifu_pmu_bus_trxn),
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.io_tlu_mem_ifu_ic_error_start(tlu_io_tlu_mem_ifu_ic_error_start),
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.io_tlu_mem_ifu_iccm_rd_ecc_single_err(tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err),
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.io_tlu_mem_ifu_ic_debug_rd_data(tlu_io_tlu_mem_ifu_ic_debug_rd_data),
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.io_tlu_mem_ifu_ic_debug_rd_data_valid(tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid),
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.io_tlu_mem_ifu_miss_state_idle(tlu_io_tlu_mem_ifu_miss_state_idle),
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.io_tlu_busbuff_lsu_pmu_bus_trxn(tlu_io_tlu_busbuff_lsu_pmu_bus_trxn),
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.io_tlu_busbuff_lsu_pmu_bus_misaligned(tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned),
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.io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error),
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.io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy),
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.io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
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.io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
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|
.io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
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|
.io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any),
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|
.io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any),
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|
.io_tlu_busbuff_lsu_imprecise_error_addr_any(tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any),
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.io_lsu_tlu_lsu_pmu_load_external_m(tlu_io_lsu_tlu_lsu_pmu_load_external_m),
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.io_lsu_tlu_lsu_pmu_store_external_m(tlu_io_lsu_tlu_lsu_pmu_store_external_m),
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.io_dec_pic_pic_claimid(tlu_io_dec_pic_pic_claimid),
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.io_dec_pic_pic_pl(tlu_io_dec_pic_pic_pl),
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.io_dec_pic_mhwakeup(tlu_io_dec_pic_mhwakeup),
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.io_dec_pic_dec_tlu_meicurpl(tlu_io_dec_pic_dec_tlu_meicurpl),
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.io_dec_pic_dec_tlu_meipt(tlu_io_dec_pic_dec_tlu_meipt),
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.io_dec_pic_mexintpend(tlu_io_dec_pic_mexintpend)
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);
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dec_trigger dec_trigger ( // @[dec.scala 134:27]
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.io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select),
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.io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt),
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.io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute),
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.io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m),
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.io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2),
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.io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select),
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.io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt),
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.io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute),
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.io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m),
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.io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2),
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.io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select),
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.io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt),
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.io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute),
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.io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m),
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|
.io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2),
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.io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select),
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|
.io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt),
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.io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute),
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.io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m),
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.io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2),
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.io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d),
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.io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d)
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);
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assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 281:29]
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assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 282:29]
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assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 283:29]
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assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 284:29]
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assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 285:29]
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assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 286:29]
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assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 287:29]
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assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 276:28]
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assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 278:28]
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assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 279:51]
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assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 322:21]
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assign io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 307:36]
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assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 274:28]
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assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 275:28]
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assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 280:29]
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assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 280:29]
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|
assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 280:29]
|
|
assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 280:29]
|
|
assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 280:29]
|
|
assign io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 280:29]
|
|
assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 280:29]
|
|
assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 201:48]
|
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assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 201:48]
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assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 201:48]
|
|
assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 201:48]
|
|
assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 203:48]
|
|
assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 288:34]
|
|
assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 289:29]
|
|
assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 290:29]
|
|
assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 291:29]
|
|
assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 292:29]
|
|
assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 202:48]
|
|
assign io_trace_rv_trace_pkt_rv_i_valid_ip = _T_1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 314:39]
|
|
assign io_trace_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb; // @[dec.scala 312:38]
|
|
assign io_trace_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb,1'h0}; // @[dec.scala 313:41]
|
|
assign io_trace_rv_trace_pkt_rv_i_exception_ip = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 315:43]
|
|
assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 316:40]
|
|
assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 317:43]
|
|
assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 318:38]
|
|
assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 300:36]
|
|
assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 305:36]
|
|
assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 303:36]
|
|
assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 304:36]
|
|
assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[dec.scala 148:22]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 222:18]
|
|
assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 223:18]
|
|
assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 223:18]
|
|
assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 224:18]
|
|
assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 224:18]
|
|
assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 224:18]
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assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 224:18]
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assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 224:18]
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assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 224:18]
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assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 224:18]
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assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 224:18]
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assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 150:20]
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assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 150:20]
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assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 150:20]
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assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 151:20]
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assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 151:20]
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assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 151:20]
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assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 151:20]
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assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_clz = decode_io_decode_exu_i0_ap_clz; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_ctz = decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_pcnt = decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sext_b = decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sext_h = decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_min = decode_io_decode_exu_i0_ap_min; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_max = decode_io_decode_exu_i0_ap_max; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_pack = decode_io_decode_exu_i0_ap_pack; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_packu = decode_io_decode_exu_i0_ap_packu; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_packh = decode_io_decode_exu_i0_ap_packh; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_rol = decode_io_decode_exu_i0_ap_rol; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_ror = decode_io_decode_exu_i0_ap_ror; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_grev = decode_io_decode_exu_i0_ap_grev; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_gorc = decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_zbb = decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sbset = decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sbclr = decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sbinv = decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sbext = decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_branch_d = decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_result_r = decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_qual_lsu_d = decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 149:23 dec.scala 205:48]
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assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 149:23]
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assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 149:23]
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assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 225:18]
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assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 225:18]
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assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 225:18]
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assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 139:22]
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assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 139:22]
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assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 220:22]
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assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 220:22]
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assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 242:26]
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assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 242:26]
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assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 242:26]
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assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 226:18]
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assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 244:14]
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assign io_dec_pic_dec_tlu_meipt = tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 244:14]
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assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_icaf_second = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 138:22]
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assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 138:22]
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assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 140:22]
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assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 140:22]
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assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 140:22]
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assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 140:22]
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assign decode_clock = clock;
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assign decode_reset = reset;
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assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 149:23]
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assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 149:23]
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assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 150:20]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 157:26]
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assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 157:26]
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assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 152:22]
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assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 147:21]
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assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 167:22]
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assign decode_io_dec_tlu_trace_disable = tlu_io_dec_tlu_trace_disable; // @[dec.scala 153:48]
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assign decode_io_dec_debug_valid_d = instbuff_io_dec_debug_valid_d; // @[dec.scala 154:48]
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assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 155:48]
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assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 156:48]
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assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 158:48]
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assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 159:48]
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assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 160:48]
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assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 161:48]
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assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 162:48]
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assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 163:48]
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assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 165:48]
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assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 166:48]
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assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 168:48]
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assign decode_io_dec_i0_icaf_second_d = instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 169:48]
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assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 170:48]
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assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 171:48]
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assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 172:48]
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assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 172:48]
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assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 173:48]
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assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 174:48]
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assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 175:48]
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assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 176:48]
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assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 177:48]
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assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 178:48]
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assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 179:48]
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assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 180:48]
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assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 181:48]
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assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 182:48]
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assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 183:48]
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assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 184:48]
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assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 185:48]
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assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 186:48]
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assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 187:48]
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assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 188:48]
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assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 189:48]
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assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 190:48]
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assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 191:48]
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assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 192:48]
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assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 193:48]
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assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 194:48]
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assign decode_io_active_clk = io_active_clk; // @[dec.scala 196:48]
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assign decode_io_free_l2clk = io_free_l2clk; // @[dec.scala 195:48]
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assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 197:48]
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assign gpr_clock = clock;
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assign gpr_reset = reset;
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assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 208:23]
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assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 209:23]
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assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 210:23]
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assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 211:23]
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assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 212:23]
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assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 213:23]
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assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 214:23]
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assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[dec.scala 215:23]
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assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 216:23]
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assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 217:23]
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assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 218:23]
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assign tlu_clock = clock;
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assign tlu_reset = reset;
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assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 225:18]
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assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 225:18]
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assign tlu_io_tlu_dma_dma_pmu_dccm_read = io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 226:18]
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assign tlu_io_tlu_dma_dma_pmu_dccm_write = io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 226:18]
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assign tlu_io_tlu_dma_dma_pmu_any_read = io_dec_dma_tlu_dma_dma_pmu_any_read; // @[dec.scala 226:18]
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assign tlu_io_tlu_dma_dma_pmu_any_write = io_dec_dma_tlu_dma_dma_pmu_any_write; // @[dec.scala 226:18]
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assign tlu_io_tlu_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dec.scala 226:18]
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assign tlu_io_tlu_dma_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dec.scala 226:18]
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assign tlu_io_free_clk = io_free_clk; // @[dec.scala 228:45]
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assign tlu_io_free_l2clk = io_free_l2clk; // @[dec.scala 227:45]
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assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 230:45]
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assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 231:45]
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assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 232:45]
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assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 233:45]
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assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 234:45]
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assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 235:45]
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assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 266:45]
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assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 237:45]
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assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 238:45]
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assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 239:45]
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assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 240:45]
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assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 241:45]
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assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 245:45]
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assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 246:45]
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assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 247:45]
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assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 248:45]
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assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 248:45]
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assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 248:45]
|
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assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 248:45]
|
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assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 248:45]
|
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assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 248:45]
|
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assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 249:45]
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assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 250:45]
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assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 251:45]
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assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 252:45]
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assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 253:45]
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assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 254:45]
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assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 255:45]
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assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 256:45]
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assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 257:45]
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assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 258:45]
|
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assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 259:45]
|
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assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_icaf_second = decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 260:45]
|
|
assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 260:45]
|
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assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 260:45]
|
|
assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 260:45]
|
|
assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 261:45]
|
|
assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[dec.scala 262:45]
|
|
assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 263:45]
|
|
assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 264:45]
|
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assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 265:45]
|
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assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 267:45]
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assign tlu_io_timer_int = io_timer_int; // @[dec.scala 268:45]
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assign tlu_io_soft_int = io_soft_int; // @[dec.scala 269:45]
|
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assign tlu_io_core_id = io_core_id; // @[dec.scala 270:45]
|
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assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 271:45]
|
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assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 272:45]
|
|
assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 273:45]
|
|
assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 236:45]
|
|
assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 223:18]
|
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assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 222:18]
|
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assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 222:18]
|
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assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 222:18]
|
|
assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 242:26]
|
|
assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 242:26]
|
|
assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 243:14]
|
|
assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 243:14]
|
|
assign tlu_io_dec_pic_pic_claimid = io_dec_pic_pic_claimid; // @[dec.scala 244:14]
|
|
assign tlu_io_dec_pic_pic_pl = io_dec_pic_pic_pl; // @[dec.scala 244:14]
|
|
assign tlu_io_dec_pic_mhwakeup = io_dec_pic_mhwakeup; // @[dec.scala 244:14]
|
|
assign tlu_io_dec_pic_mexintpend = io_dec_pic_mexintpend; // @[dec.scala 244:14]
|
|
assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 143:34]
|
|
assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 142:30]
|
|
endmodule
|
|
module dbg(
|
|
input clock,
|
|
input reset,
|
|
output [1:0] io_dbg_cmd_size,
|
|
output io_dbg_core_rst_l,
|
|
input [31:0] io_core_dbg_rddata,
|
|
input io_core_dbg_cmd_done,
|
|
input io_core_dbg_cmd_fail,
|
|
output io_dbg_halt_req,
|
|
output io_dbg_resume_req,
|
|
input io_dec_tlu_dbg_halted,
|
|
input io_dec_tlu_mpc_halted_only,
|
|
input io_dec_tlu_resume_ack,
|
|
input io_dmi_reg_en,
|
|
input [6:0] io_dmi_reg_addr,
|
|
input io_dmi_reg_wr_en,
|
|
input [31:0] io_dmi_reg_wdata,
|
|
output [31:0] io_dmi_reg_rdata,
|
|
input io_sb_axi_aw_ready,
|
|
output io_sb_axi_aw_valid,
|
|
output [31:0] io_sb_axi_aw_bits_addr,
|
|
output [3:0] io_sb_axi_aw_bits_region,
|
|
output [2:0] io_sb_axi_aw_bits_size,
|
|
input io_sb_axi_w_ready,
|
|
output io_sb_axi_w_valid,
|
|
output [63:0] io_sb_axi_w_bits_data,
|
|
output [7:0] io_sb_axi_w_bits_strb,
|
|
output io_sb_axi_b_ready,
|
|
input io_sb_axi_b_valid,
|
|
input [1:0] io_sb_axi_b_bits_resp,
|
|
input io_sb_axi_ar_ready,
|
|
output io_sb_axi_ar_valid,
|
|
output [31:0] io_sb_axi_ar_bits_addr,
|
|
output [3:0] io_sb_axi_ar_bits_region,
|
|
output [2:0] io_sb_axi_ar_bits_size,
|
|
output io_sb_axi_r_ready,
|
|
input io_sb_axi_r_valid,
|
|
input [63:0] io_sb_axi_r_bits_data,
|
|
input [1:0] io_sb_axi_r_bits_resp,
|
|
output io_dbg_dec_dma_dbg_ib_dbg_cmd_valid,
|
|
output io_dbg_dec_dma_dbg_ib_dbg_cmd_write,
|
|
output [1:0] io_dbg_dec_dma_dbg_ib_dbg_cmd_type,
|
|
output [31:0] io_dbg_dec_dma_dbg_ib_dbg_cmd_addr,
|
|
output [31:0] io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata,
|
|
output io_dbg_dma_dbg_dma_bubble,
|
|
input io_dbg_dma_dma_dbg_ready,
|
|
input io_dbg_bus_clk_en,
|
|
input io_dbg_rst_l,
|
|
input io_scan_mode
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire [3:0] dbg_state;
|
|
wire dbg_state_en;
|
|
wire [3:0] sb_state;
|
|
wire sb_state_en;
|
|
wire [31:0] dmcontrol_reg;
|
|
wire [31:0] sbaddress0_reg;
|
|
wire sbcs_sbbusy_wren;
|
|
wire sbcs_sberror_wren;
|
|
wire [63:0] sb_bus_rdata;
|
|
wire sbaddress0_reg_wren1;
|
|
wire [31:0] dmstatus_reg;
|
|
wire dmstatus_havereset;
|
|
wire dmstatus_haveresetn;
|
|
wire dmstatus_resumeack;
|
|
wire dmstatus_unavail;
|
|
wire dmstatus_running;
|
|
wire dmstatus_halted;
|
|
wire abstractcs_busy_wren;
|
|
wire sb_bus_cmd_read;
|
|
wire sb_bus_cmd_write_addr;
|
|
wire sb_bus_cmd_write_data;
|
|
wire sb_bus_rsp_read;
|
|
wire sb_bus_rsp_error;
|
|
wire sb_bus_rsp_write;
|
|
wire sbcs_sbbusy_din;
|
|
wire [31:0] abmem_addr;
|
|
wire [31:0] sbcs_reg;
|
|
wire execute_command;
|
|
wire [31:0] command_reg;
|
|
wire dbg_sb_bus_error;
|
|
wire command_wren;
|
|
wire [31:0] command_din;
|
|
wire [31:0] dbg_cmd_next_addr;
|
|
wire data0_reg_wren2;
|
|
wire sb_abmem_cmd_done_en;
|
|
wire sb_abmem_data_done_en;
|
|
wire abmem_addr_external;
|
|
wire sb_cmd_pending;
|
|
wire sb_abmem_cmd_write;
|
|
wire abmem_addr_in_dccm_region;
|
|
wire abmem_addr_in_iccm_region;
|
|
wire abmem_addr_in_pic_region;
|
|
wire [3:0] sb_abmem_cmd_size;
|
|
wire dmcontrol_wren_Q;
|
|
wire [31:0] abstractcs_reg;
|
|
wire _T_14 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 121:74]
|
|
wire dbg_dm_rst_l = io_dbg_rst_l & _T_14; // @[dbg.scala 121:103]
|
|
wire _T_17 = ~dmcontrol_reg[1]; // @[dbg.scala 122:32]
|
|
wire _T_20 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 123:48]
|
|
wire _T_21 = _T_20 & io_dmi_reg_en; // @[dbg.scala 123:66]
|
|
wire _T_22 = _T_21 & io_dmi_reg_wr_en; // @[dbg.scala 123:82]
|
|
wire _T_23 = sb_state == 4'h0; // @[dbg.scala 123:113]
|
|
wire sbcs_wren = _T_22 & _T_23; // @[dbg.scala 123:101]
|
|
wire _T_25 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 124:42]
|
|
wire _T_27 = sbcs_reg[21] & io_dmi_reg_en; // @[dbg.scala 124:82]
|
|
wire _T_28 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 125:22]
|
|
wire _T_29 = io_dmi_reg_wr_en & _T_28; // @[dbg.scala 124:119]
|
|
wire _T_30 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 125:60]
|
|
wire _T_31 = _T_29 | _T_30; // @[dbg.scala 125:41]
|
|
wire _T_32 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 126:22]
|
|
wire _T_33 = _T_31 | _T_32; // @[dbg.scala 125:78]
|
|
wire _T_34 = _T_27 & _T_33; // @[dbg.scala 124:98]
|
|
wire sbcs_sbbusyerror_wren = _T_25 | _T_34; // @[dbg.scala 124:66]
|
|
wire sbcs_sbbusyerror_din = ~_T_25; // @[dbg.scala 128:32]
|
|
reg temp_sbcs_22; // @[Reg.scala 27:20]
|
|
reg temp_sbcs_21; // @[Reg.scala 27:20]
|
|
reg temp_sbcs_20; // @[Reg.scala 27:20]
|
|
wire _T_40 = ~io_dmi_reg_wdata[18]; // @[dbg.scala 136:41]
|
|
wire [4:0] _T_43 = {io_dmi_reg_wdata[19],_T_40,io_dmi_reg_wdata[17:15]}; // @[Cat.scala 29:58]
|
|
reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20]
|
|
reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20]
|
|
wire _T_47 = ~temp_sbcs_19_15[3]; // @[dbg.scala 140:101]
|
|
wire [18:0] _T_52 = {_T_47,temp_sbcs_19_15[2:0],temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_57 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20,temp_sbcs_19_15[4]}; // @[Cat.scala 29:58]
|
|
wire _T_60 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 143:42]
|
|
wire _T_62 = _T_60 & sbaddress0_reg[0]; // @[dbg.scala 143:56]
|
|
wire _T_64 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 144:23]
|
|
wire _T_66 = |sbaddress0_reg[1:0]; // @[dbg.scala 144:60]
|
|
wire _T_67 = _T_64 & _T_66; // @[dbg.scala 144:37]
|
|
wire _T_68 = _T_62 | _T_67; // @[dbg.scala 143:76]
|
|
wire _T_70 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 145:23]
|
|
wire _T_72 = |sbaddress0_reg[2:0]; // @[dbg.scala 145:60]
|
|
wire _T_73 = _T_70 & _T_72; // @[dbg.scala 145:37]
|
|
wire sbcs_unaligned = _T_68 | _T_73; // @[dbg.scala 144:64]
|
|
wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 147:35]
|
|
wire _T_75 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 148:53]
|
|
wire [3:0] _T_77 = _T_75 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_78 = _T_77 & 4'h1; // @[dbg.scala 148:68]
|
|
wire [3:0] _T_82 = _T_60 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_83 = _T_82 & 4'h2; // @[dbg.scala 148:122]
|
|
wire [3:0] _T_84 = _T_78 | _T_83; // @[dbg.scala 148:79]
|
|
wire [3:0] _T_88 = _T_64 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_89 = _T_88 & 4'h4; // @[dbg.scala 149:46]
|
|
wire [3:0] _T_90 = _T_84 | _T_89; // @[dbg.scala 148:133]
|
|
wire [3:0] _T_94 = _T_70 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_95 = _T_94 & 4'h8; // @[dbg.scala 149:100]
|
|
wire [3:0] sbaddress0_incr = _T_90 | _T_95; // @[dbg.scala 149:57]
|
|
wire _T_96 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 151:41]
|
|
wire sbdata0_reg_wren0 = _T_96 & _T_30; // @[dbg.scala 151:60]
|
|
wire _T_98 = sb_state == 4'h7; // @[dbg.scala 152:37]
|
|
wire _T_99 = _T_98 & sb_state_en; // @[dbg.scala 152:60]
|
|
wire _T_100 = ~sbcs_sberror_wren; // @[dbg.scala 152:76]
|
|
wire sbdata0_reg_wren1 = _T_99 & _T_100; // @[dbg.scala 152:74]
|
|
wire sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[dbg.scala 153:45]
|
|
wire sbdata1_reg_wren0 = _T_96 & _T_32; // @[dbg.scala 154:60]
|
|
wire sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[dbg.scala 156:45]
|
|
wire [31:0] _T_107 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_108 = _T_107 & io_dmi_reg_wdata; // @[dbg.scala 157:55]
|
|
wire [31:0] _T_110 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_112 = _T_110 & sb_bus_rdata[31:0]; // @[dbg.scala 157:104]
|
|
wire [31:0] sbdata0_din = _T_108 | _T_112; // @[dbg.scala 157:74]
|
|
wire [31:0] _T_114 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_115 = _T_114 & io_dmi_reg_wdata; // @[dbg.scala 158:55]
|
|
wire [31:0] _T_119 = _T_110 & sb_bus_rdata[63:32]; // @[dbg.scala 158:104]
|
|
wire [31:0] sbdata1_din = _T_115 | _T_119; // @[dbg.scala 158:74]
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] sbdata0_reg; // @[Reg.scala 27:20]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] sbdata1_reg; // @[Reg.scala 27:20]
|
|
wire sbaddress0_reg_wren0 = _T_96 & _T_28; // @[dbg.scala 163:64]
|
|
wire sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[dbg.scala 164:52]
|
|
wire [31:0] _T_123 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_124 = _T_123 & io_dmi_reg_wdata; // @[dbg.scala 165:62]
|
|
wire [31:0] _T_126 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_127 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_129 = sbaddress0_reg + _T_127; // @[dbg.scala 166:54]
|
|
wire [31:0] _T_130 = _T_126 & _T_129; // @[dbg.scala 166:36]
|
|
wire [31:0] sbaddress0_reg_din = _T_124 | _T_130; // @[dbg.scala 165:81]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] _T_131; // @[Reg.scala 27:20]
|
|
wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 170:94]
|
|
wire _T_136 = ~io_dmi_reg_wr_en; // @[dbg.scala 171:45]
|
|
wire _T_137 = io_dmi_reg_en & _T_136; // @[dbg.scala 171:43]
|
|
wire _T_139 = _T_137 & _T_30; // @[dbg.scala 171:63]
|
|
wire sbreadondata_access = _T_139 & sbcs_reg[15]; // @[dbg.scala 171:95]
|
|
wire _T_143 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 173:46]
|
|
wire _T_144 = _T_143 & io_dmi_reg_en; // @[dbg.scala 173:59]
|
|
wire dmcontrol_wren = _T_144 & io_dmi_reg_wr_en; // @[dbg.scala 173:75]
|
|
wire _T_147 = ~dmcontrol_reg[31]; // @[dbg.scala 174:50]
|
|
wire _T_148 = dmcontrol_reg[30] & _T_147; // @[dbg.scala 174:48]
|
|
wire resumereq = _T_148 & dmcontrol_wren_Q; // @[dbg.scala 174:69]
|
|
wire [3:0] _T_154 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58]
|
|
reg [3:0] dm_temp; // @[Reg.scala 27:20]
|
|
reg dm_temp_0; // @[Reg.scala 27:20]
|
|
wire [27:0] _T_160 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_162 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58]
|
|
reg _T_163; // @[dbg.scala 184:12]
|
|
wire [1:0] _T_165 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_167 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_169 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_171 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_173 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [11:0] _T_177 = {_T_171,_T_173,1'h1,7'h2}; // @[Cat.scala 29:58]
|
|
wire [19:0] _T_181 = {12'h0,_T_165,_T_167,2'h0,_T_169}; // @[Cat.scala 29:58]
|
|
wire _T_183 = dbg_state == 4'h9; // @[dbg.scala 189:44]
|
|
wire _T_184 = _T_183 & io_dec_tlu_resume_ack; // @[dbg.scala 189:66]
|
|
wire _T_185 = dmstatus_resumeack & resumereq; // @[dbg.scala 189:111]
|
|
wire _T_186 = _T_185 & dmstatus_halted; // @[dbg.scala 189:123]
|
|
wire dmstatus_resumeack_wren = _T_184 | _T_186; // @[dbg.scala 189:90]
|
|
wire _T_190 = _T_143 & io_dmi_reg_wdata[28]; // @[dbg.scala 191:64]
|
|
wire _T_191 = _T_190 & io_dmi_reg_en; // @[dbg.scala 191:87]
|
|
wire _T_192 = _T_191 & io_dmi_reg_wr_en; // @[dbg.scala 191:103]
|
|
wire dmstatus_haveresetn_wren = _T_192 & dmcontrol_reg[0]; // @[dbg.scala 191:122]
|
|
wire _T_196 = ~reset; // @[dbg.scala 195:43]
|
|
wire _T_199 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 196:42]
|
|
reg _T_202; // @[Reg.scala 27:20]
|
|
wire _T_203 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 201:37]
|
|
reg _T_205; // @[dbg.scala 201:12]
|
|
reg _T_206; // @[Reg.scala 27:20]
|
|
wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58]
|
|
wire _T_209 = |abstractcs_reg[10:8]; // @[dbg.scala 207:75]
|
|
wire _T_210 = ~_T_209; // @[dbg.scala 207:52]
|
|
wire _T_211 = abstractcs_reg[12] & _T_210; // @[dbg.scala 207:50]
|
|
wire _T_212 = _T_211 & io_dmi_reg_en; // @[dbg.scala 207:80]
|
|
wire _T_213 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 207:137]
|
|
wire _T_214 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:22]
|
|
wire _T_215 = _T_213 | _T_214; // @[dbg.scala 207:155]
|
|
wire _T_216 = io_dmi_reg_wr_en & _T_215; // @[dbg.scala 207:117]
|
|
wire _T_217 = io_dmi_reg_addr == 7'h18; // @[dbg.scala 208:60]
|
|
wire _T_218 = _T_216 | _T_217; // @[dbg.scala 208:41]
|
|
wire _T_219 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:98]
|
|
wire _T_220 = _T_218 | _T_219; // @[dbg.scala 208:79]
|
|
wire _T_221 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 209:22]
|
|
wire _T_222 = _T_220 | _T_221; // @[dbg.scala 208:112]
|
|
wire abstractcs_error_sel0 = _T_212 & _T_222; // @[dbg.scala 207:96]
|
|
wire _T_226 = execute_command & _T_210; // @[dbg.scala 210:47]
|
|
wire _T_228 = command_reg[31:24] == 8'h0; // @[dbg.scala 211:29]
|
|
wire _T_230 = command_reg[31:24] == 8'h2; // @[dbg.scala 211:65]
|
|
wire _T_231 = _T_228 | _T_230; // @[dbg.scala 211:43]
|
|
wire _T_232 = ~_T_231; // @[dbg.scala 211:7]
|
|
wire _T_234 = command_reg[22:20] == 3'h3; // @[dbg.scala 212:29]
|
|
wire _T_236 = _T_234 | command_reg[22]; // @[dbg.scala 212:43]
|
|
wire _T_239 = _T_236 & _T_230; // @[dbg.scala 212:64]
|
|
wire _T_240 = _T_232 | _T_239; // @[dbg.scala 211:81]
|
|
wire _T_242 = command_reg[22:20] != 3'h2; // @[dbg.scala 213:28]
|
|
wire _T_246 = _T_228 & command_reg[17]; // @[dbg.scala 213:79]
|
|
wire _T_247 = _T_242 & _T_246; // @[dbg.scala 213:42]
|
|
wire _T_248 = _T_240 | _T_247; // @[dbg.scala 212:101]
|
|
wire _T_252 = _T_228 & command_reg[18]; // @[dbg.scala 214:42]
|
|
wire _T_253 = _T_248 | _T_252; // @[dbg.scala 213:101]
|
|
wire abstractcs_error_sel1 = _T_226 & _T_253; // @[dbg.scala 210:77]
|
|
wire _T_254 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 215:54]
|
|
wire _T_257 = execute_command & _T_228; // @[dbg.scala 216:22]
|
|
wire _T_259 = command_reg[15:12] == 4'h1; // @[dbg.scala 217:29]
|
|
wire _T_261 = command_reg[11:5] != 7'h0; // @[dbg.scala 217:64]
|
|
wire _T_262 = _T_259 & _T_261; // @[dbg.scala 217:43]
|
|
wire _T_264 = command_reg[15:13] != 3'h0; // @[dbg.scala 217:101]
|
|
wire _T_265 = _T_262 | _T_264; // @[dbg.scala 217:79]
|
|
wire _T_266 = _T_257 & _T_265; // @[dbg.scala 216:58]
|
|
wire _T_267 = _T_254 | _T_266; // @[dbg.scala 215:78]
|
|
wire abstractcs_error_sel2 = _T_267 & _T_210; // @[dbg.scala 217:118]
|
|
wire _T_271 = dbg_state != 4'h2; // @[dbg.scala 218:60]
|
|
wire _T_272 = execute_command & _T_271; // @[dbg.scala 218:47]
|
|
wire abstractcs_error_sel3 = _T_272 & _T_210; // @[dbg.scala 218:80]
|
|
wire _T_276 = dbg_sb_bus_error & io_dbg_bus_clk_en; // @[dbg.scala 219:48]
|
|
wire abstractcs_error_sel4 = _T_276 & _T_210; // @[dbg.scala 219:68]
|
|
wire _T_282 = execute_command & _T_230; // @[dbg.scala 220:47]
|
|
wire _T_286 = _T_282 & _T_210; // @[dbg.scala 220:83]
|
|
wire _T_288 = command_reg[22:20] == 3'h1; // @[dbg.scala 221:27]
|
|
wire _T_290 = _T_288 & abmem_addr[0]; // @[dbg.scala 221:41]
|
|
wire _T_292 = command_reg[22:20] == 3'h2; // @[dbg.scala 221:80]
|
|
wire _T_294 = |abmem_addr[1:0]; // @[dbg.scala 221:112]
|
|
wire _T_295 = _T_292 & _T_294; // @[dbg.scala 221:94]
|
|
wire _T_296 = _T_290 | _T_295; // @[dbg.scala 221:57]
|
|
wire abstractcs_error_sel5 = _T_286 & _T_296; // @[dbg.scala 220:113]
|
|
wire _T_298 = _T_213 & io_dmi_reg_en; // @[dbg.scala 222:67]
|
|
wire abstractcs_error_sel6 = _T_298 & io_dmi_reg_wr_en; // @[dbg.scala 222:83]
|
|
wire [2:0] _T_301 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 231:31]
|
|
wire [2:0] _T_303 = _T_301 & abstractcs_reg[10:8]; // @[dbg.scala 231:55]
|
|
reg abs_temp_12; // @[Reg.scala 27:20]
|
|
reg [2:0] abs_temp_10_8; // @[dbg.scala 236:12]
|
|
wire [10:0] _T_311 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58]
|
|
wire [20:0] _T_313 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_317 = _T_96 & _T_217; // @[dbg.scala 240:64]
|
|
wire _T_319 = ~abstractcs_reg[12]; // @[dbg.scala 240:103]
|
|
wire abstractauto_reg_wren = _T_317 & _T_319; // @[dbg.scala 240:101]
|
|
reg [1:0] abstractauto_reg; // @[Reg.scala 27:20]
|
|
wire _T_323 = io_dmi_reg_en & _T_319; // @[dbg.scala 244:58]
|
|
wire _T_326 = _T_219 & abstractauto_reg[0]; // @[dbg.scala 244:115]
|
|
wire _T_329 = _T_221 & abstractauto_reg[1]; // @[dbg.scala 245:60]
|
|
wire _T_330 = _T_326 | _T_329; // @[dbg.scala 245:26]
|
|
wire _T_331 = _T_323 & _T_330; // @[dbg.scala 244:80]
|
|
wire _T_333 = _T_214 & io_dmi_reg_en; // @[dbg.scala 246:64]
|
|
wire _T_338 = _T_228 & command_reg[19]; // @[dbg.scala 247:78]
|
|
wire _T_339 = dbg_state == 4'h8; // @[dbg.scala 247:109]
|
|
wire _T_340 = _T_338 & _T_339; // @[dbg.scala 247:96]
|
|
wire _T_344 = _T_340 & _T_210; // @[dbg.scala 247:131]
|
|
wire command_regno_wren = command_wren | _T_344; // @[dbg.scala 247:41]
|
|
wire _T_346 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 250:58]
|
|
wire command_postexec_din = _T_346 & io_dmi_reg_wdata[18]; // @[dbg.scala 250:72]
|
|
wire command_transfer_din = _T_346 & io_dmi_reg_wdata[17]; // @[dbg.scala 251:72]
|
|
wire [15:0] temp_command_din_31_16 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din,io_dmi_reg_wdata[16]}; // @[Cat.scala 29:58]
|
|
wire [15:0] temp_command_din_15_0 = command_wren ? io_dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]; // @[dbg.scala 253:37]
|
|
reg _T_361; // @[dbg.scala 257:12]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
reg [15:0] temp_command_reg_31_16; // @[Reg.scala 27:20]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
reg [15:0] temp_command_reg_15_0; // @[Reg.scala 27:20]
|
|
wire _T_367 = _T_96 & _T_219; // @[dbg.scala 266:58]
|
|
wire _T_368 = dbg_state == 4'h2; // @[dbg.scala 266:102]
|
|
wire _T_369 = _T_367 & _T_368; // @[dbg.scala 266:89]
|
|
wire data0_reg_wren0 = _T_369 & _T_319; // @[dbg.scala 266:122]
|
|
wire _T_372 = dbg_state == 4'h4; // @[dbg.scala 267:59]
|
|
wire _T_373 = io_core_dbg_cmd_done & _T_372; // @[dbg.scala 267:46]
|
|
wire _T_375 = ~command_reg[16]; // @[dbg.scala 267:88]
|
|
wire data0_reg_wren1 = _T_373 & _T_375; // @[dbg.scala 267:86]
|
|
wire _T_376 = data0_reg_wren0 | data0_reg_wren1; // @[dbg.scala 268:41]
|
|
wire data0_reg_wren = _T_376 | data0_reg_wren2; // @[dbg.scala 268:59]
|
|
wire [31:0] _T_378 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_379 = _T_378 & io_dmi_reg_wdata; // @[dbg.scala 270:45]
|
|
wire [31:0] _T_381 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_382 = _T_381 & io_core_dbg_rddata; // @[dbg.scala 271:31]
|
|
wire [31:0] _T_383 = _T_379 | _T_382; // @[dbg.scala 270:64]
|
|
wire [31:0] _T_385 = data0_reg_wren2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_387 = _T_385 & sb_bus_rdata[31:0]; // @[dbg.scala 272:31]
|
|
wire [31:0] data0_din = _T_383 | _T_387; // @[dbg.scala 271:52]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] data0_reg; // @[Reg.scala 27:20]
|
|
wire _T_390 = _T_96 & _T_221; // @[dbg.scala 277:59]
|
|
wire _T_392 = _T_390 & _T_368; // @[dbg.scala 277:92]
|
|
wire data1_reg_wren0 = _T_392 & _T_319; // @[dbg.scala 277:126]
|
|
wire _T_398 = _T_339 & _T_230; // @[dbg.scala 278:58]
|
|
wire _T_400 = _T_398 & command_reg[19]; // @[dbg.scala 278:94]
|
|
wire data1_reg_wren1 = _T_400 & _T_210; // @[dbg.scala 278:112]
|
|
wire data1_reg_wren = data1_reg_wren0 | data1_reg_wren1; // @[dbg.scala 279:41]
|
|
wire [31:0] _T_405 = data1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_406 = _T_405 & io_dmi_reg_wdata; // @[dbg.scala 281:45]
|
|
wire [31:0] _T_408 = data1_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_410 = _T_408 & dbg_cmd_next_addr; // @[dbg.scala 281:92]
|
|
wire [31:0] data1_din = _T_406 | _T_410; // @[dbg.scala 281:64]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] _T_411; // @[Reg.scala 27:20]
|
|
reg sb_abmem_cmd_done; // @[Reg.scala 27:20]
|
|
reg sb_abmem_data_done; // @[Reg.scala 27:20]
|
|
wire [3:0] dbg_nxtstate;
|
|
wire _T_412 = 4'h0 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_414 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 304:46]
|
|
wire [3:0] _T_415 = _T_414 ? 4'h2 : 4'h1; // @[dbg.scala 304:29]
|
|
wire _T_418 = dmcontrol_reg[31] | dmstatus_reg[9]; // @[dbg.scala 305:46]
|
|
wire _T_419 = _T_418 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 305:64]
|
|
wire _T_422 = 4'h1 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_426 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 311:44]
|
|
wire _T_428 = 4'h2 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_432 = _T_230 & abmem_addr_external; // @[dbg.scala 314:116]
|
|
wire [3:0] _T_433 = _T_432 ? 4'h5 : 4'h3; // @[dbg.scala 314:80]
|
|
wire [3:0] _T_434 = resumereq ? 4'h9 : _T_433; // @[dbg.scala 314:47]
|
|
wire [3:0] _T_436 = dmcontrol_reg[31] ? 4'h1 : 4'h0; // @[dbg.scala 315:60]
|
|
wire [3:0] _T_437 = dmstatus_reg[9] ? _T_434 : _T_436; // @[dbg.scala 314:26]
|
|
wire _T_439 = dmstatus_reg[9] & resumereq; // @[dbg.scala 316:39]
|
|
wire _T_440 = _T_439 | execute_command; // @[dbg.scala 316:51]
|
|
wire _T_443 = ~_T_414; // @[dbg.scala 316:71]
|
|
wire _T_444 = _T_440 | _T_443; // @[dbg.scala 316:69]
|
|
wire _T_445 = dbg_nxtstate == 4'h3; // @[dbg.scala 318:62]
|
|
wire _T_446 = dbg_nxtstate == 4'h5; // @[dbg.scala 318:106]
|
|
wire _T_447 = _T_445 | _T_446; // @[dbg.scala 318:90]
|
|
wire _T_448 = dbg_state_en & _T_447; // @[dbg.scala 318:45]
|
|
wire _T_449 = dbg_nxtstate == 4'h9; // @[dbg.scala 320:62]
|
|
wire _T_450 = dbg_state_en & _T_449; // @[dbg.scala 320:46]
|
|
wire _T_455 = 4'h3 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_461 = ~command_reg[17]; // @[dbg.scala 324:96]
|
|
wire _T_462 = _T_228 & _T_461; // @[dbg.scala 324:94]
|
|
wire _T_463 = _T_209 | _T_462; // @[dbg.scala 324:56]
|
|
wire [3:0] _T_464 = _T_463 ? 4'h8 : 4'h4; // @[dbg.scala 324:29]
|
|
wire _T_467 = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid | _T_209; // @[dbg.scala 325:62]
|
|
wire _T_473 = _T_467 | _T_462; // @[dbg.scala 325:90]
|
|
wire _T_477 = 4'h4 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_481 = 4'h5 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire [3:0] _T_484 = _T_209 ? 4'h8 : 4'h6; // @[dbg.scala 334:29]
|
|
wire _T_485 = ~sb_cmd_pending; // @[dbg.scala 335:47]
|
|
wire _T_486 = io_dbg_bus_clk_en & _T_485; // @[dbg.scala 335:45]
|
|
wire _T_489 = _T_486 | _T_209; // @[dbg.scala 335:64]
|
|
wire _T_493 = 4'h6 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_494 = sb_bus_cmd_read | sb_bus_cmd_write_addr; // @[dbg.scala 341:49]
|
|
wire _T_495 = _T_494 & io_dbg_bus_clk_en; // @[dbg.scala 341:74]
|
|
wire _T_496 = sb_bus_cmd_read | sb_bus_cmd_write_data; // @[dbg.scala 342:49]
|
|
wire _T_497 = _T_496 & io_dbg_bus_clk_en; // @[dbg.scala 342:74]
|
|
wire _T_498 = sb_abmem_cmd_done | sb_abmem_cmd_done_en; // @[dbg.scala 344:51]
|
|
wire _T_499 = sb_abmem_data_done | sb_abmem_data_done_en; // @[dbg.scala 344:97]
|
|
wire _T_500 = _T_498 & _T_499; // @[dbg.scala 344:75]
|
|
wire _T_501 = _T_500 & io_dbg_bus_clk_en; // @[dbg.scala 344:122]
|
|
wire _T_505 = 4'h7 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_506 = sb_bus_rsp_read | sb_bus_rsp_write; // @[dbg.scala 349:45]
|
|
wire _T_507 = _T_506 & io_dbg_bus_clk_en; // @[dbg.scala 349:65]
|
|
wire _T_509 = _T_506 & sb_bus_rsp_error; // @[dbg.scala 350:65]
|
|
wire _T_510 = _T_509 & io_dbg_bus_clk_en; // @[dbg.scala 350:84]
|
|
wire _T_511 = ~sb_abmem_cmd_write; // @[dbg.scala 351:43]
|
|
wire _T_512 = dbg_state_en & _T_511; // @[dbg.scala 351:41]
|
|
wire _T_513 = ~dbg_sb_bus_error; // @[dbg.scala 351:65]
|
|
wire _T_514 = _T_512 & _T_513; // @[dbg.scala 351:63]
|
|
wire _T_518 = 4'h8 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _T_525 = 4'h9 == dbg_state; // @[Conditional.scala 37:30]
|
|
wire _GEN_21 = _T_525 & dmstatus_reg[17]; // @[Conditional.scala 39:67]
|
|
wire _GEN_22 = _T_525 & _T_426; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_23 = _T_518 ? 4'h2 : 4'h0; // @[Conditional.scala 39:67]
|
|
wire _GEN_24 = _T_518 | _GEN_21; // @[Conditional.scala 39:67]
|
|
wire _GEN_25 = _T_518 & dbg_state_en; // @[Conditional.scala 39:67]
|
|
wire _GEN_27 = _T_518 ? _T_426 : _GEN_22; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_29 = _T_505 ? 4'h8 : _GEN_23; // @[Conditional.scala 39:67]
|
|
wire _GEN_30 = _T_505 ? _T_507 : _GEN_24; // @[Conditional.scala 39:67]
|
|
wire _GEN_31 = _T_505 & _T_510; // @[Conditional.scala 39:67]
|
|
wire _GEN_32 = _T_505 & _T_514; // @[Conditional.scala 39:67]
|
|
wire _GEN_33 = _T_505 ? _T_426 : _GEN_27; // @[Conditional.scala 39:67]
|
|
wire _GEN_34 = _T_505 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67]
|
|
wire _GEN_36 = _T_505 ? 1'h0 : _T_518; // @[Conditional.scala 39:67]
|
|
wire _GEN_38 = _T_493 ? _T_495 : _GEN_36; // @[Conditional.scala 39:67]
|
|
wire _GEN_39 = _T_493 ? _T_497 : _GEN_36; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_40 = _T_493 ? 4'h7 : _GEN_29; // @[Conditional.scala 39:67]
|
|
wire _GEN_41 = _T_493 ? _T_501 : _GEN_30; // @[Conditional.scala 39:67]
|
|
wire _GEN_42 = _T_493 ? _T_426 : _GEN_33; // @[Conditional.scala 39:67]
|
|
wire _GEN_43 = _T_493 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
|
|
wire _GEN_44 = _T_493 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
|
|
wire _GEN_45 = _T_493 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_47 = _T_481 ? _T_484 : _GEN_40; // @[Conditional.scala 39:67]
|
|
wire _GEN_48 = _T_481 ? _T_489 : _GEN_41; // @[Conditional.scala 39:67]
|
|
wire _GEN_49 = _T_481 ? _T_426 : _GEN_42; // @[Conditional.scala 39:67]
|
|
wire _GEN_51 = _T_481 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
|
|
wire _GEN_52 = _T_481 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
|
|
wire _GEN_53 = _T_481 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
|
|
wire _GEN_54 = _T_481 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67]
|
|
wire _GEN_55 = _T_481 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_57 = _T_477 ? 4'h8 : _GEN_47; // @[Conditional.scala 39:67]
|
|
wire _GEN_58 = _T_477 ? io_core_dbg_cmd_done : _GEN_48; // @[Conditional.scala 39:67]
|
|
wire _GEN_59 = _T_477 ? _T_426 : _GEN_49; // @[Conditional.scala 39:67]
|
|
wire _GEN_61 = _T_477 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67]
|
|
wire _GEN_62 = _T_477 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
|
|
wire _GEN_63 = _T_477 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
|
|
wire _GEN_64 = _T_477 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
|
|
wire _GEN_65 = _T_477 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_67 = _T_455 ? _T_464 : _GEN_57; // @[Conditional.scala 39:67]
|
|
wire _GEN_68 = _T_455 ? _T_473 : _GEN_58; // @[Conditional.scala 39:67]
|
|
wire _GEN_69 = _T_455 ? _T_426 : _GEN_59; // @[Conditional.scala 39:67]
|
|
wire _GEN_71 = _T_455 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
|
|
wire _GEN_72 = _T_455 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
|
|
wire _GEN_73 = _T_455 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
|
|
wire _GEN_74 = _T_455 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
|
|
wire _GEN_75 = _T_455 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_77 = _T_428 ? _T_437 : _GEN_67; // @[Conditional.scala 39:67]
|
|
wire _GEN_78 = _T_428 ? _T_444 : _GEN_68; // @[Conditional.scala 39:67]
|
|
wire _GEN_79 = _T_428 ? _T_448 : _GEN_75; // @[Conditional.scala 39:67]
|
|
wire _GEN_81 = _T_428 & _T_450; // @[Conditional.scala 39:67]
|
|
wire _GEN_82 = _T_428 ? _T_426 : _GEN_69; // @[Conditional.scala 39:67]
|
|
wire _GEN_84 = _T_428 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
|
|
wire _GEN_85 = _T_428 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
|
|
wire _GEN_86 = _T_428 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
|
|
wire _GEN_87 = _T_428 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_88 = _T_422 ? 4'h2 : _GEN_77; // @[Conditional.scala 39:67]
|
|
wire _GEN_89 = _T_422 ? _T_414 : _GEN_78; // @[Conditional.scala 39:67]
|
|
wire _GEN_90 = _T_422 ? _T_426 : _GEN_82; // @[Conditional.scala 39:67]
|
|
wire _GEN_91 = _T_422 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
|
|
wire _GEN_93 = _T_422 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
|
|
wire _GEN_95 = _T_422 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67]
|
|
wire _GEN_96 = _T_422 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67]
|
|
wire _GEN_97 = _T_422 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67]
|
|
wire _GEN_98 = _T_422 ? 1'h0 : _GEN_87; // @[Conditional.scala 39:67]
|
|
wire [31:0] _T_532 = _T_219 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_533 = _T_532 & data0_reg; // @[dbg.scala 372:76]
|
|
wire [31:0] _T_536 = _T_221 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_537 = _T_536 & abmem_addr; // @[dbg.scala 373:47]
|
|
wire [31:0] _T_538 = _T_533 | _T_537; // @[dbg.scala 372:88]
|
|
wire [31:0] _T_541 = _T_143 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_546 = {2'h0,dmcontrol_reg[29],1'h0,dmcontrol_reg[27:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_547 = _T_541 & _T_546; // @[dbg.scala 374:48]
|
|
wire [31:0] _T_548 = _T_538 | _T_547; // @[dbg.scala 373:59]
|
|
wire _T_549 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 375:30]
|
|
wire [31:0] _T_551 = _T_549 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_552 = _T_551 & dmstatus_reg; // @[dbg.scala 375:48]
|
|
wire [31:0] _T_553 = _T_548 | _T_552; // @[dbg.scala 374:109]
|
|
wire [31:0] _T_556 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_557 = _T_556 & abstractcs_reg; // @[dbg.scala 376:48]
|
|
wire [31:0] _T_558 = _T_553 | _T_557; // @[dbg.scala 375:63]
|
|
wire [31:0] _T_561 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_562 = _T_561 & command_reg; // @[dbg.scala 377:48]
|
|
wire [31:0] _T_563 = _T_558 | _T_562; // @[dbg.scala 376:65]
|
|
wire [31:0] _T_566 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_568 = {30'h0,abstractauto_reg}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_569 = _T_566 & _T_568; // @[dbg.scala 378:48]
|
|
wire [31:0] _T_570 = _T_563 | _T_569; // @[dbg.scala 377:62]
|
|
wire _T_571 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 379:30]
|
|
wire [31:0] _T_573 = _T_571 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_574 = _T_573 & haltsum0_reg; // @[dbg.scala 379:48]
|
|
wire [31:0] _T_575 = _T_570 | _T_574; // @[dbg.scala 378:88]
|
|
wire [31:0] _T_578 = _T_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_579 = _T_578 & sbcs_reg; // @[dbg.scala 380:48]
|
|
wire [31:0] _T_580 = _T_575 | _T_579; // @[dbg.scala 379:63]
|
|
wire [31:0] _T_583 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_584 = _T_583 & sbaddress0_reg; // @[dbg.scala 381:48]
|
|
wire [31:0] _T_585 = _T_580 | _T_584; // @[dbg.scala 380:59]
|
|
wire [31:0] _T_588 = _T_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_589 = _T_588 & sbdata0_reg; // @[dbg.scala 382:48]
|
|
wire [31:0] _T_590 = _T_585 | _T_589; // @[dbg.scala 381:65]
|
|
wire [31:0] _T_593 = _T_32 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_594 = _T_593 & sbdata1_reg; // @[dbg.scala 383:48]
|
|
wire [31:0] dmi_reg_rdata_din = _T_590 | _T_594; // @[dbg.scala 382:62]
|
|
wire _T_595 = io_dbg_rst_l & _T_14; // @[dbg.scala 385:68]
|
|
wire _T_597 = _T_595 & reset; // @[dbg.scala 385:95]
|
|
reg [3:0] _T_598; // @[Reg.scala 27:20]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
reg [31:0] _T_599; // @[Reg.scala 27:20]
|
|
wire _T_600 = abmem_addr_in_dccm_region | abmem_addr_in_iccm_region; // @[dbg.scala 392:58]
|
|
wire abmem_addr_core_local = _T_600 | abmem_addr_in_pic_region; // @[dbg.scala 392:86]
|
|
wire [31:0] _T_613 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58]
|
|
wire _T_616 = dbg_state == 4'h3; // @[dbg.scala 401:54]
|
|
wire _T_628 = _T_463 | _T_432; // @[dbg.scala 401:170]
|
|
wire _T_629 = ~_T_628; // @[dbg.scala 401:84]
|
|
wire _T_630 = _T_616 & _T_629; // @[dbg.scala 401:82]
|
|
wire _T_637 = command_reg[15:12] == 4'h0; // @[dbg.scala 404:123]
|
|
wire [1:0] _T_638 = {1'h0,_T_637}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_644 = 7'h1 << sb_abmem_cmd_size[1:0]; // @[dbg.scala 407:76]
|
|
wire [6:0] dbg_cmd_addr_incr = _T_230 ? _T_644 : 7'h1; // @[dbg.scala 407:30]
|
|
wire [31:0] _T_648 = {16'h0,command_reg[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] dbg_cmd_curr_addr = _T_230 ? abmem_addr : _T_648; // @[dbg.scala 408:30]
|
|
wire [34:0] _T_649 = {28'h0,dbg_cmd_addr_incr}; // @[Cat.scala 29:58]
|
|
wire [34:0] _GEN_180 = {{3'd0}, dbg_cmd_curr_addr}; // @[dbg.scala 409:45]
|
|
wire [34:0] _T_651 = _GEN_180 + _T_649; // @[dbg.scala 409:45]
|
|
wire _T_656 = _T_616 & _T_210; // @[dbg.scala 411:72]
|
|
wire _T_660 = sb_state == 4'h3; // @[dbg.scala 413:41]
|
|
wire _T_661 = sb_state == 4'h4; // @[dbg.scala 413:76]
|
|
wire _T_662 = _T_660 | _T_661; // @[dbg.scala 413:64]
|
|
wire _T_663 = sb_state == 4'h5; // @[dbg.scala 413:111]
|
|
wire _T_664 = _T_662 | _T_663; // @[dbg.scala 413:99]
|
|
wire _T_665 = sb_state == 4'h6; // @[dbg.scala 414:15]
|
|
wire _T_666 = _T_664 | _T_665; // @[dbg.scala 413:139]
|
|
wire _T_668 = _T_666 | _T_98; // @[dbg.scala 414:43]
|
|
wire _T_669 = sb_state == 4'h8; // @[dbg.scala 414:90]
|
|
wire _T_671 = dbg_state == 4'h5; // @[dbg.scala 415:42]
|
|
wire _T_672 = dbg_state == 4'h6; // @[dbg.scala 415:81]
|
|
wire _T_673 = _T_671 | _T_672; // @[dbg.scala 415:68]
|
|
wire _T_674 = dbg_state == 4'h7; // @[dbg.scala 415:119]
|
|
wire sb_abmem_cmd_pending = _T_673 | _T_674; // @[dbg.scala 415:106]
|
|
wire _T_675 = 4'h0 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_677 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 428:40]
|
|
wire _T_678 = _T_677 | sbreadonaddr_access; // @[dbg.scala 428:62]
|
|
wire _T_680 = |sbcs_reg[14:12]; // @[dbg.scala 428:105]
|
|
wire _T_681 = ~_T_680; // @[dbg.scala 428:87]
|
|
wire _T_682 = _T_678 & _T_681; // @[dbg.scala 428:85]
|
|
wire _T_684 = ~sbcs_reg[22]; // @[dbg.scala 428:112]
|
|
wire _T_685 = _T_682 & _T_684; // @[dbg.scala 428:110]
|
|
wire _T_687 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 431:65]
|
|
wire _T_688 = sbcs_wren & _T_687; // @[dbg.scala 431:38]
|
|
wire [2:0] _T_690 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 432:27]
|
|
wire [2:0] _T_692 = _T_690 & sbcs_reg[14:12]; // @[dbg.scala 432:53]
|
|
wire _T_693 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_694 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 435:47]
|
|
wire _T_696 = ~sb_abmem_cmd_pending; // @[dbg.scala 436:49]
|
|
wire _T_697 = io_dbg_bus_clk_en & _T_696; // @[dbg.scala 436:47]
|
|
wire _T_698 = _T_697 | sbcs_unaligned; // @[dbg.scala 436:72]
|
|
wire _T_699 = _T_698 | sbcs_illegal_size; // @[dbg.scala 436:89]
|
|
wire _T_702 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_711 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_712 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 448:38]
|
|
wire _T_713 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_714 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 451:48]
|
|
wire _T_717 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 453:45]
|
|
wire _T_718 = _T_717 & io_dbg_bus_clk_en; // @[dbg.scala 453:70]
|
|
wire _T_719 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_720 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 457:44]
|
|
wire _T_721 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_722 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 461:44]
|
|
wire _T_723 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_724 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 465:38]
|
|
wire _T_725 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 466:40]
|
|
wire _T_726 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_727 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 471:39]
|
|
wire _T_729 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
|
|
wire _T_732 = sbcs_reg[14:12] == 3'h0; // @[dbg.scala 480:63]
|
|
wire _T_733 = sbcs_reg[16] & _T_732; // @[dbg.scala 480:44]
|
|
wire _GEN_115 = _T_729 & _T_733; // @[Conditional.scala 39:67]
|
|
wire _GEN_117 = _T_726 ? _T_727 : _T_729; // @[Conditional.scala 39:67]
|
|
wire _GEN_118 = _T_726 & _T_725; // @[Conditional.scala 39:67]
|
|
wire _GEN_120 = _T_726 ? 1'h0 : _T_729; // @[Conditional.scala 39:67]
|
|
wire _GEN_122 = _T_726 ? 1'h0 : _GEN_115; // @[Conditional.scala 39:67]
|
|
wire _GEN_124 = _T_723 ? _T_724 : _GEN_117; // @[Conditional.scala 39:67]
|
|
wire _GEN_125 = _T_723 ? _T_725 : _GEN_118; // @[Conditional.scala 39:67]
|
|
wire _GEN_127 = _T_723 ? 1'h0 : _GEN_120; // @[Conditional.scala 39:67]
|
|
wire _GEN_129 = _T_723 ? 1'h0 : _GEN_122; // @[Conditional.scala 39:67]
|
|
wire _GEN_131 = _T_721 ? _T_722 : _GEN_124; // @[Conditional.scala 39:67]
|
|
wire _GEN_132 = _T_721 ? 1'h0 : _GEN_125; // @[Conditional.scala 39:67]
|
|
wire _GEN_134 = _T_721 ? 1'h0 : _GEN_127; // @[Conditional.scala 39:67]
|
|
wire _GEN_136 = _T_721 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67]
|
|
wire _GEN_138 = _T_719 ? _T_720 : _GEN_131; // @[Conditional.scala 39:67]
|
|
wire _GEN_139 = _T_719 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67]
|
|
wire _GEN_141 = _T_719 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67]
|
|
wire _GEN_143 = _T_719 ? 1'h0 : _GEN_136; // @[Conditional.scala 39:67]
|
|
wire _GEN_145 = _T_713 ? _T_718 : _GEN_138; // @[Conditional.scala 39:67]
|
|
wire _GEN_146 = _T_713 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67]
|
|
wire _GEN_148 = _T_713 ? 1'h0 : _GEN_141; // @[Conditional.scala 39:67]
|
|
wire _GEN_150 = _T_713 ? 1'h0 : _GEN_143; // @[Conditional.scala 39:67]
|
|
wire _GEN_152 = _T_711 ? _T_712 : _GEN_145; // @[Conditional.scala 39:67]
|
|
wire _GEN_153 = _T_711 ? 1'h0 : _GEN_146; // @[Conditional.scala 39:67]
|
|
wire _GEN_155 = _T_711 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67]
|
|
wire _GEN_157 = _T_711 ? 1'h0 : _GEN_150; // @[Conditional.scala 39:67]
|
|
wire _GEN_159 = _T_702 ? _T_699 : _GEN_152; // @[Conditional.scala 39:67]
|
|
wire _GEN_160 = _T_702 ? _T_694 : _GEN_153; // @[Conditional.scala 39:67]
|
|
wire _GEN_162 = _T_702 ? 1'h0 : _GEN_155; // @[Conditional.scala 39:67]
|
|
wire _GEN_164 = _T_702 ? 1'h0 : _GEN_157; // @[Conditional.scala 39:67]
|
|
wire _GEN_166 = _T_693 ? _T_699 : _GEN_159; // @[Conditional.scala 39:67]
|
|
wire _GEN_167 = _T_693 ? _T_694 : _GEN_160; // @[Conditional.scala 39:67]
|
|
wire _GEN_169 = _T_693 ? 1'h0 : _GEN_162; // @[Conditional.scala 39:67]
|
|
wire _GEN_171 = _T_693 ? 1'h0 : _GEN_164; // @[Conditional.scala 39:67]
|
|
reg [3:0] _T_734; // @[Reg.scala 27:20]
|
|
wire [2:0] _T_737 = {1'h0,command_reg[21:20]}; // @[Cat.scala 29:58]
|
|
wire [63:0] sb_cmd_wdata = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
|
|
wire _T_741 = _T_672 & sb_abmem_cmd_write; // @[dbg.scala 496:67]
|
|
wire _T_742 = ~sb_abmem_cmd_done; // @[dbg.scala 496:90]
|
|
wire sb_abmem_cmd_awvalid = _T_741 & _T_742; // @[dbg.scala 496:88]
|
|
wire _T_745 = ~sb_abmem_data_done; // @[dbg.scala 497:90]
|
|
wire sb_abmem_cmd_wvalid = _T_741 & _T_745; // @[dbg.scala 497:88]
|
|
wire _T_748 = _T_672 & _T_511; // @[dbg.scala 498:67]
|
|
wire _T_750 = _T_748 & _T_742; // @[dbg.scala 498:89]
|
|
wire sb_abmem_cmd_arvalid = _T_750 & _T_745; // @[dbg.scala 498:110]
|
|
wire sb_abmem_read_pend = _T_674 & _T_511; // @[dbg.scala 499:67]
|
|
wire sb_cmd_awvalid = _T_661 | _T_663; // @[dbg.scala 501:59]
|
|
wire sb_cmd_wvalid = _T_661 | _T_665; // @[dbg.scala 502:59]
|
|
wire _T_758 = sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid; // @[dbg.scala 506:49]
|
|
wire _T_759 = _T_758 | sb_abmem_cmd_arvalid; // @[dbg.scala 506:71]
|
|
wire _T_760 = _T_759 | sb_abmem_read_pend; // @[dbg.scala 506:94]
|
|
wire [2:0] sb_axi_size = _T_760 ? sb_abmem_cmd_size[2:0] : sbcs_reg[19:17]; // @[dbg.scala 506:26]
|
|
wire [31:0] sb_axi_addr = _T_760 ? abmem_addr : sbaddress0_reg; // @[dbg.scala 507:26]
|
|
wire [63:0] _T_770 = {data0_reg,data0_reg}; // @[Cat.scala 29:58]
|
|
wire [63:0] sb_axi_wrdata = _T_758 ? _T_770 : sb_cmd_wdata; // @[dbg.scala 508:26]
|
|
wire _T_778 = |io_sb_axi_r_bits_resp; // @[dbg.scala 515:74]
|
|
wire _T_779 = sb_bus_rsp_read & _T_778; // @[dbg.scala 515:44]
|
|
wire _T_781 = |io_sb_axi_b_bits_resp; // @[dbg.scala 515:127]
|
|
wire _T_782 = sb_bus_rsp_write & _T_781; // @[dbg.scala 515:97]
|
|
wire _T_787 = sb_axi_size == 3'h0; // @[dbg.scala 530:52]
|
|
wire [63:0] _T_789 = _T_787 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_793 = {sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0],sb_axi_wrdata[7:0]}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_794 = _T_789 & _T_793; // @[dbg.scala 530:67]
|
|
wire _T_795 = sb_axi_size == 3'h1; // @[dbg.scala 531:27]
|
|
wire [63:0] _T_797 = _T_795 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_800 = {sb_axi_wrdata[15:0],sb_axi_wrdata[15:0],sb_axi_wrdata[15:0],sb_axi_wrdata[15:0]}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_801 = _T_797 & _T_800; // @[dbg.scala 531:42]
|
|
wire [63:0] _T_802 = _T_794 | _T_801; // @[dbg.scala 530:100]
|
|
wire _T_803 = sb_axi_size == 3'h2; // @[dbg.scala 532:27]
|
|
wire [63:0] _T_805 = _T_803 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_807 = {sb_axi_wrdata[31:0],sb_axi_wrdata[31:0]}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_808 = _T_805 & _T_807; // @[dbg.scala 532:42]
|
|
wire [63:0] _T_809 = _T_802 | _T_808; // @[dbg.scala 531:74]
|
|
wire _T_810 = sb_axi_size == 3'h3; // @[dbg.scala 533:27]
|
|
wire [63:0] _T_812 = _T_810 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
|
|
wire [63:0] _T_813 = _T_812 & sb_axi_wrdata; // @[dbg.scala 533:42]
|
|
wire [7:0] _T_817 = _T_787 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [14:0] _T_819 = 15'h1 << sb_axi_addr[2:0]; // @[dbg.scala 535:79]
|
|
wire [14:0] _GEN_181 = {{7'd0}, _T_817}; // @[dbg.scala 535:64]
|
|
wire [14:0] _T_820 = _GEN_181 & _T_819; // @[dbg.scala 535:64]
|
|
wire [7:0] _T_823 = _T_795 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_825 = {sb_axi_addr[2:1],1'h0}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_826 = 15'h3 << _T_825; // @[dbg.scala 536:56]
|
|
wire [14:0] _GEN_182 = {{7'd0}, _T_823}; // @[dbg.scala 536:41]
|
|
wire [14:0] _T_827 = _GEN_182 & _T_826; // @[dbg.scala 536:41]
|
|
wire [14:0] _T_828 = _T_820 | _T_827; // @[dbg.scala 535:101]
|
|
wire [7:0] _T_831 = _T_803 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_833 = {sb_axi_addr[2],2'h0}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_834 = 15'hf << _T_833; // @[dbg.scala 537:56]
|
|
wire [14:0] _GEN_183 = {{7'd0}, _T_831}; // @[dbg.scala 537:41]
|
|
wire [14:0] _T_835 = _GEN_183 & _T_834; // @[dbg.scala 537:41]
|
|
wire [14:0] _T_836 = _T_828 | _T_835; // @[dbg.scala 536:93]
|
|
wire [7:0] _T_839 = _T_810 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [14:0] _GEN_184 = {{7'd0}, _T_839}; // @[dbg.scala 537:90]
|
|
wire [14:0] _T_841 = _T_836 | _GEN_184; // @[dbg.scala 537:90]
|
|
wire [3:0] _GEN_185 = {{1'd0}, sb_axi_addr[2:0]}; // @[dbg.scala 556:94]
|
|
wire [6:0] _T_849 = 4'h8 * _GEN_185; // @[dbg.scala 556:94]
|
|
wire [63:0] _T_850 = io_sb_axi_r_bits_data >> _T_849; // @[dbg.scala 556:87]
|
|
wire [63:0] _T_851 = _T_850 & 64'hff; // @[dbg.scala 556:115]
|
|
wire [63:0] _T_852 = _T_789 & _T_851; // @[dbg.scala 556:54]
|
|
wire [4:0] _GEN_186 = {{3'd0}, sb_axi_addr[2:1]}; // @[dbg.scala 557:81]
|
|
wire [6:0] _T_858 = 5'h10 * _GEN_186; // @[dbg.scala 557:81]
|
|
wire [63:0] _T_859 = io_sb_axi_r_bits_data >> _T_858; // @[dbg.scala 557:73]
|
|
wire [63:0] _T_860 = _T_859 & 64'hffff; // @[dbg.scala 557:102]
|
|
wire [63:0] _T_861 = _T_797 & _T_860; // @[dbg.scala 557:40]
|
|
wire [63:0] _T_862 = _T_852 | _T_861; // @[dbg.scala 556:132]
|
|
wire [5:0] _GEN_187 = {{5'd0}, sb_axi_addr[2]}; // @[dbg.scala 558:81]
|
|
wire [6:0] _T_868 = 6'h20 * _GEN_187; // @[dbg.scala 558:81]
|
|
wire [63:0] _T_869 = io_sb_axi_r_bits_data >> _T_868; // @[dbg.scala 558:73]
|
|
wire [63:0] _T_870 = _T_869 & 64'hffffffff; // @[dbg.scala 558:99]
|
|
wire [63:0] _T_871 = _T_805 & _T_870; // @[dbg.scala 558:40]
|
|
wire [63:0] _T_872 = _T_862 | _T_871; // @[dbg.scala 557:121]
|
|
wire [63:0] _T_877 = _T_812 & io_sb_axi_r_bits_data; // @[dbg.scala 559:40]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 405:21]
|
|
assign io_dbg_core_rst_l = _T_17 | io_scan_mode; // @[dbg.scala 122:28]
|
|
assign io_dbg_halt_req = _T_412 ? dmcontrol_reg[31] : _GEN_90; // @[dbg.scala 294:25 dbg.scala 306:23 dbg.scala 311:23 dbg.scala 321:29 dbg.scala 326:23 dbg.scala 331:23 dbg.scala 336:23 dbg.scala 345:29 dbg.scala 352:25 dbg.scala 359:29 dbg.scala 364:29 dbg.scala 369:23]
|
|
assign io_dbg_resume_req = _T_412 ? 1'h0 : _GEN_93; // @[dbg.scala 295:25 dbg.scala 320:29]
|
|
assign io_dmi_reg_rdata = _T_599; // @[dbg.scala 388:21]
|
|
assign io_sb_axi_aw_valid = sb_abmem_cmd_awvalid | sb_cmd_awvalid; // @[dbg.scala 517:24]
|
|
assign io_sb_axi_aw_bits_addr = _T_760 ? abmem_addr : sbaddress0_reg; // @[dbg.scala 518:29]
|
|
assign io_sb_axi_aw_bits_region = sb_axi_addr[31:28]; // @[dbg.scala 523:29]
|
|
assign io_sb_axi_aw_bits_size = _T_760 ? sb_abmem_cmd_size[2:0] : sbcs_reg[19:17]; // @[dbg.scala 520:29]
|
|
assign io_sb_axi_w_valid = sb_abmem_cmd_wvalid | sb_cmd_wvalid; // @[dbg.scala 529:22]
|
|
assign io_sb_axi_w_bits_data = _T_809 | _T_813; // @[dbg.scala 530:27]
|
|
assign io_sb_axi_w_bits_strb = _T_841[7:0]; // @[dbg.scala 535:25]
|
|
assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 553:21]
|
|
assign io_sb_axi_ar_valid = sb_abmem_cmd_arvalid | _T_660; // @[dbg.scala 541:24]
|
|
assign io_sb_axi_ar_bits_addr = _T_760 ? abmem_addr : sbaddress0_reg; // @[dbg.scala 542:29]
|
|
assign io_sb_axi_ar_bits_region = sb_axi_addr[31:28]; // @[dbg.scala 547:29]
|
|
assign io_sb_axi_ar_bits_size = _T_760 ? sb_abmem_cmd_size[2:0] : sbcs_reg[19:17]; // @[dbg.scala 544:29]
|
|
assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 554:21]
|
|
assign io_dbg_dec_dma_dbg_ib_dbg_cmd_valid = _T_630 & io_dbg_dma_dma_dbg_ready; // @[dbg.scala 401:40]
|
|
assign io_dbg_dec_dma_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 403:40]
|
|
assign io_dbg_dec_dma_dbg_ib_dbg_cmd_type = _T_230 ? 2'h2 : _T_638; // @[dbg.scala 404:40]
|
|
assign io_dbg_dec_dma_dbg_ib_dbg_cmd_addr = _T_230 ? abmem_addr : _T_613; // @[dbg.scala 399:40]
|
|
assign io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 400:42]
|
|
assign io_dbg_dma_dbg_dma_bubble = _T_656 | _T_372; // @[dbg.scala 411:29]
|
|
assign dbg_state = _T_598; // @[dbg.scala 385:13]
|
|
assign dbg_state_en = _T_412 ? _T_419 : _GEN_89; // @[dbg.scala 291:25 dbg.scala 305:23 dbg.scala 310:23 dbg.scala 316:20 dbg.scala 325:23 dbg.scala 330:23 dbg.scala 335:23 dbg.scala 344:29 dbg.scala 349:25 dbg.scala 356:29 dbg.scala 368:20]
|
|
assign sb_state = _T_734; // @[dbg.scala 483:12]
|
|
assign sb_state_en = _T_675 ? _T_685 : _GEN_166; // @[dbg.scala 428:19 dbg.scala 436:25 dbg.scala 442:25 dbg.scala 448:19 dbg.scala 453:19 dbg.scala 457:19 dbg.scala 461:19 dbg.scala 465:19 dbg.scala 471:19 dbg.scala 477:19]
|
|
assign dmcontrol_reg = {_T_162,_T_160}; // @[dbg.scala 181:18]
|
|
assign sbaddress0_reg = _T_131; // @[dbg.scala 168:18]
|
|
assign sbcs_sbbusy_wren = _T_675 ? sb_state_en : _GEN_169; // @[dbg.scala 420:20 dbg.scala 429:24 dbg.scala 478:24]
|
|
assign sbcs_sberror_wren = _T_675 ? _T_688 : _GEN_167; // @[dbg.scala 422:21 dbg.scala 431:25 dbg.scala 437:25 dbg.scala 443:25 dbg.scala 466:25 dbg.scala 472:25]
|
|
assign sb_bus_rdata = _T_872 | _T_877; // @[dbg.scala 556:16]
|
|
assign sbaddress0_reg_wren1 = _T_675 ? 1'h0 : _GEN_171; // @[dbg.scala 424:24 dbg.scala 480:28]
|
|
assign dmstatus_reg = {_T_181,_T_177}; // @[dbg.scala 186:16]
|
|
assign dmstatus_havereset = ~dmstatus_haveresetn; // @[dbg.scala 192:23]
|
|
assign dmstatus_haveresetn = _T_206; // @[dbg.scala 202:23]
|
|
assign dmstatus_resumeack = _T_202; // @[dbg.scala 198:22]
|
|
assign dmstatus_unavail = dmcontrol_reg[1] | _T_196; // @[dbg.scala 195:20]
|
|
assign dmstatus_running = ~_T_199; // @[dbg.scala 196:20]
|
|
assign dmstatus_halted = _T_205; // @[dbg.scala 200:22]
|
|
assign abstractcs_busy_wren = _T_412 ? 1'h0 : _GEN_91; // @[dbg.scala 292:25 dbg.scala 318:29 dbg.scala 357:29]
|
|
assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 510:25]
|
|
assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 511:25]
|
|
assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 512:25]
|
|
assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 513:25]
|
|
assign sb_bus_rsp_error = _T_779 | _T_782; // @[dbg.scala 515:25]
|
|
assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 514:25]
|
|
assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 421:19 dbg.scala 430:23 dbg.scala 479:23]
|
|
assign abmem_addr = _T_411; // @[dbg.scala 282:16]
|
|
assign sbcs_reg = {_T_57,_T_52}; // @[dbg.scala 140:12]
|
|
assign execute_command = _T_361; // @[dbg.scala 256:19]
|
|
assign command_reg = {temp_command_reg_31_16,temp_command_reg_15_0}; // @[dbg.scala 264:15]
|
|
assign dbg_sb_bus_error = _T_412 ? 1'h0 : _GEN_97; // @[dbg.scala 296:25 dbg.scala 350:25]
|
|
assign command_wren = _T_333 & io_dmi_reg_wr_en; // @[dbg.scala 246:25]
|
|
assign command_din = {temp_command_din_31_16,temp_command_din_15_0}; // @[dbg.scala 255:19]
|
|
assign dbg_cmd_next_addr = _T_651[31:0]; // @[dbg.scala 409:24]
|
|
assign data0_reg_wren2 = _T_412 ? 1'h0 : _GEN_98; // @[dbg.scala 297:25 dbg.scala 351:25]
|
|
assign sb_abmem_cmd_done_en = _T_412 ? 1'h0 : _GEN_95; // @[dbg.scala 300:25 dbg.scala 341:29 dbg.scala 362:29]
|
|
assign sb_abmem_data_done_en = _T_412 ? 1'h0 : _GEN_96; // @[dbg.scala 301:25 dbg.scala 342:29 dbg.scala 363:29]
|
|
assign abmem_addr_external = ~abmem_addr_core_local; // @[dbg.scala 393:28]
|
|
assign sb_cmd_pending = _T_668 | _T_669; // @[dbg.scala 413:28]
|
|
assign sb_abmem_cmd_write = command_reg[16]; // @[dbg.scala 487:34]
|
|
assign abmem_addr_in_dccm_region = abmem_addr[31:28] == 4'hf; // @[dbg.scala 395:29]
|
|
assign abmem_addr_in_iccm_region = abmem_addr[31:28] == 4'he; // @[dbg.scala 396:29]
|
|
assign abmem_addr_in_pic_region = abmem_addr[31:28] == 4'hf; // @[dbg.scala 397:29]
|
|
assign sb_abmem_cmd_size = {{1'd0}, _T_737}; // @[dbg.scala 488:34]
|
|
assign dmcontrol_wren_Q = _T_163; // @[dbg.scala 183:21]
|
|
assign abstractcs_reg = {_T_313,_T_311}; // @[dbg.scala 238:20]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = command_wren; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = command_wren | _T_344; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = _T_376 | data0_reg_wren2; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = data1_reg_wren0 | data1_reg_wren1; // @[lib.scala 425:17]
|
|
assign dbg_nxtstate = _T_412 ? _T_415 : _GEN_88; // @[dbg.scala 290:25 dbg.scala 304:23 dbg.scala 309:23 dbg.scala 314:20 dbg.scala 324:23 dbg.scala 329:23 dbg.scala 334:23 dbg.scala 343:29 dbg.scala 348:25 dbg.scala 355:29 dbg.scala 367:20]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = io_dmi_reg_en; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
temp_sbcs_22 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
temp_sbcs_21 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
temp_sbcs_20 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
temp_sbcs_19_15 = _RAND_3[4:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
temp_sbcs_14_12 = _RAND_4[2:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
sbdata0_reg = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
sbdata1_reg = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_131 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
dm_temp = _RAND_8[3:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
dm_temp_0 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_163 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_202 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_205 = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
_T_206 = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
abs_temp_12 = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
abs_temp_10_8 = _RAND_15[2:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
abstractauto_reg = _RAND_16[1:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_361 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
temp_command_reg_31_16 = _RAND_18[15:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
temp_command_reg_15_0 = _RAND_19[15:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
data0_reg = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
_T_411 = _RAND_21[31:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
sb_abmem_cmd_done = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
sb_abmem_data_done = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
_T_598 = _RAND_24[3:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
_T_599 = _RAND_25[31:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
_T_734 = _RAND_26[3:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_22 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_21 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_20 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_19_15 = 5'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_14_12 = 3'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
sbdata0_reg = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
sbdata1_reg = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_131 = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
dm_temp = 4'h0;
|
|
end
|
|
if (io_dbg_rst_l) begin
|
|
dm_temp_0 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_163 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_202 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_205 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_206 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
abs_temp_12 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
abs_temp_10_8 = 3'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
abstractauto_reg = 2'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_361 = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_command_reg_31_16 = 16'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
temp_command_reg_15_0 = 16'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
data0_reg = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_411 = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
sb_abmem_cmd_done = 1'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
sb_abmem_data_done = 1'h0;
|
|
end
|
|
if (_T_597) begin
|
|
_T_598 = 4'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_599 = 32'h0;
|
|
end
|
|
if (dbg_dm_rst_l) begin
|
|
_T_734 = 4'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_22 <= 1'h0;
|
|
end else if (sbcs_sbbusyerror_wren) begin
|
|
temp_sbcs_22 <= sbcs_sbbusyerror_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_21 <= 1'h0;
|
|
end else if (sbcs_sbbusy_wren) begin
|
|
temp_sbcs_21 <= sbcs_sbbusy_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_20 <= 1'h0;
|
|
end else if (sbcs_wren) begin
|
|
temp_sbcs_20 <= io_dmi_reg_wdata[20];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_19_15 <= 5'h0;
|
|
end else if (sbcs_wren) begin
|
|
temp_sbcs_19_15 <= _T_43;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (sbcs_sberror_wren) begin
|
|
if (_T_675) begin
|
|
temp_sbcs_14_12 <= _T_692;
|
|
end else if (_T_693) begin
|
|
if (sbcs_unaligned) begin
|
|
temp_sbcs_14_12 <= 3'h3;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h4;
|
|
end
|
|
end else if (_T_702) begin
|
|
if (sbcs_unaligned) begin
|
|
temp_sbcs_14_12 <= 3'h3;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h4;
|
|
end
|
|
end else if (_T_711) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_713) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_719) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_721) begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end else if (_T_723) begin
|
|
temp_sbcs_14_12 <= 3'h2;
|
|
end else if (_T_726) begin
|
|
temp_sbcs_14_12 <= 3'h2;
|
|
end else begin
|
|
temp_sbcs_14_12 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
sbdata0_reg <= 32'h0;
|
|
end else if (sbdata0_reg_wren) begin
|
|
sbdata0_reg <= sbdata0_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
sbdata1_reg <= 32'h0;
|
|
end else if (sbdata1_reg_wren) begin
|
|
sbdata1_reg <= sbdata1_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_131 <= 32'h0;
|
|
end else if (sbaddress0_reg_wren) begin
|
|
_T_131 <= sbaddress0_reg_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
dm_temp <= 4'h0;
|
|
end else if (dmcontrol_wren) begin
|
|
dm_temp <= _T_154;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge io_dbg_rst_l) begin
|
|
if (io_dbg_rst_l) begin
|
|
dm_temp_0 <= 1'h0;
|
|
end else if (dmcontrol_wren) begin
|
|
dm_temp_0 <= io_dmi_reg_wdata[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_163 <= 1'h0;
|
|
end else begin
|
|
_T_163 <= _T_144 & io_dmi_reg_wr_en;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_202 <= 1'h0;
|
|
end else if (dmstatus_resumeack_wren) begin
|
|
_T_202 <= _T_184;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_205 <= 1'h0;
|
|
end else begin
|
|
_T_205 <= io_dec_tlu_dbg_halted & _T_203;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_206 <= 1'h0;
|
|
end else begin
|
|
_T_206 <= dmstatus_haveresetn_wren | _T_206;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else if (abstractcs_busy_wren) begin
|
|
if (_T_412) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else if (_T_422) begin
|
|
abs_temp_12 <= 1'h0;
|
|
end else begin
|
|
abs_temp_12 <= _T_428;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
abs_temp_10_8 <= 3'h0;
|
|
end else if (abstractcs_error_sel0) begin
|
|
abs_temp_10_8 <= 3'h1;
|
|
end else if (abstractcs_error_sel1) begin
|
|
abs_temp_10_8 <= 3'h2;
|
|
end else if (abstractcs_error_sel2) begin
|
|
abs_temp_10_8 <= 3'h3;
|
|
end else if (abstractcs_error_sel3) begin
|
|
abs_temp_10_8 <= 3'h4;
|
|
end else if (abstractcs_error_sel4) begin
|
|
abs_temp_10_8 <= 3'h5;
|
|
end else if (abstractcs_error_sel5) begin
|
|
abs_temp_10_8 <= 3'h7;
|
|
end else if (abstractcs_error_sel6) begin
|
|
abs_temp_10_8 <= _T_303;
|
|
end else begin
|
|
abs_temp_10_8 <= abstractcs_reg[10:8];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
abstractauto_reg <= 2'h0;
|
|
end else if (abstractauto_reg_wren) begin
|
|
abstractauto_reg <= io_dmi_reg_wdata[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_361 <= 1'h0;
|
|
end else begin
|
|
_T_361 <= command_wren | _T_331;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_command_reg_31_16 <= 16'h0;
|
|
end else if (command_wren) begin
|
|
temp_command_reg_31_16 <= command_din[31:16];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
temp_command_reg_15_0 <= 16'h0;
|
|
end else if (command_regno_wren) begin
|
|
temp_command_reg_15_0 <= command_din[15:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
data0_reg <= 32'h0;
|
|
end else if (data0_reg_wren) begin
|
|
data0_reg <= data0_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_411 <= 32'h0;
|
|
end else if (data1_reg_wren) begin
|
|
_T_411 <= data1_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (sb_abmem_cmd_done_en) begin
|
|
if (_T_412) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (_T_422) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (_T_428) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (_T_455) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (_T_477) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else if (_T_481) begin
|
|
sb_abmem_cmd_done <= 1'h0;
|
|
end else begin
|
|
sb_abmem_cmd_done <= _T_493;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (sb_abmem_data_done_en) begin
|
|
if (_T_412) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (_T_422) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (_T_428) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (_T_455) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (_T_477) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else if (_T_481) begin
|
|
sb_abmem_data_done <= 1'h0;
|
|
end else begin
|
|
sb_abmem_data_done <= _T_493;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge _T_597) begin
|
|
if (_T_597) begin
|
|
_T_598 <= 4'h0;
|
|
end else if (dbg_state_en) begin
|
|
if (_T_412) begin
|
|
if (_T_414) begin
|
|
_T_598 <= 4'h2;
|
|
end else begin
|
|
_T_598 <= 4'h1;
|
|
end
|
|
end else if (_T_422) begin
|
|
_T_598 <= 4'h2;
|
|
end else if (_T_428) begin
|
|
if (dmstatus_reg[9]) begin
|
|
if (resumereq) begin
|
|
_T_598 <= 4'h9;
|
|
end else if (_T_432) begin
|
|
_T_598 <= 4'h5;
|
|
end else begin
|
|
_T_598 <= 4'h3;
|
|
end
|
|
end else if (dmcontrol_reg[31]) begin
|
|
_T_598 <= 4'h1;
|
|
end else begin
|
|
_T_598 <= 4'h0;
|
|
end
|
|
end else if (_T_455) begin
|
|
if (_T_463) begin
|
|
_T_598 <= 4'h8;
|
|
end else begin
|
|
_T_598 <= 4'h4;
|
|
end
|
|
end else if (_T_477) begin
|
|
_T_598 <= 4'h8;
|
|
end else if (_T_481) begin
|
|
if (_T_209) begin
|
|
_T_598 <= 4'h8;
|
|
end else begin
|
|
_T_598 <= 4'h6;
|
|
end
|
|
end else if (_T_493) begin
|
|
_T_598 <= 4'h7;
|
|
end else if (_T_505) begin
|
|
_T_598 <= 4'h8;
|
|
end else if (_T_518) begin
|
|
_T_598 <= 4'h2;
|
|
end else begin
|
|
_T_598 <= 4'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_599 <= 32'h0;
|
|
end else if (io_dmi_reg_en) begin
|
|
_T_599 <= dmi_reg_rdata_din;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge dbg_dm_rst_l) begin
|
|
if (dbg_dm_rst_l) begin
|
|
_T_734 <= 4'h0;
|
|
end else if (sb_state_en) begin
|
|
if (_T_675) begin
|
|
if (sbdata0_reg_wren0) begin
|
|
_T_734 <= 4'h2;
|
|
end else begin
|
|
_T_734 <= 4'h1;
|
|
end
|
|
end else if (_T_693) begin
|
|
if (_T_694) begin
|
|
_T_734 <= 4'h9;
|
|
end else begin
|
|
_T_734 <= 4'h3;
|
|
end
|
|
end else if (_T_702) begin
|
|
if (_T_694) begin
|
|
_T_734 <= 4'h9;
|
|
end else begin
|
|
_T_734 <= 4'h4;
|
|
end
|
|
end else if (_T_711) begin
|
|
_T_734 <= 4'h7;
|
|
end else if (_T_713) begin
|
|
if (_T_714) begin
|
|
_T_734 <= 4'h8;
|
|
end else if (sb_bus_cmd_write_data) begin
|
|
_T_734 <= 4'h5;
|
|
end else begin
|
|
_T_734 <= 4'h6;
|
|
end
|
|
end else if (_T_719) begin
|
|
_T_734 <= 4'h8;
|
|
end else if (_T_721) begin
|
|
_T_734 <= 4'h8;
|
|
end else if (_T_723) begin
|
|
_T_734 <= 4'h9;
|
|
end else if (_T_726) begin
|
|
_T_734 <= 4'h9;
|
|
end else begin
|
|
_T_734 <= 4'h0;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
module exu_alu_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_dec_alu_dec_i0_alu_decode_d,
|
|
input io_dec_alu_dec_csr_ren_d,
|
|
input [11:0] io_dec_alu_dec_i0_br_immed_d,
|
|
output [30:0] io_dec_alu_exu_i0_pc_x,
|
|
input [31:0] io_csr_rddata_in,
|
|
input [30:0] io_dec_i0_pc_d,
|
|
input io_flush_upper_x,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input io_enable,
|
|
input io_i0_ap_clz,
|
|
input io_i0_ap_ctz,
|
|
input io_i0_ap_pcnt,
|
|
input io_i0_ap_sext_b,
|
|
input io_i0_ap_sext_h,
|
|
input io_i0_ap_min,
|
|
input io_i0_ap_max,
|
|
input io_i0_ap_pack,
|
|
input io_i0_ap_packu,
|
|
input io_i0_ap_packh,
|
|
input io_i0_ap_rol,
|
|
input io_i0_ap_ror,
|
|
input io_i0_ap_grev,
|
|
input io_i0_ap_gorc,
|
|
input io_i0_ap_zbb,
|
|
input io_i0_ap_sbset,
|
|
input io_i0_ap_sbclr,
|
|
input io_i0_ap_sbinv,
|
|
input io_i0_ap_sbext,
|
|
input io_i0_ap_land,
|
|
input io_i0_ap_lor,
|
|
input io_i0_ap_lxor,
|
|
input io_i0_ap_sll,
|
|
input io_i0_ap_srl,
|
|
input io_i0_ap_sra,
|
|
input io_i0_ap_beq,
|
|
input io_i0_ap_bne,
|
|
input io_i0_ap_blt,
|
|
input io_i0_ap_bge,
|
|
input io_i0_ap_add,
|
|
input io_i0_ap_sub,
|
|
input io_i0_ap_slt,
|
|
input io_i0_ap_unsign,
|
|
input io_i0_ap_jal,
|
|
input io_i0_ap_predict_t,
|
|
input io_i0_ap_predict_nt,
|
|
input io_i0_ap_csr_write,
|
|
input io_i0_ap_csr_imm,
|
|
input [31:0] io_a_in,
|
|
input [31:0] io_b_in,
|
|
input io_pp_in_valid,
|
|
input io_pp_in_bits_boffset,
|
|
input io_pp_in_bits_pc4,
|
|
input [1:0] io_pp_in_bits_hist,
|
|
input [11:0] io_pp_in_bits_toffset,
|
|
input io_pp_in_bits_br_error,
|
|
input io_pp_in_bits_br_start_error,
|
|
input io_pp_in_bits_pcall,
|
|
input io_pp_in_bits_pja,
|
|
input io_pp_in_bits_way,
|
|
input io_pp_in_bits_pret,
|
|
input [30:0] io_pp_in_bits_prett,
|
|
output [31:0] io_result_ff,
|
|
output io_flush_upper_out,
|
|
output io_flush_final_out,
|
|
output [30:0] io_flush_path_out,
|
|
output io_pred_correct_out,
|
|
output io_predict_p_out_valid,
|
|
output io_predict_p_out_bits_misp,
|
|
output io_predict_p_out_bits_ataken,
|
|
output io_predict_p_out_bits_boffset,
|
|
output io_predict_p_out_bits_pc4,
|
|
output [1:0] io_predict_p_out_bits_hist,
|
|
output [11:0] io_predict_p_out_bits_toffset,
|
|
output io_predict_p_out_bits_br_error,
|
|
output io_predict_p_out_bits_br_start_error,
|
|
output io_predict_p_out_bits_pcall,
|
|
output io_predict_p_out_bits_pja,
|
|
output io_predict_p_out_bits_way,
|
|
output io_predict_p_out_bits_pret
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire _T_1 = io_b_in[4:0] == 5'h1f; // @[exu_alu_ctl.scala 87:55]
|
|
wire ap_rev = io_i0_ap_grev & _T_1; // @[exu_alu_ctl.scala 87:39]
|
|
wire _T_4 = io_b_in[4:0] == 5'h18; // @[exu_alu_ctl.scala 88:55]
|
|
wire ap_rev8 = io_i0_ap_grev & _T_4; // @[exu_alu_ctl.scala 88:39]
|
|
wire _T_7 = io_b_in[4:0] == 5'h7; // @[exu_alu_ctl.scala 89:55]
|
|
wire ap_orc_b = io_i0_ap_gorc & _T_7; // @[exu_alu_ctl.scala 89:39]
|
|
wire _T_10 = io_b_in[4:0] == 5'h10; // @[exu_alu_ctl.scala 90:55]
|
|
wire ap_orc16 = io_i0_ap_gorc & _T_10; // @[exu_alu_ctl.scala 90:39]
|
|
reg [30:0] _T_14; // @[Reg.scala 27:20]
|
|
wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43]
|
|
reg [31:0] _T_18; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72]
|
|
wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72]
|
|
wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22]
|
|
wire _T_95 = io_i0_ap_land & _T_94; // @[exu_alu_ctl.scala 160:20]
|
|
wire [32:0] _T_98 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_99 = {1'h0,io_a_in}; // @[exu_alu_ctl.scala 160:67]
|
|
wire [31:0] _T_100 = io_b_in; // @[exu_alu_ctl.scala 160:85]
|
|
wire [32:0] _GEN_2 = {{1{_T_100[31]}},_T_100}; // @[exu_alu_ctl.scala 160:74]
|
|
wire [32:0] _T_156 = $signed(_T_99) & $signed(_GEN_2); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_173 = _T_95 ? $signed(_T_156) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_180 = $signed(_T_172) | $signed(_T_173); // @[Mux.scala 27:72]
|
|
wire _T_104 = io_i0_ap_lor & _T_94; // @[exu_alu_ctl.scala 161:20]
|
|
wire [32:0] _T_159 = $signed(_T_99) | $signed(_GEN_2); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_174 = _T_104 ? $signed(_T_159) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_182 = $signed(_T_180) | $signed(_T_174); // @[Mux.scala 27:72]
|
|
wire _T_113 = io_i0_ap_lxor & _T_94; // @[exu_alu_ctl.scala 162:20]
|
|
wire [32:0] _T_162 = $signed(_T_99) ^ $signed(_GEN_2); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_175 = _T_113 ? $signed(_T_162) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_184 = $signed(_T_182) | $signed(_T_175); // @[Mux.scala 27:72]
|
|
wire _T_121 = io_i0_ap_land & io_i0_ap_zbb; // @[exu_alu_ctl.scala 163:20]
|
|
wire [31:0] _T_128 = ~io_b_in; // @[exu_alu_ctl.scala 163:76]
|
|
wire [32:0] _GEN_5 = {{1{_T_128[31]}},_T_128}; // @[exu_alu_ctl.scala 163:74]
|
|
wire [32:0] _T_165 = $signed(_T_99) & $signed(_GEN_5); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_176 = _T_121 ? $signed(_T_165) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_186 = $signed(_T_184) | $signed(_T_176); // @[Mux.scala 27:72]
|
|
wire _T_131 = io_i0_ap_lor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 164:20]
|
|
wire [32:0] _T_168 = $signed(_T_99) | $signed(_GEN_5); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_177 = _T_131 ? $signed(_T_168) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_188 = $signed(_T_186) | $signed(_T_177); // @[Mux.scala 27:72]
|
|
wire _T_141 = io_i0_ap_lxor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 165:20]
|
|
wire [32:0] _T_171 = $signed(_T_99) ^ $signed(_GEN_5); // @[Mux.scala 27:72]
|
|
wire [32:0] _T_178 = _T_141 ? $signed(_T_171) : $signed(33'sh0); // @[Mux.scala 27:72]
|
|
wire [32:0] lout = $signed(_T_188) | $signed(_T_178); // @[Mux.scala 27:72]
|
|
wire _T_836 = io_i0_ap_sll | io_i0_ap_srl; // @[exu_alu_ctl.scala 293:44]
|
|
wire _T_837 = _T_836 | io_i0_ap_sra; // @[exu_alu_ctl.scala 293:59]
|
|
wire _T_840 = _T_837 | io_i0_ap_rol; // @[exu_alu_ctl.scala 293:92]
|
|
wire sel_shift = _T_840 | io_i0_ap_ror; // @[exu_alu_ctl.scala 293:101]
|
|
wire [31:0] _T_887 = sel_shift ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [30:0] _T_345 = io_a_in[31] ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
|
|
wire [30:0] _T_352 = io_i0_ap_sra ? _T_345 : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_353 = io_i0_ap_sll ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_354 = io_i0_ap_rol ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_355 = io_i0_ap_ror ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72]
|
|
wire [62:0] shift_extend = {_T_360,io_a_in}; // @[Cat.scala 29:58]
|
|
wire [5:0] _T_195 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
|
|
wire [5:0] _T_197 = 6'h20 - _T_195; // @[exu_alu_ctl.scala 179:41]
|
|
wire [5:0] _T_218 = io_i0_ap_sll ? _T_197 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_219 = io_i0_ap_srl ? _T_195 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_226 = _T_218 | _T_219; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_220 = io_i0_ap_sra ? _T_195 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_227 = _T_226 | _T_220; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_221 = io_i0_ap_rol ? _T_197 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_228 = _T_227 | _T_221; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_222 = io_i0_ap_ror ? _T_195 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_229 = _T_228 | _T_222; // @[Mux.scala 27:72]
|
|
wire [5:0] _T_225 = io_i0_ap_sbext ? _T_195 : 6'h0; // @[Mux.scala 27:72]
|
|
wire [5:0] shift_amount = _T_229 | _T_225; // @[Mux.scala 27:72]
|
|
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[exu_alu_ctl.scala 202:32]
|
|
wire [4:0] _T_238 = {io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll}; // @[Cat.scala 29:58]
|
|
wire [4:0] _T_240 = _T_238 & io_b_in[4:0]; // @[exu_alu_ctl.scala 189:73]
|
|
wire [62:0] _T_241 = 63'hffffffff << _T_240; // @[exu_alu_ctl.scala 189:39]
|
|
wire [31:0] shift_mask = _T_241[31:0]; // @[exu_alu_ctl.scala 189:14]
|
|
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[exu_alu_ctl.scala 204:34]
|
|
wire [31:0] _T_889 = _T_887 & sout; // @[exu_alu_ctl.scala 304:56]
|
|
wire [31:0] _T_890 = lout[31:0] | _T_889; // @[exu_alu_ctl.scala 304:31]
|
|
wire _T_841 = io_i0_ap_add | io_i0_ap_sub; // @[exu_alu_ctl.scala 294:44]
|
|
wire _T_843 = ~io_i0_ap_slt; // @[exu_alu_ctl.scala 294:71]
|
|
wire _T_844 = _T_841 & _T_843; // @[exu_alu_ctl.scala 294:69]
|
|
wire _T_845 = ~io_i0_ap_min; // @[exu_alu_ctl.scala 294:87]
|
|
wire _T_846 = _T_844 & _T_845; // @[exu_alu_ctl.scala 294:85]
|
|
wire _T_847 = ~io_i0_ap_max; // @[exu_alu_ctl.scala 294:97]
|
|
wire sel_adder = _T_846 & _T_847; // @[exu_alu_ctl.scala 294:95]
|
|
wire [31:0] _T_892 = sel_adder ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [32:0] _T_57 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_58 = ~io_b_in; // @[exu_alu_ctl.scala 146:74]
|
|
wire [32:0] _T_59 = {1'h0,_T_58}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_61 = _T_57 + _T_59; // @[exu_alu_ctl.scala 146:59]
|
|
wire [32:0] _T_62 = {32'h0,io_i0_ap_sub}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_64 = _T_61 + _T_62; // @[exu_alu_ctl.scala 146:84]
|
|
wire [32:0] _T_67 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
|
|
wire [32:0] _T_69 = _T_98 + _T_67; // @[exu_alu_ctl.scala 146:139]
|
|
wire [32:0] _T_72 = _T_69 + _T_62; // @[exu_alu_ctl.scala 146:164]
|
|
wire [32:0] aout = io_i0_ap_sub ? _T_64 : _T_72; // @[exu_alu_ctl.scala 146:14]
|
|
wire [31:0] _T_894 = _T_892 & aout[31:0]; // @[exu_alu_ctl.scala 305:28]
|
|
wire [31:0] _T_895 = _T_890 | _T_894; // @[exu_alu_ctl.scala 304:71]
|
|
wire _T_848 = io_i0_ap_jal | io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 295:44]
|
|
wire _T_849 = _T_848 | io_pp_in_bits_pja; // @[exu_alu_ctl.scala 295:66]
|
|
wire sel_pc = _T_849 | io_pp_in_bits_pret; // @[exu_alu_ctl.scala 295:86]
|
|
wire [31:0] _T_897 = sel_pc ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [12:0] _T_853 = {io_dec_alu_dec_i0_br_immed_d,1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_852 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_856 = _T_852[12:1] + _T_853[12:1]; // @[lib.scala 74:31]
|
|
wire _T_865 = ~_T_856[12]; // @[lib.scala 78:28]
|
|
wire _T_866 = _T_853[12] ^ _T_865; // @[lib.scala 78:26]
|
|
wire [18:0] _T_877 = _T_866 ? _T_852[31:13] : 19'h0; // @[Mux.scala 27:72]
|
|
wire _T_869 = ~_T_853[12]; // @[lib.scala 79:8]
|
|
wire _T_871 = _T_869 & _T_856[12]; // @[lib.scala 79:14]
|
|
wire [18:0] _T_859 = _T_852[31:13] + 19'h1; // @[lib.scala 75:27]
|
|
wire [18:0] _T_878 = _T_871 ? _T_859 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_880 = _T_877 | _T_878; // @[Mux.scala 27:72]
|
|
wire _T_875 = _T_853[12] & _T_865; // @[lib.scala 80:14]
|
|
wire [18:0] _T_862 = _T_852[31:13] - 19'h1; // @[lib.scala 76:27]
|
|
wire [18:0] _T_879 = _T_875 ? _T_862 : 19'h0; // @[Mux.scala 27:72]
|
|
wire [18:0] _T_881 = _T_880 | _T_879; // @[Mux.scala 27:72]
|
|
wire [31:0] pcout = {_T_881,_T_856[11:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_898 = _T_897 & pcout; // @[exu_alu_ctl.scala 306:28]
|
|
wire [31:0] _T_899 = _T_895 | _T_898; // @[exu_alu_ctl.scala 305:43]
|
|
wire [31:0] _T_901 = io_i0_ap_csr_write ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_902 = io_i0_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[exu_alu_ctl.scala 307:51]
|
|
wire [31:0] _T_903 = _T_901 & _T_902; // @[exu_alu_ctl.scala 307:34]
|
|
wire [31:0] _T_904 = _T_899 | _T_903; // @[exu_alu_ctl.scala 306:41]
|
|
wire _T_88 = ~io_i0_ap_unsign; // @[exu_alu_ctl.scala 154:30]
|
|
wire neg = aout[31]; // @[exu_alu_ctl.scala 153:34]
|
|
wire _T_75 = ~io_a_in[31]; // @[exu_alu_ctl.scala 149:14]
|
|
wire [31:0] bm = io_i0_ap_sub ? _T_58 : io_b_in; // @[exu_alu_ctl.scala 143:17]
|
|
wire _T_77 = ~bm[31]; // @[exu_alu_ctl.scala 149:29]
|
|
wire _T_78 = _T_75 & _T_77; // @[exu_alu_ctl.scala 149:27]
|
|
wire _T_80 = _T_78 & neg; // @[exu_alu_ctl.scala 149:37]
|
|
wire _T_83 = io_a_in[31] & bm[31]; // @[exu_alu_ctl.scala 149:66]
|
|
wire _T_85 = ~neg; // @[exu_alu_ctl.scala 149:78]
|
|
wire _T_86 = _T_83 & _T_85; // @[exu_alu_ctl.scala 149:76]
|
|
wire ov = _T_80 | _T_86; // @[exu_alu_ctl.scala 149:50]
|
|
wire _T_89 = neg ^ ov; // @[exu_alu_ctl.scala 154:54]
|
|
wire _T_90 = _T_88 & _T_89; // @[exu_alu_ctl.scala 154:47]
|
|
wire cout = aout[32]; // @[exu_alu_ctl.scala 147:18]
|
|
wire _T_91 = ~cout; // @[exu_alu_ctl.scala 154:84]
|
|
wire _T_92 = io_i0_ap_unsign & _T_91; // @[exu_alu_ctl.scala 154:82]
|
|
wire lt = _T_90 | _T_92; // @[exu_alu_ctl.scala 154:61]
|
|
wire slt_one = io_i0_ap_slt & lt; // @[exu_alu_ctl.scala 298:43]
|
|
wire [31:0] _T_905 = {31'h0,slt_one}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_906 = _T_904 | _T_905; // @[exu_alu_ctl.scala 307:59]
|
|
wire [31:0] _T_908 = io_i0_ap_sbext ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_910 = {31'h0,sout[0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_911 = _T_908 & _T_910; // @[exu_alu_ctl.scala 309:28]
|
|
wire [31:0] _T_912 = _T_906 | _T_911; // @[exu_alu_ctl.scala 308:56]
|
|
wire _T_547 = io_i0_ap_clz | io_i0_ap_ctz; // @[exu_alu_ctl.scala 221:52]
|
|
wire [5:0] _T_549 = _T_547 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_445 = io_i0_ap_clz ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [9:0] _T_416 = {io_a_in[0],io_a_in[1],io_a_in[2],io_a_in[3],io_a_in[4],io_a_in[5],io_a_in[6],io_a_in[7],io_a_in[8],io_a_in[9]}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_425 = {_T_416,io_a_in[10],io_a_in[11],io_a_in[12],io_a_in[13],io_a_in[14],io_a_in[15],io_a_in[16],io_a_in[17],io_a_in[18]}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_434 = {_T_425,io_a_in[19],io_a_in[20],io_a_in[21],io_a_in[22],io_a_in[23],io_a_in[24],io_a_in[25],io_a_in[26],io_a_in[27]}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_a_reverse_ff = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_444 = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_446 = io_i0_ap_ctz ? $signed(_T_444) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] bitmanip_lzd_in = $signed(_T_445) | $signed(_T_446); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_451 = $signed(_T_445) | $signed(_T_446); // @[exu_alu_ctl.scala 219:75]
|
|
wire _T_452 = _T_451 == 32'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_454 = bitmanip_lzd_in[31:1] == 31'h0; // @[exu_alu_ctl.scala 219:81]
|
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wire _T_456 = bitmanip_lzd_in[31:2] == 30'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_458 = bitmanip_lzd_in[31:3] == 29'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_460 = bitmanip_lzd_in[31:4] == 28'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_462 = bitmanip_lzd_in[31:5] == 27'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_464 = bitmanip_lzd_in[31:6] == 26'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_466 = bitmanip_lzd_in[31:7] == 25'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_468 = bitmanip_lzd_in[31:8] == 24'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_470 = bitmanip_lzd_in[31:9] == 23'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_472 = bitmanip_lzd_in[31:10] == 22'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_474 = bitmanip_lzd_in[31:11] == 21'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_476 = bitmanip_lzd_in[31:12] == 20'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_478 = bitmanip_lzd_in[31:13] == 19'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_480 = bitmanip_lzd_in[31:14] == 18'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_482 = bitmanip_lzd_in[31:15] == 17'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_484 = bitmanip_lzd_in[31:16] == 16'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_486 = bitmanip_lzd_in[31:17] == 15'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_488 = bitmanip_lzd_in[31:18] == 14'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_490 = bitmanip_lzd_in[31:19] == 13'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_492 = bitmanip_lzd_in[31:20] == 12'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_494 = bitmanip_lzd_in[31:21] == 11'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_496 = bitmanip_lzd_in[31:22] == 10'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_498 = bitmanip_lzd_in[31:23] == 9'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_500 = bitmanip_lzd_in[31:24] == 8'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_502 = bitmanip_lzd_in[31:25] == 7'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_504 = bitmanip_lzd_in[31:26] == 6'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_506 = bitmanip_lzd_in[31:27] == 5'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_508 = bitmanip_lzd_in[31:28] == 4'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_510 = bitmanip_lzd_in[31:29] == 3'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_512 = bitmanip_lzd_in[31:30] == 2'h0; // @[exu_alu_ctl.scala 219:81]
|
|
wire _T_514 = ~bitmanip_lzd_in[31]; // @[exu_alu_ctl.scala 219:81]
|
|
wire [1:0] _T_516 = _T_512 ? 2'h2 : {{1'd0}, _T_514}; // @[Mux.scala 98:16]
|
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wire [1:0] _T_517 = _T_510 ? 2'h3 : _T_516; // @[Mux.scala 98:16]
|
|
wire [2:0] _T_518 = _T_508 ? 3'h4 : {{1'd0}, _T_517}; // @[Mux.scala 98:16]
|
|
wire [2:0] _T_519 = _T_506 ? 3'h5 : _T_518; // @[Mux.scala 98:16]
|
|
wire [2:0] _T_520 = _T_504 ? 3'h6 : _T_519; // @[Mux.scala 98:16]
|
|
wire [2:0] _T_521 = _T_502 ? 3'h7 : _T_520; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_522 = _T_500 ? 4'h8 : {{1'd0}, _T_521}; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_523 = _T_498 ? 4'h9 : _T_522; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_524 = _T_496 ? 4'ha : _T_523; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_525 = _T_494 ? 4'hb : _T_524; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_526 = _T_492 ? 4'hc : _T_525; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_527 = _T_490 ? 4'hd : _T_526; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_528 = _T_488 ? 4'he : _T_527; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_529 = _T_486 ? 4'hf : _T_528; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_530 = _T_484 ? 5'h10 : {{1'd0}, _T_529}; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_531 = _T_482 ? 5'h11 : _T_530; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_532 = _T_480 ? 5'h12 : _T_531; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_533 = _T_478 ? 5'h13 : _T_532; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_534 = _T_476 ? 5'h14 : _T_533; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_535 = _T_474 ? 5'h15 : _T_534; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_536 = _T_472 ? 5'h16 : _T_535; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_537 = _T_470 ? 5'h17 : _T_536; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_538 = _T_468 ? 5'h18 : _T_537; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_539 = _T_466 ? 5'h19 : _T_538; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_540 = _T_464 ? 5'h1a : _T_539; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_541 = _T_462 ? 5'h1b : _T_540; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_542 = _T_460 ? 5'h1c : _T_541; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_543 = _T_458 ? 5'h1d : _T_542; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_544 = _T_456 ? 5'h1e : _T_543; // @[Mux.scala 98:16]
|
|
wire [4:0] _T_545 = _T_454 ? 5'h1f : _T_544; // @[Mux.scala 98:16]
|
|
wire [5:0] bitmanip_dw_lzd_enc = _T_452 ? 6'h20 : {{1'd0}, _T_545}; // @[Mux.scala 98:16]
|
|
wire [5:0] _GEN_8 = {{5'd0}, bitmanip_dw_lzd_enc[5]}; // @[exu_alu_ctl.scala 221:62]
|
|
wire [5:0] _T_551 = _T_549 & _GEN_8; // @[exu_alu_ctl.scala 221:62]
|
|
wire _T_553 = ~bitmanip_dw_lzd_enc[5]; // @[exu_alu_ctl.scala 221:96]
|
|
wire [4:0] _T_555 = _T_553 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
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wire [4:0] _T_557 = _T_555 & bitmanip_dw_lzd_enc[4:0]; // @[exu_alu_ctl.scala 221:121]
|
|
wire [10:0] bitmanip_clz_ctz_result = {_T_551,_T_557}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_914 = {26'h0,bitmanip_clz_ctz_result[5:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_915 = _T_912 | _T_914; // @[exu_alu_ctl.scala 309:56]
|
|
wire [5:0] _T_559 = io_i0_ap_pcnt ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_592 = io_a_in[0] + io_a_in[1]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_594 = io_a_in[2] + io_a_in[3]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_596 = _T_592 + _T_594; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_598 = io_a_in[4] + io_a_in[5]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_600 = io_a_in[6] + io_a_in[7]; // @[Bitwise.scala 47:55]
|
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wire [2:0] _T_602 = _T_598 + _T_600; // @[Bitwise.scala 47:55]
|
|
wire [3:0] _T_604 = _T_596 + _T_602; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_606 = io_a_in[8] + io_a_in[9]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_608 = io_a_in[10] + io_a_in[11]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_610 = _T_606 + _T_608; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_612 = io_a_in[12] + io_a_in[13]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_614 = io_a_in[14] + io_a_in[15]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_616 = _T_612 + _T_614; // @[Bitwise.scala 47:55]
|
|
wire [3:0] _T_618 = _T_610 + _T_616; // @[Bitwise.scala 47:55]
|
|
wire [4:0] _T_620 = _T_604 + _T_618; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_622 = io_a_in[16] + io_a_in[17]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_624 = io_a_in[18] + io_a_in[19]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_626 = _T_622 + _T_624; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_628 = io_a_in[20] + io_a_in[21]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_630 = io_a_in[22] + io_a_in[23]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_632 = _T_628 + _T_630; // @[Bitwise.scala 47:55]
|
|
wire [3:0] _T_634 = _T_626 + _T_632; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_636 = io_a_in[24] + io_a_in[25]; // @[Bitwise.scala 47:55]
|
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wire [1:0] _T_638 = io_a_in[26] + io_a_in[27]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_640 = _T_636 + _T_638; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_642 = io_a_in[28] + io_a_in[29]; // @[Bitwise.scala 47:55]
|
|
wire [1:0] _T_644 = io_a_in[30] + io_a_in[31]; // @[Bitwise.scala 47:55]
|
|
wire [2:0] _T_646 = _T_642 + _T_644; // @[Bitwise.scala 47:55]
|
|
wire [3:0] _T_648 = _T_640 + _T_646; // @[Bitwise.scala 47:55]
|
|
wire [4:0] _T_650 = _T_634 + _T_648; // @[Bitwise.scala 47:55]
|
|
wire [5:0] _T_652 = _T_620 + _T_650; // @[Bitwise.scala 47:55]
|
|
wire [5:0] bitmanip_pcnt_result = _T_559 & _T_652; // @[exu_alu_ctl.scala 224:50]
|
|
wire [31:0] _T_917 = {26'h0,bitmanip_pcnt_result}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_918 = _T_915 | _T_917; // @[exu_alu_ctl.scala 310:52]
|
|
wire [23:0] _T_656 = io_a_in[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_658 = {_T_656,io_a_in[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_664 = io_i0_ap_sext_b ? _T_658 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [15:0] _T_661 = io_a_in[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_663 = {_T_661,io_a_in[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_665 = io_i0_ap_sext_h ? _T_663 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] bitmanip_sext_result = _T_664 | _T_665; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_920 = _T_918 | bitmanip_sext_result; // @[exu_alu_ctl.scala 311:52]
|
|
wire bitmanip_minmax_sel = io_i0_ap_min | io_i0_ap_max; // @[exu_alu_ctl.scala 233:46]
|
|
wire ge = ~lt; // @[exu_alu_ctl.scala 155:29]
|
|
wire bitmanip_minmax_sel_a = ge ^ io_i0_ap_min; // @[exu_alu_ctl.scala 235:43]
|
|
wire _T_667 = bitmanip_minmax_sel & bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 238:26]
|
|
wire [31:0] _T_677 = _T_667 ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire _T_668 = ~bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 239:28]
|
|
wire _T_669 = bitmanip_minmax_sel & _T_668; // @[exu_alu_ctl.scala 239:26]
|
|
wire [31:0] _T_678 = _T_669 ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_921 = $signed(_T_677) | $signed(_T_678); // @[exu_alu_ctl.scala 313:27]
|
|
wire [31:0] _T_922 = _T_920 | _T_921; // @[exu_alu_ctl.scala 312:35]
|
|
wire [31:0] _T_684 = io_i0_ap_pack ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_687 = {io_b_in[15:0],io_a_in[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_pack_result = _T_684 & _T_687; // @[exu_alu_ctl.scala 244:50]
|
|
wire [31:0] _T_924 = _T_922 | bitmanip_pack_result; // @[exu_alu_ctl.scala 313:35]
|
|
wire [31:0] _T_689 = io_i0_ap_packu ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_692 = {io_b_in[31:16],io_a_in[31:16]}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_packu_result = _T_689 & _T_692; // @[exu_alu_ctl.scala 245:50]
|
|
wire [31:0] _T_926 = _T_924 | bitmanip_packu_result; // @[exu_alu_ctl.scala 314:35]
|
|
wire [31:0] _T_694 = io_i0_ap_packh ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_698 = {16'h0,io_b_in[7:0],io_a_in[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_packh_result = _T_694 & _T_698; // @[exu_alu_ctl.scala 246:50]
|
|
wire [31:0] _T_928 = _T_926 | bitmanip_packh_result; // @[exu_alu_ctl.scala 315:35]
|
|
wire [31:0] _T_700 = ap_rev ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] bitmanip_rev_result = _T_700 & bitmanip_a_reverse_ff; // @[exu_alu_ctl.scala 252:48]
|
|
wire [31:0] _T_930 = _T_928 | bitmanip_rev_result; // @[exu_alu_ctl.scala 316:35]
|
|
wire [31:0] _T_765 = ap_rev8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_772 = {io_a_in[7:0],io_a_in[15:8],io_a_in[23:16],io_a_in[31:24]}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_rev8_result = _T_765 & _T_772; // @[exu_alu_ctl.scala 254:50]
|
|
wire [31:0] _T_932 = _T_930 | bitmanip_rev8_result; // @[exu_alu_ctl.scala 317:35]
|
|
wire [31:0] _T_774 = ap_orc_b ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_788 = |io_a_in[31:24]; // @[exu_alu_ctl.scala 279:117]
|
|
wire [7:0] _T_790 = _T_788 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_784 = |io_a_in[23:16]; // @[exu_alu_ctl.scala 279:117]
|
|
wire [7:0] _T_786 = _T_784 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_780 = |io_a_in[15:8]; // @[exu_alu_ctl.scala 279:117]
|
|
wire [7:0] _T_782 = _T_780 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_776 = |io_a_in[7:0]; // @[exu_alu_ctl.scala 279:117]
|
|
wire [7:0] _T_778 = _T_776 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_793 = {_T_790,_T_786,_T_782,_T_778}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_orc_b_result = _T_774 & _T_793; // @[exu_alu_ctl.scala 279:50]
|
|
wire [31:0] _T_934 = _T_932 | bitmanip_orc_b_result; // @[exu_alu_ctl.scala 318:35]
|
|
wire [31:0] _T_795 = ap_orc16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_798 = io_a_in[31:16] | io_a_in[15:0]; // @[exu_alu_ctl.scala 281:71]
|
|
wire [31:0] _T_802 = {_T_798,_T_798}; // @[Cat.scala 29:58]
|
|
wire [31:0] bitmanip_orc16_result = _T_795 & _T_802; // @[exu_alu_ctl.scala 281:50]
|
|
wire [31:0] _T_936 = _T_934 | bitmanip_orc16_result; // @[exu_alu_ctl.scala 319:35]
|
|
wire [62:0] bitmanip_sb_1hot = 63'h1 << io_b_in[4:0]; // @[exu_alu_ctl.scala 285:53]
|
|
wire [31:0] _T_805 = bitmanip_sb_1hot[31:0]; // @[exu_alu_ctl.scala 288:53]
|
|
wire [31:0] _T_820 = $signed(io_a_in) | $signed(_T_805); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_827 = io_i0_ap_sbset ? $signed(_T_820) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_811 = ~_T_805; // @[exu_alu_ctl.scala 289:29]
|
|
wire [31:0] _T_823 = $signed(io_a_in) & $signed(_T_811); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_828 = io_i0_ap_sbclr ? $signed(_T_823) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_831 = $signed(_T_827) | $signed(_T_828); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_826 = $signed(io_a_in) ^ $signed(_T_805); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_829 = io_i0_ap_sbinv ? $signed(_T_826) : $signed(32'sh0); // @[Mux.scala 27:72]
|
|
wire [31:0] _T_937 = $signed(_T_831) | $signed(_T_829); // @[exu_alu_ctl.scala 321:21]
|
|
wire [31:0] result = _T_936 | _T_937; // @[exu_alu_ctl.scala 320:35]
|
|
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[exu_alu_ctl.scala 151:38]
|
|
wire ne = ~eq; // @[exu_alu_ctl.scala 152:29]
|
|
wire _T_941 = io_i0_ap_beq & eq; // @[exu_alu_ctl.scala 335:43]
|
|
wire _T_942 = io_i0_ap_bne & ne; // @[exu_alu_ctl.scala 335:65]
|
|
wire _T_943 = _T_941 | _T_942; // @[exu_alu_ctl.scala 335:49]
|
|
wire _T_944 = io_i0_ap_blt & lt; // @[exu_alu_ctl.scala 335:94]
|
|
wire _T_945 = _T_943 | _T_944; // @[exu_alu_ctl.scala 335:78]
|
|
wire _T_946 = io_i0_ap_bge & ge; // @[exu_alu_ctl.scala 335:116]
|
|
wire _T_947 = _T_945 | _T_946; // @[exu_alu_ctl.scala 335:100]
|
|
wire actual_taken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 335:122]
|
|
wire _T_948 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_nt; // @[exu_alu_ctl.scala 340:61]
|
|
wire _T_949 = ~actual_taken; // @[exu_alu_ctl.scala 340:85]
|
|
wire _T_950 = _T_948 & _T_949; // @[exu_alu_ctl.scala 340:83]
|
|
wire _T_951 = ~sel_pc; // @[exu_alu_ctl.scala 340:101]
|
|
wire _T_952 = _T_950 & _T_951; // @[exu_alu_ctl.scala 340:99]
|
|
wire _T_953 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_t; // @[exu_alu_ctl.scala 340:145]
|
|
wire _T_954 = _T_953 & actual_taken; // @[exu_alu_ctl.scala 340:167]
|
|
wire _T_956 = _T_954 & _T_951; // @[exu_alu_ctl.scala 340:183]
|
|
wire _T_963 = io_i0_ap_predict_t & _T_949; // @[exu_alu_ctl.scala 345:48]
|
|
wire _T_964 = io_i0_ap_predict_nt & actual_taken; // @[exu_alu_ctl.scala 345:88]
|
|
wire cond_mispredict = _T_963 | _T_964; // @[exu_alu_ctl.scala 345:65]
|
|
wire _T_966 = io_pp_in_bits_prett != aout[31:1]; // @[exu_alu_ctl.scala 348:72]
|
|
wire target_mispredict = io_pp_in_bits_pret & _T_966; // @[exu_alu_ctl.scala 348:49]
|
|
wire _T_967 = io_i0_ap_jal | cond_mispredict; // @[exu_alu_ctl.scala 350:45]
|
|
wire _T_968 = _T_967 | target_mispredict; // @[exu_alu_ctl.scala 350:63]
|
|
wire _T_969 = _T_968 & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 350:84]
|
|
wire _T_970 = ~io_flush_upper_x; // @[exu_alu_ctl.scala 350:119]
|
|
wire _T_971 = _T_969 & _T_970; // @[exu_alu_ctl.scala 350:117]
|
|
wire _T_972 = ~io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 350:141]
|
|
wire _T_982 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:44]
|
|
wire _T_984 = ~io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:73]
|
|
wire _T_985 = _T_984 & actual_taken; // @[exu_alu_ctl.scala 355:96]
|
|
wire _T_986 = _T_982 | _T_985; // @[exu_alu_ctl.scala 355:70]
|
|
wire _T_988 = ~io_pp_in_bits_hist[1]; // @[exu_alu_ctl.scala 356:6]
|
|
wire _T_990 = _T_988 & _T_949; // @[exu_alu_ctl.scala 356:29]
|
|
wire _T_992 = io_pp_in_bits_hist[1] & actual_taken; // @[exu_alu_ctl.scala 356:72]
|
|
wire _T_993 = _T_990 | _T_992; // @[exu_alu_ctl.scala 356:47]
|
|
wire _T_997 = _T_970 & _T_972; // @[exu_alu_ctl.scala 359:56]
|
|
wire _T_998 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 359:103]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
assign io_dec_alu_exu_i0_pc_x = _T_14; // @[exu_alu_ctl.scala 133:26]
|
|
assign io_result_ff = _T_18; // @[exu_alu_ctl.scala 135:16]
|
|
assign io_flush_upper_out = _T_971 & _T_972; // @[exu_alu_ctl.scala 350:26]
|
|
assign io_flush_final_out = _T_971 | io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 351:26]
|
|
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[exu_alu_ctl.scala 342:22]
|
|
assign io_pred_correct_out = _T_952 | _T_956; // @[exu_alu_ctl.scala 340:26]
|
|
assign io_predict_p_out_valid = io_pp_in_valid; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_misp = _T_997 & _T_998; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 359:35]
|
|
assign io_predict_p_out_bits_ataken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 360:35]
|
|
assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_hist = {_T_986,_T_993}; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 361:35]
|
|
assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 358:30]
|
|
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 358:30]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_14 = _RAND_0[30:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_18 = _RAND_1[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_14 = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_18 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14 <= 31'h0;
|
|
end else if (io_enable) begin
|
|
_T_14 <= io_dec_i0_pc_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_18 <= 32'h0;
|
|
end else if (_T_15) begin
|
|
_T_18 <= result;
|
|
end
|
|
end
|
|
endmodule
|
|
module exu_mul_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_mul_p_valid,
|
|
input io_mul_p_bits_rs1_sign,
|
|
input io_mul_p_bits_rs2_sign,
|
|
input io_mul_p_bits_low,
|
|
input [31:0] io_rs1_in,
|
|
input [31:0] io_rs2_in,
|
|
output [31:0] io_result_x
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [63:0] _RAND_1;
|
|
reg [63:0] _RAND_2;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 449:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 449:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 449:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 449:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44]
|
|
wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[exu_mul_ctl.scala 123:71]
|
|
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44]
|
|
wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[exu_mul_ctl.scala 124:71]
|
|
reg low_x; // @[Reg.scala 27:20]
|
|
reg [32:0] rs1_x; // @[Reg.scala 27:20]
|
|
reg [32:0] rs2_x; // @[Reg.scala 27:20]
|
|
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20]
|
|
wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46]
|
|
wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_39763 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_39764 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762,_T_39763}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_39766 = _T_39764 & prod_x[63:32]; // @[exu_mul_ctl.scala 388:54]
|
|
wire [7:0] _T_39771 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_39772 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 449:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 449:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 451:18]
|
|
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 452:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 451:18]
|
|
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 452:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
low_x = _RAND_0[0:0];
|
|
_RAND_1 = {2{`RANDOM}};
|
|
rs1_x = _RAND_1[32:0];
|
|
_RAND_2 = {2{`RANDOM}};
|
|
rs2_x = _RAND_2[32:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
low_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rs1_x = 33'sh0;
|
|
end
|
|
if (reset) begin
|
|
rs2_x = 33'sh0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
low_x <= 1'h0;
|
|
end else if (io_mul_p_valid) begin
|
|
low_x <= io_mul_p_bits_low;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rs1_x <= 33'sh0;
|
|
end else if (io_mul_p_valid) begin
|
|
rs1_x <= rs1_ext_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rs2_x <= 33'sh0;
|
|
end else if (io_mul_p_valid) begin
|
|
rs2_x <= rs2_ext_in;
|
|
end
|
|
end
|
|
endmodule
|
|
module exu_div_cls(
|
|
input [32:0] io_operand,
|
|
output [4:0] io_cls
|
|
);
|
|
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 950:63]
|
|
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
|
|
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
|
|
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
|
|
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
|
|
wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 952:25]
|
|
wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 953:76]
|
|
wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
|
|
wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
|
|
wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
|
|
wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 952:44]
|
|
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 954:25]
|
|
endmodule
|
|
module exu_div_new_4bit_fullshortq(
|
|
input clock,
|
|
input reset,
|
|
input io_cancel,
|
|
input io_valid_in,
|
|
input io_signed_in,
|
|
input io_rem_in,
|
|
input [31:0] io_dividend_in,
|
|
input [31:0] io_divisor_in,
|
|
output [31:0] io_data_out,
|
|
output io_valid_out
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [63:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [63:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 913:31]
|
|
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 913:31]
|
|
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 916:31]
|
|
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 916:31]
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire _T = ~io_cancel; // @[exu_div_ctl.scala 776:44]
|
|
wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 776:42]
|
|
wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 777:35]
|
|
reg [2:0] control_ff; // @[Reg.scala 27:20]
|
|
wire _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 777:48]
|
|
wire _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 777:80]
|
|
wire _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 777:96]
|
|
wire _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 777:65]
|
|
wire _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 777:133]
|
|
wire _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 777:181]
|
|
wire _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 777:150]
|
|
wire _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 777:218]
|
|
wire _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 777:250]
|
|
wire _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 777:235]
|
|
wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58]
|
|
reg [32:0] b_ff1; // @[Reg.scala 27:20]
|
|
wire [37:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58]
|
|
wire _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 781:54]
|
|
reg valid_ff; // @[Reg.scala 27:20]
|
|
wire by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 781:40]
|
|
reg [31:0] a_ff; // @[Reg.scala 27:20]
|
|
wire _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 783:37]
|
|
wire _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 783:60]
|
|
wire _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 783:46]
|
|
wire _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 783:71]
|
|
wire _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 783:69]
|
|
wire _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 783:87]
|
|
wire _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 783:85]
|
|
wire _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 783:95]
|
|
wire _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 783:106]
|
|
wire _T_36 = a_ff == 32'h0; // @[exu_div_ctl.scala 784:18]
|
|
wire _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 784:27]
|
|
wire _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 784:43]
|
|
wire _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 784:53]
|
|
wire _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 784:64]
|
|
wire smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 783:120]
|
|
reg [6:0] count_ff; // @[Reg.scala 27:20]
|
|
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 785:42]
|
|
reg shortq_enable_ff; // @[Reg.scala 27:20]
|
|
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 785:45]
|
|
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 786:43]
|
|
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 786:54]
|
|
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 786:66]
|
|
reg finish_ff; // @[Reg.scala 27:20]
|
|
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 786:82]
|
|
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 787:45]
|
|
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 787:72]
|
|
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 787:60]
|
|
wire finish = finish_raw & _T; // @[exu_div_ctl.scala 788:41]
|
|
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 789:40]
|
|
wire _T_52 = ~finish; // @[exu_div_ctl.scala 789:59]
|
|
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 789:57]
|
|
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 789:69]
|
|
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 789:67]
|
|
wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 789:80]
|
|
wire [6:0] _T_1394 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1395 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_1397 = _T_1394 - _T_1395; // @[exu_div_ctl.scala 921:43]
|
|
wire [6:0] dw_shortq_raw = _T_1397 + 7'h1; // @[exu_div_ctl.scala 921:63]
|
|
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 922:28]
|
|
wire _T_1403 = ~shortq[5]; // @[exu_div_ctl.scala 923:37]
|
|
wire _T_1404 = valid_ff & _T_1403; // @[exu_div_ctl.scala 923:35]
|
|
wire _T_1406 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 923:64]
|
|
wire _T_1407 = ~_T_1406; // @[exu_div_ctl.scala 923:50]
|
|
wire _T_1408 = _T_1404 & _T_1407; // @[exu_div_ctl.scala 923:48]
|
|
wire shortq_enable = _T_1408 & _T; // @[exu_div_ctl.scala 923:79]
|
|
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 789:95]
|
|
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 789:93]
|
|
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
|
wire [6:0] _T_62 = count_ff + 7'h4; // @[exu_div_ctl.scala 790:63]
|
|
reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
|
|
wire [6:0] _T_63 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
|
|
wire [6:0] _T_65 = _T_62 + _T_63; // @[exu_div_ctl.scala 790:74]
|
|
wire [6:0] count_in = _T_60 & _T_65; // @[exu_div_ctl.scala 790:51]
|
|
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 791:43]
|
|
wire _T_66 = ~shortq_enable_ff; // @[exu_div_ctl.scala 792:47]
|
|
wire a_shift = running_state & _T_66; // @[exu_div_ctl.scala 792:45]
|
|
wire [32:0] _T_68 = control_ff[2] ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
|
|
wire [64:0] _T_70 = {_T_68,a_ff}; // @[Cat.scala 29:58]
|
|
wire [95:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 793:74]
|
|
wire [95:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 793:74]
|
|
wire _T_72 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 794:61]
|
|
wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 794:42]
|
|
wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 794:40]
|
|
wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 796:30]
|
|
wire _T_78 = _T_76 & _T_30; // @[exu_div_ctl.scala 796:40]
|
|
wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 796:50]
|
|
reg by_zero_case_ff; // @[Reg.scala 27:20]
|
|
wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 796:92]
|
|
wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 796:90]
|
|
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 797:43]
|
|
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 798:54]
|
|
wire _T_83 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 799:40]
|
|
wire r_sign_sel = _T_83 & _T_28; // @[exu_div_ctl.scala 799:59]
|
|
reg [32:0] r_ff; // @[Reg.scala 27:20]
|
|
wire [37:0] _T_287 = {r_ff[32],r_ff,a_ff[31:28]}; // @[Cat.scala 29:58]
|
|
wire [37:0] _T_289 = {b_ff[34:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [37:0] _T_291 = _T_287 + _T_289; // @[exu_div_ctl.scala 815:67]
|
|
wire [37:0] _T_293 = {b_ff[35:0],2'h0}; // @[Cat.scala 29:58]
|
|
wire [37:0] _T_295 = _T_291 + _T_293; // @[exu_div_ctl.scala 815:94]
|
|
wire [37:0] _T_297 = {b_ff[36:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [37:0] _T_299 = _T_295 + _T_297; // @[exu_div_ctl.scala 815:121]
|
|
wire [37:0] adder15_out = _T_299 + b_ff; // @[exu_div_ctl.scala 815:143]
|
|
wire _T_302 = ~adder15_out[37]; // @[exu_div_ctl.scala 818:6]
|
|
wire _T_303 = _T_302 ^ control_ff[2]; // @[exu_div_ctl.scala 818:23]
|
|
wire _T_305 = a_ff[27:0] == 28'h0; // @[exu_div_ctl.scala 818:58]
|
|
wire _T_306 = adder15_out == 38'h0; // @[exu_div_ctl.scala 818:82]
|
|
wire _T_307 = _T_305 & _T_306; // @[exu_div_ctl.scala 818:67]
|
|
wire _T_308 = _T_303 | _T_307; // @[exu_div_ctl.scala 818:43]
|
|
wire _T_310 = ~_T_299[37]; // @[exu_div_ctl.scala 819:6]
|
|
wire _T_311 = _T_310 ^ control_ff[2]; // @[exu_div_ctl.scala 819:23]
|
|
wire _T_314 = _T_299 == 38'h0; // @[exu_div_ctl.scala 819:82]
|
|
wire _T_315 = _T_305 & _T_314; // @[exu_div_ctl.scala 819:67]
|
|
wire _T_316 = _T_311 | _T_315; // @[exu_div_ctl.scala 819:43]
|
|
wire [37:0] adder13_out = _T_295 + b_ff; // @[exu_div_ctl.scala 813:121]
|
|
wire _T_318 = ~adder13_out[37]; // @[exu_div_ctl.scala 820:6]
|
|
wire _T_319 = _T_318 ^ control_ff[2]; // @[exu_div_ctl.scala 820:23]
|
|
wire _T_322 = adder13_out == 38'h0; // @[exu_div_ctl.scala 820:82]
|
|
wire _T_323 = _T_305 & _T_322; // @[exu_div_ctl.scala 820:67]
|
|
wire _T_324 = _T_319 | _T_323; // @[exu_div_ctl.scala 820:43]
|
|
wire _T_326 = ~_T_295[37]; // @[exu_div_ctl.scala 821:6]
|
|
wire _T_327 = _T_326 ^ control_ff[2]; // @[exu_div_ctl.scala 821:23]
|
|
wire _T_330 = _T_295 == 38'h0; // @[exu_div_ctl.scala 821:82]
|
|
wire _T_331 = _T_305 & _T_330; // @[exu_div_ctl.scala 821:67]
|
|
wire _T_332 = _T_327 | _T_331; // @[exu_div_ctl.scala 821:43]
|
|
wire [37:0] _T_239 = _T_291 + _T_297; // @[exu_div_ctl.scala 811:94]
|
|
wire [37:0] adder11_out = _T_239 + b_ff; // @[exu_div_ctl.scala 811:116]
|
|
wire _T_334 = ~adder11_out[37]; // @[exu_div_ctl.scala 822:6]
|
|
wire _T_335 = _T_334 ^ control_ff[2]; // @[exu_div_ctl.scala 822:23]
|
|
wire _T_338 = adder11_out == 38'h0; // @[exu_div_ctl.scala 822:82]
|
|
wire _T_339 = _T_305 & _T_338; // @[exu_div_ctl.scala 822:67]
|
|
wire _T_340 = _T_335 | _T_339; // @[exu_div_ctl.scala 822:43]
|
|
wire _T_342 = ~_T_239[37]; // @[exu_div_ctl.scala 823:6]
|
|
wire _T_343 = _T_342 ^ control_ff[2]; // @[exu_div_ctl.scala 823:23]
|
|
wire _T_346 = _T_239 == 38'h0; // @[exu_div_ctl.scala 823:82]
|
|
wire _T_347 = _T_305 & _T_346; // @[exu_div_ctl.scala 823:67]
|
|
wire _T_348 = _T_343 | _T_347; // @[exu_div_ctl.scala 823:43]
|
|
wire [37:0] adder9_out = _T_291 + b_ff; // @[exu_div_ctl.scala 809:94]
|
|
wire _T_350 = ~adder9_out[37]; // @[exu_div_ctl.scala 824:6]
|
|
wire _T_351 = _T_350 ^ control_ff[2]; // @[exu_div_ctl.scala 824:22]
|
|
wire _T_354 = adder9_out == 38'h0; // @[exu_div_ctl.scala 824:80]
|
|
wire _T_355 = _T_305 & _T_354; // @[exu_div_ctl.scala 824:66]
|
|
wire _T_356 = _T_351 | _T_355; // @[exu_div_ctl.scala 824:42]
|
|
wire _T_358 = ~_T_291[37]; // @[exu_div_ctl.scala 825:6]
|
|
wire _T_359 = _T_358 ^ control_ff[2]; // @[exu_div_ctl.scala 825:22]
|
|
wire _T_362 = _T_291 == 38'h0; // @[exu_div_ctl.scala 825:80]
|
|
wire _T_363 = _T_305 & _T_362; // @[exu_div_ctl.scala 825:66]
|
|
wire _T_364 = _T_359 | _T_363; // @[exu_div_ctl.scala 825:42]
|
|
wire [37:0] _T_191 = _T_287 + _T_293; // @[exu_div_ctl.scala 807:67]
|
|
wire [37:0] _T_195 = _T_191 + _T_297; // @[exu_div_ctl.scala 807:94]
|
|
wire [37:0] adder7_out = _T_195 + b_ff; // @[exu_div_ctl.scala 807:116]
|
|
wire _T_366 = ~adder7_out[37]; // @[exu_div_ctl.scala 826:6]
|
|
wire _T_367 = _T_366 ^ control_ff[2]; // @[exu_div_ctl.scala 826:22]
|
|
wire _T_370 = adder7_out == 38'h0; // @[exu_div_ctl.scala 826:80]
|
|
wire _T_371 = _T_305 & _T_370; // @[exu_div_ctl.scala 826:66]
|
|
wire _T_372 = _T_367 | _T_371; // @[exu_div_ctl.scala 826:42]
|
|
wire _T_374 = ~_T_195[37]; // @[exu_div_ctl.scala 827:6]
|
|
wire _T_375 = _T_374 ^ control_ff[2]; // @[exu_div_ctl.scala 827:22]
|
|
wire _T_378 = _T_195 == 38'h0; // @[exu_div_ctl.scala 827:80]
|
|
wire _T_379 = _T_305 & _T_378; // @[exu_div_ctl.scala 827:66]
|
|
wire _T_380 = _T_375 | _T_379; // @[exu_div_ctl.scala 827:42]
|
|
wire [37:0] adder5_out = _T_191 + b_ff; // @[exu_div_ctl.scala 805:94]
|
|
wire _T_382 = ~adder5_out[37]; // @[exu_div_ctl.scala 828:6]
|
|
wire _T_383 = _T_382 ^ control_ff[2]; // @[exu_div_ctl.scala 828:22]
|
|
wire _T_386 = adder5_out == 38'h0; // @[exu_div_ctl.scala 828:80]
|
|
wire _T_387 = _T_305 & _T_386; // @[exu_div_ctl.scala 828:66]
|
|
wire _T_388 = _T_383 | _T_387; // @[exu_div_ctl.scala 828:42]
|
|
wire _T_390 = ~_T_191[37]; // @[exu_div_ctl.scala 829:6]
|
|
wire _T_391 = _T_390 ^ control_ff[2]; // @[exu_div_ctl.scala 829:22]
|
|
wire _T_394 = _T_191 == 38'h0; // @[exu_div_ctl.scala 829:80]
|
|
wire _T_395 = _T_305 & _T_394; // @[exu_div_ctl.scala 829:66]
|
|
wire _T_396 = _T_391 | _T_395; // @[exu_div_ctl.scala 829:42]
|
|
wire [36:0] _T_146 = {r_ff,a_ff[31:28]}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_148 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_150 = _T_146 + _T_148; // @[exu_div_ctl.scala 803:58]
|
|
wire [36:0] adder3_out = _T_150 + b_ff[36:0]; // @[exu_div_ctl.scala 803:80]
|
|
wire _T_398 = ~adder3_out[36]; // @[exu_div_ctl.scala 830:6]
|
|
wire _T_399 = _T_398 ^ control_ff[2]; // @[exu_div_ctl.scala 830:22]
|
|
wire _T_402 = adder3_out == 37'h0; // @[exu_div_ctl.scala 830:80]
|
|
wire _T_403 = _T_305 & _T_402; // @[exu_div_ctl.scala 830:66]
|
|
wire _T_404 = _T_399 | _T_403; // @[exu_div_ctl.scala 830:42]
|
|
wire [35:0] _T_140 = {r_ff[31:0],a_ff[31:28]}; // @[Cat.scala 29:58]
|
|
wire [35:0] _T_142 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58]
|
|
wire [35:0] adder2_out = _T_140 + _T_142; // @[exu_div_ctl.scala 802:58]
|
|
wire _T_406 = ~adder2_out[35]; // @[exu_div_ctl.scala 831:6]
|
|
wire _T_407 = _T_406 ^ control_ff[2]; // @[exu_div_ctl.scala 831:22]
|
|
wire _T_410 = adder2_out == 36'h0; // @[exu_div_ctl.scala 831:80]
|
|
wire _T_411 = _T_305 & _T_410; // @[exu_div_ctl.scala 831:66]
|
|
wire _T_412 = _T_407 | _T_411; // @[exu_div_ctl.scala 831:42]
|
|
wire [34:0] _T_135 = {r_ff[30:0],a_ff[31:28]}; // @[Cat.scala 29:58]
|
|
wire [34:0] adder1_out = _T_135 + b_ff[34:0]; // @[exu_div_ctl.scala 801:58]
|
|
wire _T_414 = ~adder1_out[34]; // @[exu_div_ctl.scala 832:6]
|
|
wire _T_415 = _T_414 ^ control_ff[2]; // @[exu_div_ctl.scala 832:22]
|
|
wire _T_418 = adder1_out == 35'h0; // @[exu_div_ctl.scala 832:80]
|
|
wire _T_419 = _T_305 & _T_418; // @[exu_div_ctl.scala 832:66]
|
|
wire _T_420 = _T_415 | _T_419; // @[exu_div_ctl.scala 832:42]
|
|
wire [7:0] _T_427 = {_T_372,_T_380,_T_388,_T_396,_T_404,_T_412,_T_420,1'h0}; // @[Cat.scala 29:58]
|
|
wire [15:0] quotient_raw = {_T_308,_T_316,_T_324,_T_332,_T_340,_T_348,_T_356,_T_364,_T_427}; // @[Cat.scala 29:58]
|
|
wire _T_439 = quotient_raw[15:8] == 8'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_444 = quotient_raw[15:9] == 7'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_477 = _T_439 | _T_444; // @[Mux.scala 27:72]
|
|
wire _T_449 = quotient_raw[15:10] == 6'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_478 = _T_477 | _T_449; // @[Mux.scala 27:72]
|
|
wire _T_454 = quotient_raw[15:11] == 5'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_479 = _T_478 | _T_454; // @[Mux.scala 27:72]
|
|
wire _T_459 = quotient_raw[15:12] == 4'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_480 = _T_479 | _T_459; // @[Mux.scala 27:72]
|
|
wire _T_464 = quotient_raw[15:13] == 3'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_481 = _T_480 | _T_464; // @[Mux.scala 27:72]
|
|
wire _T_468 = quotient_raw[15:14] == 2'h1; // @[exu_div_ctl.scala 835:49]
|
|
wire _T_482 = _T_481 | _T_468; // @[Mux.scala 27:72]
|
|
wire _T_486 = _T_482 | quotient_raw[15]; // @[exu_div_ctl.scala 835:94]
|
|
wire _T_488 = quotient_raw[15:4] == 12'h1; // @[exu_div_ctl.scala 836:40]
|
|
wire _T_490 = quotient_raw[15:5] == 11'h1; // @[exu_div_ctl.scala 836:98]
|
|
wire _T_511 = _T_488 | _T_490; // @[Mux.scala 27:72]
|
|
wire _T_492 = quotient_raw[15:6] == 10'h1; // @[exu_div_ctl.scala 836:155]
|
|
wire _T_512 = _T_511 | _T_492; // @[Mux.scala 27:72]
|
|
wire _T_494 = quotient_raw[15:7] == 9'h1; // @[exu_div_ctl.scala 836:211]
|
|
wire _T_513 = _T_512 | _T_494; // @[Mux.scala 27:72]
|
|
wire _T_514 = _T_513 | _T_459; // @[Mux.scala 27:72]
|
|
wire _T_515 = _T_514 | _T_464; // @[Mux.scala 27:72]
|
|
wire _T_516 = _T_515 | _T_468; // @[Mux.scala 27:72]
|
|
wire _T_517 = _T_516 | quotient_raw[15]; // @[Mux.scala 27:72]
|
|
wire _T_520 = quotient_raw[15:2] == 14'h1; // @[exu_div_ctl.scala 838:37]
|
|
wire _T_522 = quotient_raw[15:3] == 13'h1; // @[exu_div_ctl.scala 838:97]
|
|
wire _T_543 = _T_520 | _T_522; // @[Mux.scala 27:72]
|
|
wire _T_544 = _T_543 | _T_492; // @[Mux.scala 27:72]
|
|
wire _T_545 = _T_544 | _T_494; // @[Mux.scala 27:72]
|
|
wire _T_546 = _T_545 | _T_449; // @[Mux.scala 27:72]
|
|
wire _T_547 = _T_546 | _T_454; // @[Mux.scala 27:72]
|
|
wire _T_548 = _T_547 | _T_468; // @[Mux.scala 27:72]
|
|
wire _T_549 = _T_548 | quotient_raw[15]; // @[Mux.scala 27:72]
|
|
wire _T_554 = quotient_raw[15:1] == 15'h1; // @[exu_div_ctl.scala 840:54]
|
|
wire _T_593 = _T_554 | _T_522; // @[Mux.scala 27:72]
|
|
wire _T_594 = _T_593 | _T_490; // @[Mux.scala 27:72]
|
|
wire _T_595 = _T_594 | _T_494; // @[Mux.scala 27:72]
|
|
wire _T_596 = _T_595 | _T_444; // @[Mux.scala 27:72]
|
|
wire _T_597 = _T_596 | _T_454; // @[Mux.scala 27:72]
|
|
wire _T_598 = _T_597 | _T_464; // @[Mux.scala 27:72]
|
|
wire _T_602 = _T_598 | quotient_raw[15]; // @[exu_div_ctl.scala 840:99]
|
|
wire [3:0] quotient_new = {_T_486,_T_517,_T_549,_T_602}; // @[Cat.scala 29:58]
|
|
wire _T_85 = quotient_new == 4'h0; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_0 = _T_86 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_88 = quotient_new == 4'h1; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_89 = running_state & _T_88; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_1 = _T_89 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_91 = quotient_new == 4'h2; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_92 = running_state & _T_91; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_2 = _T_92 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_94 = quotient_new == 4'h3; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_95 = running_state & _T_94; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_3 = _T_95 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_97 = quotient_new == 4'h4; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_98 = running_state & _T_97; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_4 = _T_98 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_100 = quotient_new == 4'h5; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_101 = running_state & _T_100; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_5 = _T_101 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_103 = quotient_new == 4'h6; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_6 = _T_104 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_106 = quotient_new == 4'h7; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_107 = running_state & _T_106; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_7 = _T_107 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_109 = quotient_new == 4'h8; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_110 = running_state & _T_109; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_8 = _T_110 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_112 = quotient_new == 4'h9; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_113 = running_state & _T_112; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_9 = _T_113 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_115 = quotient_new == 4'ha; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_116 = running_state & _T_115; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_10 = _T_116 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_118 = quotient_new == 4'hb; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_119 = running_state & _T_118; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_11 = _T_119 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_121 = quotient_new == 4'hc; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_122 = running_state & _T_121; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_12 = _T_122 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_124 = quotient_new == 4'hd; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_125 = running_state & _T_124; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_13 = _T_125 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_127 = quotient_new == 4'he; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_128 = running_state & _T_127; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_14 = _T_128 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
wire _T_130 = quotient_new == 4'hf; // @[exu_div_ctl.scala 800:80]
|
|
wire _T_131 = running_state & _T_130; // @[exu_div_ctl.scala 800:64]
|
|
wire r_adder_sel_15 = _T_131 & _T_66; // @[exu_div_ctl.scala 800:94]
|
|
reg [31:0] q_ff; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_607 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_608 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] twos_comp_in = _T_607 | _T_608; // @[Mux.scala 27:72]
|
|
wire _T_612 = |twos_comp_in[0]; // @[lib.scala 679:35]
|
|
wire _T_614 = ~twos_comp_in[1]; // @[lib.scala 679:40]
|
|
wire _T_616 = _T_612 ? _T_614 : twos_comp_in[1]; // @[lib.scala 679:23]
|
|
wire _T_618 = |twos_comp_in[1:0]; // @[lib.scala 679:35]
|
|
wire _T_620 = ~twos_comp_in[2]; // @[lib.scala 679:40]
|
|
wire _T_622 = _T_618 ? _T_620 : twos_comp_in[2]; // @[lib.scala 679:23]
|
|
wire _T_624 = |twos_comp_in[2:0]; // @[lib.scala 679:35]
|
|
wire _T_626 = ~twos_comp_in[3]; // @[lib.scala 679:40]
|
|
wire _T_628 = _T_624 ? _T_626 : twos_comp_in[3]; // @[lib.scala 679:23]
|
|
wire _T_630 = |twos_comp_in[3:0]; // @[lib.scala 679:35]
|
|
wire _T_632 = ~twos_comp_in[4]; // @[lib.scala 679:40]
|
|
wire _T_634 = _T_630 ? _T_632 : twos_comp_in[4]; // @[lib.scala 679:23]
|
|
wire _T_636 = |twos_comp_in[4:0]; // @[lib.scala 679:35]
|
|
wire _T_638 = ~twos_comp_in[5]; // @[lib.scala 679:40]
|
|
wire _T_640 = _T_636 ? _T_638 : twos_comp_in[5]; // @[lib.scala 679:23]
|
|
wire _T_642 = |twos_comp_in[5:0]; // @[lib.scala 679:35]
|
|
wire _T_644 = ~twos_comp_in[6]; // @[lib.scala 679:40]
|
|
wire _T_646 = _T_642 ? _T_644 : twos_comp_in[6]; // @[lib.scala 679:23]
|
|
wire _T_648 = |twos_comp_in[6:0]; // @[lib.scala 679:35]
|
|
wire _T_650 = ~twos_comp_in[7]; // @[lib.scala 679:40]
|
|
wire _T_652 = _T_648 ? _T_650 : twos_comp_in[7]; // @[lib.scala 679:23]
|
|
wire _T_654 = |twos_comp_in[7:0]; // @[lib.scala 679:35]
|
|
wire _T_656 = ~twos_comp_in[8]; // @[lib.scala 679:40]
|
|
wire _T_658 = _T_654 ? _T_656 : twos_comp_in[8]; // @[lib.scala 679:23]
|
|
wire _T_660 = |twos_comp_in[8:0]; // @[lib.scala 679:35]
|
|
wire _T_662 = ~twos_comp_in[9]; // @[lib.scala 679:40]
|
|
wire _T_664 = _T_660 ? _T_662 : twos_comp_in[9]; // @[lib.scala 679:23]
|
|
wire _T_666 = |twos_comp_in[9:0]; // @[lib.scala 679:35]
|
|
wire _T_668 = ~twos_comp_in[10]; // @[lib.scala 679:40]
|
|
wire _T_670 = _T_666 ? _T_668 : twos_comp_in[10]; // @[lib.scala 679:23]
|
|
wire _T_672 = |twos_comp_in[10:0]; // @[lib.scala 679:35]
|
|
wire _T_674 = ~twos_comp_in[11]; // @[lib.scala 679:40]
|
|
wire _T_676 = _T_672 ? _T_674 : twos_comp_in[11]; // @[lib.scala 679:23]
|
|
wire _T_678 = |twos_comp_in[11:0]; // @[lib.scala 679:35]
|
|
wire _T_680 = ~twos_comp_in[12]; // @[lib.scala 679:40]
|
|
wire _T_682 = _T_678 ? _T_680 : twos_comp_in[12]; // @[lib.scala 679:23]
|
|
wire _T_684 = |twos_comp_in[12:0]; // @[lib.scala 679:35]
|
|
wire _T_686 = ~twos_comp_in[13]; // @[lib.scala 679:40]
|
|
wire _T_688 = _T_684 ? _T_686 : twos_comp_in[13]; // @[lib.scala 679:23]
|
|
wire _T_690 = |twos_comp_in[13:0]; // @[lib.scala 679:35]
|
|
wire _T_692 = ~twos_comp_in[14]; // @[lib.scala 679:40]
|
|
wire _T_694 = _T_690 ? _T_692 : twos_comp_in[14]; // @[lib.scala 679:23]
|
|
wire _T_696 = |twos_comp_in[14:0]; // @[lib.scala 679:35]
|
|
wire _T_698 = ~twos_comp_in[15]; // @[lib.scala 679:40]
|
|
wire _T_700 = _T_696 ? _T_698 : twos_comp_in[15]; // @[lib.scala 679:23]
|
|
wire _T_702 = |twos_comp_in[15:0]; // @[lib.scala 679:35]
|
|
wire _T_704 = ~twos_comp_in[16]; // @[lib.scala 679:40]
|
|
wire _T_706 = _T_702 ? _T_704 : twos_comp_in[16]; // @[lib.scala 679:23]
|
|
wire _T_708 = |twos_comp_in[16:0]; // @[lib.scala 679:35]
|
|
wire _T_710 = ~twos_comp_in[17]; // @[lib.scala 679:40]
|
|
wire _T_712 = _T_708 ? _T_710 : twos_comp_in[17]; // @[lib.scala 679:23]
|
|
wire _T_714 = |twos_comp_in[17:0]; // @[lib.scala 679:35]
|
|
wire _T_716 = ~twos_comp_in[18]; // @[lib.scala 679:40]
|
|
wire _T_718 = _T_714 ? _T_716 : twos_comp_in[18]; // @[lib.scala 679:23]
|
|
wire _T_720 = |twos_comp_in[18:0]; // @[lib.scala 679:35]
|
|
wire _T_722 = ~twos_comp_in[19]; // @[lib.scala 679:40]
|
|
wire _T_724 = _T_720 ? _T_722 : twos_comp_in[19]; // @[lib.scala 679:23]
|
|
wire _T_726 = |twos_comp_in[19:0]; // @[lib.scala 679:35]
|
|
wire _T_728 = ~twos_comp_in[20]; // @[lib.scala 679:40]
|
|
wire _T_730 = _T_726 ? _T_728 : twos_comp_in[20]; // @[lib.scala 679:23]
|
|
wire _T_732 = |twos_comp_in[20:0]; // @[lib.scala 679:35]
|
|
wire _T_734 = ~twos_comp_in[21]; // @[lib.scala 679:40]
|
|
wire _T_736 = _T_732 ? _T_734 : twos_comp_in[21]; // @[lib.scala 679:23]
|
|
wire _T_738 = |twos_comp_in[21:0]; // @[lib.scala 679:35]
|
|
wire _T_740 = ~twos_comp_in[22]; // @[lib.scala 679:40]
|
|
wire _T_742 = _T_738 ? _T_740 : twos_comp_in[22]; // @[lib.scala 679:23]
|
|
wire _T_744 = |twos_comp_in[22:0]; // @[lib.scala 679:35]
|
|
wire _T_746 = ~twos_comp_in[23]; // @[lib.scala 679:40]
|
|
wire _T_748 = _T_744 ? _T_746 : twos_comp_in[23]; // @[lib.scala 679:23]
|
|
wire _T_750 = |twos_comp_in[23:0]; // @[lib.scala 679:35]
|
|
wire _T_752 = ~twos_comp_in[24]; // @[lib.scala 679:40]
|
|
wire _T_754 = _T_750 ? _T_752 : twos_comp_in[24]; // @[lib.scala 679:23]
|
|
wire _T_756 = |twos_comp_in[24:0]; // @[lib.scala 679:35]
|
|
wire _T_758 = ~twos_comp_in[25]; // @[lib.scala 679:40]
|
|
wire _T_760 = _T_756 ? _T_758 : twos_comp_in[25]; // @[lib.scala 679:23]
|
|
wire _T_762 = |twos_comp_in[25:0]; // @[lib.scala 679:35]
|
|
wire _T_764 = ~twos_comp_in[26]; // @[lib.scala 679:40]
|
|
wire _T_766 = _T_762 ? _T_764 : twos_comp_in[26]; // @[lib.scala 679:23]
|
|
wire _T_768 = |twos_comp_in[26:0]; // @[lib.scala 679:35]
|
|
wire _T_770 = ~twos_comp_in[27]; // @[lib.scala 679:40]
|
|
wire _T_772 = _T_768 ? _T_770 : twos_comp_in[27]; // @[lib.scala 679:23]
|
|
wire _T_774 = |twos_comp_in[27:0]; // @[lib.scala 679:35]
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wire _T_776 = ~twos_comp_in[28]; // @[lib.scala 679:40]
|
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wire _T_778 = _T_774 ? _T_776 : twos_comp_in[28]; // @[lib.scala 679:23]
|
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wire _T_780 = |twos_comp_in[28:0]; // @[lib.scala 679:35]
|
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wire _T_782 = ~twos_comp_in[29]; // @[lib.scala 679:40]
|
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wire _T_784 = _T_780 ? _T_782 : twos_comp_in[29]; // @[lib.scala 679:23]
|
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wire _T_786 = |twos_comp_in[29:0]; // @[lib.scala 679:35]
|
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wire _T_788 = ~twos_comp_in[30]; // @[lib.scala 679:40]
|
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wire _T_790 = _T_786 ? _T_788 : twos_comp_in[30]; // @[lib.scala 679:23]
|
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wire _T_792 = |twos_comp_in[30:0]; // @[lib.scala 679:35]
|
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wire _T_794 = ~twos_comp_in[31]; // @[lib.scala 679:40]
|
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wire _T_796 = _T_792 ? _T_794 : twos_comp_in[31]; // @[lib.scala 679:23]
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wire [6:0] _T_802 = {_T_652,_T_646,_T_640,_T_634,_T_628,_T_622,_T_616}; // @[lib.scala 681:14]
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wire [14:0] _T_810 = {_T_700,_T_694,_T_688,_T_682,_T_676,_T_670,_T_664,_T_658,_T_802}; // @[lib.scala 681:14]
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wire [7:0] _T_817 = {_T_748,_T_742,_T_736,_T_730,_T_724,_T_718,_T_712,_T_706}; // @[lib.scala 681:14]
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wire [30:0] _T_826 = {_T_796,_T_790,_T_784,_T_778,_T_772,_T_766,_T_760,_T_754,_T_817,_T_810}; // @[lib.scala 681:14]
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wire [31:0] twos_comp_out = {_T_826,twos_comp_in[0]}; // @[Cat.scala 29:58]
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wire _T_828 = ~a_shift; // @[exu_div_ctl.scala 847:6]
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wire _T_830 = _T_828 & _T_66; // @[exu_div_ctl.scala 847:15]
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wire [31:0] _T_834 = {a_ff[27:0],4'h0}; // @[Cat.scala 29:58]
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wire [64:0] ar_shifted = _T_71[64:0]; // @[exu_div_ctl.scala 793:28]
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wire [31:0] _T_836 = _T_830 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_837 = a_shift ? _T_834 : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_838 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
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wire [31:0] _T_839 = _T_836 | _T_837; // @[Mux.scala 27:72]
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wire [31:0] a_in = _T_839 | _T_838; // @[Mux.scala 27:72]
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wire _T_841 = ~b_twos_comp; // @[exu_div_ctl.scala 852:5]
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wire _T_843 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 852:63]
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wire [32:0] _T_845 = {_T_843,io_divisor_in}; // @[Cat.scala 29:58]
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wire _T_846 = ~control_ff[1]; // @[exu_div_ctl.scala 853:50]
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wire [32:0] _T_848 = {_T_846,_T_826,twos_comp_in[0]}; // @[Cat.scala 29:58]
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wire [32:0] _T_849 = _T_841 ? _T_845 : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_850 = b_twos_comp ? _T_848 : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] b_in = _T_849 | _T_850; // @[Mux.scala 27:72]
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wire [32:0] _T_855 = {r_ff[28:0],a_ff[31:28]}; // @[Cat.scala 29:58]
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wire [32:0] _T_873 = {1'h0,a_ff}; // @[Cat.scala 29:58]
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wire [32:0] _T_874 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_875 = r_adder_sel_0 ? _T_855 : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_876 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_877 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_878 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_879 = r_adder_sel_4 ? _T_191[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_880 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_881 = r_adder_sel_6 ? _T_195[32:0] : 33'h0; // @[Mux.scala 27:72]
|
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wire [32:0] _T_882 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_883 = r_adder_sel_8 ? _T_291[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_884 = r_adder_sel_9 ? adder9_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_885 = r_adder_sel_10 ? _T_239[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_886 = r_adder_sel_11 ? adder11_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
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wire [32:0] _T_887 = r_adder_sel_12 ? _T_295[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_888 = r_adder_sel_13 ? adder13_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_889 = r_adder_sel_14 ? _T_299[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_890 = r_adder_sel_15 ? adder15_out[32:0] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_891 = shortq_enable_ff ? ar_shifted[64:32] : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_892 = by_zero_case ? _T_873 : 33'h0; // @[Mux.scala 27:72]
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wire [32:0] _T_893 = _T_874 | _T_875; // @[Mux.scala 27:72]
|
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wire [32:0] _T_894 = _T_893 | _T_876; // @[Mux.scala 27:72]
|
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wire [32:0] _T_895 = _T_894 | _T_877; // @[Mux.scala 27:72]
|
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wire [32:0] _T_896 = _T_895 | _T_878; // @[Mux.scala 27:72]
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wire [32:0] _T_897 = _T_896 | _T_879; // @[Mux.scala 27:72]
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wire [32:0] _T_898 = _T_897 | _T_880; // @[Mux.scala 27:72]
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wire [32:0] _T_899 = _T_898 | _T_881; // @[Mux.scala 27:72]
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wire [32:0] _T_900 = _T_899 | _T_882; // @[Mux.scala 27:72]
|
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wire [32:0] _T_901 = _T_900 | _T_883; // @[Mux.scala 27:72]
|
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wire [32:0] _T_902 = _T_901 | _T_884; // @[Mux.scala 27:72]
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wire [32:0] _T_903 = _T_902 | _T_885; // @[Mux.scala 27:72]
|
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wire [32:0] _T_904 = _T_903 | _T_886; // @[Mux.scala 27:72]
|
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wire [32:0] _T_905 = _T_904 | _T_887; // @[Mux.scala 27:72]
|
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wire [32:0] _T_906 = _T_905 | _T_888; // @[Mux.scala 27:72]
|
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wire [32:0] _T_907 = _T_906 | _T_889; // @[Mux.scala 27:72]
|
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wire [32:0] _T_908 = _T_907 | _T_890; // @[Mux.scala 27:72]
|
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wire [32:0] _T_909 = _T_908 | _T_891; // @[Mux.scala 27:72]
|
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wire [32:0] r_in = _T_909 | _T_892; // @[Mux.scala 27:72]
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wire [31:0] _T_913 = {q_ff[27:0],_T_486,_T_517,_T_549,_T_602}; // @[Cat.scala 29:58]
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wire _T_936 = ~b_ff[3]; // @[exu_div_ctl.scala 889:70]
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wire _T_938 = ~b_ff[2]; // @[exu_div_ctl.scala 889:70]
|
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wire _T_941 = _T_936 & _T_938; // @[exu_div_ctl.scala 889:95]
|
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wire _T_940 = ~b_ff[1]; // @[exu_div_ctl.scala 889:70]
|
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wire _T_942 = _T_941 & _T_940; // @[exu_div_ctl.scala 889:95]
|
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wire _T_943 = a_ff[3] & _T_942; // @[exu_div_ctl.scala 890:11]
|
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wire _T_950 = a_ff[3] & _T_941; // @[exu_div_ctl.scala 890:11]
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wire _T_952 = ~b_ff[0]; // @[exu_div_ctl.scala 895:33]
|
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wire _T_953 = _T_950 & _T_952; // @[exu_div_ctl.scala 895:31]
|
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wire _T_963 = a_ff[2] & _T_942; // @[exu_div_ctl.scala 890:11]
|
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wire _T_964 = _T_953 | _T_963; // @[exu_div_ctl.scala 895:42]
|
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wire _T_967 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_973 = _T_967 & _T_941; // @[exu_div_ctl.scala 890:11]
|
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wire _T_974 = _T_964 | _T_973; // @[exu_div_ctl.scala 895:75]
|
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wire _T_981 = a_ff[2] & _T_941; // @[exu_div_ctl.scala 890:11]
|
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wire _T_984 = _T_981 & _T_952; // @[exu_div_ctl.scala 897:31]
|
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wire _T_994 = a_ff[1] & _T_942; // @[exu_div_ctl.scala 890:11]
|
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wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 897:42]
|
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wire _T_1001 = _T_936 & _T_940; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1002 = a_ff[3] & _T_1001; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1005 = _T_1002 & _T_952; // @[exu_div_ctl.scala 897:106]
|
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wire _T_1006 = _T_995 | _T_1005; // @[exu_div_ctl.scala 897:78]
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wire _T_1009 = ~a_ff[2]; // @[exu_div_ctl.scala 888:70]
|
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wire _T_1010 = a_ff[3] & _T_1009; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1018 = _T_941 & b_ff[1]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1019 = _T_1018 & b_ff[0]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1020 = _T_1010 & _T_1019; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1021 = _T_1006 | _T_1020; // @[exu_div_ctl.scala 897:117]
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wire _T_1023 = ~a_ff[3]; // @[exu_div_ctl.scala 888:70]
|
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wire _T_1026 = _T_1023 & a_ff[2]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1027 = _T_1026 & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1033 = _T_1027 & _T_941; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1034 = _T_1021 | _T_1033; // @[exu_div_ctl.scala 898:44]
|
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wire _T_1040 = _T_967 & _T_936; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1043 = _T_1040 & _T_952; // @[exu_div_ctl.scala 898:107]
|
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wire _T_1044 = _T_1034 | _T_1043; // @[exu_div_ctl.scala 898:80]
|
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wire _T_1053 = _T_936 & b_ff[2]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1054 = _T_1053 & _T_940; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1055 = _T_967 & _T_1054; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1056 = _T_1044 | _T_1055; // @[exu_div_ctl.scala 898:119]
|
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wire _T_1059 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1065 = _T_1059 & _T_1001; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1066 = _T_1056 | _T_1065; // @[exu_div_ctl.scala 899:44]
|
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wire _T_1071 = _T_967 & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1076 = _T_1071 & _T_1053; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1077 = _T_1066 | _T_1076; // @[exu_div_ctl.scala 899:79]
|
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wire _T_1081 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1082 = _T_1081 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1088 = _T_1082 & _T_1001; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1094 = _T_1010 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1099 = _T_936 & b_ff[1]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1100 = _T_1099 & b_ff[0]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1101 = _T_1094 & _T_1100; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1102 = _T_1088 | _T_1101; // @[exu_div_ctl.scala 901:45]
|
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wire _T_1109 = a_ff[2] & _T_1001; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1112 = _T_1109 & _T_952; // @[exu_div_ctl.scala 901:114]
|
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wire _T_1113 = _T_1102 | _T_1112; // @[exu_div_ctl.scala 901:86]
|
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wire _T_1120 = a_ff[1] & _T_941; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1123 = _T_1120 & _T_952; // @[exu_div_ctl.scala 902:33]
|
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wire _T_1124 = _T_1113 | _T_1123; // @[exu_div_ctl.scala 901:129]
|
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wire _T_1134 = a_ff[0] & _T_942; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1135 = _T_1124 | _T_1134; // @[exu_div_ctl.scala 902:47]
|
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wire _T_1140 = ~a_ff[1]; // @[exu_div_ctl.scala 888:70]
|
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wire _T_1142 = _T_1026 & _T_1140; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1152 = _T_1142 & _T_1019; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1153 = _T_1135 | _T_1152; // @[exu_div_ctl.scala 902:88]
|
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wire _T_1162 = _T_1027 & _T_936; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1165 = _T_1162 & _T_952; // @[exu_div_ctl.scala 903:36]
|
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wire _T_1166 = _T_1153 | _T_1165; // @[exu_div_ctl.scala 902:131]
|
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wire _T_1172 = _T_938 & _T_940; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1173 = a_ff[3] & _T_1172; // @[exu_div_ctl.scala 890:11]
|
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wire _T_1176 = _T_1173 & _T_952; // @[exu_div_ctl.scala 903:76]
|
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wire _T_1177 = _T_1166 | _T_1176; // @[exu_div_ctl.scala 903:47]
|
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wire _T_1187 = _T_1053 & b_ff[1]; // @[exu_div_ctl.scala 889:95]
|
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wire _T_1188 = _T_1010 & _T_1187; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1189 = _T_1177 | _T_1188; // @[exu_div_ctl.scala 903:88]
|
|
wire _T_1203 = _T_1027 & _T_1054; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1204 = _T_1189 | _T_1203; // @[exu_div_ctl.scala 903:131]
|
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wire _T_1210 = _T_1026 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
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wire _T_1216 = _T_1210 & _T_1001; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1217 = _T_1204 | _T_1216; // @[exu_div_ctl.scala 904:47]
|
|
wire _T_1224 = _T_1010 & _T_1140; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1230 = _T_1053 & b_ff[0]; // @[exu_div_ctl.scala 889:95]
|
|
wire _T_1231 = _T_1224 & _T_1230; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1232 = _T_1217 | _T_1231; // @[exu_div_ctl.scala 904:88]
|
|
wire _T_1237 = _T_1009 & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1238 = _T_1237 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1244 = _T_1238 & _T_941; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1245 = _T_1232 | _T_1244; // @[exu_div_ctl.scala 904:131]
|
|
wire _T_1251 = _T_967 & _T_940; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1254 = _T_1251 & _T_952; // @[exu_div_ctl.scala 905:75]
|
|
wire _T_1255 = _T_1245 | _T_1254; // @[exu_div_ctl.scala 905:47]
|
|
wire _T_1263 = _T_1027 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1268 = _T_1263 & _T_1053; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1269 = _T_1255 | _T_1268; // @[exu_div_ctl.scala 905:88]
|
|
wire _T_1276 = b_ff[3] & _T_938; // @[exu_div_ctl.scala 889:95]
|
|
wire _T_1277 = _T_967 & _T_1276; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1278 = _T_1269 | _T_1277; // @[exu_div_ctl.scala 905:131]
|
|
wire _T_1288 = _T_1276 & _T_940; // @[exu_div_ctl.scala 889:95]
|
|
wire _T_1289 = _T_1059 & _T_1288; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1290 = _T_1278 | _T_1289; // @[exu_div_ctl.scala 906:47]
|
|
wire _T_1293 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1299 = _T_1293 & _T_1172; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1300 = _T_1290 | _T_1299; // @[exu_div_ctl.scala 906:88]
|
|
wire _T_1304 = a_ff[3] & _T_1140; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1312 = _T_1187 & b_ff[0]; // @[exu_div_ctl.scala 889:95]
|
|
wire _T_1313 = _T_1304 & _T_1312; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1314 = _T_1300 | _T_1313; // @[exu_div_ctl.scala 906:131]
|
|
wire _T_1321 = _T_1071 & b_ff[3]; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1324 = _T_1321 & _T_952; // @[exu_div_ctl.scala 907:77]
|
|
wire _T_1325 = _T_1314 | _T_1324; // @[exu_div_ctl.scala 907:47]
|
|
wire _T_1334 = b_ff[3] & _T_940; // @[exu_div_ctl.scala 889:95]
|
|
wire _T_1335 = _T_1071 & _T_1334; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1336 = _T_1325 | _T_1335; // @[exu_div_ctl.scala 907:88]
|
|
wire _T_1341 = _T_967 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1346 = _T_1341 & _T_1334; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1347 = _T_1336 | _T_1346; // @[exu_div_ctl.scala 907:131]
|
|
wire _T_1353 = _T_1010 & a_ff[1]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1358 = _T_1353 & _T_1099; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1359 = _T_1347 | _T_1358; // @[exu_div_ctl.scala 908:47]
|
|
wire _T_1364 = _T_1059 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1367 = _T_1364 & _T_938; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1368 = _T_1359 | _T_1367; // @[exu_div_ctl.scala 908:88]
|
|
wire _T_1375 = _T_1071 & a_ff[0]; // @[exu_div_ctl.scala 888:95]
|
|
wire _T_1377 = _T_1375 & b_ff[3]; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1378 = _T_1368 | _T_1377; // @[exu_div_ctl.scala 908:131]
|
|
wire _T_1384 = _T_1059 & _T_938; // @[exu_div_ctl.scala 890:11]
|
|
wire _T_1387 = _T_1384 & _T_952; // @[exu_div_ctl.scala 909:74]
|
|
wire _T_1388 = _T_1378 | _T_1387; // @[exu_div_ctl.scala 909:47]
|
|
wire [31:0] _T_914 = {28'h0,_T_943,_T_974,_T_1077,_T_1388}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_916 = _T_76 ? _T_913 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_917 = smallnum_case ? _T_914 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_918 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_919 = _T_916 | _T_917; // @[Mux.scala 27:72]
|
|
wire [31:0] q_in = _T_919 | _T_918; // @[Mux.scala 27:72]
|
|
wire _T_924 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 883:16]
|
|
wire _T_925 = _T_30 & _T_924; // @[exu_div_ctl.scala 883:14]
|
|
wire [31:0] _T_928 = _T_925 ? q_ff : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_929 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_930 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_931 = _T_928 | _T_929; // @[Mux.scala 27:72]
|
|
wire _T_1415 = shortq == 6'h1b; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1416 = shortq == 6'h1a; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1417 = shortq == 6'h19; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1418 = shortq == 6'h18; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1419 = shortq == 6'h17; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1420 = shortq == 6'h16; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1421 = shortq == 6'h15; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1422 = shortq == 6'h14; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1423 = shortq == 6'h13; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1424 = shortq == 6'h12; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1425 = shortq == 6'h11; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1426 = shortq == 6'h10; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1427 = shortq == 6'hf; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1428 = shortq == 6'he; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1429 = shortq == 6'hd; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1430 = shortq == 6'hc; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1431 = shortq == 6'hb; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1432 = shortq == 6'ha; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1433 = shortq == 6'h9; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1434 = shortq == 6'h8; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1435 = shortq == 6'h7; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1436 = shortq == 6'h6; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1437 = shortq == 6'h5; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1438 = shortq == 6'h4; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1439 = shortq == 6'h3; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1440 = shortq == 6'h2; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1441 = shortq == 6'h1; // @[exu_div_ctl.scala 925:64]
|
|
wire _T_1442 = shortq == 6'h0; // @[exu_div_ctl.scala 925:64]
|
|
wire [2:0] _T_1447 = _T_1415 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1448 = _T_1416 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1449 = _T_1417 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1450 = _T_1418 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1451 = _T_1419 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1452 = _T_1420 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1453 = _T_1421 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1454 = _T_1422 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1455 = _T_1423 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1456 = _T_1424 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1457 = _T_1425 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1458 = _T_1426 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1459 = _T_1427 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1460 = _T_1428 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1461 = _T_1429 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1462 = _T_1430 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1463 = _T_1431 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1464 = _T_1432 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1465 = _T_1433 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1466 = _T_1434 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1467 = _T_1435 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1468 = _T_1436 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1469 = _T_1437 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1470 = _T_1438 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1471 = _T_1439 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1472 = _T_1440 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1473 = _T_1441 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1474 = _T_1442 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1479 = _T_1447 | _T_1448; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1480 = _T_1479 | _T_1449; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1481 = _T_1480 | _T_1450; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_12 = {{1'd0}, _T_1481}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1482 = _GEN_12 | _T_1451; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1483 = _T_1482 | _T_1452; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1484 = _T_1483 | _T_1453; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1485 = _T_1484 | _T_1454; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1486 = _T_1485 | _T_1455; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1487 = _T_1486 | _T_1456; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1488 = _T_1487 | _T_1457; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1489 = _T_1488 | _T_1458; // @[Mux.scala 27:72]
|
|
wire [4:0] _GEN_13 = {{1'd0}, _T_1489}; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1490 = _GEN_13 | _T_1459; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1491 = _T_1490 | _T_1460; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1492 = _T_1491 | _T_1461; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1493 = _T_1492 | _T_1462; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1494 = _T_1493 | _T_1463; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1495 = _T_1494 | _T_1464; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1496 = _T_1495 | _T_1465; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1497 = _T_1496 | _T_1466; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1498 = _T_1497 | _T_1467; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1499 = _T_1498 | _T_1468; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1500 = _T_1499 | _T_1469; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1501 = _T_1500 | _T_1470; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1502 = _T_1501 | _T_1471; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1503 = _T_1502 | _T_1472; // @[Mux.scala 27:72]
|
|
wire [4:0] _T_1504 = _T_1503 | _T_1473; // @[Mux.scala 27:72]
|
|
wire [4:0] shortq_decode = _T_1504 | _T_1474; // @[Mux.scala 27:72]
|
|
exu_div_cls a_enc ( // @[exu_div_ctl.scala 913:31]
|
|
.io_operand(a_enc_io_operand),
|
|
.io_cls(a_enc_io_cls)
|
|
);
|
|
exu_div_cls b_enc ( // @[exu_div_ctl.scala 916:31]
|
|
.io_operand(b_enc_io_operand),
|
|
.io_cls(b_enc_io_cls)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
assign io_data_out = _T_931 | _T_930; // @[exu_div_ctl.scala 882:15]
|
|
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 881:16]
|
|
assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 914:23]
|
|
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 917:23]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
control_ff = _RAND_0[2:0];
|
|
_RAND_1 = {2{`RANDOM}};
|
|
b_ff1 = _RAND_1[32:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
valid_ff = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
a_ff = _RAND_3[31:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
count_ff = _RAND_4[6:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
shortq_enable_ff = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
finish_ff = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
shortq_shift_ff = _RAND_7[4:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
by_zero_case_ff = _RAND_8[0:0];
|
|
_RAND_9 = {2{`RANDOM}};
|
|
r_ff = _RAND_9[32:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
q_ff = _RAND_10[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
control_ff = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
b_ff1 = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
valid_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
a_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
count_ff = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
shortq_enable_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
finish_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
shortq_shift_ff = 5'h0;
|
|
end
|
|
if (reset) begin
|
|
by_zero_case_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
r_ff = 33'h0;
|
|
end
|
|
if (reset) begin
|
|
q_ff = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
control_ff <= 3'h0;
|
|
end else if (misc_enable) begin
|
|
control_ff <= control_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
b_ff1 <= 33'h0;
|
|
end else if (b_enable) begin
|
|
b_ff1 <= b_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
valid_ff <= 1'h0;
|
|
end else if (misc_enable) begin
|
|
valid_ff <= valid_ff_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
a_ff <= 32'h0;
|
|
end else if (a_enable) begin
|
|
a_ff <= a_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
count_ff <= 7'h0;
|
|
end else if (misc_enable) begin
|
|
count_ff <= count_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
shortq_enable_ff <= 1'h0;
|
|
end else if (misc_enable) begin
|
|
shortq_enable_ff <= shortq_enable;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
finish_ff <= 1'h0;
|
|
end else if (misc_enable) begin
|
|
finish_ff <= finish;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
shortq_shift_ff <= 5'h0;
|
|
end else if (misc_enable) begin
|
|
if (_T_58) begin
|
|
shortq_shift_ff <= 5'h0;
|
|
end else begin
|
|
shortq_shift_ff <= shortq_decode;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
by_zero_case_ff <= 1'h0;
|
|
end else if (misc_enable) begin
|
|
by_zero_case_ff <= by_zero_case;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
r_ff <= 33'h0;
|
|
end else if (rq_enable) begin
|
|
r_ff <= r_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
q_ff <= 32'h0;
|
|
end else if (rq_enable) begin
|
|
q_ff <= q_in;
|
|
end
|
|
end
|
|
endmodule
|
|
module exu_div_ctl(
|
|
input clock,
|
|
input reset,
|
|
input [31:0] io_dividend,
|
|
input [31:0] io_divisor,
|
|
output [31:0] io_exu_div_result,
|
|
output io_exu_div_wren,
|
|
input io_dec_div_div_p_valid,
|
|
input io_dec_div_div_p_bits_unsign,
|
|
input io_dec_div_div_p_bits_rem,
|
|
input io_dec_div_dec_div_cancel
|
|
);
|
|
wire exu_div_new_4bit_fullshortq_clock; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_reset; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_io_cancel; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_io_valid_in; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_io_signed_in; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_io_rem_in; // @[exu_div_ctl.scala 71:30]
|
|
wire [31:0] exu_div_new_4bit_fullshortq_io_dividend_in; // @[exu_div_ctl.scala 71:30]
|
|
wire [31:0] exu_div_new_4bit_fullshortq_io_divisor_in; // @[exu_div_ctl.scala 71:30]
|
|
wire [31:0] exu_div_new_4bit_fullshortq_io_data_out; // @[exu_div_ctl.scala 71:30]
|
|
wire exu_div_new_4bit_fullshortq_io_valid_out; // @[exu_div_ctl.scala 71:30]
|
|
wire [31:0] _T_1 = io_exu_div_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] out_raw = exu_div_new_4bit_fullshortq_io_data_out; // @[exu_div_ctl.scala 79:29]
|
|
exu_div_new_4bit_fullshortq exu_div_new_4bit_fullshortq ( // @[exu_div_ctl.scala 71:30]
|
|
.clock(exu_div_new_4bit_fullshortq_clock),
|
|
.reset(exu_div_new_4bit_fullshortq_reset),
|
|
.io_cancel(exu_div_new_4bit_fullshortq_io_cancel),
|
|
.io_valid_in(exu_div_new_4bit_fullshortq_io_valid_in),
|
|
.io_signed_in(exu_div_new_4bit_fullshortq_io_signed_in),
|
|
.io_rem_in(exu_div_new_4bit_fullshortq_io_rem_in),
|
|
.io_dividend_in(exu_div_new_4bit_fullshortq_io_dividend_in),
|
|
.io_divisor_in(exu_div_new_4bit_fullshortq_io_divisor_in),
|
|
.io_data_out(exu_div_new_4bit_fullshortq_io_data_out),
|
|
.io_valid_out(exu_div_new_4bit_fullshortq_io_valid_out)
|
|
);
|
|
assign io_exu_div_result = _T_1 & out_raw; // @[exu_div_ctl.scala 21:21]
|
|
assign io_exu_div_wren = exu_div_new_4bit_fullshortq_io_valid_out; // @[exu_div_ctl.scala 80:29]
|
|
assign exu_div_new_4bit_fullshortq_clock = clock;
|
|
assign exu_div_new_4bit_fullshortq_reset = reset;
|
|
assign exu_div_new_4bit_fullshortq_io_cancel = io_dec_div_dec_div_cancel; // @[exu_div_ctl.scala 73:34]
|
|
assign exu_div_new_4bit_fullshortq_io_valid_in = io_dec_div_div_p_valid; // @[exu_div_ctl.scala 74:34]
|
|
assign exu_div_new_4bit_fullshortq_io_signed_in = ~io_dec_div_div_p_bits_unsign; // @[exu_div_ctl.scala 75:34]
|
|
assign exu_div_new_4bit_fullshortq_io_rem_in = io_dec_div_div_p_bits_rem; // @[exu_div_ctl.scala 76:34]
|
|
assign exu_div_new_4bit_fullshortq_io_dividend_in = io_dividend; // @[exu_div_ctl.scala 77:34]
|
|
assign exu_div_new_4bit_fullshortq_io_divisor_in = io_divisor; // @[exu_div_ctl.scala 78:34]
|
|
endmodule
|
|
module exu(
|
|
input clock,
|
|
input reset,
|
|
input io_dec_exu_dec_alu_dec_i0_alu_decode_d,
|
|
input io_dec_exu_dec_alu_dec_csr_ren_d,
|
|
input [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d,
|
|
output [30:0] io_dec_exu_dec_alu_exu_i0_pc_x,
|
|
input io_dec_exu_dec_div_div_p_valid,
|
|
input io_dec_exu_dec_div_div_p_bits_unsign,
|
|
input io_dec_exu_dec_div_div_p_bits_rem,
|
|
input io_dec_exu_dec_div_dec_div_cancel,
|
|
input [1:0] io_dec_exu_decode_exu_dec_data_en,
|
|
input [1:0] io_dec_exu_decode_exu_dec_ctl_en,
|
|
input io_dec_exu_decode_exu_i0_ap_clz,
|
|
input io_dec_exu_decode_exu_i0_ap_ctz,
|
|
input io_dec_exu_decode_exu_i0_ap_pcnt,
|
|
input io_dec_exu_decode_exu_i0_ap_sext_b,
|
|
input io_dec_exu_decode_exu_i0_ap_sext_h,
|
|
input io_dec_exu_decode_exu_i0_ap_min,
|
|
input io_dec_exu_decode_exu_i0_ap_max,
|
|
input io_dec_exu_decode_exu_i0_ap_pack,
|
|
input io_dec_exu_decode_exu_i0_ap_packu,
|
|
input io_dec_exu_decode_exu_i0_ap_packh,
|
|
input io_dec_exu_decode_exu_i0_ap_rol,
|
|
input io_dec_exu_decode_exu_i0_ap_ror,
|
|
input io_dec_exu_decode_exu_i0_ap_grev,
|
|
input io_dec_exu_decode_exu_i0_ap_gorc,
|
|
input io_dec_exu_decode_exu_i0_ap_zbb,
|
|
input io_dec_exu_decode_exu_i0_ap_sbset,
|
|
input io_dec_exu_decode_exu_i0_ap_sbclr,
|
|
input io_dec_exu_decode_exu_i0_ap_sbinv,
|
|
input io_dec_exu_decode_exu_i0_ap_sbext,
|
|
input io_dec_exu_decode_exu_i0_ap_land,
|
|
input io_dec_exu_decode_exu_i0_ap_lor,
|
|
input io_dec_exu_decode_exu_i0_ap_lxor,
|
|
input io_dec_exu_decode_exu_i0_ap_sll,
|
|
input io_dec_exu_decode_exu_i0_ap_srl,
|
|
input io_dec_exu_decode_exu_i0_ap_sra,
|
|
input io_dec_exu_decode_exu_i0_ap_beq,
|
|
input io_dec_exu_decode_exu_i0_ap_bne,
|
|
input io_dec_exu_decode_exu_i0_ap_blt,
|
|
input io_dec_exu_decode_exu_i0_ap_bge,
|
|
input io_dec_exu_decode_exu_i0_ap_add,
|
|
input io_dec_exu_decode_exu_i0_ap_sub,
|
|
input io_dec_exu_decode_exu_i0_ap_slt,
|
|
input io_dec_exu_decode_exu_i0_ap_unsign,
|
|
input io_dec_exu_decode_exu_i0_ap_jal,
|
|
input io_dec_exu_decode_exu_i0_ap_predict_t,
|
|
input io_dec_exu_decode_exu_i0_ap_predict_nt,
|
|
input io_dec_exu_decode_exu_i0_ap_csr_write,
|
|
input io_dec_exu_decode_exu_i0_ap_csr_imm,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_valid,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4,
|
|
input [1:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist,
|
|
input [11:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way,
|
|
input io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret,
|
|
input [30:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett,
|
|
input [7:0] io_dec_exu_decode_exu_i0_predict_fghr_d,
|
|
input [7:0] io_dec_exu_decode_exu_i0_predict_index_d,
|
|
input [4:0] io_dec_exu_decode_exu_i0_predict_btag_d,
|
|
input io_dec_exu_decode_exu_dec_i0_rs1_en_d,
|
|
input io_dec_exu_decode_exu_dec_i0_branch_d,
|
|
input io_dec_exu_decode_exu_dec_i0_rs2_en_d,
|
|
input [31:0] io_dec_exu_decode_exu_dec_i0_immed_d,
|
|
input [31:0] io_dec_exu_decode_exu_dec_i0_result_r,
|
|
input io_dec_exu_decode_exu_dec_qual_lsu_d,
|
|
input io_dec_exu_decode_exu_dec_i0_select_pc_d,
|
|
input [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d,
|
|
input [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d,
|
|
input io_dec_exu_decode_exu_mul_p_valid,
|
|
input io_dec_exu_decode_exu_mul_p_bits_rs1_sign,
|
|
input io_dec_exu_decode_exu_mul_p_bits_rs2_sign,
|
|
input io_dec_exu_decode_exu_mul_p_bits_low,
|
|
input [30:0] io_dec_exu_decode_exu_pred_correct_npc_x,
|
|
input io_dec_exu_decode_exu_dec_extint_stall,
|
|
output [31:0] io_dec_exu_decode_exu_exu_i0_result_x,
|
|
output [31:0] io_dec_exu_decode_exu_exu_csr_rs1_x,
|
|
input [29:0] io_dec_exu_tlu_exu_dec_tlu_meihap,
|
|
input io_dec_exu_tlu_exu_dec_tlu_flush_lower_r,
|
|
input [30:0] io_dec_exu_tlu_exu_dec_tlu_flush_path_r,
|
|
output [1:0] io_dec_exu_tlu_exu_exu_i0_br_hist_r,
|
|
output io_dec_exu_tlu_exu_exu_i0_br_error_r,
|
|
output io_dec_exu_tlu_exu_exu_i0_br_start_error_r,
|
|
output [7:0] io_dec_exu_tlu_exu_exu_i0_br_index_r,
|
|
output io_dec_exu_tlu_exu_exu_i0_br_valid_r,
|
|
output io_dec_exu_tlu_exu_exu_i0_br_mp_r,
|
|
output io_dec_exu_tlu_exu_exu_i0_br_middle_r,
|
|
output io_dec_exu_tlu_exu_exu_pmu_i0_br_misp,
|
|
output io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken,
|
|
output io_dec_exu_tlu_exu_exu_pmu_i0_pc4,
|
|
output [30:0] io_dec_exu_tlu_exu_exu_npc_r,
|
|
input [30:0] io_dec_exu_ib_exu_dec_i0_pc_d,
|
|
input io_dec_exu_ib_exu_dec_debug_wdata_rs1_d,
|
|
input [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d,
|
|
input [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d,
|
|
output [7:0] io_exu_bp_exu_i0_br_fghr_r,
|
|
output io_exu_bp_exu_i0_br_way_r,
|
|
output io_exu_bp_exu_mp_pkt_valid,
|
|
output io_exu_bp_exu_mp_pkt_bits_misp,
|
|
output io_exu_bp_exu_mp_pkt_bits_ataken,
|
|
output io_exu_bp_exu_mp_pkt_bits_boffset,
|
|
output io_exu_bp_exu_mp_pkt_bits_pc4,
|
|
output [1:0] io_exu_bp_exu_mp_pkt_bits_hist,
|
|
output [11:0] io_exu_bp_exu_mp_pkt_bits_toffset,
|
|
output io_exu_bp_exu_mp_pkt_bits_pcall,
|
|
output io_exu_bp_exu_mp_pkt_bits_pja,
|
|
output io_exu_bp_exu_mp_pkt_bits_way,
|
|
output io_exu_bp_exu_mp_pkt_bits_pret,
|
|
output [7:0] io_exu_bp_exu_mp_eghr,
|
|
output [7:0] io_exu_bp_exu_mp_fghr,
|
|
output [7:0] io_exu_bp_exu_mp_index,
|
|
output [4:0] io_exu_bp_exu_mp_btag,
|
|
output io_exu_flush_final,
|
|
output [31:0] io_exu_div_result,
|
|
output io_exu_div_wren,
|
|
input [31:0] io_dbg_cmd_wrdata,
|
|
input [31:0] io_dec_csr_rddata_d,
|
|
input [31:0] io_lsu_nonblock_load_data,
|
|
output [31:0] io_lsu_exu_exu_lsu_rs1_d,
|
|
output [31:0] io_lsu_exu_exu_lsu_rs2_d,
|
|
input [31:0] io_lsu_exu_lsu_result_m,
|
|
output [30:0] io_exu_flush_path_final
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire i_alu_clock; // @[exu.scala 130:19]
|
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wire i_alu_reset; // @[exu.scala 130:19]
|
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wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:19]
|
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wire i_alu_io_dec_alu_dec_csr_ren_d; // @[exu.scala 130:19]
|
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wire [11:0] i_alu_io_dec_alu_dec_i0_br_immed_d; // @[exu.scala 130:19]
|
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wire [30:0] i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:19]
|
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wire [31:0] i_alu_io_csr_rddata_in; // @[exu.scala 130:19]
|
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wire [30:0] i_alu_io_dec_i0_pc_d; // @[exu.scala 130:19]
|
|
wire i_alu_io_flush_upper_x; // @[exu.scala 130:19]
|
|
wire i_alu_io_dec_tlu_flush_lower_r; // @[exu.scala 130:19]
|
|
wire i_alu_io_enable; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_clz; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_ctz; // @[exu.scala 130:19]
|
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wire i_alu_io_i0_ap_pcnt; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sext_b; // @[exu.scala 130:19]
|
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wire i_alu_io_i0_ap_sext_h; // @[exu.scala 130:19]
|
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wire i_alu_io_i0_ap_min; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_max; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_pack; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_packu; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_packh; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_rol; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_ror; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_grev; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_gorc; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_zbb; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sbset; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sbclr; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sbinv; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sbext; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_land; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_lor; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_lxor; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sll; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_srl; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sra; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_beq; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_bne; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_blt; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_bge; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_add; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_sub; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_slt; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_unsign; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_jal; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_predict_t; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_predict_nt; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_csr_write; // @[exu.scala 130:19]
|
|
wire i_alu_io_i0_ap_csr_imm; // @[exu.scala 130:19]
|
|
wire [31:0] i_alu_io_a_in; // @[exu.scala 130:19]
|
|
wire [31:0] i_alu_io_b_in; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_valid; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_boffset; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_pc4; // @[exu.scala 130:19]
|
|
wire [1:0] i_alu_io_pp_in_bits_hist; // @[exu.scala 130:19]
|
|
wire [11:0] i_alu_io_pp_in_bits_toffset; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_br_error; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_br_start_error; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_pcall; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_pja; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_way; // @[exu.scala 130:19]
|
|
wire i_alu_io_pp_in_bits_pret; // @[exu.scala 130:19]
|
|
wire [30:0] i_alu_io_pp_in_bits_prett; // @[exu.scala 130:19]
|
|
wire [31:0] i_alu_io_result_ff; // @[exu.scala 130:19]
|
|
wire i_alu_io_flush_upper_out; // @[exu.scala 130:19]
|
|
wire i_alu_io_flush_final_out; // @[exu.scala 130:19]
|
|
wire [30:0] i_alu_io_flush_path_out; // @[exu.scala 130:19]
|
|
wire i_alu_io_pred_correct_out; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_valid; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_misp; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 130:19]
|
|
wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[exu.scala 130:19]
|
|
wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_pja; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_way; // @[exu.scala 130:19]
|
|
wire i_alu_io_predict_p_out_bits_pret; // @[exu.scala 130:19]
|
|
wire i_mul_clock; // @[exu.scala 150:21]
|
|
wire i_mul_reset; // @[exu.scala 150:21]
|
|
wire i_mul_io_mul_p_valid; // @[exu.scala 150:21]
|
|
wire i_mul_io_mul_p_bits_rs1_sign; // @[exu.scala 150:21]
|
|
wire i_mul_io_mul_p_bits_rs2_sign; // @[exu.scala 150:21]
|
|
wire i_mul_io_mul_p_bits_low; // @[exu.scala 150:21]
|
|
wire [31:0] i_mul_io_rs1_in; // @[exu.scala 150:21]
|
|
wire [31:0] i_mul_io_rs2_in; // @[exu.scala 150:21]
|
|
wire [31:0] i_mul_io_result_x; // @[exu.scala 150:21]
|
|
wire i_div_clock; // @[exu.scala 158:21]
|
|
wire i_div_reset; // @[exu.scala 158:21]
|
|
wire [31:0] i_div_io_dividend; // @[exu.scala 158:21]
|
|
wire [31:0] i_div_io_divisor; // @[exu.scala 158:21]
|
|
wire [31:0] i_div_io_exu_div_result; // @[exu.scala 158:21]
|
|
wire i_div_io_exu_div_wren; // @[exu.scala 158:21]
|
|
wire i_div_io_dec_div_div_p_valid; // @[exu.scala 158:21]
|
|
wire i_div_io_dec_div_div_p_bits_unsign; // @[exu.scala 158:21]
|
|
wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 158:21]
|
|
wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 158:21]
|
|
wire x_data_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 55:69]
|
|
wire x_data_en_q1 = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 56:73]
|
|
wire x_data_en_q2 = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[exu.scala 57:73]
|
|
wire r_data_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[exu.scala 58:69]
|
|
reg i0_branch_x; // @[Reg.scala 27:20]
|
|
wire r_data_en_q2 = r_data_en & i0_branch_x; // @[exu.scala 59:73]
|
|
wire x_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[exu.scala 60:68]
|
|
wire r_ctl_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[exu.scala 61:68]
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|
wire [20:0] predpipe_d = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d,io_dec_exu_decode_exu_i0_predict_btag_d}; // @[Cat.scala 29:58]
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|
reg [30:0] i0_flush_path_x; // @[Reg.scala 27:20]
|
|
wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[exu.scala 41:53 exu.scala 145:45]
|
|
reg i0_predict_p_x_valid; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_misp; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_ataken; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_boffset; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_pc4; // @[Reg.scala 27:20]
|
|
reg [1:0] i0_predict_p_x_bits_hist; // @[Reg.scala 27:20]
|
|
reg [11:0] i0_predict_p_x_bits_toffset; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_br_error; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_br_start_error; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_pcall; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_pja; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_way; // @[Reg.scala 27:20]
|
|
reg i0_predict_p_x_bits_pret; // @[Reg.scala 27:20]
|
|
wire i0_predict_p_d_bits_pret = i_alu_io_predict_p_out_bits_pret; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_way = i_alu_io_predict_p_out_bits_way; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_pja = i_alu_io_predict_p_out_bits_pja; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_pcall = i_alu_io_predict_p_out_bits_pcall; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_br_start_error = i_alu_io_predict_p_out_bits_br_start_error; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_br_error = i_alu_io_predict_p_out_bits_br_error; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire [11:0] i0_predict_p_d_bits_toffset = i_alu_io_predict_p_out_bits_toffset; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire [1:0] i0_predict_p_d_bits_hist = i_alu_io_predict_p_out_bits_hist; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_pc4 = i_alu_io_predict_p_out_bits_pc4; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_boffset = i_alu_io_predict_p_out_bits_boffset; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_bits_misp = i_alu_io_predict_p_out_bits_misp; // @[exu.scala 42:53 exu.scala 147:45]
|
|
wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 42:53 exu.scala 147:45]
|
|
reg [20:0] predpipe_x; // @[Reg.scala 27:20]
|
|
reg [20:0] predpipe_r; // @[Reg.scala 27:20]
|
|
reg [7:0] ghr_x; // @[Reg.scala 27:20]
|
|
reg i0_valid_x; // @[Reg.scala 27:20]
|
|
reg i0_taken_x; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58]
|
|
reg i0_pred_correct_upper_x; // @[Reg.scala 27:20]
|
|
wire i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 148:27]
|
|
reg i0_flush_upper_x; // @[Reg.scala 27:20]
|
|
wire i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 144:35]
|
|
wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 176:59]
|
|
wire _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 175:54]
|
|
wire _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 175:97]
|
|
wire i0_valid_d = _T_169 & _T_170; // @[exu.scala 175:95]
|
|
reg i0_pp_r_valid; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_misp; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_ataken; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_boffset; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_pc4; // @[Reg.scala 27:20]
|
|
reg [1:0] i0_pp_r_bits_hist; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_br_error; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_br_start_error; // @[Reg.scala 27:20]
|
|
reg i0_pp_r_bits_way; // @[Reg.scala 27:20]
|
|
reg [5:0] pred_temp1; // @[Reg.scala 27:20]
|
|
reg i0_pred_correct_upper_r; // @[Reg.scala 27:20]
|
|
reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20]
|
|
reg [24:0] pred_temp2; // @[Reg.scala 27:20]
|
|
wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58]
|
|
wire _T_174 = _T_170 & i0_valid_d; // @[exu.scala 182:50]
|
|
reg [7:0] ghr_d; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72]
|
|
wire _T_179 = ~i0_valid_d; // @[exu.scala 183:52]
|
|
wire _T_180 = _T_170 & _T_179; // @[exu.scala 183:50]
|
|
wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] ghr_d_ns = _T_186 | _T_185; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 466:21]
|
|
wire _T_34 = |_T_33; // @[lib.scala 466:29]
|
|
reg mul_valid_x; // @[Reg.scala 27:20]
|
|
wire _T_37 = io_dec_exu_decode_exu_mul_p_valid ^ mul_valid_x; // @[lib.scala 488:21]
|
|
wire _T_38 = |_T_37; // @[lib.scala 488:29]
|
|
wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 466:21]
|
|
wire _T_42 = |_T_41; // @[lib.scala 466:29]
|
|
wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 83:84]
|
|
wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 83:134]
|
|
wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 83:184]
|
|
wire _T_52 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 84:84]
|
|
wire _T_54 = _T_52 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2]; // @[exu.scala 84:134]
|
|
wire i0_rs2_bypass_en_d = _T_54 | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3]; // @[exu.scala 84:184]
|
|
wire [31:0] _T_64 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_65 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_66 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_67 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3] ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_68 = _T_64 | _T_65; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_69 = _T_68 | _T_66; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs1_bypass_data_d = _T_69 | _T_67; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_79 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] ? io_dec_exu_decode_exu_dec_i0_result_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_80 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1] ? io_lsu_exu_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_81 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[2] ? io_dec_exu_decode_exu_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_82 = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[3] ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_83 = _T_79 | _T_80; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_84 = _T_83 | _T_81; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs2_bypass_data_d = _T_84 | _T_82; // @[Mux.scala 27:72]
|
|
wire _T_87 = ~i0_rs1_bypass_en_d; // @[exu.scala 101:6]
|
|
wire _T_88 = _T_87 & io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[exu.scala 101:26]
|
|
wire [31:0] _T_90 = {io_dec_exu_ib_exu_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_92 = _T_87 & io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 102:26]
|
|
wire _T_95 = ~io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[exu.scala 103:28]
|
|
wire _T_96 = _T_87 & _T_95; // @[exu.scala 103:26]
|
|
wire _T_97 = _T_96 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 103:69]
|
|
wire [31:0] _T_99 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_100 = _T_88 ? _T_90 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_101 = _T_92 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_102 = _T_97 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_103 = _T_99 | _T_100; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_104 = _T_103 | _T_101; // @[Mux.scala 27:72]
|
|
wire [31:0] i0_rs1_d = _T_104 | _T_102; // @[Mux.scala 27:72]
|
|
reg [31:0] _T_107; // @[Reg.scala 27:20]
|
|
wire _T_108 = ~i0_rs2_bypass_en_d; // @[exu.scala 108:6]
|
|
wire _T_109 = _T_108 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 108:26]
|
|
wire [31:0] _T_114 = _T_109 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_115 = _T_108 ? io_dec_exu_decode_exu_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_116 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_117 = _T_114 | _T_115; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_118 = _T_117 | _T_116; // @[Mux.scala 27:72]
|
|
wire _T_120 = ~io_dec_exu_decode_exu_dec_extint_stall; // @[exu.scala 115:28]
|
|
wire _T_121 = _T_87 & _T_120; // @[exu.scala 115:26]
|
|
wire _T_122 = _T_121 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 115:68]
|
|
wire _T_123 = _T_122 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 115:108]
|
|
wire _T_126 = i0_rs1_bypass_en_d & _T_120; // @[exu.scala 116:25]
|
|
wire _T_127 = _T_126 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 116:67]
|
|
wire _T_129 = io_dec_exu_decode_exu_dec_extint_stall & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 117:45]
|
|
wire [31:0] _T_131 = {io_dec_exu_tlu_exu_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_132 = _T_123 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_133 = _T_127 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_134 = _T_129 ? _T_131 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_135 = _T_132 | _T_133; // @[Mux.scala 27:72]
|
|
wire _T_140 = _T_108 & _T_120; // @[exu.scala 121:26]
|
|
wire _T_141 = _T_140 & io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[exu.scala 121:68]
|
|
wire _T_142 = _T_141 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 121:108]
|
|
wire _T_145 = i0_rs2_bypass_en_d & _T_120; // @[exu.scala 122:25]
|
|
wire _T_146 = _T_145 & io_dec_exu_decode_exu_dec_qual_lsu_d; // @[exu.scala 122:67]
|
|
wire [31:0] _T_148 = _T_142 ? io_dec_exu_gpr_exu_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_149 = _T_146 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 126:26]
|
|
wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72]
|
|
wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 201:48]
|
|
wire _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 203:75]
|
|
wire _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 242:48]
|
|
wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72]
|
|
wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 78:45]
|
|
wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 244:55]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
exu_alu_ctl i_alu ( // @[exu.scala 130:19]
|
|
.clock(i_alu_clock),
|
|
.reset(i_alu_reset),
|
|
.io_dec_alu_dec_i0_alu_decode_d(i_alu_io_dec_alu_dec_i0_alu_decode_d),
|
|
.io_dec_alu_dec_csr_ren_d(i_alu_io_dec_alu_dec_csr_ren_d),
|
|
.io_dec_alu_dec_i0_br_immed_d(i_alu_io_dec_alu_dec_i0_br_immed_d),
|
|
.io_dec_alu_exu_i0_pc_x(i_alu_io_dec_alu_exu_i0_pc_x),
|
|
.io_csr_rddata_in(i_alu_io_csr_rddata_in),
|
|
.io_dec_i0_pc_d(i_alu_io_dec_i0_pc_d),
|
|
.io_flush_upper_x(i_alu_io_flush_upper_x),
|
|
.io_dec_tlu_flush_lower_r(i_alu_io_dec_tlu_flush_lower_r),
|
|
.io_enable(i_alu_io_enable),
|
|
.io_i0_ap_clz(i_alu_io_i0_ap_clz),
|
|
.io_i0_ap_ctz(i_alu_io_i0_ap_ctz),
|
|
.io_i0_ap_pcnt(i_alu_io_i0_ap_pcnt),
|
|
.io_i0_ap_sext_b(i_alu_io_i0_ap_sext_b),
|
|
.io_i0_ap_sext_h(i_alu_io_i0_ap_sext_h),
|
|
.io_i0_ap_min(i_alu_io_i0_ap_min),
|
|
.io_i0_ap_max(i_alu_io_i0_ap_max),
|
|
.io_i0_ap_pack(i_alu_io_i0_ap_pack),
|
|
.io_i0_ap_packu(i_alu_io_i0_ap_packu),
|
|
.io_i0_ap_packh(i_alu_io_i0_ap_packh),
|
|
.io_i0_ap_rol(i_alu_io_i0_ap_rol),
|
|
.io_i0_ap_ror(i_alu_io_i0_ap_ror),
|
|
.io_i0_ap_grev(i_alu_io_i0_ap_grev),
|
|
.io_i0_ap_gorc(i_alu_io_i0_ap_gorc),
|
|
.io_i0_ap_zbb(i_alu_io_i0_ap_zbb),
|
|
.io_i0_ap_sbset(i_alu_io_i0_ap_sbset),
|
|
.io_i0_ap_sbclr(i_alu_io_i0_ap_sbclr),
|
|
.io_i0_ap_sbinv(i_alu_io_i0_ap_sbinv),
|
|
.io_i0_ap_sbext(i_alu_io_i0_ap_sbext),
|
|
.io_i0_ap_land(i_alu_io_i0_ap_land),
|
|
.io_i0_ap_lor(i_alu_io_i0_ap_lor),
|
|
.io_i0_ap_lxor(i_alu_io_i0_ap_lxor),
|
|
.io_i0_ap_sll(i_alu_io_i0_ap_sll),
|
|
.io_i0_ap_srl(i_alu_io_i0_ap_srl),
|
|
.io_i0_ap_sra(i_alu_io_i0_ap_sra),
|
|
.io_i0_ap_beq(i_alu_io_i0_ap_beq),
|
|
.io_i0_ap_bne(i_alu_io_i0_ap_bne),
|
|
.io_i0_ap_blt(i_alu_io_i0_ap_blt),
|
|
.io_i0_ap_bge(i_alu_io_i0_ap_bge),
|
|
.io_i0_ap_add(i_alu_io_i0_ap_add),
|
|
.io_i0_ap_sub(i_alu_io_i0_ap_sub),
|
|
.io_i0_ap_slt(i_alu_io_i0_ap_slt),
|
|
.io_i0_ap_unsign(i_alu_io_i0_ap_unsign),
|
|
.io_i0_ap_jal(i_alu_io_i0_ap_jal),
|
|
.io_i0_ap_predict_t(i_alu_io_i0_ap_predict_t),
|
|
.io_i0_ap_predict_nt(i_alu_io_i0_ap_predict_nt),
|
|
.io_i0_ap_csr_write(i_alu_io_i0_ap_csr_write),
|
|
.io_i0_ap_csr_imm(i_alu_io_i0_ap_csr_imm),
|
|
.io_a_in(i_alu_io_a_in),
|
|
.io_b_in(i_alu_io_b_in),
|
|
.io_pp_in_valid(i_alu_io_pp_in_valid),
|
|
.io_pp_in_bits_boffset(i_alu_io_pp_in_bits_boffset),
|
|
.io_pp_in_bits_pc4(i_alu_io_pp_in_bits_pc4),
|
|
.io_pp_in_bits_hist(i_alu_io_pp_in_bits_hist),
|
|
.io_pp_in_bits_toffset(i_alu_io_pp_in_bits_toffset),
|
|
.io_pp_in_bits_br_error(i_alu_io_pp_in_bits_br_error),
|
|
.io_pp_in_bits_br_start_error(i_alu_io_pp_in_bits_br_start_error),
|
|
.io_pp_in_bits_pcall(i_alu_io_pp_in_bits_pcall),
|
|
.io_pp_in_bits_pja(i_alu_io_pp_in_bits_pja),
|
|
.io_pp_in_bits_way(i_alu_io_pp_in_bits_way),
|
|
.io_pp_in_bits_pret(i_alu_io_pp_in_bits_pret),
|
|
.io_pp_in_bits_prett(i_alu_io_pp_in_bits_prett),
|
|
.io_result_ff(i_alu_io_result_ff),
|
|
.io_flush_upper_out(i_alu_io_flush_upper_out),
|
|
.io_flush_final_out(i_alu_io_flush_final_out),
|
|
.io_flush_path_out(i_alu_io_flush_path_out),
|
|
.io_pred_correct_out(i_alu_io_pred_correct_out),
|
|
.io_predict_p_out_valid(i_alu_io_predict_p_out_valid),
|
|
.io_predict_p_out_bits_misp(i_alu_io_predict_p_out_bits_misp),
|
|
.io_predict_p_out_bits_ataken(i_alu_io_predict_p_out_bits_ataken),
|
|
.io_predict_p_out_bits_boffset(i_alu_io_predict_p_out_bits_boffset),
|
|
.io_predict_p_out_bits_pc4(i_alu_io_predict_p_out_bits_pc4),
|
|
.io_predict_p_out_bits_hist(i_alu_io_predict_p_out_bits_hist),
|
|
.io_predict_p_out_bits_toffset(i_alu_io_predict_p_out_bits_toffset),
|
|
.io_predict_p_out_bits_br_error(i_alu_io_predict_p_out_bits_br_error),
|
|
.io_predict_p_out_bits_br_start_error(i_alu_io_predict_p_out_bits_br_start_error),
|
|
.io_predict_p_out_bits_pcall(i_alu_io_predict_p_out_bits_pcall),
|
|
.io_predict_p_out_bits_pja(i_alu_io_predict_p_out_bits_pja),
|
|
.io_predict_p_out_bits_way(i_alu_io_predict_p_out_bits_way),
|
|
.io_predict_p_out_bits_pret(i_alu_io_predict_p_out_bits_pret)
|
|
);
|
|
exu_mul_ctl i_mul ( // @[exu.scala 150:21]
|
|
.clock(i_mul_clock),
|
|
.reset(i_mul_reset),
|
|
.io_mul_p_valid(i_mul_io_mul_p_valid),
|
|
.io_mul_p_bits_rs1_sign(i_mul_io_mul_p_bits_rs1_sign),
|
|
.io_mul_p_bits_rs2_sign(i_mul_io_mul_p_bits_rs2_sign),
|
|
.io_mul_p_bits_low(i_mul_io_mul_p_bits_low),
|
|
.io_rs1_in(i_mul_io_rs1_in),
|
|
.io_rs2_in(i_mul_io_rs2_in),
|
|
.io_result_x(i_mul_io_result_x)
|
|
);
|
|
exu_div_ctl i_div ( // @[exu.scala 158:21]
|
|
.clock(i_div_clock),
|
|
.reset(i_div_reset),
|
|
.io_dividend(i_div_io_dividend),
|
|
.io_divisor(i_div_io_divisor),
|
|
.io_exu_div_result(i_div_io_exu_div_result),
|
|
.io_exu_div_wren(i_div_io_exu_div_wren),
|
|
.io_dec_div_div_p_valid(i_div_io_dec_div_div_p_valid),
|
|
.io_dec_div_div_p_bits_unsign(i_div_io_dec_div_div_p_bits_unsign),
|
|
.io_dec_div_div_p_bits_rem(i_div_io_dec_div_div_p_bits_rem),
|
|
.io_dec_div_dec_div_cancel(i_div_io_dec_div_dec_div_cancel)
|
|
);
|
|
assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 131:20]
|
|
assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 166:57]
|
|
assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 105:57]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 193:43]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 194:43]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 196:48]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 198:43]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_valid_r = i0_pp_r_valid; // @[exu.scala 190:43]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[exu.scala 191:43]
|
|
assign io_dec_exu_tlu_exu_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[exu.scala 195:43]
|
|
assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 170:47]
|
|
assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 171:47]
|
|
assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 172:47]
|
|
assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 244:49]
|
|
assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 197:43]
|
|
assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 192:43]
|
|
assign io_exu_bp_exu_mp_pkt_valid = i0_flush_upper_x & i0_predict_p_x_valid; // @[exu.scala 52:53 exu.scala 205:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 207:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[exu.scala 211:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[exu.scala 212:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[exu.scala 213:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[exu.scala 214:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[exu.scala 215:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_pcall = i0_flush_upper_x & i0_predict_p_x_bits_pcall; // @[exu.scala 208:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_pja = i0_flush_upper_x & i0_predict_p_x_bits_pja; // @[exu.scala 209:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_way = i0_flush_upper_x & i0_predict_p_x_bits_way; // @[exu.scala 206:39]
|
|
assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 210:39]
|
|
assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 219:39]
|
|
assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 216:39]
|
|
assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 217:39]
|
|
assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 218:39]
|
|
assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 146:27]
|
|
assign io_exu_div_result = i_div_io_exu_div_result; // @[exu.scala 164:33]
|
|
assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 163:41]
|
|
assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 114:27]
|
|
assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 120:27]
|
|
assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 240:33]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = r_data_en & i0_branch_x; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 425:17]
|
|
assign i_alu_clock = clock;
|
|
assign i_alu_reset = reset;
|
|
assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 131:20]
|
|
assign i_alu_io_dec_alu_dec_csr_ren_d = io_dec_exu_dec_alu_dec_csr_ren_d; // @[exu.scala 131:20]
|
|
assign i_alu_io_dec_alu_dec_i0_br_immed_d = io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[exu.scala 131:20]
|
|
assign i_alu_io_csr_rddata_in = io_dec_csr_rddata_d; // @[exu.scala 137:33]
|
|
assign i_alu_io_dec_i0_pc_d = io_dec_exu_ib_exu_dec_i0_pc_d; // @[exu.scala 141:33]
|
|
assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[exu.scala 136:33]
|
|
assign i_alu_io_dec_tlu_flush_lower_r = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 138:41]
|
|
assign i_alu_io_enable = io_dec_exu_decode_exu_dec_data_en[1]; // @[exu.scala 134:45]
|
|
assign i_alu_io_i0_ap_clz = io_dec_exu_decode_exu_i0_ap_clz; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_ctz = io_dec_exu_decode_exu_i0_ap_ctz; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_pcnt = io_dec_exu_decode_exu_i0_ap_pcnt; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sext_b = io_dec_exu_decode_exu_i0_ap_sext_b; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sext_h = io_dec_exu_decode_exu_i0_ap_sext_h; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_min = io_dec_exu_decode_exu_i0_ap_min; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_max = io_dec_exu_decode_exu_i0_ap_max; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_pack = io_dec_exu_decode_exu_i0_ap_pack; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_packu = io_dec_exu_decode_exu_i0_ap_packu; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_packh = io_dec_exu_decode_exu_i0_ap_packh; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_rol = io_dec_exu_decode_exu_i0_ap_rol; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_ror = io_dec_exu_decode_exu_i0_ap_ror; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_grev = io_dec_exu_decode_exu_i0_ap_grev; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_gorc = io_dec_exu_decode_exu_i0_ap_gorc; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_zbb = io_dec_exu_decode_exu_i0_ap_zbb; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sbset = io_dec_exu_decode_exu_i0_ap_sbset; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sbclr = io_dec_exu_decode_exu_i0_ap_sbclr; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sbinv = io_dec_exu_decode_exu_i0_ap_sbinv; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sbext = io_dec_exu_decode_exu_i0_ap_sbext; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_land = io_dec_exu_decode_exu_i0_ap_land; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_lor = io_dec_exu_decode_exu_i0_ap_lor; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_lxor = io_dec_exu_decode_exu_i0_ap_lxor; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sll = io_dec_exu_decode_exu_i0_ap_sll; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_srl = io_dec_exu_decode_exu_i0_ap_srl; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sra = io_dec_exu_decode_exu_i0_ap_sra; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_beq = io_dec_exu_decode_exu_i0_ap_beq; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_bne = io_dec_exu_decode_exu_i0_ap_bne; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_blt = io_dec_exu_decode_exu_i0_ap_blt; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_bge = io_dec_exu_decode_exu_i0_ap_bge; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_add = io_dec_exu_decode_exu_i0_ap_add; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_sub = io_dec_exu_decode_exu_i0_ap_sub; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_slt = io_dec_exu_decode_exu_i0_ap_slt; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_unsign = io_dec_exu_decode_exu_i0_ap_unsign; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_jal = io_dec_exu_decode_exu_i0_ap_jal; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_predict_t = io_dec_exu_decode_exu_i0_ap_predict_t; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_predict_nt = io_dec_exu_decode_exu_i0_ap_predict_nt; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_csr_write = io_dec_exu_decode_exu_i0_ap_csr_write; // @[exu.scala 142:51]
|
|
assign i_alu_io_i0_ap_csr_imm = io_dec_exu_decode_exu_i0_ap_csr_imm; // @[exu.scala 142:51]
|
|
assign i_alu_io_a_in = _T_104 | _T_102; // @[exu.scala 139:39]
|
|
assign i_alu_io_b_in = i0_rs2_d; // @[exu.scala 140:39]
|
|
assign i_alu_io_pp_in_valid = io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_boffset = io_dec_exu_ib_exu_dec_i0_pc_d[0]; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_pc4 = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_hist = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_toffset = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_br_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_br_start_error = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_pcall = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_pja = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_way = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_pret = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[exu.scala 135:45]
|
|
assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 135:45]
|
|
assign i_mul_clock = clock;
|
|
assign i_mul_reset = reset;
|
|
assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 152:23]
|
|
assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 152:23]
|
|
assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 152:23]
|
|
assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 152:23]
|
|
assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 154:41]
|
|
assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 155:41]
|
|
assign i_div_clock = clock;
|
|
assign i_div_reset = reset;
|
|
assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 161:33]
|
|
assign i_div_io_divisor = i0_rs2_d; // @[exu.scala 162:33]
|
|
assign i_div_io_dec_div_div_p_valid = io_dec_exu_dec_div_div_p_valid; // @[exu.scala 159:20]
|
|
assign i_div_io_dec_div_div_p_bits_unsign = io_dec_exu_dec_div_div_p_bits_unsign; // @[exu.scala 159:20]
|
|
assign i_div_io_dec_div_div_p_bits_rem = io_dec_exu_dec_div_div_p_bits_rem; // @[exu.scala 159:20]
|
|
assign i_div_io_dec_div_dec_div_cancel = io_dec_exu_dec_div_dec_div_cancel; // @[exu.scala 159:20]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
i0_branch_x = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
i0_flush_path_x = _RAND_1[30:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
i0_predict_p_x_valid = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_misp = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_ataken = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_boffset = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pc4 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_hist = _RAND_7[1:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_toffset = _RAND_8[11:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_br_error = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_br_start_error = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pcall = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pja = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_way = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
i0_predict_p_x_bits_pret = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
predpipe_x = _RAND_15[20:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
predpipe_r = _RAND_16[20:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
ghr_x = _RAND_17[7:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
i0_valid_x = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
i0_taken_x = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
i0_pred_correct_upper_x = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
i0_flush_upper_x = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
i0_pp_r_valid = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
i0_pp_r_bits_misp = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
i0_pp_r_bits_ataken = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
i0_pp_r_bits_boffset = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
i0_pp_r_bits_pc4 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
i0_pp_r_bits_hist = _RAND_27[1:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
i0_pp_r_bits_br_error = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
i0_pp_r_bits_br_start_error = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
i0_pp_r_bits_way = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
pred_temp1 = _RAND_31[5:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
i0_pred_correct_upper_r = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
i0_flush_path_upper_r = _RAND_33[30:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
pred_temp2 = _RAND_34[24:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
ghr_d = _RAND_35[7:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
mul_valid_x = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_107 = _RAND_37[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
i0_branch_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_flush_path_x = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_misp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_ataken = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_boffset = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pc4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_hist = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_toffset = 12'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_start_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pcall = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pja = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_way = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pret = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
predpipe_x = 21'h0;
|
|
end
|
|
if (reset) begin
|
|
predpipe_r = 21'h0;
|
|
end
|
|
if (reset) begin
|
|
ghr_x = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_valid_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_taken_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pred_correct_upper_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_flush_upper_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_misp = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_ataken = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_boffset = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_pc4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_hist = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_start_error = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pp_r_bits_way = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
pred_temp1 = 6'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_pred_correct_upper_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
i0_flush_path_upper_r = 31'h0;
|
|
end
|
|
if (reset) begin
|
|
pred_temp2 = 25'h0;
|
|
end
|
|
if (reset) begin
|
|
ghr_d = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
mul_valid_x = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_107 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_branch_x <= 1'h0;
|
|
end else if (_T_42) begin
|
|
i0_branch_x <= io_dec_exu_decode_exu_dec_i0_branch_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_path_x <= 31'h0;
|
|
end else if (x_data_en) begin
|
|
i0_flush_path_x <= i0_flush_path_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_valid <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_valid <= i0_predict_p_d_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_misp <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_misp <= i0_predict_p_d_bits_misp;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_ataken <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_ataken <= i0_predict_p_d_bits_ataken;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_boffset <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_boffset <= i0_predict_p_d_bits_boffset;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pc4 <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_pc4 <= i0_predict_p_d_bits_pc4;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_hist <= 2'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_hist <= i0_predict_p_d_bits_hist;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_toffset <= 12'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_toffset <= i0_predict_p_d_bits_toffset;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_error <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_br_error <= i0_predict_p_d_bits_br_error;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_br_start_error <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_br_start_error <= i0_predict_p_d_bits_br_start_error;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pcall <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_pcall <= i0_predict_p_d_bits_pcall;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pja <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_pja <= i0_predict_p_d_bits_pja;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_way <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_way <= i0_predict_p_d_bits_way;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_predict_p_x_bits_pret <= 1'h0;
|
|
end else if (x_data_en) begin
|
|
i0_predict_p_x_bits_pret <= i0_predict_p_d_bits_pret;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
predpipe_x <= 21'h0;
|
|
end else if (x_data_en_q2) begin
|
|
predpipe_x <= predpipe_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
predpipe_r <= 21'h0;
|
|
end else if (r_data_en_q2) begin
|
|
predpipe_r <= predpipe_x;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ghr_x <= 8'h0;
|
|
end else if (x_ctl_en) begin
|
|
if (i0_valid_x) begin
|
|
ghr_x <= _T_191;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_valid_x <= 1'h0;
|
|
end else if (x_ctl_en) begin
|
|
i0_valid_x <= i0_valid_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_taken_x <= 1'h0;
|
|
end else if (x_ctl_en) begin
|
|
i0_taken_x <= i0_taken_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pred_correct_upper_x <= 1'h0;
|
|
end else if (x_ctl_en) begin
|
|
i0_pred_correct_upper_x <= i0_pred_correct_upper_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_upper_x <= 1'h0;
|
|
end else if (x_ctl_en) begin
|
|
i0_flush_upper_x <= i0_flush_upper_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_valid <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_valid <= i0_predict_p_x_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_misp <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_misp <= i0_predict_p_x_bits_misp;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_ataken <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_ataken <= i0_predict_p_x_bits_ataken;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_boffset <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_boffset <= i0_predict_p_x_bits_boffset;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_pc4 <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_pc4 <= i0_predict_p_x_bits_pc4;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_hist <= 2'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_hist <= i0_predict_p_x_bits_hist;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_error <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_br_error <= i0_predict_p_x_bits_br_error;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_br_start_error <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_br_start_error <= i0_predict_p_x_bits_br_start_error;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pp_r_bits_way <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pp_r_bits_way <= i0_predict_p_x_bits_way;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
pred_temp1 <= 6'h0;
|
|
end else if (r_data_en) begin
|
|
pred_temp1 <= io_dec_exu_decode_exu_pred_correct_npc_x[5:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_pred_correct_upper_r <= 1'h0;
|
|
end else if (r_ctl_en) begin
|
|
i0_pred_correct_upper_r <= i0_pred_correct_upper_x;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
i0_flush_path_upper_r <= 31'h0;
|
|
end else if (r_data_en) begin
|
|
i0_flush_path_upper_r <= i0_flush_path_x;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
pred_temp2 <= 25'h0;
|
|
end else if (r_data_en) begin
|
|
pred_temp2 <= io_dec_exu_decode_exu_pred_correct_npc_x[30:6];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ghr_d <= 8'h0;
|
|
end else if (_T_34) begin
|
|
ghr_d <= ghr_d_ns;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
mul_valid_x <= 1'h0;
|
|
end else if (_T_38) begin
|
|
mul_valid_x <= io_dec_exu_decode_exu_mul_p_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_107 <= 32'h0;
|
|
end else if (x_data_en_q1) begin
|
|
_T_107 <= i0_rs1_d;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_addrcheck(
|
|
input reset,
|
|
input io_lsu_c2_m_clk,
|
|
input [31:0] io_start_addr_d,
|
|
input [31:0] io_end_addr_d,
|
|
input io_lsu_pkt_d_valid,
|
|
input io_lsu_pkt_d_bits_fast_int,
|
|
input io_lsu_pkt_d_bits_by,
|
|
input io_lsu_pkt_d_bits_half,
|
|
input io_lsu_pkt_d_bits_word,
|
|
input io_lsu_pkt_d_bits_load,
|
|
input io_lsu_pkt_d_bits_store,
|
|
input io_lsu_pkt_d_bits_dma,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
input [3:0] io_rs1_region_d,
|
|
output io_is_sideeffects_m,
|
|
output io_addr_in_dccm_d,
|
|
output io_addr_in_pic_d,
|
|
output io_addr_external_d,
|
|
output io_access_fault_d,
|
|
output io_misaligned_fault_d,
|
|
output [3:0] io_exc_mscause_d,
|
|
output io_fir_dccm_access_error_d,
|
|
output io_fir_nondccm_access_error_d
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 376:49]
|
|
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 381:39]
|
|
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 376:49]
|
|
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 381:39]
|
|
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45]
|
|
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 381:39]
|
|
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 381:39]
|
|
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60]
|
|
wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55]
|
|
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91]
|
|
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50]
|
|
wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121]
|
|
wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62]
|
|
wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60]
|
|
wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137]
|
|
wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185]
|
|
wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158]
|
|
wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80]
|
|
wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56]
|
|
wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138]
|
|
wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116]
|
|
wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90]
|
|
wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148]
|
|
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57]
|
|
wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76]
|
|
wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92]
|
|
wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90]
|
|
wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51]
|
|
wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87]
|
|
wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64]
|
|
wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62]
|
|
wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57]
|
|
wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36]
|
|
wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34]
|
|
wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112]
|
|
wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29]
|
|
wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85]
|
|
wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29]
|
|
wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85]
|
|
wire _T_164 = unmapped_access_fault_d | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70]
|
|
wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92]
|
|
wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118]
|
|
wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141]
|
|
wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164]
|
|
wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120]
|
|
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[lsu_addrcheck.scala 112:35]
|
|
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61]
|
|
wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59]
|
|
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57]
|
|
wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90]
|
|
wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57]
|
|
wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113]
|
|
wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80]
|
|
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39]
|
|
wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66]
|
|
wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64]
|
|
wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120]
|
|
wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118]
|
|
wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88]
|
|
wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142]
|
|
wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66]
|
|
wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36]
|
|
wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95]
|
|
reg _T_201; // @[lsu_addrcheck.scala 121:60]
|
|
assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50]
|
|
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32]
|
|
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32]
|
|
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30]
|
|
assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21]
|
|
assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25]
|
|
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21]
|
|
assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31]
|
|
assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_201 = _RAND_0[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_201 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_201 <= 1'h0;
|
|
end else begin
|
|
_T_201 <= _T_32 & _T_33;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_lsc_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_clk_override,
|
|
input io_lsu_c1_m_clk,
|
|
input io_lsu_c1_r_clk,
|
|
input io_lsu_c2_m_clk,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_store_c1_m_clk,
|
|
input [31:0] io_lsu_ld_data_corr_r,
|
|
input io_lsu_single_ecc_error_r,
|
|
input io_lsu_double_ecc_error_r,
|
|
input [31:0] io_lsu_ld_data_m,
|
|
input io_lsu_single_ecc_error_m,
|
|
input io_lsu_double_ecc_error_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
input io_ldst_dual_d,
|
|
input io_ldst_dual_m,
|
|
input io_ldst_dual_r,
|
|
input [31:0] io_lsu_exu_exu_lsu_rs1_d,
|
|
input [31:0] io_lsu_exu_exu_lsu_rs2_d,
|
|
output [31:0] io_lsu_exu_lsu_result_m,
|
|
input io_lsu_p_valid,
|
|
input io_lsu_p_bits_fast_int,
|
|
input io_lsu_p_bits_by,
|
|
input io_lsu_p_bits_half,
|
|
input io_lsu_p_bits_word,
|
|
input io_lsu_p_bits_load,
|
|
input io_lsu_p_bits_store,
|
|
input io_lsu_p_bits_unsign,
|
|
input io_lsu_p_bits_store_data_bypass_d,
|
|
input io_lsu_p_bits_load_ldst_bypass_d,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [11:0] io_dec_lsu_offset_d,
|
|
input [31:0] io_picm_mask_data_m,
|
|
input [31:0] io_bus_read_data_m,
|
|
output [31:0] io_lsu_result_corr_r,
|
|
output [31:0] io_lsu_addr_d,
|
|
output [31:0] io_lsu_addr_m,
|
|
output [31:0] io_lsu_addr_r,
|
|
output [31:0] io_end_addr_d,
|
|
output [31:0] io_end_addr_m,
|
|
output [31:0] io_end_addr_r,
|
|
output [31:0] io_store_data_m,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
output io_lsu_exc_m,
|
|
output io_is_sideeffects_m,
|
|
output io_lsu_commit_r,
|
|
output io_lsu_single_ecc_error_incr,
|
|
output io_lsu_error_pkt_r_valid,
|
|
output io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
output io_lsu_error_pkt_r_bits_inst_type,
|
|
output io_lsu_error_pkt_r_bits_exc_type,
|
|
output [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
output [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
output [30:0] io_lsu_fir_addr,
|
|
output [1:0] io_lsu_fir_error,
|
|
output io_addr_in_dccm_d,
|
|
output io_addr_in_dccm_m,
|
|
output io_addr_in_dccm_r,
|
|
output io_addr_in_pic_d,
|
|
output io_addr_in_pic_m,
|
|
output io_addr_in_pic_r,
|
|
output io_addr_external_m,
|
|
input io_dma_lsc_ctl_dma_dccm_req,
|
|
input [31:0] io_dma_lsc_ctl_dma_mem_addr,
|
|
input [2:0] io_dma_lsc_ctl_dma_mem_sz,
|
|
input io_dma_lsc_ctl_dma_mem_write,
|
|
input [63:0] io_dma_lsc_ctl_dma_mem_wdata,
|
|
output io_lsu_pkt_d_valid,
|
|
output io_lsu_pkt_d_bits_fast_int,
|
|
output io_lsu_pkt_d_bits_by,
|
|
output io_lsu_pkt_d_bits_half,
|
|
output io_lsu_pkt_d_bits_word,
|
|
output io_lsu_pkt_d_bits_dword,
|
|
output io_lsu_pkt_d_bits_load,
|
|
output io_lsu_pkt_d_bits_store,
|
|
output io_lsu_pkt_d_bits_unsign,
|
|
output io_lsu_pkt_d_bits_dma,
|
|
output io_lsu_pkt_d_bits_store_data_bypass_d,
|
|
output io_lsu_pkt_d_bits_load_ldst_bypass_d,
|
|
output io_lsu_pkt_d_bits_store_data_bypass_m,
|
|
output io_lsu_pkt_m_valid,
|
|
output io_lsu_pkt_m_bits_fast_int,
|
|
output io_lsu_pkt_m_bits_by,
|
|
output io_lsu_pkt_m_bits_half,
|
|
output io_lsu_pkt_m_bits_word,
|
|
output io_lsu_pkt_m_bits_dword,
|
|
output io_lsu_pkt_m_bits_load,
|
|
output io_lsu_pkt_m_bits_store,
|
|
output io_lsu_pkt_m_bits_unsign,
|
|
output io_lsu_pkt_m_bits_dma,
|
|
output io_lsu_pkt_m_bits_store_data_bypass_m,
|
|
output io_lsu_pkt_r_valid,
|
|
output io_lsu_pkt_r_bits_by,
|
|
output io_lsu_pkt_r_bits_half,
|
|
output io_lsu_pkt_r_bits_word,
|
|
output io_lsu_pkt_r_bits_dword,
|
|
output io_lsu_pkt_r_bits_load,
|
|
output io_lsu_pkt_r_bits_store,
|
|
output io_lsu_pkt_r_bits_unsign,
|
|
output io_lsu_pkt_r_bits_dma
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25]
|
|
wire rvclkhdr_io_clk; // @[lib.scala 435:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 435:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28]
|
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wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
|
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wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51]
|
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wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_exu_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28]
|
|
wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
|
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wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
|
|
wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 98:39]
|
|
wire _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 99:46]
|
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wire _T_15 = ~_T_14; // @[lib.scala 99:33]
|
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wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
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wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 99:58]
|
|
wire _T_21 = ~lsu_offset_d[11]; // @[lib.scala 100:18]
|
|
wire _T_23 = _T_21 & _T_11[12]; // @[lib.scala 100:30]
|
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wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
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wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 100:54]
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wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 100:41]
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wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 99:72]
|
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wire _T_33 = ~_T_11[12]; // @[lib.scala 101:31]
|
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wire _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 101:29]
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wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
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wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 101:54]
|
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wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 101:41]
|
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wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 100:61]
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wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
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wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58]
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wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
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wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40]
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wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70]
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wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
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wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52]
|
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wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58]
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wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58]
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wire [12:0] _GEN_9 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60]
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wire [12:0] end_addr_offset_d = _T_55 + _GEN_9; // @[lsu_lsc_ctl.scala 112:60]
|
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wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58]
|
|
reg access_fault_m; // @[lsu_lsc_ctl.scala 148:75]
|
|
reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75]
|
|
reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75]
|
|
reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75]
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reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75]
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wire _T_70 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:34]
|
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wire _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64]
|
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wire _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62]
|
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wire _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111]
|
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wire _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92]
|
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wire _T_77 = _T_70 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 177:67]
|
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wire _T_78 = _T_77 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 177:96]
|
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wire _T_79 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 177:119]
|
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wire _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 177:117]
|
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wire _T_81 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 177:144]
|
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wire _T_82 = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 177:142]
|
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wire _T_83 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 177:174]
|
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wire lsu_error_pkt_m_valid = _T_82 & _T_83; // @[lsu_lsc_ctl.scala 177:172]
|
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wire _T_85 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:75]
|
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wire _T_86 = io_lsu_single_ecc_error_m & _T_85; // @[lsu_lsc_ctl.scala 178:73]
|
|
wire lsu_error_pkt_m_bits_single_ecc_error = _T_86 & _T_79; // @[lsu_lsc_ctl.scala 178:99]
|
|
wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 180:46]
|
|
wire _T_91 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 181:78]
|
|
wire _T_92 = ~access_fault_m; // @[lsu_lsc_ctl.scala 181:102]
|
|
wire _T_93 = _T_91 & _T_92; // @[lsu_lsc_ctl.scala 181:100]
|
|
wire _T_100 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 183:166]
|
|
wire _T_105 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 184:73]
|
|
wire _T_106 = _T_105 | io_clk_override; // @[lsu_lsc_ctl.scala 184:113]
|
|
reg _T_110_bits_inst_type; // @[Reg.scala 27:20]
|
|
reg _T_110_bits_exc_type; // @[Reg.scala 27:20]
|
|
reg [3:0] _T_110_bits_mscause; // @[Reg.scala 27:20]
|
|
reg [31:0] _T_110_bits_addr; // @[Reg.scala 27:20]
|
|
reg _T_111; // @[lsu_lsc_ctl.scala 185:83]
|
|
reg _T_112; // @[lsu_lsc_ctl.scala 186:67]
|
|
reg [1:0] _T_113; // @[lsu_lsc_ctl.scala 187:75]
|
|
wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30]
|
|
wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62]
|
|
wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62]
|
|
wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62]
|
|
wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62]
|
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wire _T_125 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64]
|
|
wire _T_126 = io_flush_m_up & _T_125; // @[lsu_lsc_ctl.scala 212:61]
|
|
wire _T_127 = ~_T_126; // @[lsu_lsc_ctl.scala 212:45]
|
|
wire _T_128 = io_lsu_p_valid & _T_127; // @[lsu_lsc_ctl.scala 212:43]
|
|
wire _T_130 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68]
|
|
wire _T_131 = io_flush_m_up & _T_130; // @[lsu_lsc_ctl.scala 213:65]
|
|
wire _T_132 = ~_T_131; // @[lsu_lsc_ctl.scala 213:49]
|
|
wire _T_135 = io_flush_m_up & _T_79; // @[lsu_lsc_ctl.scala 214:65]
|
|
wire _T_136 = ~_T_135; // @[lsu_lsc_ctl.scala 214:49]
|
|
reg _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65]
|
|
reg _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:65]
|
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reg _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:65]
|
|
reg _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:65]
|
|
reg _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:65]
|
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reg _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:65]
|
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reg _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:65]
|
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reg _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:65]
|
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reg _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:65]
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reg _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65]
|
|
reg _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
|
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reg _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
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reg _T_142; // @[lsu_lsc_ctl.scala 218:65]
|
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reg _T_143; // @[lsu_lsc_ctl.scala 219:65]
|
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wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66]
|
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reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
|
|
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 226:62]
|
|
reg [31:0] _T_154; // @[lsu_lsc_ctl.scala 227:62]
|
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reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20]
|
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wire [28:0] _T_157 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27]
|
|
reg [2:0] _T_159; // @[lsu_lsc_ctl.scala 228:114]
|
|
reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20]
|
|
wire [28:0] _T_163 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
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reg [2:0] _T_165; // @[lsu_lsc_ctl.scala 229:114]
|
|
wire _T_168 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69]
|
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wire _T_169 = _T_168 | io_clk_override; // @[lsu_lsc_ctl.scala 230:87]
|
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wire _T_174 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69]
|
|
wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87]
|
|
reg _T_179; // @[lsu_lsc_ctl.scala 232:62]
|
|
reg _T_180; // @[lsu_lsc_ctl.scala 233:62]
|
|
reg _T_181; // @[lsu_lsc_ctl.scala 234:62]
|
|
reg _T_182; // @[lsu_lsc_ctl.scala 235:62]
|
|
reg _T_183; // @[lsu_lsc_ctl.scala 236:62]
|
|
reg addr_external_r; // @[lsu_lsc_ctl.scala 237:66]
|
|
wire _T_184 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 238:77]
|
|
reg [31:0] bus_read_data_r; // @[Reg.scala 27:20]
|
|
wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68]
|
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wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 245:41]
|
|
wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96]
|
|
wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 245:94]
|
|
wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 245:110]
|
|
wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69]
|
|
wire [31:0] _T_196 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
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wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 246:59]
|
|
wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94]
|
|
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 267:33]
|
|
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 268:33]
|
|
wire _T_204 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 269:74]
|
|
wire [31:0] _T_206 = _T_204 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_208 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_209 = _T_206 & _T_208; // @[lsu_lsc_ctl.scala 269:102]
|
|
wire _T_210 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 270:43]
|
|
wire [31:0] _T_212 = _T_210 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_214 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_215 = _T_212 & _T_214; // @[lsu_lsc_ctl.scala 270:71]
|
|
wire [31:0] _T_216 = _T_209 | _T_215; // @[lsu_lsc_ctl.scala 269:141]
|
|
wire _T_217 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 271:17]
|
|
wire _T_218 = _T_217 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 271:43]
|
|
wire [31:0] _T_220 = _T_218 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [23:0] _T_223 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_225 = {_T_223,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_226 = _T_220 & _T_225; // @[lsu_lsc_ctl.scala 271:71]
|
|
wire [31:0] _T_227 = _T_216 | _T_226; // @[lsu_lsc_ctl.scala 270:114]
|
|
wire _T_229 = _T_217 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 272:43]
|
|
wire [31:0] _T_231 = _T_229 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_234 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_236 = {_T_234,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_237 = _T_231 & _T_236; // @[lsu_lsc_ctl.scala 272:71]
|
|
wire [31:0] _T_238 = _T_227 | _T_237; // @[lsu_lsc_ctl.scala 271:134]
|
|
wire [31:0] _T_240 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_242 = _T_240 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 273:43]
|
|
wire _T_244 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 274:66]
|
|
wire [31:0] _T_246 = _T_244 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_248 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_249 = _T_246 & _T_248; // @[lsu_lsc_ctl.scala 274:94]
|
|
wire _T_250 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 275:43]
|
|
wire [31:0] _T_252 = _T_250 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_254 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_255 = _T_252 & _T_254; // @[lsu_lsc_ctl.scala 275:71]
|
|
wire [31:0] _T_256 = _T_249 | _T_255; // @[lsu_lsc_ctl.scala 274:138]
|
|
wire _T_257 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 276:17]
|
|
wire _T_258 = _T_257 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 276:43]
|
|
wire [31:0] _T_260 = _T_258 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [23:0] _T_263 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_265 = {_T_263,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_266 = _T_260 & _T_265; // @[lsu_lsc_ctl.scala 276:71]
|
|
wire [31:0] _T_267 = _T_256 | _T_266; // @[lsu_lsc_ctl.scala 275:119]
|
|
wire _T_269 = _T_257 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 277:43]
|
|
wire [31:0] _T_271 = _T_269 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_274 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_276 = {_T_274,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_277 = _T_271 & _T_276; // @[lsu_lsc_ctl.scala 277:71]
|
|
wire [31:0] _T_278 = _T_267 | _T_277; // @[lsu_lsc_ctl.scala 276:144]
|
|
wire [31:0] _T_280 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_282 = _T_280 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 278:43]
|
|
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25]
|
|
.reset(addrcheck_reset),
|
|
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
|
.io_start_addr_d(addrcheck_io_start_addr_d),
|
|
.io_end_addr_d(addrcheck_io_end_addr_d),
|
|
.io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int),
|
|
.io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by),
|
|
.io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half),
|
|
.io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma),
|
|
.io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff),
|
|
.io_rs1_region_d(addrcheck_io_rs1_region_d),
|
|
.io_is_sideeffects_m(addrcheck_io_is_sideeffects_m),
|
|
.io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d),
|
|
.io_addr_in_pic_d(addrcheck_io_addr_in_pic_d),
|
|
.io_addr_external_d(addrcheck_io_addr_external_d),
|
|
.io_access_fault_d(addrcheck_io_access_fault_d),
|
|
.io_misaligned_fault_d(addrcheck_io_misaligned_fault_d),
|
|
.io_exc_mscause_d(addrcheck_io_exc_mscause_d),
|
|
.io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d),
|
|
.io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d)
|
|
);
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 435:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
assign io_lsu_exu_lsu_result_m = _T_238 | _T_242; // @[lsu_lsc_ctl.scala 269:35]
|
|
assign io_lsu_result_corr_r = _T_278 | _T_282; // @[lsu_lsc_ctl.scala 274:27]
|
|
assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 243:28]
|
|
assign io_lsu_addr_m = _T_153; // @[lsu_lsc_ctl.scala 226:24]
|
|
assign io_lsu_addr_r = _T_154; // @[lsu_lsc_ctl.scala 227:24]
|
|
assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24]
|
|
assign io_end_addr_m = {_T_157,_T_159}; // @[lsu_lsc_ctl.scala 228:17]
|
|
assign io_end_addr_r = {_T_163,_T_165}; // @[lsu_lsc_ctl.scala 229:17]
|
|
assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 246:29]
|
|
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16]
|
|
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42]
|
|
assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 245:19]
|
|
assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32]
|
|
assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30]
|
|
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46]
|
|
assign io_lsu_error_pkt_r_bits_inst_type = _T_110_bits_inst_type; // @[lsu_lsc_ctl.scala 184:24]
|
|
assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24]
|
|
assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24]
|
|
assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24]
|
|
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28]
|
|
assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38]
|
|
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42]
|
|
assign io_addr_in_dccm_m = _T_179; // @[lsu_lsc_ctl.scala 232:24]
|
|
assign io_addr_in_dccm_r = _T_180; // @[lsu_lsc_ctl.scala 233:24]
|
|
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42]
|
|
assign io_addr_in_pic_m = _T_181; // @[lsu_lsc_ctl.scala 234:24]
|
|
assign io_addr_in_pic_r = _T_182; // @[lsu_lsc_ctl.scala 235:24]
|
|
assign io_addr_external_m = _T_183; // @[lsu_lsc_ctl.scala 236:24]
|
|
assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
|
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? 1'h0 : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? 1'h0 : 1'h1; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_d_bits_store_data_bypass_m = 1'h0; // @[lsu_lsc_ctl.scala 208:20]
|
|
assign io_lsu_pkt_m_valid = _T_142; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28]
|
|
assign io_lsu_pkt_m_bits_fast_int = _T_139_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_by = _T_139_bits_by; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_half = _T_139_bits_half; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_word = _T_139_bits_word; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_dword = _T_139_bits_dword; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_load = _T_139_bits_load; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_store = _T_139_bits_store; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_unsign = _T_139_bits_unsign; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_dma = _T_139_bits_dma; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_139_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28]
|
|
assign io_lsu_pkt_r_valid = _T_143; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
|
|
assign io_lsu_pkt_r_bits_by = _T_141_bits_by; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_half = _T_141_bits_half; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_word = _T_141_bits_word; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_dword = _T_141_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_load = _T_141_bits_load; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_store = _T_141_bits_store; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_unsign = _T_141_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign io_lsu_pkt_r_bits_dma = _T_141_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
|
|
assign addrcheck_reset = reset;
|
|
assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42]
|
|
assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42]
|
|
assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42]
|
|
assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42]
|
|
assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42]
|
|
assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 437:18]
|
|
assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 438:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = _T_168 | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = _T_174 | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
access_fault_m = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
misaligned_fault_m = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
exc_mscause_m = _RAND_2[3:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
fir_dccm_access_error_m = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
fir_nondccm_access_error_m = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_110_bits_inst_type = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_110_bits_exc_type = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_110_bits_mscause = _RAND_7[3:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_110_bits_addr = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_111 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_112 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_113 = _RAND_11[1:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_139_bits_fast_int = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
_T_139_bits_by = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
_T_139_bits_half = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
_T_139_bits_word = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
_T_139_bits_dword = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_139_bits_load = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_139_bits_store = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
_T_139_bits_unsign = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_139_bits_dma = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
_T_139_bits_store_data_bypass_m = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
_T_141_bits_by = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
_T_141_bits_half = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
_T_141_bits_word = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
_T_141_bits_dword = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
_T_141_bits_load = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
_T_141_bits_store = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
_T_141_bits_unsign = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
_T_141_bits_dma = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
_T_142 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
_T_143 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
store_data_pre_m = _RAND_32[31:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
_T_153 = _RAND_33[31:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
_T_154 = _RAND_34[31:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
end_addr_pre_m = _RAND_35[28:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
_T_159 = _RAND_36[2:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
end_addr_pre_r = _RAND_37[28:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
_T_165 = _RAND_38[2:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
_T_179 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
_T_180 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
_T_181 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
_T_182 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
_T_183 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
addr_external_r = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
bus_read_data_r = _RAND_45[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
access_fault_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
misaligned_fault_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
exc_mscause_m = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
fir_dccm_access_error_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fir_nondccm_access_error_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110_bits_inst_type = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110_bits_exc_type = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110_bits_mscause = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110_bits_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_112 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_113 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_fast_int = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_by = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_half = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_word = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_dword = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_dma = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_139_bits_store_data_bypass_m = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_by = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_half = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_word = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_dword = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_load = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_store = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_141_bits_dma = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_142 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_143 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
store_data_pre_m = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_153 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_154 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
end_addr_pre_m = 29'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_159 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
end_addr_pre_r = 29'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_165 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_179 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_180 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_181 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_182 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_183 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
addr_external_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
bus_read_data_r = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
access_fault_m <= 1'h0;
|
|
end else begin
|
|
access_fault_m <= addrcheck_io_access_fault_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
misaligned_fault_m <= 1'h0;
|
|
end else begin
|
|
misaligned_fault_m <= addrcheck_io_misaligned_fault_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
exc_mscause_m <= 4'h0;
|
|
end else begin
|
|
exc_mscause_m <= addrcheck_io_exc_mscause_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fir_dccm_access_error_m <= 1'h0;
|
|
end else begin
|
|
fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
fir_nondccm_access_error_m <= 1'h0;
|
|
end else begin
|
|
fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110_bits_inst_type <= 1'h0;
|
|
end else if (_T_106) begin
|
|
_T_110_bits_inst_type <= io_lsu_pkt_m_bits_store;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110_bits_exc_type <= 1'h0;
|
|
end else if (_T_106) begin
|
|
_T_110_bits_exc_type <= lsu_error_pkt_m_bits_exc_type;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110_bits_mscause <= 4'h0;
|
|
end else if (_T_106) begin
|
|
if (_T_93) begin
|
|
_T_110_bits_mscause <= 4'h1;
|
|
end else begin
|
|
_T_110_bits_mscause <= exc_mscause_m;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110_bits_addr <= 32'h0;
|
|
end else if (_T_106) begin
|
|
_T_110_bits_addr <= io_lsu_addr_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_111 <= 1'h0;
|
|
end else begin
|
|
_T_111 <= _T_86 & _T_79;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_112 <= 1'h0;
|
|
end else begin
|
|
_T_112 <= _T_82 & _T_83;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_113 <= 2'h0;
|
|
end else if (fir_nondccm_access_error_m) begin
|
|
_T_113 <= 2'h3;
|
|
end else if (fir_dccm_access_error_m) begin
|
|
_T_113 <= 2'h2;
|
|
end else if (_T_100) begin
|
|
_T_113 <= 2'h1;
|
|
end else begin
|
|
_T_113 <= 2'h0;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_fast_int <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_by <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_by <= io_lsu_pkt_d_bits_by;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_half <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_half <= io_lsu_pkt_d_bits_half;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_word <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_word <= io_lsu_pkt_d_bits_word;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_dword <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_dword <= io_lsu_pkt_d_bits_dword;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_load <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_load <= io_lsu_pkt_d_bits_load;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_store <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_store <= io_lsu_pkt_d_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_unsign <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_unsign <= io_lsu_pkt_d_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_dma <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_dma <= io_lsu_pkt_d_bits_dma;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_139_bits_store_data_bypass_m <= 1'h0;
|
|
end else begin
|
|
_T_139_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_by <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_by <= io_lsu_pkt_m_bits_by;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_half <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_half <= io_lsu_pkt_m_bits_half;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_word <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_word <= io_lsu_pkt_m_bits_word;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_dword <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_dword <= io_lsu_pkt_m_bits_dword;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_load <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_load <= io_lsu_pkt_m_bits_load;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_store <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_store <= io_lsu_pkt_m_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_unsign <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_unsign <= io_lsu_pkt_m_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_141_bits_dma <= 1'h0;
|
|
end else begin
|
|
_T_141_bits_dma <= io_lsu_pkt_m_bits_dma;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_142 <= 1'h0;
|
|
end else begin
|
|
_T_142 <= io_lsu_pkt_d_valid & _T_132;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_143 <= 1'h0;
|
|
end else begin
|
|
_T_143 <= io_lsu_pkt_m_valid & _T_136;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
store_data_pre_m <= 32'h0;
|
|
end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin
|
|
store_data_pre_m <= io_lsu_exu_lsu_result_m;
|
|
end else if (io_dma_lsc_ctl_dma_dccm_req) begin
|
|
store_data_pre_m <= dma_mem_wdata_shifted[31:0];
|
|
end else begin
|
|
store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_153 <= 32'h0;
|
|
end else begin
|
|
_T_153 <= io_lsu_addr_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_154 <= 32'h0;
|
|
end else begin
|
|
_T_154 <= io_lsu_addr_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
end_addr_pre_m <= 29'h0;
|
|
end else if (_T_169) begin
|
|
end_addr_pre_m <= io_end_addr_d[31:3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_159 <= 3'h0;
|
|
end else begin
|
|
_T_159 <= io_end_addr_d[2:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
end_addr_pre_r <= 29'h0;
|
|
end else if (_T_175) begin
|
|
end_addr_pre_r <= io_end_addr_m[31:3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_165 <= 3'h0;
|
|
end else begin
|
|
_T_165 <= io_end_addr_m[2:0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_179 <= 1'h0;
|
|
end else begin
|
|
_T_179 <= io_addr_in_dccm_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_180 <= 1'h0;
|
|
end else begin
|
|
_T_180 <= io_addr_in_dccm_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_181 <= 1'h0;
|
|
end else begin
|
|
_T_181 <= io_addr_in_pic_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_182 <= 1'h0;
|
|
end else begin
|
|
_T_182 <= io_addr_in_pic_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_183 <= 1'h0;
|
|
end else begin
|
|
_T_183 <= addrcheck_io_addr_external_d;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
addr_external_r <= 1'h0;
|
|
end else begin
|
|
addr_external_r <= io_addr_external_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
bus_read_data_r <= 32'h0;
|
|
end else if (_T_184) begin
|
|
bus_read_data_r <= io_bus_read_data_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_dccm_ctl(
|
|
input clock,
|
|
input reset,
|
|
input io_clk_override,
|
|
input io_lsu_c2_m_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_lsu_store_c1_r_clk,
|
|
input io_lsu_pkt_d_valid,
|
|
input io_lsu_pkt_d_bits_word,
|
|
input io_lsu_pkt_d_bits_dword,
|
|
input io_lsu_pkt_d_bits_load,
|
|
input io_lsu_pkt_d_bits_store,
|
|
input io_lsu_pkt_d_bits_dma,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_by,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_dma,
|
|
input io_addr_in_dccm_d,
|
|
input io_addr_in_dccm_m,
|
|
input io_addr_in_dccm_r,
|
|
input io_addr_in_pic_d,
|
|
input io_addr_in_pic_m,
|
|
input io_addr_in_pic_r,
|
|
input io_lsu_raw_fwd_lo_r,
|
|
input io_lsu_raw_fwd_hi_r,
|
|
input io_lsu_commit_r,
|
|
input io_ldst_dual_m,
|
|
input [31:0] io_lsu_addr_d,
|
|
input [15:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [15:0] io_end_addr_d,
|
|
input [15:0] io_end_addr_m,
|
|
input [15:0] io_end_addr_r,
|
|
input io_stbuf_reqvld_any,
|
|
input [15:0] io_stbuf_addr_any,
|
|
input [31:0] io_stbuf_data_any,
|
|
input [6:0] io_stbuf_ecc_any,
|
|
input [31:0] io_stbuf_fwddata_hi_m,
|
|
input [31:0] io_stbuf_fwddata_lo_m,
|
|
input [3:0] io_stbuf_fwdbyteen_lo_m,
|
|
input [3:0] io_stbuf_fwdbyteen_hi_m,
|
|
output [31:0] io_lsu_ld_data_corr_r,
|
|
input io_lsu_double_ecc_error_r,
|
|
input io_single_ecc_error_hi_r,
|
|
input io_single_ecc_error_lo_r,
|
|
input [31:0] io_sec_data_hi_r_ff,
|
|
input [31:0] io_sec_data_lo_r_ff,
|
|
input [6:0] io_sec_data_ecc_hi_r_ff,
|
|
input [6:0] io_sec_data_ecc_lo_r_ff,
|
|
output [31:0] io_dccm_rdata_hi_m,
|
|
output [31:0] io_dccm_rdata_lo_m,
|
|
output [6:0] io_dccm_data_ecc_hi_m,
|
|
output [6:0] io_dccm_data_ecc_lo_m,
|
|
output [31:0] io_lsu_ld_data_m,
|
|
input io_lsu_double_ecc_error_m,
|
|
input [31:0] io_sec_data_hi_m,
|
|
input [31:0] io_sec_data_lo_m,
|
|
input [31:0] io_store_data_m,
|
|
input io_dma_dccm_wen,
|
|
input io_dma_pic_wen,
|
|
input [2:0] io_dma_mem_tag_m,
|
|
input [31:0] io_dma_dccm_wdata_lo,
|
|
input [31:0] io_dma_dccm_wdata_hi,
|
|
input [6:0] io_dma_dccm_wdata_ecc_hi,
|
|
input [6:0] io_dma_dccm_wdata_ecc_lo,
|
|
output [31:0] io_store_data_hi_r,
|
|
output [31:0] io_store_data_lo_r,
|
|
output [31:0] io_store_datafn_hi_r,
|
|
output [31:0] io_store_datafn_lo_r,
|
|
output [31:0] io_store_data_r,
|
|
output io_ld_single_ecc_error_r,
|
|
output io_ld_single_ecc_error_r_ff,
|
|
output [31:0] io_picm_mask_data_m,
|
|
output io_lsu_stbuf_commit_any,
|
|
output io_lsu_dccm_rden_m,
|
|
input [31:0] io_dma_dccm_ctl_dma_mem_addr,
|
|
input [63:0] io_dma_dccm_ctl_dma_mem_wdata,
|
|
output io_dma_dccm_ctl_dccm_dma_rvalid,
|
|
output io_dma_dccm_ctl_dccm_dma_ecc_error,
|
|
output [2:0] io_dma_dccm_ctl_dccm_dma_rtag,
|
|
output [63:0] io_dma_dccm_ctl_dccm_dma_rdata,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output io_lsu_pic_picm_wren,
|
|
output io_lsu_pic_picm_rden,
|
|
output io_lsu_pic_picm_mken,
|
|
output [31:0] io_lsu_pic_picm_rdaddr,
|
|
output [31:0] io_lsu_pic_picm_wraddr,
|
|
output [31:0] io_lsu_pic_picm_wr_data,
|
|
input [31:0] io_lsu_pic_picm_rd_data
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [63:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58]
|
|
wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
|
|
wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
|
|
wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[lsu_dccm_ctl.scala 145:63]
|
|
wire [7:0] _T_6 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_9 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_14 = io_addr_in_dccm_m ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_16 = _T_14 & dccm_rdata_corr_m[7:0]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_17 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_16; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_18 = _T_6[0] ? _T_9[7:0] : _T_17; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_22 = {{4'd0}, _T_18[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_24 = {_T_18[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_26 = _T_24 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_27 = _T_22 | _T_26; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_4 = {{2'd0}, _T_27[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_32 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_34 = {_T_27[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_36 = _T_34 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_37 = _T_32 | _T_36; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_5 = {{1'd0}, _T_37[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_42 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_44 = {_T_37[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_46 = _T_44 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_47 = _T_42 | _T_46; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_58 = _T_14 & dccm_rdata_corr_m[15:8]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_59 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_58; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_60 = _T_6[1] ? _T_9[15:8] : _T_59; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_64 = {{4'd0}, _T_60[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_66 = {_T_60[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_68 = _T_66 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_69 = _T_64 | _T_68; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_6 = {{2'd0}, _T_69[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_74 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_76 = {_T_69[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_78 = _T_76 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_79 = _T_74 | _T_78; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_7 = {{1'd0}, _T_79[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_84 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_86 = {_T_79[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_88 = _T_86 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_89 = _T_84 | _T_88; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_100 = _T_14 & dccm_rdata_corr_m[23:16]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_101 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_100; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_102 = _T_6[2] ? _T_9[23:16] : _T_101; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_106 = {{4'd0}, _T_102[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_108 = {_T_102[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_110 = _T_108 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_111 = _T_106 | _T_110; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_8 = {{2'd0}, _T_111[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_116 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_118 = {_T_111[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_120 = _T_118 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_121 = _T_116 | _T_120; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_9 = {{1'd0}, _T_121[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_126 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_128 = {_T_121[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_130 = _T_128 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_131 = _T_126 | _T_130; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_142 = _T_14 & dccm_rdata_corr_m[31:24]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_143 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_142; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_144 = _T_6[3] ? _T_9[31:24] : _T_143; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_148 = {{4'd0}, _T_144[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_150 = {_T_144[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_152 = _T_150 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_153 = _T_148 | _T_152; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_10 = {{2'd0}, _T_153[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_158 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_160 = {_T_153[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_162 = _T_160 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_163 = _T_158 | _T_162; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_11 = {{1'd0}, _T_163[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_168 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_170 = {_T_163[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_172 = _T_170 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_173 = _T_168 | _T_172; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_184 = _T_14 & dccm_rdata_corr_m[39:32]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_185 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_184; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_186 = _T_6[4] ? _T_9[39:32] : _T_185; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_190 = {{4'd0}, _T_186[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_192 = {_T_186[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_194 = _T_192 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_195 = _T_190 | _T_194; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_12 = {{2'd0}, _T_195[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_200 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_202 = {_T_195[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_204 = _T_202 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_205 = _T_200 | _T_204; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_13 = {{1'd0}, _T_205[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_210 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_212 = {_T_205[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_214 = _T_212 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_215 = _T_210 | _T_214; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_226 = _T_14 & dccm_rdata_corr_m[47:40]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_227 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_226; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_228 = _T_6[5] ? _T_9[47:40] : _T_227; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_232 = {{4'd0}, _T_228[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_234 = {_T_228[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_236 = _T_234 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_237 = _T_232 | _T_236; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_14 = {{2'd0}, _T_237[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_242 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_244 = {_T_237[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_246 = _T_244 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_247 = _T_242 | _T_246; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_15 = {{1'd0}, _T_247[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_252 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_254 = {_T_247[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_256 = _T_254 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_257 = _T_252 | _T_256; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_268 = _T_14 & dccm_rdata_corr_m[55:48]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_269 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_268; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_270 = _T_6[6] ? _T_9[55:48] : _T_269; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_274 = {{4'd0}, _T_270[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_276 = {_T_270[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_278 = _T_276 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_279 = _T_274 | _T_278; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_16 = {{2'd0}, _T_279[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_284 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_286 = {_T_279[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_288 = _T_286 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_289 = _T_284 | _T_288; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_17 = {{1'd0}, _T_289[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_294 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_296 = {_T_289[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_298 = _T_296 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_299 = _T_294 | _T_298; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_310 = _T_14 & dccm_rdata_corr_m[63:56]; // @[lsu_dccm_ctl.scala 155:294]
|
|
wire [7:0] _T_311 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_310; // @[lsu_dccm_ctl.scala 155:214]
|
|
wire [7:0] _T_312 = _T_6[7] ? _T_9[63:56] : _T_311; // @[lsu_dccm_ctl.scala 155:78]
|
|
wire [7:0] _T_316 = {{4'd0}, _T_312[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_318 = {_T_312[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_320 = _T_318 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_321 = _T_316 | _T_320; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_18 = {{2'd0}, _T_321[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_326 = _GEN_18 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_328 = {_T_321[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_330 = _T_328 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_19 = {{1'd0}, _T_331[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_336 = _GEN_19 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_338 = {_T_331[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_340 = _T_338 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _T_349 = {_T_47,_T_89,_T_131,_T_173,_T_215,_T_257,_T_299,_T_341}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_353 = {{32'd0}, _T_349[63:32]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_355 = {_T_349[31:0], 32'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_357 = _T_355 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_358 = _T_353 | _T_357; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_20 = {{16'd0}, _T_358[63:16]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_363 = _GEN_20 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_365 = {_T_358[47:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_367 = _T_365 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_368 = _T_363 | _T_367; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_21 = {{8'd0}, _T_368[63:8]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_373 = _GEN_21 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_375 = {_T_368[55:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_377 = _T_375 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_378 = _T_373 | _T_377; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_22 = {{4'd0}, _T_378[63:4]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_383 = _GEN_22 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_385 = {_T_378[59:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_387 = _T_385 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_388 = _T_383 | _T_387; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_23 = {{2'd0}, _T_388[63:2]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_393 = _GEN_23 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_395 = {_T_388[61:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_397 = _T_395 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_398 = _T_393 | _T_397; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_24 = {{1'd0}, _T_398[63:1]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_403 = _GEN_24 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_405 = {_T_398[62:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_407 = _T_405 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] lsu_rdata_corr_m = _T_403 | _T_407; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _T_4 = {lsu_rdata_corr_m[31:0],lsu_rdata_corr_m[31:0]}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_419 = _T_14 & dccm_rdata_m[7:0]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_420 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_419; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_421 = _T_6[0] ? _T_9[7:0] : _T_420; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_425 = {{4'd0}, _T_421[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_427 = {_T_421[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_429 = _T_427 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_430 = _T_425 | _T_429; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_25 = {{2'd0}, _T_430[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_435 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_437 = {_T_430[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_439 = _T_437 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_440 = _T_435 | _T_439; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_26 = {{1'd0}, _T_440[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_445 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_447 = {_T_440[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_449 = _T_447 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_450 = _T_445 | _T_449; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_461 = _T_14 & dccm_rdata_m[15:8]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_462 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_461; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_463 = _T_6[1] ? _T_9[15:8] : _T_462; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_467 = {{4'd0}, _T_463[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_469 = {_T_463[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_471 = _T_469 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_472 = _T_467 | _T_471; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_27 = {{2'd0}, _T_472[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_477 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_479 = {_T_472[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_481 = _T_479 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_482 = _T_477 | _T_481; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_28 = {{1'd0}, _T_482[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_487 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_489 = {_T_482[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_491 = _T_489 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_492 = _T_487 | _T_491; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_503 = _T_14 & dccm_rdata_m[23:16]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_504 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_503; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_505 = _T_6[2] ? _T_9[23:16] : _T_504; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_509 = {{4'd0}, _T_505[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_511 = {_T_505[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_513 = _T_511 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_514 = _T_509 | _T_513; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_29 = {{2'd0}, _T_514[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_519 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_521 = {_T_514[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_523 = _T_521 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_524 = _T_519 | _T_523; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_30 = {{1'd0}, _T_524[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_529 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_531 = {_T_524[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_533 = _T_531 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_534 = _T_529 | _T_533; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_545 = _T_14 & dccm_rdata_m[31:24]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_545; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_547 = _T_6[3] ? _T_9[31:24] : _T_546; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_31 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_561 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_32 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_571 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_587 = _T_14 & dccm_rdata_m[39:32]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_588 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_587; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_589 = _T_6[4] ? _T_9[39:32] : _T_588; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_593 = {{4'd0}, _T_589[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_595 = {_T_589[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_597 = _T_595 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_598 = _T_593 | _T_597; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_33 = {{2'd0}, _T_598[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_603 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_605 = {_T_598[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_607 = _T_605 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_608 = _T_603 | _T_607; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_34 = {{1'd0}, _T_608[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_613 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_615 = {_T_608[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_617 = _T_615 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_618 = _T_613 | _T_617; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_629 = _T_14 & dccm_rdata_m[47:40]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_630 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_629; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_631 = _T_6[5] ? _T_9[47:40] : _T_630; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_635 = {{4'd0}, _T_631[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_637 = {_T_631[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_639 = _T_637 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_640 = _T_635 | _T_639; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_35 = {{2'd0}, _T_640[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_645 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_647 = {_T_640[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_649 = _T_647 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_650 = _T_645 | _T_649; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_36 = {{1'd0}, _T_650[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_655 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_657 = {_T_650[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_659 = _T_657 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_660 = _T_655 | _T_659; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_671 = _T_14 & dccm_rdata_m[55:48]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_672 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_671; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_673 = _T_6[6] ? _T_9[55:48] : _T_672; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_677 = {{4'd0}, _T_673[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_679 = {_T_673[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_681 = _T_679 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_682 = _T_677 | _T_681; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_37 = {{2'd0}, _T_682[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_687 = _GEN_37 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_689 = {_T_682[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_691 = _T_689 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_692 = _T_687 | _T_691; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_38 = {{1'd0}, _T_692[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_697 = _GEN_38 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_699 = {_T_692[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_701 = _T_699 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_702 = _T_697 | _T_701; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _T_713 = _T_14 & dccm_rdata_m[63:56]; // @[lsu_dccm_ctl.scala 156:294]
|
|
wire [7:0] _T_714 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_713; // @[lsu_dccm_ctl.scala 156:214]
|
|
wire [7:0] _T_715 = _T_6[7] ? _T_9[63:56] : _T_714; // @[lsu_dccm_ctl.scala 156:78]
|
|
wire [7:0] _T_719 = {{4'd0}, _T_715[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_721 = {_T_715[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_723 = _T_721 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_724 = _T_719 | _T_723; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_39 = {{2'd0}, _T_724[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_729 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_731 = {_T_724[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_733 = _T_731 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_734 = _T_729 | _T_733; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_40 = {{1'd0}, _T_734[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_739 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_741 = {_T_734[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_743 = _T_741 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_744 = _T_739 | _T_743; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _T_752 = {_T_450,_T_492,_T_534,_T_576,_T_618,_T_660,_T_702,_T_744}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_756 = {{32'd0}, _T_752[63:32]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_758 = {_T_752[31:0], 32'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_760 = _T_758 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_761 = _T_756 | _T_760; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_41 = {{16'd0}, _T_761[63:16]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_766 = _GEN_41 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_768 = {_T_761[47:0], 16'h0}; // @[Bitwise.scala 103:65]
|
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wire [63:0] _T_770 = _T_768 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_771 = _T_766 | _T_770; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_42 = {{8'd0}, _T_771[63:8]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_776 = _GEN_42 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_778 = {_T_771[55:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_780 = _T_778 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_781 = _T_776 | _T_780; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_43 = {{4'd0}, _T_781[63:4]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_786 = _GEN_43 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_788 = {_T_781[59:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_790 = _T_788 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_791 = _T_786 | _T_790; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_44 = {{2'd0}, _T_791[63:2]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_796 = _GEN_44 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_798 = {_T_791[61:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_800 = _T_798 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_801 = _T_796 | _T_800; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_45 = {{1'd0}, _T_801[63:1]}; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_806 = _GEN_45 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
|
|
wire [63:0] _T_808 = {_T_801[62:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [63:0] _T_810 = _T_808 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] lsu_rdata_m = _T_806 | _T_810; // @[Bitwise.scala 103:39]
|
|
wire _T_813 = io_addr_in_pic_m | io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 157:123]
|
|
wire _T_814 = _T & _T_813; // @[lsu_dccm_ctl.scala 157:103]
|
|
wire _T_815 = _T_814 | io_clk_override; // @[lsu_dccm_ctl.scala 157:145]
|
|
reg [63:0] _T_818; // @[Reg.scala 27:20]
|
|
wire [3:0] _GEN_46 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 159:54]
|
|
wire [5:0] _T_823 = 4'h8 * _GEN_46; // @[lsu_dccm_ctl.scala 159:54]
|
|
wire [63:0] lsu_ld_data_corr_m = lsu_rdata_corr_m >> _T_823; // @[lsu_dccm_ctl.scala 159:48]
|
|
wire [63:0] _T_821 = lsu_rdata_m >> _T_823; // @[lsu_dccm_ctl.scala 158:43]
|
|
wire _T_827 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60]
|
|
wire _T_830 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133]
|
|
wire _T_831 = _T_827 | _T_830; // @[lsu_dccm_ctl.scala 163:101]
|
|
wire _T_832 = _T_831 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175]
|
|
wire _T_833 = _T_832 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196]
|
|
wire _T_834 = _T_833 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222]
|
|
wire _T_835 = _T_834 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246]
|
|
wire _T_838 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37]
|
|
wire _T_841 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110]
|
|
wire _T_842 = _T_838 | _T_841; // @[lsu_dccm_ctl.scala 164:78]
|
|
wire _T_843 = _T_842 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152]
|
|
wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173]
|
|
wire _T_845 = _T_844 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199]
|
|
wire _T_846 = _T_845 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223]
|
|
wire kill_ecc_corr_lo_r = _T_835 | _T_846; // @[lsu_dccm_ctl.scala 163:267]
|
|
wire _T_849 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60]
|
|
wire _T_852 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133]
|
|
wire _T_853 = _T_849 | _T_852; // @[lsu_dccm_ctl.scala 166:101]
|
|
wire _T_854 = _T_853 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175]
|
|
wire _T_855 = _T_854 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196]
|
|
wire _T_856 = _T_855 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222]
|
|
wire _T_857 = _T_856 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246]
|
|
wire _T_860 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37]
|
|
wire _T_863 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110]
|
|
wire _T_864 = _T_860 | _T_863; // @[lsu_dccm_ctl.scala 167:78]
|
|
wire _T_865 = _T_864 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152]
|
|
wire _T_866 = _T_865 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173]
|
|
wire _T_867 = _T_866 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199]
|
|
wire _T_868 = _T_867 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223]
|
|
wire kill_ecc_corr_hi_r = _T_857 | _T_868; // @[lsu_dccm_ctl.scala 166:267]
|
|
wire _T_869 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60]
|
|
wire _T_870 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89]
|
|
wire ld_single_ecc_error_lo_r = _T_869 & _T_870; // @[lsu_dccm_ctl.scala 169:87]
|
|
wire _T_871 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60]
|
|
wire _T_872 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89]
|
|
wire ld_single_ecc_error_hi_r = _T_871 & _T_872; // @[lsu_dccm_ctl.scala 170:87]
|
|
wire _T_873 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63]
|
|
wire _T_874 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93]
|
|
wire _T_876 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81]
|
|
wire _T_877 = ld_single_ecc_error_lo_r & _T_876; // @[lsu_dccm_ctl.scala 172:62]
|
|
wire _T_878 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108]
|
|
wire _T_880 = ld_single_ecc_error_hi_r & _T_876; // @[lsu_dccm_ctl.scala 173:62]
|
|
wire _T_881 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108]
|
|
wire _T_882 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125]
|
|
wire _T_883 = ~_T_882; // @[lsu_dccm_ctl.scala 175:100]
|
|
wire _T_885 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174]
|
|
wire _T_886 = _T_883 | _T_885; // @[lsu_dccm_ctl.scala 175:152]
|
|
wire _T_887 = io_lsu_pkt_d_bits_store & _T_886; // @[lsu_dccm_ctl.scala 175:97]
|
|
wire _T_888 = io_lsu_pkt_d_bits_load | _T_887; // @[lsu_dccm_ctl.scala 175:70]
|
|
wire _T_889 = io_lsu_pkt_d_valid & _T_888; // @[lsu_dccm_ctl.scala 175:44]
|
|
wire lsu_dccm_rden_d = _T_889 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191]
|
|
reg ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 284:73]
|
|
reg ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 283:73]
|
|
wire _T_890 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63]
|
|
reg lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 282:73]
|
|
wire _T_891 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96]
|
|
wire _T_893 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75]
|
|
wire _T_894 = _T_893 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93]
|
|
wire _T_895 = ~_T_894; // @[lsu_dccm_ctl.scala 179:57]
|
|
wire _T_898 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95]
|
|
wire _T_901 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76]
|
|
wire _T_902 = _T_898 | _T_901; // @[lsu_dccm_ctl.scala 180:171]
|
|
wire _T_903 = ~_T_902; // @[lsu_dccm_ctl.scala 180:24]
|
|
wire _T_904 = lsu_dccm_rden_d & _T_903; // @[lsu_dccm_ctl.scala 180:22]
|
|
wire _T_905 = _T_895 | _T_904; // @[lsu_dccm_ctl.scala 179:124]
|
|
wire _T_907 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41]
|
|
reg [15:0] ld_sec_addr_lo_r_ff; // @[Reg.scala 27:20]
|
|
reg [15:0] ld_sec_addr_hi_r_ff; // @[Reg.scala 27:20]
|
|
wire [15:0] _T_914 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8]
|
|
wire [15:0] _T_918 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8]
|
|
wire [15:0] _T_924 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8]
|
|
wire [15:0] _T_928 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8]
|
|
wire [38:0] _T_936 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_939 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_940 = ld_single_ecc_error_lo_r_ff ? _T_936 : _T_939; // @[lsu_dccm_ctl.scala 200:8]
|
|
wire [38:0] _T_944 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_947 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_948 = io_dma_dccm_wen ? _T_944 : _T_947; // @[lsu_dccm_ctl.scala 202:8]
|
|
wire [38:0] _T_958 = ld_single_ecc_error_hi_r_ff ? _T_939 : _T_936; // @[lsu_dccm_ctl.scala 206:8]
|
|
wire [38:0] _T_962 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_966 = io_dma_dccm_wen ? _T_962 : _T_947; // @[lsu_dccm_ctl.scala 208:8]
|
|
wire [3:0] _T_969 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_971 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_972 = _T_971 & 4'h1; // @[lsu_dccm_ctl.scala 212:94]
|
|
wire [3:0] _T_974 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_975 = _T_974 & 4'h3; // @[lsu_dccm_ctl.scala 213:38]
|
|
wire [3:0] _T_976 = _T_972 | _T_975; // @[lsu_dccm_ctl.scala 212:107]
|
|
wire [3:0] _T_978 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_980 = _T_976 | _T_978; // @[lsu_dccm_ctl.scala 213:51]
|
|
wire [3:0] store_byteen_m = _T_969 & _T_980; // @[lsu_dccm_ctl.scala 212:58]
|
|
wire [3:0] _T_982 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_984 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_985 = _T_984 & 4'h1; // @[lsu_dccm_ctl.scala 216:94]
|
|
wire [3:0] _T_987 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_988 = _T_987 & 4'h3; // @[lsu_dccm_ctl.scala 217:38]
|
|
wire [3:0] _T_989 = _T_985 | _T_988; // @[lsu_dccm_ctl.scala 216:107]
|
|
wire [3:0] _T_991 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_993 = _T_989 | _T_991; // @[lsu_dccm_ctl.scala 217:51]
|
|
wire [3:0] store_byteen_r = _T_982 & _T_993; // @[lsu_dccm_ctl.scala 216:58]
|
|
wire [6:0] _GEN_48 = {{3'd0}, store_byteen_m}; // @[lsu_dccm_ctl.scala 220:45]
|
|
wire [6:0] _T_996 = _GEN_48 << io_lsu_addr_m[1:0]; // @[lsu_dccm_ctl.scala 220:45]
|
|
wire [6:0] _GEN_49 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45]
|
|
wire [6:0] _T_999 = _GEN_49 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45]
|
|
wire _T_1002 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67]
|
|
wire dccm_wr_bypass_d_m_lo = _T_1002 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 225:101]
|
|
wire _T_1005 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67]
|
|
wire dccm_wr_bypass_d_m_hi = _T_1005 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 226:101]
|
|
wire _T_1008 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67]
|
|
wire dccm_wr_bypass_d_r_lo = _T_1008 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101]
|
|
wire _T_1011 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 229:67]
|
|
wire dccm_wr_bypass_d_r_hi = _T_1011 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 229:101]
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wire [63:0] _T_1014 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58]
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wire [126:0] _GEN_51 = {{63'd0}, _T_1014}; // @[lsu_dccm_ctl.scala 258:72]
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wire [126:0] _T_1017 = _GEN_51 << _T_823; // @[lsu_dccm_ctl.scala 258:72]
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wire [63:0] store_data_pre_m = _T_1017[63:0]; // @[lsu_dccm_ctl.scala 258:29]
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wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[lsu_dccm_ctl.scala 259:48]
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wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[lsu_dccm_ctl.scala 260:48]
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wire [7:0] store_byteen_ext_m = {{1'd0}, _T_996}; // @[lsu_dccm_ctl.scala 220:22]
|
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wire _T_1023 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[lsu_dccm_ctl.scala 261:211]
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wire [7:0] _T_1027 = _T_1023 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[lsu_dccm_ctl.scala 261:185]
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wire [7:0] _T_1028 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_1027; // @[lsu_dccm_ctl.scala 261:120]
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wire [7:0] _T_1032 = {{4'd0}, _T_1028[7:4]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1034 = {_T_1028[3:0], 4'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1036 = _T_1034 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1037 = _T_1032 | _T_1036; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_52 = {{2'd0}, _T_1037[7:2]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1042 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1044 = {_T_1037[5:0], 2'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1046 = _T_1044 & 8'hcc; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1047 = _T_1042 | _T_1046; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_53 = {{1'd0}, _T_1047[7:1]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1052 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1054 = {_T_1047[6:0], 1'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1056 = _T_1054 & 8'haa; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1057 = _T_1052 | _T_1056; // @[Bitwise.scala 103:39]
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wire [7:0] _T_1065 = _T_1023 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[lsu_dccm_ctl.scala 261:185]
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wire [7:0] _T_1066 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1065; // @[lsu_dccm_ctl.scala 261:120]
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wire [7:0] _T_1070 = {{4'd0}, _T_1066[7:4]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1072 = {_T_1066[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1074 = _T_1072 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1075 = _T_1070 | _T_1074; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_54 = {{2'd0}, _T_1075[7:2]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1080 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1082 = {_T_1075[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1084 = _T_1082 & 8'hcc; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1085 = _T_1080 | _T_1084; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_55 = {{1'd0}, _T_1085[7:1]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1090 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1092 = {_T_1085[6:0], 1'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1094 = _T_1092 & 8'haa; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1095 = _T_1090 | _T_1094; // @[Bitwise.scala 103:39]
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wire [7:0] _T_1103 = _T_1023 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[lsu_dccm_ctl.scala 261:185]
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wire [7:0] _T_1104 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1103; // @[lsu_dccm_ctl.scala 261:120]
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wire [7:0] _T_1108 = {{4'd0}, _T_1104[7:4]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1110 = {_T_1104[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1112 = _T_1110 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1113 = _T_1108 | _T_1112; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_56 = {{2'd0}, _T_1113[7:2]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1118 = _GEN_56 & 8'h33; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1120 = {_T_1113[5:0], 2'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1122 = _T_1120 & 8'hcc; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1123 = _T_1118 | _T_1122; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_57 = {{1'd0}, _T_1123[7:1]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1128 = _GEN_57 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1130 = {_T_1123[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1132 = _T_1130 & 8'haa; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1133 = _T_1128 | _T_1132; // @[Bitwise.scala 103:39]
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wire [7:0] _T_1141 = _T_1023 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[lsu_dccm_ctl.scala 261:185]
|
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wire [7:0] _T_1142 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1141; // @[lsu_dccm_ctl.scala 261:120]
|
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wire [7:0] _T_1146 = {{4'd0}, _T_1142[7:4]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1148 = {_T_1142[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1150 = _T_1148 & 8'hf0; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1151 = _T_1146 | _T_1150; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_58 = {{2'd0}, _T_1151[7:2]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1156 = _GEN_58 & 8'h33; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1158 = {_T_1151[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1160 = _T_1158 & 8'hcc; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1161 = _T_1156 | _T_1160; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_59 = {{1'd0}, _T_1161[7:1]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1166 = _GEN_59 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1168 = {_T_1161[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1170 = _T_1168 & 8'haa; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1171 = _T_1166 | _T_1170; // @[Bitwise.scala 103:39]
|
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wire [31:0] _T_1175 = {_T_1057,_T_1095,_T_1133,_T_1171}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_1179 = {{16'd0}, _T_1175[31:16]}; // @[Bitwise.scala 103:31]
|
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wire [31:0] _T_1181 = {_T_1175[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
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wire [31:0] _T_1183 = _T_1181 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
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wire [31:0] _T_1184 = _T_1179 | _T_1183; // @[Bitwise.scala 103:39]
|
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wire [31:0] _GEN_60 = {{8'd0}, _T_1184[31:8]}; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1189 = _GEN_60 & 32'hff00ff; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1191 = {_T_1184[23:0], 8'h0}; // @[Bitwise.scala 103:65]
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wire [31:0] _T_1193 = _T_1191 & 32'hff00ff00; // @[Bitwise.scala 103:75]
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wire [31:0] _T_1194 = _T_1189 | _T_1193; // @[Bitwise.scala 103:39]
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wire [31:0] _GEN_61 = {{4'd0}, _T_1194[31:4]}; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1199 = _GEN_61 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
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wire [31:0] _T_1201 = {_T_1194[27:0], 4'h0}; // @[Bitwise.scala 103:65]
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wire [31:0] _T_1203 = _T_1201 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
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wire [31:0] _T_1204 = _T_1199 | _T_1203; // @[Bitwise.scala 103:39]
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wire [31:0] _GEN_62 = {{2'd0}, _T_1204[31:2]}; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1209 = _GEN_62 & 32'h33333333; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1211 = {_T_1204[29:0], 2'h0}; // @[Bitwise.scala 103:65]
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wire [31:0] _T_1213 = _T_1211 & 32'hcccccccc; // @[Bitwise.scala 103:75]
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wire [31:0] _T_1214 = _T_1209 | _T_1213; // @[Bitwise.scala 103:39]
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wire [31:0] _GEN_63 = {{1'd0}, _T_1214[31:1]}; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1219 = _GEN_63 & 32'h55555555; // @[Bitwise.scala 103:31]
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wire [31:0] _T_1221 = {_T_1214[30:0], 1'h0}; // @[Bitwise.scala 103:65]
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wire [31:0] _T_1223 = _T_1221 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
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reg [31:0] _T_1225; // @[lsu_dccm_ctl.scala 261:72]
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wire _T_1229 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[lsu_dccm_ctl.scala 262:177]
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wire [7:0] _T_1233 = _T_1229 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[lsu_dccm_ctl.scala 262:151]
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wire [7:0] _T_1234 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1233; // @[lsu_dccm_ctl.scala 262:86]
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wire [7:0] _T_1238 = {{4'd0}, _T_1234[7:4]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1240 = {_T_1234[3:0], 4'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1242 = _T_1240 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1243 = _T_1238 | _T_1242; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_64 = {{2'd0}, _T_1243[7:2]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1248 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1250 = {_T_1243[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1252 = _T_1250 & 8'hcc; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1253 = _T_1248 | _T_1252; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_65 = {{1'd0}, _T_1253[7:1]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1258 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1260 = {_T_1253[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1262 = _T_1260 & 8'haa; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1263 = _T_1258 | _T_1262; // @[Bitwise.scala 103:39]
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wire [7:0] _T_1271 = _T_1229 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[lsu_dccm_ctl.scala 262:151]
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wire [7:0] _T_1272 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1271; // @[lsu_dccm_ctl.scala 262:86]
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wire [7:0] _T_1276 = {{4'd0}, _T_1272[7:4]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1278 = {_T_1272[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1280 = _T_1278 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1281 = _T_1276 | _T_1280; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_66 = {{2'd0}, _T_1281[7:2]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1286 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1288 = {_T_1281[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1290 = _T_1288 & 8'hcc; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1291 = _T_1286 | _T_1290; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_67 = {{1'd0}, _T_1291[7:1]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1296 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1298 = {_T_1291[6:0], 1'h0}; // @[Bitwise.scala 103:65]
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wire [7:0] _T_1300 = _T_1298 & 8'haa; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1301 = _T_1296 | _T_1300; // @[Bitwise.scala 103:39]
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wire [7:0] _T_1309 = _T_1229 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[lsu_dccm_ctl.scala 262:151]
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wire [7:0] _T_1310 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1309; // @[lsu_dccm_ctl.scala 262:86]
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wire [7:0] _T_1314 = {{4'd0}, _T_1310[7:4]}; // @[Bitwise.scala 103:31]
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wire [7:0] _T_1316 = {_T_1310[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1318 = _T_1316 & 8'hf0; // @[Bitwise.scala 103:75]
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wire [7:0] _T_1319 = _T_1314 | _T_1318; // @[Bitwise.scala 103:39]
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wire [7:0] _GEN_68 = {{2'd0}, _T_1319[7:2]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1324 = _GEN_68 & 8'h33; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1326 = {_T_1319[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1328 = _T_1326 & 8'hcc; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1329 = _T_1324 | _T_1328; // @[Bitwise.scala 103:39]
|
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wire [7:0] _GEN_69 = {{1'd0}, _T_1329[7:1]}; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1334 = _GEN_69 & 8'h55; // @[Bitwise.scala 103:31]
|
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wire [7:0] _T_1336 = {_T_1329[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
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wire [7:0] _T_1338 = _T_1336 & 8'haa; // @[Bitwise.scala 103:75]
|
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wire [7:0] _T_1339 = _T_1334 | _T_1338; // @[Bitwise.scala 103:39]
|
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wire [7:0] _T_1347 = _T_1229 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[lsu_dccm_ctl.scala 262:151]
|
|
wire [7:0] _T_1348 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1347; // @[lsu_dccm_ctl.scala 262:86]
|
|
wire [7:0] _T_1352 = {{4'd0}, _T_1348[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1354 = {_T_1348[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1356 = _T_1354 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1357 = _T_1352 | _T_1356; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_70 = {{2'd0}, _T_1357[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1362 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1364 = {_T_1357[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1366 = _T_1364 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1367 = _T_1362 | _T_1366; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_71 = {{1'd0}, _T_1367[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1372 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1374 = {_T_1367[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1376 = _T_1374 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1377 = _T_1372 | _T_1376; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1381 = {_T_1263,_T_1301,_T_1339,_T_1377}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1385 = {{16'd0}, _T_1381[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1387 = {_T_1381[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1389 = _T_1387 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1390 = _T_1385 | _T_1389; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_72 = {{8'd0}, _T_1390[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1395 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1397 = {_T_1390[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1399 = _T_1397 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1400 = _T_1395 | _T_1399; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_73 = {{4'd0}, _T_1400[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1405 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1407 = {_T_1400[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1409 = _T_1407 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1410 = _T_1405 | _T_1409; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_74 = {{2'd0}, _T_1410[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1415 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1417 = {_T_1410[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1419 = _T_1417 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1420 = _T_1415 | _T_1419; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_75 = {{1'd0}, _T_1420[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1425 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1427 = {_T_1420[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1429 = _T_1427 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1430 = _T_1425 | _T_1429; // @[Bitwise.scala 103:39]
|
|
wire _T_1431 = io_ldst_dual_m & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 262:295]
|
|
wire _T_1432 = _T_1431 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 262:316]
|
|
wire _T_1433 = _T_1432 | io_clk_override; // @[lsu_dccm_ctl.scala 262:343]
|
|
reg [31:0] _T_1436; // @[Reg.scala 27:20]
|
|
wire _T_1437 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 263:105]
|
|
wire [7:0] store_byteen_ext_r = {{1'd0}, _T_999}; // @[lsu_dccm_ctl.scala 222:22]
|
|
wire _T_1439 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 263:131]
|
|
wire _T_1440 = _T_1437 & _T_1439; // @[lsu_dccm_ctl.scala 263:129]
|
|
wire [7:0] _T_1444 = _T_1440 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 263:79]
|
|
wire [7:0] _T_1448 = {{4'd0}, _T_1444[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1450 = {_T_1444[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1452 = _T_1450 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_76 = {{2'd0}, _T_1453[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1458 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1460 = {_T_1453[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1462 = _T_1460 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1463 = _T_1458 | _T_1462; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_77 = {{1'd0}, _T_1463[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1468 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1470 = {_T_1463[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1472 = _T_1470 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1473 = _T_1468 | _T_1472; // @[Bitwise.scala 103:39]
|
|
wire _T_1476 = ~store_byteen_ext_r[1]; // @[lsu_dccm_ctl.scala 263:131]
|
|
wire _T_1477 = _T_1437 & _T_1476; // @[lsu_dccm_ctl.scala 263:129]
|
|
wire [7:0] _T_1481 = _T_1477 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 263:79]
|
|
wire [7:0] _T_1485 = {{4'd0}, _T_1481[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1487 = {_T_1481[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1489 = _T_1487 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_78 = {{2'd0}, _T_1490[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1495 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1497 = {_T_1490[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1499 = _T_1497 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1500 = _T_1495 | _T_1499; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_79 = {{1'd0}, _T_1500[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1505 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1507 = {_T_1500[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1509 = _T_1507 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1510 = _T_1505 | _T_1509; // @[Bitwise.scala 103:39]
|
|
wire _T_1513 = ~store_byteen_ext_r[2]; // @[lsu_dccm_ctl.scala 263:131]
|
|
wire _T_1514 = _T_1437 & _T_1513; // @[lsu_dccm_ctl.scala 263:129]
|
|
wire [7:0] _T_1518 = _T_1514 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 263:79]
|
|
wire [7:0] _T_1522 = {{4'd0}, _T_1518[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1524 = {_T_1518[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1526 = _T_1524 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_80 = {{2'd0}, _T_1527[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1532 = _GEN_80 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1534 = {_T_1527[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1536 = _T_1534 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1537 = _T_1532 | _T_1536; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_81 = {{1'd0}, _T_1537[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1542 = _GEN_81 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1544 = {_T_1537[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1546 = _T_1544 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1547 = _T_1542 | _T_1546; // @[Bitwise.scala 103:39]
|
|
wire _T_1550 = ~store_byteen_ext_r[3]; // @[lsu_dccm_ctl.scala 263:131]
|
|
wire _T_1551 = _T_1437 & _T_1550; // @[lsu_dccm_ctl.scala 263:129]
|
|
wire [7:0] _T_1555 = _T_1551 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 263:79]
|
|
wire [7:0] _T_1559 = {{4'd0}, _T_1555[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1561 = {_T_1555[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1563 = _T_1561 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1564 = _T_1559 | _T_1563; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_82 = {{2'd0}, _T_1564[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1569 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1571 = {_T_1564[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1573 = _T_1571 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1574 = _T_1569 | _T_1573; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_83 = {{1'd0}, _T_1574[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1579 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1581 = {_T_1574[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1583 = _T_1581 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1584 = _T_1579 | _T_1583; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1588 = {_T_1473,_T_1510,_T_1547,_T_1584}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1592 = {{16'd0}, _T_1588[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1594 = {_T_1588[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1596 = _T_1594 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_84 = {{8'd0}, _T_1597[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1602 = _GEN_84 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1604 = {_T_1597[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1606 = _T_1604 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_85 = {{4'd0}, _T_1607[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1612 = _GEN_85 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1614 = {_T_1607[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1616 = _T_1614 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_86 = {{2'd0}, _T_1617[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1622 = _GEN_86 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1624 = {_T_1617[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1626 = _T_1624 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1627 = _T_1622 | _T_1626; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_87 = {{1'd0}, _T_1627[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1632 = _GEN_87 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1634 = {_T_1627[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1636 = _T_1634 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire _T_1638 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[lsu_dccm_ctl.scala 264:105]
|
|
wire _T_1640 = ~store_byteen_ext_r[4]; // @[lsu_dccm_ctl.scala 264:131]
|
|
wire _T_1641 = _T_1638 & _T_1640; // @[lsu_dccm_ctl.scala 264:129]
|
|
wire [7:0] _T_1645 = _T_1641 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 264:79]
|
|
wire [7:0] _T_1649 = {{4'd0}, _T_1645[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1651 = {_T_1645[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1653 = _T_1651 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_88 = {{2'd0}, _T_1654[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1659 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1661 = {_T_1654[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1663 = _T_1661 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1664 = _T_1659 | _T_1663; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_89 = {{1'd0}, _T_1664[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1669 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1671 = {_T_1664[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1673 = _T_1671 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1674 = _T_1669 | _T_1673; // @[Bitwise.scala 103:39]
|
|
wire _T_1677 = ~store_byteen_ext_r[5]; // @[lsu_dccm_ctl.scala 264:131]
|
|
wire _T_1678 = _T_1638 & _T_1677; // @[lsu_dccm_ctl.scala 264:129]
|
|
wire [7:0] _T_1682 = _T_1678 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 264:79]
|
|
wire [7:0] _T_1686 = {{4'd0}, _T_1682[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1688 = {_T_1682[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1690 = _T_1688 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_90 = {{2'd0}, _T_1691[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1696 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1698 = {_T_1691[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1700 = _T_1698 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1701 = _T_1696 | _T_1700; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_91 = {{1'd0}, _T_1701[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1706 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1708 = {_T_1701[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1710 = _T_1708 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1711 = _T_1706 | _T_1710; // @[Bitwise.scala 103:39]
|
|
wire _T_1714 = ~store_byteen_ext_r[6]; // @[lsu_dccm_ctl.scala 264:131]
|
|
wire _T_1715 = _T_1638 & _T_1714; // @[lsu_dccm_ctl.scala 264:129]
|
|
wire [7:0] _T_1719 = _T_1715 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 264:79]
|
|
wire [7:0] _T_1723 = {{4'd0}, _T_1719[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1725 = {_T_1719[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1727 = _T_1725 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_92 = {{2'd0}, _T_1728[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1733 = _GEN_92 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1735 = {_T_1728[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1737 = _T_1735 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1738 = _T_1733 | _T_1737; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_93 = {{1'd0}, _T_1738[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1743 = _GEN_93 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1745 = {_T_1738[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1747 = _T_1745 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1748 = _T_1743 | _T_1747; // @[Bitwise.scala 103:39]
|
|
wire _T_1751 = ~store_byteen_ext_r[7]; // @[lsu_dccm_ctl.scala 264:131]
|
|
wire _T_1752 = _T_1638 & _T_1751; // @[lsu_dccm_ctl.scala 264:129]
|
|
wire [7:0] _T_1756 = _T_1752 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 264:79]
|
|
wire [7:0] _T_1760 = {{4'd0}, _T_1756[7:4]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1762 = {_T_1756[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1764 = _T_1762 & 8'hf0; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1765 = _T_1760 | _T_1764; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_94 = {{2'd0}, _T_1765[7:2]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1770 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1772 = {_T_1765[5:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1774 = _T_1772 & 8'hcc; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1775 = _T_1770 | _T_1774; // @[Bitwise.scala 103:39]
|
|
wire [7:0] _GEN_95 = {{1'd0}, _T_1775[7:1]}; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1780 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31]
|
|
wire [7:0] _T_1782 = {_T_1775[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [7:0] _T_1784 = _T_1782 & 8'haa; // @[Bitwise.scala 103:75]
|
|
wire [7:0] _T_1785 = _T_1780 | _T_1784; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _T_1789 = {_T_1674,_T_1711,_T_1748,_T_1785}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1793 = {{16'd0}, _T_1789[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1795 = {_T_1789[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1797 = _T_1795 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1798 = _T_1793 | _T_1797; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_96 = {{8'd0}, _T_1798[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1803 = _GEN_96 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1805 = {_T_1798[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1807 = _T_1805 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1808 = _T_1803 | _T_1807; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_97 = {{4'd0}, _T_1808[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1813 = _GEN_97 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1815 = {_T_1808[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1817 = _T_1815 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1818 = _T_1813 | _T_1817; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_98 = {{2'd0}, _T_1818[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1823 = _GEN_98 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1825 = {_T_1818[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1827 = _T_1825 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1828 = _T_1823 | _T_1827; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_99 = {{1'd0}, _T_1828[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1833 = _GEN_99 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1835 = {_T_1828[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1837 = _T_1835 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [63:0] _T_1841 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_100 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 265:94]
|
|
wire [5:0] _T_1843 = 4'h8 * _GEN_100; // @[lsu_dccm_ctl.scala 265:94]
|
|
wire [63:0] _T_1844 = _T_1841 >> _T_1843; // @[lsu_dccm_ctl.scala 265:88]
|
|
wire [7:0] _T_1847 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1850 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1853 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1856 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1860 = {_T_1847,_T_1850,_T_1853,_T_1856}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1864 = {{16'd0}, _T_1860[31:16]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1866 = {_T_1860[15:0], 16'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1868 = _T_1866 & 32'hffff0000; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1869 = _T_1864 | _T_1868; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_101 = {{8'd0}, _T_1869[31:8]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1874 = _GEN_101 & 32'hff00ff; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1876 = {_T_1869[23:0], 8'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1878 = _T_1876 & 32'hff00ff00; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1879 = _T_1874 | _T_1878; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_102 = {{4'd0}, _T_1879[31:4]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1884 = _GEN_102 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1886 = {_T_1879[27:0], 4'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1888 = _T_1886 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1889 = _T_1884 | _T_1888; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_103 = {{2'd0}, _T_1889[31:2]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1894 = _GEN_103 & 32'h33333333; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1896 = {_T_1889[29:0], 2'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1898 = _T_1896 & 32'hcccccccc; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1899 = _T_1894 | _T_1898; // @[Bitwise.scala 103:39]
|
|
wire [31:0] _GEN_104 = {{1'd0}, _T_1899[31:1]}; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1904 = _GEN_104 & 32'h55555555; // @[Bitwise.scala 103:31]
|
|
wire [31:0] _T_1906 = {_T_1899[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
|
wire [31:0] _T_1908 = _T_1906 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
|
wire [31:0] _T_1909 = _T_1904 | _T_1908; // @[Bitwise.scala 103:39]
|
|
wire [63:0] _GEN_105 = {{32'd0}, _T_1909}; // @[lsu_dccm_ctl.scala 265:115]
|
|
wire [63:0] _T_1910 = _T_1844 & _GEN_105; // @[lsu_dccm_ctl.scala 265:115]
|
|
wire _T_1915 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58]
|
|
wire _T_1916 = _T_1915 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84]
|
|
wire _T_1917 = _T_1916 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103]
|
|
wire _T_1919 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58]
|
|
wire _T_1921 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58]
|
|
wire [31:0] _T_1925 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
|
|
wire [14:0] _T_1931 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93]
|
|
wire [31:0] _T_1932 = {17'h0,_T_1931}; // @[Cat.scala 29:58]
|
|
reg _T_1939; // @[lsu_dccm_ctl.scala 280:61]
|
|
wire _T_1945 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_dccm_ctl.scala 285:90]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
assign io_lsu_ld_data_corr_r = _T_818[31:0]; // @[lsu_dccm_ctl.scala 157:28]
|
|
assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 268:27]
|
|
assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 267:27]
|
|
assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 270:27]
|
|
assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 269:27]
|
|
assign io_lsu_ld_data_m = _T_821[31:0]; // @[lsu_dccm_ctl.scala 121:20 lsu_dccm_ctl.scala 158:28]
|
|
assign io_store_data_hi_r = _T_1436; // @[lsu_dccm_ctl.scala 262:29]
|
|
assign io_store_data_lo_r = _T_1225; // @[lsu_dccm_ctl.scala 261:29]
|
|
assign io_store_datafn_hi_r = _T_1833 | _T_1837; // @[lsu_dccm_ctl.scala 264:29]
|
|
assign io_store_datafn_lo_r = _T_1632 | _T_1636; // @[lsu_dccm_ctl.scala 263:29]
|
|
assign io_store_data_r = _T_1910[31:0]; // @[lsu_dccm_ctl.scala 265:29]
|
|
assign io_ld_single_ecc_error_r = _T_873 & _T_874; // @[lsu_dccm_ctl.scala 171:34]
|
|
assign io_ld_single_ecc_error_r_ff = _T_890 & _T_891; // @[lsu_dccm_ctl.scala 178:31]
|
|
assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 277:27]
|
|
assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_905; // @[lsu_dccm_ctl.scala 179:31]
|
|
assign io_lsu_dccm_rden_m = _T_1939; // @[lsu_dccm_ctl.scala 280:24]
|
|
assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 145:41]
|
|
assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[lsu_dccm_ctl.scala 146:41]
|
|
assign io_dma_dccm_ctl_dccm_dma_rtag = io_dma_mem_tag_m; // @[lsu_dccm_ctl.scala 148:41]
|
|
assign io_dma_dccm_ctl_dccm_dma_rdata = io_ldst_dual_m ? lsu_rdata_corr_m : _T_4; // @[lsu_dccm_ctl.scala 147:41]
|
|
assign io_dccm_wren = _T_907 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22]
|
|
assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 186:22]
|
|
assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_914 : _T_918; // @[lsu_dccm_ctl.scala 188:22]
|
|
assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_924 : _T_928; // @[lsu_dccm_ctl.scala 192:22]
|
|
assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 196:22]
|
|
assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 197:22]
|
|
assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_940 : _T_948; // @[lsu_dccm_ctl.scala 199:22]
|
|
assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_958 : _T_966; // @[lsu_dccm_ctl.scala 205:22]
|
|
assign io_lsu_pic_picm_wren = _T_1917 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35]
|
|
assign io_lsu_pic_picm_rden = _T_1919 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35]
|
|
assign io_lsu_pic_picm_mken = _T_1921 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35]
|
|
assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1925; // @[lsu_dccm_ctl.scala 275:35]
|
|
assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1932; // @[lsu_dccm_ctl.scala 276:35]
|
|
assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = _T_814 | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = _T_1432 | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {2{`RANDOM}};
|
|
_T_818 = _RAND_0[63:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
ld_single_ecc_error_lo_r_ff = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
ld_single_ecc_error_hi_r_ff = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
lsu_double_ecc_error_r_ff = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
ld_sec_addr_lo_r_ff = _RAND_4[15:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
ld_sec_addr_hi_r_ff = _RAND_5[15:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_1225 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_1436 = _RAND_7[31:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_1939 = _RAND_8[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_818 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_single_ecc_error_lo_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_single_ecc_error_hi_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_double_ecc_error_r_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_sec_addr_lo_r_ff = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
ld_sec_addr_hi_r_ff = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1225 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1436 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1939 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_818 <= 64'h0;
|
|
end else if (_T_815) begin
|
|
_T_818 <= lsu_ld_data_corr_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_single_ecc_error_lo_r_ff <= 1'h0;
|
|
end else begin
|
|
ld_single_ecc_error_lo_r_ff <= _T_877 & _T_878;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ld_single_ecc_error_hi_r_ff <= 1'h0;
|
|
end else begin
|
|
ld_single_ecc_error_hi_r_ff <= _T_880 & _T_881;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_double_ecc_error_r_ff <= 1'h0;
|
|
end else begin
|
|
lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ld_sec_addr_lo_r_ff <= 16'h0;
|
|
end else if (_T_1945) begin
|
|
ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ld_sec_addr_hi_r_ff <= 16'h0;
|
|
end else if (_T_1945) begin
|
|
ld_sec_addr_hi_r_ff <= io_end_addr_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1225 <= 32'h0;
|
|
end else begin
|
|
_T_1225 <= _T_1219 | _T_1223;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1436 <= 32'h0;
|
|
end else if (_T_1433) begin
|
|
_T_1436 <= _T_1430;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1939 <= 1'h0;
|
|
end else begin
|
|
_T_1939 <= _T_889 & io_addr_in_dccm_d;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_stbuf(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_stbuf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_dword,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_dma,
|
|
input io_store_stbuf_reqvld_r,
|
|
input io_lsu_commit_r,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [31:0] io_store_data_hi_r,
|
|
input [31:0] io_store_data_lo_r,
|
|
input [31:0] io_store_datafn_hi_r,
|
|
input [31:0] io_store_datafn_lo_r,
|
|
input io_lsu_stbuf_commit_any,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_end_addr_r,
|
|
input io_ldst_dual_d,
|
|
input io_ldst_dual_m,
|
|
input io_ldst_dual_r,
|
|
input io_addr_in_dccm_m,
|
|
input io_addr_in_dccm_r,
|
|
output io_stbuf_reqvld_any,
|
|
output io_stbuf_reqvld_flushed_any,
|
|
output [15:0] io_stbuf_addr_any,
|
|
output [31:0] io_stbuf_data_any,
|
|
output io_lsu_stbuf_full_any,
|
|
output io_ldst_stbuf_reqvld_r,
|
|
output [31:0] io_stbuf_fwddata_hi_m,
|
|
output [31:0] io_stbuf_fwddata_lo_m,
|
|
output [3:0] io_stbuf_fwdbyteen_hi_m,
|
|
output [3:0] io_stbuf_fwdbyteen_lo_m
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_18 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_8 = _GEN_18 | _T_5; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_19 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_9 = _GEN_19 | _T_6; // @[Mux.scala 27:72]
|
|
wire [7:0] _GEN_20 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
|
|
wire [7:0] ldst_byteen_r = _GEN_20 | _T_7; // @[Mux.scala 27:72]
|
|
wire dual_stbuf_write_r = io_ldst_dual_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 115:43]
|
|
wire [10:0] _GEN_21 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 117:39]
|
|
wire [10:0] _T_12 = _GEN_21 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 117:39]
|
|
wire [7:0] store_byteen_ext_r = _T_12[7:0]; // @[lsu_stbuf.scala 117:22]
|
|
wire [3:0] _T_15 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_15; // @[lsu_stbuf.scala 118:52]
|
|
wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_15; // @[lsu_stbuf.scala 119:52]
|
|
reg [1:0] RdPtr; // @[Reg.scala 27:20]
|
|
wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[lsu_stbuf.scala 121:26]
|
|
reg [1:0] WrPtr; // @[Reg.scala 27:20]
|
|
wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 122:26]
|
|
wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 123:26]
|
|
wire _T_22 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 125:46]
|
|
reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20]
|
|
wire _T_26 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
|
|
reg _T_587; // @[lsu_stbuf.scala 160:14]
|
|
reg _T_579; // @[lsu_stbuf.scala 160:14]
|
|
reg _T_571; // @[lsu_stbuf.scala 160:14]
|
|
reg _T_563; // @[lsu_stbuf.scala 160:14]
|
|
wire [3:0] stbuf_vld = {_T_587,_T_579,_T_571,_T_563}; // @[Cat.scala 29:58]
|
|
wire _T_28 = _T_26 & stbuf_vld[0]; // @[lsu_stbuf.scala 127:179]
|
|
reg _T_622; // @[lsu_stbuf.scala 163:14]
|
|
reg _T_614; // @[lsu_stbuf.scala 163:14]
|
|
reg _T_606; // @[lsu_stbuf.scala 163:14]
|
|
reg _T_598; // @[lsu_stbuf.scala 163:14]
|
|
wire [3:0] stbuf_dma_kill = {_T_622,_T_614,_T_606,_T_598}; // @[Cat.scala 29:58]
|
|
wire _T_30 = ~stbuf_dma_kill[0]; // @[lsu_stbuf.scala 127:197]
|
|
wire _T_31 = _T_28 & _T_30; // @[lsu_stbuf.scala 127:195]
|
|
wire _T_211 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[lsu_stbuf.scala 138:81]
|
|
wire _T_212 = 2'h3 == RdPtr; // @[lsu_stbuf.scala 138:124]
|
|
wire _T_214 = _T_211 & _T_212; // @[lsu_stbuf.scala 138:112]
|
|
wire _T_208 = 2'h2 == RdPtr; // @[lsu_stbuf.scala 138:124]
|
|
wire _T_210 = _T_211 & _T_208; // @[lsu_stbuf.scala 138:112]
|
|
wire _T_204 = 2'h1 == RdPtr; // @[lsu_stbuf.scala 138:124]
|
|
wire _T_206 = _T_211 & _T_204; // @[lsu_stbuf.scala 138:112]
|
|
wire _T_200 = 2'h0 == RdPtr; // @[lsu_stbuf.scala 138:124]
|
|
wire _T_202 = _T_211 & _T_200; // @[lsu_stbuf.scala 138:112]
|
|
wire [3:0] stbuf_reset = {_T_214,_T_210,_T_206,_T_202}; // @[Cat.scala 29:58]
|
|
wire _T_33 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 127:218]
|
|
wire _T_34 = _T_31 & _T_33; // @[lsu_stbuf.scala 127:216]
|
|
reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20]
|
|
wire _T_37 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
|
|
wire _T_39 = _T_37 & stbuf_vld[1]; // @[lsu_stbuf.scala 127:179]
|
|
wire _T_41 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 127:197]
|
|
wire _T_42 = _T_39 & _T_41; // @[lsu_stbuf.scala 127:195]
|
|
wire _T_44 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 127:218]
|
|
wire _T_45 = _T_42 & _T_44; // @[lsu_stbuf.scala 127:216]
|
|
reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20]
|
|
wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
|
|
wire _T_50 = _T_48 & stbuf_vld[2]; // @[lsu_stbuf.scala 127:179]
|
|
wire _T_52 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 127:197]
|
|
wire _T_53 = _T_50 & _T_52; // @[lsu_stbuf.scala 127:195]
|
|
wire _T_55 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 127:218]
|
|
wire _T_56 = _T_53 & _T_55; // @[lsu_stbuf.scala 127:216]
|
|
reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20]
|
|
wire _T_59 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
|
|
wire _T_61 = _T_59 & stbuf_vld[3]; // @[lsu_stbuf.scala 127:179]
|
|
wire _T_63 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 127:197]
|
|
wire _T_64 = _T_61 & _T_63; // @[lsu_stbuf.scala 127:195]
|
|
wire _T_66 = ~stbuf_reset[3]; // @[lsu_stbuf.scala 127:218]
|
|
wire _T_67 = _T_64 & _T_66; // @[lsu_stbuf.scala 127:216]
|
|
wire [3:0] store_matchvec_lo_r = {_T_67,_T_56,_T_45,_T_34}; // @[Cat.scala 29:58]
|
|
wire _T_72 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120]
|
|
wire _T_74 = _T_72 & stbuf_vld[0]; // @[lsu_stbuf.scala 128:179]
|
|
wire _T_77 = _T_74 & _T_30; // @[lsu_stbuf.scala 128:194]
|
|
wire _T_78 = _T_77 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215]
|
|
wire _T_81 = _T_78 & _T_33; // @[lsu_stbuf.scala 128:236]
|
|
wire _T_84 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120]
|
|
wire _T_86 = _T_84 & stbuf_vld[1]; // @[lsu_stbuf.scala 128:179]
|
|
wire _T_89 = _T_86 & _T_41; // @[lsu_stbuf.scala 128:194]
|
|
wire _T_90 = _T_89 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215]
|
|
wire _T_93 = _T_90 & _T_44; // @[lsu_stbuf.scala 128:236]
|
|
wire _T_96 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120]
|
|
wire _T_98 = _T_96 & stbuf_vld[2]; // @[lsu_stbuf.scala 128:179]
|
|
wire _T_101 = _T_98 & _T_52; // @[lsu_stbuf.scala 128:194]
|
|
wire _T_102 = _T_101 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215]
|
|
wire _T_105 = _T_102 & _T_55; // @[lsu_stbuf.scala 128:236]
|
|
wire _T_108 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 128:120]
|
|
wire _T_110 = _T_108 & stbuf_vld[3]; // @[lsu_stbuf.scala 128:179]
|
|
wire _T_113 = _T_110 & _T_63; // @[lsu_stbuf.scala 128:194]
|
|
wire _T_114 = _T_113 & dual_stbuf_write_r; // @[lsu_stbuf.scala 128:215]
|
|
wire _T_117 = _T_114 & _T_66; // @[lsu_stbuf.scala 128:236]
|
|
wire [3:0] store_matchvec_hi_r = {_T_117,_T_105,_T_93,_T_81}; // @[Cat.scala 29:58]
|
|
wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[lsu_stbuf.scala 130:49]
|
|
wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[lsu_stbuf.scala 131:49]
|
|
wire _T_120 = 2'h0 == WrPtr; // @[lsu_stbuf.scala 134:18]
|
|
wire _T_121 = ~store_coalesce_lo_r; // @[lsu_stbuf.scala 134:31]
|
|
wire _T_122 = _T_120 & _T_121; // @[lsu_stbuf.scala 134:29]
|
|
wire _T_124 = _T_120 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31]
|
|
wire _T_125 = ~store_coalesce_hi_r; // @[lsu_stbuf.scala 135:54]
|
|
wire _T_126 = _T_124 & _T_125; // @[lsu_stbuf.scala 135:52]
|
|
wire _T_127 = _T_122 | _T_126; // @[lsu_stbuf.scala 134:53]
|
|
wire _T_128 = 2'h0 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20]
|
|
wire _T_129 = _T_128 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36]
|
|
wire _T_130 = store_coalesce_lo_r | store_coalesce_hi_r; // @[lsu_stbuf.scala 136:81]
|
|
wire _T_131 = ~_T_130; // @[lsu_stbuf.scala 136:59]
|
|
wire _T_132 = _T_129 & _T_131; // @[lsu_stbuf.scala 136:57]
|
|
wire _T_133 = _T_127 | _T_132; // @[lsu_stbuf.scala 135:76]
|
|
wire _T_135 = _T_133 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 136:105]
|
|
wire _T_137 = _T_135 | store_matchvec_hi_r[0]; // @[lsu_stbuf.scala 137:32]
|
|
wire _T_138 = io_ldst_stbuf_reqvld_r & _T_137; // @[lsu_stbuf.scala 133:79]
|
|
wire _T_139 = 2'h1 == WrPtr; // @[lsu_stbuf.scala 134:18]
|
|
wire _T_141 = _T_139 & _T_121; // @[lsu_stbuf.scala 134:29]
|
|
wire _T_143 = _T_139 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31]
|
|
wire _T_145 = _T_143 & _T_125; // @[lsu_stbuf.scala 135:52]
|
|
wire _T_146 = _T_141 | _T_145; // @[lsu_stbuf.scala 134:53]
|
|
wire _T_147 = 2'h1 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20]
|
|
wire _T_148 = _T_147 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36]
|
|
wire _T_151 = _T_148 & _T_131; // @[lsu_stbuf.scala 136:57]
|
|
wire _T_152 = _T_146 | _T_151; // @[lsu_stbuf.scala 135:76]
|
|
wire _T_154 = _T_152 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 136:105]
|
|
wire _T_156 = _T_154 | store_matchvec_hi_r[1]; // @[lsu_stbuf.scala 137:32]
|
|
wire _T_157 = io_ldst_stbuf_reqvld_r & _T_156; // @[lsu_stbuf.scala 133:79]
|
|
wire _T_158 = 2'h2 == WrPtr; // @[lsu_stbuf.scala 134:18]
|
|
wire _T_160 = _T_158 & _T_121; // @[lsu_stbuf.scala 134:29]
|
|
wire _T_162 = _T_158 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31]
|
|
wire _T_164 = _T_162 & _T_125; // @[lsu_stbuf.scala 135:52]
|
|
wire _T_165 = _T_160 | _T_164; // @[lsu_stbuf.scala 134:53]
|
|
wire _T_166 = 2'h2 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20]
|
|
wire _T_167 = _T_166 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36]
|
|
wire _T_170 = _T_167 & _T_131; // @[lsu_stbuf.scala 136:57]
|
|
wire _T_171 = _T_165 | _T_170; // @[lsu_stbuf.scala 135:76]
|
|
wire _T_173 = _T_171 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 136:105]
|
|
wire _T_175 = _T_173 | store_matchvec_hi_r[2]; // @[lsu_stbuf.scala 137:32]
|
|
wire _T_176 = io_ldst_stbuf_reqvld_r & _T_175; // @[lsu_stbuf.scala 133:79]
|
|
wire _T_177 = 2'h3 == WrPtr; // @[lsu_stbuf.scala 134:18]
|
|
wire _T_179 = _T_177 & _T_121; // @[lsu_stbuf.scala 134:29]
|
|
wire _T_181 = _T_177 & dual_stbuf_write_r; // @[lsu_stbuf.scala 135:31]
|
|
wire _T_183 = _T_181 & _T_125; // @[lsu_stbuf.scala 135:52]
|
|
wire _T_184 = _T_179 | _T_183; // @[lsu_stbuf.scala 134:53]
|
|
wire _T_185 = 2'h3 == WrPtrPlus1; // @[lsu_stbuf.scala 136:20]
|
|
wire _T_186 = _T_185 & dual_stbuf_write_r; // @[lsu_stbuf.scala 136:36]
|
|
wire _T_189 = _T_186 & _T_131; // @[lsu_stbuf.scala 136:57]
|
|
wire _T_190 = _T_184 | _T_189; // @[lsu_stbuf.scala 135:76]
|
|
wire _T_192 = _T_190 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 136:105]
|
|
wire _T_194 = _T_192 | store_matchvec_hi_r[3]; // @[lsu_stbuf.scala 137:32]
|
|
wire _T_195 = io_ldst_stbuf_reqvld_r & _T_194; // @[lsu_stbuf.scala 133:79]
|
|
wire [3:0] stbuf_wr_en = {_T_195,_T_176,_T_157,_T_138}; // @[Cat.scala 29:58]
|
|
wire _T_218 = ~io_ldst_dual_r; // @[lsu_stbuf.scala 139:56]
|
|
wire _T_219 = _T_218 | io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 139:72]
|
|
wire _T_222 = _T_219 & _T_120; // @[lsu_stbuf.scala 139:99]
|
|
wire _T_224 = _T_222 & _T_121; // @[lsu_stbuf.scala 139:129]
|
|
wire _T_226 = _T_224 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 139:153]
|
|
wire _T_231 = _T_219 & _T_139; // @[lsu_stbuf.scala 139:99]
|
|
wire _T_233 = _T_231 & _T_121; // @[lsu_stbuf.scala 139:129]
|
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wire _T_235 = _T_233 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 139:153]
|
|
wire _T_240 = _T_219 & _T_158; // @[lsu_stbuf.scala 139:99]
|
|
wire _T_242 = _T_240 & _T_121; // @[lsu_stbuf.scala 139:129]
|
|
wire _T_244 = _T_242 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 139:153]
|
|
wire _T_249 = _T_219 & _T_177; // @[lsu_stbuf.scala 139:99]
|
|
wire _T_251 = _T_249 & _T_121; // @[lsu_stbuf.scala 139:129]
|
|
wire _T_253 = _T_251 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 139:153]
|
|
wire [3:0] sel_lo = {_T_253,_T_244,_T_235,_T_226}; // @[Cat.scala 29:58]
|
|
reg [3:0] stbuf_byteen_0; // @[lsu_stbuf.scala 166:14]
|
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wire [3:0] _T_273 = stbuf_byteen_0 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89]
|
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wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126]
|
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wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_273 : _T_274; // @[lsu_stbuf.scala 142:61]
|
|
reg [3:0] stbuf_byteen_1; // @[lsu_stbuf.scala 166:14]
|
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wire [3:0] _T_277 = stbuf_byteen_1 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89]
|
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wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126]
|
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wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_277 : _T_278; // @[lsu_stbuf.scala 142:61]
|
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reg [3:0] stbuf_byteen_2; // @[lsu_stbuf.scala 166:14]
|
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wire [3:0] _T_281 = stbuf_byteen_2 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89]
|
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wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126]
|
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wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_281 : _T_282; // @[lsu_stbuf.scala 142:61]
|
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reg [3:0] stbuf_byteen_3; // @[lsu_stbuf.scala 166:14]
|
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wire [3:0] _T_285 = stbuf_byteen_3 | store_byteen_lo_r; // @[lsu_stbuf.scala 142:89]
|
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wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_hi_r; // @[lsu_stbuf.scala 142:126]
|
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wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_285 : _T_286; // @[lsu_stbuf.scala 142:61]
|
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wire _T_290 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 144:70]
|
|
wire _T_292 = _T_290 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
|
|
reg [31:0] stbuf_data_0; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_295 = _T_292 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 144:69]
|
|
wire _T_299 = _T_290 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
|
|
wire [7:0] _T_302 = _T_299 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 145:10]
|
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wire [7:0] datain1_0 = sel_lo[0] ? _T_295 : _T_302; // @[lsu_stbuf.scala 144:54]
|
|
wire _T_306 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 144:70]
|
|
wire _T_308 = _T_306 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
|
|
reg [31:0] stbuf_data_1; // @[Reg.scala 27:20]
|
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wire [7:0] _T_311 = _T_308 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 144:69]
|
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wire _T_315 = _T_306 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
|
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wire [7:0] _T_318 = _T_315 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 145:10]
|
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wire [7:0] datain1_1 = sel_lo[1] ? _T_311 : _T_318; // @[lsu_stbuf.scala 144:54]
|
|
wire _T_322 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 144:70]
|
|
wire _T_324 = _T_322 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
|
|
reg [31:0] stbuf_data_2; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_327 = _T_324 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 144:69]
|
|
wire _T_331 = _T_322 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
|
|
wire [7:0] _T_334 = _T_331 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 145:10]
|
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wire [7:0] datain1_2 = sel_lo[2] ? _T_327 : _T_334; // @[lsu_stbuf.scala 144:54]
|
|
wire _T_338 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 144:70]
|
|
wire _T_340 = _T_338 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
|
|
reg [31:0] stbuf_data_3; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_343 = _T_340 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 144:69]
|
|
wire _T_347 = _T_338 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
|
|
wire [7:0] _T_350 = _T_347 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 145:10]
|
|
wire [7:0] datain1_3 = sel_lo[3] ? _T_343 : _T_350; // @[lsu_stbuf.scala 144:54]
|
|
wire _T_354 = ~stbuf_byteen_0[1]; // @[lsu_stbuf.scala 147:70]
|
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wire _T_356 = _T_354 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90]
|
|
wire [7:0] _T_359 = _T_356 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 147:69]
|
|
wire _T_363 = _T_354 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31]
|
|
wire [7:0] _T_366 = _T_363 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 148:10]
|
|
wire [7:0] datain2_0 = sel_lo[0] ? _T_359 : _T_366; // @[lsu_stbuf.scala 147:54]
|
|
wire _T_370 = ~stbuf_byteen_1[1]; // @[lsu_stbuf.scala 147:70]
|
|
wire _T_372 = _T_370 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90]
|
|
wire [7:0] _T_375 = _T_372 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 147:69]
|
|
wire _T_379 = _T_370 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31]
|
|
wire [7:0] _T_382 = _T_379 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 148:10]
|
|
wire [7:0] datain2_1 = sel_lo[1] ? _T_375 : _T_382; // @[lsu_stbuf.scala 147:54]
|
|
wire _T_386 = ~stbuf_byteen_2[1]; // @[lsu_stbuf.scala 147:70]
|
|
wire _T_388 = _T_386 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90]
|
|
wire [7:0] _T_391 = _T_388 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 147:69]
|
|
wire _T_395 = _T_386 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31]
|
|
wire [7:0] _T_398 = _T_395 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 148:10]
|
|
wire [7:0] datain2_2 = sel_lo[2] ? _T_391 : _T_398; // @[lsu_stbuf.scala 147:54]
|
|
wire _T_402 = ~stbuf_byteen_3[1]; // @[lsu_stbuf.scala 147:70]
|
|
wire _T_404 = _T_402 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 147:90]
|
|
wire [7:0] _T_407 = _T_404 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 147:69]
|
|
wire _T_411 = _T_402 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 148:31]
|
|
wire [7:0] _T_414 = _T_411 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 148:10]
|
|
wire [7:0] datain2_3 = sel_lo[3] ? _T_407 : _T_414; // @[lsu_stbuf.scala 147:54]
|
|
wire _T_418 = ~stbuf_byteen_0[2]; // @[lsu_stbuf.scala 150:70]
|
|
wire _T_420 = _T_418 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90]
|
|
wire [7:0] _T_423 = _T_420 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 150:69]
|
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wire _T_427 = _T_418 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31]
|
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wire [7:0] _T_430 = _T_427 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 151:10]
|
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wire [7:0] datain3_0 = sel_lo[0] ? _T_423 : _T_430; // @[lsu_stbuf.scala 150:54]
|
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wire _T_434 = ~stbuf_byteen_1[2]; // @[lsu_stbuf.scala 150:70]
|
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wire _T_436 = _T_434 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90]
|
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wire [7:0] _T_439 = _T_436 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 150:69]
|
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wire _T_443 = _T_434 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31]
|
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wire [7:0] _T_446 = _T_443 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 151:10]
|
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wire [7:0] datain3_1 = sel_lo[1] ? _T_439 : _T_446; // @[lsu_stbuf.scala 150:54]
|
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wire _T_450 = ~stbuf_byteen_2[2]; // @[lsu_stbuf.scala 150:70]
|
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wire _T_452 = _T_450 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90]
|
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wire [7:0] _T_455 = _T_452 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 150:69]
|
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wire _T_459 = _T_450 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31]
|
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wire [7:0] _T_462 = _T_459 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 151:10]
|
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wire [7:0] datain3_2 = sel_lo[2] ? _T_455 : _T_462; // @[lsu_stbuf.scala 150:54]
|
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wire _T_466 = ~stbuf_byteen_3[2]; // @[lsu_stbuf.scala 150:70]
|
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wire _T_468 = _T_466 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 150:90]
|
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wire [7:0] _T_471 = _T_468 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 150:69]
|
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wire _T_475 = _T_466 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 151:31]
|
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wire [7:0] _T_478 = _T_475 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 151:10]
|
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wire [7:0] datain3_3 = sel_lo[3] ? _T_471 : _T_478; // @[lsu_stbuf.scala 150:54]
|
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wire _T_482 = ~stbuf_byteen_0[3]; // @[lsu_stbuf.scala 153:70]
|
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wire _T_484 = _T_482 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90]
|
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wire [7:0] _T_487 = _T_484 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 153:69]
|
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wire _T_491 = _T_482 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31]
|
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wire [7:0] _T_494 = _T_491 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 154:10]
|
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wire [7:0] datain4_0 = sel_lo[0] ? _T_487 : _T_494; // @[lsu_stbuf.scala 153:54]
|
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wire _T_498 = ~stbuf_byteen_1[3]; // @[lsu_stbuf.scala 153:70]
|
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wire _T_500 = _T_498 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90]
|
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wire [7:0] _T_503 = _T_500 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 153:69]
|
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wire _T_507 = _T_498 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31]
|
|
wire [7:0] _T_510 = _T_507 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 154:10]
|
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wire [7:0] datain4_1 = sel_lo[1] ? _T_503 : _T_510; // @[lsu_stbuf.scala 153:54]
|
|
wire _T_514 = ~stbuf_byteen_2[3]; // @[lsu_stbuf.scala 153:70]
|
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wire _T_516 = _T_514 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90]
|
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wire [7:0] _T_519 = _T_516 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 153:69]
|
|
wire _T_523 = _T_514 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31]
|
|
wire [7:0] _T_526 = _T_523 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 154:10]
|
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wire [7:0] datain4_2 = sel_lo[2] ? _T_519 : _T_526; // @[lsu_stbuf.scala 153:54]
|
|
wire _T_530 = ~stbuf_byteen_3[3]; // @[lsu_stbuf.scala 153:70]
|
|
wire _T_532 = _T_530 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 153:90]
|
|
wire [7:0] _T_535 = _T_532 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 153:69]
|
|
wire _T_539 = _T_530 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31]
|
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wire [7:0] _T_542 = _T_539 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 154:10]
|
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wire [7:0] datain4_3 = sel_lo[3] ? _T_535 : _T_542; // @[lsu_stbuf.scala 153:54]
|
|
wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58]
|
|
wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58]
|
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wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58]
|
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wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58]
|
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wire _T_559 = stbuf_wr_en[0] | stbuf_vld[0]; // @[lsu_stbuf.scala 160:18]
|
|
wire _T_567 = stbuf_wr_en[1] | stbuf_vld[1]; // @[lsu_stbuf.scala 160:18]
|
|
wire _T_575 = stbuf_wr_en[2] | stbuf_vld[2]; // @[lsu_stbuf.scala 160:18]
|
|
wire _T_583 = stbuf_wr_en[3] | stbuf_vld[3]; // @[lsu_stbuf.scala 160:18]
|
|
wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[lsu_stbuf.scala 208:16]
|
|
wire _T_786 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115]
|
|
wire _T_788 = _T_786 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:139]
|
|
wire _T_791 = _T_788 & _T_63; // @[lsu_stbuf.scala 212:154]
|
|
wire _T_792 = _T_791 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175]
|
|
wire _T_777 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115]
|
|
wire _T_779 = _T_777 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:139]
|
|
wire _T_782 = _T_779 & _T_52; // @[lsu_stbuf.scala 212:154]
|
|
wire _T_783 = _T_782 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175]
|
|
wire _T_768 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115]
|
|
wire _T_770 = _T_768 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:139]
|
|
wire _T_773 = _T_770 & _T_41; // @[lsu_stbuf.scala 212:154]
|
|
wire _T_774 = _T_773 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175]
|
|
wire _T_759 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 212:115]
|
|
wire _T_761 = _T_759 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:139]
|
|
wire _T_764 = _T_761 & _T_30; // @[lsu_stbuf.scala 212:154]
|
|
wire _T_765 = _T_764 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 212:175]
|
|
wire [3:0] stbuf_match_hi = {_T_792,_T_783,_T_774,_T_765}; // @[Cat.scala 29:58]
|
|
wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[lsu_stbuf.scala 209:17]
|
|
wire _T_824 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115]
|
|
wire _T_826 = _T_824 & stbuf_vld[3]; // @[lsu_stbuf.scala 213:139]
|
|
wire _T_829 = _T_826 & _T_63; // @[lsu_stbuf.scala 213:154]
|
|
wire _T_830 = _T_829 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175]
|
|
wire _T_815 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115]
|
|
wire _T_817 = _T_815 & stbuf_vld[2]; // @[lsu_stbuf.scala 213:139]
|
|
wire _T_820 = _T_817 & _T_52; // @[lsu_stbuf.scala 213:154]
|
|
wire _T_821 = _T_820 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175]
|
|
wire _T_806 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115]
|
|
wire _T_808 = _T_806 & stbuf_vld[1]; // @[lsu_stbuf.scala 213:139]
|
|
wire _T_811 = _T_808 & _T_41; // @[lsu_stbuf.scala 213:154]
|
|
wire _T_812 = _T_811 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175]
|
|
wire _T_797 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 213:115]
|
|
wire _T_799 = _T_797 & stbuf_vld[0]; // @[lsu_stbuf.scala 213:139]
|
|
wire _T_802 = _T_799 & _T_30; // @[lsu_stbuf.scala 213:154]
|
|
wire _T_803 = _T_802 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 213:175]
|
|
wire [3:0] stbuf_match_lo = {_T_830,_T_821,_T_812,_T_803}; // @[Cat.scala 29:58]
|
|
wire _T_853 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[lsu_stbuf.scala 214:78]
|
|
wire _T_854 = _T_853 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99]
|
|
wire _T_855 = _T_854 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120]
|
|
wire _T_856 = _T_855 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144]
|
|
wire _T_847 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[lsu_stbuf.scala 214:78]
|
|
wire _T_848 = _T_847 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99]
|
|
wire _T_849 = _T_848 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120]
|
|
wire _T_850 = _T_849 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144]
|
|
wire _T_841 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[lsu_stbuf.scala 214:78]
|
|
wire _T_842 = _T_841 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99]
|
|
wire _T_843 = _T_842 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120]
|
|
wire _T_844 = _T_843 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144]
|
|
wire _T_835 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[lsu_stbuf.scala 214:78]
|
|
wire _T_836 = _T_835 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 214:99]
|
|
wire _T_837 = _T_836 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 214:120]
|
|
wire _T_838 = _T_837 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 214:144]
|
|
wire [3:0] stbuf_dma_kill_en = {_T_856,_T_850,_T_844,_T_838}; // @[Cat.scala 29:58]
|
|
wire _T_594 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[lsu_stbuf.scala 163:18]
|
|
wire _T_602 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[lsu_stbuf.scala 163:18]
|
|
wire _T_610 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[lsu_stbuf.scala 163:18]
|
|
wire _T_618 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[lsu_stbuf.scala 163:18]
|
|
wire [3:0] _T_628 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[lsu_stbuf.scala 166:18]
|
|
wire [3:0] _T_632 = _T_33 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_637 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[lsu_stbuf.scala 166:18]
|
|
wire [3:0] _T_641 = _T_44 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_646 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[lsu_stbuf.scala 166:18]
|
|
wire [3:0] _T_650 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_655 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[lsu_stbuf.scala 166:18]
|
|
wire [3:0] _T_659 = _T_66 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_686 = stbuf_vld >> RdPtr; // @[lsu_stbuf.scala 183:43]
|
|
wire [3:0] _T_688 = stbuf_dma_kill >> RdPtr; // @[lsu_stbuf.scala 183:67]
|
|
wire _T_695 = ~_T_688[0]; // @[lsu_stbuf.scala 184:46]
|
|
wire _T_696 = _T_686[0] & _T_695; // @[lsu_stbuf.scala 184:44]
|
|
wire _T_697 = |stbuf_dma_kill_en; // @[lsu_stbuf.scala 184:91]
|
|
wire _T_698 = ~_T_697; // @[lsu_stbuf.scala 184:71]
|
|
wire [15:0] _GEN_9 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 185:22]
|
|
wire [15:0] _GEN_10 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_9; // @[lsu_stbuf.scala 185:22]
|
|
wire [31:0] _GEN_13 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 186:22]
|
|
wire [31:0] _GEN_14 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_13; // @[lsu_stbuf.scala 186:22]
|
|
wire _T_700 = ~dual_stbuf_write_r; // @[lsu_stbuf.scala 188:44]
|
|
wire _T_701 = io_ldst_stbuf_reqvld_r & _T_700; // @[lsu_stbuf.scala 188:42]
|
|
wire _T_702 = store_coalesce_hi_r | store_coalesce_lo_r; // @[lsu_stbuf.scala 188:88]
|
|
wire _T_703 = ~_T_702; // @[lsu_stbuf.scala 188:66]
|
|
wire _T_704 = _T_701 & _T_703; // @[lsu_stbuf.scala 188:64]
|
|
wire _T_705 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[lsu_stbuf.scala 189:30]
|
|
wire _T_706 = store_coalesce_hi_r & store_coalesce_lo_r; // @[lsu_stbuf.scala 189:76]
|
|
wire _T_707 = ~_T_706; // @[lsu_stbuf.scala 189:54]
|
|
wire _T_708 = _T_705 & _T_707; // @[lsu_stbuf.scala 189:52]
|
|
wire WrPtrEn = _T_704 | _T_708; // @[lsu_stbuf.scala 188:113]
|
|
wire _T_713 = _T_705 & _T_703; // @[lsu_stbuf.scala 190:67]
|
|
wire [3:0] _T_718 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_720 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_722 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_724 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_727 = _T_718 + _T_720; // @[lsu_stbuf.scala 197:101]
|
|
wire [3:0] _T_729 = _T_727 + _T_722; // @[lsu_stbuf.scala 197:101]
|
|
wire [3:0] stbuf_numvld_any = _T_729 + _T_724; // @[lsu_stbuf.scala 197:101]
|
|
wire _T_731 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 198:39]
|
|
wire _T_732 = _T_731 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 198:65]
|
|
wire _T_733 = ~io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 198:87]
|
|
wire isdccmst_m = _T_732 & _T_733; // @[lsu_stbuf.scala 198:85]
|
|
wire _T_734 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 199:39]
|
|
wire _T_735 = _T_734 & io_addr_in_dccm_r; // @[lsu_stbuf.scala 199:65]
|
|
wire _T_736 = ~io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 199:87]
|
|
wire isdccmst_r = _T_735 & _T_736; // @[lsu_stbuf.scala 199:85]
|
|
wire [1:0] _T_737 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58]
|
|
wire _T_738 = isdccmst_m & io_ldst_dual_m; // @[lsu_stbuf.scala 201:62]
|
|
wire [2:0] _GEN_22 = {{1'd0}, _T_737}; // @[lsu_stbuf.scala 201:47]
|
|
wire [2:0] _T_739 = _GEN_22 << _T_738; // @[lsu_stbuf.scala 201:47]
|
|
wire [1:0] _T_740 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58]
|
|
wire _T_741 = isdccmst_r & io_ldst_dual_r; // @[lsu_stbuf.scala 202:62]
|
|
wire [2:0] _GEN_23 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 202:47]
|
|
wire [2:0] _T_742 = _GEN_23 << _T_741; // @[lsu_stbuf.scala 202:47]
|
|
wire [1:0] stbuf_specvld_m = _T_739[1:0]; // @[lsu_stbuf.scala 201:19]
|
|
wire [3:0] _T_743 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_745 = stbuf_numvld_any + _T_743; // @[lsu_stbuf.scala 203:44]
|
|
wire [1:0] stbuf_specvld_r = _T_742[1:0]; // @[lsu_stbuf.scala 202:19]
|
|
wire [3:0] _T_746 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58]
|
|
wire [3:0] stbuf_specvld_any = _T_745 + _T_746; // @[lsu_stbuf.scala 203:78]
|
|
wire _T_748 = ~io_ldst_dual_d; // @[lsu_stbuf.scala 205:34]
|
|
wire _T_749 = _T_748 & io_dec_lsu_valid_raw_d; // @[lsu_stbuf.scala 205:50]
|
|
wire _T_751 = stbuf_specvld_any >= 4'h4; // @[lsu_stbuf.scala 205:102]
|
|
wire _T_752 = stbuf_specvld_any >= 4'h3; // @[lsu_stbuf.scala 205:143]
|
|
wire _T_862 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_0 = _T_862 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_866 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_1 = _T_866 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_870 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_2 = _T_870 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_874 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_0_3 = _T_874 & stbuf_vld[0]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_878 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_0 = _T_878 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_882 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_1 = _T_882 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_886 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_2 = _T_886 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_890 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_1_3 = _T_890 & stbuf_vld[1]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_894 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_0 = _T_894 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_898 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_1 = _T_898 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_902 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_2 = _T_902 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_906 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_2_3 = _T_906 & stbuf_vld[2]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_910 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_0 = _T_910 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_914 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_1 = _T_914 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_918 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_2 = _T_918 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_922 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 217:116]
|
|
wire stbuf_fwdbyteenvec_hi_3_3 = _T_922 & stbuf_vld[3]; // @[lsu_stbuf.scala 217:137]
|
|
wire _T_926 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_0 = _T_926 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_930 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_1 = _T_930 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_934 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_2 = _T_934 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_938 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_0_3 = _T_938 & stbuf_vld[0]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_942 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_0 = _T_942 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_946 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_1 = _T_946 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_950 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_2 = _T_950 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_954 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_1_3 = _T_954 & stbuf_vld[1]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_958 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_0 = _T_958 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_962 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_1 = _T_962 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_966 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_2 = _T_966 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_970 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_2_3 = _T_970 & stbuf_vld[2]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_974 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_0 = _T_974 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_978 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_1 = _T_978 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_982 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_2 = _T_982 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_986 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 218:116]
|
|
wire stbuf_fwdbyteenvec_lo_3_3 = _T_986 & stbuf_vld[3]; // @[lsu_stbuf.scala 218:137]
|
|
wire _T_988 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_989 = _T_988 | stbuf_fwdbyteenvec_hi_2_0; // @[lsu_stbuf.scala 219:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_0 = _T_989 | stbuf_fwdbyteenvec_hi_3_0; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_990 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_991 = _T_990 | stbuf_fwdbyteenvec_hi_2_1; // @[lsu_stbuf.scala 219:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_1 = _T_991 | stbuf_fwdbyteenvec_hi_3_1; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_992 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_993 = _T_992 | stbuf_fwdbyteenvec_hi_2_2; // @[lsu_stbuf.scala 219:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_2 = _T_993 | stbuf_fwdbyteenvec_hi_3_2; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_994 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_995 = _T_994 | stbuf_fwdbyteenvec_hi_2_3; // @[lsu_stbuf.scala 219:147]
|
|
wire stbuf_fwdbyteen_hi_pre_m_3 = _T_995 | stbuf_fwdbyteenvec_hi_3_3; // @[lsu_stbuf.scala 219:147]
|
|
wire _T_996 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_997 = _T_996 | stbuf_fwdbyteenvec_lo_2_0; // @[lsu_stbuf.scala 220:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_0 = _T_997 | stbuf_fwdbyteenvec_lo_3_0; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_998 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_999 = _T_998 | stbuf_fwdbyteenvec_lo_2_1; // @[lsu_stbuf.scala 220:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_1 = _T_999 | stbuf_fwdbyteenvec_lo_3_1; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_1000 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_1001 = _T_1000 | stbuf_fwdbyteenvec_lo_2_2; // @[lsu_stbuf.scala 220:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1001 | stbuf_fwdbyteenvec_lo_3_2; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_1002 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[lsu_stbuf.scala 220:147]
|
|
wire _T_1003 = _T_1002 | stbuf_fwdbyteenvec_lo_2_3; // @[lsu_stbuf.scala 220:147]
|
|
wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1003 | stbuf_fwdbyteenvec_lo_3_3; // @[lsu_stbuf.scala 220:147]
|
|
wire [31:0] _T_1006 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1007 = _T_1006 & stbuf_data_0; // @[lsu_stbuf.scala 222:97]
|
|
wire [31:0] _T_1010 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1011 = _T_1010 & stbuf_data_1; // @[lsu_stbuf.scala 222:97]
|
|
wire [31:0] _T_1014 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1015 = _T_1014 & stbuf_data_2; // @[lsu_stbuf.scala 222:97]
|
|
wire [31:0] _T_1018 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1019 = _T_1018 & stbuf_data_3; // @[lsu_stbuf.scala 222:97]
|
|
wire [31:0] _T_1021 = _T_1019 | _T_1015; // @[lsu_stbuf.scala 222:130]
|
|
wire [31:0] _T_1022 = _T_1021 | _T_1011; // @[lsu_stbuf.scala 222:130]
|
|
wire [31:0] stbuf_fwddata_hi_pre_m = _T_1022 | _T_1007; // @[lsu_stbuf.scala 222:130]
|
|
wire [31:0] _T_1025 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1026 = _T_1025 & stbuf_data_0; // @[lsu_stbuf.scala 223:97]
|
|
wire [31:0] _T_1029 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1030 = _T_1029 & stbuf_data_1; // @[lsu_stbuf.scala 223:97]
|
|
wire [31:0] _T_1033 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1034 = _T_1033 & stbuf_data_2; // @[lsu_stbuf.scala 223:97]
|
|
wire [31:0] _T_1037 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_1038 = _T_1037 & stbuf_data_3; // @[lsu_stbuf.scala 223:97]
|
|
wire [31:0] _T_1040 = _T_1038 | _T_1034; // @[lsu_stbuf.scala 223:130]
|
|
wire [31:0] _T_1041 = _T_1040 | _T_1030; // @[lsu_stbuf.scala 223:130]
|
|
wire [31:0] stbuf_fwddata_lo_pre_m = _T_1041 | _T_1026; // @[lsu_stbuf.scala 223:130]
|
|
wire _T_1046 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 230:49]
|
|
wire _T_1047 = _T_1046 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 230:74]
|
|
wire _T_1048 = _T_1047 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 230:95]
|
|
wire ld_addr_rhit_lo_lo = _T_1048 & _T_736; // @[lsu_stbuf.scala 230:121]
|
|
wire _T_1052 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 231:49]
|
|
wire _T_1053 = _T_1052 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 231:74]
|
|
wire _T_1054 = _T_1053 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 231:95]
|
|
wire ld_addr_rhit_lo_hi = _T_1054 & _T_736; // @[lsu_stbuf.scala 231:121]
|
|
wire _T_1058 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 232:49]
|
|
wire _T_1059 = _T_1058 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 232:74]
|
|
wire _T_1060 = _T_1059 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 232:95]
|
|
wire _T_1062 = _T_1060 & _T_736; // @[lsu_stbuf.scala 232:121]
|
|
wire ld_addr_rhit_hi_lo = _T_1062 & dual_stbuf_write_r; // @[lsu_stbuf.scala 232:146]
|
|
wire _T_1065 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 233:49]
|
|
wire _T_1066 = _T_1065 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 233:74]
|
|
wire _T_1067 = _T_1066 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 233:95]
|
|
wire _T_1069 = _T_1067 & _T_736; // @[lsu_stbuf.scala 233:121]
|
|
wire ld_addr_rhit_hi_hi = _T_1069 & dual_stbuf_write_r; // @[lsu_stbuf.scala 233:146]
|
|
wire _T_1071 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 235:79]
|
|
wire _T_1073 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 235:79]
|
|
wire _T_1075 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 235:79]
|
|
wire _T_1077 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 235:79]
|
|
wire [3:0] ld_byte_rhit_lo_lo = {_T_1077,_T_1075,_T_1073,_T_1071}; // @[Cat.scala 29:58]
|
|
wire _T_1082 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 236:79]
|
|
wire _T_1084 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 236:79]
|
|
wire _T_1086 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 236:79]
|
|
wire _T_1088 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 236:79]
|
|
wire [3:0] ld_byte_rhit_lo_hi = {_T_1088,_T_1086,_T_1084,_T_1082}; // @[Cat.scala 29:58]
|
|
wire _T_1093 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 237:79]
|
|
wire _T_1095 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 237:79]
|
|
wire _T_1097 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 237:79]
|
|
wire _T_1099 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 237:79]
|
|
wire [3:0] ld_byte_rhit_hi_lo = {_T_1099,_T_1097,_T_1095,_T_1093}; // @[Cat.scala 29:58]
|
|
wire _T_1104 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 238:79]
|
|
wire _T_1106 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 238:79]
|
|
wire _T_1108 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 238:79]
|
|
wire _T_1110 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 238:79]
|
|
wire [3:0] ld_byte_rhit_hi_hi = {_T_1110,_T_1108,_T_1106,_T_1104}; // @[Cat.scala 29:58]
|
|
wire _T_1116 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_stbuf.scala 240:79]
|
|
wire _T_1119 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_stbuf.scala 240:79]
|
|
wire _T_1122 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_stbuf.scala 240:79]
|
|
wire _T_1125 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_stbuf.scala 240:79]
|
|
wire [3:0] ld_byte_rhit_lo = {_T_1125,_T_1122,_T_1119,_T_1116}; // @[Cat.scala 29:58]
|
|
wire _T_1131 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_stbuf.scala 241:79]
|
|
wire _T_1134 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_stbuf.scala 241:79]
|
|
wire _T_1137 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_stbuf.scala 241:79]
|
|
wire _T_1140 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_stbuf.scala 241:79]
|
|
wire [3:0] ld_byte_rhit_hi = {_T_1140,_T_1137,_T_1134,_T_1131}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1146 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1148 = _T_1146 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 243:53]
|
|
wire [7:0] _T_1151 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1153 = _T_1151 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 243:114]
|
|
wire [7:0] fwdpipe1_lo = _T_1148 | _T_1153; // @[lsu_stbuf.scala 243:80]
|
|
wire [7:0] _T_1156 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1158 = _T_1156 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 244:53]
|
|
wire [7:0] _T_1161 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1163 = _T_1161 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 244:115]
|
|
wire [7:0] fwdpipe2_lo = _T_1158 | _T_1163; // @[lsu_stbuf.scala 244:81]
|
|
wire [7:0] _T_1166 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1168 = _T_1166 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 245:53]
|
|
wire [7:0] _T_1171 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1173 = _T_1171 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 245:116]
|
|
wire [7:0] fwdpipe3_lo = _T_1168 | _T_1173; // @[lsu_stbuf.scala 245:82]
|
|
wire [7:0] _T_1176 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1178 = _T_1176 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 246:53]
|
|
wire [7:0] _T_1181 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1183 = _T_1181 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 246:116]
|
|
wire [7:0] fwdpipe4_lo = _T_1178 | _T_1183; // @[lsu_stbuf.scala 246:82]
|
|
wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1189 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1191 = _T_1189 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 249:53]
|
|
wire [7:0] _T_1194 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1196 = _T_1194 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 249:114]
|
|
wire [7:0] fwdpipe1_hi = _T_1191 | _T_1196; // @[lsu_stbuf.scala 249:80]
|
|
wire [7:0] _T_1199 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1201 = _T_1199 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 250:53]
|
|
wire [7:0] _T_1204 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1206 = _T_1204 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 250:115]
|
|
wire [7:0] fwdpipe2_hi = _T_1201 | _T_1206; // @[lsu_stbuf.scala 250:81]
|
|
wire [7:0] _T_1209 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1211 = _T_1209 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 251:53]
|
|
wire [7:0] _T_1214 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1216 = _T_1214 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 251:116]
|
|
wire [7:0] fwdpipe3_hi = _T_1211 | _T_1216; // @[lsu_stbuf.scala 251:82]
|
|
wire [7:0] _T_1219 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1221 = _T_1219 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 252:53]
|
|
wire [7:0] _T_1224 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_1226 = _T_1224 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 252:116]
|
|
wire [7:0] fwdpipe4_hi = _T_1221 | _T_1226; // @[lsu_stbuf.scala 252:82]
|
|
wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58]
|
|
wire _T_1261 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[lsu_stbuf.scala 258:83]
|
|
wire _T_1263 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[lsu_stbuf.scala 258:83]
|
|
wire _T_1265 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[lsu_stbuf.scala 258:83]
|
|
wire _T_1267 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[lsu_stbuf.scala 258:83]
|
|
wire [2:0] _T_1269 = {_T_1267,_T_1265,_T_1263}; // @[Cat.scala 29:58]
|
|
wire _T_1272 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[lsu_stbuf.scala 259:83]
|
|
wire _T_1274 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[lsu_stbuf.scala 259:83]
|
|
wire _T_1276 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[lsu_stbuf.scala 259:83]
|
|
wire _T_1278 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[lsu_stbuf.scala 259:83]
|
|
wire [2:0] _T_1280 = {_T_1278,_T_1276,_T_1274}; // @[Cat.scala 29:58]
|
|
wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[lsu_stbuf.scala 262:30]
|
|
wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[lsu_stbuf.scala 263:30]
|
|
wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[lsu_stbuf.scala 264:30]
|
|
wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[lsu_stbuf.scala 265:30]
|
|
wire [15:0] _T_1294 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_1295 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58]
|
|
wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[lsu_stbuf.scala 268:30]
|
|
wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[lsu_stbuf.scala 269:30]
|
|
wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[lsu_stbuf.scala 270:30]
|
|
wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 271:30]
|
|
wire [15:0] _T_1309 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
|
|
wire [15:0] _T_1310 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
assign io_stbuf_reqvld_any = _T_696 & _T_698; // @[lsu_stbuf.scala 51:47 lsu_stbuf.scala 184:24]
|
|
assign io_stbuf_reqvld_flushed_any = _T_686[0] & _T_688[0]; // @[lsu_stbuf.scala 52:35 lsu_stbuf.scala 183:31]
|
|
assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_10; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 185:22]
|
|
assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_14; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 186:22]
|
|
assign io_lsu_stbuf_full_any = _T_749 ? _T_751 : _T_752; // @[lsu_stbuf.scala 55:43 lsu_stbuf.scala 205:26]
|
|
assign io_ldst_stbuf_reqvld_r = _T_22 & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 57:43 lsu_stbuf.scala 125:26]
|
|
assign io_stbuf_fwddata_hi_m = {_T_1310,_T_1309}; // @[lsu_stbuf.scala 58:43 lsu_stbuf.scala 272:25]
|
|
assign io_stbuf_fwddata_lo_m = {_T_1295,_T_1294}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 266:25]
|
|
assign io_stbuf_fwdbyteen_hi_m = {_T_1269,_T_1261}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 258:27]
|
|
assign io_stbuf_fwdbyteen_lo_m = {_T_1280,_T_1272}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 259:27]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
RdPtr = _RAND_0[1:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
WrPtr = _RAND_1[1:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
stbuf_addr_0 = _RAND_2[15:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_587 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_579 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_571 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_563 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_622 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_614 = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_606 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_598 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
stbuf_addr_1 = _RAND_11[15:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
stbuf_addr_2 = _RAND_12[15:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
stbuf_addr_3 = _RAND_13[15:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
stbuf_byteen_0 = _RAND_14[3:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
stbuf_byteen_1 = _RAND_15[3:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
stbuf_byteen_2 = _RAND_16[3:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
stbuf_byteen_3 = _RAND_17[3:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
stbuf_data_0 = _RAND_18[31:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
stbuf_data_1 = _RAND_19[31:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
stbuf_data_2 = _RAND_20[31:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
stbuf_data_3 = _RAND_21[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
RdPtr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_0 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_587 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_579 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_571 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_563 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_622 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_614 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_606 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_598 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_1 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_2 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_addr_3 = 16'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_byteen_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
stbuf_data_3 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
RdPtr <= 2'h0;
|
|
end else if (_T_211) begin
|
|
RdPtr <= RdPtrPlus1;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr <= 2'h0;
|
|
end else if (WrPtrEn) begin
|
|
if (_T_713) begin
|
|
WrPtr <= WrPtrPlus2;
|
|
end else begin
|
|
WrPtr <= WrPtrPlus1;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_0 <= 16'h0;
|
|
end else if (stbuf_wr_en[0]) begin
|
|
if (sel_lo[0]) begin
|
|
stbuf_addr_0 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_0 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_587 <= 1'h0;
|
|
end else begin
|
|
_T_587 <= _T_583 & _T_66;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_579 <= 1'h0;
|
|
end else begin
|
|
_T_579 <= _T_575 & _T_55;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_571 <= 1'h0;
|
|
end else begin
|
|
_T_571 <= _T_567 & _T_44;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_563 <= 1'h0;
|
|
end else begin
|
|
_T_563 <= _T_559 & _T_33;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_622 <= 1'h0;
|
|
end else begin
|
|
_T_622 <= _T_618 & _T_66;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_614 <= 1'h0;
|
|
end else begin
|
|
_T_614 <= _T_610 & _T_55;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_606 <= 1'h0;
|
|
end else begin
|
|
_T_606 <= _T_602 & _T_44;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_598 <= 1'h0;
|
|
end else begin
|
|
_T_598 <= _T_594 & _T_33;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_1 <= 16'h0;
|
|
end else if (stbuf_wr_en[1]) begin
|
|
if (sel_lo[1]) begin
|
|
stbuf_addr_1 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_1 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_2 <= 16'h0;
|
|
end else if (stbuf_wr_en[2]) begin
|
|
if (sel_lo[2]) begin
|
|
stbuf_addr_2 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_2 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_addr_3 <= 16'h0;
|
|
end else if (stbuf_wr_en[3]) begin
|
|
if (sel_lo[3]) begin
|
|
stbuf_addr_3 <= io_lsu_addr_r[15:0];
|
|
end else begin
|
|
stbuf_addr_3 <= io_end_addr_r[15:0];
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_0 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_0 <= _T_628 & _T_632;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_1 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_1 <= _T_637 & _T_641;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_2 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_2 <= _T_646 & _T_650;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_byteen_3 <= 4'h0;
|
|
end else begin
|
|
stbuf_byteen_3 <= _T_655 & _T_659;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_0 <= 32'h0;
|
|
end else if (stbuf_wr_en[0]) begin
|
|
stbuf_data_0 <= stbuf_datain_0;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_1 <= 32'h0;
|
|
end else if (stbuf_wr_en[1]) begin
|
|
stbuf_data_1 <= stbuf_datain_1;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_2 <= 32'h0;
|
|
end else if (stbuf_wr_en[2]) begin
|
|
stbuf_data_2 <= stbuf_datain_2;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
stbuf_data_3 <= 32'h0;
|
|
end else if (stbuf_wr_en[3]) begin
|
|
stbuf_data_3 <= stbuf_datain_3;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_ecc(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_c2_r_clk,
|
|
input io_clk_override,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input [31:0] io_stbuf_data_any,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
input [15:0] io_lsu_addr_m,
|
|
input [15:0] io_end_addr_m,
|
|
input [31:0] io_dccm_rdata_hi_m,
|
|
input [31:0] io_dccm_rdata_lo_m,
|
|
input [6:0] io_dccm_data_ecc_hi_m,
|
|
input [6:0] io_dccm_data_ecc_lo_m,
|
|
input io_ld_single_ecc_error_r,
|
|
input io_ld_single_ecc_error_r_ff,
|
|
input io_lsu_dccm_rden_m,
|
|
input io_addr_in_dccm_m,
|
|
input io_dma_dccm_wen,
|
|
input [31:0] io_dma_dccm_wdata_lo,
|
|
input [31:0] io_dma_dccm_wdata_hi,
|
|
output [31:0] io_sec_data_hi_r,
|
|
output [31:0] io_sec_data_lo_r,
|
|
output [31:0] io_sec_data_hi_m,
|
|
output [31:0] io_sec_data_lo_m,
|
|
output [31:0] io_sec_data_hi_r_ff,
|
|
output [31:0] io_sec_data_lo_r_ff,
|
|
output [6:0] io_dma_dccm_wdata_ecc_hi,
|
|
output [6:0] io_dma_dccm_wdata_ecc_lo,
|
|
output [6:0] io_stbuf_ecc_any,
|
|
output [6:0] io_sec_data_ecc_hi_r_ff,
|
|
output [6:0] io_sec_data_ecc_lo_r_ff,
|
|
output io_single_ecc_error_hi_r,
|
|
output io_single_ecc_error_lo_r,
|
|
output io_lsu_single_ecc_error_r,
|
|
output io_lsu_double_ecc_error_r,
|
|
output io_lsu_single_ecc_error_m,
|
|
output io_lsu_double_ecc_error_m
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 199:30]
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wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 199:44]
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wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 199:35]
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wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 199:76]
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wire _T_107 = ^_T_106; // @[lib.scala 199:83]
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wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 199:71]
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wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 199:103]
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wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 199:103]
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wire _T_124 = ^_T_123; // @[lib.scala 199:110]
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wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 199:98]
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wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 199:130]
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wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 199:130]
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wire _T_141 = ^_T_140; // @[lib.scala 199:137]
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wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 199:125]
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wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 199:157]
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wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 199:157]
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wire _T_161 = ^_T_160; // @[lib.scala 199:164]
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wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 199:152]
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wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 199:184]
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wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 199:184]
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wire _T_181 = ^_T_180; // @[lib.scala 199:191]
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wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 199:179]
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wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 199:211]
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wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 199:211]
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wire _T_201 = ^_T_200; // @[lib.scala 199:218]
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wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 199:206]
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wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
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wire _T_209 = _T_208 != 7'h0; // @[lib.scala 200:44]
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wire _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48]
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wire _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65]
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wire _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39]
|
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wire _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92]
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wire is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112]
|
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wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39]
|
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wire _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48]
|
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wire _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33]
|
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wire is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73]
|
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wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 200:32]
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wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 200:53]
|
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wire _T_215 = ~_T_208[6]; // @[lib.scala 201:55]
|
|
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 201:53]
|
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wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 205:41]
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wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 205:41]
|
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wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 205:41]
|
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wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 205:41]
|
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wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 205:41]
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wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 205:41]
|
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wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 205:41]
|
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wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 205:41]
|
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wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 205:41]
|
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wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 205:41]
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wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 205:41]
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wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 205:41]
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wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 205:41]
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wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 205:41]
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wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 205:41]
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wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 205:41]
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wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 205:41]
|
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wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 205:41]
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wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 205:41]
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wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 205:41]
|
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wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 205:41]
|
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wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 205:41]
|
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wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 205:41]
|
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wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 205:41]
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wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 205:41]
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wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 205:41]
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wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 205:41]
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wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 205:41]
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wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 205:41]
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wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 205:41]
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wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 205:41]
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wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 205:41]
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wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 205:41]
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wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 205:41]
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wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 205:41]
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wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 205:41]
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wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 205:41]
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wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 205:41]
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wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 205:41]
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wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
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wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
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wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 208:69]
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wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 208:69]
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wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 208:69]
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wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 208:69]
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wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 208:69]
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wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 208:76]
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wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 208:31]
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wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
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wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
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wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 199:30]
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wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 199:44]
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wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 199:35]
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wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 199:76]
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wire _T_485 = ^_T_484; // @[lib.scala 199:83]
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wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 199:71]
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wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 199:103]
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wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 199:103]
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wire _T_502 = ^_T_501; // @[lib.scala 199:110]
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wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 199:98]
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wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 199:130]
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wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 199:130]
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wire _T_519 = ^_T_518; // @[lib.scala 199:137]
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wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 199:125]
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wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 199:157]
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wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 199:157]
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wire _T_539 = ^_T_538; // @[lib.scala 199:164]
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wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 199:152]
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wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 199:184]
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wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 199:184]
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wire _T_559 = ^_T_558; // @[lib.scala 199:191]
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wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 199:179]
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wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 199:211]
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wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 199:211]
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wire _T_579 = ^_T_578; // @[lib.scala 199:218]
|
|
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 199:206]
|
|
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
|
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wire _T_587 = _T_586 != 7'h0; // @[lib.scala 200:44]
|
|
wire is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33]
|
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wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 200:32]
|
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wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 200:53]
|
|
wire _T_593 = ~_T_586[6]; // @[lib.scala 201:55]
|
|
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 201:53]
|
|
wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 205:41]
|
|
wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 205:41]
|
|
wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 205:41]
|
|
wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 205:41]
|
|
wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 205:41]
|
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wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 205:41]
|
|
wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 205:41]
|
|
wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 205:41]
|
|
wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 205:41]
|
|
wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 205:41]
|
|
wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 205:41]
|
|
wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 205:41]
|
|
wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 205:41]
|
|
wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 205:41]
|
|
wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 205:41]
|
|
wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 205:41]
|
|
wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 205:41]
|
|
wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 205:41]
|
|
wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 205:41]
|
|
wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 205:41]
|
|
wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 205:41]
|
|
wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 205:41]
|
|
wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 205:41]
|
|
wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 205:41]
|
|
wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 205:41]
|
|
wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 205:41]
|
|
wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 205:41]
|
|
wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 205:41]
|
|
wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 205:41]
|
|
wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 205:41]
|
|
wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 205:41]
|
|
wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 205:41]
|
|
wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 205:41]
|
|
wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 205:41]
|
|
wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 205:41]
|
|
wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 205:41]
|
|
wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 205:41]
|
|
wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 205:41]
|
|
wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 205:41]
|
|
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
|
|
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
|
|
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 208:69]
|
|
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 208:69]
|
|
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 208:69]
|
|
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 208:69]
|
|
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 208:69]
|
|
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 208:76]
|
|
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 208:31]
|
|
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_1159 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 148:87]
|
|
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1159; // @[lsu_ecc.scala 148:27]
|
|
wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 125:74]
|
|
wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 125:74]
|
|
wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 125:74]
|
|
wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 125:74]
|
|
wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 125:74]
|
|
wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 125:74]
|
|
wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 125:74]
|
|
wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 125:74]
|
|
wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 125:74]
|
|
wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 125:74]
|
|
wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 125:74]
|
|
wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 125:74]
|
|
wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 125:74]
|
|
wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 125:74]
|
|
wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 125:74]
|
|
wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 125:74]
|
|
wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 125:74]
|
|
wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 125:74]
|
|
wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 125:74]
|
|
wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 125:74]
|
|
wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 125:74]
|
|
wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 125:74]
|
|
wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 125:74]
|
|
wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 125:74]
|
|
wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 125:74]
|
|
wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 125:74]
|
|
wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 125:74]
|
|
wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 125:74]
|
|
wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 125:74]
|
|
wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 125:74]
|
|
wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 125:74]
|
|
wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 125:74]
|
|
wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 125:74]
|
|
wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 125:74]
|
|
wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 125:74]
|
|
wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 125:74]
|
|
wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 125:74]
|
|
wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 125:74]
|
|
wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 125:74]
|
|
wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 125:74]
|
|
wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 125:74]
|
|
wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 125:74]
|
|
wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 125:74]
|
|
wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 125:74]
|
|
wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 125:74]
|
|
wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 125:74]
|
|
wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 125:74]
|
|
wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 125:74]
|
|
wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 125:74]
|
|
wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 125:74]
|
|
wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 125:74]
|
|
wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 125:74]
|
|
wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 125:74]
|
|
wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 125:74]
|
|
wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 125:74]
|
|
wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 125:74]
|
|
wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 125:74]
|
|
wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 125:74]
|
|
wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 125:74]
|
|
wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 125:74]
|
|
wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 125:74]
|
|
wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 125:74]
|
|
wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 125:74]
|
|
wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 125:74]
|
|
wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 125:74]
|
|
wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 125:74]
|
|
wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 125:74]
|
|
wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 125:74]
|
|
wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 125:74]
|
|
wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 125:74]
|
|
wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 125:74]
|
|
wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 125:74]
|
|
wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 125:74]
|
|
wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 125:74]
|
|
wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 125:74]
|
|
wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 125:74]
|
|
wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 125:74]
|
|
wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 125:74]
|
|
wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 125:74]
|
|
wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 125:74]
|
|
wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 125:74]
|
|
wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 125:74]
|
|
wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 125:74]
|
|
wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 125:74]
|
|
wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58]
|
|
wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 133:13]
|
|
wire _T_936 = ^_T_934; // @[lib.scala 133:23]
|
|
wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 133:18]
|
|
wire [31:0] _T_1163 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : 32'h0; // @[lsu_ecc.scala 149:87]
|
|
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1163; // @[lsu_ecc.scala 149:27]
|
|
wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 125:74]
|
|
wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 125:74]
|
|
wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 125:74]
|
|
wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 125:74]
|
|
wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 125:74]
|
|
wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 125:74]
|
|
wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 125:74]
|
|
wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 125:74]
|
|
wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 125:74]
|
|
wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 125:74]
|
|
wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 125:74]
|
|
wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 125:74]
|
|
wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 125:74]
|
|
wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 125:74]
|
|
wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 125:74]
|
|
wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 125:74]
|
|
wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 125:74]
|
|
wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 125:74]
|
|
wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 125:74]
|
|
wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 125:74]
|
|
wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 125:74]
|
|
wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 125:74]
|
|
wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 125:74]
|
|
wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 125:74]
|
|
wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 125:74]
|
|
wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 125:74]
|
|
wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 125:74]
|
|
wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 125:74]
|
|
wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 125:74]
|
|
wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 125:74]
|
|
wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 125:74]
|
|
wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 125:74]
|
|
wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 125:74]
|
|
wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 125:74]
|
|
wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 125:74]
|
|
wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 125:74]
|
|
wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 125:74]
|
|
wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 125:74]
|
|
wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 125:74]
|
|
wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 125:74]
|
|
wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 125:74]
|
|
wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 125:74]
|
|
wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 125:74]
|
|
wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 125:74]
|
|
wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 125:74]
|
|
wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 125:74]
|
|
wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 125:74]
|
|
wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 125:74]
|
|
wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 125:74]
|
|
wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 125:74]
|
|
wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 125:74]
|
|
wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 125:74]
|
|
wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 125:74]
|
|
wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 125:74]
|
|
wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 125:74]
|
|
wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 125:74]
|
|
wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 125:74]
|
|
wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 125:74]
|
|
wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 125:74]
|
|
wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 125:74]
|
|
wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 125:74]
|
|
wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 125:74]
|
|
wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 125:74]
|
|
wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 125:74]
|
|
wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 125:74]
|
|
wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 125:74]
|
|
wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 125:74]
|
|
wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 125:74]
|
|
wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 125:74]
|
|
wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 125:74]
|
|
wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 125:74]
|
|
wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 125:74]
|
|
wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 125:74]
|
|
wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 125:74]
|
|
wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 125:74]
|
|
wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 125:74]
|
|
wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 125:74]
|
|
wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 125:74]
|
|
wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 125:74]
|
|
wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 125:74]
|
|
wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 125:74]
|
|
wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 125:74]
|
|
wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 125:74]
|
|
wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 125:74]
|
|
wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58]
|
|
wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 133:13]
|
|
wire _T_1118 = ^_T_1116; // @[lib.scala 133:23]
|
|
wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 133:18]
|
|
reg _T_1149; // @[lsu_ecc.scala 140:72]
|
|
reg _T_1150; // @[lsu_ecc.scala 141:72]
|
|
reg _T_1151; // @[lsu_ecc.scala 142:72]
|
|
reg _T_1152; // @[lsu_ecc.scala 143:72]
|
|
wire _T_1153 = io_lsu_single_ecc_error_m | io_clk_override; // @[lsu_ecc.scala 144:87]
|
|
reg [31:0] _T_1154; // @[Reg.scala 27:20]
|
|
reg [31:0] _T_1156; // @[Reg.scala 27:20]
|
|
wire _T_1165 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_ecc.scala 156:75]
|
|
reg [31:0] _T_1166; // @[Reg.scala 27:20]
|
|
reg [31:0] _T_1168; // @[Reg.scala 27:20]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34]
|
|
assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34]
|
|
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27]
|
|
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27]
|
|
assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23]
|
|
assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23]
|
|
assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28]
|
|
assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 154:28]
|
|
assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28]
|
|
assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28]
|
|
assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28]
|
|
assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62]
|
|
assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62]
|
|
assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62]
|
|
assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62]
|
|
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33]
|
|
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_1149 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_1150 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_1151 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_1152 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_1154 = _RAND_4[31:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_1156 = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_1166 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_1168 = _RAND_7[31:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_1149 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1150 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1151 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1152 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1154 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1156 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1166 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1168 = 32'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1149 <= 1'h0;
|
|
end else begin
|
|
_T_1149 <= io_lsu_single_ecc_error_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1150 <= 1'h0;
|
|
end else begin
|
|
_T_1150 <= io_lsu_double_ecc_error_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1151 <= 1'h0;
|
|
end else begin
|
|
_T_1151 <= _T_588 & _T_586[6];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1152 <= 1'h0;
|
|
end else begin
|
|
_T_1152 <= _T_210 & _T_208[6];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1154 <= 32'h0;
|
|
end else if (_T_1153) begin
|
|
_T_1154 <= io_sec_data_hi_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1156 <= 32'h0;
|
|
end else if (_T_1153) begin
|
|
_T_1156 <= io_sec_data_lo_m;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1166 <= 32'h0;
|
|
end else if (_T_1165) begin
|
|
_T_1166 <= io_sec_data_hi_r;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1168 <= 32'h0;
|
|
end else if (_T_1165) begin
|
|
_T_1168 <= io_sec_data_lo_r;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_trigger(
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_store,
|
|
input io_trigger_pkt_any_0_load,
|
|
input io_trigger_pkt_any_0_m,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_store,
|
|
input io_trigger_pkt_any_1_load,
|
|
input io_trigger_pkt_any_1_m,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_store,
|
|
input io_trigger_pkt_any_2_load,
|
|
input io_trigger_pkt_any_2_m,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_store,
|
|
input io_trigger_pkt_any_3_load,
|
|
input io_trigger_pkt_any_3_m,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_m_bits_store,
|
|
input io_lsu_pkt_m_bits_dma,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_store_data_m,
|
|
output [3:0] io_lsu_trigger_match_m
|
|
);
|
|
wire _T = io_trigger_pkt_any_0_m | io_trigger_pkt_any_1_m; // @[lsu_trigger.scala 16:73]
|
|
wire _T_1 = _T | io_trigger_pkt_any_2_m; // @[lsu_trigger.scala 16:73]
|
|
wire trigger_enable = _T_1 | io_trigger_pkt_any_3_m; // @[lsu_trigger.scala 16:73]
|
|
wire [15:0] _T_4 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [15:0] _T_6 = _T_4 & io_store_data_m[31:16]; // @[lsu_trigger.scala 17:66]
|
|
wire _T_7 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 17:124]
|
|
wire [7:0] _T_9 = _T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_11 = _T_9 & io_store_data_m[15:8]; // @[lsu_trigger.scala 17:151]
|
|
wire [31:0] store_data_trigger_m = {_T_6,_T_11,io_store_data_m[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_15 = trigger_enable ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] ldst_addr_trigger_m = io_lsu_addr_m & _T_15; // @[lsu_trigger.scala 18:43]
|
|
wire _T_17 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 19:53]
|
|
wire _T_18 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 19:143]
|
|
wire [31:0] _T_20 = _T_17 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_21 = _T_18 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_0 = _T_20 | _T_21; // @[Mux.scala 27:72]
|
|
wire _T_24 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 19:53]
|
|
wire _T_25 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 19:143]
|
|
wire [31:0] _T_27 = _T_24 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_28 = _T_25 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_1 = _T_27 | _T_28; // @[Mux.scala 27:72]
|
|
wire _T_31 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 19:53]
|
|
wire _T_32 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 19:143]
|
|
wire [31:0] _T_34 = _T_31 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_35 = _T_32 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_2 = _T_34 | _T_35; // @[Mux.scala 27:72]
|
|
wire _T_38 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 19:53]
|
|
wire _T_39 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 19:143]
|
|
wire [31:0] _T_41 = _T_38 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_42 = _T_39 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_match_data_3 = _T_41 | _T_42; // @[Mux.scala 27:72]
|
|
wire _T_44 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 20:70]
|
|
wire _T_45 = io_lsu_pkt_m_valid & _T_44; // @[lsu_trigger.scala 20:68]
|
|
wire _T_46 = _T_45 & trigger_enable; // @[lsu_trigger.scala 20:93]
|
|
wire _T_47 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
|
|
wire _T_48 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
|
|
wire _T_50 = _T_48 & _T_17; // @[lsu_trigger.scala 21:58]
|
|
wire _T_51 = _T_47 | _T_50; // @[lsu_trigger.scala 20:168]
|
|
wire _T_52 = _T_46 & _T_51; // @[lsu_trigger.scala 20:110]
|
|
wire _T_55 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 107:45]
|
|
wire _T_56 = ~_T_55; // @[lib.scala 107:39]
|
|
wire _T_57 = io_trigger_pkt_any_0_match_pkt & _T_56; // @[lib.scala 107:37]
|
|
wire _T_60 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 108:52]
|
|
wire _T_61 = _T_57 | _T_60; // @[lib.scala 108:41]
|
|
wire _T_63 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_64 = _T_63 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_67 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 110:80]
|
|
wire _T_68 = _T_64 | _T_67; // @[lib.scala 110:25]
|
|
wire _T_70 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_71 = _T_70 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_74 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 110:80]
|
|
wire _T_75 = _T_71 | _T_74; // @[lib.scala 110:25]
|
|
wire _T_77 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_78 = _T_77 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_81 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 110:80]
|
|
wire _T_82 = _T_78 | _T_81; // @[lib.scala 110:25]
|
|
wire _T_84 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_85 = _T_84 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_88 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 110:80]
|
|
wire _T_89 = _T_85 | _T_88; // @[lib.scala 110:25]
|
|
wire _T_91 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_92 = _T_91 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_95 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 110:80]
|
|
wire _T_96 = _T_92 | _T_95; // @[lib.scala 110:25]
|
|
wire _T_98 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_99 = _T_98 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_102 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 110:80]
|
|
wire _T_103 = _T_99 | _T_102; // @[lib.scala 110:25]
|
|
wire _T_105 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_106 = _T_105 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_109 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 110:80]
|
|
wire _T_110 = _T_106 | _T_109; // @[lib.scala 110:25]
|
|
wire _T_112 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_113 = _T_112 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_116 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 110:80]
|
|
wire _T_117 = _T_113 | _T_116; // @[lib.scala 110:25]
|
|
wire _T_119 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_120 = _T_119 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_123 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 110:80]
|
|
wire _T_124 = _T_120 | _T_123; // @[lib.scala 110:25]
|
|
wire _T_126 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_127 = _T_126 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_130 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 110:80]
|
|
wire _T_131 = _T_127 | _T_130; // @[lib.scala 110:25]
|
|
wire _T_133 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 110:38]
|
|
wire _T_134 = _T_133 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_137 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 110:80]
|
|
wire _T_138 = _T_134 | _T_137; // @[lib.scala 110:25]
|
|
wire _T_140 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_141 = _T_140 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_144 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 110:80]
|
|
wire _T_145 = _T_141 | _T_144; // @[lib.scala 110:25]
|
|
wire _T_147 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_148 = _T_147 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_151 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 110:80]
|
|
wire _T_152 = _T_148 | _T_151; // @[lib.scala 110:25]
|
|
wire _T_154 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_155 = _T_154 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_158 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 110:80]
|
|
wire _T_159 = _T_155 | _T_158; // @[lib.scala 110:25]
|
|
wire _T_161 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_162 = _T_161 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_165 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 110:80]
|
|
wire _T_166 = _T_162 | _T_165; // @[lib.scala 110:25]
|
|
wire _T_168 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_169 = _T_168 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_172 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 110:80]
|
|
wire _T_173 = _T_169 | _T_172; // @[lib.scala 110:25]
|
|
wire _T_175 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_176 = _T_175 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_179 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 110:80]
|
|
wire _T_180 = _T_176 | _T_179; // @[lib.scala 110:25]
|
|
wire _T_182 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_183 = _T_182 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_186 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 110:80]
|
|
wire _T_187 = _T_183 | _T_186; // @[lib.scala 110:25]
|
|
wire _T_189 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_190 = _T_189 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_193 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 110:80]
|
|
wire _T_194 = _T_190 | _T_193; // @[lib.scala 110:25]
|
|
wire _T_196 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_197 = _T_196 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_200 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 110:80]
|
|
wire _T_201 = _T_197 | _T_200; // @[lib.scala 110:25]
|
|
wire _T_203 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_204 = _T_203 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_207 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 110:80]
|
|
wire _T_208 = _T_204 | _T_207; // @[lib.scala 110:25]
|
|
wire _T_210 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_211 = _T_210 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_214 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 110:80]
|
|
wire _T_215 = _T_211 | _T_214; // @[lib.scala 110:25]
|
|
wire _T_217 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_218 = _T_217 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_221 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 110:80]
|
|
wire _T_222 = _T_218 | _T_221; // @[lib.scala 110:25]
|
|
wire _T_224 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_225 = _T_224 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_228 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 110:80]
|
|
wire _T_229 = _T_225 | _T_228; // @[lib.scala 110:25]
|
|
wire _T_231 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_232 = _T_231 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_235 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 110:80]
|
|
wire _T_236 = _T_232 | _T_235; // @[lib.scala 110:25]
|
|
wire _T_238 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_239 = _T_238 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_242 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 110:80]
|
|
wire _T_243 = _T_239 | _T_242; // @[lib.scala 110:25]
|
|
wire _T_245 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_246 = _T_245 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_249 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 110:80]
|
|
wire _T_250 = _T_246 | _T_249; // @[lib.scala 110:25]
|
|
wire _T_252 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_253 = _T_252 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_256 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 110:80]
|
|
wire _T_257 = _T_253 | _T_256; // @[lib.scala 110:25]
|
|
wire _T_259 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_260 = _T_259 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_263 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 110:80]
|
|
wire _T_264 = _T_260 | _T_263; // @[lib.scala 110:25]
|
|
wire _T_266 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_267 = _T_266 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_270 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 110:80]
|
|
wire _T_271 = _T_267 | _T_270; // @[lib.scala 110:25]
|
|
wire _T_273 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_274 = _T_273 & _T_57; // @[lib.scala 110:43]
|
|
wire _T_277 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 110:80]
|
|
wire _T_278 = _T_274 | _T_277; // @[lib.scala 110:25]
|
|
wire [7:0] _T_285 = {_T_110,_T_103,_T_96,_T_89,_T_82,_T_75,_T_68,_T_61}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_293 = {_T_166,_T_159,_T_152,_T_145,_T_138,_T_131,_T_124,_T_117,_T_285}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_300 = {_T_222,_T_215,_T_208,_T_201,_T_194,_T_187,_T_180,_T_173}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_309 = {_T_278,_T_271,_T_264,_T_257,_T_250,_T_243,_T_236,_T_229,_T_300,_T_293}; // @[lib.scala 111:14]
|
|
wire _T_310 = &_T_309; // @[lib.scala 111:25]
|
|
wire _T_311 = _T_52 & _T_310; // @[lsu_trigger.scala 21:92]
|
|
wire _T_315 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
|
|
wire _T_316 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
|
|
wire _T_318 = _T_316 & _T_24; // @[lsu_trigger.scala 21:58]
|
|
wire _T_319 = _T_315 | _T_318; // @[lsu_trigger.scala 20:168]
|
|
wire _T_320 = _T_46 & _T_319; // @[lsu_trigger.scala 20:110]
|
|
wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 107:45]
|
|
wire _T_324 = ~_T_323; // @[lib.scala 107:39]
|
|
wire _T_325 = io_trigger_pkt_any_1_match_pkt & _T_324; // @[lib.scala 107:37]
|
|
wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 108:52]
|
|
wire _T_329 = _T_325 | _T_328; // @[lib.scala 108:41]
|
|
wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_332 = _T_331 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 110:80]
|
|
wire _T_336 = _T_332 | _T_335; // @[lib.scala 110:25]
|
|
wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_339 = _T_338 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 110:80]
|
|
wire _T_343 = _T_339 | _T_342; // @[lib.scala 110:25]
|
|
wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_346 = _T_345 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 110:80]
|
|
wire _T_350 = _T_346 | _T_349; // @[lib.scala 110:25]
|
|
wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_353 = _T_352 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 110:80]
|
|
wire _T_357 = _T_353 | _T_356; // @[lib.scala 110:25]
|
|
wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_360 = _T_359 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 110:80]
|
|
wire _T_364 = _T_360 | _T_363; // @[lib.scala 110:25]
|
|
wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_367 = _T_366 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 110:80]
|
|
wire _T_371 = _T_367 | _T_370; // @[lib.scala 110:25]
|
|
wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_374 = _T_373 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 110:80]
|
|
wire _T_378 = _T_374 | _T_377; // @[lib.scala 110:25]
|
|
wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_381 = _T_380 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 110:80]
|
|
wire _T_385 = _T_381 | _T_384; // @[lib.scala 110:25]
|
|
wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_388 = _T_387 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 110:80]
|
|
wire _T_392 = _T_388 | _T_391; // @[lib.scala 110:25]
|
|
wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_395 = _T_394 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 110:80]
|
|
wire _T_399 = _T_395 | _T_398; // @[lib.scala 110:25]
|
|
wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 110:38]
|
|
wire _T_402 = _T_401 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 110:80]
|
|
wire _T_406 = _T_402 | _T_405; // @[lib.scala 110:25]
|
|
wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_409 = _T_408 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 110:80]
|
|
wire _T_413 = _T_409 | _T_412; // @[lib.scala 110:25]
|
|
wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_416 = _T_415 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 110:80]
|
|
wire _T_420 = _T_416 | _T_419; // @[lib.scala 110:25]
|
|
wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_423 = _T_422 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 110:80]
|
|
wire _T_427 = _T_423 | _T_426; // @[lib.scala 110:25]
|
|
wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_430 = _T_429 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 110:80]
|
|
wire _T_434 = _T_430 | _T_433; // @[lib.scala 110:25]
|
|
wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_437 = _T_436 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 110:80]
|
|
wire _T_441 = _T_437 | _T_440; // @[lib.scala 110:25]
|
|
wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_444 = _T_443 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 110:80]
|
|
wire _T_448 = _T_444 | _T_447; // @[lib.scala 110:25]
|
|
wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_451 = _T_450 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 110:80]
|
|
wire _T_455 = _T_451 | _T_454; // @[lib.scala 110:25]
|
|
wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_458 = _T_457 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 110:80]
|
|
wire _T_462 = _T_458 | _T_461; // @[lib.scala 110:25]
|
|
wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_465 = _T_464 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 110:80]
|
|
wire _T_469 = _T_465 | _T_468; // @[lib.scala 110:25]
|
|
wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_472 = _T_471 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 110:80]
|
|
wire _T_476 = _T_472 | _T_475; // @[lib.scala 110:25]
|
|
wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_479 = _T_478 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 110:80]
|
|
wire _T_483 = _T_479 | _T_482; // @[lib.scala 110:25]
|
|
wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_486 = _T_485 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 110:80]
|
|
wire _T_490 = _T_486 | _T_489; // @[lib.scala 110:25]
|
|
wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_493 = _T_492 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 110:80]
|
|
wire _T_497 = _T_493 | _T_496; // @[lib.scala 110:25]
|
|
wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_500 = _T_499 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 110:80]
|
|
wire _T_504 = _T_500 | _T_503; // @[lib.scala 110:25]
|
|
wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_507 = _T_506 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 110:80]
|
|
wire _T_511 = _T_507 | _T_510; // @[lib.scala 110:25]
|
|
wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_514 = _T_513 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 110:80]
|
|
wire _T_518 = _T_514 | _T_517; // @[lib.scala 110:25]
|
|
wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_521 = _T_520 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 110:80]
|
|
wire _T_525 = _T_521 | _T_524; // @[lib.scala 110:25]
|
|
wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_528 = _T_527 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 110:80]
|
|
wire _T_532 = _T_528 | _T_531; // @[lib.scala 110:25]
|
|
wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_535 = _T_534 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 110:80]
|
|
wire _T_539 = _T_535 | _T_538; // @[lib.scala 110:25]
|
|
wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_542 = _T_541 & _T_325; // @[lib.scala 110:43]
|
|
wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 110:80]
|
|
wire _T_546 = _T_542 | _T_545; // @[lib.scala 110:25]
|
|
wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[lib.scala 111:14]
|
|
wire _T_578 = &_T_577; // @[lib.scala 111:25]
|
|
wire _T_579 = _T_320 & _T_578; // @[lsu_trigger.scala 21:92]
|
|
wire _T_583 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
|
|
wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
|
|
wire _T_586 = _T_584 & _T_31; // @[lsu_trigger.scala 21:58]
|
|
wire _T_587 = _T_583 | _T_586; // @[lsu_trigger.scala 20:168]
|
|
wire _T_588 = _T_46 & _T_587; // @[lsu_trigger.scala 20:110]
|
|
wire _T_591 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 107:45]
|
|
wire _T_592 = ~_T_591; // @[lib.scala 107:39]
|
|
wire _T_593 = io_trigger_pkt_any_2_match_pkt & _T_592; // @[lib.scala 107:37]
|
|
wire _T_596 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 108:52]
|
|
wire _T_597 = _T_593 | _T_596; // @[lib.scala 108:41]
|
|
wire _T_599 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_600 = _T_599 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_603 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 110:80]
|
|
wire _T_604 = _T_600 | _T_603; // @[lib.scala 110:25]
|
|
wire _T_606 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_607 = _T_606 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_610 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 110:80]
|
|
wire _T_611 = _T_607 | _T_610; // @[lib.scala 110:25]
|
|
wire _T_613 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_614 = _T_613 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_617 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 110:80]
|
|
wire _T_618 = _T_614 | _T_617; // @[lib.scala 110:25]
|
|
wire _T_620 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_621 = _T_620 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_624 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 110:80]
|
|
wire _T_625 = _T_621 | _T_624; // @[lib.scala 110:25]
|
|
wire _T_627 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_628 = _T_627 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_631 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 110:80]
|
|
wire _T_632 = _T_628 | _T_631; // @[lib.scala 110:25]
|
|
wire _T_634 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_635 = _T_634 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_638 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 110:80]
|
|
wire _T_639 = _T_635 | _T_638; // @[lib.scala 110:25]
|
|
wire _T_641 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_642 = _T_641 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_645 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 110:80]
|
|
wire _T_646 = _T_642 | _T_645; // @[lib.scala 110:25]
|
|
wire _T_648 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_649 = _T_648 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_652 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 110:80]
|
|
wire _T_653 = _T_649 | _T_652; // @[lib.scala 110:25]
|
|
wire _T_655 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_656 = _T_655 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_659 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 110:80]
|
|
wire _T_660 = _T_656 | _T_659; // @[lib.scala 110:25]
|
|
wire _T_662 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_663 = _T_662 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_666 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 110:80]
|
|
wire _T_667 = _T_663 | _T_666; // @[lib.scala 110:25]
|
|
wire _T_669 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 110:38]
|
|
wire _T_670 = _T_669 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_673 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 110:80]
|
|
wire _T_674 = _T_670 | _T_673; // @[lib.scala 110:25]
|
|
wire _T_676 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_677 = _T_676 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_680 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 110:80]
|
|
wire _T_681 = _T_677 | _T_680; // @[lib.scala 110:25]
|
|
wire _T_683 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_684 = _T_683 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_687 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 110:80]
|
|
wire _T_688 = _T_684 | _T_687; // @[lib.scala 110:25]
|
|
wire _T_690 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_691 = _T_690 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_694 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 110:80]
|
|
wire _T_695 = _T_691 | _T_694; // @[lib.scala 110:25]
|
|
wire _T_697 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_698 = _T_697 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_701 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 110:80]
|
|
wire _T_702 = _T_698 | _T_701; // @[lib.scala 110:25]
|
|
wire _T_704 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_705 = _T_704 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_708 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 110:80]
|
|
wire _T_709 = _T_705 | _T_708; // @[lib.scala 110:25]
|
|
wire _T_711 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_712 = _T_711 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_715 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 110:80]
|
|
wire _T_716 = _T_712 | _T_715; // @[lib.scala 110:25]
|
|
wire _T_718 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_719 = _T_718 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_722 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 110:80]
|
|
wire _T_723 = _T_719 | _T_722; // @[lib.scala 110:25]
|
|
wire _T_725 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_726 = _T_725 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_729 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 110:80]
|
|
wire _T_730 = _T_726 | _T_729; // @[lib.scala 110:25]
|
|
wire _T_732 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_733 = _T_732 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_736 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 110:80]
|
|
wire _T_737 = _T_733 | _T_736; // @[lib.scala 110:25]
|
|
wire _T_739 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_740 = _T_739 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_743 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 110:80]
|
|
wire _T_744 = _T_740 | _T_743; // @[lib.scala 110:25]
|
|
wire _T_746 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_747 = _T_746 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_750 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 110:80]
|
|
wire _T_751 = _T_747 | _T_750; // @[lib.scala 110:25]
|
|
wire _T_753 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_754 = _T_753 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_757 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 110:80]
|
|
wire _T_758 = _T_754 | _T_757; // @[lib.scala 110:25]
|
|
wire _T_760 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_761 = _T_760 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_764 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 110:80]
|
|
wire _T_765 = _T_761 | _T_764; // @[lib.scala 110:25]
|
|
wire _T_767 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_768 = _T_767 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_771 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 110:80]
|
|
wire _T_772 = _T_768 | _T_771; // @[lib.scala 110:25]
|
|
wire _T_774 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_775 = _T_774 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_778 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 110:80]
|
|
wire _T_779 = _T_775 | _T_778; // @[lib.scala 110:25]
|
|
wire _T_781 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_782 = _T_781 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_785 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 110:80]
|
|
wire _T_786 = _T_782 | _T_785; // @[lib.scala 110:25]
|
|
wire _T_788 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_789 = _T_788 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_792 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 110:80]
|
|
wire _T_793 = _T_789 | _T_792; // @[lib.scala 110:25]
|
|
wire _T_795 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_796 = _T_795 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_799 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 110:80]
|
|
wire _T_800 = _T_796 | _T_799; // @[lib.scala 110:25]
|
|
wire _T_802 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_803 = _T_802 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_806 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 110:80]
|
|
wire _T_807 = _T_803 | _T_806; // @[lib.scala 110:25]
|
|
wire _T_809 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_810 = _T_809 & _T_593; // @[lib.scala 110:43]
|
|
wire _T_813 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 110:80]
|
|
wire _T_814 = _T_810 | _T_813; // @[lib.scala 110:25]
|
|
wire [7:0] _T_821 = {_T_646,_T_639,_T_632,_T_625,_T_618,_T_611,_T_604,_T_597}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_829 = {_T_702,_T_695,_T_688,_T_681,_T_674,_T_667,_T_660,_T_653,_T_821}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_836 = {_T_758,_T_751,_T_744,_T_737,_T_730,_T_723,_T_716,_T_709}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_845 = {_T_814,_T_807,_T_800,_T_793,_T_786,_T_779,_T_772,_T_765,_T_836,_T_829}; // @[lib.scala 111:14]
|
|
wire _T_846 = &_T_845; // @[lib.scala 111:25]
|
|
wire _T_847 = _T_588 & _T_846; // @[lsu_trigger.scala 21:92]
|
|
wire _T_851 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
|
|
wire _T_852 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
|
|
wire _T_854 = _T_852 & _T_38; // @[lsu_trigger.scala 21:58]
|
|
wire _T_855 = _T_851 | _T_854; // @[lsu_trigger.scala 20:168]
|
|
wire _T_856 = _T_46 & _T_855; // @[lsu_trigger.scala 20:110]
|
|
wire _T_859 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 107:45]
|
|
wire _T_860 = ~_T_859; // @[lib.scala 107:39]
|
|
wire _T_861 = io_trigger_pkt_any_3_match_pkt & _T_860; // @[lib.scala 107:37]
|
|
wire _T_864 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 108:52]
|
|
wire _T_865 = _T_861 | _T_864; // @[lib.scala 108:41]
|
|
wire _T_867 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 110:38]
|
|
wire _T_868 = _T_867 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_871 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 110:80]
|
|
wire _T_872 = _T_868 | _T_871; // @[lib.scala 110:25]
|
|
wire _T_874 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 110:38]
|
|
wire _T_875 = _T_874 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_878 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 110:80]
|
|
wire _T_879 = _T_875 | _T_878; // @[lib.scala 110:25]
|
|
wire _T_881 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 110:38]
|
|
wire _T_882 = _T_881 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_885 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 110:80]
|
|
wire _T_886 = _T_882 | _T_885; // @[lib.scala 110:25]
|
|
wire _T_888 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 110:38]
|
|
wire _T_889 = _T_888 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_892 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 110:80]
|
|
wire _T_893 = _T_889 | _T_892; // @[lib.scala 110:25]
|
|
wire _T_895 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 110:38]
|
|
wire _T_896 = _T_895 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_899 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 110:80]
|
|
wire _T_900 = _T_896 | _T_899; // @[lib.scala 110:25]
|
|
wire _T_902 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 110:38]
|
|
wire _T_903 = _T_902 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_906 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 110:80]
|
|
wire _T_907 = _T_903 | _T_906; // @[lib.scala 110:25]
|
|
wire _T_909 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 110:38]
|
|
wire _T_910 = _T_909 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_913 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 110:80]
|
|
wire _T_914 = _T_910 | _T_913; // @[lib.scala 110:25]
|
|
wire _T_916 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 110:38]
|
|
wire _T_917 = _T_916 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_920 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 110:80]
|
|
wire _T_921 = _T_917 | _T_920; // @[lib.scala 110:25]
|
|
wire _T_923 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 110:38]
|
|
wire _T_924 = _T_923 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_927 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 110:80]
|
|
wire _T_928 = _T_924 | _T_927; // @[lib.scala 110:25]
|
|
wire _T_930 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 110:38]
|
|
wire _T_931 = _T_930 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_934 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 110:80]
|
|
wire _T_935 = _T_931 | _T_934; // @[lib.scala 110:25]
|
|
wire _T_937 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 110:38]
|
|
wire _T_938 = _T_937 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_941 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 110:80]
|
|
wire _T_942 = _T_938 | _T_941; // @[lib.scala 110:25]
|
|
wire _T_944 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 110:38]
|
|
wire _T_945 = _T_944 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_948 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 110:80]
|
|
wire _T_949 = _T_945 | _T_948; // @[lib.scala 110:25]
|
|
wire _T_951 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 110:38]
|
|
wire _T_952 = _T_951 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_955 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 110:80]
|
|
wire _T_956 = _T_952 | _T_955; // @[lib.scala 110:25]
|
|
wire _T_958 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 110:38]
|
|
wire _T_959 = _T_958 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_962 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 110:80]
|
|
wire _T_963 = _T_959 | _T_962; // @[lib.scala 110:25]
|
|
wire _T_965 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 110:38]
|
|
wire _T_966 = _T_965 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_969 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 110:80]
|
|
wire _T_970 = _T_966 | _T_969; // @[lib.scala 110:25]
|
|
wire _T_972 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 110:38]
|
|
wire _T_973 = _T_972 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_976 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 110:80]
|
|
wire _T_977 = _T_973 | _T_976; // @[lib.scala 110:25]
|
|
wire _T_979 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 110:38]
|
|
wire _T_980 = _T_979 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_983 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 110:80]
|
|
wire _T_984 = _T_980 | _T_983; // @[lib.scala 110:25]
|
|
wire _T_986 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 110:38]
|
|
wire _T_987 = _T_986 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_990 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 110:80]
|
|
wire _T_991 = _T_987 | _T_990; // @[lib.scala 110:25]
|
|
wire _T_993 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 110:38]
|
|
wire _T_994 = _T_993 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_997 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 110:80]
|
|
wire _T_998 = _T_994 | _T_997; // @[lib.scala 110:25]
|
|
wire _T_1000 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 110:38]
|
|
wire _T_1001 = _T_1000 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1004 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 110:80]
|
|
wire _T_1005 = _T_1001 | _T_1004; // @[lib.scala 110:25]
|
|
wire _T_1007 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 110:38]
|
|
wire _T_1008 = _T_1007 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1011 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 110:80]
|
|
wire _T_1012 = _T_1008 | _T_1011; // @[lib.scala 110:25]
|
|
wire _T_1014 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 110:38]
|
|
wire _T_1015 = _T_1014 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1018 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 110:80]
|
|
wire _T_1019 = _T_1015 | _T_1018; // @[lib.scala 110:25]
|
|
wire _T_1021 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 110:38]
|
|
wire _T_1022 = _T_1021 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1025 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 110:80]
|
|
wire _T_1026 = _T_1022 | _T_1025; // @[lib.scala 110:25]
|
|
wire _T_1028 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 110:38]
|
|
wire _T_1029 = _T_1028 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1032 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 110:80]
|
|
wire _T_1033 = _T_1029 | _T_1032; // @[lib.scala 110:25]
|
|
wire _T_1035 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 110:38]
|
|
wire _T_1036 = _T_1035 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1039 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 110:80]
|
|
wire _T_1040 = _T_1036 | _T_1039; // @[lib.scala 110:25]
|
|
wire _T_1042 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 110:38]
|
|
wire _T_1043 = _T_1042 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1046 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 110:80]
|
|
wire _T_1047 = _T_1043 | _T_1046; // @[lib.scala 110:25]
|
|
wire _T_1049 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 110:38]
|
|
wire _T_1050 = _T_1049 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1053 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 110:80]
|
|
wire _T_1054 = _T_1050 | _T_1053; // @[lib.scala 110:25]
|
|
wire _T_1056 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 110:38]
|
|
wire _T_1057 = _T_1056 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1060 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 110:80]
|
|
wire _T_1061 = _T_1057 | _T_1060; // @[lib.scala 110:25]
|
|
wire _T_1063 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 110:38]
|
|
wire _T_1064 = _T_1063 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1067 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 110:80]
|
|
wire _T_1068 = _T_1064 | _T_1067; // @[lib.scala 110:25]
|
|
wire _T_1070 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 110:38]
|
|
wire _T_1071 = _T_1070 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1074 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 110:80]
|
|
wire _T_1075 = _T_1071 | _T_1074; // @[lib.scala 110:25]
|
|
wire _T_1077 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 110:38]
|
|
wire _T_1078 = _T_1077 & _T_861; // @[lib.scala 110:43]
|
|
wire _T_1081 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 110:80]
|
|
wire _T_1082 = _T_1078 | _T_1081; // @[lib.scala 110:25]
|
|
wire [7:0] _T_1089 = {_T_914,_T_907,_T_900,_T_893,_T_886,_T_879,_T_872,_T_865}; // @[lib.scala 111:14]
|
|
wire [15:0] _T_1097 = {_T_970,_T_963,_T_956,_T_949,_T_942,_T_935,_T_928,_T_921,_T_1089}; // @[lib.scala 111:14]
|
|
wire [7:0] _T_1104 = {_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_991,_T_984,_T_977}; // @[lib.scala 111:14]
|
|
wire [31:0] _T_1113 = {_T_1082,_T_1075,_T_1068,_T_1061,_T_1054,_T_1047,_T_1040,_T_1033,_T_1104,_T_1097}; // @[lib.scala 111:14]
|
|
wire _T_1114 = &_T_1113; // @[lib.scala 111:25]
|
|
wire _T_1115 = _T_856 & _T_1114; // @[lsu_trigger.scala 21:92]
|
|
wire [2:0] _T_1117 = {_T_1115,_T_847,_T_579}; // @[Cat.scala 29:58]
|
|
assign io_lsu_trigger_match_m = {_T_1117,_T_311}; // @[lsu_trigger.scala 20:25]
|
|
endmodule
|
|
module lsu_clkdomain(
|
|
input clock,
|
|
input io_clk_override,
|
|
input io_lsu_busreq_r,
|
|
input io_lsu_bus_buffer_pend_any,
|
|
input io_lsu_bus_buffer_empty_any,
|
|
input io_lsu_bus_clk_en,
|
|
output io_lsu_bus_obuf_c1_clken,
|
|
output io_lsu_busm_clken,
|
|
output io_lsu_c1_m_clk,
|
|
output io_lsu_c1_r_clk,
|
|
output io_lsu_c2_m_clk,
|
|
output io_lsu_c2_r_clk,
|
|
output io_lsu_store_c1_m_clk,
|
|
output io_lsu_store_c1_r_clk,
|
|
output io_lsu_stbuf_c1_clk,
|
|
output io_lsu_bus_ibuf_c1_clk,
|
|
output io_lsu_bus_buf_c1_clk,
|
|
output io_lsu_free_c2_clk
|
|
);
|
|
wire rvclkhdr_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_io_en; // @[lib.scala 349:22]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 349:22]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 349:22]
|
|
wire _T_8 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:62]
|
|
wire _T_9 = _T_8 | io_clk_override; // @[lsu_clkdomain.scala 74:80]
|
|
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32]
|
|
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61]
|
|
wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 349:22]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30]
|
|
assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21]
|
|
assign io_lsu_c1_m_clk = clock; // @[lsu_clkdomain.scala 87:26]
|
|
assign io_lsu_c1_r_clk = clock; // @[lsu_clkdomain.scala 88:26]
|
|
assign io_lsu_c2_m_clk = clock; // @[lsu_clkdomain.scala 89:26]
|
|
assign io_lsu_c2_r_clk = clock; // @[lsu_clkdomain.scala 90:26]
|
|
assign io_lsu_store_c1_m_clk = clock; // @[lsu_clkdomain.scala 91:26]
|
|
assign io_lsu_store_c1_r_clk = clock; // @[lsu_clkdomain.scala 92:26]
|
|
assign io_lsu_stbuf_c1_clk = clock; // @[lsu_clkdomain.scala 93:26]
|
|
assign io_lsu_bus_ibuf_c1_clk = clock; // @[lsu_clkdomain.scala 94:26]
|
|
assign io_lsu_bus_buf_c1_clk = clock; // @[lsu_clkdomain.scala 96:26]
|
|
assign io_lsu_free_c2_clk = clock; // @[lsu_clkdomain.scala 98:26]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 351:16]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 350:17]
|
|
assign rvclkhdr_1_io_en = io_lsu_busm_clken; // @[lib.scala 351:16]
|
|
endmodule
|
|
module lsu_bus_buffer(
|
|
input clock,
|
|
input reset,
|
|
output io_tlu_busbuff_lsu_pmu_bus_trxn,
|
|
output io_tlu_busbuff_lsu_pmu_bus_misaligned,
|
|
output io_tlu_busbuff_lsu_pmu_bus_error,
|
|
output io_tlu_busbuff_lsu_pmu_bus_busy,
|
|
input io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
|
|
input io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
|
|
input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
|
|
output io_tlu_busbuff_lsu_imprecise_error_load_any,
|
|
output io_tlu_busbuff_lsu_imprecise_error_store_any,
|
|
output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any,
|
|
output io_dctl_busbuff_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m,
|
|
output io_dctl_busbuff_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r,
|
|
output io_dctl_busbuff_lsu_nonblock_load_data_valid,
|
|
output io_dctl_busbuff_lsu_nonblock_load_data_error,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag,
|
|
input io_dec_tlu_force_halt,
|
|
input io_lsu_bus_obuf_c1_clken,
|
|
input io_lsu_busm_clken,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_bus_ibuf_c1_clk,
|
|
input io_lsu_bus_buf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_unsign,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [31:0] io_end_addr_r,
|
|
input [31:0] io_store_data_r,
|
|
input io_no_word_merge_r,
|
|
input io_no_dword_merge_r,
|
|
input io_lsu_busreq_m,
|
|
input io_ld_full_hit_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
input io_lsu_commit_r,
|
|
input io_is_sideeffects_r,
|
|
input io_ldst_dual_d,
|
|
input io_ldst_dual_m,
|
|
input io_ldst_dual_r,
|
|
input [7:0] io_ldst_byteen_ext_m,
|
|
input io_lsu_axi_aw_ready,
|
|
output io_lsu_axi_aw_valid,
|
|
output [2:0] io_lsu_axi_aw_bits_id,
|
|
output [31:0] io_lsu_axi_aw_bits_addr,
|
|
output [3:0] io_lsu_axi_aw_bits_region,
|
|
output [2:0] io_lsu_axi_aw_bits_size,
|
|
output [3:0] io_lsu_axi_aw_bits_cache,
|
|
input io_lsu_axi_w_ready,
|
|
output io_lsu_axi_w_valid,
|
|
output [63:0] io_lsu_axi_w_bits_data,
|
|
output [7:0] io_lsu_axi_w_bits_strb,
|
|
output io_lsu_axi_b_ready,
|
|
input io_lsu_axi_b_valid,
|
|
input [1:0] io_lsu_axi_b_bits_resp,
|
|
input [2:0] io_lsu_axi_b_bits_id,
|
|
input io_lsu_axi_ar_ready,
|
|
output io_lsu_axi_ar_valid,
|
|
output [2:0] io_lsu_axi_ar_bits_id,
|
|
output [31:0] io_lsu_axi_ar_bits_addr,
|
|
output [3:0] io_lsu_axi_ar_bits_region,
|
|
output [2:0] io_lsu_axi_ar_bits_size,
|
|
output [3:0] io_lsu_axi_ar_bits_cache,
|
|
output io_lsu_axi_r_ready,
|
|
input io_lsu_axi_r_valid,
|
|
input [2:0] io_lsu_axi_r_bits_id,
|
|
input [63:0] io_lsu_axi_r_bits_data,
|
|
input [1:0] io_lsu_axi_r_bits_resp,
|
|
input io_lsu_bus_clk_en,
|
|
input io_lsu_bus_clk_en_q,
|
|
output io_lsu_busreq_r,
|
|
output io_lsu_bus_buffer_pend_any,
|
|
output io_lsu_bus_buffer_full_any,
|
|
output io_lsu_bus_buffer_empty_any,
|
|
output [3:0] io_ld_byte_hit_buf_lo,
|
|
output [3:0] io_ld_byte_hit_buf_hi,
|
|
output [31:0] io_ld_fwddata_buf_lo,
|
|
output [31:0] io_ld_fwddata_buf_hi,
|
|
output [31:0] io_lsu_nonblock_load_data
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [63:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 77:46]
|
|
wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 78:46]
|
|
reg [31:0] buf_addr_0; // @[Reg.scala 27:20]
|
|
wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 80:74]
|
|
reg _T_4355; // @[Reg.scala 27:20]
|
|
reg _T_4352; // @[Reg.scala 27:20]
|
|
reg _T_4349; // @[Reg.scala 27:20]
|
|
reg _T_4346; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58]
|
|
wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 80:98]
|
|
reg [2:0] buf_state_0; // @[Reg.scala 27:20]
|
|
wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 80:129]
|
|
wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 80:113]
|
|
wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141]
|
|
reg [31:0] buf_addr_1; // @[Reg.scala 27:20]
|
|
wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 80:74]
|
|
wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 80:98]
|
|
reg [2:0] buf_state_1; // @[Reg.scala 27:20]
|
|
wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 80:129]
|
|
wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 80:113]
|
|
wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141]
|
|
reg [31:0] buf_addr_2; // @[Reg.scala 27:20]
|
|
wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 80:74]
|
|
wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 80:98]
|
|
reg [2:0] buf_state_2; // @[Reg.scala 27:20]
|
|
wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 80:129]
|
|
wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 80:113]
|
|
wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141]
|
|
reg [31:0] buf_addr_3; // @[Reg.scala 27:20]
|
|
wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 80:74]
|
|
wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 80:98]
|
|
reg [2:0] buf_state_3; // @[Reg.scala 27:20]
|
|
wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 80:129]
|
|
wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 80:113]
|
|
wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 80:141]
|
|
wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 81:74]
|
|
wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 81:98]
|
|
wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 81:113]
|
|
wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141]
|
|
wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 81:74]
|
|
wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 81:98]
|
|
wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 81:113]
|
|
wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141]
|
|
wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 81:74]
|
|
wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 81:98]
|
|
wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 81:113]
|
|
wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141]
|
|
wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 81:74]
|
|
wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 81:98]
|
|
wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 81:113]
|
|
wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 81:141]
|
|
reg [3:0] buf_byteen_3; // @[Reg.scala 27:20]
|
|
wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114]
|
|
reg [3:0] buf_byteen_2; // @[Reg.scala 27:20]
|
|
wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114]
|
|
reg [3:0] buf_byteen_1; // @[Reg.scala 27:20]
|
|
wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114]
|
|
reg [3:0] buf_byteen_0; // @[Reg.scala 27:20]
|
|
wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58]
|
|
reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 515:60]
|
|
wire _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 419:93]
|
|
wire _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30]
|
|
reg [1:0] _T_1781; // @[Reg.scala 27:20]
|
|
wire [2:0] obuf_tag0 = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 358:13]
|
|
wire _T_4138 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 462:48]
|
|
reg obuf_merge; // @[Reg.scala 27:20]
|
|
reg [1:0] obuf_tag1; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_376 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 462:104]
|
|
wire _T_4139 = _GEN_376 == 3'h3; // @[lsu_bus_buffer.scala 462:104]
|
|
wire _T_4140 = obuf_merge & _T_4139; // @[lsu_bus_buffer.scala 462:91]
|
|
wire _T_4141 = _T_4138 | _T_4140; // @[lsu_bus_buffer.scala 462:77]
|
|
reg obuf_valid; // @[lsu_bus_buffer.scala 351:54]
|
|
wire _T_4142 = _T_4141 & obuf_valid; // @[lsu_bus_buffer.scala 462:135]
|
|
reg obuf_wr_enQ; // @[Reg.scala 27:20]
|
|
wire _T_4143 = _T_4142 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 462:148]
|
|
wire _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30]
|
|
wire _GEN_290 = _T_4131 & _T_4143; // @[Conditional.scala 39:67]
|
|
wire _GEN_303 = _T_4127 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_303; // @[Conditional.scala 40:58]
|
|
wire _T_2591 = _T_2590 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 419:103]
|
|
wire _T_2592 = ~_T_2591; // @[lsu_bus_buffer.scala 419:78]
|
|
wire _T_2593 = buf_ageQ_3[3] & _T_2592; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 419:132]
|
|
wire _T_2595 = _T_2593 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 419:93]
|
|
wire _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_3947 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 462:48]
|
|
wire _T_3948 = _GEN_376 == 3'h2; // @[lsu_bus_buffer.scala 462:104]
|
|
wire _T_3949 = obuf_merge & _T_3948; // @[lsu_bus_buffer.scala 462:91]
|
|
wire _T_3950 = _T_3947 | _T_3949; // @[lsu_bus_buffer.scala 462:77]
|
|
wire _T_3951 = _T_3950 & obuf_valid; // @[lsu_bus_buffer.scala 462:135]
|
|
wire _T_3952 = _T_3951 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 462:148]
|
|
wire _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30]
|
|
wire _GEN_214 = _T_3940 & _T_3952; // @[Conditional.scala 39:67]
|
|
wire _GEN_227 = _T_3936 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_227; // @[Conditional.scala 40:58]
|
|
wire _T_2584 = _T_2583 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 419:103]
|
|
wire _T_2585 = ~_T_2584; // @[lsu_bus_buffer.scala 419:78]
|
|
wire _T_2586 = buf_ageQ_3[2] & _T_2585; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2588 = _T_2586 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 419:93]
|
|
wire _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3756 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 462:48]
|
|
wire _T_3757 = _GEN_376 == 3'h1; // @[lsu_bus_buffer.scala 462:104]
|
|
wire _T_3758 = obuf_merge & _T_3757; // @[lsu_bus_buffer.scala 462:91]
|
|
wire _T_3759 = _T_3756 | _T_3758; // @[lsu_bus_buffer.scala 462:77]
|
|
wire _T_3760 = _T_3759 & obuf_valid; // @[lsu_bus_buffer.scala 462:135]
|
|
wire _T_3761 = _T_3760 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 462:148]
|
|
wire _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30]
|
|
wire _GEN_138 = _T_3749 & _T_3761; // @[Conditional.scala 39:67]
|
|
wire _GEN_151 = _T_3745 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_151; // @[Conditional.scala 40:58]
|
|
wire _T_2577 = _T_2576 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 419:103]
|
|
wire _T_2578 = ~_T_2577; // @[lsu_bus_buffer.scala 419:78]
|
|
wire _T_2579 = buf_ageQ_3[1] & _T_2578; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2581 = _T_2579 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 419:93]
|
|
wire _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3565 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 462:48]
|
|
wire _T_3566 = _GEN_376 == 3'h0; // @[lsu_bus_buffer.scala 462:104]
|
|
wire _T_3567 = obuf_merge & _T_3566; // @[lsu_bus_buffer.scala 462:91]
|
|
wire _T_3568 = _T_3565 | _T_3567; // @[lsu_bus_buffer.scala 462:77]
|
|
wire _T_3569 = _T_3568 & obuf_valid; // @[lsu_bus_buffer.scala 462:135]
|
|
wire _T_3570 = _T_3569 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 462:148]
|
|
wire _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30]
|
|
wire _GEN_62 = _T_3558 & _T_3570; // @[Conditional.scala 39:67]
|
|
wire _GEN_75 = _T_3554 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
|
|
wire buf_cmd_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_75; // @[Conditional.scala 40:58]
|
|
wire _T_2570 = _T_2569 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 419:103]
|
|
wire _T_2571 = ~_T_2570; // @[lsu_bus_buffer.scala 419:78]
|
|
wire _T_2572 = buf_ageQ_3[0] & _T_2571; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2574 = _T_2572 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58]
|
|
wire _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 420:104]
|
|
wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 150:97]
|
|
reg [31:0] ibuf_addr; // @[Reg.scala 27:20]
|
|
wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 156:51]
|
|
reg ibuf_write; // @[Reg.scala 27:20]
|
|
wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 156:73]
|
|
reg ibuf_valid; // @[lsu_bus_buffer.scala 246:54]
|
|
wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 156:86]
|
|
wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 156:99]
|
|
wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
reg [3:0] ibuf_byteen; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 161:55]
|
|
wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 161:69]
|
|
wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 150:150]
|
|
wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 150:148]
|
|
reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 515:60]
|
|
wire _T_2562 = buf_ageQ_2[3] & _T_2592; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2564 = _T_2562 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2555 = buf_ageQ_2[2] & _T_2585; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2557 = _T_2555 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2548 = buf_ageQ_2[1] & _T_2578; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2550 = _T_2548 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2541 = buf_ageQ_2[0] & _T_2571; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2543 = _T_2541 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58]
|
|
wire _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 420:104]
|
|
wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 150:148]
|
|
reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 515:60]
|
|
wire _T_2531 = buf_ageQ_1[3] & _T_2592; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2533 = _T_2531 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2524 = buf_ageQ_1[2] & _T_2585; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2526 = _T_2524 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2517 = buf_ageQ_1[1] & _T_2578; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2519 = _T_2517 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2510 = buf_ageQ_1[0] & _T_2571; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2512 = _T_2510 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58]
|
|
wire _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 420:104]
|
|
wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 150:148]
|
|
reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 515:60]
|
|
wire _T_2500 = buf_ageQ_0[3] & _T_2592; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2502 = _T_2500 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2493 = buf_ageQ_0[2] & _T_2585; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2495 = _T_2493 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2486 = buf_ageQ_0[1] & _T_2578; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2488 = _T_2486 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire _T_2479 = buf_ageQ_0[0] & _T_2571; // @[lsu_bus_buffer.scala 419:76]
|
|
wire _T_2481 = _T_2479 & _T_2594; // @[lsu_bus_buffer.scala 419:130]
|
|
wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58]
|
|
wire _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 420:104]
|
|
wire _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 420:89]
|
|
wire _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 420:104]
|
|
wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58]
|
|
wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 142:73]
|
|
wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 142:77]
|
|
wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 150:150]
|
|
wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58]
|
|
wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 142:73]
|
|
wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 142:77]
|
|
wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 150:150]
|
|
wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58]
|
|
wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 142:73]
|
|
wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 142:77]
|
|
wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 145:95]
|
|
wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 145:114]
|
|
wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 150:150]
|
|
wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 150:122]
|
|
wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 150:144]
|
|
wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 150:99]
|
|
wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 150:97]
|
|
wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 150:148]
|
|
wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58]
|
|
wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 142:73]
|
|
wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 142:77]
|
|
wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58]
|
|
wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 157:51]
|
|
wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 157:73]
|
|
wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 157:86]
|
|
wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 157:99]
|
|
wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 162:55]
|
|
wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 162:69]
|
|
wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 151:150]
|
|
wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58]
|
|
wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 143:73]
|
|
wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 143:77]
|
|
wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 151:150]
|
|
wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58]
|
|
wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 143:73]
|
|
wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 143:77]
|
|
wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 151:150]
|
|
wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58]
|
|
wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 143:73]
|
|
wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 143:77]
|
|
wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 146:95]
|
|
wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 146:114]
|
|
wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 151:150]
|
|
wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 151:122]
|
|
wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 151:144]
|
|
wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 151:99]
|
|
wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 151:97]
|
|
wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 151:148]
|
|
wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58]
|
|
wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 143:73]
|
|
wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 143:77]
|
|
wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_0; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 170:65]
|
|
wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_1; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 170:65]
|
|
wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_2; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 170:65]
|
|
wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [31:0] buf_data_3; // @[Reg.scala 27:20]
|
|
wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 170:65]
|
|
wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 170:97]
|
|
wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 170:97]
|
|
wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 170:97]
|
|
wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 171:65]
|
|
wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 171:65]
|
|
wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 171:65]
|
|
wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 171:65]
|
|
wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 171:97]
|
|
wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 171:97]
|
|
wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 171:97]
|
|
wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 172:65]
|
|
wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 172:65]
|
|
wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 172:65]
|
|
wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 172:65]
|
|
wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 172:97]
|
|
wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 172:97]
|
|
wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 172:97]
|
|
wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 173:65]
|
|
wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 173:65]
|
|
wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 173:65]
|
|
wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 173:65]
|
|
wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 173:97]
|
|
wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 173:97]
|
|
wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 173:97]
|
|
wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58]
|
|
reg [31:0] ibuf_data; // @[Reg.scala 27:20]
|
|
wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 174:32]
|
|
wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 177:65]
|
|
wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 177:65]
|
|
wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 177:65]
|
|
wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 177:65]
|
|
wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 177:97]
|
|
wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 177:97]
|
|
wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 177:97]
|
|
wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 178:65]
|
|
wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 178:65]
|
|
wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 178:65]
|
|
wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 178:65]
|
|
wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 178:97]
|
|
wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 178:97]
|
|
wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 178:97]
|
|
wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 179:65]
|
|
wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 179:65]
|
|
wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 179:65]
|
|
wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 179:65]
|
|
wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 179:97]
|
|
wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 179:97]
|
|
wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 179:97]
|
|
wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 180:65]
|
|
wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 180:65]
|
|
wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 180:65]
|
|
wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 180:65]
|
|
wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 180:97]
|
|
wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 180:97]
|
|
wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 180:97]
|
|
wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 181:32]
|
|
wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72]
|
|
wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 188:55]
|
|
wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 189:24]
|
|
wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58]
|
|
wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 190:24]
|
|
wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58]
|
|
wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 191:24]
|
|
wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58]
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wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72]
|
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wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58]
|
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wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58]
|
|
wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58]
|
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wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72]
|
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wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72]
|
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wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72]
|
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wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72]
|
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wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72]
|
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wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58]
|
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wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72]
|
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wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72]
|
|
wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72]
|
|
wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 209:40]
|
|
wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 211:31]
|
|
wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72]
|
|
wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72]
|
|
wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72]
|
|
wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72]
|
|
wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 213:60]
|
|
wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 213:34]
|
|
wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 213:84]
|
|
wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 213:82]
|
|
wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 214:36]
|
|
wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 214:56]
|
|
wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 214:54]
|
|
wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 216:36]
|
|
reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 259:55]
|
|
wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 222:62]
|
|
wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 222:48]
|
|
wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 241:54]
|
|
wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 241:80]
|
|
wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 241:93]
|
|
wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 241:129]
|
|
wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 241:106]
|
|
wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 241:152]
|
|
wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 241:150]
|
|
wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 241:175]
|
|
wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 241:173]
|
|
wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 242:20]
|
|
wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 222:98]
|
|
wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 222:82]
|
|
wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 222:80]
|
|
wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 223:5]
|
|
wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 217:44]
|
|
wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 217:42]
|
|
wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 217:61]
|
|
wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 217:120]
|
|
wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 217:100]
|
|
wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 217:74]
|
|
wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 223:16]
|
|
reg ibuf_sideeffect; // @[Reg.scala 27:20]
|
|
wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 223:35]
|
|
wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 223:55]
|
|
wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 223:53]
|
|
wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 223:67]
|
|
wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 222:32]
|
|
wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 216:34]
|
|
wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 216:49]
|
|
reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 629:49]
|
|
reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 628:49]
|
|
reg [1:0] ibuf_tag; // @[Reg.scala 27:20]
|
|
wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58]
|
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wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 232:77]
|
|
wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 237:8]
|
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wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 238:8]
|
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wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 236:46]
|
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wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 237:8]
|
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wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 238:8]
|
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wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 236:46]
|
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wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 237:8]
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wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 238:8]
|
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wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 236:46]
|
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wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 237:8]
|
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wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 238:8]
|
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wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 236:46]
|
|
wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58]
|
|
wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 239:60]
|
|
wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 239:95]
|
|
wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 243:65]
|
|
wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 243:63]
|
|
wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 243:96]
|
|
wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 243:48]
|
|
wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 243:96]
|
|
wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 243:48]
|
|
wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 243:96]
|
|
wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 243:48]
|
|
wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 243:96]
|
|
wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 243:48]
|
|
wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 244:45]
|
|
wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 244:45]
|
|
wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 244:45]
|
|
wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 244:45]
|
|
wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58]
|
|
wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 246:58]
|
|
wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 246:93]
|
|
reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20]
|
|
reg ibuf_dual; // @[Reg.scala 27:20]
|
|
reg ibuf_samedw; // @[Reg.scala 27:20]
|
|
reg ibuf_nomerge; // @[Reg.scala 27:20]
|
|
reg ibuf_unsign; // @[Reg.scala 27:20]
|
|
reg [1:0] ibuf_sz; // @[Reg.scala 27:20]
|
|
wire _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 535:64]
|
|
wire _T_4442 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 535:91]
|
|
wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 535:89]
|
|
wire _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 535:64]
|
|
wire _T_4437 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 535:91]
|
|
wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 535:89]
|
|
wire [1:0] _T_4444 = _T_4443 + _T_4438; // @[lsu_bus_buffer.scala 535:142]
|
|
wire _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 535:64]
|
|
wire _T_4432 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 535:91]
|
|
wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 535:89]
|
|
wire [1:0] _GEN_380 = {{1'd0}, _T_4433}; // @[lsu_bus_buffer.scala 535:142]
|
|
wire [2:0] _T_4445 = _T_4444 + _GEN_380; // @[lsu_bus_buffer.scala 535:142]
|
|
wire _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 535:64]
|
|
wire _T_4427 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 535:91]
|
|
wire _T_4428 = _T_4426 & _T_4427; // @[lsu_bus_buffer.scala 535:89]
|
|
wire [2:0] _GEN_381 = {{2'd0}, _T_4428}; // @[lsu_bus_buffer.scala 535:142]
|
|
wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_381; // @[lsu_bus_buffer.scala 535:142]
|
|
wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 269:43]
|
|
wire _T_4458 = _T_2590 & _T_4442; // @[lsu_bus_buffer.scala 536:73]
|
|
wire _T_4455 = _T_2583 & _T_4437; // @[lsu_bus_buffer.scala 536:73]
|
|
wire [1:0] _T_4459 = _T_4458 + _T_4455; // @[lsu_bus_buffer.scala 536:126]
|
|
wire _T_4452 = _T_2576 & _T_4432; // @[lsu_bus_buffer.scala 536:73]
|
|
wire [1:0] _GEN_382 = {{1'd0}, _T_4452}; // @[lsu_bus_buffer.scala 536:126]
|
|
wire [2:0] _T_4460 = _T_4459 + _GEN_382; // @[lsu_bus_buffer.scala 536:126]
|
|
wire _T_4449 = _T_2569 & _T_4427; // @[lsu_bus_buffer.scala 536:73]
|
|
wire [2:0] _GEN_383 = {{2'd0}, _T_4449}; // @[lsu_bus_buffer.scala 536:126]
|
|
wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_383; // @[lsu_bus_buffer.scala 536:126]
|
|
wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 269:72]
|
|
wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 269:51]
|
|
reg [2:0] obuf_wr_timer; // @[Reg.scala 27:20]
|
|
wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 269:97]
|
|
wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 269:80]
|
|
wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 269:114]
|
|
wire _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 385:58]
|
|
wire _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 385:45]
|
|
wire _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 385:63]
|
|
wire _T_1923 = _T_1921 & _T_4442; // @[lsu_bus_buffer.scala 385:88]
|
|
wire _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 385:58]
|
|
wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 385:45]
|
|
wire _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 385:63]
|
|
wire _T_1917 = _T_1915 & _T_4437; // @[lsu_bus_buffer.scala 385:88]
|
|
wire _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 385:58]
|
|
wire _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 385:45]
|
|
wire _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 385:63]
|
|
wire _T_1911 = _T_1909 & _T_4432; // @[lsu_bus_buffer.scala 385:88]
|
|
wire _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 385:58]
|
|
wire _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 385:45]
|
|
wire _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 385:63]
|
|
wire _T_1905 = _T_1903 & _T_4427; // @[lsu_bus_buffer.scala 385:88]
|
|
wire [3:0] CmdPtr0Dec = {_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1993 = {4'h0,_T_1923,_T_1917,_T_1911,_T_1905}; // @[Cat.scala 29:58]
|
|
wire _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 393:42]
|
|
wire _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 393:48]
|
|
wire _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 393:54]
|
|
wire _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 393:67]
|
|
wire _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 393:73]
|
|
wire _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 393:79]
|
|
wire _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 393:92]
|
|
wire _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 393:98]
|
|
wire _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 393:104]
|
|
wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58]
|
|
wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 398:11]
|
|
wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 270:114]
|
|
wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 270:114]
|
|
wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 270:114]
|
|
wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 270:114]
|
|
reg buf_nomerge_0; // @[Reg.scala 27:20]
|
|
wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_1; // @[Reg.scala 27:20]
|
|
wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_2; // @[Reg.scala 27:20]
|
|
wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72]
|
|
reg buf_nomerge_3; // @[Reg.scala 27:20]
|
|
wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72]
|
|
wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72]
|
|
wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72]
|
|
wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72]
|
|
wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 270:31]
|
|
wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 270:29]
|
|
reg _T_4325; // @[Reg.scala 27:20]
|
|
reg _T_4322; // @[Reg.scala 27:20]
|
|
reg _T_4319; // @[Reg.scala 27:20]
|
|
reg _T_4316; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58]
|
|
wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72]
|
|
wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72]
|
|
wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72]
|
|
wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72]
|
|
wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72]
|
|
wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72]
|
|
wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72]
|
|
wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 271:5]
|
|
wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 270:140]
|
|
wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 273:58]
|
|
wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 273:72]
|
|
wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72]
|
|
wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72]
|
|
wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 273:123]
|
|
wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 273:101]
|
|
wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 271:119]
|
|
wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 271:117]
|
|
wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 272:75]
|
|
wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 272:95]
|
|
wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 272:79]
|
|
wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 272:123]
|
|
wire _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 537:63]
|
|
wire _T_4481 = _T_4477 | _T_4458; // @[lsu_bus_buffer.scala 537:74]
|
|
wire _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 537:63]
|
|
wire _T_4476 = _T_4472 | _T_4455; // @[lsu_bus_buffer.scala 537:74]
|
|
wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 537:154]
|
|
wire _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 537:63]
|
|
wire _T_4471 = _T_4467 | _T_4452; // @[lsu_bus_buffer.scala 537:74]
|
|
wire [1:0] _GEN_384 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 537:154]
|
|
wire [2:0] _T_4483 = _T_4482 + _GEN_384; // @[lsu_bus_buffer.scala 537:154]
|
|
wire _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 537:63]
|
|
wire _T_4466 = _T_4462 | _T_4449; // @[lsu_bus_buffer.scala 537:74]
|
|
wire [2:0] _GEN_385 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 537:154]
|
|
wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_385; // @[lsu_bus_buffer.scala 537:154]
|
|
wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 275:53]
|
|
wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 275:31]
|
|
wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 275:64]
|
|
wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 275:89]
|
|
wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 275:61]
|
|
wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 291:32]
|
|
wire _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 565:62]
|
|
wire _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 565:73]
|
|
wire _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 565:93]
|
|
wire _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 565:62]
|
|
wire _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 565:73]
|
|
wire _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 565:93]
|
|
wire _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 565:153]
|
|
wire _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 565:62]
|
|
wire _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 565:73]
|
|
wire _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 565:93]
|
|
wire _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 565:153]
|
|
wire _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 565:62]
|
|
wire _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 565:73]
|
|
wire _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 565:93]
|
|
wire _T_4769 = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 565:153]
|
|
reg obuf_sideeffect; // @[Reg.scala 27:20]
|
|
wire _T_4770 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 565:171]
|
|
wire _T_4771 = _T_4770 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 565:189]
|
|
wire bus_sideeffect_pend = _T_4769 | _T_4771; // @[lsu_bus_buffer.scala 565:157]
|
|
wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 291:74]
|
|
wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 291:52]
|
|
wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 291:50]
|
|
wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72]
|
|
wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 292:36]
|
|
wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 390:31]
|
|
wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 292:47]
|
|
wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58]
|
|
wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72]
|
|
wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72]
|
|
wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72]
|
|
wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72]
|
|
wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72]
|
|
wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72]
|
|
wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72]
|
|
wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 293:23]
|
|
wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 293:21]
|
|
wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 293:141]
|
|
wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 293:105]
|
|
wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 293:103]
|
|
reg buf_dual_3; // @[Reg.scala 27:20]
|
|
reg buf_dual_2; // @[Reg.scala 27:20]
|
|
reg buf_dual_1; // @[Reg.scala 27:20]
|
|
reg buf_dual_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58]
|
|
wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72]
|
|
wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72]
|
|
wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72]
|
|
wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72]
|
|
wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72]
|
|
wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72]
|
|
wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72]
|
|
reg buf_samedw_3; // @[Reg.scala 27:20]
|
|
reg buf_samedw_2; // @[Reg.scala 27:20]
|
|
reg buf_samedw_1; // @[Reg.scala 27:20]
|
|
reg buf_samedw_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58]
|
|
wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72]
|
|
wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72]
|
|
wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72]
|
|
wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72]
|
|
wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72]
|
|
wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72]
|
|
wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72]
|
|
wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 294:77]
|
|
wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72]
|
|
wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72]
|
|
wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72]
|
|
wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72]
|
|
wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72]
|
|
wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72]
|
|
wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72]
|
|
wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 294:150]
|
|
wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 294:148]
|
|
wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 294:8]
|
|
wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 386:62]
|
|
wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 386:59]
|
|
wire _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 386:76]
|
|
wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 386:45]
|
|
wire _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 386:83]
|
|
wire _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 386:81]
|
|
wire _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 386:98]
|
|
wire _T_1969 = _T_1967 & _T_4442; // @[lsu_bus_buffer.scala 386:123]
|
|
wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 386:59]
|
|
wire _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 386:76]
|
|
wire _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 386:45]
|
|
wire _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 386:83]
|
|
wire _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 386:81]
|
|
wire _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 386:98]
|
|
wire _T_1958 = _T_1956 & _T_4437; // @[lsu_bus_buffer.scala 386:123]
|
|
wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 386:59]
|
|
wire _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 386:76]
|
|
wire _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 386:45]
|
|
wire _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 386:83]
|
|
wire _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 386:81]
|
|
wire _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 386:98]
|
|
wire _T_1947 = _T_1945 & _T_4432; // @[lsu_bus_buffer.scala 386:123]
|
|
wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 386:59]
|
|
wire _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 386:76]
|
|
wire _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 386:45]
|
|
wire _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 386:83]
|
|
wire _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 386:81]
|
|
wire _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 386:98]
|
|
wire _T_1936 = _T_1934 & _T_4427; // @[lsu_bus_buffer.scala 386:123]
|
|
wire [3:0] CmdPtr1Dec = {_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58]
|
|
wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 391:31]
|
|
wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 294:181]
|
|
wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58]
|
|
wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72]
|
|
wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72]
|
|
wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72]
|
|
wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72]
|
|
wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72]
|
|
wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72]
|
|
wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72]
|
|
wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 294:197]
|
|
wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 294:269]
|
|
wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 293:164]
|
|
wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 291:98]
|
|
reg obuf_write; // @[Reg.scala 27:20]
|
|
reg obuf_cmd_done; // @[Reg.scala 27:20]
|
|
reg obuf_data_done; // @[Reg.scala 27:20]
|
|
wire _T_4825 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 569:54]
|
|
wire _T_4826 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 569:75]
|
|
wire _T_4827 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 569:153]
|
|
wire _T_4828 = _T_4825 ? _T_4826 : _T_4827; // @[lsu_bus_buffer.scala 569:39]
|
|
wire bus_cmd_ready = obuf_write ? _T_4828 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 569:23]
|
|
wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 295:48]
|
|
wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 295:46]
|
|
reg obuf_nosend; // @[Reg.scala 27:20]
|
|
wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 295:60]
|
|
wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 295:29]
|
|
wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 295:77]
|
|
wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 295:75]
|
|
reg [31:0] obuf_addr; // @[Reg.scala 27:20]
|
|
wire _T_4776 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 567:37]
|
|
wire _T_4777 = obuf_valid & _T_4776; // @[lsu_bus_buffer.scala 567:19]
|
|
wire _T_4779 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 567:107]
|
|
wire _T_4780 = obuf_merge & _T_4779; // @[lsu_bus_buffer.scala 567:95]
|
|
wire _T_4781 = _T_3565 | _T_4780; // @[lsu_bus_buffer.scala 567:81]
|
|
wire _T_4782 = ~_T_4781; // @[lsu_bus_buffer.scala 567:61]
|
|
wire _T_4783 = _T_4777 & _T_4782; // @[lsu_bus_buffer.scala 567:59]
|
|
wire _T_4817 = _T_4751 & _T_4783; // @[Mux.scala 27:72]
|
|
wire _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 567:37]
|
|
wire _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 567:19]
|
|
wire _T_4790 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 567:107]
|
|
wire _T_4791 = obuf_merge & _T_4790; // @[lsu_bus_buffer.scala 567:95]
|
|
wire _T_4792 = _T_3756 | _T_4791; // @[lsu_bus_buffer.scala 567:81]
|
|
wire _T_4793 = ~_T_4792; // @[lsu_bus_buffer.scala 567:61]
|
|
wire _T_4794 = _T_4788 & _T_4793; // @[lsu_bus_buffer.scala 567:59]
|
|
wire _T_4818 = _T_4755 & _T_4794; // @[Mux.scala 27:72]
|
|
wire _T_4821 = _T_4817 | _T_4818; // @[Mux.scala 27:72]
|
|
wire _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 567:37]
|
|
wire _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 567:19]
|
|
wire _T_4801 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 567:107]
|
|
wire _T_4802 = obuf_merge & _T_4801; // @[lsu_bus_buffer.scala 567:95]
|
|
wire _T_4803 = _T_3947 | _T_4802; // @[lsu_bus_buffer.scala 567:81]
|
|
wire _T_4804 = ~_T_4803; // @[lsu_bus_buffer.scala 567:61]
|
|
wire _T_4805 = _T_4799 & _T_4804; // @[lsu_bus_buffer.scala 567:59]
|
|
wire _T_4819 = _T_4759 & _T_4805; // @[Mux.scala 27:72]
|
|
wire _T_4822 = _T_4821 | _T_4819; // @[Mux.scala 27:72]
|
|
wire _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 567:37]
|
|
wire _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 567:19]
|
|
wire _T_4812 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 567:107]
|
|
wire _T_4813 = obuf_merge & _T_4812; // @[lsu_bus_buffer.scala 567:95]
|
|
wire _T_4814 = _T_4138 | _T_4813; // @[lsu_bus_buffer.scala 567:81]
|
|
wire _T_4815 = ~_T_4814; // @[lsu_bus_buffer.scala 567:61]
|
|
wire _T_4816 = _T_4810 & _T_4815; // @[lsu_bus_buffer.scala 567:59]
|
|
wire _T_4820 = _T_4763 & _T_4816; // @[Mux.scala 27:72]
|
|
wire bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72]
|
|
wire _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 295:94]
|
|
wire _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 295:92]
|
|
wire obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 295:118]
|
|
wire _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 298:47]
|
|
wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 570:40]
|
|
wire _T_4832 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 572:35]
|
|
wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 571:40]
|
|
wire _T_4833 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 572:70]
|
|
wire _T_4834 = _T_4832 & _T_4833; // @[lsu_bus_buffer.scala 572:52]
|
|
wire _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 572:112]
|
|
wire bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 572:89]
|
|
wire _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 298:33]
|
|
wire _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 298:65]
|
|
wire _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 298:63]
|
|
wire _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 298:77]
|
|
wire obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 298:98]
|
|
wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 299:26]
|
|
wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1284 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72]
|
|
wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 301:25]
|
|
reg [1:0] buf_sz_0; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1295 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_2; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1296 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
|
|
reg [1:0] buf_sz_3; // @[Reg.scala 27:20]
|
|
wire [1:0] _T_1297 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72]
|
|
wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 304:23]
|
|
wire [7:0] _T_2018 = {4'h0,_T_1969,_T_1958,_T_1947,_T_1936}; // @[Cat.scala 29:58]
|
|
wire _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 393:42]
|
|
wire _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 393:48]
|
|
wire _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 393:54]
|
|
wire _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 393:67]
|
|
wire _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 393:73]
|
|
wire _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 393:79]
|
|
wire _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 393:92]
|
|
wire _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 393:98]
|
|
wire _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 393:104]
|
|
wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58]
|
|
wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 400:11]
|
|
wire _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 312:39]
|
|
wire _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 312:26]
|
|
wire obuf_cmd_done_in = _T_1303 & _T_4832; // @[lsu_bus_buffer.scala 312:51]
|
|
wire obuf_data_done_in = _T_1303 & _T_4833; // @[lsu_bus_buffer.scala 315:52]
|
|
wire _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 316:72]
|
|
wire _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 316:98]
|
|
wire _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 316:96]
|
|
wire _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 316:79]
|
|
wire _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 316:153]
|
|
wire _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 316:134]
|
|
wire _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 316:132]
|
|
wire _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 316:116]
|
|
wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 316:28]
|
|
wire _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 330:40]
|
|
wire _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 330:60]
|
|
wire _T_1339 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 330:80]
|
|
wire _T_1340 = _T_1338 & _T_1339; // @[lsu_bus_buffer.scala 330:78]
|
|
wire _T_1341 = ~obuf_write; // @[lsu_bus_buffer.scala 330:99]
|
|
wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 330:97]
|
|
wire _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 330:113]
|
|
wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 330:111]
|
|
wire _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 330:130]
|
|
wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 330:128]
|
|
wire _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 331:20]
|
|
wire _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 331:18]
|
|
reg obuf_rdrsp_pend; // @[Reg.scala 27:20]
|
|
wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 573:38]
|
|
reg [2:0] obuf_rdrsp_tag; // @[Reg.scala 27:20]
|
|
wire _T_1349 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 331:90]
|
|
wire _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 331:70]
|
|
wire _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 331:55]
|
|
wire _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 331:53]
|
|
wire _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 331:34]
|
|
wire obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 330:177]
|
|
wire _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 324:45]
|
|
wire _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 324:43]
|
|
wire _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 324:30]
|
|
wire _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 324:62]
|
|
wire _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 324:80]
|
|
wire _T_1330 = bus_cmd_sent & _T_1341; // @[lsu_bus_buffer.scala 324:155]
|
|
wire _T_1331 = _T_1328 | _T_1330; // @[lsu_bus_buffer.scala 324:139]
|
|
wire obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 324:171]
|
|
wire obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 325:47]
|
|
wire [7:0] _T_1356 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1356 : _T_1357; // @[lsu_bus_buffer.scala 332:46]
|
|
wire [3:0] _T_1377 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1378 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1379 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1380 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1381 = _T_1377 | _T_1378; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1382 = _T_1381 | _T_1379; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1383 = _T_1382 | _T_1380; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1385 = {_T_1383,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1398 = {4'h0,_T_1383}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1399 = _T_1287[2] ? _T_1385 : _T_1398; // @[lsu_bus_buffer.scala 333:8]
|
|
wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1399; // @[lsu_bus_buffer.scala 332:28]
|
|
wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 334:46]
|
|
wire _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_1407 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 62:123]
|
|
wire [31:0] _T_1408 = _T_1404 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1409 = _T_1405 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1410 = _T_1406 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1411 = _T_1407 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1412 = _T_1408 | _T_1409; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1413 = _T_1412 | _T_1410; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1414 = _T_1413 | _T_1411; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1422 = _T_1404 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1423 = _T_1405 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1424 = _T_1406 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1425 = _T_1407 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1426 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1427 = _T_1426 | _T_1424; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 335:8]
|
|
wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 334:28]
|
|
wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 337:44]
|
|
wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1470 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1471 = _T_1467 | _T_1468; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1472 = _T_1471 | _T_1469; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 338:8]
|
|
wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 337:26]
|
|
wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 339:44]
|
|
wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1515 = _T_1407 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1516 = _T_1512 | _T_1513; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1517 = _T_1516 | _T_1514; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 340:8]
|
|
wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 339:26]
|
|
wire _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 346:30]
|
|
wire _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 346:43]
|
|
wire _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 346:59]
|
|
wire _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 346:75]
|
|
wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1642 = _T_1406 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
|
|
wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72]
|
|
wire _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 346:150]
|
|
wire _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 346:118]
|
|
wire _T_1670 = _T_1649 & _T_1128; // @[lsu_bus_buffer.scala 346:161]
|
|
wire _T_1688 = _T_1670 & _T_1053; // @[lsu_bus_buffer.scala 347:85]
|
|
wire _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 348:36]
|
|
reg buf_dualhi_3; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_2; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_1; // @[Reg.scala 27:20]
|
|
reg buf_dualhi_0; // @[Reg.scala 27:20]
|
|
wire [3:0] _T_1728 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58]
|
|
wire _T_1737 = _T_1023 & _T_1728[0]; // @[Mux.scala 27:72]
|
|
wire _T_1738 = _T_1024 & _T_1728[1]; // @[Mux.scala 27:72]
|
|
wire _T_1741 = _T_1737 | _T_1738; // @[Mux.scala 27:72]
|
|
wire _T_1739 = _T_1025 & _T_1728[2]; // @[Mux.scala 27:72]
|
|
wire _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72]
|
|
wire _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72]
|
|
wire _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72]
|
|
wire _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 348:107]
|
|
wire _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 348:105]
|
|
wire _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 348:177]
|
|
wire _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 347:122]
|
|
wire _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 349:19]
|
|
wire _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 349:35]
|
|
wire obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 348:250]
|
|
wire _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1538 = obuf_byteen0_in[0] | _T_1537; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1542 = obuf_byteen0_in[1] | _T_1541; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1546 = obuf_byteen0_in[2] | _T_1545; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1550 = obuf_byteen0_in[3] | _T_1549; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1554 = obuf_byteen0_in[4] | _T_1553; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1558 = obuf_byteen0_in[5] | _T_1557; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1562 = obuf_byteen0_in[6] | _T_1561; // @[lsu_bus_buffer.scala 341:63]
|
|
wire _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 341:80]
|
|
wire _T_1566 = obuf_byteen0_in[7] | _T_1565; // @[lsu_bus_buffer.scala 341:63]
|
|
wire [7:0] obuf_byteen_in = {_T_1566,_T_1562,_T_1558,_T_1554,_T_1550,_T_1546,_T_1542,_T_1538}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 342:44]
|
|
wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58]
|
|
wire _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 351:58]
|
|
wire _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 351:93]
|
|
wire _T_1780 = io_lsu_bus_obuf_c1_clken & obuf_wr_en; // @[lib.scala 399:57]
|
|
reg [1:0] obuf_sz; // @[Reg.scala 27:20]
|
|
reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
|
|
reg [63:0] obuf_data; // @[Reg.scala 27:20]
|
|
wire _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 371:65]
|
|
wire _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 372:30]
|
|
wire _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 372:19]
|
|
wire _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 373:18]
|
|
wire _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 373:57]
|
|
wire _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 373:45]
|
|
wire _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 373:27]
|
|
wire _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 372:58]
|
|
wire _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 372:39]
|
|
wire _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 372:5]
|
|
wire _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 371:76]
|
|
wire _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 371:65]
|
|
wire _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 372:30]
|
|
wire _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 372:19]
|
|
wire _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 373:18]
|
|
wire _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 373:57]
|
|
wire _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 373:45]
|
|
wire _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 373:27]
|
|
wire _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 372:58]
|
|
wire _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 372:39]
|
|
wire _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 372:5]
|
|
wire _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 371:76]
|
|
wire _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 371:65]
|
|
wire _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 372:30]
|
|
wire _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 372:19]
|
|
wire _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 373:18]
|
|
wire _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 373:57]
|
|
wire _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 373:45]
|
|
wire _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 373:27]
|
|
wire _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 372:58]
|
|
wire _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 372:39]
|
|
wire _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 372:5]
|
|
wire _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 371:76]
|
|
wire _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 371:65]
|
|
wire _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 372:30]
|
|
wire _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 373:18]
|
|
wire _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 373:57]
|
|
wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16]
|
|
wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16]
|
|
wire _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 378:33]
|
|
wire _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 378:22]
|
|
wire _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 377:112]
|
|
wire _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 378:42]
|
|
wire _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 377:78]
|
|
wire _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 377:76]
|
|
wire _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 378:33]
|
|
wire _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 378:22]
|
|
wire _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 377:112]
|
|
wire _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 378:42]
|
|
wire _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 377:78]
|
|
wire _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 377:76]
|
|
wire _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 378:33]
|
|
wire _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 378:22]
|
|
wire _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 377:112]
|
|
wire _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 378:42]
|
|
wire _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 377:78]
|
|
wire _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 377:76]
|
|
reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 516:63]
|
|
wire _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 421:102]
|
|
wire _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 421:102]
|
|
wire _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 421:102]
|
|
wire _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 421:102]
|
|
wire _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 421:87]
|
|
wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58]
|
|
wire _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 389:65]
|
|
wire _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 389:44]
|
|
wire _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 389:70]
|
|
reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 516:63]
|
|
wire _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 421:87]
|
|
wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58]
|
|
wire _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 389:65]
|
|
wire _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 389:44]
|
|
wire _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 389:70]
|
|
reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 516:63]
|
|
wire _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 421:87]
|
|
wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58]
|
|
wire _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 389:65]
|
|
wire _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 389:44]
|
|
wire _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 389:70]
|
|
reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 516:63]
|
|
wire _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 421:87]
|
|
wire _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 421:87]
|
|
wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58]
|
|
wire _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 389:65]
|
|
wire _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 389:44]
|
|
wire _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 389:70]
|
|
wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58]
|
|
wire _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 393:42]
|
|
wire _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 393:48]
|
|
wire _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 393:54]
|
|
wire _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 393:67]
|
|
wire _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 393:73]
|
|
wire _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 393:79]
|
|
wire _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 393:92]
|
|
wire _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 393:98]
|
|
wire _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 393:104]
|
|
wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58]
|
|
wire _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 447:77]
|
|
wire _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 447:97]
|
|
wire _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 447:95]
|
|
wire _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 447:117]
|
|
wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 447:112]
|
|
wire _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 447:144]
|
|
wire _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 447:166]
|
|
wire _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 447:161]
|
|
wire _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 447:132]
|
|
wire _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 447:63]
|
|
wire _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 447:206]
|
|
wire _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 447:201]
|
|
wire _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 447:183]
|
|
wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 574:39]
|
|
wire _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 477:73]
|
|
wire _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 477:52]
|
|
wire _T_3638 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 478:46]
|
|
reg _T_4302; // @[Reg.scala 27:20]
|
|
reg _T_4300; // @[Reg.scala 27:20]
|
|
reg _T_4298; // @[Reg.scala 27:20]
|
|
reg _T_4296; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58]
|
|
reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_386 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_3640 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_3641 = buf_ldfwd[0] & _T_3640; // @[lsu_bus_buffer.scala 479:27]
|
|
wire _T_3642 = _T_3638 | _T_3641; // @[lsu_bus_buffer.scala 478:77]
|
|
wire _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 480:26]
|
|
wire _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 480:44]
|
|
wire _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 480:42]
|
|
wire _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 480:58]
|
|
reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_387 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_3648 = io_lsu_axi_r_bits_id == _GEN_387; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 480:74]
|
|
wire _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 479:71]
|
|
wire _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 478:25]
|
|
wire _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 477:105]
|
|
wire _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67]
|
|
wire _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
|
|
wire _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
|
|
wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 494:21]
|
|
reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20]
|
|
reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20]
|
|
reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20]
|
|
wire [1:0] _GEN_33 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_34 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_33; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_35 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_34; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [2:0] _GEN_389 = {{1'd0}, _GEN_35}; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_3689 = io_lsu_axi_r_bits_id == _GEN_389; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_3690 = _T_3687[0] & _T_3689; // @[lsu_bus_buffer.scala 494:38]
|
|
wire _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 493:95]
|
|
wire _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 493:45]
|
|
wire _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67]
|
|
wire _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67]
|
|
wire _GEN_63 = _T_3558 ? buf_cmd_state_bus_en_0 : _GEN_53; // @[Conditional.scala 39:67]
|
|
wire _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
|
|
wire _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 464:49]
|
|
wire _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 464:70]
|
|
wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 401:10]
|
|
wire _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 501:37]
|
|
wire _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 501:98]
|
|
wire _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 501:80]
|
|
wire _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 501:65]
|
|
wire _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 501:112]
|
|
wire _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67]
|
|
wire _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67]
|
|
wire _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67]
|
|
wire _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67]
|
|
wire _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58]
|
|
wire _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 413:94]
|
|
wire _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 415:23]
|
|
wire _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 415:41]
|
|
wire _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 415:71]
|
|
wire _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 416:17]
|
|
wire _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 416:35]
|
|
wire _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 416:52]
|
|
wire _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58]
|
|
wire _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 447:117]
|
|
wire _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 447:112]
|
|
wire _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 447:166]
|
|
wire _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 447:161]
|
|
wire _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 447:132]
|
|
wire _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 447:63]
|
|
wire _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 447:206]
|
|
wire _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 447:201]
|
|
wire _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 447:183]
|
|
wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 477:73]
|
|
wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 477:52]
|
|
wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 478:46]
|
|
wire [2:0] _GEN_390 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_390; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 479:27]
|
|
wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 478:77]
|
|
wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 480:26]
|
|
wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 480:44]
|
|
wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 480:42]
|
|
wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 480:58]
|
|
reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_391 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_391; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 480:74]
|
|
wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 479:71]
|
|
wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 478:25]
|
|
wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 477:105]
|
|
wire _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67]
|
|
wire _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67]
|
|
wire _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58]
|
|
wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 494:21]
|
|
wire [1:0] _GEN_109 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_110 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_109; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_111 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_110; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [2:0] _GEN_393 = {{1'd0}, _GEN_111}; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_3880 = io_lsu_axi_r_bits_id == _GEN_393; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_3881 = _T_3878[0] & _T_3880; // @[lsu_bus_buffer.scala 494:38]
|
|
wire _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 493:95]
|
|
wire _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 493:45]
|
|
wire _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67]
|
|
wire _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67]
|
|
wire _GEN_139 = _T_3749 ? buf_cmd_state_bus_en_1 : _GEN_129; // @[Conditional.scala 39:67]
|
|
wire _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58]
|
|
wire _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 464:49]
|
|
wire _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 464:70]
|
|
wire _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 501:37]
|
|
wire _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 501:98]
|
|
wire _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 501:80]
|
|
wire _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 501:65]
|
|
wire _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 501:112]
|
|
wire _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67]
|
|
wire _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67]
|
|
wire _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67]
|
|
wire _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67]
|
|
wire _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58]
|
|
wire _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 413:94]
|
|
wire _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 415:71]
|
|
wire _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 416:52]
|
|
wire _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58]
|
|
wire _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 447:117]
|
|
wire _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 447:112]
|
|
wire _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 447:166]
|
|
wire _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 447:161]
|
|
wire _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 447:132]
|
|
wire _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 447:63]
|
|
wire _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 447:206]
|
|
wire _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 447:201]
|
|
wire _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 447:183]
|
|
wire _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 477:73]
|
|
wire _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 477:52]
|
|
wire _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 478:46]
|
|
wire [2:0] _GEN_394 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_4022 = io_lsu_axi_r_bits_id == _GEN_394; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_4023 = buf_ldfwd[2] & _T_4022; // @[lsu_bus_buffer.scala 479:27]
|
|
wire _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 478:77]
|
|
wire _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 480:26]
|
|
wire _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 480:44]
|
|
wire _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 480:42]
|
|
wire _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 480:58]
|
|
reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_395 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_4030 = io_lsu_axi_r_bits_id == _GEN_395; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 480:74]
|
|
wire _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 479:71]
|
|
wire _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 478:25]
|
|
wire _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 477:105]
|
|
wire _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67]
|
|
wire _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67]
|
|
wire _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58]
|
|
wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 494:21]
|
|
wire [1:0] _GEN_185 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_186 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_185; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_187 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_186; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [2:0] _GEN_397 = {{1'd0}, _GEN_187}; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_4071 = io_lsu_axi_r_bits_id == _GEN_397; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_4072 = _T_4069[0] & _T_4071; // @[lsu_bus_buffer.scala 494:38]
|
|
wire _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 493:95]
|
|
wire _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 493:45]
|
|
wire _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67]
|
|
wire _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67]
|
|
wire _GEN_215 = _T_3940 ? buf_cmd_state_bus_en_2 : _GEN_205; // @[Conditional.scala 39:67]
|
|
wire _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58]
|
|
wire _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 464:49]
|
|
wire _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 464:70]
|
|
wire _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 501:37]
|
|
wire _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 501:98]
|
|
wire _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 501:80]
|
|
wire _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 501:65]
|
|
wire _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 501:112]
|
|
wire _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67]
|
|
wire _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67]
|
|
wire _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67]
|
|
wire _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67]
|
|
wire _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58]
|
|
wire _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 413:94]
|
|
wire _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 415:71]
|
|
wire _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 416:52]
|
|
wire _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58]
|
|
wire _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 447:117]
|
|
wire _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 447:112]
|
|
wire _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 447:166]
|
|
wire _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 447:161]
|
|
wire _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 447:132]
|
|
wire _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 447:63]
|
|
wire _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 447:206]
|
|
wire _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 447:201]
|
|
wire _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 447:183]
|
|
wire _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 477:73]
|
|
wire _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 477:52]
|
|
wire _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 478:46]
|
|
wire [2:0] _GEN_398 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_4213 = io_lsu_axi_r_bits_id == _GEN_398; // @[lsu_bus_buffer.scala 479:47]
|
|
wire _T_4214 = buf_ldfwd[3] & _T_4213; // @[lsu_bus_buffer.scala 479:27]
|
|
wire _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 478:77]
|
|
wire _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 480:26]
|
|
wire _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 480:44]
|
|
wire _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 480:42]
|
|
wire _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 480:58]
|
|
reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_399 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_4221 = io_lsu_axi_r_bits_id == _GEN_399; // @[lsu_bus_buffer.scala 480:94]
|
|
wire _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 480:74]
|
|
wire _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 479:71]
|
|
wire _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 478:25]
|
|
wire _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 477:105]
|
|
wire _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67]
|
|
wire _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67]
|
|
wire _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67]
|
|
wire buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58]
|
|
wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 494:21]
|
|
wire [1:0] _GEN_261 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_262 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_261; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [1:0] _GEN_263 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_262; // @[lsu_bus_buffer.scala 494:58]
|
|
wire [2:0] _GEN_401 = {{1'd0}, _GEN_263}; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_4262 = io_lsu_axi_r_bits_id == _GEN_401; // @[lsu_bus_buffer.scala 494:58]
|
|
wire _T_4263 = _T_4260[0] & _T_4262; // @[lsu_bus_buffer.scala 494:38]
|
|
wire _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 493:95]
|
|
wire _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 493:45]
|
|
wire _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67]
|
|
wire _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67]
|
|
wire _GEN_291 = _T_4131 ? buf_cmd_state_bus_en_3 : _GEN_281; // @[Conditional.scala 39:67]
|
|
wire _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67]
|
|
wire buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58]
|
|
wire _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 464:49]
|
|
wire _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 464:70]
|
|
wire _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 501:37]
|
|
wire _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 501:98]
|
|
wire _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 501:80]
|
|
wire _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 501:65]
|
|
wire _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 501:112]
|
|
wire _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67]
|
|
wire _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67]
|
|
wire _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67]
|
|
wire _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67]
|
|
wire _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67]
|
|
wire buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58]
|
|
wire _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 413:94]
|
|
wire _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 415:71]
|
|
wire _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 416:52]
|
|
wire _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 415:92]
|
|
wire _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 414:86]
|
|
wire _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 416:73]
|
|
wire _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 415:114]
|
|
wire _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 413:113]
|
|
wire _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 416:97]
|
|
wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58]
|
|
wire _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 424:47]
|
|
wire _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 424:32]
|
|
wire _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 424:6]
|
|
wire _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 424:47]
|
|
wire _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 424:32]
|
|
wire _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 424:6]
|
|
wire _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 424:47]
|
|
wire _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 424:32]
|
|
wire _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 424:6]
|
|
wire _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 424:47]
|
|
wire _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 424:32]
|
|
wire _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 424:6]
|
|
wire _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 423:112]
|
|
wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58]
|
|
wire _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 423:112]
|
|
wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58]
|
|
wire _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 423:112]
|
|
wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58]
|
|
wire _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 423:112]
|
|
wire _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 424:59]
|
|
wire _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 425:110]
|
|
wire _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 423:112]
|
|
wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58]
|
|
wire _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 428:110]
|
|
wire _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 428:84]
|
|
wire _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 428:110]
|
|
wire _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 428:84]
|
|
wire _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 428:110]
|
|
wire _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 428:84]
|
|
wire _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 428:110]
|
|
wire _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 428:84]
|
|
wire _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58]
|
|
wire _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58]
|
|
wire _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58]
|
|
wire _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58]
|
|
wire _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58]
|
|
wire _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58]
|
|
wire _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 428:82]
|
|
wire _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 428:136]
|
|
wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58]
|
|
wire _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 427:88]
|
|
wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58]
|
|
wire _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 429:63]
|
|
wire _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 429:63]
|
|
wire _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 429:63]
|
|
wire _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 429:63]
|
|
wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58]
|
|
wire _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 431:35]
|
|
wire _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 431:35]
|
|
wire _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 431:35]
|
|
wire _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 431:35]
|
|
wire _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 433:45]
|
|
wire _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 433:45]
|
|
wire _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 433:45]
|
|
wire _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 433:45]
|
|
wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58]
|
|
wire _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 434:47]
|
|
wire _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 434:47]
|
|
wire _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 434:47]
|
|
wire _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 434:47]
|
|
wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58]
|
|
wire _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 435:84]
|
|
wire _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 435:48]
|
|
wire _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 435:48]
|
|
wire _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 435:48]
|
|
wire _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 435:48]
|
|
wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58]
|
|
wire _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 436:47]
|
|
wire _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 436:47]
|
|
wire _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 436:47]
|
|
wire _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 436:47]
|
|
wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58]
|
|
wire _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 438:51]
|
|
wire _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 438:51]
|
|
wire _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 438:51]
|
|
wire _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 438:51]
|
|
wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58]
|
|
wire _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 439:47]
|
|
wire _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 439:47]
|
|
wire _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 439:47]
|
|
wire _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 439:47]
|
|
wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58]
|
|
wire _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 441:46]
|
|
wire _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 441:46]
|
|
wire _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 441:46]
|
|
wire _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 441:46]
|
|
wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58]
|
|
wire _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 461:89]
|
|
wire _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 461:104]
|
|
wire _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 466:44]
|
|
wire _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 466:60]
|
|
wire _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 466:74]
|
|
wire _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 468:67]
|
|
wire _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 468:81]
|
|
wire _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 578:64]
|
|
wire bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 578:38]
|
|
wire _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 469:82]
|
|
wire _T_3659 = bus_rsp_read_error & _T_3638; // @[lsu_bus_buffer.scala 484:91]
|
|
wire _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 485:31]
|
|
wire _T_3663 = _T_3661 & _T_3640; // @[lsu_bus_buffer.scala 485:46]
|
|
wire _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 484:143]
|
|
wire _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 577:66]
|
|
wire bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 577:40]
|
|
wire _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 486:33]
|
|
wire _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 485:88]
|
|
wire _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 484:68]
|
|
wire _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67]
|
|
wire _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67]
|
|
wire _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
|
|
wire _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 474:75]
|
|
wire _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 474:73]
|
|
wire _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 474:57]
|
|
wire _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 475:30]
|
|
wire _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 475:28]
|
|
wire _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 475:45]
|
|
wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 475:61]
|
|
wire _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 538:93]
|
|
wire _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 538:93]
|
|
wire any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 538:93]
|
|
wire _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 476:31]
|
|
wire _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72]
|
|
wire _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72]
|
|
wire _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72]
|
|
wire _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 476:101]
|
|
wire _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 476:167]
|
|
wire _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 476:138]
|
|
wire _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 476:187]
|
|
wire _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 476:53]
|
|
wire _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 483:47]
|
|
wire _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 483:62]
|
|
wire _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 487:50]
|
|
wire _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 487:48]
|
|
wire _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 492:90]
|
|
wire _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 492:118]
|
|
wire _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
|
|
wire _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67]
|
|
wire _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67]
|
|
wire _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67]
|
|
wire _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67]
|
|
wire _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67]
|
|
wire _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67]
|
|
wire _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67]
|
|
wire _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67]
|
|
wire _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67]
|
|
wire _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67]
|
|
wire _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67]
|
|
wire _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67]
|
|
wire _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58]
|
|
wire buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58]
|
|
wire buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58]
|
|
wire _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 466:44]
|
|
wire _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 466:60]
|
|
wire _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 466:74]
|
|
wire _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 468:67]
|
|
wire _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 468:81]
|
|
wire _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 469:82]
|
|
wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 484:91]
|
|
wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 485:31]
|
|
wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 485:46]
|
|
wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 484:143]
|
|
wire _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 486:33]
|
|
wire _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 485:88]
|
|
wire _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 484:68]
|
|
wire _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67]
|
|
wire _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67]
|
|
wire _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58]
|
|
wire _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 474:73]
|
|
wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 474:57]
|
|
wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 475:30]
|
|
wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 475:28]
|
|
wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 475:45]
|
|
wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 475:61]
|
|
wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 476:31]
|
|
wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72]
|
|
wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72]
|
|
wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72]
|
|
wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 476:101]
|
|
wire _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 476:167]
|
|
wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 476:138]
|
|
wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 476:187]
|
|
wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 476:53]
|
|
wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 483:47]
|
|
wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 483:62]
|
|
wire _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 487:50]
|
|
wire _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 487:48]
|
|
wire _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 492:90]
|
|
wire _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 492:118]
|
|
wire _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
|
|
wire _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67]
|
|
wire _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67]
|
|
wire _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67]
|
|
wire _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67]
|
|
wire _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67]
|
|
wire _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67]
|
|
wire _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67]
|
|
wire _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67]
|
|
wire _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67]
|
|
wire _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67]
|
|
wire _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67]
|
|
wire _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67]
|
|
wire _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58]
|
|
wire buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58]
|
|
wire buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58]
|
|
wire _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 466:44]
|
|
wire _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 466:60]
|
|
wire _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 466:74]
|
|
wire _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 468:67]
|
|
wire _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 468:81]
|
|
wire _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 469:82]
|
|
wire _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 484:91]
|
|
wire _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 485:31]
|
|
wire _T_4045 = _T_4043 & _T_4022; // @[lsu_bus_buffer.scala 485:46]
|
|
wire _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 484:143]
|
|
wire _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 486:33]
|
|
wire _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 485:88]
|
|
wire _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 484:68]
|
|
wire _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67]
|
|
wire _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67]
|
|
wire _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58]
|
|
wire _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 474:73]
|
|
wire _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 474:57]
|
|
wire _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 475:30]
|
|
wire _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 475:28]
|
|
wire _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 475:45]
|
|
wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 475:61]
|
|
wire _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 476:31]
|
|
wire _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72]
|
|
wire _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72]
|
|
wire _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72]
|
|
wire _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 476:101]
|
|
wire _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 476:167]
|
|
wire _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 476:138]
|
|
wire _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 476:187]
|
|
wire _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 476:53]
|
|
wire _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 483:47]
|
|
wire _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 483:62]
|
|
wire _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 487:50]
|
|
wire _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 487:48]
|
|
wire _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 492:90]
|
|
wire _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 492:118]
|
|
wire _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
|
|
wire _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67]
|
|
wire _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67]
|
|
wire _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67]
|
|
wire _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67]
|
|
wire _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67]
|
|
wire _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67]
|
|
wire _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67]
|
|
wire _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67]
|
|
wire _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67]
|
|
wire _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67]
|
|
wire _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67]
|
|
wire _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67]
|
|
wire _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58]
|
|
wire buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58]
|
|
wire buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58]
|
|
wire _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 466:44]
|
|
wire _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 466:60]
|
|
wire _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 466:74]
|
|
wire _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 468:67]
|
|
wire _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 468:81]
|
|
wire _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 469:82]
|
|
wire _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 484:91]
|
|
wire _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 485:31]
|
|
wire _T_4236 = _T_4234 & _T_4213; // @[lsu_bus_buffer.scala 485:46]
|
|
wire _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 484:143]
|
|
wire _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 486:33]
|
|
wire _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 485:88]
|
|
wire _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 484:68]
|
|
wire _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67]
|
|
wire _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67]
|
|
wire _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67]
|
|
wire buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58]
|
|
wire _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 474:73]
|
|
wire _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 474:57]
|
|
wire _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 475:30]
|
|
wire _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 475:28]
|
|
wire _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 475:45]
|
|
wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 475:90]
|
|
wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 475:90]
|
|
wire _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 475:61]
|
|
wire _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 476:31]
|
|
wire _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 61:118]
|
|
wire _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72]
|
|
wire _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72]
|
|
wire _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72]
|
|
wire _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72]
|
|
wire _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72]
|
|
wire _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72]
|
|
wire _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72]
|
|
wire _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 476:101]
|
|
wire _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 476:167]
|
|
wire _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 476:138]
|
|
wire _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 476:187]
|
|
wire _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 476:53]
|
|
wire _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 483:47]
|
|
wire _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 483:62]
|
|
wire _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 487:50]
|
|
wire _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 487:48]
|
|
wire _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 492:90]
|
|
wire _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 492:118]
|
|
wire _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
|
|
wire _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67]
|
|
wire _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67]
|
|
wire _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67]
|
|
wire _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67]
|
|
wire _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67]
|
|
wire _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67]
|
|
wire _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67]
|
|
wire _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67]
|
|
wire _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67]
|
|
wire _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67]
|
|
wire _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67]
|
|
wire _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67]
|
|
wire _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67]
|
|
wire buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58]
|
|
wire buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58]
|
|
wire buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58]
|
|
wire buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58]
|
|
reg _T_4331; // @[Reg.scala 27:20]
|
|
reg _T_4334; // @[Reg.scala 27:20]
|
|
reg _T_4337; // @[Reg.scala 27:20]
|
|
reg _T_4340; // @[Reg.scala 27:20]
|
|
wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58]
|
|
wire _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 533:81]
|
|
reg _T_4406; // @[lsu_bus_buffer.scala 533:80]
|
|
reg _T_4401; // @[lsu_bus_buffer.scala 533:80]
|
|
reg _T_4396; // @[lsu_bus_buffer.scala 533:80]
|
|
reg _T_4391; // @[lsu_bus_buffer.scala 533:80]
|
|
wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58]
|
|
wire _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 533:98]
|
|
wire _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 533:81]
|
|
wire _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 533:98]
|
|
wire _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 533:81]
|
|
wire _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 533:98]
|
|
wire _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 533:81]
|
|
wire _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 533:98]
|
|
wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 534:28]
|
|
wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 534:94]
|
|
wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 534:88]
|
|
wire [2:0] _GEN_406 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 534:154]
|
|
wire [3:0] _T_4415 = _T_4414 + _GEN_406; // @[lsu_bus_buffer.scala 534:154]
|
|
wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 534:217]
|
|
wire [1:0] _GEN_407 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 534:217]
|
|
wire [2:0] _T_4421 = _T_4420 + _GEN_407; // @[lsu_bus_buffer.scala 534:217]
|
|
wire [2:0] _GEN_408 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 534:217]
|
|
wire [3:0] _T_4422 = _T_4421 + _GEN_408; // @[lsu_bus_buffer.scala 534:217]
|
|
wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 534:169]
|
|
wire _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 540:52]
|
|
wire _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 540:92]
|
|
wire _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 540:121]
|
|
wire _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 541:52]
|
|
wire _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 541:52]
|
|
wire _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 541:52]
|
|
wire _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 541:52]
|
|
wire _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 541:65]
|
|
wire _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 541:65]
|
|
wire _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 541:65]
|
|
wire _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 541:34]
|
|
wire _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 541:70]
|
|
wire _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 543:64]
|
|
wire _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 543:85]
|
|
wire _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 543:112]
|
|
wire _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 543:110]
|
|
wire _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 543:129]
|
|
wire _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 546:74]
|
|
reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 631:66]
|
|
wire _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72]
|
|
wire _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72]
|
|
wire _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72]
|
|
wire _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72]
|
|
wire _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72]
|
|
wire _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72]
|
|
wire lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72]
|
|
wire _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 549:121]
|
|
wire _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 549:121]
|
|
wire _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 549:121]
|
|
wire _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 549:121]
|
|
wire _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72]
|
|
wire _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72]
|
|
wire _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72]
|
|
wire _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72]
|
|
wire _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72]
|
|
wire _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72]
|
|
wire _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 550:121]
|
|
wire _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 550:136]
|
|
wire _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 550:134]
|
|
wire _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 550:118]
|
|
wire _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 550:121]
|
|
wire _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 550:136]
|
|
wire _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 550:134]
|
|
wire _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 550:118]
|
|
wire _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 550:121]
|
|
wire _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 550:136]
|
|
wire _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 550:134]
|
|
wire _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 550:118]
|
|
wire _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 550:121]
|
|
wire _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 550:136]
|
|
wire _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 550:134]
|
|
wire _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 550:118]
|
|
wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_409 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4601 = _GEN_409 | _T_4598; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72]
|
|
wire _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 552:105]
|
|
wire _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 552:105]
|
|
wire _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 552:105]
|
|
wire _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 552:105]
|
|
wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72]
|
|
wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72]
|
|
wire _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 62:123]
|
|
wire _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 62:123]
|
|
wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 553:96]
|
|
wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72]
|
|
wire _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72]
|
|
wire _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72]
|
|
wire _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72]
|
|
wire _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72]
|
|
wire _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72]
|
|
wire _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72]
|
|
wire lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_410 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 557:121]
|
|
wire [5:0] _T_4713 = _GEN_410 * 4'h8; // @[lsu_bus_buffer.scala 557:121]
|
|
wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 557:92]
|
|
wire _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 559:82]
|
|
wire _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 560:81]
|
|
wire _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 560:63]
|
|
wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 561:45]
|
|
wire _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 561:26]
|
|
wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 562:6]
|
|
wire _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 562:27]
|
|
wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 563:27]
|
|
wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
|
wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
|
|
wire _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 564:21]
|
|
wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72]
|
|
wire [63:0] _GEN_411 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_4749 = _GEN_411 | _T_4745; // @[Mux.scala 27:72]
|
|
wire _T_4843 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 582:37]
|
|
wire _T_4844 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 582:52]
|
|
wire _T_4845 = _T_4843 & _T_4844; // @[lsu_bus_buffer.scala 582:50]
|
|
wire [31:0] _T_4849 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58]
|
|
wire [2:0] _T_4851 = {1'h0,obuf_sz}; // @[Cat.scala 29:58]
|
|
wire _T_4856 = ~obuf_data_done; // @[lsu_bus_buffer.scala 594:51]
|
|
wire _T_4857 = _T_4843 & _T_4856; // @[lsu_bus_buffer.scala 594:49]
|
|
wire [7:0] _T_4861 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
wire _T_4864 = obuf_valid & _T_1341; // @[lsu_bus_buffer.scala 599:37]
|
|
wire _T_4866 = _T_4864 & _T_1347; // @[lsu_bus_buffer.scala 599:51]
|
|
wire _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 612:126]
|
|
wire _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 612:141]
|
|
wire _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 612:126]
|
|
wire _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 612:141]
|
|
wire _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 612:126]
|
|
wire _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 612:141]
|
|
wire _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 612:126]
|
|
wire _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 612:141]
|
|
wire _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72]
|
|
wire _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72]
|
|
wire _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72]
|
|
wire _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72]
|
|
wire _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72]
|
|
wire _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72]
|
|
wire _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 613:93]
|
|
wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 613:108]
|
|
wire _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 613:93]
|
|
wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 613:108]
|
|
wire _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 613:93]
|
|
wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 613:108]
|
|
wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
|
wire [1:0] _GEN_412 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72]
|
|
wire [1:0] _T_4929 = _GEN_412 | _T_4926; // @[Mux.scala 27:72]
|
|
wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72]
|
|
wire _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 615:97]
|
|
wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 616:53]
|
|
wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 616:53]
|
|
wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 616:53]
|
|
wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 616:53]
|
|
wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 616:53]
|
|
wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 616:53]
|
|
wire _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 622:82]
|
|
wire _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 623:60]
|
|
wire _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 626:61]
|
|
wire _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 626:59]
|
|
wire _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 626:107]
|
|
wire _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 626:105]
|
|
wire _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 626:83]
|
|
wire _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 626:153]
|
|
wire _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 626:151]
|
|
wire _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 630:75]
|
|
wire _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 630:73]
|
|
reg _T_4956; // @[lsu_bus_buffer.scala 630:56]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 622:35]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 623:41]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 624:36]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 626:35]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 615:47]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 612:48]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 616:47]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 543:45]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 544:43]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 546:43]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 547:47]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 559:48]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 549:48]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 550:45]
|
|
assign io_lsu_axi_aw_valid = _T_4845 & _T_1237; // @[lsu_bus_buffer.scala 582:23]
|
|
assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 583:25]
|
|
assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 584:27]
|
|
assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 588:29]
|
|
assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 585:27]
|
|
assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 587:28]
|
|
assign io_lsu_axi_w_valid = _T_4857 & _T_1237; // @[lsu_bus_buffer.scala 594:22]
|
|
assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 596:26]
|
|
assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4861; // @[lsu_bus_buffer.scala 595:26]
|
|
assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 610:22]
|
|
assign io_lsu_axi_ar_valid = _T_4866 & _T_1237; // @[lsu_bus_buffer.scala 599:23]
|
|
assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1781}; // @[lsu_bus_buffer.scala 600:25]
|
|
assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4849; // @[lsu_bus_buffer.scala 601:27]
|
|
assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 605:29]
|
|
assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4851 : 3'h3; // @[lsu_bus_buffer.scala 602:27]
|
|
assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 604:28]
|
|
assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 611:22]
|
|
assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 630:19]
|
|
assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 539:30]
|
|
assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 540:30]
|
|
assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 541:31]
|
|
assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 142:25]
|
|
assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 143:25]
|
|
assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 169:24]
|
|
assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 176:24]
|
|
assign io_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 560:29]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
buf_addr_0 = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_4355 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
_T_4352 = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_4349 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_4346 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
buf_state_0 = _RAND_5[2:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
buf_addr_1 = _RAND_6[31:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
buf_state_1 = _RAND_7[2:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
buf_addr_2 = _RAND_8[31:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
buf_state_2 = _RAND_9[2:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
buf_addr_3 = _RAND_10[31:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
buf_state_3 = _RAND_11[2:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
buf_byteen_3 = _RAND_12[3:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
buf_byteen_2 = _RAND_13[3:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
buf_byteen_1 = _RAND_14[3:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
buf_byteen_0 = _RAND_15[3:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
buf_ageQ_3 = _RAND_16[3:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_1781 = _RAND_17[1:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
obuf_merge = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
obuf_tag1 = _RAND_19[1:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
obuf_valid = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
obuf_wr_enQ = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
ibuf_addr = _RAND_22[31:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
ibuf_write = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
ibuf_valid = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
ibuf_byteen = _RAND_25[3:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
buf_ageQ_2 = _RAND_26[3:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
buf_ageQ_1 = _RAND_27[3:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
buf_ageQ_0 = _RAND_28[3:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
buf_data_0 = _RAND_29[31:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
buf_data_1 = _RAND_30[31:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
buf_data_2 = _RAND_31[31:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
buf_data_3 = _RAND_32[31:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
ibuf_data = _RAND_33[31:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
ibuf_timer = _RAND_34[2:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
ibuf_sideeffect = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
WrPtr1_r = _RAND_36[1:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
WrPtr0_r = _RAND_37[1:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
ibuf_tag = _RAND_38[1:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
ibuf_dualtag = _RAND_39[1:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
ibuf_dual = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
ibuf_samedw = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
ibuf_nomerge = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
ibuf_unsign = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
ibuf_sz = _RAND_44[1:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
obuf_wr_timer = _RAND_45[2:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
buf_nomerge_0 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
buf_nomerge_1 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
buf_nomerge_2 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
buf_nomerge_3 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
_T_4325 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
_T_4322 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_4319 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
_T_4316 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
obuf_sideeffect = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
buf_dual_3 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
buf_dual_2 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
buf_dual_1 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
buf_dual_0 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
buf_samedw_3 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
buf_samedw_2 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
buf_samedw_1 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
buf_samedw_0 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
obuf_write = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
obuf_cmd_done = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
obuf_data_done = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
obuf_nosend = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
obuf_addr = _RAND_67[31:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
buf_sz_0 = _RAND_68[1:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
buf_sz_1 = _RAND_69[1:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
buf_sz_2 = _RAND_70[1:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
buf_sz_3 = _RAND_71[1:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
obuf_rdrsp_pend = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
obuf_rdrsp_tag = _RAND_73[2:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
buf_dualhi_3 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
buf_dualhi_2 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
buf_dualhi_1 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
buf_dualhi_0 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
obuf_sz = _RAND_78[1:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
obuf_byteen = _RAND_79[7:0];
|
|
_RAND_80 = {2{`RANDOM}};
|
|
obuf_data = _RAND_80[63:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
buf_rspageQ_0 = _RAND_81[3:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
buf_rspageQ_1 = _RAND_82[3:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
buf_rspageQ_2 = _RAND_83[3:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
buf_rspageQ_3 = _RAND_84[3:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
_T_4302 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
_T_4300 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
_T_4298 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
_T_4296 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
buf_ldfwdtag_0 = _RAND_89[1:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
buf_dualtag_0 = _RAND_90[1:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
buf_ldfwdtag_3 = _RAND_91[1:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
buf_ldfwdtag_2 = _RAND_92[1:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
buf_ldfwdtag_1 = _RAND_93[1:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
buf_dualtag_1 = _RAND_94[1:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
buf_dualtag_2 = _RAND_95[1:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
buf_dualtag_3 = _RAND_96[1:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
_T_4331 = _RAND_97[0:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
_T_4334 = _RAND_98[0:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
_T_4337 = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
_T_4340 = _RAND_100[0:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
_T_4406 = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
_T_4401 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
_T_4396 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
_T_4391 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
lsu_nonblock_load_valid_r = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
_T_4956 = _RAND_106[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
buf_addr_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4355 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4352 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4349 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4346 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_0 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_1 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_2 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_addr_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_state_3 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_byteen_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1781 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_merge = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_tag1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_wr_enQ = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_write = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_valid = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_byteen = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ageQ_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_data_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_data = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_timer = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_sideeffect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr1_r = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr0_r = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_tag = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_dualtag = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_dual = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_samedw = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_nomerge = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_unsign = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
ibuf_sz = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_wr_timer = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_nomerge_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4325 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4322 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4319 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4316 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_sideeffect = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dual_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_samedw_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_write = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_cmd_done = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_data_done = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_nosend = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_sz_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_rdrsp_pend = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_rdrsp_tag = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualhi_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_sz = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_byteen = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
obuf_data = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_0 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_rspageQ_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4302 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4300 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4298 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4296 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_ldfwdtag_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
buf_dualtag_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4331 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4334 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4337 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4340 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4406 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4401 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4396 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4391 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_nonblock_load_valid_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_4956 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_0 <= 32'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_addr_0 <= ibuf_addr;
|
|
end else if (_T_3346) begin
|
|
buf_addr_0 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_0 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4355 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4355 <= buf_write_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4352 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4352 <= buf_write_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4349 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4349 <= buf_write_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4346 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4346 <= buf_write_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (buf_state_en_0) begin
|
|
if (_T_3531) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_0 <= 3'h2;
|
|
end else begin
|
|
buf_state_0 <= 3'h1;
|
|
end
|
|
end else if (_T_3554) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else begin
|
|
buf_state_0 <= 3'h2;
|
|
end
|
|
end else if (_T_3558) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3562) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h3;
|
|
end
|
|
end else if (_T_3592) begin
|
|
if (_T_3596) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3604) begin
|
|
buf_state_0 <= 3'h4;
|
|
end else if (_T_3632) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else if (_T_3677) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else if (_T_3683) begin
|
|
buf_state_0 <= 3'h5;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else if (_T_3695) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_0 <= 3'h0;
|
|
end else begin
|
|
buf_state_0 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_0 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_1 <= 32'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_addr_1 <= ibuf_addr;
|
|
end else if (_T_3355) begin
|
|
buf_addr_1 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_1 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (buf_state_en_1) begin
|
|
if (_T_3722) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_1 <= 3'h2;
|
|
end else begin
|
|
buf_state_1 <= 3'h1;
|
|
end
|
|
end else if (_T_3745) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else begin
|
|
buf_state_1 <= 3'h2;
|
|
end
|
|
end else if (_T_3749) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3562) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h3;
|
|
end
|
|
end else if (_T_3783) begin
|
|
if (_T_3787) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3795) begin
|
|
buf_state_1 <= 3'h4;
|
|
end else if (_T_3823) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else if (_T_3868) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else if (_T_3874) begin
|
|
buf_state_1 <= 3'h5;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else if (_T_3886) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_1 <= 3'h0;
|
|
end else begin
|
|
buf_state_1 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_1 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_2 <= 32'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_addr_2 <= ibuf_addr;
|
|
end else if (_T_3364) begin
|
|
buf_addr_2 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_2 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (buf_state_en_2) begin
|
|
if (_T_3913) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_2 <= 3'h2;
|
|
end else begin
|
|
buf_state_2 <= 3'h1;
|
|
end
|
|
end else if (_T_3936) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else begin
|
|
buf_state_2 <= 3'h2;
|
|
end
|
|
end else if (_T_3940) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_3562) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h3;
|
|
end
|
|
end else if (_T_3974) begin
|
|
if (_T_3978) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_3986) begin
|
|
buf_state_2 <= 3'h4;
|
|
end else if (_T_4014) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else if (_T_4059) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else if (_T_4065) begin
|
|
buf_state_2 <= 3'h5;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else if (_T_4077) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_2 <= 3'h0;
|
|
end else begin
|
|
buf_state_2 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_2 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_addr_3 <= 32'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_addr_3 <= ibuf_addr;
|
|
end else if (_T_3373) begin
|
|
buf_addr_3 <= io_end_addr_r;
|
|
end else begin
|
|
buf_addr_3 <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (buf_state_en_3) begin
|
|
if (_T_4104) begin
|
|
if (io_lsu_bus_clk_en) begin
|
|
buf_state_3 <= 3'h2;
|
|
end else begin
|
|
buf_state_3 <= 3'h1;
|
|
end
|
|
end else if (_T_4127) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else begin
|
|
buf_state_3 <= 3'h2;
|
|
end
|
|
end else if (_T_4131) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_3562) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h3;
|
|
end
|
|
end else if (_T_4165) begin
|
|
if (_T_4169) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_4177) begin
|
|
buf_state_3 <= 3'h4;
|
|
end else if (_T_4205) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else if (_T_4250) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else if (_T_4256) begin
|
|
buf_state_3 <= 3'h5;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else if (_T_4268) begin
|
|
if (io_dec_tlu_force_halt) begin
|
|
buf_state_3 <= 3'h0;
|
|
end else begin
|
|
buf_state_3 <= 3'h6;
|
|
end
|
|
end else begin
|
|
buf_state_3 <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_3 <= 4'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_byteen_3 <= ibuf_byteen_out;
|
|
end else if (_T_3373) begin
|
|
buf_byteen_3 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_3 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_2 <= 4'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_byteen_2 <= ibuf_byteen_out;
|
|
end else if (_T_3364) begin
|
|
buf_byteen_2 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_2 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_1 <= 4'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_byteen_1 <= ibuf_byteen_out;
|
|
end else if (_T_3355) begin
|
|
buf_byteen_1 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_1 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_byteen_0 <= 4'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_byteen_0 <= ibuf_byteen_out;
|
|
end else if (_T_3346) begin
|
|
buf_byteen_0 <= ldst_byteen_hi_r;
|
|
end else begin
|
|
buf_byteen_0 <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_3 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_3 <= {_T_2474,_T_2397};
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1781 <= 2'h0;
|
|
end else if (_T_1780) begin
|
|
if (ibuf_buf_byp) begin
|
|
_T_1781 <= WrPtr0_r;
|
|
end else begin
|
|
_T_1781 <= CmdPtr0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_merge <= 1'h0;
|
|
end else if (_T_1780) begin
|
|
obuf_merge <= obuf_merge_en;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_tag1 <= 2'h0;
|
|
end else if (_T_1780) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_tag1 <= WrPtr1_r;
|
|
end else begin
|
|
obuf_tag1 <= CmdPtr1;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_valid <= 1'h0;
|
|
end else begin
|
|
obuf_valid <= _T_1771 & _T_1772;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_wr_enQ <= 1'h0;
|
|
end else if (io_lsu_busm_clken) begin
|
|
obuf_wr_enQ <= obuf_wr_en;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_addr <= 32'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
if (io_ldst_dual_r) begin
|
|
ibuf_addr <= io_end_addr_r;
|
|
end else begin
|
|
ibuf_addr <= io_lsu_addr_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_write <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_write <= io_lsu_pkt_r_bits_store;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_valid <= 1'h0;
|
|
end else begin
|
|
ibuf_valid <= _T_1005 & _T_1006;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_byteen <= 4'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
if (_T_866) begin
|
|
ibuf_byteen <= _T_881;
|
|
end else if (io_ldst_dual_r) begin
|
|
ibuf_byteen <= ldst_byteen_hi_r;
|
|
end else begin
|
|
ibuf_byteen <= ldst_byteen_lo_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_2 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_2 <= {_T_2372,_T_2295};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_1 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_1 <= {_T_2270,_T_2193};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ageQ_0 <= 4'h0;
|
|
end else begin
|
|
buf_ageQ_0 <= {_T_2168,_T_2091};
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_0 <= 32'h0;
|
|
end else if (buf_data_en_0) begin
|
|
if (_T_3531) begin
|
|
if (_T_3546) begin
|
|
buf_data_0 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_0 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3554) begin
|
|
buf_data_0 <= 32'h0;
|
|
end else if (_T_3558) begin
|
|
if (buf_error_en_0) begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
|
|
end else if (buf_addr_0[2]) begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else if (_T_3592) begin
|
|
if (_T_3670) begin
|
|
if (buf_addr_0[2]) begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_0 <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_1 <= 32'h0;
|
|
end else if (buf_data_en_1) begin
|
|
if (_T_3722) begin
|
|
if (_T_3737) begin
|
|
buf_data_1 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_1 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3745) begin
|
|
buf_data_1 <= 32'h0;
|
|
end else if (_T_3749) begin
|
|
if (buf_error_en_1) begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
|
|
end else if (buf_addr_1[2]) begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else if (_T_3783) begin
|
|
if (_T_3861) begin
|
|
if (buf_addr_1[2]) begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_1 <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_2 <= 32'h0;
|
|
end else if (buf_data_en_2) begin
|
|
if (_T_3913) begin
|
|
if (_T_3928) begin
|
|
buf_data_2 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_2 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_3936) begin
|
|
buf_data_2 <= 32'h0;
|
|
end else if (_T_3940) begin
|
|
if (buf_error_en_2) begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
|
|
end else if (buf_addr_2[2]) begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else if (_T_3974) begin
|
|
if (_T_4052) begin
|
|
if (buf_addr_2[2]) begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_2 <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
buf_data_3 <= 32'h0;
|
|
end else if (buf_data_en_3) begin
|
|
if (_T_4104) begin
|
|
if (_T_4119) begin
|
|
buf_data_3 <= ibuf_data_out;
|
|
end else begin
|
|
buf_data_3 <= store_data_lo_r;
|
|
end
|
|
end else if (_T_4127) begin
|
|
buf_data_3 <= 32'h0;
|
|
end else if (_T_4131) begin
|
|
if (buf_error_en_3) begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
|
|
end else if (buf_addr_3[2]) begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else if (_T_4165) begin
|
|
if (_T_4243) begin
|
|
if (buf_addr_3[2]) begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
|
|
end
|
|
end else begin
|
|
buf_data_3 <= 32'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_data <= 32'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_data <= ibuf_data_in;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_timer <= 3'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_timer <= 3'h0;
|
|
end else if (_T_923) begin
|
|
ibuf_timer <= _T_926;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_sideeffect <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_sideeffect <= io_is_sideeffects_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr1_r <= 2'h0;
|
|
end else if (_T_1853) begin
|
|
WrPtr1_r <= 2'h0;
|
|
end else if (_T_1867) begin
|
|
WrPtr1_r <= 2'h1;
|
|
end else if (_T_1881) begin
|
|
WrPtr1_r <= 2'h2;
|
|
end else begin
|
|
WrPtr1_r <= 2'h3;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr0_r <= 2'h0;
|
|
end else if (_T_1802) begin
|
|
WrPtr0_r <= 2'h0;
|
|
end else if (_T_1813) begin
|
|
WrPtr0_r <= 2'h1;
|
|
end else if (_T_1824) begin
|
|
WrPtr0_r <= 2'h2;
|
|
end else begin
|
|
WrPtr0_r <= 2'h3;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_tag <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
if (!(_T_866)) begin
|
|
if (io_ldst_dual_r) begin
|
|
ibuf_tag <= WrPtr1_r;
|
|
end else begin
|
|
ibuf_tag <= WrPtr0_r;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_dualtag <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_dualtag <= WrPtr0_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_dual <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_dual <= io_ldst_dual_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_samedw <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_samedw <= ldst_samedw_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_nomerge <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_nomerge <= io_no_dword_merge_r;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_unsign <= 1'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_unsign <= io_lsu_pkt_r_bits_unsign;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ibuf_sz <= 2'h0;
|
|
end else if (ibuf_wr_en) begin
|
|
ibuf_sz <= ibuf_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_wr_timer <= 3'h0;
|
|
end else if (io_lsu_busm_clken) begin
|
|
if (obuf_wr_en) begin
|
|
obuf_wr_timer <= 3'h0;
|
|
end else if (_T_1058) begin
|
|
obuf_wr_timer <= _T_1060;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_nomerge_0 <= buf_nomerge_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_nomerge_1 <= buf_nomerge_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_nomerge_2 <= buf_nomerge_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_nomerge_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_nomerge_3 <= buf_nomerge_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4325 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4325 <= buf_sideeffect_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4322 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4322 <= buf_sideeffect_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4319 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4319 <= buf_sideeffect_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4316 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4316 <= buf_sideeffect_in[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_sideeffect <= 1'h0;
|
|
end else if (_T_1780) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_sideeffect <= io_is_sideeffects_r;
|
|
end else begin
|
|
obuf_sideeffect <= _T_1051;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_dual_3 <= buf_dual_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_dual_2 <= buf_dual_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_dual_1 <= buf_dual_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dual_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_dual_0 <= buf_dual_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_samedw_3 <= buf_samedw_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_samedw_2 <= buf_samedw_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_samedw_1 <= buf_samedw_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_samedw_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_samedw_0 <= buf_samedw_in[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_write <= 1'h0;
|
|
end else if (_T_1780) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_write <= io_lsu_pkt_r_bits_store;
|
|
end else begin
|
|
obuf_write <= _T_1202;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_cmd_done <= 1'h0;
|
|
end else if (io_lsu_busm_clken) begin
|
|
obuf_cmd_done <= obuf_cmd_done_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_data_done <= 1'h0;
|
|
end else if (io_lsu_busm_clken) begin
|
|
obuf_data_done <= obuf_data_done_in;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_nosend <= 1'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_nosend <= obuf_nosend_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_addr <= 32'h0;
|
|
end else if (obuf_wr_en) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_addr <= io_lsu_addr_r;
|
|
end else begin
|
|
obuf_addr <= _T_1287;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_0 <= 2'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_sz_0 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_0 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_1 <= 2'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_sz_1 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_1 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_2 <= 2'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_sz_2 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_2 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_sz_3 <= 2'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_sz_3 <= ibuf_sz;
|
|
end else begin
|
|
buf_sz_3 <= ibuf_sz_in;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_rdrsp_pend <= 1'h0;
|
|
end else if (obuf_rdrsp_pend_en) begin
|
|
obuf_rdrsp_pend <= obuf_rdrsp_pend_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_rdrsp_tag <= 3'h0;
|
|
end else if (io_lsu_busm_clken) begin
|
|
if (_T_1330) begin
|
|
obuf_rdrsp_tag <= obuf_tag0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_3 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
buf_dualhi_3 <= buf_dualhi_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_2 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
buf_dualhi_2 <= buf_dualhi_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_1 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
buf_dualhi_1 <= buf_dualhi_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualhi_0 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
buf_dualhi_0 <= buf_dualhi_in[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_sz <= 2'h0;
|
|
end else if (_T_1780) begin
|
|
if (ibuf_buf_byp) begin
|
|
obuf_sz <= ibuf_sz_in;
|
|
end else begin
|
|
obuf_sz <= _T_1300;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_byteen <= 8'h0;
|
|
end else if (_T_1780) begin
|
|
obuf_byteen <= obuf_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
obuf_data <= 64'h0;
|
|
end else if (obuf_wr_en) begin
|
|
obuf_data <= obuf_data_in;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_0 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_0 <= {_T_3144,_T_3133};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_1 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_1 <= {_T_3159,_T_3148};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_2 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_2 <= {_T_3174,_T_3163};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_rspageQ_3 <= 4'h0;
|
|
end else begin
|
|
buf_rspageQ_3 <= {_T_3189,_T_3178};
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4302 <= 1'h0;
|
|
end else if (buf_ldfwd_en_3) begin
|
|
if (_T_4104) begin
|
|
_T_4302 <= 1'h0;
|
|
end else if (_T_4127) begin
|
|
_T_4302 <= 1'h0;
|
|
end else begin
|
|
_T_4302 <= _T_4131;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4300 <= 1'h0;
|
|
end else if (buf_ldfwd_en_2) begin
|
|
if (_T_3913) begin
|
|
_T_4300 <= 1'h0;
|
|
end else if (_T_3936) begin
|
|
_T_4300 <= 1'h0;
|
|
end else begin
|
|
_T_4300 <= _T_3940;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4298 <= 1'h0;
|
|
end else if (buf_ldfwd_en_1) begin
|
|
if (_T_3722) begin
|
|
_T_4298 <= 1'h0;
|
|
end else if (_T_3745) begin
|
|
_T_4298 <= 1'h0;
|
|
end else begin
|
|
_T_4298 <= _T_3749;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4296 <= 1'h0;
|
|
end else if (buf_ldfwd_en_0) begin
|
|
if (_T_3531) begin
|
|
_T_4296 <= 1'h0;
|
|
end else if (_T_3554) begin
|
|
_T_4296 <= 1'h0;
|
|
end else begin
|
|
_T_4296 <= _T_3558;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (buf_ldfwd_en_0) begin
|
|
if (_T_3531) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (_T_3554) begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end else if (_T_3558) begin
|
|
buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_0 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_0 <= 2'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
if (ibuf_drainvec_vld[0]) begin
|
|
buf_dualtag_0 <= ibuf_dualtag;
|
|
end else if (_T_3346) begin
|
|
buf_dualtag_0 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_0 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (buf_ldfwd_en_3) begin
|
|
if (_T_4104) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (_T_4127) begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end else if (_T_4131) begin
|
|
buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_3 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (buf_ldfwd_en_2) begin
|
|
if (_T_3913) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (_T_3936) begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end else if (_T_3940) begin
|
|
buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_2 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (buf_ldfwd_en_1) begin
|
|
if (_T_3722) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (_T_3745) begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end else if (_T_3749) begin
|
|
buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0];
|
|
end else begin
|
|
buf_ldfwdtag_1 <= 2'h0;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_1 <= 2'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
if (ibuf_drainvec_vld[1]) begin
|
|
buf_dualtag_1 <= ibuf_dualtag;
|
|
end else if (_T_3355) begin
|
|
buf_dualtag_1 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_1 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_2 <= 2'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
if (ibuf_drainvec_vld[2]) begin
|
|
buf_dualtag_2 <= ibuf_dualtag;
|
|
end else if (_T_3364) begin
|
|
buf_dualtag_2 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_2 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
buf_dualtag_3 <= 2'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
if (ibuf_drainvec_vld[3]) begin
|
|
buf_dualtag_3 <= ibuf_dualtag;
|
|
end else if (_T_3373) begin
|
|
buf_dualtag_3 <= WrPtr0_r;
|
|
end else begin
|
|
buf_dualtag_3 <= WrPtr1_r;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4331 <= 1'h0;
|
|
end else if (buf_wr_en_0) begin
|
|
_T_4331 <= buf_unsign_in[0];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4334 <= 1'h0;
|
|
end else if (buf_wr_en_1) begin
|
|
_T_4334 <= buf_unsign_in[1];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4337 <= 1'h0;
|
|
end else if (buf_wr_en_2) begin
|
|
_T_4337 <= buf_unsign_in[2];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4340 <= 1'h0;
|
|
end else if (buf_wr_en_3) begin
|
|
_T_4340 <= buf_unsign_in[3];
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4406 <= 1'h0;
|
|
end else begin
|
|
_T_4406 <= _T_4402 & _T_4404;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4401 <= 1'h0;
|
|
end else begin
|
|
_T_4401 <= _T_4397 & _T_4399;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4396 <= 1'h0;
|
|
end else begin
|
|
_T_4396 <= _T_4392 & _T_4394;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4391 <= 1'h0;
|
|
end else begin
|
|
_T_4391 <= _T_4387 & _T_4389;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_nonblock_load_valid_r <= 1'h0;
|
|
end else begin
|
|
lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_4956 <= 1'h0;
|
|
end else begin
|
|
_T_4956 <= _T_4953 & _T_4513;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu_bus_intf(
|
|
input clock,
|
|
input reset,
|
|
output io_tlu_busbuff_lsu_pmu_bus_trxn,
|
|
output io_tlu_busbuff_lsu_pmu_bus_misaligned,
|
|
output io_tlu_busbuff_lsu_pmu_bus_error,
|
|
output io_tlu_busbuff_lsu_pmu_bus_busy,
|
|
input io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
|
|
input io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
|
|
input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
|
|
output io_tlu_busbuff_lsu_imprecise_error_load_any,
|
|
output io_tlu_busbuff_lsu_imprecise_error_store_any,
|
|
output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any,
|
|
input io_lsu_bus_obuf_c1_clken,
|
|
input io_lsu_busm_clken,
|
|
input io_lsu_c1_r_clk,
|
|
input io_lsu_c2_r_clk,
|
|
input io_lsu_bus_ibuf_c1_clk,
|
|
input io_lsu_bus_buf_c1_clk,
|
|
input io_lsu_free_c2_clk,
|
|
input io_active_clk,
|
|
input io_axi_aw_ready,
|
|
output io_axi_aw_valid,
|
|
output [2:0] io_axi_aw_bits_id,
|
|
output [31:0] io_axi_aw_bits_addr,
|
|
output [3:0] io_axi_aw_bits_region,
|
|
output [2:0] io_axi_aw_bits_size,
|
|
output [3:0] io_axi_aw_bits_cache,
|
|
input io_axi_w_ready,
|
|
output io_axi_w_valid,
|
|
output [63:0] io_axi_w_bits_data,
|
|
output [7:0] io_axi_w_bits_strb,
|
|
input io_axi_b_valid,
|
|
input [1:0] io_axi_b_bits_resp,
|
|
input [2:0] io_axi_b_bits_id,
|
|
input io_axi_ar_ready,
|
|
output io_axi_ar_valid,
|
|
output [2:0] io_axi_ar_bits_id,
|
|
output [31:0] io_axi_ar_bits_addr,
|
|
output [3:0] io_axi_ar_bits_region,
|
|
output [2:0] io_axi_ar_bits_size,
|
|
output [3:0] io_axi_ar_bits_cache,
|
|
input io_axi_r_valid,
|
|
input [2:0] io_axi_r_bits_id,
|
|
input [63:0] io_axi_r_bits_data,
|
|
input [1:0] io_axi_r_bits_resp,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input io_lsu_busreq_m,
|
|
input io_lsu_pkt_m_valid,
|
|
input io_lsu_pkt_m_bits_by,
|
|
input io_lsu_pkt_m_bits_half,
|
|
input io_lsu_pkt_m_bits_word,
|
|
input io_lsu_pkt_m_bits_load,
|
|
input io_lsu_pkt_r_valid,
|
|
input io_lsu_pkt_r_bits_by,
|
|
input io_lsu_pkt_r_bits_half,
|
|
input io_lsu_pkt_r_bits_word,
|
|
input io_lsu_pkt_r_bits_load,
|
|
input io_lsu_pkt_r_bits_store,
|
|
input io_lsu_pkt_r_bits_unsign,
|
|
input [31:0] io_lsu_addr_m,
|
|
input [31:0] io_lsu_addr_r,
|
|
input [31:0] io_end_addr_m,
|
|
input [31:0] io_end_addr_r,
|
|
input io_ldst_dual_d,
|
|
input io_ldst_dual_m,
|
|
input io_ldst_dual_r,
|
|
input [31:0] io_store_data_r,
|
|
input io_dec_tlu_force_halt,
|
|
input io_lsu_commit_r,
|
|
input io_is_sideeffects_m,
|
|
input io_flush_m_up,
|
|
input io_flush_r,
|
|
output io_lsu_busreq_r,
|
|
output io_lsu_bus_buffer_pend_any,
|
|
output io_lsu_bus_buffer_full_any,
|
|
output io_lsu_bus_buffer_empty_any,
|
|
output [31:0] io_bus_read_data_m,
|
|
output [31:0] io_lsu_nonblock_load_data,
|
|
output io_dctl_busbuff_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m,
|
|
output io_dctl_busbuff_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r,
|
|
output io_dctl_busbuff_lsu_nonblock_load_data_valid,
|
|
output io_dctl_busbuff_lsu_nonblock_load_data_error,
|
|
output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag,
|
|
input io_lsu_bus_clk_en
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39]
|
|
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_busm_clken; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39]
|
|
wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39]
|
|
wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39]
|
|
wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39]
|
|
wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39]
|
|
wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39]
|
|
wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72]
|
|
wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72]
|
|
wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51]
|
|
wire _T_14 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71]
|
|
wire _T_15 = ~_T_14; // @[lsu_bus_intf.scala 156:53]
|
|
wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_15; // @[lsu_bus_intf.scala 156:51]
|
|
wire _T_17 = ~io_ldst_dual_r; // @[lsu_bus_intf.scala 157:48]
|
|
wire _T_18 = io_lsu_busreq_r & _T_17; // @[lsu_bus_intf.scala 157:46]
|
|
wire _T_19 = _T_18 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:64]
|
|
wire _T_20 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:110]
|
|
wire _T_21 = io_lsu_pkt_m_bits_load | _T_20; // @[lsu_bus_intf.scala 157:108]
|
|
wire _T_26 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:110]
|
|
wire _T_27 = io_lsu_pkt_m_bits_load | _T_26; // @[lsu_bus_intf.scala 158:108]
|
|
wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49]
|
|
wire [6:0] _T_31 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49]
|
|
reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 200:33]
|
|
wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49]
|
|
wire [6:0] _T_34 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49]
|
|
wire [4:0] _T_37 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52]
|
|
wire [62:0] _T_38 = _GEN_2 << _T_37; // @[lsu_bus_intf.scala 162:52]
|
|
wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 160:27]
|
|
wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47]
|
|
wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47]
|
|
wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27]
|
|
wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47]
|
|
wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47]
|
|
wire [63:0] store_data_ext_r = {{1'd0}, _T_38}; // @[lsu_bus_intf.scala 162:27]
|
|
wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46]
|
|
wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46]
|
|
wire _T_47 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51]
|
|
wire _T_48 = _T_47 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76]
|
|
wire _T_49 = _T_48 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97]
|
|
wire ld_addr_rhit_lo_lo = _T_49 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123]
|
|
wire _T_53 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51]
|
|
wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76]
|
|
wire _T_55 = _T_54 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97]
|
|
wire ld_addr_rhit_lo_hi = _T_55 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123]
|
|
wire _T_59 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51]
|
|
wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76]
|
|
wire _T_61 = _T_60 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97]
|
|
wire ld_addr_rhit_hi_lo = _T_61 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123]
|
|
wire _T_65 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51]
|
|
wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76]
|
|
wire _T_67 = _T_66 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97]
|
|
wire ld_addr_rhit_hi_hi = _T_67 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123]
|
|
wire _T_70 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70]
|
|
wire _T_72 = _T_70 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92]
|
|
wire _T_74 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70]
|
|
wire _T_76 = _T_74 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92]
|
|
wire _T_78 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70]
|
|
wire _T_80 = _T_78 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92]
|
|
wire _T_82 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70]
|
|
wire _T_84 = _T_82 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92]
|
|
wire [3:0] ld_byte_rhit_lo_lo = {_T_84,_T_80,_T_76,_T_72}; // @[Cat.scala 29:58]
|
|
wire _T_89 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70]
|
|
wire _T_91 = _T_89 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92]
|
|
wire _T_93 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70]
|
|
wire _T_95 = _T_93 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92]
|
|
wire _T_97 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70]
|
|
wire _T_99 = _T_97 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92]
|
|
wire _T_101 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70]
|
|
wire _T_103 = _T_101 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92]
|
|
wire [3:0] ld_byte_rhit_lo_hi = {_T_103,_T_99,_T_95,_T_91}; // @[Cat.scala 29:58]
|
|
wire _T_108 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70]
|
|
wire _T_110 = _T_108 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92]
|
|
wire _T_112 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70]
|
|
wire _T_114 = _T_112 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92]
|
|
wire _T_116 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70]
|
|
wire _T_118 = _T_116 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92]
|
|
wire _T_120 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70]
|
|
wire _T_122 = _T_120 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92]
|
|
wire [3:0] ld_byte_rhit_hi_lo = {_T_122,_T_118,_T_114,_T_110}; // @[Cat.scala 29:58]
|
|
wire _T_127 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70]
|
|
wire _T_129 = _T_127 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92]
|
|
wire _T_131 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70]
|
|
wire _T_133 = _T_131 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92]
|
|
wire _T_135 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70]
|
|
wire _T_137 = _T_135 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92]
|
|
wire _T_139 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70]
|
|
wire _T_141 = _T_139 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92]
|
|
wire [3:0] ld_byte_rhit_hi_hi = {_T_141,_T_137,_T_133,_T_129}; // @[Cat.scala 29:58]
|
|
wire _T_147 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73]
|
|
wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38]
|
|
wire _T_149 = _T_147 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97]
|
|
wire _T_152 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73]
|
|
wire _T_154 = _T_152 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97]
|
|
wire _T_157 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73]
|
|
wire _T_159 = _T_157 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97]
|
|
wire _T_162 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73]
|
|
wire _T_164 = _T_162 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97]
|
|
wire [3:0] ld_byte_hit_lo = {_T_164,_T_159,_T_154,_T_149}; // @[Cat.scala 29:58]
|
|
wire _T_170 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73]
|
|
wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38]
|
|
wire _T_172 = _T_170 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97]
|
|
wire _T_175 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73]
|
|
wire _T_177 = _T_175 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97]
|
|
wire _T_180 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73]
|
|
wire _T_182 = _T_180 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97]
|
|
wire _T_185 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73]
|
|
wire _T_187 = _T_185 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97]
|
|
wire [3:0] ld_byte_hit_hi = {_T_187,_T_182,_T_177,_T_172}; // @[Cat.scala 29:58]
|
|
wire [3:0] ld_byte_rhit_lo = {_T_162,_T_157,_T_152,_T_147}; // @[Cat.scala 29:58]
|
|
wire [3:0] ld_byte_rhit_hi = {_T_185,_T_180,_T_175,_T_170}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_225 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_226 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_227 = _T_225 | _T_226; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_233 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_234 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_235 = _T_233 | _T_234; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_241 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_242 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_243 = _T_241 | _T_242; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_249 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_250 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_251 = _T_249 | _T_250; // @[Mux.scala 27:72]
|
|
wire [31:0] ld_fwddata_rpipe_lo = {_T_251,_T_243,_T_235,_T_227}; // @[Cat.scala 29:58]
|
|
wire [7:0] _T_260 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_261 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_262 = _T_260 | _T_261; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_268 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_269 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_270 = _T_268 | _T_269; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_276 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_277 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_278 = _T_276 | _T_277; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_284 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_285 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
|
wire [7:0] _T_286 = _T_284 | _T_285; // @[Mux.scala 27:72]
|
|
wire [31:0] ld_fwddata_rpipe_hi = {_T_286,_T_278,_T_270,_T_262}; // @[Cat.scala 29:58]
|
|
wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38]
|
|
wire [7:0] _T_294 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54]
|
|
wire [7:0] _T_298 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54]
|
|
wire [7:0] _T_302 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54]
|
|
wire [7:0] _T_306 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54]
|
|
wire [31:0] _T_309 = {_T_306,_T_302,_T_298,_T_294}; // @[Cat.scala 29:58]
|
|
wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38]
|
|
wire [7:0] _T_313 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54]
|
|
wire [7:0] _T_317 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54]
|
|
wire [7:0] _T_321 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54]
|
|
wire [7:0] _T_325 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54]
|
|
wire [31:0] _T_328 = {_T_325,_T_321,_T_317,_T_313}; // @[Cat.scala 29:58]
|
|
wire _T_331 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72]
|
|
wire _T_332 = ld_byte_hit_lo[0] | _T_331; // @[lsu_bus_intf.scala 188:70]
|
|
wire _T_335 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72]
|
|
wire _T_336 = ld_byte_hit_lo[1] | _T_335; // @[lsu_bus_intf.scala 188:70]
|
|
wire _T_339 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72]
|
|
wire _T_340 = ld_byte_hit_lo[2] | _T_339; // @[lsu_bus_intf.scala 188:70]
|
|
wire _T_343 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72]
|
|
wire _T_344 = ld_byte_hit_lo[3] | _T_343; // @[lsu_bus_intf.scala 188:70]
|
|
wire _T_345 = _T_332 & _T_336; // @[lsu_bus_intf.scala 188:111]
|
|
wire _T_346 = _T_345 & _T_340; // @[lsu_bus_intf.scala 188:111]
|
|
wire ld_full_hit_lo_m = _T_346 & _T_344; // @[lsu_bus_intf.scala 188:111]
|
|
wire _T_350 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72]
|
|
wire _T_351 = ld_byte_hit_hi[0] | _T_350; // @[lsu_bus_intf.scala 189:70]
|
|
wire _T_354 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72]
|
|
wire _T_355 = ld_byte_hit_hi[1] | _T_354; // @[lsu_bus_intf.scala 189:70]
|
|
wire _T_358 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72]
|
|
wire _T_359 = ld_byte_hit_hi[2] | _T_358; // @[lsu_bus_intf.scala 189:70]
|
|
wire _T_362 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72]
|
|
wire _T_363 = ld_byte_hit_hi[3] | _T_362; // @[lsu_bus_intf.scala 189:70]
|
|
wire _T_364 = _T_351 & _T_355; // @[lsu_bus_intf.scala 189:111]
|
|
wire _T_365 = _T_364 & _T_359; // @[lsu_bus_intf.scala 189:111]
|
|
wire ld_full_hit_hi_m = _T_365 & _T_363; // @[lsu_bus_intf.scala 189:111]
|
|
wire _T_367 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47]
|
|
wire _T_368 = _T_367 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66]
|
|
wire _T_369 = _T_368 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84]
|
|
wire _T_370 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111]
|
|
wire [63:0] ld_fwddata_hi = {{32'd0}, _T_328}; // @[lsu_bus_intf.scala 187:27]
|
|
wire [63:0] ld_fwddata_lo = {{32'd0}, _T_309}; // @[lsu_bus_intf.scala 186:27]
|
|
wire [63:0] _T_374 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58]
|
|
wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83]
|
|
wire [5:0] _T_376 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83]
|
|
wire [63:0] ld_fwddata_m = _T_374 >> _T_376; // @[lsu_bus_intf.scala 191:76]
|
|
reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32]
|
|
reg is_sideeffects_r; // @[lsu_bus_intf.scala 199:33]
|
|
lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39]
|
|
.clock(bus_buffer_clock),
|
|
.reset(bus_buffer_reset),
|
|
.io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn),
|
|
.io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned),
|
|
.io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error),
|
|
.io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy),
|
|
.io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
|
|
.io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
|
|
.io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
|
|
.io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any),
|
|
.io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any),
|
|
.io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any),
|
|
.io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag),
|
|
.io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt),
|
|
.io_lsu_bus_obuf_c1_clken(bus_buffer_io_lsu_bus_obuf_c1_clken),
|
|
.io_lsu_busm_clken(bus_buffer_io_lsu_busm_clken),
|
|
.io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk),
|
|
.io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d),
|
|
.io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_addr_m(bus_buffer_io_lsu_addr_m),
|
|
.io_end_addr_m(bus_buffer_io_end_addr_m),
|
|
.io_lsu_addr_r(bus_buffer_io_lsu_addr_r),
|
|
.io_end_addr_r(bus_buffer_io_end_addr_r),
|
|
.io_store_data_r(bus_buffer_io_store_data_r),
|
|
.io_no_word_merge_r(bus_buffer_io_no_word_merge_r),
|
|
.io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r),
|
|
.io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m),
|
|
.io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m),
|
|
.io_flush_m_up(bus_buffer_io_flush_m_up),
|
|
.io_flush_r(bus_buffer_io_flush_r),
|
|
.io_lsu_commit_r(bus_buffer_io_lsu_commit_r),
|
|
.io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r),
|
|
.io_ldst_dual_d(bus_buffer_io_ldst_dual_d),
|
|
.io_ldst_dual_m(bus_buffer_io_ldst_dual_m),
|
|
.io_ldst_dual_r(bus_buffer_io_ldst_dual_r),
|
|
.io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m),
|
|
.io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready),
|
|
.io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid),
|
|
.io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id),
|
|
.io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr),
|
|
.io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region),
|
|
.io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size),
|
|
.io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache),
|
|
.io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready),
|
|
.io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid),
|
|
.io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data),
|
|
.io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb),
|
|
.io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready),
|
|
.io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid),
|
|
.io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp),
|
|
.io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id),
|
|
.io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready),
|
|
.io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid),
|
|
.io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id),
|
|
.io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr),
|
|
.io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region),
|
|
.io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size),
|
|
.io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache),
|
|
.io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready),
|
|
.io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid),
|
|
.io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id),
|
|
.io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data),
|
|
.io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp),
|
|
.io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en),
|
|
.io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q),
|
|
.io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any),
|
|
.io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any),
|
|
.io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo),
|
|
.io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi),
|
|
.io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo),
|
|
.io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi),
|
|
.io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data)
|
|
);
|
|
assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18]
|
|
assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 131:38]
|
|
assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38]
|
|
assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38]
|
|
assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38]
|
|
assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38]
|
|
assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27]
|
|
assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 133:38]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19]
|
|
assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19]
|
|
assign bus_buffer_clock = clock;
|
|
assign bus_buffer_reset = reset;
|
|
assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18]
|
|
assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18]
|
|
assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18]
|
|
assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51]
|
|
assign bus_buffer_io_lsu_bus_obuf_c1_clken = io_lsu_bus_obuf_c1_clken; // @[lsu_bus_intf.scala 105:51]
|
|
assign bus_buffer_io_lsu_busm_clken = io_lsu_busm_clken; // @[lsu_bus_intf.scala 106:51]
|
|
assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51]
|
|
assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51]
|
|
assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51]
|
|
assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51]
|
|
assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51]
|
|
assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27]
|
|
assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27]
|
|
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:38]
|
|
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:38]
|
|
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:38]
|
|
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:38]
|
|
assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:38]
|
|
assign bus_buffer_io_no_word_merge_r = _T_19 & _T_21; // @[lsu_bus_intf.scala 144:51]
|
|
assign bus_buffer_io_no_dword_merge_r = _T_19 & _T_27; // @[lsu_bus_intf.scala 145:51]
|
|
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:38]
|
|
assign bus_buffer_io_ld_full_hit_m = _T_369 & _T_370; // @[lsu_bus_intf.scala 151:51]
|
|
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:38]
|
|
assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:38]
|
|
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:38]
|
|
assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51]
|
|
assign bus_buffer_io_ldst_dual_d = io_ldst_dual_d; // @[lsu_bus_intf.scala 147:51]
|
|
assign bus_buffer_io_ldst_dual_m = io_ldst_dual_m; // @[lsu_bus_intf.scala 148:51]
|
|
assign bus_buffer_io_ldst_dual_r = io_ldst_dual_r; // @[lsu_bus_intf.scala 149:51]
|
|
assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_31}; // @[lsu_bus_intf.scala 150:51]
|
|
assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:38]
|
|
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:38]
|
|
assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
ldst_byteen_r = _RAND_0[3:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
lsu_bus_clk_en_q = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
is_sideeffects_r = _RAND_2[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
ldst_byteen_r = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_bus_clk_en_q = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
is_sideeffects_r = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
ldst_byteen_r <= 4'h0;
|
|
end else begin
|
|
ldst_byteen_r <= _T_6 | _T_5;
|
|
end
|
|
end
|
|
always @(posedge io_active_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_bus_clk_en_q <= 1'h0;
|
|
end else begin
|
|
lsu_bus_clk_en_q <= io_lsu_bus_clk_en;
|
|
end
|
|
end
|
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
is_sideeffects_r <= 1'h0;
|
|
end else begin
|
|
is_sideeffects_r <= io_is_sideeffects_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module lsu(
|
|
input clock,
|
|
input reset,
|
|
input io_clk_override,
|
|
input io_lsu_dma_dma_lsc_ctl_dma_dccm_req,
|
|
input [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr,
|
|
input [2:0] io_lsu_dma_dma_lsc_ctl_dma_mem_sz,
|
|
input io_lsu_dma_dma_lsc_ctl_dma_mem_write,
|
|
input [63:0] io_lsu_dma_dma_lsc_ctl_dma_mem_wdata,
|
|
input [31:0] io_lsu_dma_dma_dccm_ctl_dma_mem_addr,
|
|
input [63:0] io_lsu_dma_dma_dccm_ctl_dma_mem_wdata,
|
|
output io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
|
|
output io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error,
|
|
output [2:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag,
|
|
output [63:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata,
|
|
output io_lsu_dma_dccm_ready,
|
|
input [2:0] io_lsu_dma_dma_mem_tag,
|
|
output io_lsu_pic_picm_wren,
|
|
output io_lsu_pic_picm_rden,
|
|
output io_lsu_pic_picm_mken,
|
|
output [31:0] io_lsu_pic_picm_rdaddr,
|
|
output [31:0] io_lsu_pic_picm_wraddr,
|
|
output [31:0] io_lsu_pic_picm_wr_data,
|
|
input [31:0] io_lsu_pic_picm_rd_data,
|
|
input [31:0] io_lsu_exu_exu_lsu_rs1_d,
|
|
input [31:0] io_lsu_exu_exu_lsu_rs2_d,
|
|
output [31:0] io_lsu_exu_lsu_result_m,
|
|
output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
|
|
output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
|
|
output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
|
|
output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
|
|
input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable,
|
|
input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable,
|
|
input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
|
|
output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any,
|
|
output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any,
|
|
output [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any,
|
|
output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m,
|
|
output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m,
|
|
output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r,
|
|
output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r,
|
|
output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid,
|
|
output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error,
|
|
output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output io_lsu_tlu_lsu_pmu_load_external_m,
|
|
output io_lsu_tlu_lsu_pmu_store_external_m,
|
|
input io_axi_aw_ready,
|
|
output io_axi_aw_valid,
|
|
output [2:0] io_axi_aw_bits_id,
|
|
output [31:0] io_axi_aw_bits_addr,
|
|
output [3:0] io_axi_aw_bits_region,
|
|
output [2:0] io_axi_aw_bits_size,
|
|
output [3:0] io_axi_aw_bits_cache,
|
|
input io_axi_w_ready,
|
|
output io_axi_w_valid,
|
|
output [63:0] io_axi_w_bits_data,
|
|
output [7:0] io_axi_w_bits_strb,
|
|
input io_axi_b_valid,
|
|
input [1:0] io_axi_b_bits_resp,
|
|
input [2:0] io_axi_b_bits_id,
|
|
input io_axi_ar_ready,
|
|
output io_axi_ar_valid,
|
|
output [2:0] io_axi_ar_bits_id,
|
|
output [31:0] io_axi_ar_bits_addr,
|
|
output [3:0] io_axi_ar_bits_region,
|
|
output [2:0] io_axi_ar_bits_size,
|
|
output [3:0] io_axi_ar_bits_cache,
|
|
input io_axi_r_valid,
|
|
input [2:0] io_axi_r_bits_id,
|
|
input [63:0] io_axi_r_bits_data,
|
|
input [1:0] io_axi_r_bits_resp,
|
|
input io_dec_tlu_flush_lower_r,
|
|
input io_dec_tlu_i0_kill_writeb_r,
|
|
input io_dec_tlu_force_halt,
|
|
input io_dec_tlu_core_ecc_disable,
|
|
input [11:0] io_dec_lsu_offset_d,
|
|
input io_lsu_p_valid,
|
|
input io_lsu_p_bits_fast_int,
|
|
input io_lsu_p_bits_by,
|
|
input io_lsu_p_bits_half,
|
|
input io_lsu_p_bits_word,
|
|
input io_lsu_p_bits_load,
|
|
input io_lsu_p_bits_store,
|
|
input io_lsu_p_bits_unsign,
|
|
input io_lsu_p_bits_store_data_bypass_d,
|
|
input io_lsu_p_bits_load_ldst_bypass_d,
|
|
input io_trigger_pkt_any_0_select,
|
|
input io_trigger_pkt_any_0_match_pkt,
|
|
input io_trigger_pkt_any_0_store,
|
|
input io_trigger_pkt_any_0_load,
|
|
input io_trigger_pkt_any_0_m,
|
|
input [31:0] io_trigger_pkt_any_0_tdata2,
|
|
input io_trigger_pkt_any_1_select,
|
|
input io_trigger_pkt_any_1_match_pkt,
|
|
input io_trigger_pkt_any_1_store,
|
|
input io_trigger_pkt_any_1_load,
|
|
input io_trigger_pkt_any_1_m,
|
|
input [31:0] io_trigger_pkt_any_1_tdata2,
|
|
input io_trigger_pkt_any_2_select,
|
|
input io_trigger_pkt_any_2_match_pkt,
|
|
input io_trigger_pkt_any_2_store,
|
|
input io_trigger_pkt_any_2_load,
|
|
input io_trigger_pkt_any_2_m,
|
|
input [31:0] io_trigger_pkt_any_2_tdata2,
|
|
input io_trigger_pkt_any_3_select,
|
|
input io_trigger_pkt_any_3_match_pkt,
|
|
input io_trigger_pkt_any_3_store,
|
|
input io_trigger_pkt_any_3_load,
|
|
input io_trigger_pkt_any_3_m,
|
|
input [31:0] io_trigger_pkt_any_3_tdata2,
|
|
input io_dec_lsu_valid_raw_d,
|
|
input [31:0] io_dec_tlu_mrac_ff,
|
|
output [31:0] io_lsu_result_corr_r,
|
|
output io_lsu_load_stall_any,
|
|
output io_lsu_store_stall_any,
|
|
output io_lsu_fastint_stall_any,
|
|
output io_lsu_idle_any,
|
|
output [30:0] io_lsu_fir_addr,
|
|
output [1:0] io_lsu_fir_error,
|
|
output io_lsu_single_ecc_error_incr,
|
|
output io_lsu_error_pkt_r_valid,
|
|
output io_lsu_error_pkt_r_bits_single_ecc_error,
|
|
output io_lsu_error_pkt_r_bits_inst_type,
|
|
output io_lsu_error_pkt_r_bits_exc_type,
|
|
output [3:0] io_lsu_error_pkt_r_bits_mscause,
|
|
output [31:0] io_lsu_error_pkt_r_bits_addr,
|
|
output io_lsu_pmu_misaligned_m,
|
|
output [3:0] io_lsu_trigger_match_m,
|
|
input io_lsu_bus_clk_en,
|
|
input io_active_clk,
|
|
output [31:0] io_lsu_nonblock_load_data
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire lsu_lsc_ctl_clock; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_reset; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_clk_override; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_flush_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_ldst_dual_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_ldst_dual_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_ldst_dual_r; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 72:30]
|
|
wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 72:30]
|
|
wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 72:30]
|
|
wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 72:30]
|
|
wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 72:30]
|
|
wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 72:30]
|
|
wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 72:30]
|
|
wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 72:30]
|
|
wire lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 72:30]
|
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 72:30]
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wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 72:30]
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wire dccm_ctl_clock; // @[lsu.scala 76:30]
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wire dccm_ctl_reset; // @[lsu.scala 76:30]
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wire dccm_ctl_io_clk_override; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 76:30]
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wire dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_commit_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_ldst_dual_m; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 76:30]
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wire dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 76:30]
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wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 76:30]
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|
wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 76:30]
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wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 76:30]
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|
wire dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 76:30]
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|
wire dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 76:30]
|
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wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 76:30]
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|
wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 76:30]
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|
wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 76:30]
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|
wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 76:30]
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|
wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 76:30]
|
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wire dccm_ctl_io_dma_pic_wen; // @[lsu.scala 76:30]
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wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 76:30]
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|
wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 76:30]
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|
wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 76:30]
|
|
wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 76:30]
|
|
wire dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 76:30]
|
|
wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 76:30]
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|
wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 76:30]
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wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 76:30]
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|
wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 76:30]
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wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 76:30]
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wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 76:30]
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wire dccm_ctl_io_dccm_wren; // @[lsu.scala 76:30]
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|
wire dccm_ctl_io_dccm_rden; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 76:30]
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wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 76:30]
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wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 76:30]
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wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 76:30]
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wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 76:30]
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wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 76:30]
|
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wire dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 76:30]
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wire dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 76:30]
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wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 76:30]
|
|
wire stbuf_clock; // @[lsu.scala 77:30]
|
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wire stbuf_reset; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_free_c2_clk; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 77:30]
|
|
wire stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_commit_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_ldst_dual_d; // @[lsu.scala 77:30]
|
|
wire stbuf_io_ldst_dual_m; // @[lsu.scala 77:30]
|
|
wire stbuf_io_ldst_dual_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_addr_in_dccm_m; // @[lsu.scala 77:30]
|
|
wire stbuf_io_addr_in_dccm_r; // @[lsu.scala 77:30]
|
|
wire stbuf_io_stbuf_reqvld_any; // @[lsu.scala 77:30]
|
|
wire stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 77:30]
|
|
wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 77:30]
|
|
wire stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 77:30]
|
|
wire stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 77:30]
|
|
wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 77:30]
|
|
wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 77:30]
|
|
wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 77:30]
|
|
wire ecc_clock; // @[lsu.scala 78:30]
|
|
wire ecc_reset; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_c2_r_clk; // @[lsu.scala 78:30]
|
|
wire ecc_io_clk_override; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_pkt_m_valid; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_pkt_m_bits_load; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_pkt_m_bits_store; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_pkt_m_bits_dma; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 78:30]
|
|
wire ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 78:30]
|
|
wire [15:0] ecc_io_lsu_addr_m; // @[lsu.scala 78:30]
|
|
wire [15:0] ecc_io_end_addr_m; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_dccm_rdata_hi_m; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_dccm_rdata_lo_m; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[lsu.scala 78:30]
|
|
wire ecc_io_ld_single_ecc_error_r; // @[lsu.scala 78:30]
|
|
wire ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_dccm_rden_m; // @[lsu.scala 78:30]
|
|
wire ecc_io_addr_in_dccm_m; // @[lsu.scala 78:30]
|
|
wire ecc_io_dma_dccm_wen; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_hi_m; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_lo_m; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 78:30]
|
|
wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 78:30]
|
|
wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 78:30]
|
|
wire ecc_io_single_ecc_error_hi_r; // @[lsu.scala 78:30]
|
|
wire ecc_io_single_ecc_error_lo_r; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 78:30]
|
|
wire ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 78:30]
|
|
wire trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_0_m; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_1_m; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_2_m; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 79:30]
|
|
wire trigger_io_trigger_pkt_any_3_m; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_valid; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 79:30]
|
|
wire trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 79:30]
|
|
wire [31:0] trigger_io_store_data_m; // @[lsu.scala 79:30]
|
|
wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 79:30]
|
|
wire clkdomain_clock; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_clk_override; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_busreq_r; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_busm_clken; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 80:30]
|
|
wire clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 80:30]
|
|
wire bus_intf_clock; // @[lsu.scala 81:30]
|
|
wire bus_intf_reset; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_busm_clken; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_active_clk; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_aw_ready; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_aw_valid; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 81:30]
|
|
wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 81:30]
|
|
wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_w_ready; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_w_valid; // @[lsu.scala 81:30]
|
|
wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 81:30]
|
|
wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_b_valid; // @[lsu.scala 81:30]
|
|
wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_ar_ready; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_ar_valid; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 81:30]
|
|
wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 81:30]
|
|
wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_axi_r_valid; // @[lsu.scala 81:30]
|
|
wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 81:30]
|
|
wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 81:30]
|
|
wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_busreq_m; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_ldst_dual_d; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_ldst_dual_m; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_ldst_dual_r; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_commit_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_is_sideeffects_m; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_flush_m_up; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_flush_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_busreq_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 81:30]
|
|
wire [31:0] bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 81:30]
|
|
wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 81:30]
|
|
wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 81:30]
|
|
wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 81:30]
|
|
wire bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 81:30]
|
|
wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 87:60]
|
|
wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 94:62]
|
|
wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 94:60]
|
|
wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 94:130]
|
|
wire _T_6 = _T_4 & _T_5; // @[lsu.scala 94:97]
|
|
wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 94:162]
|
|
wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 95:55]
|
|
wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 95:73]
|
|
wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 96:65]
|
|
wire _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 96:104]
|
|
wire [5:0] _T_15 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
|
wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 98:67]
|
|
wire _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 109:130]
|
|
wire _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 109:128]
|
|
wire _T_23 = _T_4 | _T_22; // @[lsu.scala 109:94]
|
|
wire _T_24 = ~_T_23; // @[lsu.scala 109:22]
|
|
wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 112:60]
|
|
wire _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 112:98]
|
|
wire _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 112:132]
|
|
wire _T_33 = _T_31 & _T_32; // @[lsu.scala 112:130]
|
|
wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_r_bits_by | lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 112:216]
|
|
wire _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 112:256]
|
|
wire _T_37 = _T_35 & _T_36; // @[lsu.scala 112:254]
|
|
wire _T_38 = _T_21 | _T_37; // @[lsu.scala 112:179]
|
|
wire _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 114:92]
|
|
wire _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:132]
|
|
wire _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 116:54]
|
|
wire _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 116:168]
|
|
wire _T_46 = _T_44 & _T_45; // @[lsu.scala 116:166]
|
|
wire _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 116:182]
|
|
wire _T_48 = _T_46 & _T_47; // @[lsu.scala 116:180]
|
|
wire _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 116:210]
|
|
wire _T_51 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 120:112]
|
|
wire _T_53 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 120:215]
|
|
wire _T_54 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_53; // @[lsu.scala 120:182]
|
|
wire _T_55 = _T_51 | _T_54; // @[lsu.scala 120:144]
|
|
wire _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 121:73]
|
|
wire _T_59 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 122:73]
|
|
reg _T_66; // @[lsu.scala 155:96]
|
|
reg _T_70; // @[lsu.scala 156:96]
|
|
wire _T_76 = lsu_lsc_ctl_io_addr_external_m & lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 331:119]
|
|
wire [31:0] _T_78 = _T_76 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
wire lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 346:31]
|
|
wire [31:0] _T_81 = lsu_busreq_r ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
|
reg [2:0] dma_mem_tag_m; // @[lsu.scala 350:67]
|
|
reg lsu_raw_fwd_hi_r; // @[lsu.scala 351:67]
|
|
reg lsu_raw_fwd_lo_r; // @[lsu.scala 352:67]
|
|
lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 72:30]
|
|
.clock(lsu_lsc_ctl_clock),
|
|
.reset(lsu_lsc_ctl_reset),
|
|
.io_clk_override(lsu_lsc_ctl_io_clk_override),
|
|
.io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk),
|
|
.io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk),
|
|
.io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk),
|
|
.io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r),
|
|
.io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r),
|
|
.io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r),
|
|
.io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m),
|
|
.io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m),
|
|
.io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m),
|
|
.io_flush_m_up(lsu_lsc_ctl_io_flush_m_up),
|
|
.io_flush_r(lsu_lsc_ctl_io_flush_r),
|
|
.io_ldst_dual_d(lsu_lsc_ctl_io_ldst_dual_d),
|
|
.io_ldst_dual_m(lsu_lsc_ctl_io_ldst_dual_m),
|
|
.io_ldst_dual_r(lsu_lsc_ctl_io_ldst_dual_r),
|
|
.io_lsu_exu_exu_lsu_rs1_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d),
|
|
.io_lsu_exu_exu_lsu_rs2_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d),
|
|
.io_lsu_exu_lsu_result_m(lsu_lsc_ctl_io_lsu_exu_lsu_result_m),
|
|
.io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(lsu_lsc_ctl_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(lsu_lsc_ctl_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(lsu_lsc_ctl_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(lsu_lsc_ctl_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(lsu_lsc_ctl_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(lsu_lsc_ctl_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(lsu_lsc_ctl_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d),
|
|
.io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d),
|
|
.io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m),
|
|
.io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m),
|
|
.io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r),
|
|
.io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d),
|
|
.io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m),
|
|
.io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r),
|
|
.io_end_addr_d(lsu_lsc_ctl_io_end_addr_d),
|
|
.io_end_addr_m(lsu_lsc_ctl_io_end_addr_m),
|
|
.io_end_addr_r(lsu_lsc_ctl_io_end_addr_r),
|
|
.io_store_data_m(lsu_lsc_ctl_io_store_data_m),
|
|
.io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff),
|
|
.io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m),
|
|
.io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m),
|
|
.io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r),
|
|
.io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr),
|
|
.io_lsu_error_pkt_r_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error),
|
|
.io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d),
|
|
.io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r),
|
|
.io_addr_in_pic_d(lsu_lsc_ctl_io_addr_in_pic_d),
|
|
.io_addr_in_pic_m(lsu_lsc_ctl_io_addr_in_pic_m),
|
|
.io_addr_in_pic_r(lsu_lsc_ctl_io_addr_in_pic_r),
|
|
.io_addr_external_m(lsu_lsc_ctl_io_addr_external_m),
|
|
.io_dma_lsc_ctl_dma_dccm_req(lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req),
|
|
.io_dma_lsc_ctl_dma_mem_addr(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr),
|
|
.io_dma_lsc_ctl_dma_mem_sz(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz),
|
|
.io_dma_lsc_ctl_dma_mem_write(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write),
|
|
.io_dma_lsc_ctl_dma_mem_wdata(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata),
|
|
.io_lsu_pkt_d_valid(lsu_lsc_ctl_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int),
|
|
.io_lsu_pkt_d_bits_by(lsu_lsc_ctl_io_lsu_pkt_d_bits_by),
|
|
.io_lsu_pkt_d_bits_half(lsu_lsc_ctl_io_lsu_pkt_d_bits_half),
|
|
.io_lsu_pkt_d_bits_word(lsu_lsc_ctl_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_dword(lsu_lsc_ctl_io_lsu_pkt_d_bits_dword),
|
|
.io_lsu_pkt_d_bits_load(lsu_lsc_ctl_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(lsu_lsc_ctl_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign),
|
|
.io_lsu_pkt_d_bits_dma(lsu_lsc_ctl_io_lsu_pkt_d_bits_dma),
|
|
.io_lsu_pkt_d_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d),
|
|
.io_lsu_pkt_d_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d),
|
|
.io_lsu_pkt_d_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m),
|
|
.io_lsu_pkt_m_valid(lsu_lsc_ctl_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int),
|
|
.io_lsu_pkt_m_bits_by(lsu_lsc_ctl_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(lsu_lsc_ctl_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(lsu_lsc_ctl_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_dword(lsu_lsc_ctl_io_lsu_pkt_m_bits_dword),
|
|
.io_lsu_pkt_m_bits_load(lsu_lsc_ctl_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(lsu_lsc_ctl_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign),
|
|
.io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m),
|
|
.io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_dword(lsu_lsc_ctl_io_lsu_pkt_r_bits_dword),
|
|
.io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma)
|
|
);
|
|
lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 76:30]
|
|
.clock(dccm_ctl_clock),
|
|
.reset(dccm_ctl_reset),
|
|
.io_clk_override(dccm_ctl_io_clk_override),
|
|
.io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk),
|
|
.io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk),
|
|
.io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk),
|
|
.io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid),
|
|
.io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word),
|
|
.io_lsu_pkt_d_bits_dword(dccm_ctl_io_lsu_pkt_d_bits_dword),
|
|
.io_lsu_pkt_d_bits_load(dccm_ctl_io_lsu_pkt_d_bits_load),
|
|
.io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store),
|
|
.io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma),
|
|
.io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(dccm_ctl_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(dccm_ctl_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(dccm_ctl_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(dccm_ctl_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(dccm_ctl_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_dma(dccm_ctl_io_lsu_pkt_r_bits_dma),
|
|
.io_addr_in_dccm_d(dccm_ctl_io_addr_in_dccm_d),
|
|
.io_addr_in_dccm_m(dccm_ctl_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(dccm_ctl_io_addr_in_dccm_r),
|
|
.io_addr_in_pic_d(dccm_ctl_io_addr_in_pic_d),
|
|
.io_addr_in_pic_m(dccm_ctl_io_addr_in_pic_m),
|
|
.io_addr_in_pic_r(dccm_ctl_io_addr_in_pic_r),
|
|
.io_lsu_raw_fwd_lo_r(dccm_ctl_io_lsu_raw_fwd_lo_r),
|
|
.io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r),
|
|
.io_lsu_commit_r(dccm_ctl_io_lsu_commit_r),
|
|
.io_ldst_dual_m(dccm_ctl_io_ldst_dual_m),
|
|
.io_lsu_addr_d(dccm_ctl_io_lsu_addr_d),
|
|
.io_lsu_addr_m(dccm_ctl_io_lsu_addr_m),
|
|
.io_lsu_addr_r(dccm_ctl_io_lsu_addr_r),
|
|
.io_end_addr_d(dccm_ctl_io_end_addr_d),
|
|
.io_end_addr_m(dccm_ctl_io_end_addr_m),
|
|
.io_end_addr_r(dccm_ctl_io_end_addr_r),
|
|
.io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any),
|
|
.io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any),
|
|
.io_stbuf_data_any(dccm_ctl_io_stbuf_data_any),
|
|
.io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any),
|
|
.io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m),
|
|
.io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m),
|
|
.io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m),
|
|
.io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m),
|
|
.io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r),
|
|
.io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r),
|
|
.io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r),
|
|
.io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r),
|
|
.io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff),
|
|
.io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff),
|
|
.io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff),
|
|
.io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff),
|
|
.io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m),
|
|
.io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m),
|
|
.io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m),
|
|
.io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m),
|
|
.io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m),
|
|
.io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m),
|
|
.io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m),
|
|
.io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m),
|
|
.io_store_data_m(dccm_ctl_io_store_data_m),
|
|
.io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen),
|
|
.io_dma_pic_wen(dccm_ctl_io_dma_pic_wen),
|
|
.io_dma_mem_tag_m(dccm_ctl_io_dma_mem_tag_m),
|
|
.io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo),
|
|
.io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi),
|
|
.io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi),
|
|
.io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo),
|
|
.io_store_data_hi_r(dccm_ctl_io_store_data_hi_r),
|
|
.io_store_data_lo_r(dccm_ctl_io_store_data_lo_r),
|
|
.io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r),
|
|
.io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r),
|
|
.io_store_data_r(dccm_ctl_io_store_data_r),
|
|
.io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r),
|
|
.io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff),
|
|
.io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m),
|
|
.io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any),
|
|
.io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m),
|
|
.io_dma_dccm_ctl_dma_mem_addr(dccm_ctl_io_dma_dccm_ctl_dma_mem_addr),
|
|
.io_dma_dccm_ctl_dma_mem_wdata(dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata),
|
|
.io_dma_dccm_ctl_dccm_dma_rvalid(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid),
|
|
.io_dma_dccm_ctl_dccm_dma_ecc_error(dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error),
|
|
.io_dma_dccm_ctl_dccm_dma_rtag(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag),
|
|
.io_dma_dccm_ctl_dccm_dma_rdata(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata),
|
|
.io_dccm_wren(dccm_ctl_io_dccm_wren),
|
|
.io_dccm_rden(dccm_ctl_io_dccm_rden),
|
|
.io_dccm_wr_addr_lo(dccm_ctl_io_dccm_wr_addr_lo),
|
|
.io_dccm_wr_addr_hi(dccm_ctl_io_dccm_wr_addr_hi),
|
|
.io_dccm_rd_addr_lo(dccm_ctl_io_dccm_rd_addr_lo),
|
|
.io_dccm_rd_addr_hi(dccm_ctl_io_dccm_rd_addr_hi),
|
|
.io_dccm_wr_data_lo(dccm_ctl_io_dccm_wr_data_lo),
|
|
.io_dccm_wr_data_hi(dccm_ctl_io_dccm_wr_data_hi),
|
|
.io_dccm_rd_data_lo(dccm_ctl_io_dccm_rd_data_lo),
|
|
.io_dccm_rd_data_hi(dccm_ctl_io_dccm_rd_data_hi),
|
|
.io_lsu_pic_picm_wren(dccm_ctl_io_lsu_pic_picm_wren),
|
|
.io_lsu_pic_picm_rden(dccm_ctl_io_lsu_pic_picm_rden),
|
|
.io_lsu_pic_picm_mken(dccm_ctl_io_lsu_pic_picm_mken),
|
|
.io_lsu_pic_picm_rdaddr(dccm_ctl_io_lsu_pic_picm_rdaddr),
|
|
.io_lsu_pic_picm_wraddr(dccm_ctl_io_lsu_pic_picm_wraddr),
|
|
.io_lsu_pic_picm_wr_data(dccm_ctl_io_lsu_pic_picm_wr_data),
|
|
.io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data)
|
|
);
|
|
lsu_stbuf stbuf ( // @[lsu.scala 77:30]
|
|
.clock(stbuf_clock),
|
|
.reset(stbuf_reset),
|
|
.io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk),
|
|
.io_lsu_free_c2_clk(stbuf_io_lsu_free_c2_clk),
|
|
.io_lsu_pkt_m_valid(stbuf_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_store(stbuf_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(stbuf_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_pkt_r_valid(stbuf_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(stbuf_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(stbuf_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(stbuf_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_dword(stbuf_io_lsu_pkt_r_bits_dword),
|
|
.io_lsu_pkt_r_bits_store(stbuf_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_dma(stbuf_io_lsu_pkt_r_bits_dma),
|
|
.io_store_stbuf_reqvld_r(stbuf_io_store_stbuf_reqvld_r),
|
|
.io_lsu_commit_r(stbuf_io_lsu_commit_r),
|
|
.io_dec_lsu_valid_raw_d(stbuf_io_dec_lsu_valid_raw_d),
|
|
.io_store_data_hi_r(stbuf_io_store_data_hi_r),
|
|
.io_store_data_lo_r(stbuf_io_store_data_lo_r),
|
|
.io_store_datafn_hi_r(stbuf_io_store_datafn_hi_r),
|
|
.io_store_datafn_lo_r(stbuf_io_store_datafn_lo_r),
|
|
.io_lsu_stbuf_commit_any(stbuf_io_lsu_stbuf_commit_any),
|
|
.io_lsu_addr_m(stbuf_io_lsu_addr_m),
|
|
.io_lsu_addr_r(stbuf_io_lsu_addr_r),
|
|
.io_end_addr_m(stbuf_io_end_addr_m),
|
|
.io_end_addr_r(stbuf_io_end_addr_r),
|
|
.io_ldst_dual_d(stbuf_io_ldst_dual_d),
|
|
.io_ldst_dual_m(stbuf_io_ldst_dual_m),
|
|
.io_ldst_dual_r(stbuf_io_ldst_dual_r),
|
|
.io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m),
|
|
.io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r),
|
|
.io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any),
|
|
.io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any),
|
|
.io_stbuf_addr_any(stbuf_io_stbuf_addr_any),
|
|
.io_stbuf_data_any(stbuf_io_stbuf_data_any),
|
|
.io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any),
|
|
.io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r),
|
|
.io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m),
|
|
.io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m),
|
|
.io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m),
|
|
.io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m)
|
|
);
|
|
lsu_ecc ecc ( // @[lsu.scala 78:30]
|
|
.clock(ecc_clock),
|
|
.reset(ecc_reset),
|
|
.io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk),
|
|
.io_clk_override(ecc_io_clk_override),
|
|
.io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma),
|
|
.io_stbuf_data_any(ecc_io_stbuf_data_any),
|
|
.io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable),
|
|
.io_lsu_addr_m(ecc_io_lsu_addr_m),
|
|
.io_end_addr_m(ecc_io_end_addr_m),
|
|
.io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m),
|
|
.io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m),
|
|
.io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m),
|
|
.io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m),
|
|
.io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r),
|
|
.io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff),
|
|
.io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m),
|
|
.io_addr_in_dccm_m(ecc_io_addr_in_dccm_m),
|
|
.io_dma_dccm_wen(ecc_io_dma_dccm_wen),
|
|
.io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo),
|
|
.io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi),
|
|
.io_sec_data_hi_r(ecc_io_sec_data_hi_r),
|
|
.io_sec_data_lo_r(ecc_io_sec_data_lo_r),
|
|
.io_sec_data_hi_m(ecc_io_sec_data_hi_m),
|
|
.io_sec_data_lo_m(ecc_io_sec_data_lo_m),
|
|
.io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff),
|
|
.io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff),
|
|
.io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi),
|
|
.io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo),
|
|
.io_stbuf_ecc_any(ecc_io_stbuf_ecc_any),
|
|
.io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff),
|
|
.io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff),
|
|
.io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r),
|
|
.io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r),
|
|
.io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r),
|
|
.io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r),
|
|
.io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m),
|
|
.io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m)
|
|
);
|
|
lsu_trigger trigger ( // @[lsu.scala 79:30]
|
|
.io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_m(trigger_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_m(trigger_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_m(trigger_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_m(trigger_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2),
|
|
.io_lsu_pkt_m_valid(trigger_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_half(trigger_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(trigger_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(trigger_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_m_bits_store(trigger_io_lsu_pkt_m_bits_store),
|
|
.io_lsu_pkt_m_bits_dma(trigger_io_lsu_pkt_m_bits_dma),
|
|
.io_lsu_addr_m(trigger_io_lsu_addr_m),
|
|
.io_store_data_m(trigger_io_store_data_m),
|
|
.io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m)
|
|
);
|
|
lsu_clkdomain clkdomain ( // @[lsu.scala 80:30]
|
|
.clock(clkdomain_clock),
|
|
.io_clk_override(clkdomain_io_clk_override),
|
|
.io_lsu_busreq_r(clkdomain_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any),
|
|
.io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en),
|
|
.io_lsu_bus_obuf_c1_clken(clkdomain_io_lsu_bus_obuf_c1_clken),
|
|
.io_lsu_busm_clken(clkdomain_io_lsu_busm_clken),
|
|
.io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk),
|
|
.io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk),
|
|
.io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk),
|
|
.io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk),
|
|
.io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk),
|
|
.io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk)
|
|
);
|
|
lsu_bus_intf bus_intf ( // @[lsu.scala 81:30]
|
|
.clock(bus_intf_clock),
|
|
.reset(bus_intf_reset),
|
|
.io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn),
|
|
.io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned),
|
|
.io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error),
|
|
.io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy),
|
|
.io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
|
|
.io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
|
|
.io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
|
|
.io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any),
|
|
.io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any),
|
|
.io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any),
|
|
.io_lsu_bus_obuf_c1_clken(bus_intf_io_lsu_bus_obuf_c1_clken),
|
|
.io_lsu_busm_clken(bus_intf_io_lsu_busm_clken),
|
|
.io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk),
|
|
.io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk),
|
|
.io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk),
|
|
.io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk),
|
|
.io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk),
|
|
.io_active_clk(bus_intf_io_active_clk),
|
|
.io_axi_aw_ready(bus_intf_io_axi_aw_ready),
|
|
.io_axi_aw_valid(bus_intf_io_axi_aw_valid),
|
|
.io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id),
|
|
.io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr),
|
|
.io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region),
|
|
.io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size),
|
|
.io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache),
|
|
.io_axi_w_ready(bus_intf_io_axi_w_ready),
|
|
.io_axi_w_valid(bus_intf_io_axi_w_valid),
|
|
.io_axi_w_bits_data(bus_intf_io_axi_w_bits_data),
|
|
.io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb),
|
|
.io_axi_b_valid(bus_intf_io_axi_b_valid),
|
|
.io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp),
|
|
.io_axi_b_bits_id(bus_intf_io_axi_b_bits_id),
|
|
.io_axi_ar_ready(bus_intf_io_axi_ar_ready),
|
|
.io_axi_ar_valid(bus_intf_io_axi_ar_valid),
|
|
.io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id),
|
|
.io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr),
|
|
.io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region),
|
|
.io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size),
|
|
.io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache),
|
|
.io_axi_r_valid(bus_intf_io_axi_r_valid),
|
|
.io_axi_r_bits_id(bus_intf_io_axi_r_bits_id),
|
|
.io_axi_r_bits_data(bus_intf_io_axi_r_bits_data),
|
|
.io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp),
|
|
.io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d),
|
|
.io_lsu_busreq_m(bus_intf_io_lsu_busreq_m),
|
|
.io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid),
|
|
.io_lsu_pkt_m_bits_by(bus_intf_io_lsu_pkt_m_bits_by),
|
|
.io_lsu_pkt_m_bits_half(bus_intf_io_lsu_pkt_m_bits_half),
|
|
.io_lsu_pkt_m_bits_word(bus_intf_io_lsu_pkt_m_bits_word),
|
|
.io_lsu_pkt_m_bits_load(bus_intf_io_lsu_pkt_m_bits_load),
|
|
.io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid),
|
|
.io_lsu_pkt_r_bits_by(bus_intf_io_lsu_pkt_r_bits_by),
|
|
.io_lsu_pkt_r_bits_half(bus_intf_io_lsu_pkt_r_bits_half),
|
|
.io_lsu_pkt_r_bits_word(bus_intf_io_lsu_pkt_r_bits_word),
|
|
.io_lsu_pkt_r_bits_load(bus_intf_io_lsu_pkt_r_bits_load),
|
|
.io_lsu_pkt_r_bits_store(bus_intf_io_lsu_pkt_r_bits_store),
|
|
.io_lsu_pkt_r_bits_unsign(bus_intf_io_lsu_pkt_r_bits_unsign),
|
|
.io_lsu_addr_m(bus_intf_io_lsu_addr_m),
|
|
.io_lsu_addr_r(bus_intf_io_lsu_addr_r),
|
|
.io_end_addr_m(bus_intf_io_end_addr_m),
|
|
.io_end_addr_r(bus_intf_io_end_addr_r),
|
|
.io_ldst_dual_d(bus_intf_io_ldst_dual_d),
|
|
.io_ldst_dual_m(bus_intf_io_ldst_dual_m),
|
|
.io_ldst_dual_r(bus_intf_io_ldst_dual_r),
|
|
.io_store_data_r(bus_intf_io_store_data_r),
|
|
.io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt),
|
|
.io_lsu_commit_r(bus_intf_io_lsu_commit_r),
|
|
.io_is_sideeffects_m(bus_intf_io_is_sideeffects_m),
|
|
.io_flush_m_up(bus_intf_io_flush_m_up),
|
|
.io_flush_r(bus_intf_io_flush_r),
|
|
.io_lsu_busreq_r(bus_intf_io_lsu_busreq_r),
|
|
.io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any),
|
|
.io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any),
|
|
.io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any),
|
|
.io_bus_read_data_m(bus_intf_io_bus_read_data_m),
|
|
.io_lsu_nonblock_load_data(bus_intf_io_lsu_nonblock_load_data),
|
|
.io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_error(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error),
|
|
.io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag),
|
|
.io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en)
|
|
);
|
|
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 220:27]
|
|
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 220:27]
|
|
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 220:27]
|
|
assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 220:27]
|
|
assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 95:27]
|
|
assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 222:14]
|
|
assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 222:14]
|
|
assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 222:14]
|
|
assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 222:14]
|
|
assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 222:14]
|
|
assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 222:14]
|
|
assign io_lsu_exu_lsu_result_m = lsu_lsc_ctl_io_lsu_exu_lsu_result_m; // @[lsu.scala 144:46]
|
|
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 314:49]
|
|
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 314:49]
|
|
assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 314:49]
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assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 314:49]
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assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 314:49]
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assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 314:49]
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assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 314:49]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 344:31]
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assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 344:31]
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assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 221:11]
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assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 221:11]
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assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 221:11]
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assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 221:11]
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assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 221:11]
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assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 221:11]
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assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 221:11]
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assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 221:11]
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assign io_lsu_tlu_lsu_pmu_load_external_m = _T_57 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 121:39]
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assign io_lsu_tlu_lsu_pmu_store_external_m = _T_59 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 122:39]
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assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 347:31]
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assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 347:31]
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assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 347:31]
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assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 347:31]
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assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 347:31]
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assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 347:31]
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assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 347:31]
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assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 347:31]
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assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 347:31]
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assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 347:31]
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assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 347:31]
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assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 347:31]
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assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 347:31]
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assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 347:31]
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assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 347:31]
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assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 75:24]
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assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 88:29]
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assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:29]
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assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 89:29]
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assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 109:19]
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assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 160:49]
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assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 161:49]
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assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 158:49]
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assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 159:49]
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assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 159:49]
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assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 159:49]
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assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 159:49]
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assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 159:49]
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assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 159:49]
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assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_55; // @[lsu.scala 120:39]
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assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 289:50]
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assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[lsu.scala 345:31]
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assign lsu_lsc_ctl_clock = clock;
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assign lsu_lsc_ctl_reset = reset;
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assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 126:46]
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assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 127:46]
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assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 128:46]
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assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 129:46]
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assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 130:46]
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assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 131:46]
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assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 133:46]
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assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 134:46]
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assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 135:46]
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assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 136:46]
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assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 137:46]
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assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 138:46]
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assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 139:46]
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assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 140:46]
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assign lsu_lsc_ctl_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 141:46]
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assign lsu_lsc_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != _T_66; // @[lsu.scala 142:46]
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assign lsu_lsc_ctl_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != _T_70; // @[lsu.scala 143:46]
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assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 144:46]
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assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 144:46]
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assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 145:46]
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assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 146:46]
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assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 147:46]
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assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 148:46]
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assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 149:46]
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assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 151:46]
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assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 150:46]
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assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 150:46]
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assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 150:46]
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assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 150:46]
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assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 150:46]
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assign dccm_ctl_clock = clock;
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assign dccm_ctl_reset = reset;
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assign dccm_ctl_io_clk_override = io_clk_override; // @[lsu.scala 164:46]
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assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 167:46]
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assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 169:46]
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assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 171:46]
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assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 172:46]
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assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 173:46]
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assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 174:46]
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assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 174:46]
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assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 175:46]
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assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 176:46]
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assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 177:46]
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assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 178:46]
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assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 179:46]
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assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 180:46]
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assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 181:46]
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assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 182:46]
|
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assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 183:46]
|
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assign dccm_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != _T_66; // @[lsu.scala 165:46]
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assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 184:46]
|
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assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 185:46]
|
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assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 186:46]
|
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assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 187:46]
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assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 188:46]
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assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[lsu.scala 189:46]
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assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 190:46]
|
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assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 191:46]
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assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 192:46]
|
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assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 193:46]
|
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assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 194:46]
|
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assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 195:46]
|
|
assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 196:46]
|
|
assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 197:46]
|
|
assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 198:46]
|
|
assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 199:46]
|
|
assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 200:46]
|
|
assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 203:46]
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assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 204:46]
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assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 205:46]
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assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 206:46]
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assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 207:46]
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assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[lsu.scala 208:46]
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assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[lsu.scala 209:46]
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assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 210:46]
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assign dccm_ctl_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 211:46]
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assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 212:46]
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assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 213:46]
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assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 214:46]
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assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 215:46]
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assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 216:46]
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assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 217:46]
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assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 220:27]
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assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 220:27]
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assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 221:11]
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assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 221:11]
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assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 222:14]
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assign stbuf_clock = clock;
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assign stbuf_reset = reset;
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assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 228:54]
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assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 229:54]
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assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 230:50]
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assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 230:50]
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assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 230:50]
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assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 231:50]
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assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 231:50]
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assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 232:50]
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assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 233:50]
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assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 234:50]
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assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 235:62]
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assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 236:62]
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assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 237:50]
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assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 238:56]
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assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 239:54]
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assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 241:66]
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assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 242:66]
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assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 244:66]
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assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 245:66]
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assign stbuf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 225:50]
|
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assign stbuf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != _T_66; // @[lsu.scala 226:50]
|
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assign stbuf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != _T_70; // @[lsu.scala 227:50]
|
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assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 246:50]
|
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assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 247:56]
|
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assign ecc_clock = clock;
|
|
assign ecc_reset = reset;
|
|
assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 254:52]
|
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assign ecc_io_clk_override = io_clk_override; // @[lsu.scala 253:50]
|
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assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 255:52]
|
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assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 255:52]
|
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assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 255:52]
|
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assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 255:52]
|
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assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 257:54]
|
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assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 258:50]
|
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assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 263:58]
|
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assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 264:58]
|
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assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 267:54]
|
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assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 268:54]
|
|
assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 271:50]
|
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assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 272:50]
|
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assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 273:50]
|
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assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 274:50]
|
|
assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 275:50]
|
|
assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 276:50]
|
|
assign ecc_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 277:50]
|
|
assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 278:50]
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assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 279:50]
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assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_0_m = io_trigger_pkt_any_0_m; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_1_m = io_trigger_pkt_any_1_m; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 284:50]
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assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_2_m = io_trigger_pkt_any_2_m; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_m = io_trigger_pkt_any_3_m; // @[lsu.scala 284:50]
|
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assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 284:50]
|
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assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 285:50]
|
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assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 285:50]
|
|
assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 285:50]
|
|
assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 285:50]
|
|
assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 285:50]
|
|
assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 285:50]
|
|
assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 286:50]
|
|
assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 287:50]
|
|
assign clkdomain_clock = clock;
|
|
assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 294:50]
|
|
assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 300:50]
|
|
assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 301:50]
|
|
assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 302:50]
|
|
assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 304:50]
|
|
assign bus_intf_clock = clock;
|
|
assign bus_intf_reset = reset;
|
|
assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 314:49]
|
|
assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 314:49]
|
|
assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 314:49]
|
|
assign bus_intf_io_lsu_bus_obuf_c1_clken = clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 319:49]
|
|
assign bus_intf_io_lsu_busm_clken = clkdomain_io_lsu_busm_clken; // @[lsu.scala 318:49]
|
|
assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 316:49]
|
|
assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 317:49]
|
|
assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 320:49]
|
|
assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 322:49]
|
|
assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 323:49]
|
|
assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 324:49]
|
|
assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 347:31]
|
|
assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 326:49]
|
|
assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 327:49]
|
|
assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 336:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 336:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 336:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 336:49]
|
|
assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 336:49]
|
|
assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 337:49]
|
|
assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m & _T_78; // @[lsu.scala 331:49]
|
|
assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r & _T_81; // @[lsu.scala 332:49]
|
|
assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m & _T_78; // @[lsu.scala 333:49]
|
|
assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r & _T_81; // @[lsu.scala 334:49]
|
|
assign bus_intf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 328:49]
|
|
assign bus_intf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != _T_66; // @[lsu.scala 329:49]
|
|
assign bus_intf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != _T_70; // @[lsu.scala 330:49]
|
|
assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r & _T_81; // @[lsu.scala 335:49]
|
|
assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 338:49]
|
|
assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 339:49]
|
|
assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 340:49]
|
|
assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 341:49]
|
|
assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 342:49]
|
|
assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 348:31]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
_T_66 = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
_T_70 = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
dma_mem_tag_m = _RAND_2[2:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
lsu_raw_fwd_hi_r = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
lsu_raw_fwd_lo_r = _RAND_4[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
_T_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_mem_tag_m = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_raw_fwd_hi_r = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
lsu_raw_fwd_lo_r = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_66 <= 1'h0;
|
|
end else begin
|
|
_T_66 <= lsu_lsc_ctl_io_end_addr_d[2];
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c1_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_70 <= 1'h0;
|
|
end else begin
|
|
_T_70 <= lsu_lsc_ctl_io_end_addr_m[2];
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin
|
|
if (reset) begin
|
|
dma_mem_tag_m <= 3'h0;
|
|
end else begin
|
|
dma_mem_tag_m <= io_lsu_dma_dma_mem_tag;
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_raw_fwd_hi_r <= 1'h0;
|
|
end else begin
|
|
lsu_raw_fwd_hi_r <= |stbuf_io_stbuf_fwdbyteen_hi_m;
|
|
end
|
|
end
|
|
always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin
|
|
if (reset) begin
|
|
lsu_raw_fwd_lo_r <= 1'h0;
|
|
end else begin
|
|
lsu_raw_fwd_lo_r <= |stbuf_io_stbuf_fwdbyteen_lo_m;
|
|
end
|
|
end
|
|
endmodule
|
|
module pic_ctrl(
|
|
input clock,
|
|
input reset,
|
|
input io_free_clk,
|
|
input io_io_clk_override,
|
|
input [31:0] io_extintsrc_req,
|
|
input io_lsu_pic_picm_wren,
|
|
input io_lsu_pic_picm_rden,
|
|
input io_lsu_pic_picm_mken,
|
|
input [31:0] io_lsu_pic_picm_rdaddr,
|
|
input [31:0] io_lsu_pic_picm_wraddr,
|
|
input [31:0] io_lsu_pic_picm_wr_data,
|
|
output [31:0] io_lsu_pic_picm_rd_data,
|
|
output [7:0] io_dec_pic_pic_claimid,
|
|
output [3:0] io_dec_pic_pic_pl,
|
|
output io_dec_pic_mhwakeup,
|
|
input [3:0] io_dec_pic_dec_tlu_meicurpl,
|
|
input [3:0] io_dec_pic_dec_tlu_meipt,
|
|
output io_dec_pic_mexintpend
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
reg [31:0] _RAND_137;
|
|
reg [31:0] _RAND_138;
|
|
reg [31:0] _RAND_139;
|
|
reg [31:0] _RAND_140;
|
|
reg [31:0] _RAND_141;
|
|
reg [31:0] _RAND_142;
|
|
reg [31:0] _RAND_143;
|
|
reg [31:0] _RAND_144;
|
|
reg [31:0] _RAND_145;
|
|
reg [31:0] _RAND_146;
|
|
reg [31:0] _RAND_147;
|
|
reg [31:0] _RAND_148;
|
|
reg [31:0] _RAND_149;
|
|
reg [31:0] _RAND_150;
|
|
reg [31:0] _RAND_151;
|
|
reg [31:0] _RAND_152;
|
|
reg [31:0] _RAND_153;
|
|
reg [31:0] _RAND_154;
|
|
reg [31:0] _RAND_155;
|
|
reg [31:0] _RAND_156;
|
|
reg [31:0] _RAND_157;
|
|
reg [31:0] _RAND_158;
|
|
reg [31:0] _RAND_159;
|
|
reg [31:0] _RAND_160;
|
|
reg [31:0] _RAND_161;
|
|
reg [31:0] _RAND_162;
|
|
reg [31:0] _RAND_163;
|
|
reg [31:0] _RAND_164;
|
|
reg [31:0] _RAND_165;
|
|
reg [31:0] _RAND_166;
|
|
reg [31:0] _RAND_167;
|
|
reg [31:0] _RAND_168;
|
|
reg [31:0] _RAND_169;
|
|
reg [31:0] _RAND_170;
|
|
reg [31:0] _RAND_171;
|
|
reg [31:0] _RAND_172;
|
|
reg [31:0] _RAND_173;
|
|
reg [31:0] _RAND_174;
|
|
reg [31:0] _RAND_175;
|
|
reg [31:0] _RAND_176;
|
|
reg [31:0] _RAND_177;
|
|
reg [31:0] _RAND_178;
|
|
reg [31:0] _RAND_179;
|
|
reg [31:0] _RAND_180;
|
|
reg [31:0] _RAND_181;
|
|
reg [31:0] _RAND_182;
|
|
reg [31:0] _RAND_183;
|
|
reg [31:0] _RAND_184;
|
|
reg [31:0] _RAND_185;
|
|
reg [31:0] _RAND_186;
|
|
reg [31:0] _RAND_187;
|
|
reg [31:0] _RAND_188;
|
|
reg [31:0] _RAND_189;
|
|
reg [31:0] _RAND_190;
|
|
reg [31:0] _RAND_191;
|
|
reg [31:0] _RAND_192;
|
|
reg [31:0] _RAND_193;
|
|
reg [31:0] _RAND_194;
|
|
reg [31:0] _RAND_195;
|
|
reg [31:0] _RAND_196;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
reg [31:0] picm_raddr_ff; // @[pic_ctrl.scala 101:56]
|
|
reg [31:0] picm_waddr_ff; // @[pic_ctrl.scala 102:57]
|
|
reg picm_wren_ff; // @[pic_ctrl.scala 103:53]
|
|
reg picm_rden_ff; // @[pic_ctrl.scala 104:53]
|
|
reg picm_mken_ff; // @[pic_ctrl.scala 105:53]
|
|
reg [31:0] picm_wr_data_ff; // @[pic_ctrl.scala 106:58]
|
|
reg [1:0] gw_config_reg_31; // @[Reg.scala 27:20]
|
|
wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[pic_ctrl.scala 133:71]
|
|
wire _T_465 = picm_waddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 158:139]
|
|
wire _T_466 = waddr_intenable_base_match & _T_465; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_31 = _T_466 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1239 = gw_config_reg_31[1] | intenable_reg_we_31; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_31; // @[Reg.scala 27:20]
|
|
wire _T_1240 = _T_1239 | intenable_reg_31; // @[pic_ctrl.scala 170:117]
|
|
wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[pic_ctrl.scala 131:71]
|
|
wire _T_838 = addr_clear_gw_base_match & _T_465; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_31 = _T_838 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1241 = _T_1240 | gw_clear_reg_we_31; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_30; // @[Reg.scala 27:20]
|
|
wire _T_462 = picm_waddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 158:139]
|
|
wire _T_463 = waddr_intenable_base_match & _T_462; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_30 = _T_463 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1235 = gw_config_reg_30[1] | intenable_reg_we_30; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_30; // @[Reg.scala 27:20]
|
|
wire _T_1236 = _T_1235 | intenable_reg_30; // @[pic_ctrl.scala 170:117]
|
|
wire _T_835 = addr_clear_gw_base_match & _T_462; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_30 = _T_835 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1237 = _T_1236 | gw_clear_reg_we_30; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_29; // @[Reg.scala 27:20]
|
|
wire _T_459 = picm_waddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 158:139]
|
|
wire _T_460 = waddr_intenable_base_match & _T_459; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_29 = _T_460 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1231 = gw_config_reg_29[1] | intenable_reg_we_29; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_29; // @[Reg.scala 27:20]
|
|
wire _T_1232 = _T_1231 | intenable_reg_29; // @[pic_ctrl.scala 170:117]
|
|
wire _T_832 = addr_clear_gw_base_match & _T_459; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_29 = _T_832 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1233 = _T_1232 | gw_clear_reg_we_29; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_28; // @[Reg.scala 27:20]
|
|
wire _T_456 = picm_waddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 158:139]
|
|
wire _T_457 = waddr_intenable_base_match & _T_456; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_28 = _T_457 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1227 = gw_config_reg_28[1] | intenable_reg_we_28; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_28; // @[Reg.scala 27:20]
|
|
wire _T_1228 = _T_1227 | intenable_reg_28; // @[pic_ctrl.scala 170:117]
|
|
wire _T_829 = addr_clear_gw_base_match & _T_456; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_28 = _T_829 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
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wire _T_1229 = _T_1228 | gw_clear_reg_we_28; // @[pic_ctrl.scala 170:136]
|
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reg [1:0] gw_config_reg_27; // @[Reg.scala 27:20]
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wire _T_453 = picm_waddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 158:139]
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wire _T_454 = waddr_intenable_base_match & _T_453; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_27 = _T_454 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1223 = gw_config_reg_27[1] | intenable_reg_we_27; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_27; // @[Reg.scala 27:20]
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wire _T_1224 = _T_1223 | intenable_reg_27; // @[pic_ctrl.scala 170:117]
|
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wire _T_826 = addr_clear_gw_base_match & _T_453; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_27 = _T_826 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1225 = _T_1224 | gw_clear_reg_we_27; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_26; // @[Reg.scala 27:20]
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wire _T_450 = picm_waddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 158:139]
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wire _T_451 = waddr_intenable_base_match & _T_450; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_26 = _T_451 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1219 = gw_config_reg_26[1] | intenable_reg_we_26; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_26; // @[Reg.scala 27:20]
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wire _T_1220 = _T_1219 | intenable_reg_26; // @[pic_ctrl.scala 170:117]
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wire _T_823 = addr_clear_gw_base_match & _T_450; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_26 = _T_823 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1221 = _T_1220 | gw_clear_reg_we_26; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_25; // @[Reg.scala 27:20]
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wire _T_447 = picm_waddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 158:139]
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wire _T_448 = waddr_intenable_base_match & _T_447; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_25 = _T_448 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1215 = gw_config_reg_25[1] | intenable_reg_we_25; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_25; // @[Reg.scala 27:20]
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wire _T_1216 = _T_1215 | intenable_reg_25; // @[pic_ctrl.scala 170:117]
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wire _T_820 = addr_clear_gw_base_match & _T_447; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_25 = _T_820 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1217 = _T_1216 | gw_clear_reg_we_25; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_24; // @[Reg.scala 27:20]
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wire _T_444 = picm_waddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 158:139]
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wire _T_445 = waddr_intenable_base_match & _T_444; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_24 = _T_445 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1211 = gw_config_reg_24[1] | intenable_reg_we_24; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_24; // @[Reg.scala 27:20]
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wire _T_1212 = _T_1211 | intenable_reg_24; // @[pic_ctrl.scala 170:117]
|
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wire _T_817 = addr_clear_gw_base_match & _T_444; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_24 = _T_817 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1213 = _T_1212 | gw_clear_reg_we_24; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_23; // @[Reg.scala 27:20]
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wire _T_441 = picm_waddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 158:139]
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wire _T_442 = waddr_intenable_base_match & _T_441; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_23 = _T_442 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1207 = gw_config_reg_23[1] | intenable_reg_we_23; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_23; // @[Reg.scala 27:20]
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wire _T_1208 = _T_1207 | intenable_reg_23; // @[pic_ctrl.scala 170:117]
|
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wire _T_814 = addr_clear_gw_base_match & _T_441; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_23 = _T_814 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
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wire _T_1209 = _T_1208 | gw_clear_reg_we_23; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_22; // @[Reg.scala 27:20]
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wire _T_438 = picm_waddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 158:139]
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wire _T_439 = waddr_intenable_base_match & _T_438; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_22 = _T_439 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1203 = gw_config_reg_22[1] | intenable_reg_we_22; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_22; // @[Reg.scala 27:20]
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wire _T_1204 = _T_1203 | intenable_reg_22; // @[pic_ctrl.scala 170:117]
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wire _T_811 = addr_clear_gw_base_match & _T_438; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_22 = _T_811 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1205 = _T_1204 | gw_clear_reg_we_22; // @[pic_ctrl.scala 170:136]
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wire [9:0] _T_1250 = {_T_1241,_T_1237,_T_1233,_T_1229,_T_1225,_T_1221,_T_1217,_T_1213,_T_1209,_T_1205}; // @[Cat.scala 29:58]
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reg [1:0] gw_config_reg_21; // @[Reg.scala 27:20]
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wire _T_435 = picm_waddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 158:139]
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wire _T_436 = waddr_intenable_base_match & _T_435; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_21 = _T_436 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1199 = gw_config_reg_21[1] | intenable_reg_we_21; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_21; // @[Reg.scala 27:20]
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wire _T_1200 = _T_1199 | intenable_reg_21; // @[pic_ctrl.scala 170:117]
|
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wire _T_808 = addr_clear_gw_base_match & _T_435; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_21 = _T_808 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
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wire _T_1201 = _T_1200 | gw_clear_reg_we_21; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_20; // @[Reg.scala 27:20]
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wire _T_432 = picm_waddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 158:139]
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wire _T_433 = waddr_intenable_base_match & _T_432; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_20 = _T_433 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1195 = gw_config_reg_20[1] | intenable_reg_we_20; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_20; // @[Reg.scala 27:20]
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wire _T_1196 = _T_1195 | intenable_reg_20; // @[pic_ctrl.scala 170:117]
|
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wire _T_805 = addr_clear_gw_base_match & _T_432; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_20 = _T_805 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1197 = _T_1196 | gw_clear_reg_we_20; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_19; // @[Reg.scala 27:20]
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wire _T_429 = picm_waddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 158:139]
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wire _T_430 = waddr_intenable_base_match & _T_429; // @[pic_ctrl.scala 158:106]
|
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wire intenable_reg_we_19 = _T_430 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
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wire _T_1191 = gw_config_reg_19[1] | intenable_reg_we_19; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_19; // @[Reg.scala 27:20]
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wire _T_1192 = _T_1191 | intenable_reg_19; // @[pic_ctrl.scala 170:117]
|
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wire _T_802 = addr_clear_gw_base_match & _T_429; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_19 = _T_802 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1193 = _T_1192 | gw_clear_reg_we_19; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_18; // @[Reg.scala 27:20]
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wire _T_426 = picm_waddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 158:139]
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wire _T_427 = waddr_intenable_base_match & _T_426; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_18 = _T_427 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1187 = gw_config_reg_18[1] | intenable_reg_we_18; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_18; // @[Reg.scala 27:20]
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wire _T_1188 = _T_1187 | intenable_reg_18; // @[pic_ctrl.scala 170:117]
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wire _T_799 = addr_clear_gw_base_match & _T_426; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_18 = _T_799 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1189 = _T_1188 | gw_clear_reg_we_18; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_17; // @[Reg.scala 27:20]
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wire _T_423 = picm_waddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 158:139]
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wire _T_424 = waddr_intenable_base_match & _T_423; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_17 = _T_424 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1183 = gw_config_reg_17[1] | intenable_reg_we_17; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_17; // @[Reg.scala 27:20]
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wire _T_1184 = _T_1183 | intenable_reg_17; // @[pic_ctrl.scala 170:117]
|
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wire _T_796 = addr_clear_gw_base_match & _T_423; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_17 = _T_796 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1185 = _T_1184 | gw_clear_reg_we_17; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_16; // @[Reg.scala 27:20]
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wire _T_420 = picm_waddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 158:139]
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wire _T_421 = waddr_intenable_base_match & _T_420; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_16 = _T_421 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1179 = gw_config_reg_16[1] | intenable_reg_we_16; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_16; // @[Reg.scala 27:20]
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wire _T_1180 = _T_1179 | intenable_reg_16; // @[pic_ctrl.scala 170:117]
|
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wire _T_793 = addr_clear_gw_base_match & _T_420; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_16 = _T_793 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1181 = _T_1180 | gw_clear_reg_we_16; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_15; // @[Reg.scala 27:20]
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wire _T_417 = picm_waddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 158:139]
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wire _T_418 = waddr_intenable_base_match & _T_417; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_15 = _T_418 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
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wire _T_1175 = gw_config_reg_15[1] | intenable_reg_we_15; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_15; // @[Reg.scala 27:20]
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wire _T_1176 = _T_1175 | intenable_reg_15; // @[pic_ctrl.scala 170:117]
|
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wire _T_790 = addr_clear_gw_base_match & _T_417; // @[pic_ctrl.scala 162:106]
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wire gw_clear_reg_we_15 = _T_790 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1177 = _T_1176 | gw_clear_reg_we_15; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_14; // @[Reg.scala 27:20]
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wire _T_414 = picm_waddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 158:139]
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wire _T_415 = waddr_intenable_base_match & _T_414; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_14 = _T_415 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
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wire _T_1171 = gw_config_reg_14[1] | intenable_reg_we_14; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_14; // @[Reg.scala 27:20]
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wire _T_1172 = _T_1171 | intenable_reg_14; // @[pic_ctrl.scala 170:117]
|
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wire _T_787 = addr_clear_gw_base_match & _T_414; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_14 = _T_787 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1173 = _T_1172 | gw_clear_reg_we_14; // @[pic_ctrl.scala 170:136]
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reg [1:0] gw_config_reg_13; // @[Reg.scala 27:20]
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wire _T_411 = picm_waddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 158:139]
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wire _T_412 = waddr_intenable_base_match & _T_411; // @[pic_ctrl.scala 158:106]
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wire intenable_reg_we_13 = _T_412 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
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wire _T_1167 = gw_config_reg_13[1] | intenable_reg_we_13; // @[pic_ctrl.scala 170:95]
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reg intenable_reg_13; // @[Reg.scala 27:20]
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wire _T_1168 = _T_1167 | intenable_reg_13; // @[pic_ctrl.scala 170:117]
|
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wire _T_784 = addr_clear_gw_base_match & _T_411; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_13 = _T_784 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
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wire _T_1169 = _T_1168 | gw_clear_reg_we_13; // @[pic_ctrl.scala 170:136]
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wire [18:0] _T_1259 = {_T_1250,_T_1201,_T_1197,_T_1193,_T_1189,_T_1185,_T_1181,_T_1177,_T_1173,_T_1169}; // @[Cat.scala 29:58]
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reg [1:0] gw_config_reg_12; // @[Reg.scala 27:20]
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wire _T_408 = picm_waddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 158:139]
|
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wire _T_409 = waddr_intenable_base_match & _T_408; // @[pic_ctrl.scala 158:106]
|
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wire intenable_reg_we_12 = _T_409 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
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wire _T_1163 = gw_config_reg_12[1] | intenable_reg_we_12; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_12; // @[Reg.scala 27:20]
|
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wire _T_1164 = _T_1163 | intenable_reg_12; // @[pic_ctrl.scala 170:117]
|
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wire _T_781 = addr_clear_gw_base_match & _T_408; // @[pic_ctrl.scala 162:106]
|
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wire gw_clear_reg_we_12 = _T_781 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
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wire _T_1165 = _T_1164 | gw_clear_reg_we_12; // @[pic_ctrl.scala 170:136]
|
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reg [1:0] gw_config_reg_11; // @[Reg.scala 27:20]
|
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wire _T_405 = picm_waddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 158:139]
|
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wire _T_406 = waddr_intenable_base_match & _T_405; // @[pic_ctrl.scala 158:106]
|
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wire intenable_reg_we_11 = _T_406 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
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wire _T_1159 = gw_config_reg_11[1] | intenable_reg_we_11; // @[pic_ctrl.scala 170:95]
|
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reg intenable_reg_11; // @[Reg.scala 27:20]
|
|
wire _T_1160 = _T_1159 | intenable_reg_11; // @[pic_ctrl.scala 170:117]
|
|
wire _T_778 = addr_clear_gw_base_match & _T_405; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_11 = _T_778 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1161 = _T_1160 | gw_clear_reg_we_11; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_10; // @[Reg.scala 27:20]
|
|
wire _T_402 = picm_waddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 158:139]
|
|
wire _T_403 = waddr_intenable_base_match & _T_402; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_10 = _T_403 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1155 = gw_config_reg_10[1] | intenable_reg_we_10; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_10; // @[Reg.scala 27:20]
|
|
wire _T_1156 = _T_1155 | intenable_reg_10; // @[pic_ctrl.scala 170:117]
|
|
wire _T_775 = addr_clear_gw_base_match & _T_402; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_10 = _T_775 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1157 = _T_1156 | gw_clear_reg_we_10; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_9; // @[Reg.scala 27:20]
|
|
wire _T_399 = picm_waddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 158:139]
|
|
wire _T_400 = waddr_intenable_base_match & _T_399; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_9 = _T_400 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1151 = gw_config_reg_9[1] | intenable_reg_we_9; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_9; // @[Reg.scala 27:20]
|
|
wire _T_1152 = _T_1151 | intenable_reg_9; // @[pic_ctrl.scala 170:117]
|
|
wire _T_772 = addr_clear_gw_base_match & _T_399; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_9 = _T_772 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1153 = _T_1152 | gw_clear_reg_we_9; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_8; // @[Reg.scala 27:20]
|
|
wire _T_396 = picm_waddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 158:139]
|
|
wire _T_397 = waddr_intenable_base_match & _T_396; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_8 = _T_397 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1147 = gw_config_reg_8[1] | intenable_reg_we_8; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_8; // @[Reg.scala 27:20]
|
|
wire _T_1148 = _T_1147 | intenable_reg_8; // @[pic_ctrl.scala 170:117]
|
|
wire _T_769 = addr_clear_gw_base_match & _T_396; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_8 = _T_769 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1149 = _T_1148 | gw_clear_reg_we_8; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_7; // @[Reg.scala 27:20]
|
|
wire _T_393 = picm_waddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 158:139]
|
|
wire _T_394 = waddr_intenable_base_match & _T_393; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_7 = _T_394 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1143 = gw_config_reg_7[1] | intenable_reg_we_7; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_7; // @[Reg.scala 27:20]
|
|
wire _T_1144 = _T_1143 | intenable_reg_7; // @[pic_ctrl.scala 170:117]
|
|
wire _T_766 = addr_clear_gw_base_match & _T_393; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_7 = _T_766 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1145 = _T_1144 | gw_clear_reg_we_7; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_6; // @[Reg.scala 27:20]
|
|
wire _T_390 = picm_waddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 158:139]
|
|
wire _T_391 = waddr_intenable_base_match & _T_390; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_6 = _T_391 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1139 = gw_config_reg_6[1] | intenable_reg_we_6; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_6; // @[Reg.scala 27:20]
|
|
wire _T_1140 = _T_1139 | intenable_reg_6; // @[pic_ctrl.scala 170:117]
|
|
wire _T_763 = addr_clear_gw_base_match & _T_390; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_6 = _T_763 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
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wire _T_1141 = _T_1140 | gw_clear_reg_we_6; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_5; // @[Reg.scala 27:20]
|
|
wire _T_387 = picm_waddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 158:139]
|
|
wire _T_388 = waddr_intenable_base_match & _T_387; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_5 = _T_388 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1135 = gw_config_reg_5[1] | intenable_reg_we_5; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_5; // @[Reg.scala 27:20]
|
|
wire _T_1136 = _T_1135 | intenable_reg_5; // @[pic_ctrl.scala 170:117]
|
|
wire _T_760 = addr_clear_gw_base_match & _T_387; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_5 = _T_760 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1137 = _T_1136 | gw_clear_reg_we_5; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_4; // @[Reg.scala 27:20]
|
|
wire _T_384 = picm_waddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 158:139]
|
|
wire _T_385 = waddr_intenable_base_match & _T_384; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_4 = _T_385 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1131 = gw_config_reg_4[1] | intenable_reg_we_4; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_4; // @[Reg.scala 27:20]
|
|
wire _T_1132 = _T_1131 | intenable_reg_4; // @[pic_ctrl.scala 170:117]
|
|
wire _T_757 = addr_clear_gw_base_match & _T_384; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_4 = _T_757 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1133 = _T_1132 | gw_clear_reg_we_4; // @[pic_ctrl.scala 170:136]
|
|
wire [27:0] _T_1268 = {_T_1259,_T_1165,_T_1161,_T_1157,_T_1153,_T_1149,_T_1145,_T_1141,_T_1137,_T_1133}; // @[Cat.scala 29:58]
|
|
reg [1:0] gw_config_reg_3; // @[Reg.scala 27:20]
|
|
wire _T_381 = picm_waddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 158:139]
|
|
wire _T_382 = waddr_intenable_base_match & _T_381; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_3 = _T_382 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1127 = gw_config_reg_3[1] | intenable_reg_we_3; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_3; // @[Reg.scala 27:20]
|
|
wire _T_1128 = _T_1127 | intenable_reg_3; // @[pic_ctrl.scala 170:117]
|
|
wire _T_754 = addr_clear_gw_base_match & _T_381; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_3 = _T_754 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1129 = _T_1128 | gw_clear_reg_we_3; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_2; // @[Reg.scala 27:20]
|
|
wire _T_378 = picm_waddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 158:139]
|
|
wire _T_379 = waddr_intenable_base_match & _T_378; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_2 = _T_379 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1123 = gw_config_reg_2[1] | intenable_reg_we_2; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_2; // @[Reg.scala 27:20]
|
|
wire _T_1124 = _T_1123 | intenable_reg_2; // @[pic_ctrl.scala 170:117]
|
|
wire _T_751 = addr_clear_gw_base_match & _T_378; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_2 = _T_751 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1125 = _T_1124 | gw_clear_reg_we_2; // @[pic_ctrl.scala 170:136]
|
|
reg [1:0] gw_config_reg_1; // @[Reg.scala 27:20]
|
|
wire _T_375 = picm_waddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 158:139]
|
|
wire _T_376 = waddr_intenable_base_match & _T_375; // @[pic_ctrl.scala 158:106]
|
|
wire intenable_reg_we_1 = _T_376 & picm_wren_ff; // @[pic_ctrl.scala 158:153]
|
|
wire _T_1119 = gw_config_reg_1[1] | intenable_reg_we_1; // @[pic_ctrl.scala 170:95]
|
|
reg intenable_reg_1; // @[Reg.scala 27:20]
|
|
wire _T_1120 = _T_1119 | intenable_reg_1; // @[pic_ctrl.scala 170:117]
|
|
wire _T_748 = addr_clear_gw_base_match & _T_375; // @[pic_ctrl.scala 162:106]
|
|
wire gw_clear_reg_we_1 = _T_748 & picm_wren_ff; // @[pic_ctrl.scala 162:153]
|
|
wire _T_1121 = _T_1120 | gw_clear_reg_we_1; // @[pic_ctrl.scala 170:136]
|
|
wire [31:0] intenable_clk_enable = {_T_1268,_T_1129,_T_1125,_T_1121,1'h0}; // @[Cat.scala 29:58]
|
|
wire _T_7 = |intenable_clk_enable[3:0]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_0 = _T_7 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_11 = |intenable_clk_enable[7:4]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_1 = _T_11 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_15 = |intenable_clk_enable[11:8]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_2 = _T_15 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_19 = |intenable_clk_enable[15:12]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_3 = _T_19 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_23 = |intenable_clk_enable[19:16]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_4 = _T_23 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_27 = |intenable_clk_enable[23:20]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_5 = _T_27 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_31 = |intenable_clk_enable[27:24]; // @[pic_ctrl.scala 116:72]
|
|
wire intenable_clk_enable_grp_6 = _T_31 | io_io_clk_override; // @[pic_ctrl.scala 116:76]
|
|
wire _T_35 = |intenable_clk_enable[31:28]; // @[pic_ctrl.scala 113:87]
|
|
wire intenable_clk_enable_grp_7 = _T_35 | io_io_clk_override; // @[pic_ctrl.scala 113:91]
|
|
wire [31:0] _T_38 = picm_raddr_ff ^ 32'hf00c2000; // @[pic_ctrl.scala 122:59]
|
|
wire [31:0] temp_raddr_intenable_base_match = ~_T_38; // @[pic_ctrl.scala 122:43]
|
|
wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[pic_ctrl.scala 123:89]
|
|
wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 125:71]
|
|
wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 126:71]
|
|
wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 127:71]
|
|
wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[pic_ctrl.scala 128:71]
|
|
wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 130:71]
|
|
wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 132:71]
|
|
wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 134:71]
|
|
wire _T_49 = picm_rden_ff & picm_wren_ff; // @[pic_ctrl.scala 135:53]
|
|
wire _T_50 = picm_raddr_ff == picm_waddr_ff; // @[pic_ctrl.scala 135:86]
|
|
wire picm_bypass_ff = _T_49 & _T_50; // @[pic_ctrl.scala 135:68]
|
|
wire _T_53 = raddr_intpriority_base_match & picm_rden_ff; // @[pic_ctrl.scala 141:108]
|
|
wire _T_56 = raddr_intenable_base_match & picm_rden_ff; // @[pic_ctrl.scala 142:104]
|
|
wire _T_59 = raddr_config_gw_base_match & picm_rden_ff; // @[pic_ctrl.scala 143:108]
|
|
reg _T_66; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_1; // @[Reg.scala 27:20]
|
|
reg _T_70; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_2; // @[Reg.scala 27:20]
|
|
reg _T_74; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_3; // @[Reg.scala 27:20]
|
|
reg _T_78; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_4; // @[Reg.scala 27:20]
|
|
reg _T_82; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_5; // @[Reg.scala 27:20]
|
|
reg _T_86; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_6; // @[Reg.scala 27:20]
|
|
reg _T_90; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_7; // @[Reg.scala 27:20]
|
|
reg _T_94; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_8; // @[Reg.scala 27:20]
|
|
reg _T_98; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_9; // @[Reg.scala 27:20]
|
|
reg _T_102; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_10; // @[Reg.scala 27:20]
|
|
reg _T_106; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_11; // @[Reg.scala 27:20]
|
|
reg _T_110; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_12; // @[Reg.scala 27:20]
|
|
reg _T_114; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_13; // @[Reg.scala 27:20]
|
|
reg _T_118; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_14; // @[Reg.scala 27:20]
|
|
reg _T_122; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_15; // @[Reg.scala 27:20]
|
|
reg _T_126; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_16; // @[Reg.scala 27:20]
|
|
reg _T_130; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_17; // @[Reg.scala 27:20]
|
|
reg _T_134; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_18; // @[Reg.scala 27:20]
|
|
reg _T_138; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_19; // @[Reg.scala 27:20]
|
|
reg _T_142; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_20; // @[Reg.scala 27:20]
|
|
reg _T_146; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_21; // @[Reg.scala 27:20]
|
|
reg _T_150; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_22; // @[Reg.scala 27:20]
|
|
reg _T_154; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_23; // @[Reg.scala 27:20]
|
|
reg _T_158; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_24; // @[Reg.scala 27:20]
|
|
reg _T_162; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_25; // @[Reg.scala 27:20]
|
|
reg _T_166; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_26; // @[Reg.scala 27:20]
|
|
reg _T_170; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_27; // @[Reg.scala 27:20]
|
|
reg _T_174; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_28; // @[Reg.scala 27:20]
|
|
reg _T_178; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_29; // @[Reg.scala 27:20]
|
|
reg _T_182; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_30; // @[Reg.scala 27:20]
|
|
reg _T_186; // @[Reg.scala 27:20]
|
|
reg extintsrc_req_sync_31; // @[Reg.scala 27:20]
|
|
wire _T_190 = waddr_intpriority_base_match & _T_375; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_1 = _T_190 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_193 = waddr_intpriority_base_match & _T_378; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_2 = _T_193 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_196 = waddr_intpriority_base_match & _T_381; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_3 = _T_196 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_199 = waddr_intpriority_base_match & _T_384; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_4 = _T_199 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_202 = waddr_intpriority_base_match & _T_387; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_5 = _T_202 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_205 = waddr_intpriority_base_match & _T_390; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_6 = _T_205 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_208 = waddr_intpriority_base_match & _T_393; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_7 = _T_208 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_211 = waddr_intpriority_base_match & _T_396; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_8 = _T_211 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_214 = waddr_intpriority_base_match & _T_399; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_9 = _T_214 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_217 = waddr_intpriority_base_match & _T_402; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_10 = _T_217 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_220 = waddr_intpriority_base_match & _T_405; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_11 = _T_220 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_223 = waddr_intpriority_base_match & _T_408; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_12 = _T_223 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_226 = waddr_intpriority_base_match & _T_411; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_13 = _T_226 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_229 = waddr_intpriority_base_match & _T_414; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_14 = _T_229 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_232 = waddr_intpriority_base_match & _T_417; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_15 = _T_232 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_235 = waddr_intpriority_base_match & _T_420; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_16 = _T_235 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_238 = waddr_intpriority_base_match & _T_423; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_17 = _T_238 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_241 = waddr_intpriority_base_match & _T_426; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_18 = _T_241 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_244 = waddr_intpriority_base_match & _T_429; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_19 = _T_244 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_247 = waddr_intpriority_base_match & _T_432; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_20 = _T_247 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_250 = waddr_intpriority_base_match & _T_435; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_21 = _T_250 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_253 = waddr_intpriority_base_match & _T_438; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_22 = _T_253 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_256 = waddr_intpriority_base_match & _T_441; // @[pic_ctrl.scala 156:106]
|
|
wire intpriority_reg_we_23 = _T_256 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
|
wire _T_259 = waddr_intpriority_base_match & _T_444; // @[pic_ctrl.scala 156:106]
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wire intpriority_reg_we_24 = _T_259 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_262 = waddr_intpriority_base_match & _T_447; // @[pic_ctrl.scala 156:106]
|
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wire intpriority_reg_we_25 = _T_262 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_265 = waddr_intpriority_base_match & _T_450; // @[pic_ctrl.scala 156:106]
|
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wire intpriority_reg_we_26 = _T_265 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_268 = waddr_intpriority_base_match & _T_453; // @[pic_ctrl.scala 156:106]
|
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wire intpriority_reg_we_27 = _T_268 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_271 = waddr_intpriority_base_match & _T_456; // @[pic_ctrl.scala 156:106]
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wire intpriority_reg_we_28 = _T_271 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_274 = waddr_intpriority_base_match & _T_459; // @[pic_ctrl.scala 156:106]
|
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wire intpriority_reg_we_29 = _T_274 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_277 = waddr_intpriority_base_match & _T_462; // @[pic_ctrl.scala 156:106]
|
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wire intpriority_reg_we_30 = _T_277 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_280 = waddr_intpriority_base_match & _T_465; // @[pic_ctrl.scala 156:106]
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wire intpriority_reg_we_31 = _T_280 & picm_wren_ff; // @[pic_ctrl.scala 156:153]
|
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wire _T_282 = picm_raddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 157:139]
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wire _T_283 = raddr_intpriority_base_match & _T_282; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_1 = _T_283 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_285 = picm_raddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 157:139]
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wire _T_286 = raddr_intpriority_base_match & _T_285; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_2 = _T_286 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_288 = picm_raddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 157:139]
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wire _T_289 = raddr_intpriority_base_match & _T_288; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_3 = _T_289 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_291 = picm_raddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 157:139]
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wire _T_292 = raddr_intpriority_base_match & _T_291; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_4 = _T_292 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_294 = picm_raddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 157:139]
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wire _T_295 = raddr_intpriority_base_match & _T_294; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_5 = _T_295 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_297 = picm_raddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 157:139]
|
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wire _T_298 = raddr_intpriority_base_match & _T_297; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_6 = _T_298 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_300 = picm_raddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 157:139]
|
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wire _T_301 = raddr_intpriority_base_match & _T_300; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_7 = _T_301 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_303 = picm_raddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 157:139]
|
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wire _T_304 = raddr_intpriority_base_match & _T_303; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_8 = _T_304 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_306 = picm_raddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 157:139]
|
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wire _T_307 = raddr_intpriority_base_match & _T_306; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_9 = _T_307 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_309 = picm_raddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 157:139]
|
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wire _T_310 = raddr_intpriority_base_match & _T_309; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_10 = _T_310 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_312 = picm_raddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 157:139]
|
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wire _T_313 = raddr_intpriority_base_match & _T_312; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_11 = _T_313 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_315 = picm_raddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 157:139]
|
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wire _T_316 = raddr_intpriority_base_match & _T_315; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_12 = _T_316 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_318 = picm_raddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 157:139]
|
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wire _T_319 = raddr_intpriority_base_match & _T_318; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_13 = _T_319 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_321 = picm_raddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 157:139]
|
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wire _T_322 = raddr_intpriority_base_match & _T_321; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_14 = _T_322 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_324 = picm_raddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 157:139]
|
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wire _T_325 = raddr_intpriority_base_match & _T_324; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_15 = _T_325 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_327 = picm_raddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 157:139]
|
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wire _T_328 = raddr_intpriority_base_match & _T_327; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_16 = _T_328 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_330 = picm_raddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 157:139]
|
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wire _T_331 = raddr_intpriority_base_match & _T_330; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_17 = _T_331 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_333 = picm_raddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 157:139]
|
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wire _T_334 = raddr_intpriority_base_match & _T_333; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_18 = _T_334 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_336 = picm_raddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 157:139]
|
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wire _T_337 = raddr_intpriority_base_match & _T_336; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_19 = _T_337 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_339 = picm_raddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 157:139]
|
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wire _T_340 = raddr_intpriority_base_match & _T_339; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_20 = _T_340 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_342 = picm_raddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 157:139]
|
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wire _T_343 = raddr_intpriority_base_match & _T_342; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_21 = _T_343 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_345 = picm_raddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 157:139]
|
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wire _T_346 = raddr_intpriority_base_match & _T_345; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_22 = _T_346 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_348 = picm_raddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 157:139]
|
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wire _T_349 = raddr_intpriority_base_match & _T_348; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_23 = _T_349 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_351 = picm_raddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 157:139]
|
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wire _T_352 = raddr_intpriority_base_match & _T_351; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_24 = _T_352 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_354 = picm_raddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 157:139]
|
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wire _T_355 = raddr_intpriority_base_match & _T_354; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_25 = _T_355 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_357 = picm_raddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 157:139]
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wire _T_358 = raddr_intpriority_base_match & _T_357; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_26 = _T_358 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_360 = picm_raddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 157:139]
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wire _T_361 = raddr_intpriority_base_match & _T_360; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_27 = _T_361 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
|
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wire _T_363 = picm_raddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 157:139]
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wire _T_364 = raddr_intpriority_base_match & _T_363; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_28 = _T_364 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_366 = picm_raddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 157:139]
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wire _T_367 = raddr_intpriority_base_match & _T_366; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_29 = _T_367 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_369 = picm_raddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 157:139]
|
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wire _T_370 = raddr_intpriority_base_match & _T_369; // @[pic_ctrl.scala 157:106]
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wire intpriority_reg_re_30 = _T_370 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_372 = picm_raddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 157:139]
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wire _T_373 = raddr_intpriority_base_match & _T_372; // @[pic_ctrl.scala 157:106]
|
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wire intpriority_reg_re_31 = _T_373 & picm_rden_ff; // @[pic_ctrl.scala 157:153]
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wire _T_469 = raddr_intenable_base_match & _T_282; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_1 = _T_469 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
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wire _T_472 = raddr_intenable_base_match & _T_285; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_2 = _T_472 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_475 = raddr_intenable_base_match & _T_288; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_3 = _T_475 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_478 = raddr_intenable_base_match & _T_291; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_4 = _T_478 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_481 = raddr_intenable_base_match & _T_294; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_5 = _T_481 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_484 = raddr_intenable_base_match & _T_297; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_6 = _T_484 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_487 = raddr_intenable_base_match & _T_300; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_7 = _T_487 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_490 = raddr_intenable_base_match & _T_303; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_8 = _T_490 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_493 = raddr_intenable_base_match & _T_306; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_9 = _T_493 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_496 = raddr_intenable_base_match & _T_309; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_10 = _T_496 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_499 = raddr_intenable_base_match & _T_312; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_11 = _T_499 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_502 = raddr_intenable_base_match & _T_315; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_12 = _T_502 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_505 = raddr_intenable_base_match & _T_318; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_13 = _T_505 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_508 = raddr_intenable_base_match & _T_321; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_14 = _T_508 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_511 = raddr_intenable_base_match & _T_324; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_15 = _T_511 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_514 = raddr_intenable_base_match & _T_327; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_16 = _T_514 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
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wire _T_517 = raddr_intenable_base_match & _T_330; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_17 = _T_517 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
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wire _T_520 = raddr_intenable_base_match & _T_333; // @[pic_ctrl.scala 159:106]
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wire intenable_reg_re_18 = _T_520 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
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wire _T_523 = raddr_intenable_base_match & _T_336; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_19 = _T_523 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_526 = raddr_intenable_base_match & _T_339; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_20 = _T_526 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_529 = raddr_intenable_base_match & _T_342; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_21 = _T_529 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_532 = raddr_intenable_base_match & _T_345; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_22 = _T_532 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_535 = raddr_intenable_base_match & _T_348; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_23 = _T_535 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_538 = raddr_intenable_base_match & _T_351; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_24 = _T_538 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_541 = raddr_intenable_base_match & _T_354; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_25 = _T_541 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_544 = raddr_intenable_base_match & _T_357; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_26 = _T_544 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_547 = raddr_intenable_base_match & _T_360; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_27 = _T_547 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_550 = raddr_intenable_base_match & _T_363; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_28 = _T_550 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_553 = raddr_intenable_base_match & _T_366; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_29 = _T_553 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
|
wire _T_556 = raddr_intenable_base_match & _T_369; // @[pic_ctrl.scala 159:106]
|
|
wire intenable_reg_re_30 = _T_556 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
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wire _T_559 = raddr_intenable_base_match & _T_372; // @[pic_ctrl.scala 159:106]
|
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wire intenable_reg_re_31 = _T_559 & picm_rden_ff; // @[pic_ctrl.scala 159:153]
|
|
wire _T_562 = waddr_config_gw_base_match & _T_375; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_1 = _T_562 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
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wire _T_565 = waddr_config_gw_base_match & _T_378; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_2 = _T_565 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
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wire _T_568 = waddr_config_gw_base_match & _T_381; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_3 = _T_568 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_571 = waddr_config_gw_base_match & _T_384; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_4 = _T_571 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
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wire _T_574 = waddr_config_gw_base_match & _T_387; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_5 = _T_574 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_577 = waddr_config_gw_base_match & _T_390; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_6 = _T_577 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_580 = waddr_config_gw_base_match & _T_393; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_7 = _T_580 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_583 = waddr_config_gw_base_match & _T_396; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_8 = _T_583 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_586 = waddr_config_gw_base_match & _T_399; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_9 = _T_586 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_589 = waddr_config_gw_base_match & _T_402; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_10 = _T_589 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_592 = waddr_config_gw_base_match & _T_405; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_11 = _T_592 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_595 = waddr_config_gw_base_match & _T_408; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_12 = _T_595 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_598 = waddr_config_gw_base_match & _T_411; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_13 = _T_598 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_601 = waddr_config_gw_base_match & _T_414; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_14 = _T_601 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_604 = waddr_config_gw_base_match & _T_417; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_15 = _T_604 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_607 = waddr_config_gw_base_match & _T_420; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_16 = _T_607 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_610 = waddr_config_gw_base_match & _T_423; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_17 = _T_610 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_613 = waddr_config_gw_base_match & _T_426; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_18 = _T_613 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_616 = waddr_config_gw_base_match & _T_429; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_19 = _T_616 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_619 = waddr_config_gw_base_match & _T_432; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_20 = _T_619 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_622 = waddr_config_gw_base_match & _T_435; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_21 = _T_622 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_625 = waddr_config_gw_base_match & _T_438; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_22 = _T_625 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_628 = waddr_config_gw_base_match & _T_441; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_23 = _T_628 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_631 = waddr_config_gw_base_match & _T_444; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_24 = _T_631 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_634 = waddr_config_gw_base_match & _T_447; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_25 = _T_634 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_637 = waddr_config_gw_base_match & _T_450; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_26 = _T_637 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_640 = waddr_config_gw_base_match & _T_453; // @[pic_ctrl.scala 160:106]
|
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wire gw_config_reg_we_27 = _T_640 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_643 = waddr_config_gw_base_match & _T_456; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_28 = _T_643 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_646 = waddr_config_gw_base_match & _T_459; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_29 = _T_646 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_649 = waddr_config_gw_base_match & _T_462; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_30 = _T_649 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_652 = waddr_config_gw_base_match & _T_465; // @[pic_ctrl.scala 160:106]
|
|
wire gw_config_reg_we_31 = _T_652 & picm_wren_ff; // @[pic_ctrl.scala 160:153]
|
|
wire _T_655 = raddr_config_gw_base_match & _T_282; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_1 = _T_655 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_658 = raddr_config_gw_base_match & _T_285; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_2 = _T_658 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_661 = raddr_config_gw_base_match & _T_288; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_3 = _T_661 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_664 = raddr_config_gw_base_match & _T_291; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_4 = _T_664 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_667 = raddr_config_gw_base_match & _T_294; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_5 = _T_667 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_670 = raddr_config_gw_base_match & _T_297; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_6 = _T_670 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_673 = raddr_config_gw_base_match & _T_300; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_7 = _T_673 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_676 = raddr_config_gw_base_match & _T_303; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_8 = _T_676 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_679 = raddr_config_gw_base_match & _T_306; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_9 = _T_679 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_682 = raddr_config_gw_base_match & _T_309; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_10 = _T_682 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_685 = raddr_config_gw_base_match & _T_312; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_11 = _T_685 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_688 = raddr_config_gw_base_match & _T_315; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_12 = _T_688 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_691 = raddr_config_gw_base_match & _T_318; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_13 = _T_691 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_694 = raddr_config_gw_base_match & _T_321; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_14 = _T_694 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_697 = raddr_config_gw_base_match & _T_324; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_15 = _T_697 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_700 = raddr_config_gw_base_match & _T_327; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_16 = _T_700 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_703 = raddr_config_gw_base_match & _T_330; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_17 = _T_703 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_706 = raddr_config_gw_base_match & _T_333; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_18 = _T_706 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_709 = raddr_config_gw_base_match & _T_336; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_19 = _T_709 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_712 = raddr_config_gw_base_match & _T_339; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_20 = _T_712 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_715 = raddr_config_gw_base_match & _T_342; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_21 = _T_715 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_718 = raddr_config_gw_base_match & _T_345; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_22 = _T_718 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_721 = raddr_config_gw_base_match & _T_348; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_23 = _T_721 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_724 = raddr_config_gw_base_match & _T_351; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_24 = _T_724 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_727 = raddr_config_gw_base_match & _T_354; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_25 = _T_727 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_730 = raddr_config_gw_base_match & _T_357; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_26 = _T_730 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_733 = raddr_config_gw_base_match & _T_360; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_27 = _T_733 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_736 = raddr_config_gw_base_match & _T_363; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_28 = _T_736 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_739 = raddr_config_gw_base_match & _T_366; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_29 = _T_739 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_742 = raddr_config_gw_base_match & _T_369; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_30 = _T_742 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
wire _T_745 = raddr_config_gw_base_match & _T_372; // @[pic_ctrl.scala 161:106]
|
|
wire gw_config_reg_re_31 = _T_745 & picm_rden_ff; // @[pic_ctrl.scala 161:153]
|
|
reg [3:0] intpriority_reg_1; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_2; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_3; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_4; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_5; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_6; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_7; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_8; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_9; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_10; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_11; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_12; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_13; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_14; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_15; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_16; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_17; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_18; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_19; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_20; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_21; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_22; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_23; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_24; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_25; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_26; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_27; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_28; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_29; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_30; // @[Reg.scala 27:20]
|
|
reg [3:0] intpriority_reg_31; // @[Reg.scala 27:20]
|
|
wire _T_1279 = extintsrc_req_sync_1 ^ gw_config_reg_1[0]; // @[lib.scala 117:50]
|
|
wire _T_1280 = ~gw_clear_reg_we_1; // @[lib.scala 117:92]
|
|
reg _T_1283; // @[Reg.scala 27:20]
|
|
wire _T_1281 = _T_1283 & _T_1280; // @[lib.scala 117:90]
|
|
wire _T_1282 = _T_1279 | _T_1281; // @[lib.scala 117:72]
|
|
wire _T_1286 = _T_1279 | _T_1283; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_1286 : _T_1279; // @[lib.scala 119:8]
|
|
wire _T_1294 = extintsrc_req_sync_2 ^ gw_config_reg_2[0]; // @[lib.scala 117:50]
|
|
wire _T_1295 = ~gw_clear_reg_we_2; // @[lib.scala 117:92]
|
|
reg _T_1298; // @[Reg.scala 27:20]
|
|
wire _T_1296 = _T_1298 & _T_1295; // @[lib.scala 117:90]
|
|
wire _T_1297 = _T_1294 | _T_1296; // @[lib.scala 117:72]
|
|
wire _T_1301 = _T_1294 | _T_1298; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_1301 : _T_1294; // @[lib.scala 119:8]
|
|
wire _T_1309 = extintsrc_req_sync_3 ^ gw_config_reg_3[0]; // @[lib.scala 117:50]
|
|
wire _T_1310 = ~gw_clear_reg_we_3; // @[lib.scala 117:92]
|
|
reg _T_1313; // @[Reg.scala 27:20]
|
|
wire _T_1311 = _T_1313 & _T_1310; // @[lib.scala 117:90]
|
|
wire _T_1312 = _T_1309 | _T_1311; // @[lib.scala 117:72]
|
|
wire _T_1316 = _T_1309 | _T_1313; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1316 : _T_1309; // @[lib.scala 119:8]
|
|
wire _T_1324 = extintsrc_req_sync_4 ^ gw_config_reg_4[0]; // @[lib.scala 117:50]
|
|
wire _T_1325 = ~gw_clear_reg_we_4; // @[lib.scala 117:92]
|
|
reg _T_1328; // @[Reg.scala 27:20]
|
|
wire _T_1326 = _T_1328 & _T_1325; // @[lib.scala 117:90]
|
|
wire _T_1327 = _T_1324 | _T_1326; // @[lib.scala 117:72]
|
|
wire _T_1331 = _T_1324 | _T_1328; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1331 : _T_1324; // @[lib.scala 119:8]
|
|
wire _T_1339 = extintsrc_req_sync_5 ^ gw_config_reg_5[0]; // @[lib.scala 117:50]
|
|
wire _T_1340 = ~gw_clear_reg_we_5; // @[lib.scala 117:92]
|
|
reg _T_1343; // @[Reg.scala 27:20]
|
|
wire _T_1341 = _T_1343 & _T_1340; // @[lib.scala 117:90]
|
|
wire _T_1342 = _T_1339 | _T_1341; // @[lib.scala 117:72]
|
|
wire _T_1346 = _T_1339 | _T_1343; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1346 : _T_1339; // @[lib.scala 119:8]
|
|
wire _T_1354 = extintsrc_req_sync_6 ^ gw_config_reg_6[0]; // @[lib.scala 117:50]
|
|
wire _T_1355 = ~gw_clear_reg_we_6; // @[lib.scala 117:92]
|
|
reg _T_1358; // @[Reg.scala 27:20]
|
|
wire _T_1356 = _T_1358 & _T_1355; // @[lib.scala 117:90]
|
|
wire _T_1357 = _T_1354 | _T_1356; // @[lib.scala 117:72]
|
|
wire _T_1361 = _T_1354 | _T_1358; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1361 : _T_1354; // @[lib.scala 119:8]
|
|
wire _T_1369 = extintsrc_req_sync_7 ^ gw_config_reg_7[0]; // @[lib.scala 117:50]
|
|
wire _T_1370 = ~gw_clear_reg_we_7; // @[lib.scala 117:92]
|
|
reg _T_1373; // @[Reg.scala 27:20]
|
|
wire _T_1371 = _T_1373 & _T_1370; // @[lib.scala 117:90]
|
|
wire _T_1372 = _T_1369 | _T_1371; // @[lib.scala 117:72]
|
|
wire _T_1376 = _T_1369 | _T_1373; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1376 : _T_1369; // @[lib.scala 119:8]
|
|
wire _T_1384 = extintsrc_req_sync_8 ^ gw_config_reg_8[0]; // @[lib.scala 117:50]
|
|
wire _T_1385 = ~gw_clear_reg_we_8; // @[lib.scala 117:92]
|
|
reg _T_1388; // @[Reg.scala 27:20]
|
|
wire _T_1386 = _T_1388 & _T_1385; // @[lib.scala 117:90]
|
|
wire _T_1387 = _T_1384 | _T_1386; // @[lib.scala 117:72]
|
|
wire _T_1391 = _T_1384 | _T_1388; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1391 : _T_1384; // @[lib.scala 119:8]
|
|
wire _T_1399 = extintsrc_req_sync_9 ^ gw_config_reg_9[0]; // @[lib.scala 117:50]
|
|
wire _T_1400 = ~gw_clear_reg_we_9; // @[lib.scala 117:92]
|
|
reg _T_1403; // @[Reg.scala 27:20]
|
|
wire _T_1401 = _T_1403 & _T_1400; // @[lib.scala 117:90]
|
|
wire _T_1402 = _T_1399 | _T_1401; // @[lib.scala 117:72]
|
|
wire _T_1406 = _T_1399 | _T_1403; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1406 : _T_1399; // @[lib.scala 119:8]
|
|
wire _T_1414 = extintsrc_req_sync_10 ^ gw_config_reg_10[0]; // @[lib.scala 117:50]
|
|
wire _T_1415 = ~gw_clear_reg_we_10; // @[lib.scala 117:92]
|
|
reg _T_1418; // @[Reg.scala 27:20]
|
|
wire _T_1416 = _T_1418 & _T_1415; // @[lib.scala 117:90]
|
|
wire _T_1417 = _T_1414 | _T_1416; // @[lib.scala 117:72]
|
|
wire _T_1421 = _T_1414 | _T_1418; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1421 : _T_1414; // @[lib.scala 119:8]
|
|
wire _T_1429 = extintsrc_req_sync_11 ^ gw_config_reg_11[0]; // @[lib.scala 117:50]
|
|
wire _T_1430 = ~gw_clear_reg_we_11; // @[lib.scala 117:92]
|
|
reg _T_1433; // @[Reg.scala 27:20]
|
|
wire _T_1431 = _T_1433 & _T_1430; // @[lib.scala 117:90]
|
|
wire _T_1432 = _T_1429 | _T_1431; // @[lib.scala 117:72]
|
|
wire _T_1436 = _T_1429 | _T_1433; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1436 : _T_1429; // @[lib.scala 119:8]
|
|
wire _T_1444 = extintsrc_req_sync_12 ^ gw_config_reg_12[0]; // @[lib.scala 117:50]
|
|
wire _T_1445 = ~gw_clear_reg_we_12; // @[lib.scala 117:92]
|
|
reg _T_1448; // @[Reg.scala 27:20]
|
|
wire _T_1446 = _T_1448 & _T_1445; // @[lib.scala 117:90]
|
|
wire _T_1447 = _T_1444 | _T_1446; // @[lib.scala 117:72]
|
|
wire _T_1451 = _T_1444 | _T_1448; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1451 : _T_1444; // @[lib.scala 119:8]
|
|
wire _T_1459 = extintsrc_req_sync_13 ^ gw_config_reg_13[0]; // @[lib.scala 117:50]
|
|
wire _T_1460 = ~gw_clear_reg_we_13; // @[lib.scala 117:92]
|
|
reg _T_1463; // @[Reg.scala 27:20]
|
|
wire _T_1461 = _T_1463 & _T_1460; // @[lib.scala 117:90]
|
|
wire _T_1462 = _T_1459 | _T_1461; // @[lib.scala 117:72]
|
|
wire _T_1466 = _T_1459 | _T_1463; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1466 : _T_1459; // @[lib.scala 119:8]
|
|
wire _T_1474 = extintsrc_req_sync_14 ^ gw_config_reg_14[0]; // @[lib.scala 117:50]
|
|
wire _T_1475 = ~gw_clear_reg_we_14; // @[lib.scala 117:92]
|
|
reg _T_1478; // @[Reg.scala 27:20]
|
|
wire _T_1476 = _T_1478 & _T_1475; // @[lib.scala 117:90]
|
|
wire _T_1477 = _T_1474 | _T_1476; // @[lib.scala 117:72]
|
|
wire _T_1481 = _T_1474 | _T_1478; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1481 : _T_1474; // @[lib.scala 119:8]
|
|
wire _T_1489 = extintsrc_req_sync_15 ^ gw_config_reg_15[0]; // @[lib.scala 117:50]
|
|
wire _T_1490 = ~gw_clear_reg_we_15; // @[lib.scala 117:92]
|
|
reg _T_1493; // @[Reg.scala 27:20]
|
|
wire _T_1491 = _T_1493 & _T_1490; // @[lib.scala 117:90]
|
|
wire _T_1492 = _T_1489 | _T_1491; // @[lib.scala 117:72]
|
|
wire _T_1496 = _T_1489 | _T_1493; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1496 : _T_1489; // @[lib.scala 119:8]
|
|
wire _T_1504 = extintsrc_req_sync_16 ^ gw_config_reg_16[0]; // @[lib.scala 117:50]
|
|
wire _T_1505 = ~gw_clear_reg_we_16; // @[lib.scala 117:92]
|
|
reg _T_1508; // @[Reg.scala 27:20]
|
|
wire _T_1506 = _T_1508 & _T_1505; // @[lib.scala 117:90]
|
|
wire _T_1507 = _T_1504 | _T_1506; // @[lib.scala 117:72]
|
|
wire _T_1511 = _T_1504 | _T_1508; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1511 : _T_1504; // @[lib.scala 119:8]
|
|
wire _T_1519 = extintsrc_req_sync_17 ^ gw_config_reg_17[0]; // @[lib.scala 117:50]
|
|
wire _T_1520 = ~gw_clear_reg_we_17; // @[lib.scala 117:92]
|
|
reg _T_1523; // @[Reg.scala 27:20]
|
|
wire _T_1521 = _T_1523 & _T_1520; // @[lib.scala 117:90]
|
|
wire _T_1522 = _T_1519 | _T_1521; // @[lib.scala 117:72]
|
|
wire _T_1526 = _T_1519 | _T_1523; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1526 : _T_1519; // @[lib.scala 119:8]
|
|
wire _T_1534 = extintsrc_req_sync_18 ^ gw_config_reg_18[0]; // @[lib.scala 117:50]
|
|
wire _T_1535 = ~gw_clear_reg_we_18; // @[lib.scala 117:92]
|
|
reg _T_1538; // @[Reg.scala 27:20]
|
|
wire _T_1536 = _T_1538 & _T_1535; // @[lib.scala 117:90]
|
|
wire _T_1537 = _T_1534 | _T_1536; // @[lib.scala 117:72]
|
|
wire _T_1541 = _T_1534 | _T_1538; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1541 : _T_1534; // @[lib.scala 119:8]
|
|
wire _T_1549 = extintsrc_req_sync_19 ^ gw_config_reg_19[0]; // @[lib.scala 117:50]
|
|
wire _T_1550 = ~gw_clear_reg_we_19; // @[lib.scala 117:92]
|
|
reg _T_1553; // @[Reg.scala 27:20]
|
|
wire _T_1551 = _T_1553 & _T_1550; // @[lib.scala 117:90]
|
|
wire _T_1552 = _T_1549 | _T_1551; // @[lib.scala 117:72]
|
|
wire _T_1556 = _T_1549 | _T_1553; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1556 : _T_1549; // @[lib.scala 119:8]
|
|
wire _T_1564 = extintsrc_req_sync_20 ^ gw_config_reg_20[0]; // @[lib.scala 117:50]
|
|
wire _T_1565 = ~gw_clear_reg_we_20; // @[lib.scala 117:92]
|
|
reg _T_1568; // @[Reg.scala 27:20]
|
|
wire _T_1566 = _T_1568 & _T_1565; // @[lib.scala 117:90]
|
|
wire _T_1567 = _T_1564 | _T_1566; // @[lib.scala 117:72]
|
|
wire _T_1571 = _T_1564 | _T_1568; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1571 : _T_1564; // @[lib.scala 119:8]
|
|
wire _T_1579 = extintsrc_req_sync_21 ^ gw_config_reg_21[0]; // @[lib.scala 117:50]
|
|
wire _T_1580 = ~gw_clear_reg_we_21; // @[lib.scala 117:92]
|
|
reg _T_1583; // @[Reg.scala 27:20]
|
|
wire _T_1581 = _T_1583 & _T_1580; // @[lib.scala 117:90]
|
|
wire _T_1582 = _T_1579 | _T_1581; // @[lib.scala 117:72]
|
|
wire _T_1586 = _T_1579 | _T_1583; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1586 : _T_1579; // @[lib.scala 119:8]
|
|
wire _T_1594 = extintsrc_req_sync_22 ^ gw_config_reg_22[0]; // @[lib.scala 117:50]
|
|
wire _T_1595 = ~gw_clear_reg_we_22; // @[lib.scala 117:92]
|
|
reg _T_1598; // @[Reg.scala 27:20]
|
|
wire _T_1596 = _T_1598 & _T_1595; // @[lib.scala 117:90]
|
|
wire _T_1597 = _T_1594 | _T_1596; // @[lib.scala 117:72]
|
|
wire _T_1601 = _T_1594 | _T_1598; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1601 : _T_1594; // @[lib.scala 119:8]
|
|
wire _T_1609 = extintsrc_req_sync_23 ^ gw_config_reg_23[0]; // @[lib.scala 117:50]
|
|
wire _T_1610 = ~gw_clear_reg_we_23; // @[lib.scala 117:92]
|
|
reg _T_1613; // @[Reg.scala 27:20]
|
|
wire _T_1611 = _T_1613 & _T_1610; // @[lib.scala 117:90]
|
|
wire _T_1612 = _T_1609 | _T_1611; // @[lib.scala 117:72]
|
|
wire _T_1616 = _T_1609 | _T_1613; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1616 : _T_1609; // @[lib.scala 119:8]
|
|
wire _T_1624 = extintsrc_req_sync_24 ^ gw_config_reg_24[0]; // @[lib.scala 117:50]
|
|
wire _T_1625 = ~gw_clear_reg_we_24; // @[lib.scala 117:92]
|
|
reg _T_1628; // @[Reg.scala 27:20]
|
|
wire _T_1626 = _T_1628 & _T_1625; // @[lib.scala 117:90]
|
|
wire _T_1627 = _T_1624 | _T_1626; // @[lib.scala 117:72]
|
|
wire _T_1631 = _T_1624 | _T_1628; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1631 : _T_1624; // @[lib.scala 119:8]
|
|
wire _T_1639 = extintsrc_req_sync_25 ^ gw_config_reg_25[0]; // @[lib.scala 117:50]
|
|
wire _T_1640 = ~gw_clear_reg_we_25; // @[lib.scala 117:92]
|
|
reg _T_1643; // @[Reg.scala 27:20]
|
|
wire _T_1641 = _T_1643 & _T_1640; // @[lib.scala 117:90]
|
|
wire _T_1642 = _T_1639 | _T_1641; // @[lib.scala 117:72]
|
|
wire _T_1646 = _T_1639 | _T_1643; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1646 : _T_1639; // @[lib.scala 119:8]
|
|
wire _T_1654 = extintsrc_req_sync_26 ^ gw_config_reg_26[0]; // @[lib.scala 117:50]
|
|
wire _T_1655 = ~gw_clear_reg_we_26; // @[lib.scala 117:92]
|
|
reg _T_1658; // @[Reg.scala 27:20]
|
|
wire _T_1656 = _T_1658 & _T_1655; // @[lib.scala 117:90]
|
|
wire _T_1657 = _T_1654 | _T_1656; // @[lib.scala 117:72]
|
|
wire _T_1661 = _T_1654 | _T_1658; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1661 : _T_1654; // @[lib.scala 119:8]
|
|
wire _T_1669 = extintsrc_req_sync_27 ^ gw_config_reg_27[0]; // @[lib.scala 117:50]
|
|
wire _T_1670 = ~gw_clear_reg_we_27; // @[lib.scala 117:92]
|
|
reg _T_1673; // @[Reg.scala 27:20]
|
|
wire _T_1671 = _T_1673 & _T_1670; // @[lib.scala 117:90]
|
|
wire _T_1672 = _T_1669 | _T_1671; // @[lib.scala 117:72]
|
|
wire _T_1676 = _T_1669 | _T_1673; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1676 : _T_1669; // @[lib.scala 119:8]
|
|
wire _T_1684 = extintsrc_req_sync_28 ^ gw_config_reg_28[0]; // @[lib.scala 117:50]
|
|
wire _T_1685 = ~gw_clear_reg_we_28; // @[lib.scala 117:92]
|
|
reg _T_1688; // @[Reg.scala 27:20]
|
|
wire _T_1686 = _T_1688 & _T_1685; // @[lib.scala 117:90]
|
|
wire _T_1687 = _T_1684 | _T_1686; // @[lib.scala 117:72]
|
|
wire _T_1691 = _T_1684 | _T_1688; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1691 : _T_1684; // @[lib.scala 119:8]
|
|
wire _T_1699 = extintsrc_req_sync_29 ^ gw_config_reg_29[0]; // @[lib.scala 117:50]
|
|
wire _T_1700 = ~gw_clear_reg_we_29; // @[lib.scala 117:92]
|
|
reg _T_1703; // @[Reg.scala 27:20]
|
|
wire _T_1701 = _T_1703 & _T_1700; // @[lib.scala 117:90]
|
|
wire _T_1702 = _T_1699 | _T_1701; // @[lib.scala 117:72]
|
|
wire _T_1706 = _T_1699 | _T_1703; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1706 : _T_1699; // @[lib.scala 119:8]
|
|
wire _T_1714 = extintsrc_req_sync_30 ^ gw_config_reg_30[0]; // @[lib.scala 117:50]
|
|
wire _T_1715 = ~gw_clear_reg_we_30; // @[lib.scala 117:92]
|
|
reg _T_1718; // @[Reg.scala 27:20]
|
|
wire _T_1716 = _T_1718 & _T_1715; // @[lib.scala 117:90]
|
|
wire _T_1717 = _T_1714 | _T_1716; // @[lib.scala 117:72]
|
|
wire _T_1721 = _T_1714 | _T_1718; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1721 : _T_1714; // @[lib.scala 119:8]
|
|
wire _T_1729 = extintsrc_req_sync_31 ^ gw_config_reg_31[0]; // @[lib.scala 117:50]
|
|
wire _T_1730 = ~gw_clear_reg_we_31; // @[lib.scala 117:92]
|
|
reg _T_1733; // @[Reg.scala 27:20]
|
|
wire _T_1731 = _T_1733 & _T_1730; // @[lib.scala 117:90]
|
|
wire _T_1732 = _T_1729 | _T_1731; // @[lib.scala 117:72]
|
|
wire _T_1736 = _T_1729 | _T_1733; // @[lib.scala 119:78]
|
|
wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1736 : _T_1729; // @[lib.scala 119:8]
|
|
reg config_reg; // @[Reg.scala 27:20]
|
|
wire [3:0] intpriority_reg_0 = 4'h0; // @[pic_ctrl.scala 163:32 pic_ctrl.scala 164:208]
|
|
wire [3:0] _T_1742 = ~intpriority_reg_1; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1742 : intpriority_reg_1; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1745 = ~intpriority_reg_2; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1745 : intpriority_reg_2; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1748 = ~intpriority_reg_3; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1748 : intpriority_reg_3; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1751 = ~intpriority_reg_4; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1751 : intpriority_reg_4; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1754 = ~intpriority_reg_5; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1754 : intpriority_reg_5; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1757 = ~intpriority_reg_6; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1757 : intpriority_reg_6; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1760 = ~intpriority_reg_7; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1760 : intpriority_reg_7; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1763 = ~intpriority_reg_8; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1763 : intpriority_reg_8; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1766 = ~intpriority_reg_9; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1766 : intpriority_reg_9; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1769 = ~intpriority_reg_10; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1769 : intpriority_reg_10; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1772 = ~intpriority_reg_11; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1772 : intpriority_reg_11; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1775 = ~intpriority_reg_12; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1775 : intpriority_reg_12; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1778 = ~intpriority_reg_13; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1778 : intpriority_reg_13; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1781 = ~intpriority_reg_14; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1781 : intpriority_reg_14; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1784 = ~intpriority_reg_15; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1784 : intpriority_reg_15; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1787 = ~intpriority_reg_16; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1787 : intpriority_reg_16; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1790 = ~intpriority_reg_17; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1790 : intpriority_reg_17; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1793 = ~intpriority_reg_18; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1793 : intpriority_reg_18; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1796 = ~intpriority_reg_19; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1796 : intpriority_reg_19; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1799 = ~intpriority_reg_20; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1799 : intpriority_reg_20; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1802 = ~intpriority_reg_21; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1802 : intpriority_reg_21; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1805 = ~intpriority_reg_22; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1805 : intpriority_reg_22; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1808 = ~intpriority_reg_23; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1808 : intpriority_reg_23; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1811 = ~intpriority_reg_24; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1811 : intpriority_reg_24; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1814 = ~intpriority_reg_25; // @[pic_ctrl.scala 176:89]
|
|
wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1814 : intpriority_reg_25; // @[pic_ctrl.scala 176:70]
|
|
wire [3:0] _T_1817 = ~intpriority_reg_26; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1817 : intpriority_reg_26; // @[pic_ctrl.scala 176:70]
|
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wire [3:0] _T_1820 = ~intpriority_reg_27; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1820 : intpriority_reg_27; // @[pic_ctrl.scala 176:70]
|
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wire [3:0] _T_1823 = ~intpriority_reg_28; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1823 : intpriority_reg_28; // @[pic_ctrl.scala 176:70]
|
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wire [3:0] _T_1826 = ~intpriority_reg_29; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1826 : intpriority_reg_29; // @[pic_ctrl.scala 176:70]
|
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wire [3:0] _T_1829 = ~intpriority_reg_30; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1829 : intpriority_reg_30; // @[pic_ctrl.scala 176:70]
|
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wire [3:0] _T_1832 = ~intpriority_reg_31; // @[pic_ctrl.scala 176:89]
|
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wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1832 : intpriority_reg_31; // @[pic_ctrl.scala 176:70]
|
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wire _T_1838 = extintsrc_req_gw_1 & intenable_reg_1; // @[pic_ctrl.scala 177:109]
|
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wire [3:0] _T_1840 = _T_1838 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
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wire [3:0] intpend_w_prior_en_1 = _T_1840 & intpriority_reg_inv_1; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1842 = extintsrc_req_gw_2 & intenable_reg_2; // @[pic_ctrl.scala 177:109]
|
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wire [3:0] _T_1844 = _T_1842 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
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wire [3:0] intpend_w_prior_en_2 = _T_1844 & intpriority_reg_inv_2; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1846 = extintsrc_req_gw_3 & intenable_reg_3; // @[pic_ctrl.scala 177:109]
|
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wire [3:0] _T_1848 = _T_1846 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
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wire [3:0] intpend_w_prior_en_3 = _T_1848 & intpriority_reg_inv_3; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1850 = extintsrc_req_gw_4 & intenable_reg_4; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1852 = _T_1850 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
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wire [3:0] intpend_w_prior_en_4 = _T_1852 & intpriority_reg_inv_4; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1854 = extintsrc_req_gw_5 & intenable_reg_5; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1856 = _T_1854 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_5 = _T_1856 & intpriority_reg_inv_5; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1858 = extintsrc_req_gw_6 & intenable_reg_6; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1860 = _T_1858 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_6 = _T_1860 & intpriority_reg_inv_6; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1862 = extintsrc_req_gw_7 & intenable_reg_7; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1864 = _T_1862 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_7 = _T_1864 & intpriority_reg_inv_7; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1866 = extintsrc_req_gw_8 & intenable_reg_8; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1868 = _T_1866 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_8 = _T_1868 & intpriority_reg_inv_8; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1870 = extintsrc_req_gw_9 & intenable_reg_9; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1872 = _T_1870 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_9 = _T_1872 & intpriority_reg_inv_9; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1874 = extintsrc_req_gw_10 & intenable_reg_10; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1876 = _T_1874 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_10 = _T_1876 & intpriority_reg_inv_10; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1878 = extintsrc_req_gw_11 & intenable_reg_11; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1880 = _T_1878 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_11 = _T_1880 & intpriority_reg_inv_11; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1882 = extintsrc_req_gw_12 & intenable_reg_12; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1884 = _T_1882 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_12 = _T_1884 & intpriority_reg_inv_12; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1886 = extintsrc_req_gw_13 & intenable_reg_13; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1888 = _T_1886 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_13 = _T_1888 & intpriority_reg_inv_13; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1890 = extintsrc_req_gw_14 & intenable_reg_14; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1892 = _T_1890 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_14 = _T_1892 & intpriority_reg_inv_14; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1894 = extintsrc_req_gw_15 & intenable_reg_15; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1896 = _T_1894 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_15 = _T_1896 & intpriority_reg_inv_15; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1898 = extintsrc_req_gw_16 & intenable_reg_16; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1900 = _T_1898 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_16 = _T_1900 & intpriority_reg_inv_16; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1902 = extintsrc_req_gw_17 & intenable_reg_17; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1904 = _T_1902 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_17 = _T_1904 & intpriority_reg_inv_17; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1906 = extintsrc_req_gw_18 & intenable_reg_18; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1908 = _T_1906 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_18 = _T_1908 & intpriority_reg_inv_18; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1910 = extintsrc_req_gw_19 & intenable_reg_19; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1912 = _T_1910 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_19 = _T_1912 & intpriority_reg_inv_19; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1914 = extintsrc_req_gw_20 & intenable_reg_20; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1916 = _T_1914 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_20 = _T_1916 & intpriority_reg_inv_20; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1918 = extintsrc_req_gw_21 & intenable_reg_21; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1920 = _T_1918 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_21 = _T_1920 & intpriority_reg_inv_21; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1922 = extintsrc_req_gw_22 & intenable_reg_22; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1924 = _T_1922 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_22 = _T_1924 & intpriority_reg_inv_22; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1926 = extintsrc_req_gw_23 & intenable_reg_23; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1928 = _T_1926 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_23 = _T_1928 & intpriority_reg_inv_23; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1930 = extintsrc_req_gw_24 & intenable_reg_24; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1932 = _T_1930 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_24 = _T_1932 & intpriority_reg_inv_24; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1934 = extintsrc_req_gw_25 & intenable_reg_25; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1936 = _T_1934 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_25 = _T_1936 & intpriority_reg_inv_25; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1938 = extintsrc_req_gw_26 & intenable_reg_26; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1940 = _T_1938 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_26 = _T_1940 & intpriority_reg_inv_26; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1942 = extintsrc_req_gw_27 & intenable_reg_27; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1944 = _T_1942 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_27 = _T_1944 & intpriority_reg_inv_27; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1946 = extintsrc_req_gw_28 & intenable_reg_28; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1948 = _T_1946 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_28 = _T_1948 & intpriority_reg_inv_28; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1950 = extintsrc_req_gw_29 & intenable_reg_29; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1952 = _T_1950 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_29 = _T_1952 & intpriority_reg_inv_29; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1954 = extintsrc_req_gw_30 & intenable_reg_30; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1956 = _T_1954 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_30 = _T_1956 & intpriority_reg_inv_30; // @[pic_ctrl.scala 177:129]
|
|
wire _T_1958 = extintsrc_req_gw_31 & intenable_reg_31; // @[pic_ctrl.scala 177:109]
|
|
wire [3:0] _T_1960 = _T_1958 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
|
wire [3:0] intpend_w_prior_en_31 = _T_1960 & intpriority_reg_inv_31; // @[pic_ctrl.scala 177:129]
|
|
wire [7:0] _T_1964 = 8'hff; // @[Bitwise.scala 72:12]
|
|
wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1841 = intpend_w_prior_en_1; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1966 = intpriority_reg_0 < _T_1841; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_1 = 8'h1; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_1 = 8'h1; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_0 = 8'h0; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_0 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id = _T_1966 ? intpend_id_1 : intpend_id_0; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority = _T_1966 ? _T_1841 : intpriority_reg_0; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1845 = intpend_w_prior_en_2; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1849 = intpend_w_prior_en_3; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1968 = _T_1845 < _T_1849; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_3 = 8'h3; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_3 = 8'h3; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_2 = 8'h2; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_2 = 8'h2; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_1 = _T_1968 ? intpend_id_3 : intpend_id_2; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_1 = _T_1968 ? _T_1849 : _T_1845; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1853 = intpend_w_prior_en_4; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1857 = intpend_w_prior_en_5; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1970 = _T_1853 < _T_1857; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_5 = 8'h5; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_5 = 8'h5; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_4 = 8'h4; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_4 = 8'h4; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_2 = _T_1970 ? intpend_id_5 : intpend_id_4; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_2 = _T_1970 ? _T_1857 : _T_1853; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1861 = intpend_w_prior_en_6; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1865 = intpend_w_prior_en_7; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1972 = _T_1861 < _T_1865; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_7 = 8'h7; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_7 = 8'h7; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_6 = 8'h6; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_6 = 8'h6; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_3 = _T_1972 ? intpend_id_7 : intpend_id_6; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_3 = _T_1972 ? _T_1865 : _T_1861; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1869 = intpend_w_prior_en_8; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1873 = intpend_w_prior_en_9; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1974 = _T_1869 < _T_1873; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_9 = 8'h9; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_9 = 8'h9; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_8 = 8'h8; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_8 = 8'h8; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_4 = _T_1974 ? intpend_id_9 : intpend_id_8; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_4 = _T_1974 ? _T_1873 : _T_1869; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1877 = intpend_w_prior_en_10; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1881 = intpend_w_prior_en_11; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1976 = _T_1877 < _T_1881; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_11 = 8'hb; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_11 = 8'hb; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_10 = 8'ha; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_10 = 8'ha; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_5 = _T_1976 ? intpend_id_11 : intpend_id_10; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_5 = _T_1976 ? _T_1881 : _T_1877; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1885 = intpend_w_prior_en_12; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
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wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
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wire [3:0] _T_1889 = intpend_w_prior_en_13; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
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wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1978 = _T_1885 < _T_1889; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_13 = 8'hd; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_13 = 8'hd; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_12 = 8'hc; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
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wire [7:0] level_intpend_id_0_12 = 8'hc; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_6 = _T_1978 ? intpend_id_13 : intpend_id_12; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_6 = _T_1978 ? _T_1889 : _T_1885; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1893 = intpend_w_prior_en_14; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
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wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
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wire [3:0] _T_1897 = intpend_w_prior_en_15; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
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wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
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wire _T_1980 = _T_1893 < _T_1897; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_15 = 8'hf; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_15 = 8'hf; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_14 = 8'he; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
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wire [7:0] level_intpend_id_0_14 = 8'he; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_7 = _T_1980 ? intpend_id_15 : intpend_id_14; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_7 = _T_1980 ? _T_1897 : _T_1893; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1901 = intpend_w_prior_en_16; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
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wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
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wire [3:0] _T_1905 = intpend_w_prior_en_17; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
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wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1982 = _T_1901 < _T_1905; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_17 = 8'h11; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_17 = 8'h11; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_16 = 8'h10; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_16 = 8'h10; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_8 = _T_1982 ? intpend_id_17 : intpend_id_16; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_8 = _T_1982 ? _T_1905 : _T_1901; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1909 = intpend_w_prior_en_18; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1913 = intpend_w_prior_en_19; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1984 = _T_1909 < _T_1913; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_19 = 8'h13; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_19 = 8'h13; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_18 = 8'h12; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_18 = 8'h12; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_9 = _T_1984 ? intpend_id_19 : intpend_id_18; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_9 = _T_1984 ? _T_1913 : _T_1909; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1917 = intpend_w_prior_en_20; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1921 = intpend_w_prior_en_21; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1986 = _T_1917 < _T_1921; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_21 = 8'h15; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_21 = 8'h15; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_20 = 8'h14; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_20 = 8'h14; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_10 = _T_1986 ? intpend_id_21 : intpend_id_20; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_10 = _T_1986 ? _T_1921 : _T_1917; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1925 = intpend_w_prior_en_22; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1929 = intpend_w_prior_en_23; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1988 = _T_1925 < _T_1929; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_23 = 8'h17; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_23 = 8'h17; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_22 = 8'h16; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_22 = 8'h16; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_11 = _T_1988 ? intpend_id_23 : intpend_id_22; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_11 = _T_1988 ? _T_1929 : _T_1925; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1933 = intpend_w_prior_en_24; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1937 = intpend_w_prior_en_25; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1990 = _T_1933 < _T_1937; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_25 = 8'h19; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_25 = 8'h19; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_24 = 8'h18; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
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wire [7:0] level_intpend_id_0_24 = 8'h18; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_12 = _T_1990 ? intpend_id_25 : intpend_id_24; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_12 = _T_1990 ? _T_1937 : _T_1933; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1941 = intpend_w_prior_en_26; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1945 = intpend_w_prior_en_27; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1992 = _T_1941 < _T_1945; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_27 = 8'h1b; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_26 = 8'h1a; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_13 = _T_1992 ? intpend_id_27 : intpend_id_26; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_13 = _T_1992 ? _T_1945 : _T_1941; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1949 = intpend_w_prior_en_28; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
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wire [3:0] _T_1953 = intpend_w_prior_en_29; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1994 = _T_1949 < _T_1953; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_29 = 8'h1d; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_28 = 8'h1c; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_14 = _T_1994 ? intpend_id_29 : intpend_id_28; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_14 = _T_1994 ? _T_1953 : _T_1949; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] _T_1957 = intpend_w_prior_en_30; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] _T_1961 = intpend_w_prior_en_31; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 177:63]
|
|
wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1996 = _T_1957 < _T_1961; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] intpend_id_31 = 8'h1f; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] intpend_id_30 = 8'h1e; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 178:55]
|
|
wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_15 = _T_1996 ? intpend_id_31 : intpend_id_30; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_15 = _T_1996 ? _T_1961 : _T_1957; // @[pic_ctrl.scala 27:49]
|
|
wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 236:33]
|
|
wire _T_1998 = intpriority_reg_0 < intpriority_reg_0; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_0_33 = 8'hff; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] level_intpend_id_0_32 = 8'hff; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 237:33]
|
|
wire [7:0] out_id_16 = _T_1998 ? _T_1964 : _T_1964; // @[pic_ctrl.scala 27:9]
|
|
wire _T_2000 = out_priority < out_priority_1; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_1 = out_id_1; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_0 = out_id; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_17 = _T_2000 ? level_intpend_id_1_1 : level_intpend_id_1_0; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_17 = _T_2000 ? out_priority_1 : out_priority; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2002 = out_priority_2 < out_priority_3; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_3 = out_id_3; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_2 = out_id_2; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_18 = _T_2002 ? level_intpend_id_1_3 : level_intpend_id_1_2; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_18 = _T_2002 ? out_priority_3 : out_priority_2; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2004 = out_priority_4 < out_priority_5; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_5 = out_id_5; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_4 = out_id_4; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_19 = _T_2004 ? level_intpend_id_1_5 : level_intpend_id_1_4; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_19 = _T_2004 ? out_priority_5 : out_priority_4; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2006 = out_priority_6 < out_priority_7; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_7 = out_id_7; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_6 = out_id_6; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_20 = _T_2006 ? level_intpend_id_1_7 : level_intpend_id_1_6; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_20 = _T_2006 ? out_priority_7 : out_priority_6; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2008 = out_priority_8 < out_priority_9; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_9 = out_id_9; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_8 = out_id_8; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_21 = _T_2008 ? level_intpend_id_1_9 : level_intpend_id_1_8; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_21 = _T_2008 ? out_priority_9 : out_priority_8; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2010 = out_priority_10 < out_priority_11; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_11 = out_id_11; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_10 = out_id_10; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_22 = _T_2010 ? level_intpend_id_1_11 : level_intpend_id_1_10; // @[pic_ctrl.scala 27:9]
|
|
wire [3:0] out_priority_22 = _T_2010 ? out_priority_11 : out_priority_10; // @[pic_ctrl.scala 27:49]
|
|
wire _T_2012 = out_priority_12 < out_priority_13; // @[pic_ctrl.scala 27:20]
|
|
wire [7:0] level_intpend_id_1_13 = out_id_13; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_12 = out_id_12; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_23 = _T_2012 ? level_intpend_id_1_13 : level_intpend_id_1_12; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_23 = _T_2012 ? out_priority_13 : out_priority_12; // @[pic_ctrl.scala 27:49]
|
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wire _T_2014 = out_priority_14 < out_priority_15; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_1_15 = out_id_15; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_1_14 = out_id_14; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_24 = _T_2014 ? level_intpend_id_1_15 : level_intpend_id_1_14; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_24 = _T_2014 ? out_priority_15 : out_priority_14; // @[pic_ctrl.scala 27:49]
|
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wire [7:0] level_intpend_id_1_17 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 245:46]
|
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wire [7:0] level_intpend_id_1_16 = out_id_16; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_25 = level_intpend_id_1_16; // @[pic_ctrl.scala 27:9]
|
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wire _T_2018 = out_priority_17 < out_priority_18; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_2_1 = out_id_18; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_2_0 = out_id_17; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_26 = _T_2018 ? level_intpend_id_2_1 : level_intpend_id_2_0; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_26 = _T_2018 ? out_priority_18 : out_priority_17; // @[pic_ctrl.scala 27:49]
|
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wire _T_2020 = out_priority_19 < out_priority_20; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_2_3 = out_id_20; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_2_2 = out_id_19; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_27 = _T_2020 ? level_intpend_id_2_3 : level_intpend_id_2_2; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_27 = _T_2020 ? out_priority_20 : out_priority_19; // @[pic_ctrl.scala 27:49]
|
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wire _T_2022 = out_priority_21 < out_priority_22; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_2_5 = out_id_22; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_2_4 = out_id_21; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_28 = _T_2022 ? level_intpend_id_2_5 : level_intpend_id_2_4; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_28 = _T_2022 ? out_priority_22 : out_priority_21; // @[pic_ctrl.scala 27:49]
|
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wire _T_2024 = out_priority_23 < out_priority_24; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_2_7 = out_id_24; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_2_6 = out_id_23; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_29 = _T_2024 ? level_intpend_id_2_7 : level_intpend_id_2_6; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_29 = _T_2024 ? out_priority_24 : out_priority_23; // @[pic_ctrl.scala 27:49]
|
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wire [7:0] level_intpend_id_2_9 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 245:46]
|
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wire [7:0] level_intpend_id_2_8 = level_intpend_id_1_16; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_30 = out_id_25; // @[pic_ctrl.scala 27:9]
|
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wire _T_2028 = out_priority_26 < out_priority_27; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_3_1 = out_id_27; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_3_0 = out_id_26; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_31 = _T_2028 ? level_intpend_id_3_1 : level_intpend_id_3_0; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_31 = _T_2028 ? out_priority_27 : out_priority_26; // @[pic_ctrl.scala 27:49]
|
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wire _T_2030 = out_priority_28 < out_priority_29; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_3_3 = out_id_29; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] level_intpend_id_3_2 = out_id_28; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_32 = _T_2030 ? level_intpend_id_3_3 : level_intpend_id_3_2; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_32 = _T_2030 ? out_priority_29 : out_priority_28; // @[pic_ctrl.scala 27:49]
|
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wire [7:0] level_intpend_id_3_5 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 245:46]
|
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wire [7:0] level_intpend_id_3_4 = out_id_25; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] out_id_33 = out_id_30; // @[pic_ctrl.scala 27:9]
|
|
wire _T_2034 = out_priority_31 < out_priority_32; // @[pic_ctrl.scala 27:20]
|
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wire [7:0] level_intpend_id_4_1 = out_id_32; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_4_0 = out_id_31; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
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wire [7:0] out_id_34 = _T_2034 ? level_intpend_id_4_1 : level_intpend_id_4_0; // @[pic_ctrl.scala 27:9]
|
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wire [3:0] out_priority_34 = _T_2034 ? out_priority_32 : out_priority_31; // @[pic_ctrl.scala 27:49]
|
|
wire [7:0] level_intpend_id_4_3 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 245:46]
|
|
wire [7:0] level_intpend_id_4_2 = out_id_30; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[pic_ctrl.scala 265:47]
|
|
wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[pic_ctrl.scala 266:47]
|
|
wire [3:0] level_intpend_w_prior_en_5_0 = out_priority_34; // @[pic_ctrl.scala 229:40 pic_ctrl.scala 233:38 pic_ctrl.scala 249:43]
|
|
wire [3:0] selected_int_priority = out_priority_34; // @[pic_ctrl.scala 253:29]
|
|
wire [3:0] _T_2041 = ~level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 277:38]
|
|
wire [3:0] pl_in_q = config_reg ? _T_2041 : level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 277:20]
|
|
reg [7:0] _T_2042; // @[pic_ctrl.scala 278:59]
|
|
reg [3:0] _T_2043; // @[pic_ctrl.scala 279:54]
|
|
wire [3:0] _T_2045 = ~io_dec_pic_dec_tlu_meipt; // @[pic_ctrl.scala 280:40]
|
|
wire [3:0] meipt_inv = config_reg ? _T_2045 : io_dec_pic_dec_tlu_meipt; // @[pic_ctrl.scala 280:22]
|
|
wire [3:0] _T_2047 = ~io_dec_pic_dec_tlu_meicurpl; // @[pic_ctrl.scala 281:43]
|
|
wire [3:0] meicurpl_inv = config_reg ? _T_2047 : io_dec_pic_dec_tlu_meicurpl; // @[pic_ctrl.scala 281:25]
|
|
wire _T_2048 = level_intpend_w_prior_en_5_0 > meipt_inv; // @[pic_ctrl.scala 282:47]
|
|
wire _T_2049 = level_intpend_w_prior_en_5_0 > meicurpl_inv; // @[pic_ctrl.scala 282:86]
|
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reg _T_2050; // @[pic_ctrl.scala 283:58]
|
|
wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[pic_ctrl.scala 284:19]
|
|
reg _T_2052; // @[pic_ctrl.scala 286:56]
|
|
wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[pic_ctrl.scala 292:60]
|
|
wire [9:0] _T_2062 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58]
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wire [18:0] _T_2071 = {_T_2062,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58]
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wire [27:0] _T_2080 = {_T_2071,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58]
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wire [63:0] intpend_reg_extended = {32'h0,_T_2080,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58]
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wire _T_2087 = picm_raddr_ff[5:2] == 4'h0; // @[pic_ctrl.scala 300:105]
|
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wire _T_2088 = intpend_reg_read & _T_2087; // @[pic_ctrl.scala 300:83]
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wire [31:0] _T_2090 = _T_2088 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
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wire [31:0] intpend_rd_part_out_0 = _T_2090 & intpend_reg_extended[31:0]; // @[pic_ctrl.scala 300:121]
|
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wire _T_2094 = picm_raddr_ff[5:2] == 4'h1; // @[pic_ctrl.scala 300:105]
|
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wire _T_2095 = intpend_reg_read & _T_2094; // @[pic_ctrl.scala 300:83]
|
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wire [31:0] _T_2097 = _T_2095 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
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wire [31:0] intpend_rd_part_out_1 = _T_2097 & intpend_reg_extended[63:32]; // @[pic_ctrl.scala 300:121]
|
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wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[pic_ctrl.scala 301:58]
|
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wire _T_2132 = intenable_reg_re_31 & intenable_reg_31; // @[Mux.scala 98:16]
|
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wire _T_2133 = intenable_reg_re_30 ? intenable_reg_30 : _T_2132; // @[Mux.scala 98:16]
|
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wire _T_2134 = intenable_reg_re_29 ? intenable_reg_29 : _T_2133; // @[Mux.scala 98:16]
|
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wire _T_2135 = intenable_reg_re_28 ? intenable_reg_28 : _T_2134; // @[Mux.scala 98:16]
|
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wire _T_2136 = intenable_reg_re_27 ? intenable_reg_27 : _T_2135; // @[Mux.scala 98:16]
|
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wire _T_2137 = intenable_reg_re_26 ? intenable_reg_26 : _T_2136; // @[Mux.scala 98:16]
|
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wire _T_2138 = intenable_reg_re_25 ? intenable_reg_25 : _T_2137; // @[Mux.scala 98:16]
|
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wire _T_2139 = intenable_reg_re_24 ? intenable_reg_24 : _T_2138; // @[Mux.scala 98:16]
|
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wire _T_2140 = intenable_reg_re_23 ? intenable_reg_23 : _T_2139; // @[Mux.scala 98:16]
|
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wire _T_2141 = intenable_reg_re_22 ? intenable_reg_22 : _T_2140; // @[Mux.scala 98:16]
|
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wire _T_2142 = intenable_reg_re_21 ? intenable_reg_21 : _T_2141; // @[Mux.scala 98:16]
|
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wire _T_2143 = intenable_reg_re_20 ? intenable_reg_20 : _T_2142; // @[Mux.scala 98:16]
|
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wire _T_2144 = intenable_reg_re_19 ? intenable_reg_19 : _T_2143; // @[Mux.scala 98:16]
|
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wire _T_2145 = intenable_reg_re_18 ? intenable_reg_18 : _T_2144; // @[Mux.scala 98:16]
|
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wire _T_2146 = intenable_reg_re_17 ? intenable_reg_17 : _T_2145; // @[Mux.scala 98:16]
|
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wire _T_2147 = intenable_reg_re_16 ? intenable_reg_16 : _T_2146; // @[Mux.scala 98:16]
|
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wire _T_2148 = intenable_reg_re_15 ? intenable_reg_15 : _T_2147; // @[Mux.scala 98:16]
|
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wire _T_2149 = intenable_reg_re_14 ? intenable_reg_14 : _T_2148; // @[Mux.scala 98:16]
|
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wire _T_2150 = intenable_reg_re_13 ? intenable_reg_13 : _T_2149; // @[Mux.scala 98:16]
|
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wire _T_2151 = intenable_reg_re_12 ? intenable_reg_12 : _T_2150; // @[Mux.scala 98:16]
|
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wire _T_2152 = intenable_reg_re_11 ? intenable_reg_11 : _T_2151; // @[Mux.scala 98:16]
|
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wire _T_2153 = intenable_reg_re_10 ? intenable_reg_10 : _T_2152; // @[Mux.scala 98:16]
|
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wire _T_2154 = intenable_reg_re_9 ? intenable_reg_9 : _T_2153; // @[Mux.scala 98:16]
|
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wire _T_2155 = intenable_reg_re_8 ? intenable_reg_8 : _T_2154; // @[Mux.scala 98:16]
|
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wire _T_2156 = intenable_reg_re_7 ? intenable_reg_7 : _T_2155; // @[Mux.scala 98:16]
|
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wire _T_2157 = intenable_reg_re_6 ? intenable_reg_6 : _T_2156; // @[Mux.scala 98:16]
|
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wire _T_2158 = intenable_reg_re_5 ? intenable_reg_5 : _T_2157; // @[Mux.scala 98:16]
|
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wire _T_2159 = intenable_reg_re_4 ? intenable_reg_4 : _T_2158; // @[Mux.scala 98:16]
|
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wire _T_2160 = intenable_reg_re_3 ? intenable_reg_3 : _T_2159; // @[Mux.scala 98:16]
|
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wire _T_2161 = intenable_reg_re_2 ? intenable_reg_2 : _T_2160; // @[Mux.scala 98:16]
|
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wire intenable_rd_out = intenable_reg_re_1 ? intenable_reg_1 : _T_2161; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2194 = intpriority_reg_re_31 ? intpriority_reg_31 : 4'h0; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2195 = intpriority_reg_re_30 ? intpriority_reg_30 : _T_2194; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2196 = intpriority_reg_re_29 ? intpriority_reg_29 : _T_2195; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2197 = intpriority_reg_re_28 ? intpriority_reg_28 : _T_2196; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2198 = intpriority_reg_re_27 ? intpriority_reg_27 : _T_2197; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2199 = intpriority_reg_re_26 ? intpriority_reg_26 : _T_2198; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2200 = intpriority_reg_re_25 ? intpriority_reg_25 : _T_2199; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2201 = intpriority_reg_re_24 ? intpriority_reg_24 : _T_2200; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2202 = intpriority_reg_re_23 ? intpriority_reg_23 : _T_2201; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2203 = intpriority_reg_re_22 ? intpriority_reg_22 : _T_2202; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2204 = intpriority_reg_re_21 ? intpriority_reg_21 : _T_2203; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2205 = intpriority_reg_re_20 ? intpriority_reg_20 : _T_2204; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2206 = intpriority_reg_re_19 ? intpriority_reg_19 : _T_2205; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2207 = intpriority_reg_re_18 ? intpriority_reg_18 : _T_2206; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2208 = intpriority_reg_re_17 ? intpriority_reg_17 : _T_2207; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2209 = intpriority_reg_re_16 ? intpriority_reg_16 : _T_2208; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2210 = intpriority_reg_re_15 ? intpriority_reg_15 : _T_2209; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2211 = intpriority_reg_re_14 ? intpriority_reg_14 : _T_2210; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2212 = intpriority_reg_re_13 ? intpriority_reg_13 : _T_2211; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2213 = intpriority_reg_re_12 ? intpriority_reg_12 : _T_2212; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2214 = intpriority_reg_re_11 ? intpriority_reg_11 : _T_2213; // @[Mux.scala 98:16]
|
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wire [3:0] _T_2215 = intpriority_reg_re_10 ? intpriority_reg_10 : _T_2214; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2216 = intpriority_reg_re_9 ? intpriority_reg_9 : _T_2215; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2217 = intpriority_reg_re_8 ? intpriority_reg_8 : _T_2216; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2218 = intpriority_reg_re_7 ? intpriority_reg_7 : _T_2217; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2219 = intpriority_reg_re_6 ? intpriority_reg_6 : _T_2218; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2220 = intpriority_reg_re_5 ? intpriority_reg_5 : _T_2219; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2221 = intpriority_reg_re_4 ? intpriority_reg_4 : _T_2220; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2222 = intpriority_reg_re_3 ? intpriority_reg_3 : _T_2221; // @[Mux.scala 98:16]
|
|
wire [3:0] _T_2223 = intpriority_reg_re_2 ? intpriority_reg_2 : _T_2222; // @[Mux.scala 98:16]
|
|
wire [3:0] intpriority_rd_out = intpriority_reg_re_1 ? intpriority_reg_1 : _T_2223; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2256 = gw_config_reg_re_31 ? gw_config_reg_31 : 2'h0; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2257 = gw_config_reg_re_30 ? gw_config_reg_30 : _T_2256; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2258 = gw_config_reg_re_29 ? gw_config_reg_29 : _T_2257; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2259 = gw_config_reg_re_28 ? gw_config_reg_28 : _T_2258; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2260 = gw_config_reg_re_27 ? gw_config_reg_27 : _T_2259; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2261 = gw_config_reg_re_26 ? gw_config_reg_26 : _T_2260; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2262 = gw_config_reg_re_25 ? gw_config_reg_25 : _T_2261; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2263 = gw_config_reg_re_24 ? gw_config_reg_24 : _T_2262; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2264 = gw_config_reg_re_23 ? gw_config_reg_23 : _T_2263; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2265 = gw_config_reg_re_22 ? gw_config_reg_22 : _T_2264; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2266 = gw_config_reg_re_21 ? gw_config_reg_21 : _T_2265; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2267 = gw_config_reg_re_20 ? gw_config_reg_20 : _T_2266; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2268 = gw_config_reg_re_19 ? gw_config_reg_19 : _T_2267; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2269 = gw_config_reg_re_18 ? gw_config_reg_18 : _T_2268; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2270 = gw_config_reg_re_17 ? gw_config_reg_17 : _T_2269; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2271 = gw_config_reg_re_16 ? gw_config_reg_16 : _T_2270; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2272 = gw_config_reg_re_15 ? gw_config_reg_15 : _T_2271; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2273 = gw_config_reg_re_14 ? gw_config_reg_14 : _T_2272; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2274 = gw_config_reg_re_13 ? gw_config_reg_13 : _T_2273; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2275 = gw_config_reg_re_12 ? gw_config_reg_12 : _T_2274; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2276 = gw_config_reg_re_11 ? gw_config_reg_11 : _T_2275; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2277 = gw_config_reg_re_10 ? gw_config_reg_10 : _T_2276; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2278 = gw_config_reg_re_9 ? gw_config_reg_9 : _T_2277; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2279 = gw_config_reg_re_8 ? gw_config_reg_8 : _T_2278; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2280 = gw_config_reg_re_7 ? gw_config_reg_7 : _T_2279; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2281 = gw_config_reg_re_6 ? gw_config_reg_6 : _T_2280; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2282 = gw_config_reg_re_5 ? gw_config_reg_5 : _T_2281; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2283 = gw_config_reg_re_4 ? gw_config_reg_4 : _T_2282; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2284 = gw_config_reg_re_3 ? gw_config_reg_3 : _T_2283; // @[Mux.scala 98:16]
|
|
wire [1:0] _T_2285 = gw_config_reg_re_2 ? gw_config_reg_2 : _T_2284; // @[Mux.scala 98:16]
|
|
wire [1:0] gw_config_rd_out = gw_config_reg_re_1 ? gw_config_reg_1 : _T_2285; // @[Mux.scala 98:16]
|
|
wire [31:0] _T_2290 = {28'h0,intpriority_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2293 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2296 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_2299 = {31'h0,config_reg}; // @[Cat.scala 29:58]
|
|
wire [14:0] address = picm_raddr_ff[14:0]; // @[pic_ctrl.scala 322:30]
|
|
wire _T_2339 = 15'h3000 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2340 = 15'h4004 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2341 = 15'h4008 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2342 = 15'h400c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2343 = 15'h4010 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2344 = 15'h4014 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2345 = 15'h4018 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2346 = 15'h401c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2347 = 15'h4020 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2348 = 15'h4024 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2349 = 15'h4028 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2350 = 15'h402c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2351 = 15'h4030 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2352 = 15'h4034 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2353 = 15'h4038 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2354 = 15'h403c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2355 = 15'h4040 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2356 = 15'h4044 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2357 = 15'h4048 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2358 = 15'h404c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2359 = 15'h4050 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2360 = 15'h4054 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2361 = 15'h4058 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2362 = 15'h405c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2363 = 15'h4060 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2364 = 15'h4064 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2365 = 15'h4068 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2366 = 15'h406c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2367 = 15'h4070 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2368 = 15'h4074 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2369 = 15'h4078 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2370 = 15'h407c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2371 = 15'h2004 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2372 = 15'h2008 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2373 = 15'h200c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2374 = 15'h2010 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2375 = 15'h2014 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2376 = 15'h2018 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2377 = 15'h201c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2378 = 15'h2020 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2379 = 15'h2024 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2380 = 15'h2028 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2381 = 15'h202c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2382 = 15'h2030 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2383 = 15'h2034 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2384 = 15'h2038 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2385 = 15'h203c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2386 = 15'h2040 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2387 = 15'h2044 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2388 = 15'h2048 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2389 = 15'h204c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2390 = 15'h2050 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2391 = 15'h2054 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2392 = 15'h2058 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2393 = 15'h205c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2394 = 15'h2060 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2395 = 15'h2064 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2396 = 15'h2068 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2397 = 15'h206c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2398 = 15'h2070 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2399 = 15'h2074 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2400 = 15'h2078 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2401 = 15'h207c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2402 = 15'h4 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2403 = 15'h8 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2404 = 15'hc == address; // @[Conditional.scala 37:30]
|
|
wire _T_2405 = 15'h10 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2406 = 15'h14 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2407 = 15'h18 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2408 = 15'h1c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2409 = 15'h20 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2410 = 15'h24 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2411 = 15'h28 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2412 = 15'h2c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2413 = 15'h30 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2414 = 15'h34 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2415 = 15'h38 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2416 = 15'h3c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2417 = 15'h40 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2418 = 15'h44 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2419 = 15'h48 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2420 = 15'h4c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2421 = 15'h50 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2422 = 15'h54 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2423 = 15'h58 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2424 = 15'h5c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2425 = 15'h60 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2426 = 15'h64 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2427 = 15'h68 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2428 = 15'h6c == address; // @[Conditional.scala 37:30]
|
|
wire _T_2429 = 15'h70 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2430 = 15'h74 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2431 = 15'h78 == address; // @[Conditional.scala 37:30]
|
|
wire _T_2432 = 15'h7c == address; // @[Conditional.scala 37:30]
|
|
wire [3:0] _GEN_187 = _T_2432 ? 4'h2 : 4'h1; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_188 = _T_2431 ? 4'h2 : _GEN_187; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_189 = _T_2430 ? 4'h2 : _GEN_188; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_190 = _T_2429 ? 4'h2 : _GEN_189; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_191 = _T_2428 ? 4'h2 : _GEN_190; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_192 = _T_2427 ? 4'h2 : _GEN_191; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_193 = _T_2426 ? 4'h2 : _GEN_192; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_194 = _T_2425 ? 4'h2 : _GEN_193; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_195 = _T_2424 ? 4'h2 : _GEN_194; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_196 = _T_2423 ? 4'h2 : _GEN_195; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_197 = _T_2422 ? 4'h2 : _GEN_196; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_198 = _T_2421 ? 4'h2 : _GEN_197; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_199 = _T_2420 ? 4'h2 : _GEN_198; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_200 = _T_2419 ? 4'h2 : _GEN_199; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_201 = _T_2418 ? 4'h2 : _GEN_200; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_202 = _T_2417 ? 4'h2 : _GEN_201; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_203 = _T_2416 ? 4'h2 : _GEN_202; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_204 = _T_2415 ? 4'h2 : _GEN_203; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_205 = _T_2414 ? 4'h2 : _GEN_204; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_206 = _T_2413 ? 4'h2 : _GEN_205; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_207 = _T_2412 ? 4'h2 : _GEN_206; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_208 = _T_2411 ? 4'h2 : _GEN_207; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_209 = _T_2410 ? 4'h2 : _GEN_208; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_210 = _T_2409 ? 4'h2 : _GEN_209; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_211 = _T_2408 ? 4'h2 : _GEN_210; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_212 = _T_2407 ? 4'h2 : _GEN_211; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_213 = _T_2406 ? 4'h2 : _GEN_212; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_214 = _T_2405 ? 4'h2 : _GEN_213; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_215 = _T_2404 ? 4'h2 : _GEN_214; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_216 = _T_2403 ? 4'h2 : _GEN_215; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_217 = _T_2402 ? 4'h2 : _GEN_216; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_218 = _T_2401 ? 4'h4 : _GEN_217; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_219 = _T_2400 ? 4'h4 : _GEN_218; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_220 = _T_2399 ? 4'h4 : _GEN_219; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_221 = _T_2398 ? 4'h4 : _GEN_220; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_222 = _T_2397 ? 4'h4 : _GEN_221; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_223 = _T_2396 ? 4'h4 : _GEN_222; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_224 = _T_2395 ? 4'h4 : _GEN_223; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_225 = _T_2394 ? 4'h4 : _GEN_224; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_226 = _T_2393 ? 4'h4 : _GEN_225; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_227 = _T_2392 ? 4'h4 : _GEN_226; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_228 = _T_2391 ? 4'h4 : _GEN_227; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_229 = _T_2390 ? 4'h4 : _GEN_228; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_230 = _T_2389 ? 4'h4 : _GEN_229; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_231 = _T_2388 ? 4'h4 : _GEN_230; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_232 = _T_2387 ? 4'h4 : _GEN_231; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_233 = _T_2386 ? 4'h4 : _GEN_232; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_234 = _T_2385 ? 4'h4 : _GEN_233; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_235 = _T_2384 ? 4'h4 : _GEN_234; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_236 = _T_2383 ? 4'h4 : _GEN_235; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_237 = _T_2382 ? 4'h4 : _GEN_236; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_238 = _T_2381 ? 4'h4 : _GEN_237; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_239 = _T_2380 ? 4'h4 : _GEN_238; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_240 = _T_2379 ? 4'h4 : _GEN_239; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_241 = _T_2378 ? 4'h4 : _GEN_240; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_242 = _T_2377 ? 4'h4 : _GEN_241; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_243 = _T_2376 ? 4'h4 : _GEN_242; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_244 = _T_2375 ? 4'h4 : _GEN_243; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_245 = _T_2374 ? 4'h4 : _GEN_244; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_246 = _T_2373 ? 4'h4 : _GEN_245; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_247 = _T_2372 ? 4'h4 : _GEN_246; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_248 = _T_2371 ? 4'h4 : _GEN_247; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_249 = _T_2370 ? 4'h8 : _GEN_248; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_250 = _T_2369 ? 4'h8 : _GEN_249; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_251 = _T_2368 ? 4'h8 : _GEN_250; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_252 = _T_2367 ? 4'h8 : _GEN_251; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_253 = _T_2366 ? 4'h8 : _GEN_252; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_254 = _T_2365 ? 4'h8 : _GEN_253; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_255 = _T_2364 ? 4'h8 : _GEN_254; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_256 = _T_2363 ? 4'h8 : _GEN_255; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_257 = _T_2362 ? 4'h8 : _GEN_256; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_258 = _T_2361 ? 4'h8 : _GEN_257; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_259 = _T_2360 ? 4'h8 : _GEN_258; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_260 = _T_2359 ? 4'h8 : _GEN_259; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_261 = _T_2358 ? 4'h8 : _GEN_260; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_262 = _T_2357 ? 4'h8 : _GEN_261; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_263 = _T_2356 ? 4'h8 : _GEN_262; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_264 = _T_2355 ? 4'h8 : _GEN_263; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_265 = _T_2354 ? 4'h8 : _GEN_264; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_266 = _T_2353 ? 4'h8 : _GEN_265; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_267 = _T_2352 ? 4'h8 : _GEN_266; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_268 = _T_2351 ? 4'h8 : _GEN_267; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_269 = _T_2350 ? 4'h8 : _GEN_268; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_270 = _T_2349 ? 4'h8 : _GEN_269; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_271 = _T_2348 ? 4'h8 : _GEN_270; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_272 = _T_2347 ? 4'h8 : _GEN_271; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_273 = _T_2346 ? 4'h8 : _GEN_272; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_274 = _T_2345 ? 4'h8 : _GEN_273; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_275 = _T_2344 ? 4'h8 : _GEN_274; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_276 = _T_2343 ? 4'h8 : _GEN_275; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_277 = _T_2342 ? 4'h8 : _GEN_276; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_278 = _T_2341 ? 4'h8 : _GEN_277; // @[Conditional.scala 39:67]
|
|
wire [3:0] _GEN_279 = _T_2340 ? 4'h8 : _GEN_278; // @[Conditional.scala 39:67]
|
|
wire [3:0] mask = _T_2339 ? 4'h4 : _GEN_279; // @[Conditional.scala 40:58]
|
|
wire _T_2301 = picm_mken_ff & mask[3]; // @[pic_ctrl.scala 315:19]
|
|
wire _T_2306 = picm_mken_ff & mask[2]; // @[pic_ctrl.scala 316:19]
|
|
wire _T_2311 = picm_mken_ff & mask[1]; // @[pic_ctrl.scala 317:19]
|
|
wire [31:0] _T_2319 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2320 = _T_53 ? _T_2290 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2321 = _T_56 ? _T_2293 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2322 = _T_59 ? _T_2296 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2323 = config_reg_re ? _T_2299 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2324 = _T_2301 ? 32'h3 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2325 = _T_2306 ? 32'h1 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2326 = _T_2311 ? 32'hf : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2328 = _T_2319 | _T_2320; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2329 = _T_2328 | _T_2321; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2330 = _T_2329 | _T_2322; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2331 = _T_2330 | _T_2323; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2332 = _T_2331 | _T_2324; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_2333 = _T_2332 | _T_2325; // @[Mux.scala 27:72]
|
|
wire [31:0] picm_rd_data_in = _T_2333 | _T_2326; // @[Mux.scala 27:72]
|
|
wire [7:0] level_intpend_id_5_0 = out_id_34; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_1_18 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_19 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_20 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_21 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_22 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_23 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_24 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_25 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_26 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_27 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_28 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_29 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_30 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_31 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_32 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_1_33 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_10 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_11 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_12 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_13 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_14 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_15 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_16 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_17 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_18 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_19 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_20 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_21 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_22 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_23 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_24 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_25 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_26 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_27 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_28 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_29 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_30 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_31 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_32 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_2_33 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_6 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_7 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_8 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_9 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_10 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_11 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_12 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_13 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_14 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_15 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_16 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_17 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_18 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_19 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_20 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_21 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_22 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_23 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_24 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_25 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_26 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_27 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_28 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_29 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_30 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_31 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_32 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_3_33 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_4 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_5 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_6 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_7 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_8 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_9 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_10 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_11 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_12 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_13 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_14 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_15 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_16 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_17 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_18 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_19 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_20 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_21 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_22 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_23 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_24 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_25 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_26 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_27 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_28 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_29 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_30 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_31 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_32 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_4_33 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_1 = out_id_33; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 248:43]
|
|
wire [7:0] level_intpend_id_5_2 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30 pic_ctrl.scala 245:46]
|
|
wire [7:0] level_intpend_id_5_3 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_4 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_5 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_6 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_7 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_8 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_9 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_10 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_11 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_12 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_13 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_14 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_15 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_16 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_17 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_18 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_19 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_20 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_21 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_22 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_23 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_24 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_25 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_26 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_27 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_28 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_29 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_30 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_31 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_32 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
wire [7:0] level_intpend_id_5_33 = 8'h0; // @[pic_ctrl.scala 230:32 pic_ctrl.scala 234:30]
|
|
assign io_lsu_pic_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[pic_ctrl.scala 321:27]
|
|
assign io_dec_pic_pic_claimid = _T_2042; // @[pic_ctrl.scala 278:49]
|
|
assign io_dec_pic_pic_pl = _T_2043; // @[pic_ctrl.scala 279:44]
|
|
assign io_dec_pic_mhwakeup = _T_2052; // @[pic_ctrl.scala 286:23]
|
|
assign io_dec_pic_mexintpend = _T_2050; // @[pic_ctrl.scala 283:25]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
picm_raddr_ff = _RAND_0[31:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
picm_waddr_ff = _RAND_1[31:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
picm_wren_ff = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
picm_rden_ff = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
picm_mken_ff = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
picm_wr_data_ff = _RAND_5[31:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
gw_config_reg_31 = _RAND_6[1:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
intenable_reg_31 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
gw_config_reg_30 = _RAND_8[1:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
intenable_reg_30 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
gw_config_reg_29 = _RAND_10[1:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
intenable_reg_29 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
gw_config_reg_28 = _RAND_12[1:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
intenable_reg_28 = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
gw_config_reg_27 = _RAND_14[1:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
intenable_reg_27 = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
gw_config_reg_26 = _RAND_16[1:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
intenable_reg_26 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
gw_config_reg_25 = _RAND_18[1:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
intenable_reg_25 = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
gw_config_reg_24 = _RAND_20[1:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
intenable_reg_24 = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
gw_config_reg_23 = _RAND_22[1:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
intenable_reg_23 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
gw_config_reg_22 = _RAND_24[1:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
intenable_reg_22 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
gw_config_reg_21 = _RAND_26[1:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
intenable_reg_21 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
gw_config_reg_20 = _RAND_28[1:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
intenable_reg_20 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
gw_config_reg_19 = _RAND_30[1:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
intenable_reg_19 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
gw_config_reg_18 = _RAND_32[1:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
intenable_reg_18 = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
gw_config_reg_17 = _RAND_34[1:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
intenable_reg_17 = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
gw_config_reg_16 = _RAND_36[1:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
intenable_reg_16 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
gw_config_reg_15 = _RAND_38[1:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
intenable_reg_15 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
gw_config_reg_14 = _RAND_40[1:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
intenable_reg_14 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
gw_config_reg_13 = _RAND_42[1:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
intenable_reg_13 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
gw_config_reg_12 = _RAND_44[1:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
intenable_reg_12 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
gw_config_reg_11 = _RAND_46[1:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
intenable_reg_11 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
gw_config_reg_10 = _RAND_48[1:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
intenable_reg_10 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
gw_config_reg_9 = _RAND_50[1:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
intenable_reg_9 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
gw_config_reg_8 = _RAND_52[1:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
intenable_reg_8 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
gw_config_reg_7 = _RAND_54[1:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
intenable_reg_7 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
gw_config_reg_6 = _RAND_56[1:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
intenable_reg_6 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
gw_config_reg_5 = _RAND_58[1:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
intenable_reg_5 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
gw_config_reg_4 = _RAND_60[1:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
intenable_reg_4 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
gw_config_reg_3 = _RAND_62[1:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
intenable_reg_3 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
gw_config_reg_2 = _RAND_64[1:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
intenable_reg_2 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
gw_config_reg_1 = _RAND_66[1:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
intenable_reg_1 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
_T_66 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
extintsrc_req_sync_1 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
_T_70 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
extintsrc_req_sync_2 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
_T_74 = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
extintsrc_req_sync_3 = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
_T_78 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
extintsrc_req_sync_4 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
_T_82 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
extintsrc_req_sync_5 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
_T_86 = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
extintsrc_req_sync_6 = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
_T_90 = _RAND_80[0:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
extintsrc_req_sync_7 = _RAND_81[0:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
_T_94 = _RAND_82[0:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
extintsrc_req_sync_8 = _RAND_83[0:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
_T_98 = _RAND_84[0:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
extintsrc_req_sync_9 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
_T_102 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
extintsrc_req_sync_10 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
_T_106 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
extintsrc_req_sync_11 = _RAND_89[0:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
_T_110 = _RAND_90[0:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
extintsrc_req_sync_12 = _RAND_91[0:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
_T_114 = _RAND_92[0:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
extintsrc_req_sync_13 = _RAND_93[0:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
_T_118 = _RAND_94[0:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
extintsrc_req_sync_14 = _RAND_95[0:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
_T_122 = _RAND_96[0:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
extintsrc_req_sync_15 = _RAND_97[0:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
_T_126 = _RAND_98[0:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
extintsrc_req_sync_16 = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
_T_130 = _RAND_100[0:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
extintsrc_req_sync_17 = _RAND_101[0:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
_T_134 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
extintsrc_req_sync_18 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
_T_138 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
extintsrc_req_sync_19 = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
_T_142 = _RAND_106[0:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
extintsrc_req_sync_20 = _RAND_107[0:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
_T_146 = _RAND_108[0:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
extintsrc_req_sync_21 = _RAND_109[0:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
_T_150 = _RAND_110[0:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
extintsrc_req_sync_22 = _RAND_111[0:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
_T_154 = _RAND_112[0:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
extintsrc_req_sync_23 = _RAND_113[0:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
_T_158 = _RAND_114[0:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
extintsrc_req_sync_24 = _RAND_115[0:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
_T_162 = _RAND_116[0:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
extintsrc_req_sync_25 = _RAND_117[0:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
_T_166 = _RAND_118[0:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
extintsrc_req_sync_26 = _RAND_119[0:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
_T_170 = _RAND_120[0:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
extintsrc_req_sync_27 = _RAND_121[0:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
_T_174 = _RAND_122[0:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
extintsrc_req_sync_28 = _RAND_123[0:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
_T_178 = _RAND_124[0:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
extintsrc_req_sync_29 = _RAND_125[0:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
_T_182 = _RAND_126[0:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
extintsrc_req_sync_30 = _RAND_127[0:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
_T_186 = _RAND_128[0:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
extintsrc_req_sync_31 = _RAND_129[0:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
intpriority_reg_1 = _RAND_130[3:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
intpriority_reg_2 = _RAND_131[3:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
intpriority_reg_3 = _RAND_132[3:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
intpriority_reg_4 = _RAND_133[3:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
intpriority_reg_5 = _RAND_134[3:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
intpriority_reg_6 = _RAND_135[3:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
intpriority_reg_7 = _RAND_136[3:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
intpriority_reg_8 = _RAND_137[3:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
intpriority_reg_9 = _RAND_138[3:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
intpriority_reg_10 = _RAND_139[3:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
intpriority_reg_11 = _RAND_140[3:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
intpriority_reg_12 = _RAND_141[3:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
intpriority_reg_13 = _RAND_142[3:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
intpriority_reg_14 = _RAND_143[3:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
intpriority_reg_15 = _RAND_144[3:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
intpriority_reg_16 = _RAND_145[3:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
intpriority_reg_17 = _RAND_146[3:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
intpriority_reg_18 = _RAND_147[3:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
intpriority_reg_19 = _RAND_148[3:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
intpriority_reg_20 = _RAND_149[3:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
intpriority_reg_21 = _RAND_150[3:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
intpriority_reg_22 = _RAND_151[3:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
intpriority_reg_23 = _RAND_152[3:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
intpriority_reg_24 = _RAND_153[3:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
intpriority_reg_25 = _RAND_154[3:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
intpriority_reg_26 = _RAND_155[3:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
intpriority_reg_27 = _RAND_156[3:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
intpriority_reg_28 = _RAND_157[3:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
intpriority_reg_29 = _RAND_158[3:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
intpriority_reg_30 = _RAND_159[3:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
intpriority_reg_31 = _RAND_160[3:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
_T_1283 = _RAND_161[0:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
_T_1298 = _RAND_162[0:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
_T_1313 = _RAND_163[0:0];
|
|
_RAND_164 = {1{`RANDOM}};
|
|
_T_1328 = _RAND_164[0:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
_T_1343 = _RAND_165[0:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
_T_1358 = _RAND_166[0:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
_T_1373 = _RAND_167[0:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
_T_1388 = _RAND_168[0:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
_T_1403 = _RAND_169[0:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
_T_1418 = _RAND_170[0:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
_T_1433 = _RAND_171[0:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
_T_1448 = _RAND_172[0:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
_T_1463 = _RAND_173[0:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
_T_1478 = _RAND_174[0:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
_T_1493 = _RAND_175[0:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
_T_1508 = _RAND_176[0:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
_T_1523 = _RAND_177[0:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
_T_1538 = _RAND_178[0:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
_T_1553 = _RAND_179[0:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
_T_1568 = _RAND_180[0:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
_T_1583 = _RAND_181[0:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
_T_1598 = _RAND_182[0:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
_T_1613 = _RAND_183[0:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
_T_1628 = _RAND_184[0:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
_T_1643 = _RAND_185[0:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
_T_1658 = _RAND_186[0:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
_T_1673 = _RAND_187[0:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
_T_1688 = _RAND_188[0:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
_T_1703 = _RAND_189[0:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
_T_1718 = _RAND_190[0:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
_T_1733 = _RAND_191[0:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
config_reg = _RAND_192[0:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
_T_2042 = _RAND_193[7:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
_T_2043 = _RAND_194[3:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
_T_2050 = _RAND_195[0:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
_T_2052 = _RAND_196[0:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
picm_raddr_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_waddr_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_wren_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_rden_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_mken_ff = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
picm_wr_data_ff = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
gw_config_reg_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
intenable_reg_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_90 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_94 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_98 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_106 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_114 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_126 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_130 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_134 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_138 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_142 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_146 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_150 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_154 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_158 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_162 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_166 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_170 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_174 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_178 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_182 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_186 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
extintsrc_req_sync_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_1 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_2 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_3 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_4 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_5 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_6 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_7 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_8 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_9 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_10 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_11 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_12 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_13 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_14 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_15 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_16 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_17 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_18 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_19 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_20 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_21 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_22 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_23 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_24 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_25 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_26 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_27 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_28 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_29 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_30 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
intpriority_reg_31 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1283 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1298 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1313 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1328 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1343 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1358 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1373 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1388 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1403 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1418 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1433 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1448 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1463 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1478 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1493 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1508 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1523 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1538 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1553 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1568 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1583 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1598 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1613 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1628 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1643 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1658 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1673 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1688 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1703 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1718 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_1733 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
config_reg = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2042 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2043 = 4'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2050 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_2052 = 1'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
picm_raddr_ff <= 32'h0;
|
|
end else begin
|
|
picm_raddr_ff <= io_lsu_pic_picm_rdaddr;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
picm_waddr_ff <= 32'h0;
|
|
end else begin
|
|
picm_waddr_ff <= io_lsu_pic_picm_wraddr;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_wren_ff <= 1'h0;
|
|
end else begin
|
|
picm_wren_ff <= io_lsu_pic_picm_wren;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_rden_ff <= 1'h0;
|
|
end else begin
|
|
picm_rden_ff <= io_lsu_pic_picm_rden;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
picm_mken_ff <= 1'h0;
|
|
end else begin
|
|
picm_mken_ff <= io_lsu_pic_picm_mken;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
picm_wr_data_ff <= 32'h0;
|
|
end else begin
|
|
picm_wr_data_ff <= io_lsu_pic_picm_wr_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_31 <= 2'h0;
|
|
end else if (gw_config_reg_we_31) begin
|
|
gw_config_reg_31 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_31 <= 1'h0;
|
|
end else if (intenable_reg_we_31) begin
|
|
intenable_reg_31 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_30 <= 2'h0;
|
|
end else if (gw_config_reg_we_30) begin
|
|
gw_config_reg_30 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_30 <= 1'h0;
|
|
end else if (intenable_reg_we_30) begin
|
|
intenable_reg_30 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_29 <= 2'h0;
|
|
end else if (gw_config_reg_we_29) begin
|
|
gw_config_reg_29 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_29 <= 1'h0;
|
|
end else if (intenable_reg_we_29) begin
|
|
intenable_reg_29 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_28 <= 2'h0;
|
|
end else if (gw_config_reg_we_28) begin
|
|
gw_config_reg_28 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_28 <= 1'h0;
|
|
end else if (intenable_reg_we_28) begin
|
|
intenable_reg_28 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_27 <= 2'h0;
|
|
end else if (gw_config_reg_we_27) begin
|
|
gw_config_reg_27 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_27 <= 1'h0;
|
|
end else if (intenable_reg_we_27) begin
|
|
intenable_reg_27 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_26 <= 2'h0;
|
|
end else if (gw_config_reg_we_26) begin
|
|
gw_config_reg_26 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_26 <= 1'h0;
|
|
end else if (intenable_reg_we_26) begin
|
|
intenable_reg_26 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_25 <= 2'h0;
|
|
end else if (gw_config_reg_we_25) begin
|
|
gw_config_reg_25 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_25 <= 1'h0;
|
|
end else if (intenable_reg_we_25) begin
|
|
intenable_reg_25 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_24 <= 2'h0;
|
|
end else if (gw_config_reg_we_24) begin
|
|
gw_config_reg_24 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_24 <= 1'h0;
|
|
end else if (intenable_reg_we_24) begin
|
|
intenable_reg_24 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_23 <= 2'h0;
|
|
end else if (gw_config_reg_we_23) begin
|
|
gw_config_reg_23 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_23 <= 1'h0;
|
|
end else if (intenable_reg_we_23) begin
|
|
intenable_reg_23 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_22 <= 2'h0;
|
|
end else if (gw_config_reg_we_22) begin
|
|
gw_config_reg_22 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_22 <= 1'h0;
|
|
end else if (intenable_reg_we_22) begin
|
|
intenable_reg_22 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_21 <= 2'h0;
|
|
end else if (gw_config_reg_we_21) begin
|
|
gw_config_reg_21 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_21 <= 1'h0;
|
|
end else if (intenable_reg_we_21) begin
|
|
intenable_reg_21 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_20 <= 2'h0;
|
|
end else if (gw_config_reg_we_20) begin
|
|
gw_config_reg_20 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_20 <= 1'h0;
|
|
end else if (intenable_reg_we_20) begin
|
|
intenable_reg_20 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_19 <= 2'h0;
|
|
end else if (gw_config_reg_we_19) begin
|
|
gw_config_reg_19 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_19 <= 1'h0;
|
|
end else if (intenable_reg_we_19) begin
|
|
intenable_reg_19 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_18 <= 2'h0;
|
|
end else if (gw_config_reg_we_18) begin
|
|
gw_config_reg_18 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_18 <= 1'h0;
|
|
end else if (intenable_reg_we_18) begin
|
|
intenable_reg_18 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_17 <= 2'h0;
|
|
end else if (gw_config_reg_we_17) begin
|
|
gw_config_reg_17 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_17 <= 1'h0;
|
|
end else if (intenable_reg_we_17) begin
|
|
intenable_reg_17 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_16 <= 2'h0;
|
|
end else if (gw_config_reg_we_16) begin
|
|
gw_config_reg_16 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_16 <= 1'h0;
|
|
end else if (intenable_reg_we_16) begin
|
|
intenable_reg_16 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_15 <= 2'h0;
|
|
end else if (gw_config_reg_we_15) begin
|
|
gw_config_reg_15 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_15 <= 1'h0;
|
|
end else if (intenable_reg_we_15) begin
|
|
intenable_reg_15 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_14 <= 2'h0;
|
|
end else if (gw_config_reg_we_14) begin
|
|
gw_config_reg_14 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_14 <= 1'h0;
|
|
end else if (intenable_reg_we_14) begin
|
|
intenable_reg_14 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_13 <= 2'h0;
|
|
end else if (gw_config_reg_we_13) begin
|
|
gw_config_reg_13 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_13 <= 1'h0;
|
|
end else if (intenable_reg_we_13) begin
|
|
intenable_reg_13 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_12 <= 2'h0;
|
|
end else if (gw_config_reg_we_12) begin
|
|
gw_config_reg_12 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_12 <= 1'h0;
|
|
end else if (intenable_reg_we_12) begin
|
|
intenable_reg_12 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_11 <= 2'h0;
|
|
end else if (gw_config_reg_we_11) begin
|
|
gw_config_reg_11 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_11 <= 1'h0;
|
|
end else if (intenable_reg_we_11) begin
|
|
intenable_reg_11 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_10 <= 2'h0;
|
|
end else if (gw_config_reg_we_10) begin
|
|
gw_config_reg_10 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_10 <= 1'h0;
|
|
end else if (intenable_reg_we_10) begin
|
|
intenable_reg_10 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_9 <= 2'h0;
|
|
end else if (gw_config_reg_we_9) begin
|
|
gw_config_reg_9 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_9 <= 1'h0;
|
|
end else if (intenable_reg_we_9) begin
|
|
intenable_reg_9 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_8 <= 2'h0;
|
|
end else if (gw_config_reg_we_8) begin
|
|
gw_config_reg_8 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_8 <= 1'h0;
|
|
end else if (intenable_reg_we_8) begin
|
|
intenable_reg_8 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_7 <= 2'h0;
|
|
end else if (gw_config_reg_we_7) begin
|
|
gw_config_reg_7 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_7 <= 1'h0;
|
|
end else if (intenable_reg_we_7) begin
|
|
intenable_reg_7 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_6 <= 2'h0;
|
|
end else if (gw_config_reg_we_6) begin
|
|
gw_config_reg_6 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_6 <= 1'h0;
|
|
end else if (intenable_reg_we_6) begin
|
|
intenable_reg_6 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_5 <= 2'h0;
|
|
end else if (gw_config_reg_we_5) begin
|
|
gw_config_reg_5 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_5 <= 1'h0;
|
|
end else if (intenable_reg_we_5) begin
|
|
intenable_reg_5 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_4 <= 2'h0;
|
|
end else if (gw_config_reg_we_4) begin
|
|
gw_config_reg_4 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_4 <= 1'h0;
|
|
end else if (intenable_reg_we_4) begin
|
|
intenable_reg_4 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_3 <= 2'h0;
|
|
end else if (gw_config_reg_we_3) begin
|
|
gw_config_reg_3 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_3 <= 1'h0;
|
|
end else if (intenable_reg_we_3) begin
|
|
intenable_reg_3 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_2 <= 2'h0;
|
|
end else if (gw_config_reg_we_2) begin
|
|
gw_config_reg_2 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_2 <= 1'h0;
|
|
end else if (intenable_reg_we_2) begin
|
|
intenable_reg_2 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
gw_config_reg_1 <= 2'h0;
|
|
end else if (gw_config_reg_we_1) begin
|
|
gw_config_reg_1 <= picm_wr_data_ff[1:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intenable_reg_1 <= 1'h0;
|
|
end else if (intenable_reg_we_1) begin
|
|
intenable_reg_1 <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_66 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_66 <= io_extintsrc_req[1];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_1 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
extintsrc_req_sync_1 <= _T_66;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_70 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_70 <= io_extintsrc_req[2];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_2 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
extintsrc_req_sync_2 <= _T_70;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_74 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_74 <= io_extintsrc_req[3];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_3 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
extintsrc_req_sync_3 <= _T_74;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_78 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_78 <= io_extintsrc_req[4];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_4 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
extintsrc_req_sync_4 <= _T_78;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_82 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_82 <= io_extintsrc_req[5];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_5 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
extintsrc_req_sync_5 <= _T_82;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_86 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_86 <= io_extintsrc_req[6];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_6 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
extintsrc_req_sync_6 <= _T_86;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_90 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_90 <= io_extintsrc_req[7];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_7 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
extintsrc_req_sync_7 <= _T_90;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_94 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_94 <= io_extintsrc_req[8];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_8 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
extintsrc_req_sync_8 <= _T_94;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_98 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_98 <= io_extintsrc_req[9];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_9 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
extintsrc_req_sync_9 <= _T_98;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_102 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_102 <= io_extintsrc_req[10];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_10 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
extintsrc_req_sync_10 <= _T_102;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_106 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_106 <= io_extintsrc_req[11];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_11 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
extintsrc_req_sync_11 <= _T_106;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_110 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_110 <= io_extintsrc_req[12];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_12 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
extintsrc_req_sync_12 <= _T_110;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_114 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_114 <= io_extintsrc_req[13];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_13 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
extintsrc_req_sync_13 <= _T_114;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_118 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_118 <= io_extintsrc_req[14];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_14 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
extintsrc_req_sync_14 <= _T_118;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_122 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_122 <= io_extintsrc_req[15];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_15 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
extintsrc_req_sync_15 <= _T_122;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_126 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_126 <= io_extintsrc_req[16];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_16 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
extintsrc_req_sync_16 <= _T_126;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_130 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_130 <= io_extintsrc_req[17];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_17 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
extintsrc_req_sync_17 <= _T_130;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_134 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_134 <= io_extintsrc_req[18];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_18 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
extintsrc_req_sync_18 <= _T_134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_138 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_138 <= io_extintsrc_req[19];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_19 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
extintsrc_req_sync_19 <= _T_138;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_142 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_142 <= io_extintsrc_req[20];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_20 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
extintsrc_req_sync_20 <= _T_142;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_146 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_146 <= io_extintsrc_req[21];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_21 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
extintsrc_req_sync_21 <= _T_146;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_150 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_150 <= io_extintsrc_req[22];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_22 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
extintsrc_req_sync_22 <= _T_150;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_154 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_154 <= io_extintsrc_req[23];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_23 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
extintsrc_req_sync_23 <= _T_154;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_158 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_158 <= io_extintsrc_req[24];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_24 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
extintsrc_req_sync_24 <= _T_158;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_162 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_162 <= io_extintsrc_req[25];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_25 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
extintsrc_req_sync_25 <= _T_162;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_166 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_166 <= io_extintsrc_req[26];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_26 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
extintsrc_req_sync_26 <= _T_166;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_170 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_170 <= io_extintsrc_req[27];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_27 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
extintsrc_req_sync_27 <= _T_170;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_174 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_174 <= io_extintsrc_req[28];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_28 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
extintsrc_req_sync_28 <= _T_174;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_178 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_178 <= io_extintsrc_req[29];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_29 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
extintsrc_req_sync_29 <= _T_178;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_182 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_182 <= io_extintsrc_req[30];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_30 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
extintsrc_req_sync_30 <= _T_182;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_186 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_186 <= io_extintsrc_req[31];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
extintsrc_req_sync_31 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
extintsrc_req_sync_31 <= _T_186;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_1 <= 4'h0;
|
|
end else if (intpriority_reg_we_1) begin
|
|
intpriority_reg_1 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_2 <= 4'h0;
|
|
end else if (intpriority_reg_we_2) begin
|
|
intpriority_reg_2 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_3 <= 4'h0;
|
|
end else if (intpriority_reg_we_3) begin
|
|
intpriority_reg_3 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_4 <= 4'h0;
|
|
end else if (intpriority_reg_we_4) begin
|
|
intpriority_reg_4 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_5 <= 4'h0;
|
|
end else if (intpriority_reg_we_5) begin
|
|
intpriority_reg_5 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_6 <= 4'h0;
|
|
end else if (intpriority_reg_we_6) begin
|
|
intpriority_reg_6 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_7 <= 4'h0;
|
|
end else if (intpriority_reg_we_7) begin
|
|
intpriority_reg_7 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_8 <= 4'h0;
|
|
end else if (intpriority_reg_we_8) begin
|
|
intpriority_reg_8 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_9 <= 4'h0;
|
|
end else if (intpriority_reg_we_9) begin
|
|
intpriority_reg_9 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_10 <= 4'h0;
|
|
end else if (intpriority_reg_we_10) begin
|
|
intpriority_reg_10 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_11 <= 4'h0;
|
|
end else if (intpriority_reg_we_11) begin
|
|
intpriority_reg_11 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_12 <= 4'h0;
|
|
end else if (intpriority_reg_we_12) begin
|
|
intpriority_reg_12 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_13 <= 4'h0;
|
|
end else if (intpriority_reg_we_13) begin
|
|
intpriority_reg_13 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_14 <= 4'h0;
|
|
end else if (intpriority_reg_we_14) begin
|
|
intpriority_reg_14 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_15 <= 4'h0;
|
|
end else if (intpriority_reg_we_15) begin
|
|
intpriority_reg_15 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_16 <= 4'h0;
|
|
end else if (intpriority_reg_we_16) begin
|
|
intpriority_reg_16 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_17 <= 4'h0;
|
|
end else if (intpriority_reg_we_17) begin
|
|
intpriority_reg_17 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_18 <= 4'h0;
|
|
end else if (intpriority_reg_we_18) begin
|
|
intpriority_reg_18 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_19 <= 4'h0;
|
|
end else if (intpriority_reg_we_19) begin
|
|
intpriority_reg_19 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_20 <= 4'h0;
|
|
end else if (intpriority_reg_we_20) begin
|
|
intpriority_reg_20 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_21 <= 4'h0;
|
|
end else if (intpriority_reg_we_21) begin
|
|
intpriority_reg_21 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_22 <= 4'h0;
|
|
end else if (intpriority_reg_we_22) begin
|
|
intpriority_reg_22 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_23 <= 4'h0;
|
|
end else if (intpriority_reg_we_23) begin
|
|
intpriority_reg_23 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_24 <= 4'h0;
|
|
end else if (intpriority_reg_we_24) begin
|
|
intpriority_reg_24 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_25 <= 4'h0;
|
|
end else if (intpriority_reg_we_25) begin
|
|
intpriority_reg_25 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_26 <= 4'h0;
|
|
end else if (intpriority_reg_we_26) begin
|
|
intpriority_reg_26 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_27 <= 4'h0;
|
|
end else if (intpriority_reg_we_27) begin
|
|
intpriority_reg_27 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_28 <= 4'h0;
|
|
end else if (intpriority_reg_we_28) begin
|
|
intpriority_reg_28 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_29 <= 4'h0;
|
|
end else if (intpriority_reg_we_29) begin
|
|
intpriority_reg_29 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_30 <= 4'h0;
|
|
end else if (intpriority_reg_we_30) begin
|
|
intpriority_reg_30 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
intpriority_reg_31 <= 4'h0;
|
|
end else if (intpriority_reg_we_31) begin
|
|
intpriority_reg_31 <= picm_wr_data_ff[3:0];
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1283 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_1283 <= _T_1282;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1298 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_1298 <= _T_1297;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1313 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_0) begin
|
|
_T_1313 <= _T_1312;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1328 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_1328 <= _T_1327;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1343 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_1343 <= _T_1342;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1358 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_1358 <= _T_1357;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1373 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_1) begin
|
|
_T_1373 <= _T_1372;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1388 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_1388 <= _T_1387;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1403 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_1403 <= _T_1402;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1418 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_1418 <= _T_1417;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1433 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_2) begin
|
|
_T_1433 <= _T_1432;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1448 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_1448 <= _T_1447;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1463 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_1463 <= _T_1462;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1478 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_1478 <= _T_1477;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1493 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_3) begin
|
|
_T_1493 <= _T_1492;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1508 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_1508 <= _T_1507;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1523 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_1523 <= _T_1522;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1538 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_1538 <= _T_1537;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1553 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_4) begin
|
|
_T_1553 <= _T_1552;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1568 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_1568 <= _T_1567;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1583 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_1583 <= _T_1582;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1598 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_1598 <= _T_1597;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1613 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_5) begin
|
|
_T_1613 <= _T_1612;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1628 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_1628 <= _T_1627;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1643 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_1643 <= _T_1642;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1658 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_1658 <= _T_1657;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1673 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_6) begin
|
|
_T_1673 <= _T_1672;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1688 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_1688 <= _T_1687;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1703 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_1703 <= _T_1702;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1718 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_1718 <= _T_1717;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_1733 <= 1'h0;
|
|
end else if (intenable_clk_enable_grp_7) begin
|
|
_T_1733 <= _T_1732;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
config_reg <= 1'h0;
|
|
end else if (config_reg_we) begin
|
|
config_reg <= picm_wr_data_ff[0];
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2042 <= 8'h0;
|
|
end else begin
|
|
_T_2042 <= level_intpend_id_5_0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2043 <= 4'h0;
|
|
end else if (config_reg) begin
|
|
_T_2043 <= _T_2041;
|
|
end else begin
|
|
_T_2043 <= level_intpend_w_prior_en_5_0;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2050 <= 1'h0;
|
|
end else begin
|
|
_T_2050 <= _T_2048 & _T_2049;
|
|
end
|
|
end
|
|
always @(posedge io_free_clk or posedge reset) begin
|
|
if (reset) begin
|
|
_T_2052 <= 1'h0;
|
|
end else begin
|
|
_T_2052 <= pl_in_q == maxint;
|
|
end
|
|
end
|
|
endmodule
|
|
module dma_ctrl(
|
|
input clock,
|
|
input reset,
|
|
input io_dma_bus_clk_en,
|
|
input [1:0] io_dbg_cmd_size,
|
|
output io_dma_dbg_cmd_done,
|
|
output io_dma_dbg_cmd_fail,
|
|
output [31:0] io_dma_dbg_rddata,
|
|
input io_iccm_dma_rvalid,
|
|
input io_iccm_dma_ecc_error,
|
|
input [2:0] io_iccm_dma_rtag,
|
|
input [63:0] io_iccm_dma_rdata,
|
|
input io_iccm_ready,
|
|
input io_dbg_dec_dma_dbg_ib_dbg_cmd_valid,
|
|
input io_dbg_dec_dma_dbg_ib_dbg_cmd_write,
|
|
input [1:0] io_dbg_dec_dma_dbg_ib_dbg_cmd_type,
|
|
input [31:0] io_dbg_dec_dma_dbg_ib_dbg_cmd_addr,
|
|
input [31:0] io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata,
|
|
input io_dbg_dma_dbg_dma_bubble,
|
|
output io_dbg_dma_dma_dbg_ready,
|
|
output io_dec_dma_dctl_dma_dma_dccm_stall_any,
|
|
output io_dec_dma_tlu_dma_dma_pmu_dccm_read,
|
|
output io_dec_dma_tlu_dma_dma_pmu_dccm_write,
|
|
output io_dec_dma_tlu_dma_dma_pmu_any_read,
|
|
output io_dec_dma_tlu_dma_dma_pmu_any_write,
|
|
input [2:0] io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty,
|
|
output io_dec_dma_tlu_dma_dma_dccm_stall_any,
|
|
output io_dec_dma_tlu_dma_dma_iccm_stall_any,
|
|
output io_lsu_dma_dma_lsc_ctl_dma_dccm_req,
|
|
output [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr,
|
|
output [2:0] io_lsu_dma_dma_lsc_ctl_dma_mem_sz,
|
|
output io_lsu_dma_dma_lsc_ctl_dma_mem_write,
|
|
output [63:0] io_lsu_dma_dma_lsc_ctl_dma_mem_wdata,
|
|
output [31:0] io_lsu_dma_dma_dccm_ctl_dma_mem_addr,
|
|
output [63:0] io_lsu_dma_dma_dccm_ctl_dma_mem_wdata,
|
|
input io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
|
|
input io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error,
|
|
input [2:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag,
|
|
input [63:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata,
|
|
input io_lsu_dma_dccm_ready,
|
|
output [2:0] io_lsu_dma_dma_mem_tag,
|
|
output io_ifu_dma_dma_ifc_dma_iccm_stall_any,
|
|
output io_ifu_dma_dma_mem_ctl_dma_iccm_req,
|
|
output [31:0] io_ifu_dma_dma_mem_ctl_dma_mem_addr,
|
|
output [2:0] io_ifu_dma_dma_mem_ctl_dma_mem_sz,
|
|
output io_ifu_dma_dma_mem_ctl_dma_mem_write,
|
|
output [63:0] io_ifu_dma_dma_mem_ctl_dma_mem_wdata,
|
|
output [2:0] io_ifu_dma_dma_mem_ctl_dma_mem_tag,
|
|
output io_dma_axi_aw_ready,
|
|
input io_dma_axi_aw_valid,
|
|
input io_dma_axi_aw_bits_id,
|
|
input [31:0] io_dma_axi_aw_bits_addr,
|
|
input [2:0] io_dma_axi_aw_bits_size,
|
|
output io_dma_axi_w_ready,
|
|
input io_dma_axi_w_valid,
|
|
input [63:0] io_dma_axi_w_bits_data,
|
|
input [7:0] io_dma_axi_w_bits_strb,
|
|
input io_dma_axi_b_ready,
|
|
output io_dma_axi_b_valid,
|
|
output [1:0] io_dma_axi_b_bits_resp,
|
|
output io_dma_axi_b_bits_id,
|
|
output io_dma_axi_ar_ready,
|
|
input io_dma_axi_ar_valid,
|
|
input io_dma_axi_ar_bits_id,
|
|
input [31:0] io_dma_axi_ar_bits_addr,
|
|
input [2:0] io_dma_axi_ar_bits_size,
|
|
input io_dma_axi_r_ready,
|
|
output io_dma_axi_r_valid,
|
|
output io_dma_axi_r_bits_id,
|
|
output [63:0] io_dma_axi_r_bits_data,
|
|
output [1:0] io_dma_axi_r_bits_resp
|
|
);
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
reg [31:0] _RAND_0;
|
|
reg [31:0] _RAND_1;
|
|
reg [31:0] _RAND_2;
|
|
reg [31:0] _RAND_3;
|
|
reg [31:0] _RAND_4;
|
|
reg [31:0] _RAND_5;
|
|
reg [31:0] _RAND_6;
|
|
reg [31:0] _RAND_7;
|
|
reg [31:0] _RAND_8;
|
|
reg [31:0] _RAND_9;
|
|
reg [31:0] _RAND_10;
|
|
reg [31:0] _RAND_11;
|
|
reg [31:0] _RAND_12;
|
|
reg [31:0] _RAND_13;
|
|
reg [31:0] _RAND_14;
|
|
reg [31:0] _RAND_15;
|
|
reg [31:0] _RAND_16;
|
|
reg [31:0] _RAND_17;
|
|
reg [31:0] _RAND_18;
|
|
reg [31:0] _RAND_19;
|
|
reg [31:0] _RAND_20;
|
|
reg [31:0] _RAND_21;
|
|
reg [31:0] _RAND_22;
|
|
reg [31:0] _RAND_23;
|
|
reg [31:0] _RAND_24;
|
|
reg [31:0] _RAND_25;
|
|
reg [31:0] _RAND_26;
|
|
reg [31:0] _RAND_27;
|
|
reg [31:0] _RAND_28;
|
|
reg [31:0] _RAND_29;
|
|
reg [31:0] _RAND_30;
|
|
reg [31:0] _RAND_31;
|
|
reg [31:0] _RAND_32;
|
|
reg [31:0] _RAND_33;
|
|
reg [31:0] _RAND_34;
|
|
reg [31:0] _RAND_35;
|
|
reg [31:0] _RAND_36;
|
|
reg [31:0] _RAND_37;
|
|
reg [31:0] _RAND_38;
|
|
reg [31:0] _RAND_39;
|
|
reg [31:0] _RAND_40;
|
|
reg [31:0] _RAND_41;
|
|
reg [31:0] _RAND_42;
|
|
reg [31:0] _RAND_43;
|
|
reg [31:0] _RAND_44;
|
|
reg [31:0] _RAND_45;
|
|
reg [31:0] _RAND_46;
|
|
reg [31:0] _RAND_47;
|
|
reg [31:0] _RAND_48;
|
|
reg [31:0] _RAND_49;
|
|
reg [31:0] _RAND_50;
|
|
reg [31:0] _RAND_51;
|
|
reg [31:0] _RAND_52;
|
|
reg [31:0] _RAND_53;
|
|
reg [31:0] _RAND_54;
|
|
reg [31:0] _RAND_55;
|
|
reg [31:0] _RAND_56;
|
|
reg [31:0] _RAND_57;
|
|
reg [31:0] _RAND_58;
|
|
reg [31:0] _RAND_59;
|
|
reg [31:0] _RAND_60;
|
|
reg [31:0] _RAND_61;
|
|
reg [31:0] _RAND_62;
|
|
reg [31:0] _RAND_63;
|
|
reg [31:0] _RAND_64;
|
|
reg [31:0] _RAND_65;
|
|
reg [31:0] _RAND_66;
|
|
reg [31:0] _RAND_67;
|
|
reg [31:0] _RAND_68;
|
|
reg [31:0] _RAND_69;
|
|
reg [31:0] _RAND_70;
|
|
reg [31:0] _RAND_71;
|
|
reg [31:0] _RAND_72;
|
|
reg [31:0] _RAND_73;
|
|
reg [31:0] _RAND_74;
|
|
reg [31:0] _RAND_75;
|
|
reg [31:0] _RAND_76;
|
|
reg [31:0] _RAND_77;
|
|
reg [31:0] _RAND_78;
|
|
reg [31:0] _RAND_79;
|
|
reg [31:0] _RAND_80;
|
|
reg [31:0] _RAND_81;
|
|
reg [31:0] _RAND_82;
|
|
reg [31:0] _RAND_83;
|
|
reg [31:0] _RAND_84;
|
|
reg [31:0] _RAND_85;
|
|
reg [31:0] _RAND_86;
|
|
reg [31:0] _RAND_87;
|
|
reg [31:0] _RAND_88;
|
|
reg [31:0] _RAND_89;
|
|
reg [31:0] _RAND_90;
|
|
reg [31:0] _RAND_91;
|
|
reg [31:0] _RAND_92;
|
|
reg [31:0] _RAND_93;
|
|
reg [31:0] _RAND_94;
|
|
reg [31:0] _RAND_95;
|
|
reg [31:0] _RAND_96;
|
|
reg [31:0] _RAND_97;
|
|
reg [31:0] _RAND_98;
|
|
reg [31:0] _RAND_99;
|
|
reg [31:0] _RAND_100;
|
|
reg [31:0] _RAND_101;
|
|
reg [31:0] _RAND_102;
|
|
reg [31:0] _RAND_103;
|
|
reg [31:0] _RAND_104;
|
|
reg [31:0] _RAND_105;
|
|
reg [31:0] _RAND_106;
|
|
reg [31:0] _RAND_107;
|
|
reg [31:0] _RAND_108;
|
|
reg [31:0] _RAND_109;
|
|
reg [31:0] _RAND_110;
|
|
reg [31:0] _RAND_111;
|
|
reg [31:0] _RAND_112;
|
|
reg [31:0] _RAND_113;
|
|
reg [31:0] _RAND_114;
|
|
reg [31:0] _RAND_115;
|
|
reg [31:0] _RAND_116;
|
|
reg [31:0] _RAND_117;
|
|
reg [31:0] _RAND_118;
|
|
reg [31:0] _RAND_119;
|
|
reg [31:0] _RAND_120;
|
|
reg [31:0] _RAND_121;
|
|
reg [31:0] _RAND_122;
|
|
reg [31:0] _RAND_123;
|
|
reg [31:0] _RAND_124;
|
|
reg [31:0] _RAND_125;
|
|
reg [31:0] _RAND_126;
|
|
reg [31:0] _RAND_127;
|
|
reg [31:0] _RAND_128;
|
|
reg [31:0] _RAND_129;
|
|
reg [31:0] _RAND_130;
|
|
reg [31:0] _RAND_131;
|
|
reg [31:0] _RAND_132;
|
|
reg [31:0] _RAND_133;
|
|
reg [31:0] _RAND_134;
|
|
reg [31:0] _RAND_135;
|
|
reg [31:0] _RAND_136;
|
|
reg [31:0] _RAND_137;
|
|
reg [31:0] _RAND_138;
|
|
reg [31:0] _RAND_139;
|
|
reg [31:0] _RAND_140;
|
|
reg [31:0] _RAND_141;
|
|
reg [31:0] _RAND_142;
|
|
reg [31:0] _RAND_143;
|
|
reg [31:0] _RAND_144;
|
|
reg [31:0] _RAND_145;
|
|
reg [31:0] _RAND_146;
|
|
reg [31:0] _RAND_147;
|
|
reg [31:0] _RAND_148;
|
|
reg [31:0] _RAND_149;
|
|
reg [31:0] _RAND_150;
|
|
reg [31:0] _RAND_151;
|
|
reg [31:0] _RAND_152;
|
|
reg [31:0] _RAND_153;
|
|
reg [31:0] _RAND_154;
|
|
reg [31:0] _RAND_155;
|
|
reg [31:0] _RAND_156;
|
|
reg [31:0] _RAND_157;
|
|
reg [31:0] _RAND_158;
|
|
reg [31:0] _RAND_159;
|
|
reg [31:0] _RAND_160;
|
|
reg [31:0] _RAND_161;
|
|
reg [31:0] _RAND_162;
|
|
reg [31:0] _RAND_163;
|
|
reg [31:0] _RAND_164;
|
|
reg [31:0] _RAND_165;
|
|
reg [31:0] _RAND_166;
|
|
reg [31:0] _RAND_167;
|
|
reg [31:0] _RAND_168;
|
|
reg [31:0] _RAND_169;
|
|
reg [31:0] _RAND_170;
|
|
reg [31:0] _RAND_171;
|
|
reg [31:0] _RAND_172;
|
|
reg [31:0] _RAND_173;
|
|
reg [31:0] _RAND_174;
|
|
reg [31:0] _RAND_175;
|
|
reg [31:0] _RAND_176;
|
|
reg [31:0] _RAND_177;
|
|
reg [31:0] _RAND_178;
|
|
reg [31:0] _RAND_179;
|
|
reg [31:0] _RAND_180;
|
|
reg [31:0] _RAND_181;
|
|
reg [31:0] _RAND_182;
|
|
reg [31:0] _RAND_183;
|
|
reg [31:0] _RAND_184;
|
|
reg [31:0] _RAND_185;
|
|
reg [31:0] _RAND_186;
|
|
reg [31:0] _RAND_187;
|
|
reg [31:0] _RAND_188;
|
|
reg [31:0] _RAND_189;
|
|
reg [31:0] _RAND_190;
|
|
reg [31:0] _RAND_191;
|
|
reg [31:0] _RAND_192;
|
|
reg [31:0] _RAND_193;
|
|
reg [31:0] _RAND_194;
|
|
reg [31:0] _RAND_195;
|
|
reg [31:0] _RAND_196;
|
|
reg [31:0] _RAND_197;
|
|
reg [31:0] _RAND_198;
|
|
reg [31:0] _RAND_199;
|
|
reg [31:0] _RAND_200;
|
|
reg [31:0] _RAND_201;
|
|
reg [31:0] _RAND_202;
|
|
reg [31:0] _RAND_203;
|
|
reg [31:0] _RAND_204;
|
|
reg [31:0] _RAND_205;
|
|
reg [31:0] _RAND_206;
|
|
reg [31:0] _RAND_207;
|
|
reg [31:0] _RAND_208;
|
|
reg [31:0] _RAND_209;
|
|
reg [31:0] _RAND_210;
|
|
reg [31:0] _RAND_211;
|
|
reg [31:0] _RAND_212;
|
|
reg [31:0] _RAND_213;
|
|
reg [31:0] _RAND_214;
|
|
reg [31:0] _RAND_215;
|
|
reg [31:0] _RAND_216;
|
|
reg [31:0] _RAND_217;
|
|
reg [31:0] _RAND_218;
|
|
reg [31:0] _RAND_219;
|
|
reg [31:0] _RAND_220;
|
|
reg [31:0] _RAND_221;
|
|
reg [31:0] _RAND_222;
|
|
reg [31:0] _RAND_223;
|
|
reg [31:0] _RAND_224;
|
|
reg [31:0] _RAND_225;
|
|
reg [31:0] _RAND_226;
|
|
reg [31:0] _RAND_227;
|
|
reg [31:0] _RAND_228;
|
|
reg [31:0] _RAND_229;
|
|
reg [31:0] _RAND_230;
|
|
reg [31:0] _RAND_231;
|
|
reg [31:0] _RAND_232;
|
|
reg [31:0] _RAND_233;
|
|
reg [31:0] _RAND_234;
|
|
reg [31:0] _RAND_235;
|
|
reg [31:0] _RAND_236;
|
|
reg [31:0] _RAND_237;
|
|
reg [31:0] _RAND_238;
|
|
reg [31:0] _RAND_239;
|
|
reg [31:0] _RAND_240;
|
|
reg [31:0] _RAND_241;
|
|
reg [31:0] _RAND_242;
|
|
reg [31:0] _RAND_243;
|
|
reg [31:0] _RAND_244;
|
|
reg [31:0] _RAND_245;
|
|
reg [31:0] _RAND_246;
|
|
reg [31:0] _RAND_247;
|
|
reg [31:0] _RAND_248;
|
|
reg [31:0] _RAND_249;
|
|
reg [31:0] _RAND_250;
|
|
reg [31:0] _RAND_251;
|
|
reg [31:0] _RAND_252;
|
|
reg [31:0] _RAND_253;
|
|
reg [31:0] _RAND_254;
|
|
reg [31:0] _RAND_255;
|
|
reg [31:0] _RAND_256;
|
|
reg [31:0] _RAND_257;
|
|
reg [31:0] _RAND_258;
|
|
reg [31:0] _RAND_259;
|
|
reg [31:0] _RAND_260;
|
|
reg [31:0] _RAND_261;
|
|
reg [31:0] _RAND_262;
|
|
reg [31:0] _RAND_263;
|
|
reg [31:0] _RAND_264;
|
|
reg [31:0] _RAND_265;
|
|
reg [31:0] _RAND_266;
|
|
reg [31:0] _RAND_267;
|
|
reg [31:0] _RAND_268;
|
|
reg [31:0] _RAND_269;
|
|
reg [31:0] _RAND_270;
|
|
reg [31:0] _RAND_271;
|
|
reg [31:0] _RAND_272;
|
|
reg [31:0] _RAND_273;
|
|
reg [31:0] _RAND_274;
|
|
reg [31:0] _RAND_275;
|
|
reg [31:0] _RAND_276;
|
|
reg [31:0] _RAND_277;
|
|
reg [31:0] _RAND_278;
|
|
reg [31:0] _RAND_279;
|
|
reg [31:0] _RAND_280;
|
|
reg [31:0] _RAND_281;
|
|
reg [31:0] _RAND_282;
|
|
reg [31:0] _RAND_283;
|
|
reg [31:0] _RAND_284;
|
|
reg [31:0] _RAND_285;
|
|
reg [31:0] _RAND_286;
|
|
reg [31:0] _RAND_287;
|
|
reg [31:0] _RAND_288;
|
|
reg [31:0] _RAND_289;
|
|
reg [31:0] _RAND_290;
|
|
reg [31:0] _RAND_291;
|
|
reg [31:0] _RAND_292;
|
|
reg [31:0] _RAND_293;
|
|
reg [31:0] _RAND_294;
|
|
reg [31:0] _RAND_295;
|
|
reg [31:0] _RAND_296;
|
|
reg [31:0] _RAND_297;
|
|
reg [31:0] _RAND_298;
|
|
reg [31:0] _RAND_299;
|
|
reg [31:0] _RAND_300;
|
|
reg [31:0] _RAND_301;
|
|
reg [31:0] _RAND_302;
|
|
reg [31:0] _RAND_303;
|
|
reg [31:0] _RAND_304;
|
|
reg [31:0] _RAND_305;
|
|
reg [31:0] _RAND_306;
|
|
reg [31:0] _RAND_307;
|
|
reg [31:0] _RAND_308;
|
|
reg [31:0] _RAND_309;
|
|
reg [31:0] _RAND_310;
|
|
reg [31:0] _RAND_311;
|
|
reg [31:0] _RAND_312;
|
|
reg [31:0] _RAND_313;
|
|
reg [31:0] _RAND_314;
|
|
reg [31:0] _RAND_315;
|
|
reg [31:0] _RAND_316;
|
|
reg [31:0] _RAND_317;
|
|
reg [31:0] _RAND_318;
|
|
reg [31:0] _RAND_319;
|
|
reg [31:0] _RAND_320;
|
|
reg [31:0] _RAND_321;
|
|
reg [31:0] _RAND_322;
|
|
reg [31:0] _RAND_323;
|
|
reg [31:0] _RAND_324;
|
|
reg [31:0] _RAND_325;
|
|
reg [31:0] _RAND_326;
|
|
reg [31:0] _RAND_327;
|
|
reg [31:0] _RAND_328;
|
|
reg [31:0] _RAND_329;
|
|
reg [31:0] _RAND_330;
|
|
reg [31:0] _RAND_331;
|
|
reg [31:0] _RAND_332;
|
|
reg [31:0] _RAND_333;
|
|
reg [31:0] _RAND_334;
|
|
reg [31:0] _RAND_335;
|
|
reg [31:0] _RAND_336;
|
|
reg [31:0] _RAND_337;
|
|
reg [31:0] _RAND_338;
|
|
reg [31:0] _RAND_339;
|
|
reg [31:0] _RAND_340;
|
|
reg [31:0] _RAND_341;
|
|
reg [31:0] _RAND_342;
|
|
reg [31:0] _RAND_343;
|
|
reg [31:0] _RAND_344;
|
|
reg [31:0] _RAND_345;
|
|
reg [31:0] _RAND_346;
|
|
reg [31:0] _RAND_347;
|
|
reg [31:0] _RAND_348;
|
|
reg [31:0] _RAND_349;
|
|
reg [31:0] _RAND_350;
|
|
reg [31:0] _RAND_351;
|
|
reg [31:0] _RAND_352;
|
|
reg [31:0] _RAND_353;
|
|
reg [31:0] _RAND_354;
|
|
reg [31:0] _RAND_355;
|
|
reg [31:0] _RAND_356;
|
|
reg [31:0] _RAND_357;
|
|
reg [31:0] _RAND_358;
|
|
reg [31:0] _RAND_359;
|
|
reg [31:0] _RAND_360;
|
|
reg [31:0] _RAND_361;
|
|
reg [31:0] _RAND_362;
|
|
reg [31:0] _RAND_363;
|
|
reg [31:0] _RAND_364;
|
|
reg [31:0] _RAND_365;
|
|
reg [31:0] _RAND_366;
|
|
reg [31:0] _RAND_367;
|
|
reg [31:0] _RAND_368;
|
|
reg [31:0] _RAND_369;
|
|
reg [31:0] _RAND_370;
|
|
reg [31:0] _RAND_371;
|
|
reg [31:0] _RAND_372;
|
|
reg [31:0] _RAND_373;
|
|
reg [31:0] _RAND_374;
|
|
reg [31:0] _RAND_375;
|
|
reg [31:0] _RAND_376;
|
|
reg [31:0] _RAND_377;
|
|
reg [31:0] _RAND_378;
|
|
reg [31:0] _RAND_379;
|
|
reg [31:0] _RAND_380;
|
|
reg [31:0] _RAND_381;
|
|
reg [31:0] _RAND_382;
|
|
reg [31:0] _RAND_383;
|
|
reg [31:0] _RAND_384;
|
|
reg [31:0] _RAND_385;
|
|
reg [31:0] _RAND_386;
|
|
reg [31:0] _RAND_387;
|
|
reg [31:0] _RAND_388;
|
|
reg [31:0] _RAND_389;
|
|
reg [31:0] _RAND_390;
|
|
reg [31:0] _RAND_391;
|
|
reg [31:0] _RAND_392;
|
|
reg [31:0] _RAND_393;
|
|
reg [31:0] _RAND_394;
|
|
reg [31:0] _RAND_395;
|
|
reg [31:0] _RAND_396;
|
|
reg [31:0] _RAND_397;
|
|
reg [31:0] _RAND_398;
|
|
reg [31:0] _RAND_399;
|
|
reg [31:0] _RAND_400;
|
|
reg [31:0] _RAND_401;
|
|
reg [31:0] _RAND_402;
|
|
reg [31:0] _RAND_403;
|
|
reg [31:0] _RAND_404;
|
|
reg [31:0] _RAND_405;
|
|
reg [31:0] _RAND_406;
|
|
reg [31:0] _RAND_407;
|
|
reg [31:0] _RAND_408;
|
|
reg [31:0] _RAND_409;
|
|
reg [31:0] _RAND_410;
|
|
reg [31:0] _RAND_411;
|
|
reg [31:0] _RAND_412;
|
|
reg [31:0] _RAND_413;
|
|
reg [31:0] _RAND_414;
|
|
reg [31:0] _RAND_415;
|
|
reg [31:0] _RAND_416;
|
|
reg [31:0] _RAND_417;
|
|
reg [31:0] _RAND_418;
|
|
reg [31:0] _RAND_419;
|
|
reg [31:0] _RAND_420;
|
|
reg [31:0] _RAND_421;
|
|
reg [31:0] _RAND_422;
|
|
reg [31:0] _RAND_423;
|
|
reg [31:0] _RAND_424;
|
|
reg [31:0] _RAND_425;
|
|
reg [31:0] _RAND_426;
|
|
reg [31:0] _RAND_427;
|
|
reg [31:0] _RAND_428;
|
|
reg [31:0] _RAND_429;
|
|
reg [31:0] _RAND_430;
|
|
reg [31:0] _RAND_431;
|
|
reg [31:0] _RAND_432;
|
|
reg [31:0] _RAND_433;
|
|
reg [31:0] _RAND_434;
|
|
reg [31:0] _RAND_435;
|
|
reg [31:0] _RAND_436;
|
|
reg [31:0] _RAND_437;
|
|
reg [31:0] _RAND_438;
|
|
reg [31:0] _RAND_439;
|
|
reg [31:0] _RAND_440;
|
|
reg [31:0] _RAND_441;
|
|
reg [31:0] _RAND_442;
|
|
reg [31:0] _RAND_443;
|
|
reg [31:0] _RAND_444;
|
|
reg [31:0] _RAND_445;
|
|
reg [31:0] _RAND_446;
|
|
reg [31:0] _RAND_447;
|
|
reg [31:0] _RAND_448;
|
|
reg [31:0] _RAND_449;
|
|
reg [31:0] _RAND_450;
|
|
reg [31:0] _RAND_451;
|
|
reg [31:0] _RAND_452;
|
|
reg [31:0] _RAND_453;
|
|
reg [31:0] _RAND_454;
|
|
reg [31:0] _RAND_455;
|
|
reg [31:0] _RAND_456;
|
|
reg [31:0] _RAND_457;
|
|
reg [31:0] _RAND_458;
|
|
reg [31:0] _RAND_459;
|
|
reg [31:0] _RAND_460;
|
|
reg [31:0] _RAND_461;
|
|
reg [31:0] _RAND_462;
|
|
reg [31:0] _RAND_463;
|
|
reg [31:0] _RAND_464;
|
|
reg [31:0] _RAND_465;
|
|
reg [31:0] _RAND_466;
|
|
reg [31:0] _RAND_467;
|
|
reg [31:0] _RAND_468;
|
|
reg [31:0] _RAND_469;
|
|
reg [31:0] _RAND_470;
|
|
reg [31:0] _RAND_471;
|
|
reg [31:0] _RAND_472;
|
|
reg [31:0] _RAND_473;
|
|
reg [31:0] _RAND_474;
|
|
reg [31:0] _RAND_475;
|
|
reg [31:0] _RAND_476;
|
|
reg [31:0] _RAND_477;
|
|
reg [31:0] _RAND_478;
|
|
reg [31:0] _RAND_479;
|
|
reg [31:0] _RAND_480;
|
|
reg [31:0] _RAND_481;
|
|
reg [31:0] _RAND_482;
|
|
reg [31:0] _RAND_483;
|
|
reg [31:0] _RAND_484;
|
|
reg [31:0] _RAND_485;
|
|
reg [31:0] _RAND_486;
|
|
reg [31:0] _RAND_487;
|
|
reg [31:0] _RAND_488;
|
|
reg [31:0] _RAND_489;
|
|
reg [31:0] _RAND_490;
|
|
reg [31:0] _RAND_491;
|
|
reg [31:0] _RAND_492;
|
|
reg [31:0] _RAND_493;
|
|
reg [31:0] _RAND_494;
|
|
reg [31:0] _RAND_495;
|
|
reg [31:0] _RAND_496;
|
|
reg [31:0] _RAND_497;
|
|
reg [31:0] _RAND_498;
|
|
reg [31:0] _RAND_499;
|
|
reg [31:0] _RAND_500;
|
|
reg [31:0] _RAND_501;
|
|
reg [31:0] _RAND_502;
|
|
reg [31:0] _RAND_503;
|
|
reg [31:0] _RAND_504;
|
|
reg [31:0] _RAND_505;
|
|
reg [31:0] _RAND_506;
|
|
reg [31:0] _RAND_507;
|
|
reg [31:0] _RAND_508;
|
|
reg [31:0] _RAND_509;
|
|
reg [31:0] _RAND_510;
|
|
reg [31:0] _RAND_511;
|
|
reg [31:0] _RAND_512;
|
|
reg [31:0] _RAND_513;
|
|
reg [31:0] _RAND_514;
|
|
reg [31:0] _RAND_515;
|
|
reg [31:0] _RAND_516;
|
|
reg [31:0] _RAND_517;
|
|
reg [31:0] _RAND_518;
|
|
reg [31:0] _RAND_519;
|
|
reg [31:0] _RAND_520;
|
|
reg [31:0] _RAND_521;
|
|
reg [31:0] _RAND_522;
|
|
reg [31:0] _RAND_523;
|
|
reg [31:0] _RAND_524;
|
|
reg [31:0] _RAND_525;
|
|
reg [31:0] _RAND_526;
|
|
reg [31:0] _RAND_527;
|
|
reg [31:0] _RAND_528;
|
|
reg [31:0] _RAND_529;
|
|
reg [31:0] _RAND_530;
|
|
reg [31:0] _RAND_531;
|
|
reg [31:0] _RAND_532;
|
|
reg [31:0] _RAND_533;
|
|
reg [31:0] _RAND_534;
|
|
reg [31:0] _RAND_535;
|
|
reg [31:0] _RAND_536;
|
|
reg [31:0] _RAND_537;
|
|
reg [31:0] _RAND_538;
|
|
reg [31:0] _RAND_539;
|
|
reg [31:0] _RAND_540;
|
|
reg [31:0] _RAND_541;
|
|
reg [31:0] _RAND_542;
|
|
reg [31:0] _RAND_543;
|
|
reg [31:0] _RAND_544;
|
|
reg [31:0] _RAND_545;
|
|
reg [31:0] _RAND_546;
|
|
reg [31:0] _RAND_547;
|
|
reg [31:0] _RAND_548;
|
|
reg [31:0] _RAND_549;
|
|
reg [31:0] _RAND_550;
|
|
reg [31:0] _RAND_551;
|
|
reg [31:0] _RAND_552;
|
|
reg [31:0] _RAND_553;
|
|
reg [31:0] _RAND_554;
|
|
reg [31:0] _RAND_555;
|
|
reg [31:0] _RAND_556;
|
|
reg [31:0] _RAND_557;
|
|
reg [31:0] _RAND_558;
|
|
reg [31:0] _RAND_559;
|
|
reg [31:0] _RAND_560;
|
|
reg [31:0] _RAND_561;
|
|
reg [31:0] _RAND_562;
|
|
reg [31:0] _RAND_563;
|
|
reg [31:0] _RAND_564;
|
|
reg [31:0] _RAND_565;
|
|
reg [31:0] _RAND_566;
|
|
reg [31:0] _RAND_567;
|
|
reg [31:0] _RAND_568;
|
|
reg [31:0] _RAND_569;
|
|
reg [31:0] _RAND_570;
|
|
reg [31:0] _RAND_571;
|
|
reg [31:0] _RAND_572;
|
|
reg [31:0] _RAND_573;
|
|
reg [31:0] _RAND_574;
|
|
reg [31:0] _RAND_575;
|
|
reg [31:0] _RAND_576;
|
|
reg [31:0] _RAND_577;
|
|
reg [31:0] _RAND_578;
|
|
reg [31:0] _RAND_579;
|
|
reg [31:0] _RAND_580;
|
|
reg [31:0] _RAND_581;
|
|
reg [31:0] _RAND_582;
|
|
reg [31:0] _RAND_583;
|
|
reg [31:0] _RAND_584;
|
|
reg [31:0] _RAND_585;
|
|
reg [31:0] _RAND_586;
|
|
reg [31:0] _RAND_587;
|
|
reg [31:0] _RAND_588;
|
|
reg [31:0] _RAND_589;
|
|
reg [31:0] _RAND_590;
|
|
reg [31:0] _RAND_591;
|
|
reg [31:0] _RAND_592;
|
|
reg [31:0] _RAND_593;
|
|
reg [31:0] _RAND_594;
|
|
reg [31:0] _RAND_595;
|
|
reg [31:0] _RAND_596;
|
|
reg [31:0] _RAND_597;
|
|
reg [31:0] _RAND_598;
|
|
reg [31:0] _RAND_599;
|
|
reg [31:0] _RAND_600;
|
|
reg [31:0] _RAND_601;
|
|
reg [31:0] _RAND_602;
|
|
reg [31:0] _RAND_603;
|
|
reg [31:0] _RAND_604;
|
|
reg [31:0] _RAND_605;
|
|
reg [31:0] _RAND_606;
|
|
reg [31:0] _RAND_607;
|
|
reg [31:0] _RAND_608;
|
|
reg [31:0] _RAND_609;
|
|
reg [31:0] _RAND_610;
|
|
reg [31:0] _RAND_611;
|
|
reg [31:0] _RAND_612;
|
|
reg [31:0] _RAND_613;
|
|
reg [31:0] _RAND_614;
|
|
reg [31:0] _RAND_615;
|
|
reg [31:0] _RAND_616;
|
|
reg [31:0] _RAND_617;
|
|
reg [31:0] _RAND_618;
|
|
reg [31:0] _RAND_619;
|
|
reg [31:0] _RAND_620;
|
|
reg [31:0] _RAND_621;
|
|
reg [31:0] _RAND_622;
|
|
reg [31:0] _RAND_623;
|
|
reg [31:0] _RAND_624;
|
|
reg [31:0] _RAND_625;
|
|
reg [31:0] _RAND_626;
|
|
reg [31:0] _RAND_627;
|
|
reg [31:0] _RAND_628;
|
|
reg [31:0] _RAND_629;
|
|
reg [31:0] _RAND_630;
|
|
reg [31:0] _RAND_631;
|
|
reg [31:0] _RAND_632;
|
|
reg [31:0] _RAND_633;
|
|
reg [31:0] _RAND_634;
|
|
reg [31:0] _RAND_635;
|
|
reg [31:0] _RAND_636;
|
|
reg [31:0] _RAND_637;
|
|
reg [31:0] _RAND_638;
|
|
reg [31:0] _RAND_639;
|
|
reg [31:0] _RAND_640;
|
|
reg [31:0] _RAND_641;
|
|
reg [31:0] _RAND_642;
|
|
reg [63:0] _RAND_643;
|
|
reg [31:0] _RAND_644;
|
|
reg [31:0] _RAND_645;
|
|
reg [31:0] _RAND_646;
|
|
reg [31:0] _RAND_647;
|
|
reg [31:0] _RAND_648;
|
|
reg [31:0] _RAND_649;
|
|
reg [31:0] _RAND_650;
|
|
reg [31:0] _RAND_651;
|
|
reg [31:0] _RAND_652;
|
|
reg [31:0] _RAND_653;
|
|
reg [31:0] _RAND_654;
|
|
reg [31:0] _RAND_655;
|
|
reg [31:0] _RAND_656;
|
|
reg [31:0] _RAND_657;
|
|
reg [31:0] _RAND_658;
|
|
reg [31:0] _RAND_659;
|
|
reg [31:0] _RAND_660;
|
|
reg [31:0] _RAND_661;
|
|
reg [31:0] _RAND_662;
|
|
reg [31:0] _RAND_663;
|
|
reg [31:0] _RAND_664;
|
|
reg [31:0] _RAND_665;
|
|
reg [31:0] _RAND_666;
|
|
reg [31:0] _RAND_667;
|
|
reg [31:0] _RAND_668;
|
|
reg [31:0] _RAND_669;
|
|
reg [31:0] _RAND_670;
|
|
reg [31:0] _RAND_671;
|
|
reg [31:0] _RAND_672;
|
|
reg [31:0] _RAND_673;
|
|
reg [31:0] _RAND_674;
|
|
reg [31:0] _RAND_675;
|
|
reg [31:0] _RAND_676;
|
|
reg [31:0] _RAND_677;
|
|
reg [31:0] _RAND_678;
|
|
reg [31:0] _RAND_679;
|
|
reg [31:0] _RAND_680;
|
|
reg [31:0] _RAND_681;
|
|
reg [31:0] _RAND_682;
|
|
reg [31:0] _RAND_683;
|
|
reg [31:0] _RAND_684;
|
|
reg [31:0] _RAND_685;
|
|
reg [31:0] _RAND_686;
|
|
reg [31:0] _RAND_687;
|
|
reg [31:0] _RAND_688;
|
|
reg [31:0] _RAND_689;
|
|
reg [31:0] _RAND_690;
|
|
reg [31:0] _RAND_691;
|
|
reg [31:0] _RAND_692;
|
|
reg [31:0] _RAND_693;
|
|
reg [31:0] _RAND_694;
|
|
reg [31:0] _RAND_695;
|
|
reg [31:0] _RAND_696;
|
|
reg [31:0] _RAND_697;
|
|
reg [31:0] _RAND_698;
|
|
reg [31:0] _RAND_699;
|
|
reg [31:0] _RAND_700;
|
|
reg [31:0] _RAND_701;
|
|
reg [31:0] _RAND_702;
|
|
reg [31:0] _RAND_703;
|
|
reg [31:0] _RAND_704;
|
|
reg [31:0] _RAND_705;
|
|
reg [31:0] _RAND_706;
|
|
reg [31:0] _RAND_707;
|
|
reg [31:0] _RAND_708;
|
|
reg [31:0] _RAND_709;
|
|
reg [31:0] _RAND_710;
|
|
reg [31:0] _RAND_711;
|
|
reg [31:0] _RAND_712;
|
|
reg [31:0] _RAND_713;
|
|
reg [31:0] _RAND_714;
|
|
reg [31:0] _RAND_715;
|
|
reg [31:0] _RAND_716;
|
|
reg [31:0] _RAND_717;
|
|
reg [31:0] _RAND_718;
|
|
reg [31:0] _RAND_719;
|
|
reg [31:0] _RAND_720;
|
|
reg [31:0] _RAND_721;
|
|
reg [31:0] _RAND_722;
|
|
reg [31:0] _RAND_723;
|
|
reg [31:0] _RAND_724;
|
|
reg [31:0] _RAND_725;
|
|
reg [31:0] _RAND_726;
|
|
reg [31:0] _RAND_727;
|
|
reg [31:0] _RAND_728;
|
|
reg [31:0] _RAND_729;
|
|
reg [31:0] _RAND_730;
|
|
reg [31:0] _RAND_731;
|
|
reg [31:0] _RAND_732;
|
|
reg [31:0] _RAND_733;
|
|
reg [31:0] _RAND_734;
|
|
reg [31:0] _RAND_735;
|
|
reg [31:0] _RAND_736;
|
|
reg [31:0] _RAND_737;
|
|
reg [31:0] _RAND_738;
|
|
reg [31:0] _RAND_739;
|
|
reg [31:0] _RAND_740;
|
|
reg [31:0] _RAND_741;
|
|
reg [31:0] _RAND_742;
|
|
reg [31:0] _RAND_743;
|
|
reg [31:0] _RAND_744;
|
|
reg [31:0] _RAND_745;
|
|
reg [31:0] _RAND_746;
|
|
reg [31:0] _RAND_747;
|
|
reg [31:0] _RAND_748;
|
|
reg [31:0] _RAND_749;
|
|
reg [31:0] _RAND_750;
|
|
reg [31:0] _RAND_751;
|
|
reg [31:0] _RAND_752;
|
|
reg [31:0] _RAND_753;
|
|
reg [31:0] _RAND_754;
|
|
reg [31:0] _RAND_755;
|
|
reg [31:0] _RAND_756;
|
|
reg [31:0] _RAND_757;
|
|
reg [31:0] _RAND_758;
|
|
reg [31:0] _RAND_759;
|
|
reg [31:0] _RAND_760;
|
|
reg [31:0] _RAND_761;
|
|
reg [31:0] _RAND_762;
|
|
reg [31:0] _RAND_763;
|
|
reg [31:0] _RAND_764;
|
|
reg [31:0] _RAND_765;
|
|
reg [31:0] _RAND_766;
|
|
reg [31:0] _RAND_767;
|
|
reg [31:0] _RAND_768;
|
|
reg [31:0] _RAND_769;
|
|
reg [31:0] _RAND_770;
|
|
reg [31:0] _RAND_771;
|
|
reg [31:0] _RAND_772;
|
|
reg [31:0] _RAND_773;
|
|
reg [31:0] _RAND_774;
|
|
reg [31:0] _RAND_775;
|
|
reg [31:0] _RAND_776;
|
|
reg [31:0] _RAND_777;
|
|
reg [31:0] _RAND_778;
|
|
reg [31:0] _RAND_779;
|
|
reg [31:0] _RAND_780;
|
|
reg [31:0] _RAND_781;
|
|
reg [31:0] _RAND_782;
|
|
reg [31:0] _RAND_783;
|
|
reg [31:0] _RAND_784;
|
|
reg [31:0] _RAND_785;
|
|
reg [31:0] _RAND_786;
|
|
reg [31:0] _RAND_787;
|
|
reg [31:0] _RAND_788;
|
|
reg [31:0] _RAND_789;
|
|
reg [31:0] _RAND_790;
|
|
reg [31:0] _RAND_791;
|
|
reg [31:0] _RAND_792;
|
|
reg [31:0] _RAND_793;
|
|
reg [31:0] _RAND_794;
|
|
reg [31:0] _RAND_795;
|
|
reg [31:0] _RAND_796;
|
|
reg [31:0] _RAND_797;
|
|
reg [31:0] _RAND_798;
|
|
reg [31:0] _RAND_799;
|
|
reg [31:0] _RAND_800;
|
|
reg [31:0] _RAND_801;
|
|
reg [31:0] _RAND_802;
|
|
reg [31:0] _RAND_803;
|
|
reg [31:0] _RAND_804;
|
|
reg [31:0] _RAND_805;
|
|
reg [31:0] _RAND_806;
|
|
reg [31:0] _RAND_807;
|
|
reg [31:0] _RAND_808;
|
|
reg [31:0] _RAND_809;
|
|
reg [31:0] _RAND_810;
|
|
reg [31:0] _RAND_811;
|
|
reg [31:0] _RAND_812;
|
|
reg [31:0] _RAND_813;
|
|
reg [31:0] _RAND_814;
|
|
reg [31:0] _RAND_815;
|
|
reg [31:0] _RAND_816;
|
|
reg [31:0] _RAND_817;
|
|
reg [31:0] _RAND_818;
|
|
reg [31:0] _RAND_819;
|
|
reg [31:0] _RAND_820;
|
|
reg [31:0] _RAND_821;
|
|
reg [31:0] _RAND_822;
|
|
reg [31:0] _RAND_823;
|
|
reg [31:0] _RAND_824;
|
|
reg [31:0] _RAND_825;
|
|
reg [31:0] _RAND_826;
|
|
reg [31:0] _RAND_827;
|
|
reg [31:0] _RAND_828;
|
|
reg [31:0] _RAND_829;
|
|
reg [31:0] _RAND_830;
|
|
reg [31:0] _RAND_831;
|
|
reg [31:0] _RAND_832;
|
|
reg [31:0] _RAND_833;
|
|
reg [31:0] _RAND_834;
|
|
reg [31:0] _RAND_835;
|
|
reg [31:0] _RAND_836;
|
|
reg [31:0] _RAND_837;
|
|
reg [31:0] _RAND_838;
|
|
reg [31:0] _RAND_839;
|
|
reg [31:0] _RAND_840;
|
|
reg [31:0] _RAND_841;
|
|
reg [31:0] _RAND_842;
|
|
reg [31:0] _RAND_843;
|
|
reg [31:0] _RAND_844;
|
|
reg [31:0] _RAND_845;
|
|
reg [31:0] _RAND_846;
|
|
reg [31:0] _RAND_847;
|
|
reg [31:0] _RAND_848;
|
|
reg [31:0] _RAND_849;
|
|
reg [31:0] _RAND_850;
|
|
reg [31:0] _RAND_851;
|
|
reg [31:0] _RAND_852;
|
|
reg [31:0] _RAND_853;
|
|
reg [31:0] _RAND_854;
|
|
reg [31:0] _RAND_855;
|
|
reg [31:0] _RAND_856;
|
|
reg [31:0] _RAND_857;
|
|
reg [31:0] _RAND_858;
|
|
reg [31:0] _RAND_859;
|
|
reg [31:0] _RAND_860;
|
|
reg [31:0] _RAND_861;
|
|
reg [31:0] _RAND_862;
|
|
reg [31:0] _RAND_863;
|
|
reg [31:0] _RAND_864;
|
|
reg [31:0] _RAND_865;
|
|
reg [31:0] _RAND_866;
|
|
reg [31:0] _RAND_867;
|
|
reg [31:0] _RAND_868;
|
|
reg [31:0] _RAND_869;
|
|
reg [31:0] _RAND_870;
|
|
reg [31:0] _RAND_871;
|
|
reg [31:0] _RAND_872;
|
|
reg [31:0] _RAND_873;
|
|
reg [31:0] _RAND_874;
|
|
reg [31:0] _RAND_875;
|
|
reg [31:0] _RAND_876;
|
|
reg [31:0] _RAND_877;
|
|
reg [31:0] _RAND_878;
|
|
reg [31:0] _RAND_879;
|
|
reg [31:0] _RAND_880;
|
|
reg [31:0] _RAND_881;
|
|
reg [31:0] _RAND_882;
|
|
reg [31:0] _RAND_883;
|
|
reg [31:0] _RAND_884;
|
|
reg [31:0] _RAND_885;
|
|
reg [31:0] _RAND_886;
|
|
reg [31:0] _RAND_887;
|
|
reg [31:0] _RAND_888;
|
|
reg [31:0] _RAND_889;
|
|
reg [31:0] _RAND_890;
|
|
reg [31:0] _RAND_891;
|
|
reg [31:0] _RAND_892;
|
|
reg [31:0] _RAND_893;
|
|
reg [31:0] _RAND_894;
|
|
reg [31:0] _RAND_895;
|
|
reg [31:0] _RAND_896;
|
|
reg [31:0] _RAND_897;
|
|
reg [31:0] _RAND_898;
|
|
reg [31:0] _RAND_899;
|
|
reg [31:0] _RAND_900;
|
|
reg [31:0] _RAND_901;
|
|
reg [31:0] _RAND_902;
|
|
reg [31:0] _RAND_903;
|
|
reg [31:0] _RAND_904;
|
|
reg [31:0] _RAND_905;
|
|
reg [31:0] _RAND_906;
|
|
reg [31:0] _RAND_907;
|
|
reg [31:0] _RAND_908;
|
|
reg [31:0] _RAND_909;
|
|
reg [31:0] _RAND_910;
|
|
reg [31:0] _RAND_911;
|
|
reg [31:0] _RAND_912;
|
|
reg [31:0] _RAND_913;
|
|
reg [63:0] _RAND_914;
|
|
reg [63:0] _RAND_915;
|
|
reg [63:0] _RAND_916;
|
|
reg [63:0] _RAND_917;
|
|
reg [63:0] _RAND_918;
|
|
reg [63:0] _RAND_919;
|
|
reg [63:0] _RAND_920;
|
|
reg [63:0] _RAND_921;
|
|
reg [63:0] _RAND_922;
|
|
reg [63:0] _RAND_923;
|
|
reg [63:0] _RAND_924;
|
|
reg [63:0] _RAND_925;
|
|
reg [63:0] _RAND_926;
|
|
reg [63:0] _RAND_927;
|
|
reg [63:0] _RAND_928;
|
|
reg [63:0] _RAND_929;
|
|
reg [63:0] _RAND_930;
|
|
reg [63:0] _RAND_931;
|
|
reg [63:0] _RAND_932;
|
|
reg [63:0] _RAND_933;
|
|
reg [63:0] _RAND_934;
|
|
reg [63:0] _RAND_935;
|
|
reg [63:0] _RAND_936;
|
|
reg [63:0] _RAND_937;
|
|
reg [63:0] _RAND_938;
|
|
reg [63:0] _RAND_939;
|
|
reg [63:0] _RAND_940;
|
|
reg [63:0] _RAND_941;
|
|
reg [63:0] _RAND_942;
|
|
reg [63:0] _RAND_943;
|
|
reg [63:0] _RAND_944;
|
|
reg [63:0] _RAND_945;
|
|
reg [63:0] _RAND_946;
|
|
reg [63:0] _RAND_947;
|
|
reg [63:0] _RAND_948;
|
|
reg [63:0] _RAND_949;
|
|
reg [63:0] _RAND_950;
|
|
reg [63:0] _RAND_951;
|
|
reg [63:0] _RAND_952;
|
|
reg [63:0] _RAND_953;
|
|
reg [63:0] _RAND_954;
|
|
reg [63:0] _RAND_955;
|
|
reg [63:0] _RAND_956;
|
|
reg [63:0] _RAND_957;
|
|
reg [63:0] _RAND_958;
|
|
reg [63:0] _RAND_959;
|
|
reg [63:0] _RAND_960;
|
|
reg [63:0] _RAND_961;
|
|
reg [63:0] _RAND_962;
|
|
reg [63:0] _RAND_963;
|
|
reg [63:0] _RAND_964;
|
|
reg [63:0] _RAND_965;
|
|
reg [63:0] _RAND_966;
|
|
reg [63:0] _RAND_967;
|
|
reg [63:0] _RAND_968;
|
|
reg [63:0] _RAND_969;
|
|
reg [63:0] _RAND_970;
|
|
reg [63:0] _RAND_971;
|
|
reg [63:0] _RAND_972;
|
|
reg [63:0] _RAND_973;
|
|
reg [63:0] _RAND_974;
|
|
reg [63:0] _RAND_975;
|
|
reg [63:0] _RAND_976;
|
|
reg [63:0] _RAND_977;
|
|
reg [63:0] _RAND_978;
|
|
reg [63:0] _RAND_979;
|
|
reg [63:0] _RAND_980;
|
|
reg [63:0] _RAND_981;
|
|
reg [63:0] _RAND_982;
|
|
reg [63:0] _RAND_983;
|
|
reg [63:0] _RAND_984;
|
|
reg [63:0] _RAND_985;
|
|
reg [63:0] _RAND_986;
|
|
reg [63:0] _RAND_987;
|
|
reg [63:0] _RAND_988;
|
|
reg [63:0] _RAND_989;
|
|
reg [63:0] _RAND_990;
|
|
reg [63:0] _RAND_991;
|
|
reg [63:0] _RAND_992;
|
|
reg [63:0] _RAND_993;
|
|
reg [63:0] _RAND_994;
|
|
reg [63:0] _RAND_995;
|
|
reg [63:0] _RAND_996;
|
|
reg [63:0] _RAND_997;
|
|
reg [63:0] _RAND_998;
|
|
reg [63:0] _RAND_999;
|
|
reg [63:0] _RAND_1000;
|
|
reg [63:0] _RAND_1001;
|
|
reg [63:0] _RAND_1002;
|
|
reg [63:0] _RAND_1003;
|
|
reg [31:0] _RAND_1004;
|
|
reg [31:0] _RAND_1005;
|
|
reg [31:0] _RAND_1006;
|
|
reg [31:0] _RAND_1007;
|
|
reg [31:0] _RAND_1008;
|
|
reg [31:0] _RAND_1009;
|
|
reg [31:0] _RAND_1010;
|
|
reg [31:0] _RAND_1011;
|
|
reg [31:0] _RAND_1012;
|
|
reg [31:0] _RAND_1013;
|
|
reg [31:0] _RAND_1014;
|
|
reg [31:0] _RAND_1015;
|
|
reg [31:0] _RAND_1016;
|
|
reg [31:0] _RAND_1017;
|
|
reg [31:0] _RAND_1018;
|
|
reg [31:0] _RAND_1019;
|
|
reg [31:0] _RAND_1020;
|
|
reg [31:0] _RAND_1021;
|
|
reg [31:0] _RAND_1022;
|
|
reg [31:0] _RAND_1023;
|
|
reg [31:0] _RAND_1024;
|
|
reg [31:0] _RAND_1025;
|
|
reg [31:0] _RAND_1026;
|
|
reg [31:0] _RAND_1027;
|
|
reg [31:0] _RAND_1028;
|
|
reg [31:0] _RAND_1029;
|
|
reg [31:0] _RAND_1030;
|
|
reg [31:0] _RAND_1031;
|
|
reg [31:0] _RAND_1032;
|
|
reg [31:0] _RAND_1033;
|
|
reg [31:0] _RAND_1034;
|
|
reg [31:0] _RAND_1035;
|
|
reg [31:0] _RAND_1036;
|
|
reg [31:0] _RAND_1037;
|
|
reg [31:0] _RAND_1038;
|
|
reg [31:0] _RAND_1039;
|
|
reg [31:0] _RAND_1040;
|
|
reg [31:0] _RAND_1041;
|
|
reg [31:0] _RAND_1042;
|
|
reg [31:0] _RAND_1043;
|
|
reg [31:0] _RAND_1044;
|
|
reg [31:0] _RAND_1045;
|
|
reg [31:0] _RAND_1046;
|
|
reg [31:0] _RAND_1047;
|
|
reg [31:0] _RAND_1048;
|
|
reg [31:0] _RAND_1049;
|
|
reg [31:0] _RAND_1050;
|
|
reg [31:0] _RAND_1051;
|
|
reg [31:0] _RAND_1052;
|
|
reg [31:0] _RAND_1053;
|
|
reg [31:0] _RAND_1054;
|
|
reg [31:0] _RAND_1055;
|
|
reg [31:0] _RAND_1056;
|
|
reg [31:0] _RAND_1057;
|
|
reg [31:0] _RAND_1058;
|
|
reg [31:0] _RAND_1059;
|
|
reg [31:0] _RAND_1060;
|
|
reg [31:0] _RAND_1061;
|
|
reg [31:0] _RAND_1062;
|
|
reg [31:0] _RAND_1063;
|
|
reg [31:0] _RAND_1064;
|
|
reg [31:0] _RAND_1065;
|
|
reg [31:0] _RAND_1066;
|
|
reg [31:0] _RAND_1067;
|
|
reg [31:0] _RAND_1068;
|
|
reg [31:0] _RAND_1069;
|
|
reg [31:0] _RAND_1070;
|
|
reg [31:0] _RAND_1071;
|
|
reg [31:0] _RAND_1072;
|
|
reg [31:0] _RAND_1073;
|
|
reg [31:0] _RAND_1074;
|
|
reg [31:0] _RAND_1075;
|
|
reg [31:0] _RAND_1076;
|
|
reg [31:0] _RAND_1077;
|
|
reg [31:0] _RAND_1078;
|
|
reg [31:0] _RAND_1079;
|
|
reg [31:0] _RAND_1080;
|
|
reg [31:0] _RAND_1081;
|
|
reg [31:0] _RAND_1082;
|
|
reg [31:0] _RAND_1083;
|
|
reg [31:0] _RAND_1084;
|
|
reg [31:0] _RAND_1085;
|
|
reg [31:0] _RAND_1086;
|
|
reg [31:0] _RAND_1087;
|
|
reg [31:0] _RAND_1088;
|
|
reg [31:0] _RAND_1089;
|
|
reg [31:0] _RAND_1090;
|
|
reg [31:0] _RAND_1091;
|
|
reg [31:0] _RAND_1092;
|
|
reg [31:0] _RAND_1093;
|
|
reg [31:0] _RAND_1094;
|
|
reg [31:0] _RAND_1095;
|
|
reg [31:0] _RAND_1096;
|
|
`endif // RANDOMIZE_REG_INIT
|
|
wire rvclkhdr_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_3_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_4_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_5_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_6_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_7_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_8_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_9_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_10_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_11_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_12_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_13_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_14_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_15_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_16_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_17_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_18_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_19_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_20_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_21_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_22_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_23_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_24_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_25_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_26_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_27_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_28_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_29_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_30_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_31_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_32_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_33_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_34_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_35_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_35_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_36_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_36_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_37_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_37_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_38_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_38_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_39_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_39_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_40_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_40_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_41_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_41_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_42_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_42_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_43_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_43_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_44_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_44_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_45_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_45_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_46_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_46_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_47_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_47_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_48_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_48_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_49_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_49_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_50_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_50_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_51_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_51_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_52_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_52_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_53_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_53_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_54_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_54_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_55_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_55_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_56_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_56_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_57_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_57_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_58_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_58_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_59_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_59_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_60_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_60_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_61_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_61_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_62_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_62_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_63_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_63_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_64_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_64_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_65_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_65_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_66_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_66_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_67_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_67_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_68_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_68_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_69_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_69_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_70_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_70_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_71_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_71_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_72_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_72_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_73_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_73_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_74_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_74_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_75_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_75_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_76_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_76_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_77_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_77_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_78_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_78_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_79_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_79_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_80_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_80_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_81_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_81_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_82_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_82_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_83_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_83_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_84_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_84_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_85_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_85_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_86_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_86_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_87_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_87_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_88_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_88_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_89_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_89_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_90_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_90_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_91_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_91_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_92_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_92_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_93_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_93_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_94_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_94_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_95_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_95_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_96_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_96_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_97_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_97_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_98_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_98_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_99_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_99_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_100_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_100_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_101_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_101_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_102_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_102_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_103_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_103_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_104_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_104_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_105_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_105_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_106_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_106_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_107_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_107_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_108_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_108_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_109_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_109_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_110_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_110_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_111_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_111_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_112_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_112_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_113_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_113_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_114_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_114_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_115_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_115_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_116_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_116_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_117_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_117_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_118_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_118_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_119_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_119_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_120_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_120_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_121_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_121_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_122_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_122_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_123_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_123_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_124_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_124_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_125_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_125_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_126_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_126_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_127_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_127_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_128_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_128_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_129_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_129_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_130_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_130_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_131_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_131_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_132_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_132_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_133_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_133_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_134_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_134_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_135_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_135_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_136_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_136_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_137_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_137_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_138_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_138_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_139_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_139_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_140_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_140_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_141_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_141_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_142_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_142_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_143_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_143_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_144_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_144_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_145_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_145_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_146_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_146_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_147_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_147_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_148_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_148_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_149_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_149_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_150_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_150_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_151_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_151_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_152_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_152_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_153_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_153_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_154_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_154_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_155_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_155_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_156_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_156_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_157_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_157_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_158_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_158_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_159_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_159_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_160_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_160_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_161_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_161_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_162_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_162_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_163_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_163_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_164_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_164_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_165_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_165_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_166_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_166_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_167_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_167_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_168_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_168_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_169_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_169_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_170_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_170_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_171_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_171_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_172_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_172_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_173_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_173_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_174_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_174_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_175_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_175_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_176_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_176_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_177_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_177_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_178_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_178_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_179_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_179_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_180_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_180_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_181_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_181_io_en; // @[lib.scala 422:23]
|
|
wire rvclkhdr_182_io_clk; // @[lib.scala 422:23]
|
|
wire rvclkhdr_182_io_en; // @[lib.scala 422:23]
|
|
reg wrbuf_vld; // @[Reg.scala 27:20]
|
|
reg wrbuf_data_vld; // @[Reg.scala 27:20]
|
|
wire _T_17274 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 350:45]
|
|
reg rdbuf_vld; // @[Reg.scala 27:20]
|
|
wire bus_cmd_valid = _T_17274 | rdbuf_vld; // @[dma_ctrl.scala 350:63]
|
|
reg _T_10444; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10437; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10430; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10423; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10416; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10409; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10402; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10395; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10388; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10381; // @[dma_ctrl.scala 142:82]
|
|
wire [9:0] _T_10453 = {_T_10444,_T_10437,_T_10430,_T_10423,_T_10416,_T_10409,_T_10402,_T_10395,_T_10388,_T_10381}; // @[Cat.scala 29:58]
|
|
reg _T_10374; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10367; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10360; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10353; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10346; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10339; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10332; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10325; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10318; // @[dma_ctrl.scala 142:82]
|
|
wire [18:0] _T_10462 = {_T_10453,_T_10374,_T_10367,_T_10360,_T_10353,_T_10346,_T_10339,_T_10332,_T_10325,_T_10318}; // @[Cat.scala 29:58]
|
|
reg _T_10311; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10304; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10297; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10290; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10283; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10276; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10269; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10262; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10255; // @[dma_ctrl.scala 142:82]
|
|
wire [27:0] _T_10471 = {_T_10462,_T_10311,_T_10304,_T_10297,_T_10290,_T_10283,_T_10276,_T_10269,_T_10262,_T_10255}; // @[Cat.scala 29:58]
|
|
reg _T_10248; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10241; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10234; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10227; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10220; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10213; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10206; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10199; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10192; // @[dma_ctrl.scala 142:82]
|
|
wire [36:0] _T_10480 = {_T_10471,_T_10248,_T_10241,_T_10234,_T_10227,_T_10220,_T_10213,_T_10206,_T_10199,_T_10192}; // @[Cat.scala 29:58]
|
|
reg _T_10185; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10178; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10171; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10164; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10157; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10150; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10143; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10136; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10129; // @[dma_ctrl.scala 142:82]
|
|
wire [45:0] _T_10489 = {_T_10480,_T_10185,_T_10178,_T_10171,_T_10164,_T_10157,_T_10150,_T_10143,_T_10136,_T_10129}; // @[Cat.scala 29:58]
|
|
reg _T_10122; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10115; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10108; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10101; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10094; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10087; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10080; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10073; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10066; // @[dma_ctrl.scala 142:82]
|
|
wire [54:0] _T_10498 = {_T_10489,_T_10122,_T_10115,_T_10108,_T_10101,_T_10094,_T_10087,_T_10080,_T_10073,_T_10066}; // @[Cat.scala 29:58]
|
|
reg _T_10059; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10052; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10045; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10038; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10031; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10024; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10017; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10010; // @[dma_ctrl.scala 142:82]
|
|
reg _T_10003; // @[dma_ctrl.scala 142:82]
|
|
wire [63:0] _T_10507 = {_T_10498,_T_10059,_T_10052,_T_10045,_T_10038,_T_10031,_T_10024,_T_10017,_T_10010,_T_10003}; // @[Cat.scala 29:58]
|
|
reg _T_9996; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9989; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9982; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9975; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9968; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9961; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9954; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9947; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9940; // @[dma_ctrl.scala 142:82]
|
|
wire [72:0] _T_10516 = {_T_10507,_T_9996,_T_9989,_T_9982,_T_9975,_T_9968,_T_9961,_T_9954,_T_9947,_T_9940}; // @[Cat.scala 29:58]
|
|
reg _T_9933; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9926; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9919; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9912; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9905; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9898; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9891; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9884; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9877; // @[dma_ctrl.scala 142:82]
|
|
wire [81:0] _T_10525 = {_T_10516,_T_9933,_T_9926,_T_9919,_T_9912,_T_9905,_T_9898,_T_9891,_T_9884,_T_9877}; // @[Cat.scala 29:58]
|
|
reg _T_9870; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9863; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9856; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9849; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9842; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9835; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9828; // @[dma_ctrl.scala 142:82]
|
|
reg _T_9821; // @[dma_ctrl.scala 142:82]
|
|
wire [89:0] fifo_valid = {_T_10525,_T_9870,_T_9863,_T_9856,_T_9849,_T_9842,_T_9835,_T_9828,_T_9821}; // @[Cat.scala 29:58]
|
|
wire _T_6 = |fifo_valid; // @[dma_ctrl.scala 55:150]
|
|
wire _T_17281 = _T_17274 & rdbuf_vld; // @[dma_ctrl.scala 364:56]
|
|
reg axi_mstr_priority; // @[Reg.scala 27:20]
|
|
wire axi_mstr_sel = _T_17281 ? axi_mstr_priority : _T_17274; // @[dma_ctrl.scala 364:26]
|
|
reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
|
|
reg [31:0] rdbuf_addr; // @[Reg.scala 27:20]
|
|
wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 354:37]
|
|
wire [31:0] fifo_addr_in = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dec_dma_dbg_ib_dbg_cmd_addr : bus_cmd_addr; // @[dma_ctrl.scala 60:25]
|
|
wire _T_8 = ~io_dbg_dec_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 61:31]
|
|
wire [7:0] _T_10 = _T_8 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
|
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
|
|
wire [7:0] fifo_byteen_in = _T_10 & wrbuf_byteen; // @[dma_ctrl.scala 61:69]
|
|
wire [2:0] _T_11 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
|
|
reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
|
|
reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
|
|
wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 355:37]
|
|
wire [2:0] fifo_sz_in = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid ? _T_11 : bus_cmd_sz; // @[dma_ctrl.scala 62:23]
|
|
wire fifo_write_in = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dec_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 63:26]
|
|
reg dbg_dma_bubble_bus; // @[Reg.scala 27:20]
|
|
wire dma_fifo_ready = ~dbg_dma_bubble_bus; // @[dma_ctrl.scala 190:24]
|
|
wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 351:48]
|
|
wire _T_14 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 120:80]
|
|
wire _T_17 = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid & io_dbg_dec_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 120:140]
|
|
wire _T_18 = _T_14 | _T_17; // @[dma_ctrl.scala 120:101]
|
|
reg [6:0] WrPtr; // @[Reg.scala 27:20]
|
|
wire _T_19 = 7'h0 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_20 = _T_18 & _T_19; // @[dma_ctrl.scala 120:189]
|
|
wire _T_27 = 7'h1 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_28 = _T_18 & _T_27; // @[dma_ctrl.scala 120:189]
|
|
wire _T_35 = 7'h2 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_36 = _T_18 & _T_35; // @[dma_ctrl.scala 120:189]
|
|
wire _T_43 = 7'h3 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_44 = _T_18 & _T_43; // @[dma_ctrl.scala 120:189]
|
|
wire _T_51 = 7'h4 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_52 = _T_18 & _T_51; // @[dma_ctrl.scala 120:189]
|
|
wire _T_59 = 7'h5 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_60 = _T_18 & _T_59; // @[dma_ctrl.scala 120:189]
|
|
wire _T_67 = 7'h6 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_68 = _T_18 & _T_67; // @[dma_ctrl.scala 120:189]
|
|
wire _T_75 = 7'h7 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_76 = _T_18 & _T_75; // @[dma_ctrl.scala 120:189]
|
|
wire _T_83 = 7'h8 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_84 = _T_18 & _T_83; // @[dma_ctrl.scala 120:189]
|
|
wire _T_91 = 7'h9 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_92 = _T_18 & _T_91; // @[dma_ctrl.scala 120:189]
|
|
wire _T_99 = 7'ha == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_100 = _T_18 & _T_99; // @[dma_ctrl.scala 120:189]
|
|
wire _T_107 = 7'hb == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_108 = _T_18 & _T_107; // @[dma_ctrl.scala 120:189]
|
|
wire _T_115 = 7'hc == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_116 = _T_18 & _T_115; // @[dma_ctrl.scala 120:189]
|
|
wire _T_123 = 7'hd == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_124 = _T_18 & _T_123; // @[dma_ctrl.scala 120:189]
|
|
wire _T_131 = 7'he == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_132 = _T_18 & _T_131; // @[dma_ctrl.scala 120:189]
|
|
wire _T_139 = 7'hf == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_140 = _T_18 & _T_139; // @[dma_ctrl.scala 120:189]
|
|
wire _T_147 = 7'h10 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_148 = _T_18 & _T_147; // @[dma_ctrl.scala 120:189]
|
|
wire _T_155 = 7'h11 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_156 = _T_18 & _T_155; // @[dma_ctrl.scala 120:189]
|
|
wire _T_163 = 7'h12 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_164 = _T_18 & _T_163; // @[dma_ctrl.scala 120:189]
|
|
wire _T_171 = 7'h13 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_172 = _T_18 & _T_171; // @[dma_ctrl.scala 120:189]
|
|
wire _T_179 = 7'h14 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_180 = _T_18 & _T_179; // @[dma_ctrl.scala 120:189]
|
|
wire _T_187 = 7'h15 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_188 = _T_18 & _T_187; // @[dma_ctrl.scala 120:189]
|
|
wire _T_195 = 7'h16 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_196 = _T_18 & _T_195; // @[dma_ctrl.scala 120:189]
|
|
wire _T_203 = 7'h17 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_204 = _T_18 & _T_203; // @[dma_ctrl.scala 120:189]
|
|
wire _T_211 = 7'h18 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_212 = _T_18 & _T_211; // @[dma_ctrl.scala 120:189]
|
|
wire _T_219 = 7'h19 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_220 = _T_18 & _T_219; // @[dma_ctrl.scala 120:189]
|
|
wire _T_227 = 7'h1a == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_228 = _T_18 & _T_227; // @[dma_ctrl.scala 120:189]
|
|
wire _T_235 = 7'h1b == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_236 = _T_18 & _T_235; // @[dma_ctrl.scala 120:189]
|
|
wire _T_243 = 7'h1c == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_244 = _T_18 & _T_243; // @[dma_ctrl.scala 120:189]
|
|
wire _T_251 = 7'h1d == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_252 = _T_18 & _T_251; // @[dma_ctrl.scala 120:189]
|
|
wire _T_259 = 7'h1e == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_260 = _T_18 & _T_259; // @[dma_ctrl.scala 120:189]
|
|
wire _T_267 = 7'h1f == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_268 = _T_18 & _T_267; // @[dma_ctrl.scala 120:189]
|
|
wire _T_275 = 7'h20 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_276 = _T_18 & _T_275; // @[dma_ctrl.scala 120:189]
|
|
wire _T_283 = 7'h21 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_284 = _T_18 & _T_283; // @[dma_ctrl.scala 120:189]
|
|
wire _T_291 = 7'h22 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_292 = _T_18 & _T_291; // @[dma_ctrl.scala 120:189]
|
|
wire _T_299 = 7'h23 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_300 = _T_18 & _T_299; // @[dma_ctrl.scala 120:189]
|
|
wire _T_307 = 7'h24 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_308 = _T_18 & _T_307; // @[dma_ctrl.scala 120:189]
|
|
wire _T_315 = 7'h25 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_316 = _T_18 & _T_315; // @[dma_ctrl.scala 120:189]
|
|
wire _T_323 = 7'h26 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_324 = _T_18 & _T_323; // @[dma_ctrl.scala 120:189]
|
|
wire _T_331 = 7'h27 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_332 = _T_18 & _T_331; // @[dma_ctrl.scala 120:189]
|
|
wire _T_339 = 7'h28 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_340 = _T_18 & _T_339; // @[dma_ctrl.scala 120:189]
|
|
wire _T_347 = 7'h29 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_348 = _T_18 & _T_347; // @[dma_ctrl.scala 120:189]
|
|
wire _T_355 = 7'h2a == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_356 = _T_18 & _T_355; // @[dma_ctrl.scala 120:189]
|
|
wire _T_363 = 7'h2b == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_364 = _T_18 & _T_363; // @[dma_ctrl.scala 120:189]
|
|
wire _T_371 = 7'h2c == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_372 = _T_18 & _T_371; // @[dma_ctrl.scala 120:189]
|
|
wire _T_379 = 7'h2d == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_380 = _T_18 & _T_379; // @[dma_ctrl.scala 120:189]
|
|
wire _T_387 = 7'h2e == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_388 = _T_18 & _T_387; // @[dma_ctrl.scala 120:189]
|
|
wire _T_395 = 7'h2f == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_396 = _T_18 & _T_395; // @[dma_ctrl.scala 120:189]
|
|
wire _T_403 = 7'h30 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_404 = _T_18 & _T_403; // @[dma_ctrl.scala 120:189]
|
|
wire _T_411 = 7'h31 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_412 = _T_18 & _T_411; // @[dma_ctrl.scala 120:189]
|
|
wire _T_419 = 7'h32 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_420 = _T_18 & _T_419; // @[dma_ctrl.scala 120:189]
|
|
wire _T_427 = 7'h33 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_428 = _T_18 & _T_427; // @[dma_ctrl.scala 120:189]
|
|
wire _T_435 = 7'h34 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_436 = _T_18 & _T_435; // @[dma_ctrl.scala 120:189]
|
|
wire _T_443 = 7'h35 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_444 = _T_18 & _T_443; // @[dma_ctrl.scala 120:189]
|
|
wire _T_451 = 7'h36 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_452 = _T_18 & _T_451; // @[dma_ctrl.scala 120:189]
|
|
wire _T_459 = 7'h37 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_460 = _T_18 & _T_459; // @[dma_ctrl.scala 120:189]
|
|
wire _T_467 = 7'h38 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_468 = _T_18 & _T_467; // @[dma_ctrl.scala 120:189]
|
|
wire _T_475 = 7'h39 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_476 = _T_18 & _T_475; // @[dma_ctrl.scala 120:189]
|
|
wire _T_483 = 7'h3a == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_484 = _T_18 & _T_483; // @[dma_ctrl.scala 120:189]
|
|
wire _T_491 = 7'h3b == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_492 = _T_18 & _T_491; // @[dma_ctrl.scala 120:189]
|
|
wire _T_499 = 7'h3c == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_500 = _T_18 & _T_499; // @[dma_ctrl.scala 120:189]
|
|
wire _T_507 = 7'h3d == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_508 = _T_18 & _T_507; // @[dma_ctrl.scala 120:189]
|
|
wire _T_515 = 7'h3e == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_516 = _T_18 & _T_515; // @[dma_ctrl.scala 120:189]
|
|
wire _T_523 = 7'h3f == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_524 = _T_18 & _T_523; // @[dma_ctrl.scala 120:189]
|
|
wire _T_531 = 7'h40 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_532 = _T_18 & _T_531; // @[dma_ctrl.scala 120:189]
|
|
wire _T_539 = 7'h41 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_540 = _T_18 & _T_539; // @[dma_ctrl.scala 120:189]
|
|
wire _T_547 = 7'h42 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_548 = _T_18 & _T_547; // @[dma_ctrl.scala 120:189]
|
|
wire _T_555 = 7'h43 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_556 = _T_18 & _T_555; // @[dma_ctrl.scala 120:189]
|
|
wire _T_563 = 7'h44 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_564 = _T_18 & _T_563; // @[dma_ctrl.scala 120:189]
|
|
wire _T_571 = 7'h45 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_572 = _T_18 & _T_571; // @[dma_ctrl.scala 120:189]
|
|
wire _T_579 = 7'h46 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_580 = _T_18 & _T_579; // @[dma_ctrl.scala 120:189]
|
|
wire _T_587 = 7'h47 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_588 = _T_18 & _T_587; // @[dma_ctrl.scala 120:189]
|
|
wire _T_595 = 7'h48 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_596 = _T_18 & _T_595; // @[dma_ctrl.scala 120:189]
|
|
wire _T_603 = 7'h49 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_604 = _T_18 & _T_603; // @[dma_ctrl.scala 120:189]
|
|
wire _T_611 = 7'h4a == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_612 = _T_18 & _T_611; // @[dma_ctrl.scala 120:189]
|
|
wire _T_619 = 7'h4b == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_620 = _T_18 & _T_619; // @[dma_ctrl.scala 120:189]
|
|
wire _T_627 = 7'h4c == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_628 = _T_18 & _T_627; // @[dma_ctrl.scala 120:189]
|
|
wire _T_635 = 7'h4d == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_636 = _T_18 & _T_635; // @[dma_ctrl.scala 120:189]
|
|
wire _T_643 = 7'h4e == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_644 = _T_18 & _T_643; // @[dma_ctrl.scala 120:189]
|
|
wire _T_651 = 7'h4f == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_652 = _T_18 & _T_651; // @[dma_ctrl.scala 120:189]
|
|
wire _T_659 = 7'h50 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_660 = _T_18 & _T_659; // @[dma_ctrl.scala 120:189]
|
|
wire _T_667 = 7'h51 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_668 = _T_18 & _T_667; // @[dma_ctrl.scala 120:189]
|
|
wire _T_675 = 7'h52 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_676 = _T_18 & _T_675; // @[dma_ctrl.scala 120:189]
|
|
wire _T_683 = 7'h53 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_684 = _T_18 & _T_683; // @[dma_ctrl.scala 120:189]
|
|
wire _T_691 = 7'h54 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_692 = _T_18 & _T_691; // @[dma_ctrl.scala 120:189]
|
|
wire _T_699 = 7'h55 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_700 = _T_18 & _T_699; // @[dma_ctrl.scala 120:189]
|
|
wire _T_707 = 7'h56 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_708 = _T_18 & _T_707; // @[dma_ctrl.scala 120:189]
|
|
wire _T_715 = 7'h57 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_716 = _T_18 & _T_715; // @[dma_ctrl.scala 120:189]
|
|
wire _T_723 = 7'h58 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_724 = _T_18 & _T_723; // @[dma_ctrl.scala 120:189]
|
|
wire _T_731 = 7'h59 == WrPtr; // @[dma_ctrl.scala 120:196]
|
|
wire _T_732 = _T_18 & _T_731; // @[dma_ctrl.scala 120:189]
|
|
wire [9:0] _T_741 = {_T_732,_T_724,_T_716,_T_708,_T_700,_T_692,_T_684,_T_676,_T_668,_T_660}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_750 = {_T_741,_T_652,_T_644,_T_636,_T_628,_T_620,_T_612,_T_604,_T_596,_T_588}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_759 = {_T_750,_T_580,_T_572,_T_564,_T_556,_T_548,_T_540,_T_532,_T_524,_T_516}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_768 = {_T_759,_T_508,_T_500,_T_492,_T_484,_T_476,_T_468,_T_460,_T_452,_T_444}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_777 = {_T_768,_T_436,_T_428,_T_420,_T_412,_T_404,_T_396,_T_388,_T_380,_T_372}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_786 = {_T_777,_T_364,_T_356,_T_348,_T_340,_T_332,_T_324,_T_316,_T_308,_T_300}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_795 = {_T_786,_T_292,_T_284,_T_276,_T_268,_T_260,_T_252,_T_244,_T_236,_T_228}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_804 = {_T_795,_T_220,_T_212,_T_204,_T_196,_T_188,_T_180,_T_172,_T_164,_T_156}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_813 = {_T_804,_T_148,_T_140,_T_132,_T_124,_T_116,_T_108,_T_100,_T_92,_T_84}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_cmd_en = {_T_813,_T_76,_T_68,_T_60,_T_52,_T_44,_T_36,_T_28,_T_20}; // @[Cat.scala 29:58]
|
|
wire _T_822 = axi_mstr_prty_en & fifo_write_in; // @[dma_ctrl.scala 122:73]
|
|
wire _T_823 = _T_822 & io_dma_bus_clk_en; // @[dma_ctrl.scala 122:89]
|
|
wire _T_826 = _T_17 & io_dbg_dec_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 122:189]
|
|
wire _T_827 = _T_823 | _T_826; // @[dma_ctrl.scala 122:110]
|
|
wire _T_829 = _T_827 & _T_19; // @[dma_ctrl.scala 122:229]
|
|
reg [6:0] RdPtr; // @[Reg.scala 27:20]
|
|
wire [89:0] _T_16938 = fifo_valid >> RdPtr; // @[dma_ctrl.scala 198:35]
|
|
reg _T_13411; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13404; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13397; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13390; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13383; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13376; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13369; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13362; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13355; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13348; // @[dma_ctrl.scala 148:88]
|
|
wire [9:0] _T_13420 = {_T_13411,_T_13404,_T_13397,_T_13390,_T_13383,_T_13376,_T_13369,_T_13362,_T_13355,_T_13348}; // @[Cat.scala 29:58]
|
|
reg _T_13341; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13334; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13327; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13320; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13313; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13306; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13299; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13292; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13285; // @[dma_ctrl.scala 148:88]
|
|
wire [18:0] _T_13429 = {_T_13420,_T_13341,_T_13334,_T_13327,_T_13320,_T_13313,_T_13306,_T_13299,_T_13292,_T_13285}; // @[Cat.scala 29:58]
|
|
reg _T_13278; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13271; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13264; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13257; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13250; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13243; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13236; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13229; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13222; // @[dma_ctrl.scala 148:88]
|
|
wire [27:0] _T_13438 = {_T_13429,_T_13278,_T_13271,_T_13264,_T_13257,_T_13250,_T_13243,_T_13236,_T_13229,_T_13222}; // @[Cat.scala 29:58]
|
|
reg _T_13215; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13208; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13201; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13194; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13187; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13180; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13173; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13166; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13159; // @[dma_ctrl.scala 148:88]
|
|
wire [36:0] _T_13447 = {_T_13438,_T_13215,_T_13208,_T_13201,_T_13194,_T_13187,_T_13180,_T_13173,_T_13166,_T_13159}; // @[Cat.scala 29:58]
|
|
reg _T_13152; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13145; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13138; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13131; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13124; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13117; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13110; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13103; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13096; // @[dma_ctrl.scala 148:88]
|
|
wire [45:0] _T_13456 = {_T_13447,_T_13152,_T_13145,_T_13138,_T_13131,_T_13124,_T_13117,_T_13110,_T_13103,_T_13096}; // @[Cat.scala 29:58]
|
|
reg _T_13089; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13082; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13075; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13068; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13061; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13054; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13047; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13040; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13033; // @[dma_ctrl.scala 148:88]
|
|
wire [54:0] _T_13465 = {_T_13456,_T_13089,_T_13082,_T_13075,_T_13068,_T_13061,_T_13054,_T_13047,_T_13040,_T_13033}; // @[Cat.scala 29:58]
|
|
reg _T_13026; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13019; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13012; // @[dma_ctrl.scala 148:88]
|
|
reg _T_13005; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12998; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12991; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12984; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12977; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12970; // @[dma_ctrl.scala 148:88]
|
|
wire [63:0] _T_13474 = {_T_13465,_T_13026,_T_13019,_T_13012,_T_13005,_T_12998,_T_12991,_T_12984,_T_12977,_T_12970}; // @[Cat.scala 29:58]
|
|
reg _T_12963; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12956; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12949; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12942; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12935; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12928; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12921; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12914; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12907; // @[dma_ctrl.scala 148:88]
|
|
wire [72:0] _T_13483 = {_T_13474,_T_12963,_T_12956,_T_12949,_T_12942,_T_12935,_T_12928,_T_12921,_T_12914,_T_12907}; // @[Cat.scala 29:58]
|
|
reg _T_12900; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12893; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12886; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12879; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12872; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12865; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12858; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12851; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12844; // @[dma_ctrl.scala 148:88]
|
|
wire [81:0] _T_13492 = {_T_13483,_T_12900,_T_12893,_T_12886,_T_12879,_T_12872,_T_12865,_T_12858,_T_12851,_T_12844}; // @[Cat.scala 29:58]
|
|
reg _T_12837; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12830; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12823; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12816; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12809; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12802; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12795; // @[dma_ctrl.scala 148:88]
|
|
reg _T_12788; // @[dma_ctrl.scala 148:88]
|
|
wire [89:0] fifo_done = {_T_13492,_T_12837,_T_12830,_T_12823,_T_12816,_T_12809,_T_12802,_T_12795,_T_12788}; // @[Cat.scala 29:58]
|
|
wire [89:0] _T_16940 = fifo_done >> RdPtr; // @[dma_ctrl.scala 198:55]
|
|
wire _T_16942 = ~_T_16940[0]; // @[dma_ctrl.scala 198:45]
|
|
wire _T_16943 = _T_16938[0] & _T_16942; // @[dma_ctrl.scala 198:43]
|
|
reg _T_15745; // @[Reg.scala 27:20]
|
|
reg _T_15743; // @[Reg.scala 27:20]
|
|
reg _T_15741; // @[Reg.scala 27:20]
|
|
reg _T_15739; // @[Reg.scala 27:20]
|
|
reg _T_15737; // @[Reg.scala 27:20]
|
|
reg _T_15735; // @[Reg.scala 27:20]
|
|
reg _T_15733; // @[Reg.scala 27:20]
|
|
reg _T_15731; // @[Reg.scala 27:20]
|
|
reg _T_15729; // @[Reg.scala 27:20]
|
|
reg _T_15727; // @[Reg.scala 27:20]
|
|
wire [9:0] _T_15754 = {_T_15745,_T_15743,_T_15741,_T_15739,_T_15737,_T_15735,_T_15733,_T_15731,_T_15729,_T_15727}; // @[Cat.scala 29:58]
|
|
reg _T_15725; // @[Reg.scala 27:20]
|
|
reg _T_15723; // @[Reg.scala 27:20]
|
|
reg _T_15721; // @[Reg.scala 27:20]
|
|
reg _T_15719; // @[Reg.scala 27:20]
|
|
reg _T_15717; // @[Reg.scala 27:20]
|
|
reg _T_15715; // @[Reg.scala 27:20]
|
|
reg _T_15713; // @[Reg.scala 27:20]
|
|
reg _T_15711; // @[Reg.scala 27:20]
|
|
reg _T_15709; // @[Reg.scala 27:20]
|
|
wire [18:0] _T_15763 = {_T_15754,_T_15725,_T_15723,_T_15721,_T_15719,_T_15717,_T_15715,_T_15713,_T_15711,_T_15709}; // @[Cat.scala 29:58]
|
|
reg _T_15707; // @[Reg.scala 27:20]
|
|
reg _T_15705; // @[Reg.scala 27:20]
|
|
reg _T_15703; // @[Reg.scala 27:20]
|
|
reg _T_15701; // @[Reg.scala 27:20]
|
|
reg _T_15699; // @[Reg.scala 27:20]
|
|
reg _T_15697; // @[Reg.scala 27:20]
|
|
reg _T_15695; // @[Reg.scala 27:20]
|
|
reg _T_15693; // @[Reg.scala 27:20]
|
|
reg _T_15691; // @[Reg.scala 27:20]
|
|
wire [27:0] _T_15772 = {_T_15763,_T_15707,_T_15705,_T_15703,_T_15701,_T_15699,_T_15697,_T_15695,_T_15693,_T_15691}; // @[Cat.scala 29:58]
|
|
reg _T_15689; // @[Reg.scala 27:20]
|
|
reg _T_15687; // @[Reg.scala 27:20]
|
|
reg _T_15685; // @[Reg.scala 27:20]
|
|
reg _T_15683; // @[Reg.scala 27:20]
|
|
reg _T_15681; // @[Reg.scala 27:20]
|
|
reg _T_15679; // @[Reg.scala 27:20]
|
|
reg _T_15677; // @[Reg.scala 27:20]
|
|
reg _T_15675; // @[Reg.scala 27:20]
|
|
reg _T_15673; // @[Reg.scala 27:20]
|
|
wire [36:0] _T_15781 = {_T_15772,_T_15689,_T_15687,_T_15685,_T_15683,_T_15681,_T_15679,_T_15677,_T_15675,_T_15673}; // @[Cat.scala 29:58]
|
|
reg _T_15671; // @[Reg.scala 27:20]
|
|
reg _T_15669; // @[Reg.scala 27:20]
|
|
reg _T_15667; // @[Reg.scala 27:20]
|
|
reg _T_15665; // @[Reg.scala 27:20]
|
|
reg _T_15663; // @[Reg.scala 27:20]
|
|
reg _T_15661; // @[Reg.scala 27:20]
|
|
reg _T_15659; // @[Reg.scala 27:20]
|
|
reg _T_15657; // @[Reg.scala 27:20]
|
|
reg _T_15655; // @[Reg.scala 27:20]
|
|
wire [45:0] _T_15790 = {_T_15781,_T_15671,_T_15669,_T_15667,_T_15665,_T_15663,_T_15661,_T_15659,_T_15657,_T_15655}; // @[Cat.scala 29:58]
|
|
reg _T_15653; // @[Reg.scala 27:20]
|
|
reg _T_15651; // @[Reg.scala 27:20]
|
|
reg _T_15649; // @[Reg.scala 27:20]
|
|
reg _T_15647; // @[Reg.scala 27:20]
|
|
reg _T_15645; // @[Reg.scala 27:20]
|
|
reg _T_15643; // @[Reg.scala 27:20]
|
|
reg _T_15641; // @[Reg.scala 27:20]
|
|
reg _T_15639; // @[Reg.scala 27:20]
|
|
reg _T_15637; // @[Reg.scala 27:20]
|
|
wire [54:0] _T_15799 = {_T_15790,_T_15653,_T_15651,_T_15649,_T_15647,_T_15645,_T_15643,_T_15641,_T_15639,_T_15637}; // @[Cat.scala 29:58]
|
|
reg _T_15635; // @[Reg.scala 27:20]
|
|
reg _T_15633; // @[Reg.scala 27:20]
|
|
reg _T_15631; // @[Reg.scala 27:20]
|
|
reg _T_15629; // @[Reg.scala 27:20]
|
|
reg _T_15627; // @[Reg.scala 27:20]
|
|
reg _T_15625; // @[Reg.scala 27:20]
|
|
reg _T_15623; // @[Reg.scala 27:20]
|
|
reg _T_15621; // @[Reg.scala 27:20]
|
|
reg _T_15619; // @[Reg.scala 27:20]
|
|
wire [63:0] _T_15808 = {_T_15799,_T_15635,_T_15633,_T_15631,_T_15629,_T_15627,_T_15625,_T_15623,_T_15621,_T_15619}; // @[Cat.scala 29:58]
|
|
reg _T_15617; // @[Reg.scala 27:20]
|
|
reg _T_15615; // @[Reg.scala 27:20]
|
|
reg _T_15613; // @[Reg.scala 27:20]
|
|
reg _T_15611; // @[Reg.scala 27:20]
|
|
reg _T_15609; // @[Reg.scala 27:20]
|
|
reg _T_15607; // @[Reg.scala 27:20]
|
|
reg _T_15605; // @[Reg.scala 27:20]
|
|
reg _T_15603; // @[Reg.scala 27:20]
|
|
reg _T_15601; // @[Reg.scala 27:20]
|
|
wire [72:0] _T_15817 = {_T_15808,_T_15617,_T_15615,_T_15613,_T_15611,_T_15609,_T_15607,_T_15605,_T_15603,_T_15601}; // @[Cat.scala 29:58]
|
|
reg _T_15599; // @[Reg.scala 27:20]
|
|
reg _T_15597; // @[Reg.scala 27:20]
|
|
reg _T_15595; // @[Reg.scala 27:20]
|
|
reg _T_15593; // @[Reg.scala 27:20]
|
|
reg _T_15591; // @[Reg.scala 27:20]
|
|
reg _T_15589; // @[Reg.scala 27:20]
|
|
reg _T_15587; // @[Reg.scala 27:20]
|
|
reg _T_15585; // @[Reg.scala 27:20]
|
|
reg _T_15583; // @[Reg.scala 27:20]
|
|
wire [81:0] _T_15826 = {_T_15817,_T_15599,_T_15597,_T_15595,_T_15593,_T_15591,_T_15589,_T_15587,_T_15585,_T_15583}; // @[Cat.scala 29:58]
|
|
reg _T_15581; // @[Reg.scala 27:20]
|
|
reg _T_15579; // @[Reg.scala 27:20]
|
|
reg _T_15577; // @[Reg.scala 27:20]
|
|
reg _T_15575; // @[Reg.scala 27:20]
|
|
reg _T_15573; // @[Reg.scala 27:20]
|
|
reg _T_15571; // @[Reg.scala 27:20]
|
|
reg _T_15569; // @[Reg.scala 27:20]
|
|
reg _T_15567; // @[Reg.scala 27:20]
|
|
wire [89:0] fifo_dbg = {_T_15826,_T_15581,_T_15579,_T_15577,_T_15575,_T_15573,_T_15571,_T_15569,_T_15567}; // @[Cat.scala 29:58]
|
|
wire [89:0] _T_16944 = fifo_dbg >> RdPtr; // @[dma_ctrl.scala 198:74]
|
|
wire _T_16946 = ~_T_16944[0]; // @[dma_ctrl.scala 198:65]
|
|
wire _T_16947 = _T_16943 & _T_16946; // @[dma_ctrl.scala 198:63]
|
|
reg [31:0] fifo_addr_89; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_88; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_87; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_86; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_85; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_84; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_83; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_82; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_81; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_80; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_79; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_78; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_77; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_76; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_75; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_74; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_73; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_72; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_71; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_70; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_69; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_68; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_67; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_66; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_65; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_64; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_63; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_62; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_61; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_60; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_59; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_58; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_57; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_56; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_55; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_54; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_53; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_52; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_51; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_50; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_49; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_48; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_47; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_46; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_45; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_44; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_43; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_42; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_41; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_40; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_39; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_38; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_37; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_36; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_35; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_34; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_33; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_32; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_31; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_30; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_29; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_28; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_27; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_26; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_25; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_24; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_23; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_22; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_21; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_20; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_19; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_18; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_17; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_16; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_15; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_14; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_13; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_12; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_11; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_10; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_9; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_8; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_7; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_6; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_5; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_4; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_3; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_2; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_1; // @[Reg.scala 27:20]
|
|
reg [31:0] fifo_addr_0; // @[Reg.scala 27:20]
|
|
wire [31:0] _GEN_1265 = 7'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1266 = 7'h2 == RdPtr ? fifo_addr_2 : _GEN_1265; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1267 = 7'h3 == RdPtr ? fifo_addr_3 : _GEN_1266; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1268 = 7'h4 == RdPtr ? fifo_addr_4 : _GEN_1267; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1269 = 7'h5 == RdPtr ? fifo_addr_5 : _GEN_1268; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1270 = 7'h6 == RdPtr ? fifo_addr_6 : _GEN_1269; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1271 = 7'h7 == RdPtr ? fifo_addr_7 : _GEN_1270; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1272 = 7'h8 == RdPtr ? fifo_addr_8 : _GEN_1271; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1273 = 7'h9 == RdPtr ? fifo_addr_9 : _GEN_1272; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1274 = 7'ha == RdPtr ? fifo_addr_10 : _GEN_1273; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1275 = 7'hb == RdPtr ? fifo_addr_11 : _GEN_1274; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1276 = 7'hc == RdPtr ? fifo_addr_12 : _GEN_1275; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1277 = 7'hd == RdPtr ? fifo_addr_13 : _GEN_1276; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1278 = 7'he == RdPtr ? fifo_addr_14 : _GEN_1277; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1279 = 7'hf == RdPtr ? fifo_addr_15 : _GEN_1278; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1280 = 7'h10 == RdPtr ? fifo_addr_16 : _GEN_1279; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1281 = 7'h11 == RdPtr ? fifo_addr_17 : _GEN_1280; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1282 = 7'h12 == RdPtr ? fifo_addr_18 : _GEN_1281; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1283 = 7'h13 == RdPtr ? fifo_addr_19 : _GEN_1282; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1284 = 7'h14 == RdPtr ? fifo_addr_20 : _GEN_1283; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1285 = 7'h15 == RdPtr ? fifo_addr_21 : _GEN_1284; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1286 = 7'h16 == RdPtr ? fifo_addr_22 : _GEN_1285; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1287 = 7'h17 == RdPtr ? fifo_addr_23 : _GEN_1286; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1288 = 7'h18 == RdPtr ? fifo_addr_24 : _GEN_1287; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1289 = 7'h19 == RdPtr ? fifo_addr_25 : _GEN_1288; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1290 = 7'h1a == RdPtr ? fifo_addr_26 : _GEN_1289; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1291 = 7'h1b == RdPtr ? fifo_addr_27 : _GEN_1290; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1292 = 7'h1c == RdPtr ? fifo_addr_28 : _GEN_1291; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1293 = 7'h1d == RdPtr ? fifo_addr_29 : _GEN_1292; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1294 = 7'h1e == RdPtr ? fifo_addr_30 : _GEN_1293; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1295 = 7'h1f == RdPtr ? fifo_addr_31 : _GEN_1294; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1296 = 7'h20 == RdPtr ? fifo_addr_32 : _GEN_1295; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1297 = 7'h21 == RdPtr ? fifo_addr_33 : _GEN_1296; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1298 = 7'h22 == RdPtr ? fifo_addr_34 : _GEN_1297; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1299 = 7'h23 == RdPtr ? fifo_addr_35 : _GEN_1298; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1300 = 7'h24 == RdPtr ? fifo_addr_36 : _GEN_1299; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1301 = 7'h25 == RdPtr ? fifo_addr_37 : _GEN_1300; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1302 = 7'h26 == RdPtr ? fifo_addr_38 : _GEN_1301; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1303 = 7'h27 == RdPtr ? fifo_addr_39 : _GEN_1302; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1304 = 7'h28 == RdPtr ? fifo_addr_40 : _GEN_1303; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1305 = 7'h29 == RdPtr ? fifo_addr_41 : _GEN_1304; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1306 = 7'h2a == RdPtr ? fifo_addr_42 : _GEN_1305; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1307 = 7'h2b == RdPtr ? fifo_addr_43 : _GEN_1306; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1308 = 7'h2c == RdPtr ? fifo_addr_44 : _GEN_1307; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1309 = 7'h2d == RdPtr ? fifo_addr_45 : _GEN_1308; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1310 = 7'h2e == RdPtr ? fifo_addr_46 : _GEN_1309; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1311 = 7'h2f == RdPtr ? fifo_addr_47 : _GEN_1310; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1312 = 7'h30 == RdPtr ? fifo_addr_48 : _GEN_1311; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1313 = 7'h31 == RdPtr ? fifo_addr_49 : _GEN_1312; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1314 = 7'h32 == RdPtr ? fifo_addr_50 : _GEN_1313; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1315 = 7'h33 == RdPtr ? fifo_addr_51 : _GEN_1314; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1316 = 7'h34 == RdPtr ? fifo_addr_52 : _GEN_1315; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1317 = 7'h35 == RdPtr ? fifo_addr_53 : _GEN_1316; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1318 = 7'h36 == RdPtr ? fifo_addr_54 : _GEN_1317; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1319 = 7'h37 == RdPtr ? fifo_addr_55 : _GEN_1318; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1320 = 7'h38 == RdPtr ? fifo_addr_56 : _GEN_1319; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1321 = 7'h39 == RdPtr ? fifo_addr_57 : _GEN_1320; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1322 = 7'h3a == RdPtr ? fifo_addr_58 : _GEN_1321; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1323 = 7'h3b == RdPtr ? fifo_addr_59 : _GEN_1322; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1324 = 7'h3c == RdPtr ? fifo_addr_60 : _GEN_1323; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1325 = 7'h3d == RdPtr ? fifo_addr_61 : _GEN_1324; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1326 = 7'h3e == RdPtr ? fifo_addr_62 : _GEN_1325; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1327 = 7'h3f == RdPtr ? fifo_addr_63 : _GEN_1326; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1328 = 7'h40 == RdPtr ? fifo_addr_64 : _GEN_1327; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1329 = 7'h41 == RdPtr ? fifo_addr_65 : _GEN_1328; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1330 = 7'h42 == RdPtr ? fifo_addr_66 : _GEN_1329; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1331 = 7'h43 == RdPtr ? fifo_addr_67 : _GEN_1330; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1332 = 7'h44 == RdPtr ? fifo_addr_68 : _GEN_1331; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1333 = 7'h45 == RdPtr ? fifo_addr_69 : _GEN_1332; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1334 = 7'h46 == RdPtr ? fifo_addr_70 : _GEN_1333; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1335 = 7'h47 == RdPtr ? fifo_addr_71 : _GEN_1334; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1336 = 7'h48 == RdPtr ? fifo_addr_72 : _GEN_1335; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1337 = 7'h49 == RdPtr ? fifo_addr_73 : _GEN_1336; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1338 = 7'h4a == RdPtr ? fifo_addr_74 : _GEN_1337; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1339 = 7'h4b == RdPtr ? fifo_addr_75 : _GEN_1338; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1340 = 7'h4c == RdPtr ? fifo_addr_76 : _GEN_1339; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1341 = 7'h4d == RdPtr ? fifo_addr_77 : _GEN_1340; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1342 = 7'h4e == RdPtr ? fifo_addr_78 : _GEN_1341; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1343 = 7'h4f == RdPtr ? fifo_addr_79 : _GEN_1342; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1344 = 7'h50 == RdPtr ? fifo_addr_80 : _GEN_1343; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1345 = 7'h51 == RdPtr ? fifo_addr_81 : _GEN_1344; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1346 = 7'h52 == RdPtr ? fifo_addr_82 : _GEN_1345; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1347 = 7'h53 == RdPtr ? fifo_addr_83 : _GEN_1346; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1348 = 7'h54 == RdPtr ? fifo_addr_84 : _GEN_1347; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1349 = 7'h55 == RdPtr ? fifo_addr_85 : _GEN_1348; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1350 = 7'h56 == RdPtr ? fifo_addr_86 : _GEN_1349; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1351 = 7'h57 == RdPtr ? fifo_addr_87 : _GEN_1350; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] _GEN_1352 = 7'h58 == RdPtr ? fifo_addr_88 : _GEN_1351; // @[dma_ctrl.scala 267:24]
|
|
wire [31:0] dma_mem_addr_int = 7'h59 == RdPtr ? fifo_addr_89 : _GEN_1352; // @[dma_ctrl.scala 267:24]
|
|
wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 381:39]
|
|
wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 381:39]
|
|
wire _T_16948 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[dma_ctrl.scala 198:108]
|
|
wire _T_16949 = ~_T_16948; // @[dma_ctrl.scala 198:85]
|
|
wire dma_address_error = _T_16947 & _T_16949; // @[dma_ctrl.scala 198:82]
|
|
wire _T_16961 = ~dma_address_error; // @[dma_ctrl.scala 200:88]
|
|
wire _T_16962 = _T_16947 & _T_16961; // @[dma_ctrl.scala 200:86]
|
|
reg [2:0] fifo_sz_89; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_88; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_87; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_86; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_85; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_84; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_83; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_82; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_81; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_80; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_79; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_78; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_77; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_76; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_75; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_74; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_73; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_72; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_71; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_70; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_69; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_68; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_67; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_66; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_65; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_64; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_63; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_62; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_61; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_60; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_59; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_58; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_57; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_56; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_55; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_54; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_53; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_52; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_51; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_50; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_49; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_48; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_47; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_46; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_45; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_44; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_43; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_42; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_41; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_40; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_39; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_38; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_37; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_36; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_35; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_34; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_33; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_32; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_31; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_30; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_29; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_28; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_27; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_26; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_25; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_24; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_23; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_22; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_21; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_20; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_19; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_18; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_17; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_16; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_15; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_14; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_13; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_12; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_11; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_10; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_9; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_8; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_7; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_6; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_5; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_4; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_3; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_2; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_1; // @[Reg.scala 27:20]
|
|
reg [2:0] fifo_sz_0; // @[Reg.scala 27:20]
|
|
wire [2:0] _GEN_1355 = 7'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1356 = 7'h2 == RdPtr ? fifo_sz_2 : _GEN_1355; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1357 = 7'h3 == RdPtr ? fifo_sz_3 : _GEN_1356; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1358 = 7'h4 == RdPtr ? fifo_sz_4 : _GEN_1357; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1359 = 7'h5 == RdPtr ? fifo_sz_5 : _GEN_1358; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1360 = 7'h6 == RdPtr ? fifo_sz_6 : _GEN_1359; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1361 = 7'h7 == RdPtr ? fifo_sz_7 : _GEN_1360; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1362 = 7'h8 == RdPtr ? fifo_sz_8 : _GEN_1361; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1363 = 7'h9 == RdPtr ? fifo_sz_9 : _GEN_1362; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1364 = 7'ha == RdPtr ? fifo_sz_10 : _GEN_1363; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1365 = 7'hb == RdPtr ? fifo_sz_11 : _GEN_1364; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1366 = 7'hc == RdPtr ? fifo_sz_12 : _GEN_1365; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1367 = 7'hd == RdPtr ? fifo_sz_13 : _GEN_1366; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1368 = 7'he == RdPtr ? fifo_sz_14 : _GEN_1367; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1369 = 7'hf == RdPtr ? fifo_sz_15 : _GEN_1368; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1370 = 7'h10 == RdPtr ? fifo_sz_16 : _GEN_1369; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1371 = 7'h11 == RdPtr ? fifo_sz_17 : _GEN_1370; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1372 = 7'h12 == RdPtr ? fifo_sz_18 : _GEN_1371; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1373 = 7'h13 == RdPtr ? fifo_sz_19 : _GEN_1372; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1374 = 7'h14 == RdPtr ? fifo_sz_20 : _GEN_1373; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1375 = 7'h15 == RdPtr ? fifo_sz_21 : _GEN_1374; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1376 = 7'h16 == RdPtr ? fifo_sz_22 : _GEN_1375; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1377 = 7'h17 == RdPtr ? fifo_sz_23 : _GEN_1376; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1378 = 7'h18 == RdPtr ? fifo_sz_24 : _GEN_1377; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1379 = 7'h19 == RdPtr ? fifo_sz_25 : _GEN_1378; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1380 = 7'h1a == RdPtr ? fifo_sz_26 : _GEN_1379; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1381 = 7'h1b == RdPtr ? fifo_sz_27 : _GEN_1380; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1382 = 7'h1c == RdPtr ? fifo_sz_28 : _GEN_1381; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1383 = 7'h1d == RdPtr ? fifo_sz_29 : _GEN_1382; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1384 = 7'h1e == RdPtr ? fifo_sz_30 : _GEN_1383; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1385 = 7'h1f == RdPtr ? fifo_sz_31 : _GEN_1384; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1386 = 7'h20 == RdPtr ? fifo_sz_32 : _GEN_1385; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1387 = 7'h21 == RdPtr ? fifo_sz_33 : _GEN_1386; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1388 = 7'h22 == RdPtr ? fifo_sz_34 : _GEN_1387; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1389 = 7'h23 == RdPtr ? fifo_sz_35 : _GEN_1388; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1390 = 7'h24 == RdPtr ? fifo_sz_36 : _GEN_1389; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1391 = 7'h25 == RdPtr ? fifo_sz_37 : _GEN_1390; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1392 = 7'h26 == RdPtr ? fifo_sz_38 : _GEN_1391; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1393 = 7'h27 == RdPtr ? fifo_sz_39 : _GEN_1392; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1394 = 7'h28 == RdPtr ? fifo_sz_40 : _GEN_1393; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1395 = 7'h29 == RdPtr ? fifo_sz_41 : _GEN_1394; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1396 = 7'h2a == RdPtr ? fifo_sz_42 : _GEN_1395; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1397 = 7'h2b == RdPtr ? fifo_sz_43 : _GEN_1396; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1398 = 7'h2c == RdPtr ? fifo_sz_44 : _GEN_1397; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1399 = 7'h2d == RdPtr ? fifo_sz_45 : _GEN_1398; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1400 = 7'h2e == RdPtr ? fifo_sz_46 : _GEN_1399; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1401 = 7'h2f == RdPtr ? fifo_sz_47 : _GEN_1400; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1402 = 7'h30 == RdPtr ? fifo_sz_48 : _GEN_1401; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1403 = 7'h31 == RdPtr ? fifo_sz_49 : _GEN_1402; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1404 = 7'h32 == RdPtr ? fifo_sz_50 : _GEN_1403; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1405 = 7'h33 == RdPtr ? fifo_sz_51 : _GEN_1404; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1406 = 7'h34 == RdPtr ? fifo_sz_52 : _GEN_1405; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1407 = 7'h35 == RdPtr ? fifo_sz_53 : _GEN_1406; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1408 = 7'h36 == RdPtr ? fifo_sz_54 : _GEN_1407; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1409 = 7'h37 == RdPtr ? fifo_sz_55 : _GEN_1408; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1410 = 7'h38 == RdPtr ? fifo_sz_56 : _GEN_1409; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1411 = 7'h39 == RdPtr ? fifo_sz_57 : _GEN_1410; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1412 = 7'h3a == RdPtr ? fifo_sz_58 : _GEN_1411; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1413 = 7'h3b == RdPtr ? fifo_sz_59 : _GEN_1412; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1414 = 7'h3c == RdPtr ? fifo_sz_60 : _GEN_1413; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1415 = 7'h3d == RdPtr ? fifo_sz_61 : _GEN_1414; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1416 = 7'h3e == RdPtr ? fifo_sz_62 : _GEN_1415; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1417 = 7'h3f == RdPtr ? fifo_sz_63 : _GEN_1416; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1418 = 7'h40 == RdPtr ? fifo_sz_64 : _GEN_1417; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1419 = 7'h41 == RdPtr ? fifo_sz_65 : _GEN_1418; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1420 = 7'h42 == RdPtr ? fifo_sz_66 : _GEN_1419; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1421 = 7'h43 == RdPtr ? fifo_sz_67 : _GEN_1420; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1422 = 7'h44 == RdPtr ? fifo_sz_68 : _GEN_1421; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1423 = 7'h45 == RdPtr ? fifo_sz_69 : _GEN_1422; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1424 = 7'h46 == RdPtr ? fifo_sz_70 : _GEN_1423; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1425 = 7'h47 == RdPtr ? fifo_sz_71 : _GEN_1424; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1426 = 7'h48 == RdPtr ? fifo_sz_72 : _GEN_1425; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1427 = 7'h49 == RdPtr ? fifo_sz_73 : _GEN_1426; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1428 = 7'h4a == RdPtr ? fifo_sz_74 : _GEN_1427; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1429 = 7'h4b == RdPtr ? fifo_sz_75 : _GEN_1428; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1430 = 7'h4c == RdPtr ? fifo_sz_76 : _GEN_1429; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1431 = 7'h4d == RdPtr ? fifo_sz_77 : _GEN_1430; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1432 = 7'h4e == RdPtr ? fifo_sz_78 : _GEN_1431; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1433 = 7'h4f == RdPtr ? fifo_sz_79 : _GEN_1432; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1434 = 7'h50 == RdPtr ? fifo_sz_80 : _GEN_1433; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1435 = 7'h51 == RdPtr ? fifo_sz_81 : _GEN_1434; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1436 = 7'h52 == RdPtr ? fifo_sz_82 : _GEN_1435; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1437 = 7'h53 == RdPtr ? fifo_sz_83 : _GEN_1436; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1438 = 7'h54 == RdPtr ? fifo_sz_84 : _GEN_1437; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1439 = 7'h55 == RdPtr ? fifo_sz_85 : _GEN_1438; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1440 = 7'h56 == RdPtr ? fifo_sz_86 : _GEN_1439; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1441 = 7'h57 == RdPtr ? fifo_sz_87 : _GEN_1440; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] _GEN_1442 = 7'h58 == RdPtr ? fifo_sz_88 : _GEN_1441; // @[dma_ctrl.scala 268:24]
|
|
wire [2:0] dma_mem_sz_int = 7'h59 == RdPtr ? fifo_sz_89 : _GEN_1442; // @[dma_ctrl.scala 268:24]
|
|
wire _T_16964 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 201:28]
|
|
wire _T_16966 = _T_16964 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 201:37]
|
|
wire _T_16968 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 202:29]
|
|
wire _T_16970 = |dma_mem_addr_int[1:0]; // @[dma_ctrl.scala 202:64]
|
|
wire _T_16971 = _T_16968 & _T_16970; // @[dma_ctrl.scala 202:38]
|
|
wire _T_16972 = _T_16966 | _T_16971; // @[dma_ctrl.scala 201:60]
|
|
wire _T_16974 = dma_mem_sz_int == 3'h3; // @[dma_ctrl.scala 203:29]
|
|
wire _T_16976 = |dma_mem_addr_int[2:0]; // @[dma_ctrl.scala 203:64]
|
|
wire _T_16977 = _T_16974 & _T_16976; // @[dma_ctrl.scala 203:38]
|
|
wire _T_16978 = _T_16972 | _T_16977; // @[dma_ctrl.scala 202:70]
|
|
wire _T_16980 = dma_mem_sz_int[1:0] == 2'h2; // @[dma_ctrl.scala 204:55]
|
|
wire _T_16982 = dma_mem_sz_int[1:0] == 2'h3; // @[dma_ctrl.scala 204:88]
|
|
wire _T_16983 = _T_16980 | _T_16982; // @[dma_ctrl.scala 204:64]
|
|
wire _T_16984 = ~_T_16983; // @[dma_ctrl.scala 204:31]
|
|
wire _T_16985 = dma_mem_addr_in_iccm & _T_16984; // @[dma_ctrl.scala 204:29]
|
|
wire _T_16986 = _T_16978 | _T_16985; // @[dma_ctrl.scala 203:70]
|
|
wire _T_16987 = dma_mem_addr_in_dccm & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 205:29]
|
|
wire _T_16994 = _T_16987 & _T_16984; // @[dma_ctrl.scala 205:68]
|
|
wire _T_16995 = _T_16986 | _T_16994; // @[dma_ctrl.scala 204:108]
|
|
wire _T_16998 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_16968; // @[dma_ctrl.scala 206:45]
|
|
wire _T_17000 = dma_mem_addr_int[2:0] == 3'h0; // @[dma_ctrl.scala 206:114]
|
|
reg [7:0] fifo_byteen_89; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_88; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_87; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_86; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_85; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_84; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_83; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_82; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_81; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_80; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_79; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_78; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_77; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_76; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_75; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_74; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_73; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_72; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_71; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_70; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_69; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_68; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_67; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_66; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_65; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_64; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_63; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_62; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_61; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_60; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_59; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_58; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_57; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_56; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_55; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_54; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_53; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_52; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_51; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_50; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_49; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_48; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_47; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_46; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_45; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_44; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_43; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_42; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_41; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_40; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_39; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_38; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_37; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_36; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_35; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_34; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_33; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_32; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_31; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_30; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_29; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_28; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_27; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_26; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_25; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_24; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_23; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_22; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_21; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_20; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_19; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_18; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_17; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_16; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_15; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_14; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_13; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_12; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_11; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_10; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_9; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_8; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_7; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_6; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_5; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_4; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_3; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20]
|
|
reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20]
|
|
wire [7:0] _GEN_1445 = 7'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1446 = 7'h2 == RdPtr ? fifo_byteen_2 : _GEN_1445; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1447 = 7'h3 == RdPtr ? fifo_byteen_3 : _GEN_1446; // @[dma_ctrl.scala 274:24]
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|
wire [7:0] _GEN_1448 = 7'h4 == RdPtr ? fifo_byteen_4 : _GEN_1447; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1449 = 7'h5 == RdPtr ? fifo_byteen_5 : _GEN_1448; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1450 = 7'h6 == RdPtr ? fifo_byteen_6 : _GEN_1449; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1451 = 7'h7 == RdPtr ? fifo_byteen_7 : _GEN_1450; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1452 = 7'h8 == RdPtr ? fifo_byteen_8 : _GEN_1451; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1453 = 7'h9 == RdPtr ? fifo_byteen_9 : _GEN_1452; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1454 = 7'ha == RdPtr ? fifo_byteen_10 : _GEN_1453; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1455 = 7'hb == RdPtr ? fifo_byteen_11 : _GEN_1454; // @[dma_ctrl.scala 274:24]
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wire [7:0] _GEN_1456 = 7'hc == RdPtr ? fifo_byteen_12 : _GEN_1455; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1457 = 7'hd == RdPtr ? fifo_byteen_13 : _GEN_1456; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1458 = 7'he == RdPtr ? fifo_byteen_14 : _GEN_1457; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1459 = 7'hf == RdPtr ? fifo_byteen_15 : _GEN_1458; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1460 = 7'h10 == RdPtr ? fifo_byteen_16 : _GEN_1459; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1461 = 7'h11 == RdPtr ? fifo_byteen_17 : _GEN_1460; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1462 = 7'h12 == RdPtr ? fifo_byteen_18 : _GEN_1461; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1463 = 7'h13 == RdPtr ? fifo_byteen_19 : _GEN_1462; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1464 = 7'h14 == RdPtr ? fifo_byteen_20 : _GEN_1463; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1465 = 7'h15 == RdPtr ? fifo_byteen_21 : _GEN_1464; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1466 = 7'h16 == RdPtr ? fifo_byteen_22 : _GEN_1465; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1467 = 7'h17 == RdPtr ? fifo_byteen_23 : _GEN_1466; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1468 = 7'h18 == RdPtr ? fifo_byteen_24 : _GEN_1467; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1469 = 7'h19 == RdPtr ? fifo_byteen_25 : _GEN_1468; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1470 = 7'h1a == RdPtr ? fifo_byteen_26 : _GEN_1469; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1471 = 7'h1b == RdPtr ? fifo_byteen_27 : _GEN_1470; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1472 = 7'h1c == RdPtr ? fifo_byteen_28 : _GEN_1471; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1473 = 7'h1d == RdPtr ? fifo_byteen_29 : _GEN_1472; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1474 = 7'h1e == RdPtr ? fifo_byteen_30 : _GEN_1473; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1475 = 7'h1f == RdPtr ? fifo_byteen_31 : _GEN_1474; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1476 = 7'h20 == RdPtr ? fifo_byteen_32 : _GEN_1475; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1477 = 7'h21 == RdPtr ? fifo_byteen_33 : _GEN_1476; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1478 = 7'h22 == RdPtr ? fifo_byteen_34 : _GEN_1477; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1479 = 7'h23 == RdPtr ? fifo_byteen_35 : _GEN_1478; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1480 = 7'h24 == RdPtr ? fifo_byteen_36 : _GEN_1479; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1481 = 7'h25 == RdPtr ? fifo_byteen_37 : _GEN_1480; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1482 = 7'h26 == RdPtr ? fifo_byteen_38 : _GEN_1481; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1483 = 7'h27 == RdPtr ? fifo_byteen_39 : _GEN_1482; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1484 = 7'h28 == RdPtr ? fifo_byteen_40 : _GEN_1483; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1485 = 7'h29 == RdPtr ? fifo_byteen_41 : _GEN_1484; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1486 = 7'h2a == RdPtr ? fifo_byteen_42 : _GEN_1485; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1487 = 7'h2b == RdPtr ? fifo_byteen_43 : _GEN_1486; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1488 = 7'h2c == RdPtr ? fifo_byteen_44 : _GEN_1487; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1489 = 7'h2d == RdPtr ? fifo_byteen_45 : _GEN_1488; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1490 = 7'h2e == RdPtr ? fifo_byteen_46 : _GEN_1489; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1491 = 7'h2f == RdPtr ? fifo_byteen_47 : _GEN_1490; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1492 = 7'h30 == RdPtr ? fifo_byteen_48 : _GEN_1491; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1493 = 7'h31 == RdPtr ? fifo_byteen_49 : _GEN_1492; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1494 = 7'h32 == RdPtr ? fifo_byteen_50 : _GEN_1493; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1495 = 7'h33 == RdPtr ? fifo_byteen_51 : _GEN_1494; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1496 = 7'h34 == RdPtr ? fifo_byteen_52 : _GEN_1495; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1497 = 7'h35 == RdPtr ? fifo_byteen_53 : _GEN_1496; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1498 = 7'h36 == RdPtr ? fifo_byteen_54 : _GEN_1497; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1499 = 7'h37 == RdPtr ? fifo_byteen_55 : _GEN_1498; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1500 = 7'h38 == RdPtr ? fifo_byteen_56 : _GEN_1499; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1501 = 7'h39 == RdPtr ? fifo_byteen_57 : _GEN_1500; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1502 = 7'h3a == RdPtr ? fifo_byteen_58 : _GEN_1501; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1503 = 7'h3b == RdPtr ? fifo_byteen_59 : _GEN_1502; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1504 = 7'h3c == RdPtr ? fifo_byteen_60 : _GEN_1503; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1505 = 7'h3d == RdPtr ? fifo_byteen_61 : _GEN_1504; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1506 = 7'h3e == RdPtr ? fifo_byteen_62 : _GEN_1505; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1507 = 7'h3f == RdPtr ? fifo_byteen_63 : _GEN_1506; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1508 = 7'h40 == RdPtr ? fifo_byteen_64 : _GEN_1507; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1509 = 7'h41 == RdPtr ? fifo_byteen_65 : _GEN_1508; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1510 = 7'h42 == RdPtr ? fifo_byteen_66 : _GEN_1509; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1511 = 7'h43 == RdPtr ? fifo_byteen_67 : _GEN_1510; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1512 = 7'h44 == RdPtr ? fifo_byteen_68 : _GEN_1511; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1513 = 7'h45 == RdPtr ? fifo_byteen_69 : _GEN_1512; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1514 = 7'h46 == RdPtr ? fifo_byteen_70 : _GEN_1513; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1515 = 7'h47 == RdPtr ? fifo_byteen_71 : _GEN_1514; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1516 = 7'h48 == RdPtr ? fifo_byteen_72 : _GEN_1515; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1517 = 7'h49 == RdPtr ? fifo_byteen_73 : _GEN_1516; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1518 = 7'h4a == RdPtr ? fifo_byteen_74 : _GEN_1517; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1519 = 7'h4b == RdPtr ? fifo_byteen_75 : _GEN_1518; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1520 = 7'h4c == RdPtr ? fifo_byteen_76 : _GEN_1519; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1521 = 7'h4d == RdPtr ? fifo_byteen_77 : _GEN_1520; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1522 = 7'h4e == RdPtr ? fifo_byteen_78 : _GEN_1521; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1523 = 7'h4f == RdPtr ? fifo_byteen_79 : _GEN_1522; // @[dma_ctrl.scala 274:24]
|
|
wire [7:0] _GEN_1524 = 7'h50 == RdPtr ? fifo_byteen_80 : _GEN_1523; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1525 = 7'h51 == RdPtr ? fifo_byteen_81 : _GEN_1524; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1526 = 7'h52 == RdPtr ? fifo_byteen_82 : _GEN_1525; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1527 = 7'h53 == RdPtr ? fifo_byteen_83 : _GEN_1526; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1528 = 7'h54 == RdPtr ? fifo_byteen_84 : _GEN_1527; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1529 = 7'h55 == RdPtr ? fifo_byteen_85 : _GEN_1528; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1530 = 7'h56 == RdPtr ? fifo_byteen_86 : _GEN_1529; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1531 = 7'h57 == RdPtr ? fifo_byteen_87 : _GEN_1530; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] _GEN_1532 = 7'h58 == RdPtr ? fifo_byteen_88 : _GEN_1531; // @[dma_ctrl.scala 274:24]
|
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wire [7:0] dma_mem_byteen = 7'h59 == RdPtr ? fifo_byteen_89 : _GEN_1532; // @[dma_ctrl.scala 274:24]
|
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wire [3:0] _T_17023 = _T_17000 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
|
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wire _T_17003 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 207:32]
|
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wire [3:0] _T_17024 = _T_17003 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
|
|
wire [3:0] _T_17031 = _T_17023 | _T_17024; // @[Mux.scala 27:72]
|
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wire _T_17006 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 208:32]
|
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wire [3:0] _T_17025 = _T_17006 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17032 = _T_17031 | _T_17025; // @[Mux.scala 27:72]
|
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wire _T_17009 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 209:32]
|
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wire [3:0] _T_17026 = _T_17009 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17033 = _T_17032 | _T_17026; // @[Mux.scala 27:72]
|
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wire _T_17012 = dma_mem_addr_int[2:0] == 3'h4; // @[dma_ctrl.scala 210:32]
|
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wire [3:0] _T_17027 = _T_17012 ? dma_mem_byteen[7:4] : 4'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17034 = _T_17033 | _T_17027; // @[Mux.scala 27:72]
|
|
wire _T_17015 = dma_mem_addr_int[2:0] == 3'h5; // @[dma_ctrl.scala 211:32]
|
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wire [2:0] _T_17028 = _T_17015 ? dma_mem_byteen[7:5] : 3'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _GEN_1728 = {{1'd0}, _T_17028}; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17035 = _T_17034 | _GEN_1728; // @[Mux.scala 27:72]
|
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wire _T_17018 = dma_mem_addr_int[2:0] == 3'h6; // @[dma_ctrl.scala 212:32]
|
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wire [1:0] _T_17029 = _T_17018 ? dma_mem_byteen[7:6] : 2'h0; // @[Mux.scala 27:72]
|
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wire [3:0] _GEN_1729 = {{2'd0}, _T_17029}; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17036 = _T_17035 | _GEN_1729; // @[Mux.scala 27:72]
|
|
wire _T_17021 = dma_mem_addr_int[2:0] == 3'h7; // @[dma_ctrl.scala 213:32]
|
|
wire _T_17030 = _T_17021 & dma_mem_byteen[7]; // @[Mux.scala 27:72]
|
|
wire [3:0] _GEN_1730 = {{3'd0}, _T_17030}; // @[Mux.scala 27:72]
|
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wire [3:0] _T_17037 = _T_17036 | _GEN_1730; // @[Mux.scala 27:72]
|
|
wire _T_17039 = _T_17037 != 4'hf; // @[dma_ctrl.scala 213:66]
|
|
wire _T_17040 = _T_16998 & _T_17039; // @[dma_ctrl.scala 206:78]
|
|
wire _T_17041 = _T_16995 | _T_17040; // @[dma_ctrl.scala 205:145]
|
|
wire _T_17044 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_16974; // @[dma_ctrl.scala 214:45]
|
|
wire _T_17046 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 214:103]
|
|
wire _T_17048 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 214:139]
|
|
wire _T_17049 = _T_17046 | _T_17048; // @[dma_ctrl.scala 214:116]
|
|
wire _T_17051 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 214:175]
|
|
wire _T_17052 = _T_17049 | _T_17051; // @[dma_ctrl.scala 214:152]
|
|
wire _T_17053 = ~_T_17052; // @[dma_ctrl.scala 214:80]
|
|
wire _T_17054 = _T_17044 & _T_17053; // @[dma_ctrl.scala 214:78]
|
|
wire _T_17055 = _T_17041 | _T_17054; // @[dma_ctrl.scala 213:79]
|
|
wire dma_alignment_error = _T_16962 & _T_17055; // @[dma_ctrl.scala 200:107]
|
|
wire _T_830 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 122:279]
|
|
wire _T_831 = 7'h0 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_832 = _T_830 & _T_831; // @[dma_ctrl.scala 122:302]
|
|
wire _T_833 = _T_829 | _T_832; // @[dma_ctrl.scala 122:257]
|
|
wire _T_834 = 3'h0 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_835 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_834; // @[dma_ctrl.scala 122:373]
|
|
wire _T_836 = _T_833 | _T_835; // @[dma_ctrl.scala 122:330]
|
|
wire _T_837 = 3'h0 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_838 = io_iccm_dma_rvalid & _T_837; // @[dma_ctrl.scala 122:455]
|
|
wire _T_839 = _T_836 | _T_838; // @[dma_ctrl.scala 122:433]
|
|
wire _T_847 = _T_827 & _T_27; // @[dma_ctrl.scala 122:229]
|
|
wire _T_849 = 7'h1 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_850 = _T_830 & _T_849; // @[dma_ctrl.scala 122:302]
|
|
wire _T_851 = _T_847 | _T_850; // @[dma_ctrl.scala 122:257]
|
|
wire _T_852 = 3'h1 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_853 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_852; // @[dma_ctrl.scala 122:373]
|
|
wire _T_854 = _T_851 | _T_853; // @[dma_ctrl.scala 122:330]
|
|
wire _T_855 = 3'h1 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_856 = io_iccm_dma_rvalid & _T_855; // @[dma_ctrl.scala 122:455]
|
|
wire _T_857 = _T_854 | _T_856; // @[dma_ctrl.scala 122:433]
|
|
wire _T_865 = _T_827 & _T_35; // @[dma_ctrl.scala 122:229]
|
|
wire _T_867 = 7'h2 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_868 = _T_830 & _T_867; // @[dma_ctrl.scala 122:302]
|
|
wire _T_869 = _T_865 | _T_868; // @[dma_ctrl.scala 122:257]
|
|
wire _T_870 = 3'h2 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_871 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_870; // @[dma_ctrl.scala 122:373]
|
|
wire _T_872 = _T_869 | _T_871; // @[dma_ctrl.scala 122:330]
|
|
wire _T_873 = 3'h2 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_874 = io_iccm_dma_rvalid & _T_873; // @[dma_ctrl.scala 122:455]
|
|
wire _T_875 = _T_872 | _T_874; // @[dma_ctrl.scala 122:433]
|
|
wire _T_883 = _T_827 & _T_43; // @[dma_ctrl.scala 122:229]
|
|
wire _T_885 = 7'h3 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_886 = _T_830 & _T_885; // @[dma_ctrl.scala 122:302]
|
|
wire _T_887 = _T_883 | _T_886; // @[dma_ctrl.scala 122:257]
|
|
wire _T_888 = 3'h3 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_889 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_888; // @[dma_ctrl.scala 122:373]
|
|
wire _T_890 = _T_887 | _T_889; // @[dma_ctrl.scala 122:330]
|
|
wire _T_891 = 3'h3 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_892 = io_iccm_dma_rvalid & _T_891; // @[dma_ctrl.scala 122:455]
|
|
wire _T_893 = _T_890 | _T_892; // @[dma_ctrl.scala 122:433]
|
|
wire _T_901 = _T_827 & _T_51; // @[dma_ctrl.scala 122:229]
|
|
wire _T_903 = 7'h4 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_904 = _T_830 & _T_903; // @[dma_ctrl.scala 122:302]
|
|
wire _T_905 = _T_901 | _T_904; // @[dma_ctrl.scala 122:257]
|
|
wire _T_906 = 3'h4 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_907 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_906; // @[dma_ctrl.scala 122:373]
|
|
wire _T_908 = _T_905 | _T_907; // @[dma_ctrl.scala 122:330]
|
|
wire _T_909 = 3'h4 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_910 = io_iccm_dma_rvalid & _T_909; // @[dma_ctrl.scala 122:455]
|
|
wire _T_911 = _T_908 | _T_910; // @[dma_ctrl.scala 122:433]
|
|
wire _T_919 = _T_827 & _T_59; // @[dma_ctrl.scala 122:229]
|
|
wire _T_921 = 7'h5 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_922 = _T_830 & _T_921; // @[dma_ctrl.scala 122:302]
|
|
wire _T_923 = _T_919 | _T_922; // @[dma_ctrl.scala 122:257]
|
|
wire _T_924 = 3'h5 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_925 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_924; // @[dma_ctrl.scala 122:373]
|
|
wire _T_926 = _T_923 | _T_925; // @[dma_ctrl.scala 122:330]
|
|
wire _T_927 = 3'h5 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_928 = io_iccm_dma_rvalid & _T_927; // @[dma_ctrl.scala 122:455]
|
|
wire _T_929 = _T_926 | _T_928; // @[dma_ctrl.scala 122:433]
|
|
wire _T_937 = _T_827 & _T_67; // @[dma_ctrl.scala 122:229]
|
|
wire _T_939 = 7'h6 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_940 = _T_830 & _T_939; // @[dma_ctrl.scala 122:302]
|
|
wire _T_941 = _T_937 | _T_940; // @[dma_ctrl.scala 122:257]
|
|
wire _T_942 = 3'h6 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_943 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_942; // @[dma_ctrl.scala 122:373]
|
|
wire _T_944 = _T_941 | _T_943; // @[dma_ctrl.scala 122:330]
|
|
wire _T_945 = 3'h6 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_946 = io_iccm_dma_rvalid & _T_945; // @[dma_ctrl.scala 122:455]
|
|
wire _T_947 = _T_944 | _T_946; // @[dma_ctrl.scala 122:433]
|
|
wire _T_955 = _T_827 & _T_75; // @[dma_ctrl.scala 122:229]
|
|
wire _T_957 = 7'h7 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_958 = _T_830 & _T_957; // @[dma_ctrl.scala 122:302]
|
|
wire _T_959 = _T_955 | _T_958; // @[dma_ctrl.scala 122:257]
|
|
wire _T_960 = 3'h7 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 122:380]
|
|
wire _T_961 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_960; // @[dma_ctrl.scala 122:373]
|
|
wire _T_962 = _T_959 | _T_961; // @[dma_ctrl.scala 122:330]
|
|
wire _T_963 = 3'h7 == io_iccm_dma_rtag; // @[dma_ctrl.scala 122:462]
|
|
wire _T_964 = io_iccm_dma_rvalid & _T_963; // @[dma_ctrl.scala 122:455]
|
|
wire _T_965 = _T_962 | _T_964; // @[dma_ctrl.scala 122:433]
|
|
wire _T_973 = _T_827 & _T_83; // @[dma_ctrl.scala 122:229]
|
|
wire _T_975 = 7'h8 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_976 = _T_830 & _T_975; // @[dma_ctrl.scala 122:302]
|
|
wire _T_977 = _T_973 | _T_976; // @[dma_ctrl.scala 122:257]
|
|
wire [3:0] _GEN_1731 = {{1'd0}, io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag}; // @[dma_ctrl.scala 122:380]
|
|
wire _T_978 = 4'h8 == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_979 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_978; // @[dma_ctrl.scala 122:373]
|
|
wire _T_980 = _T_977 | _T_979; // @[dma_ctrl.scala 122:330]
|
|
wire [3:0] _GEN_1732 = {{1'd0}, io_iccm_dma_rtag}; // @[dma_ctrl.scala 122:462]
|
|
wire _T_981 = 4'h8 == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_982 = io_iccm_dma_rvalid & _T_981; // @[dma_ctrl.scala 122:455]
|
|
wire _T_983 = _T_980 | _T_982; // @[dma_ctrl.scala 122:433]
|
|
wire _T_991 = _T_827 & _T_91; // @[dma_ctrl.scala 122:229]
|
|
wire _T_993 = 7'h9 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_994 = _T_830 & _T_993; // @[dma_ctrl.scala 122:302]
|
|
wire _T_995 = _T_991 | _T_994; // @[dma_ctrl.scala 122:257]
|
|
wire _T_996 = 4'h9 == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_997 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_996; // @[dma_ctrl.scala 122:373]
|
|
wire _T_998 = _T_995 | _T_997; // @[dma_ctrl.scala 122:330]
|
|
wire _T_999 = 4'h9 == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1000 = io_iccm_dma_rvalid & _T_999; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1001 = _T_998 | _T_1000; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1009 = _T_827 & _T_99; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1011 = 7'ha == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1012 = _T_830 & _T_1011; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1013 = _T_1009 | _T_1012; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1014 = 4'ha == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1015 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1014; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1016 = _T_1013 | _T_1015; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1017 = 4'ha == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1018 = io_iccm_dma_rvalid & _T_1017; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1019 = _T_1016 | _T_1018; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1027 = _T_827 & _T_107; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1029 = 7'hb == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1030 = _T_830 & _T_1029; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1031 = _T_1027 | _T_1030; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1032 = 4'hb == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1033 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1032; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1034 = _T_1031 | _T_1033; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1035 = 4'hb == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1036 = io_iccm_dma_rvalid & _T_1035; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1037 = _T_1034 | _T_1036; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1045 = _T_827 & _T_115; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1047 = 7'hc == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1048 = _T_830 & _T_1047; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1049 = _T_1045 | _T_1048; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1050 = 4'hc == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1051 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1050; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1052 = _T_1049 | _T_1051; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1053 = 4'hc == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1054 = io_iccm_dma_rvalid & _T_1053; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1055 = _T_1052 | _T_1054; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1063 = _T_827 & _T_123; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1065 = 7'hd == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1066 = _T_830 & _T_1065; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1067 = _T_1063 | _T_1066; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1068 = 4'hd == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1069 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1068; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1070 = _T_1067 | _T_1069; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1071 = 4'hd == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1072 = io_iccm_dma_rvalid & _T_1071; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1073 = _T_1070 | _T_1072; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1081 = _T_827 & _T_131; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1083 = 7'he == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1084 = _T_830 & _T_1083; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1085 = _T_1081 | _T_1084; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1086 = 4'he == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1087 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1086; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1088 = _T_1085 | _T_1087; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1089 = 4'he == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1090 = io_iccm_dma_rvalid & _T_1089; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1091 = _T_1088 | _T_1090; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1099 = _T_827 & _T_139; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1101 = 7'hf == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1102 = _T_830 & _T_1101; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1103 = _T_1099 | _T_1102; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1104 = 4'hf == _GEN_1731; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1105 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1104; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1106 = _T_1103 | _T_1105; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1107 = 4'hf == _GEN_1732; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1108 = io_iccm_dma_rvalid & _T_1107; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1109 = _T_1106 | _T_1108; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1117 = _T_827 & _T_147; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1119 = 7'h10 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1120 = _T_830 & _T_1119; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1121 = _T_1117 | _T_1120; // @[dma_ctrl.scala 122:257]
|
|
wire [4:0] _GEN_1747 = {{2'd0}, io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag}; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1122 = 5'h10 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1123 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1122; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1124 = _T_1121 | _T_1123; // @[dma_ctrl.scala 122:330]
|
|
wire [4:0] _GEN_1748 = {{2'd0}, io_iccm_dma_rtag}; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1125 = 5'h10 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1126 = io_iccm_dma_rvalid & _T_1125; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1127 = _T_1124 | _T_1126; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1135 = _T_827 & _T_155; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1137 = 7'h11 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1138 = _T_830 & _T_1137; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1139 = _T_1135 | _T_1138; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1140 = 5'h11 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1141 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1140; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1142 = _T_1139 | _T_1141; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1143 = 5'h11 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1144 = io_iccm_dma_rvalid & _T_1143; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1145 = _T_1142 | _T_1144; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1153 = _T_827 & _T_163; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1155 = 7'h12 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1156 = _T_830 & _T_1155; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1157 = _T_1153 | _T_1156; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1158 = 5'h12 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1159 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1158; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1160 = _T_1157 | _T_1159; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1161 = 5'h12 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1162 = io_iccm_dma_rvalid & _T_1161; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1163 = _T_1160 | _T_1162; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1171 = _T_827 & _T_171; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1173 = 7'h13 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1174 = _T_830 & _T_1173; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1175 = _T_1171 | _T_1174; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1176 = 5'h13 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1177 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1176; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1178 = _T_1175 | _T_1177; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1179 = 5'h13 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1180 = io_iccm_dma_rvalid & _T_1179; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1181 = _T_1178 | _T_1180; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1189 = _T_827 & _T_179; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1191 = 7'h14 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1192 = _T_830 & _T_1191; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1193 = _T_1189 | _T_1192; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1194 = 5'h14 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1195 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1194; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1196 = _T_1193 | _T_1195; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1197 = 5'h14 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1198 = io_iccm_dma_rvalid & _T_1197; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1199 = _T_1196 | _T_1198; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1207 = _T_827 & _T_187; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1209 = 7'h15 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1210 = _T_830 & _T_1209; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1211 = _T_1207 | _T_1210; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1212 = 5'h15 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1213 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1212; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1214 = _T_1211 | _T_1213; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1215 = 5'h15 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1216 = io_iccm_dma_rvalid & _T_1215; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1217 = _T_1214 | _T_1216; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1225 = _T_827 & _T_195; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1227 = 7'h16 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1228 = _T_830 & _T_1227; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1229 = _T_1225 | _T_1228; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1230 = 5'h16 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1231 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1230; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1232 = _T_1229 | _T_1231; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1233 = 5'h16 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1234 = io_iccm_dma_rvalid & _T_1233; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1235 = _T_1232 | _T_1234; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1243 = _T_827 & _T_203; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1245 = 7'h17 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1246 = _T_830 & _T_1245; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1247 = _T_1243 | _T_1246; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1248 = 5'h17 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1249 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1248; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1250 = _T_1247 | _T_1249; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1251 = 5'h17 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1252 = io_iccm_dma_rvalid & _T_1251; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1253 = _T_1250 | _T_1252; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1261 = _T_827 & _T_211; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1263 = 7'h18 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1264 = _T_830 & _T_1263; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1265 = _T_1261 | _T_1264; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1266 = 5'h18 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1267 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1266; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1268 = _T_1265 | _T_1267; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1269 = 5'h18 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1270 = io_iccm_dma_rvalid & _T_1269; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1271 = _T_1268 | _T_1270; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1279 = _T_827 & _T_219; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1281 = 7'h19 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1282 = _T_830 & _T_1281; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1283 = _T_1279 | _T_1282; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1284 = 5'h19 == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1285 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1284; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1286 = _T_1283 | _T_1285; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1287 = 5'h19 == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1288 = io_iccm_dma_rvalid & _T_1287; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1289 = _T_1286 | _T_1288; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1297 = _T_827 & _T_227; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1299 = 7'h1a == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1300 = _T_830 & _T_1299; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1301 = _T_1297 | _T_1300; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1302 = 5'h1a == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1303 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1302; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1304 = _T_1301 | _T_1303; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1305 = 5'h1a == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1306 = io_iccm_dma_rvalid & _T_1305; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1307 = _T_1304 | _T_1306; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1315 = _T_827 & _T_235; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1317 = 7'h1b == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1318 = _T_830 & _T_1317; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1319 = _T_1315 | _T_1318; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1320 = 5'h1b == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1321 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1320; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1322 = _T_1319 | _T_1321; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1323 = 5'h1b == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1324 = io_iccm_dma_rvalid & _T_1323; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1325 = _T_1322 | _T_1324; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1333 = _T_827 & _T_243; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1335 = 7'h1c == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1336 = _T_830 & _T_1335; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1337 = _T_1333 | _T_1336; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1338 = 5'h1c == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1339 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1338; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1340 = _T_1337 | _T_1339; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1341 = 5'h1c == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1342 = io_iccm_dma_rvalid & _T_1341; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1343 = _T_1340 | _T_1342; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1351 = _T_827 & _T_251; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1353 = 7'h1d == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1354 = _T_830 & _T_1353; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1355 = _T_1351 | _T_1354; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1356 = 5'h1d == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1357 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1356; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1358 = _T_1355 | _T_1357; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1359 = 5'h1d == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1360 = io_iccm_dma_rvalid & _T_1359; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1361 = _T_1358 | _T_1360; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1369 = _T_827 & _T_259; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1371 = 7'h1e == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1372 = _T_830 & _T_1371; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1373 = _T_1369 | _T_1372; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1374 = 5'h1e == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1375 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1374; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1376 = _T_1373 | _T_1375; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1377 = 5'h1e == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1378 = io_iccm_dma_rvalid & _T_1377; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1379 = _T_1376 | _T_1378; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1387 = _T_827 & _T_267; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1389 = 7'h1f == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1390 = _T_830 & _T_1389; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1391 = _T_1387 | _T_1390; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1392 = 5'h1f == _GEN_1747; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1393 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1392; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1394 = _T_1391 | _T_1393; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1395 = 5'h1f == _GEN_1748; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1396 = io_iccm_dma_rvalid & _T_1395; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1397 = _T_1394 | _T_1396; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1405 = _T_827 & _T_275; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1407 = 7'h20 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1408 = _T_830 & _T_1407; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1409 = _T_1405 | _T_1408; // @[dma_ctrl.scala 122:257]
|
|
wire [5:0] _GEN_1779 = {{3'd0}, io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag}; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1410 = 6'h20 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1411 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1410; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1412 = _T_1409 | _T_1411; // @[dma_ctrl.scala 122:330]
|
|
wire [5:0] _GEN_1780 = {{3'd0}, io_iccm_dma_rtag}; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1413 = 6'h20 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1414 = io_iccm_dma_rvalid & _T_1413; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1415 = _T_1412 | _T_1414; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1423 = _T_827 & _T_283; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1425 = 7'h21 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1426 = _T_830 & _T_1425; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1427 = _T_1423 | _T_1426; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1428 = 6'h21 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1429 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1428; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1430 = _T_1427 | _T_1429; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1431 = 6'h21 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1432 = io_iccm_dma_rvalid & _T_1431; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1433 = _T_1430 | _T_1432; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1441 = _T_827 & _T_291; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1443 = 7'h22 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1444 = _T_830 & _T_1443; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1445 = _T_1441 | _T_1444; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1446 = 6'h22 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1447 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1446; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1448 = _T_1445 | _T_1447; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1449 = 6'h22 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1450 = io_iccm_dma_rvalid & _T_1449; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1451 = _T_1448 | _T_1450; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1459 = _T_827 & _T_299; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1461 = 7'h23 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1462 = _T_830 & _T_1461; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1463 = _T_1459 | _T_1462; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1464 = 6'h23 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1465 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1464; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1466 = _T_1463 | _T_1465; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1467 = 6'h23 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1468 = io_iccm_dma_rvalid & _T_1467; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1469 = _T_1466 | _T_1468; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1477 = _T_827 & _T_307; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1479 = 7'h24 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1480 = _T_830 & _T_1479; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1481 = _T_1477 | _T_1480; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1482 = 6'h24 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1483 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1482; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1484 = _T_1481 | _T_1483; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1485 = 6'h24 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1486 = io_iccm_dma_rvalid & _T_1485; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1487 = _T_1484 | _T_1486; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1495 = _T_827 & _T_315; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1497 = 7'h25 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1498 = _T_830 & _T_1497; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1499 = _T_1495 | _T_1498; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1500 = 6'h25 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1501 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1500; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1502 = _T_1499 | _T_1501; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1503 = 6'h25 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1504 = io_iccm_dma_rvalid & _T_1503; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1505 = _T_1502 | _T_1504; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1513 = _T_827 & _T_323; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1515 = 7'h26 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1516 = _T_830 & _T_1515; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1517 = _T_1513 | _T_1516; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1518 = 6'h26 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1519 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1518; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1520 = _T_1517 | _T_1519; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1521 = 6'h26 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1522 = io_iccm_dma_rvalid & _T_1521; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1523 = _T_1520 | _T_1522; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1531 = _T_827 & _T_331; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1533 = 7'h27 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1534 = _T_830 & _T_1533; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1535 = _T_1531 | _T_1534; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1536 = 6'h27 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1537 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1536; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1538 = _T_1535 | _T_1537; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1539 = 6'h27 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1540 = io_iccm_dma_rvalid & _T_1539; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1541 = _T_1538 | _T_1540; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1549 = _T_827 & _T_339; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1551 = 7'h28 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1552 = _T_830 & _T_1551; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1553 = _T_1549 | _T_1552; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1554 = 6'h28 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1555 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1554; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1556 = _T_1553 | _T_1555; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1557 = 6'h28 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1558 = io_iccm_dma_rvalid & _T_1557; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1559 = _T_1556 | _T_1558; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1567 = _T_827 & _T_347; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1569 = 7'h29 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1570 = _T_830 & _T_1569; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1571 = _T_1567 | _T_1570; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1572 = 6'h29 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1573 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1572; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1574 = _T_1571 | _T_1573; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1575 = 6'h29 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1576 = io_iccm_dma_rvalid & _T_1575; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1577 = _T_1574 | _T_1576; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1585 = _T_827 & _T_355; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1587 = 7'h2a == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1588 = _T_830 & _T_1587; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1589 = _T_1585 | _T_1588; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1590 = 6'h2a == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1591 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1590; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1592 = _T_1589 | _T_1591; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1593 = 6'h2a == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1594 = io_iccm_dma_rvalid & _T_1593; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1595 = _T_1592 | _T_1594; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1603 = _T_827 & _T_363; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1605 = 7'h2b == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1606 = _T_830 & _T_1605; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1607 = _T_1603 | _T_1606; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1608 = 6'h2b == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1609 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1608; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1610 = _T_1607 | _T_1609; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1611 = 6'h2b == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1612 = io_iccm_dma_rvalid & _T_1611; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1613 = _T_1610 | _T_1612; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1621 = _T_827 & _T_371; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1623 = 7'h2c == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1624 = _T_830 & _T_1623; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1625 = _T_1621 | _T_1624; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1626 = 6'h2c == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1627 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1626; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1628 = _T_1625 | _T_1627; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1629 = 6'h2c == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1630 = io_iccm_dma_rvalid & _T_1629; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1631 = _T_1628 | _T_1630; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1639 = _T_827 & _T_379; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1641 = 7'h2d == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1642 = _T_830 & _T_1641; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1643 = _T_1639 | _T_1642; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1644 = 6'h2d == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1645 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1644; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1646 = _T_1643 | _T_1645; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1647 = 6'h2d == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1648 = io_iccm_dma_rvalid & _T_1647; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1649 = _T_1646 | _T_1648; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1657 = _T_827 & _T_387; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1659 = 7'h2e == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1660 = _T_830 & _T_1659; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1661 = _T_1657 | _T_1660; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1662 = 6'h2e == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1663 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1662; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1664 = _T_1661 | _T_1663; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1665 = 6'h2e == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1666 = io_iccm_dma_rvalid & _T_1665; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1667 = _T_1664 | _T_1666; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1675 = _T_827 & _T_395; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1677 = 7'h2f == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1678 = _T_830 & _T_1677; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1679 = _T_1675 | _T_1678; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1680 = 6'h2f == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1681 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1680; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1682 = _T_1679 | _T_1681; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1683 = 6'h2f == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1684 = io_iccm_dma_rvalid & _T_1683; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1685 = _T_1682 | _T_1684; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1693 = _T_827 & _T_403; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1695 = 7'h30 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1696 = _T_830 & _T_1695; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1697 = _T_1693 | _T_1696; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1698 = 6'h30 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1699 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1698; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1700 = _T_1697 | _T_1699; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1701 = 6'h30 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1702 = io_iccm_dma_rvalid & _T_1701; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1703 = _T_1700 | _T_1702; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1711 = _T_827 & _T_411; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1713 = 7'h31 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1714 = _T_830 & _T_1713; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1715 = _T_1711 | _T_1714; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1716 = 6'h31 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1717 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1716; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1718 = _T_1715 | _T_1717; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1719 = 6'h31 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1720 = io_iccm_dma_rvalid & _T_1719; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1721 = _T_1718 | _T_1720; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1729 = _T_827 & _T_419; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1731 = 7'h32 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1732 = _T_830 & _T_1731; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1733 = _T_1729 | _T_1732; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1734 = 6'h32 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1735 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1734; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1736 = _T_1733 | _T_1735; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1737 = 6'h32 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1738 = io_iccm_dma_rvalid & _T_1737; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1739 = _T_1736 | _T_1738; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1747 = _T_827 & _T_427; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1749 = 7'h33 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1750 = _T_830 & _T_1749; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1751 = _T_1747 | _T_1750; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1752 = 6'h33 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1753 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1752; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1754 = _T_1751 | _T_1753; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1755 = 6'h33 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1756 = io_iccm_dma_rvalid & _T_1755; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1757 = _T_1754 | _T_1756; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1765 = _T_827 & _T_435; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1767 = 7'h34 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1768 = _T_830 & _T_1767; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1769 = _T_1765 | _T_1768; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1770 = 6'h34 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1771 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1770; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1772 = _T_1769 | _T_1771; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1773 = 6'h34 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1774 = io_iccm_dma_rvalid & _T_1773; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1775 = _T_1772 | _T_1774; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1783 = _T_827 & _T_443; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1785 = 7'h35 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1786 = _T_830 & _T_1785; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1787 = _T_1783 | _T_1786; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1788 = 6'h35 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1789 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1788; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1790 = _T_1787 | _T_1789; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1791 = 6'h35 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1792 = io_iccm_dma_rvalid & _T_1791; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1793 = _T_1790 | _T_1792; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1801 = _T_827 & _T_451; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1803 = 7'h36 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1804 = _T_830 & _T_1803; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1805 = _T_1801 | _T_1804; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1806 = 6'h36 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1807 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1806; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1808 = _T_1805 | _T_1807; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1809 = 6'h36 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1810 = io_iccm_dma_rvalid & _T_1809; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1811 = _T_1808 | _T_1810; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1819 = _T_827 & _T_459; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1821 = 7'h37 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1822 = _T_830 & _T_1821; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1823 = _T_1819 | _T_1822; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1824 = 6'h37 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1825 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1824; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1826 = _T_1823 | _T_1825; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1827 = 6'h37 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1828 = io_iccm_dma_rvalid & _T_1827; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1829 = _T_1826 | _T_1828; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1837 = _T_827 & _T_467; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1839 = 7'h38 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1840 = _T_830 & _T_1839; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1841 = _T_1837 | _T_1840; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1842 = 6'h38 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1843 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1842; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1844 = _T_1841 | _T_1843; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1845 = 6'h38 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1846 = io_iccm_dma_rvalid & _T_1845; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1847 = _T_1844 | _T_1846; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1855 = _T_827 & _T_475; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1857 = 7'h39 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1858 = _T_830 & _T_1857; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1859 = _T_1855 | _T_1858; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1860 = 6'h39 == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1861 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1860; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1862 = _T_1859 | _T_1861; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1863 = 6'h39 == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1864 = io_iccm_dma_rvalid & _T_1863; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1865 = _T_1862 | _T_1864; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1873 = _T_827 & _T_483; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1875 = 7'h3a == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1876 = _T_830 & _T_1875; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1877 = _T_1873 | _T_1876; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1878 = 6'h3a == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1879 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1878; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1880 = _T_1877 | _T_1879; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1881 = 6'h3a == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1882 = io_iccm_dma_rvalid & _T_1881; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1883 = _T_1880 | _T_1882; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1891 = _T_827 & _T_491; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1893 = 7'h3b == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1894 = _T_830 & _T_1893; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1895 = _T_1891 | _T_1894; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1896 = 6'h3b == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1897 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1896; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1898 = _T_1895 | _T_1897; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1899 = 6'h3b == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1900 = io_iccm_dma_rvalid & _T_1899; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1901 = _T_1898 | _T_1900; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1909 = _T_827 & _T_499; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1911 = 7'h3c == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1912 = _T_830 & _T_1911; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1913 = _T_1909 | _T_1912; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1914 = 6'h3c == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1915 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1914; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1916 = _T_1913 | _T_1915; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1917 = 6'h3c == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1918 = io_iccm_dma_rvalid & _T_1917; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1919 = _T_1916 | _T_1918; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1927 = _T_827 & _T_507; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1929 = 7'h3d == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1930 = _T_830 & _T_1929; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1931 = _T_1927 | _T_1930; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1932 = 6'h3d == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1933 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1932; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1934 = _T_1931 | _T_1933; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1935 = 6'h3d == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1936 = io_iccm_dma_rvalid & _T_1935; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1937 = _T_1934 | _T_1936; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1945 = _T_827 & _T_515; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1947 = 7'h3e == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1948 = _T_830 & _T_1947; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1949 = _T_1945 | _T_1948; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1950 = 6'h3e == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1951 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1950; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1952 = _T_1949 | _T_1951; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1953 = 6'h3e == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1954 = io_iccm_dma_rvalid & _T_1953; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1955 = _T_1952 | _T_1954; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1963 = _T_827 & _T_523; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1965 = 7'h3f == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1966 = _T_830 & _T_1965; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1967 = _T_1963 | _T_1966; // @[dma_ctrl.scala 122:257]
|
|
wire _T_1968 = 6'h3f == _GEN_1779; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1969 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1968; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1970 = _T_1967 | _T_1969; // @[dma_ctrl.scala 122:330]
|
|
wire _T_1971 = 6'h3f == _GEN_1780; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1972 = io_iccm_dma_rvalid & _T_1971; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1973 = _T_1970 | _T_1972; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1981 = _T_827 & _T_531; // @[dma_ctrl.scala 122:229]
|
|
wire _T_1983 = 7'h40 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_1984 = _T_830 & _T_1983; // @[dma_ctrl.scala 122:302]
|
|
wire _T_1985 = _T_1981 | _T_1984; // @[dma_ctrl.scala 122:257]
|
|
wire [6:0] _GEN_1843 = {{4'd0}, io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag}; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1986 = 7'h40 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_1987 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_1986; // @[dma_ctrl.scala 122:373]
|
|
wire _T_1988 = _T_1985 | _T_1987; // @[dma_ctrl.scala 122:330]
|
|
wire [6:0] _GEN_1844 = {{4'd0}, io_iccm_dma_rtag}; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1989 = 7'h40 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_1990 = io_iccm_dma_rvalid & _T_1989; // @[dma_ctrl.scala 122:455]
|
|
wire _T_1991 = _T_1988 | _T_1990; // @[dma_ctrl.scala 122:433]
|
|
wire _T_1999 = _T_827 & _T_539; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2001 = 7'h41 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2002 = _T_830 & _T_2001; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2003 = _T_1999 | _T_2002; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2004 = 7'h41 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2005 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2004; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2006 = _T_2003 | _T_2005; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2007 = 7'h41 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2008 = io_iccm_dma_rvalid & _T_2007; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2009 = _T_2006 | _T_2008; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2017 = _T_827 & _T_547; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2019 = 7'h42 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2020 = _T_830 & _T_2019; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2021 = _T_2017 | _T_2020; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2022 = 7'h42 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2023 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2022; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2024 = _T_2021 | _T_2023; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2025 = 7'h42 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2026 = io_iccm_dma_rvalid & _T_2025; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2027 = _T_2024 | _T_2026; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2035 = _T_827 & _T_555; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2037 = 7'h43 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2038 = _T_830 & _T_2037; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2039 = _T_2035 | _T_2038; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2040 = 7'h43 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2041 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2040; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2042 = _T_2039 | _T_2041; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2043 = 7'h43 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2044 = io_iccm_dma_rvalid & _T_2043; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2045 = _T_2042 | _T_2044; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2053 = _T_827 & _T_563; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2055 = 7'h44 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2056 = _T_830 & _T_2055; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2057 = _T_2053 | _T_2056; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2058 = 7'h44 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2059 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2058; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2060 = _T_2057 | _T_2059; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2061 = 7'h44 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2062 = io_iccm_dma_rvalid & _T_2061; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2063 = _T_2060 | _T_2062; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2071 = _T_827 & _T_571; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2073 = 7'h45 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2074 = _T_830 & _T_2073; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2075 = _T_2071 | _T_2074; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2076 = 7'h45 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2077 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2076; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2078 = _T_2075 | _T_2077; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2079 = 7'h45 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2080 = io_iccm_dma_rvalid & _T_2079; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2081 = _T_2078 | _T_2080; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2089 = _T_827 & _T_579; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2091 = 7'h46 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2092 = _T_830 & _T_2091; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2093 = _T_2089 | _T_2092; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2094 = 7'h46 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2095 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2094; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2096 = _T_2093 | _T_2095; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2097 = 7'h46 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2098 = io_iccm_dma_rvalid & _T_2097; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2099 = _T_2096 | _T_2098; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2107 = _T_827 & _T_587; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2109 = 7'h47 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2110 = _T_830 & _T_2109; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2111 = _T_2107 | _T_2110; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2112 = 7'h47 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2113 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2112; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2114 = _T_2111 | _T_2113; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2115 = 7'h47 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2116 = io_iccm_dma_rvalid & _T_2115; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2117 = _T_2114 | _T_2116; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2125 = _T_827 & _T_595; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2127 = 7'h48 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2128 = _T_830 & _T_2127; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2129 = _T_2125 | _T_2128; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2130 = 7'h48 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2131 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2130; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2132 = _T_2129 | _T_2131; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2133 = 7'h48 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2134 = io_iccm_dma_rvalid & _T_2133; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2135 = _T_2132 | _T_2134; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2143 = _T_827 & _T_603; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2145 = 7'h49 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2146 = _T_830 & _T_2145; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2147 = _T_2143 | _T_2146; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2148 = 7'h49 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2149 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2148; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2150 = _T_2147 | _T_2149; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2151 = 7'h49 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2152 = io_iccm_dma_rvalid & _T_2151; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2153 = _T_2150 | _T_2152; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2161 = _T_827 & _T_611; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2163 = 7'h4a == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2164 = _T_830 & _T_2163; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2165 = _T_2161 | _T_2164; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2166 = 7'h4a == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2167 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2166; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2168 = _T_2165 | _T_2167; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2169 = 7'h4a == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2170 = io_iccm_dma_rvalid & _T_2169; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2171 = _T_2168 | _T_2170; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2179 = _T_827 & _T_619; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2181 = 7'h4b == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2182 = _T_830 & _T_2181; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2183 = _T_2179 | _T_2182; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2184 = 7'h4b == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2185 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2184; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2186 = _T_2183 | _T_2185; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2187 = 7'h4b == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2188 = io_iccm_dma_rvalid & _T_2187; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2189 = _T_2186 | _T_2188; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2197 = _T_827 & _T_627; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2199 = 7'h4c == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2200 = _T_830 & _T_2199; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2201 = _T_2197 | _T_2200; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2202 = 7'h4c == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2203 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2202; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2204 = _T_2201 | _T_2203; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2205 = 7'h4c == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2206 = io_iccm_dma_rvalid & _T_2205; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2207 = _T_2204 | _T_2206; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2215 = _T_827 & _T_635; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2217 = 7'h4d == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2218 = _T_830 & _T_2217; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2219 = _T_2215 | _T_2218; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2220 = 7'h4d == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2221 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2220; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2222 = _T_2219 | _T_2221; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2223 = 7'h4d == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2224 = io_iccm_dma_rvalid & _T_2223; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2225 = _T_2222 | _T_2224; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2233 = _T_827 & _T_643; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2235 = 7'h4e == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2236 = _T_830 & _T_2235; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2237 = _T_2233 | _T_2236; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2238 = 7'h4e == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2239 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2238; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2240 = _T_2237 | _T_2239; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2241 = 7'h4e == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2242 = io_iccm_dma_rvalid & _T_2241; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2243 = _T_2240 | _T_2242; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2251 = _T_827 & _T_651; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2253 = 7'h4f == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2254 = _T_830 & _T_2253; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2255 = _T_2251 | _T_2254; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2256 = 7'h4f == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2257 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2256; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2258 = _T_2255 | _T_2257; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2259 = 7'h4f == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2260 = io_iccm_dma_rvalid & _T_2259; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2261 = _T_2258 | _T_2260; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2269 = _T_827 & _T_659; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2271 = 7'h50 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2272 = _T_830 & _T_2271; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2273 = _T_2269 | _T_2272; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2274 = 7'h50 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2275 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2274; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2276 = _T_2273 | _T_2275; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2277 = 7'h50 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2278 = io_iccm_dma_rvalid & _T_2277; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2279 = _T_2276 | _T_2278; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2287 = _T_827 & _T_667; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2289 = 7'h51 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2290 = _T_830 & _T_2289; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2291 = _T_2287 | _T_2290; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2292 = 7'h51 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2293 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2292; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2294 = _T_2291 | _T_2293; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2295 = 7'h51 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2296 = io_iccm_dma_rvalid & _T_2295; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2297 = _T_2294 | _T_2296; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2305 = _T_827 & _T_675; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2307 = 7'h52 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2308 = _T_830 & _T_2307; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2309 = _T_2305 | _T_2308; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2310 = 7'h52 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2311 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2310; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2312 = _T_2309 | _T_2311; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2313 = 7'h52 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2314 = io_iccm_dma_rvalid & _T_2313; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2315 = _T_2312 | _T_2314; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2323 = _T_827 & _T_683; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2325 = 7'h53 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2326 = _T_830 & _T_2325; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2327 = _T_2323 | _T_2326; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2328 = 7'h53 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2329 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2328; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2330 = _T_2327 | _T_2329; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2331 = 7'h53 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2332 = io_iccm_dma_rvalid & _T_2331; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2333 = _T_2330 | _T_2332; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2341 = _T_827 & _T_691; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2343 = 7'h54 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2344 = _T_830 & _T_2343; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2345 = _T_2341 | _T_2344; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2346 = 7'h54 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2347 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2346; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2348 = _T_2345 | _T_2347; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2349 = 7'h54 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2350 = io_iccm_dma_rvalid & _T_2349; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2351 = _T_2348 | _T_2350; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2359 = _T_827 & _T_699; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2361 = 7'h55 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2362 = _T_830 & _T_2361; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2363 = _T_2359 | _T_2362; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2364 = 7'h55 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2365 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2364; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2366 = _T_2363 | _T_2365; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2367 = 7'h55 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2368 = io_iccm_dma_rvalid & _T_2367; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2369 = _T_2366 | _T_2368; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2377 = _T_827 & _T_707; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2379 = 7'h56 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2380 = _T_830 & _T_2379; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2381 = _T_2377 | _T_2380; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2382 = 7'h56 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2383 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2382; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2384 = _T_2381 | _T_2383; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2385 = 7'h56 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2386 = io_iccm_dma_rvalid & _T_2385; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2387 = _T_2384 | _T_2386; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2395 = _T_827 & _T_715; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2397 = 7'h57 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2398 = _T_830 & _T_2397; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2399 = _T_2395 | _T_2398; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2400 = 7'h57 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2401 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2400; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2402 = _T_2399 | _T_2401; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2403 = 7'h57 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2404 = io_iccm_dma_rvalid & _T_2403; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2405 = _T_2402 | _T_2404; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2413 = _T_827 & _T_723; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2415 = 7'h58 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2416 = _T_830 & _T_2415; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2417 = _T_2413 | _T_2416; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2418 = 7'h58 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2419 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2418; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2420 = _T_2417 | _T_2419; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2421 = 7'h58 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2422 = io_iccm_dma_rvalid & _T_2421; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2423 = _T_2420 | _T_2422; // @[dma_ctrl.scala 122:433]
|
|
wire _T_2431 = _T_827 & _T_731; // @[dma_ctrl.scala 122:229]
|
|
wire _T_2433 = 7'h59 == RdPtr; // @[dma_ctrl.scala 122:309]
|
|
wire _T_2434 = _T_830 & _T_2433; // @[dma_ctrl.scala 122:302]
|
|
wire _T_2435 = _T_2431 | _T_2434; // @[dma_ctrl.scala 122:257]
|
|
wire _T_2436 = 7'h59 == _GEN_1843; // @[dma_ctrl.scala 122:380]
|
|
wire _T_2437 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_2436; // @[dma_ctrl.scala 122:373]
|
|
wire _T_2438 = _T_2435 | _T_2437; // @[dma_ctrl.scala 122:330]
|
|
wire _T_2439 = 7'h59 == _GEN_1844; // @[dma_ctrl.scala 122:462]
|
|
wire _T_2440 = io_iccm_dma_rvalid & _T_2439; // @[dma_ctrl.scala 122:455]
|
|
wire _T_2441 = _T_2438 | _T_2440; // @[dma_ctrl.scala 122:433]
|
|
wire [9:0] _T_2450 = {_T_2441,_T_2423,_T_2405,_T_2387,_T_2369,_T_2351,_T_2333,_T_2315,_T_2297,_T_2279}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_2459 = {_T_2450,_T_2261,_T_2243,_T_2225,_T_2207,_T_2189,_T_2171,_T_2153,_T_2135,_T_2117}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_2468 = {_T_2459,_T_2099,_T_2081,_T_2063,_T_2045,_T_2027,_T_2009,_T_1991,_T_1973,_T_1955}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_2477 = {_T_2468,_T_1937,_T_1919,_T_1901,_T_1883,_T_1865,_T_1847,_T_1829,_T_1811,_T_1793}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_2486 = {_T_2477,_T_1775,_T_1757,_T_1739,_T_1721,_T_1703,_T_1685,_T_1667,_T_1649,_T_1631}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_2495 = {_T_2486,_T_1613,_T_1595,_T_1577,_T_1559,_T_1541,_T_1523,_T_1505,_T_1487,_T_1469}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_2504 = {_T_2495,_T_1451,_T_1433,_T_1415,_T_1397,_T_1379,_T_1361,_T_1343,_T_1325,_T_1307}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_2513 = {_T_2504,_T_1289,_T_1271,_T_1253,_T_1235,_T_1217,_T_1199,_T_1181,_T_1163,_T_1145}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_2522 = {_T_2513,_T_1127,_T_1109,_T_1091,_T_1073,_T_1055,_T_1037,_T_1019,_T_1001,_T_983}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_data_en = {_T_2522,_T_965,_T_947,_T_929,_T_911,_T_893,_T_875,_T_857,_T_839}; // @[Cat.scala 29:58]
|
|
wire _T_2531 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req | io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[dma_ctrl.scala 124:95]
|
|
wire _T_2532 = ~io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 124:136]
|
|
wire _T_2533 = _T_2531 & _T_2532; // @[dma_ctrl.scala 124:134]
|
|
wire _T_2535 = _T_2533 & _T_831; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2540 = _T_2533 & _T_849; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2545 = _T_2533 & _T_867; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2550 = _T_2533 & _T_885; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2555 = _T_2533 & _T_903; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2560 = _T_2533 & _T_921; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2565 = _T_2533 & _T_939; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2570 = _T_2533 & _T_957; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2575 = _T_2533 & _T_975; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2580 = _T_2533 & _T_993; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2585 = _T_2533 & _T_1011; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2590 = _T_2533 & _T_1029; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2595 = _T_2533 & _T_1047; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2600 = _T_2533 & _T_1065; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2605 = _T_2533 & _T_1083; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2610 = _T_2533 & _T_1101; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2615 = _T_2533 & _T_1119; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2620 = _T_2533 & _T_1137; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2625 = _T_2533 & _T_1155; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2630 = _T_2533 & _T_1173; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2635 = _T_2533 & _T_1191; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2640 = _T_2533 & _T_1209; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2645 = _T_2533 & _T_1227; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2650 = _T_2533 & _T_1245; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2655 = _T_2533 & _T_1263; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2660 = _T_2533 & _T_1281; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2665 = _T_2533 & _T_1299; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2670 = _T_2533 & _T_1317; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2675 = _T_2533 & _T_1335; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2680 = _T_2533 & _T_1353; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2685 = _T_2533 & _T_1371; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2690 = _T_2533 & _T_1389; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2695 = _T_2533 & _T_1407; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2700 = _T_2533 & _T_1425; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2705 = _T_2533 & _T_1443; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2710 = _T_2533 & _T_1461; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2715 = _T_2533 & _T_1479; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2720 = _T_2533 & _T_1497; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2725 = _T_2533 & _T_1515; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2730 = _T_2533 & _T_1533; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2735 = _T_2533 & _T_1551; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2740 = _T_2533 & _T_1569; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2745 = _T_2533 & _T_1587; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2750 = _T_2533 & _T_1605; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2755 = _T_2533 & _T_1623; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2760 = _T_2533 & _T_1641; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2765 = _T_2533 & _T_1659; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2770 = _T_2533 & _T_1677; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2775 = _T_2533 & _T_1695; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2780 = _T_2533 & _T_1713; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2785 = _T_2533 & _T_1731; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2790 = _T_2533 & _T_1749; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2795 = _T_2533 & _T_1767; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2800 = _T_2533 & _T_1785; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2805 = _T_2533 & _T_1803; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2810 = _T_2533 & _T_1821; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2815 = _T_2533 & _T_1839; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2820 = _T_2533 & _T_1857; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2825 = _T_2533 & _T_1875; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2830 = _T_2533 & _T_1893; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2835 = _T_2533 & _T_1911; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2840 = _T_2533 & _T_1929; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2845 = _T_2533 & _T_1947; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2850 = _T_2533 & _T_1965; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2855 = _T_2533 & _T_1983; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2860 = _T_2533 & _T_2001; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2865 = _T_2533 & _T_2019; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2870 = _T_2533 & _T_2037; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2875 = _T_2533 & _T_2055; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2880 = _T_2533 & _T_2073; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2885 = _T_2533 & _T_2091; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2890 = _T_2533 & _T_2109; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2895 = _T_2533 & _T_2127; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2900 = _T_2533 & _T_2145; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2905 = _T_2533 & _T_2163; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2910 = _T_2533 & _T_2181; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2915 = _T_2533 & _T_2199; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2920 = _T_2533 & _T_2217; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2925 = _T_2533 & _T_2235; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2930 = _T_2533 & _T_2253; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2935 = _T_2533 & _T_2271; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2940 = _T_2533 & _T_2289; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2945 = _T_2533 & _T_2307; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2950 = _T_2533 & _T_2325; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2955 = _T_2533 & _T_2343; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2960 = _T_2533 & _T_2361; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2965 = _T_2533 & _T_2379; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2970 = _T_2533 & _T_2397; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2975 = _T_2533 & _T_2415; // @[dma_ctrl.scala 124:174]
|
|
wire _T_2980 = _T_2533 & _T_2433; // @[dma_ctrl.scala 124:174]
|
|
wire [9:0] _T_2989 = {_T_2980,_T_2975,_T_2970,_T_2965,_T_2960,_T_2955,_T_2950,_T_2945,_T_2940,_T_2935}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_2998 = {_T_2989,_T_2930,_T_2925,_T_2920,_T_2915,_T_2910,_T_2905,_T_2900,_T_2895,_T_2890}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_3007 = {_T_2998,_T_2885,_T_2880,_T_2875,_T_2870,_T_2865,_T_2860,_T_2855,_T_2850,_T_2845}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_3016 = {_T_3007,_T_2840,_T_2835,_T_2830,_T_2825,_T_2820,_T_2815,_T_2810,_T_2805,_T_2800}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_3025 = {_T_3016,_T_2795,_T_2790,_T_2785,_T_2780,_T_2775,_T_2770,_T_2765,_T_2760,_T_2755}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_3034 = {_T_3025,_T_2750,_T_2745,_T_2740,_T_2735,_T_2730,_T_2725,_T_2720,_T_2715,_T_2710}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_3043 = {_T_3034,_T_2705,_T_2700,_T_2695,_T_2690,_T_2685,_T_2680,_T_2675,_T_2670,_T_2665}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_3052 = {_T_3043,_T_2660,_T_2655,_T_2650,_T_2645,_T_2640,_T_2635,_T_2630,_T_2625,_T_2620}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_3061 = {_T_3052,_T_2615,_T_2610,_T_2605,_T_2600,_T_2595,_T_2590,_T_2585,_T_2580,_T_2575}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_pend_en = {_T_3061,_T_2570,_T_2565,_T_2560,_T_2555,_T_2550,_T_2545,_T_2540,_T_2535}; // @[Cat.scala 29:58]
|
|
wire _T_17110 = _T_16943 & _T_16944[0]; // @[dma_ctrl.scala 236:62]
|
|
wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 381:39]
|
|
wire _T_17112 = _T_16948 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 237:53]
|
|
wire _T_17113 = ~_T_17112; // @[dma_ctrl.scala 237:7]
|
|
wire _T_17114 = dma_mem_addr_in_iccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 238:30]
|
|
wire _T_17116 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 238:76]
|
|
wire _T_17117 = _T_17114 & _T_17116; // @[dma_ctrl.scala 238:53]
|
|
wire _T_17118 = _T_17113 | _T_17117; // @[dma_ctrl.scala 237:77]
|
|
wire dma_dbg_cmd_error = _T_17110 & _T_17118; // @[dma_ctrl.scala 236:80]
|
|
wire _T_3073 = _T_830 | dma_dbg_cmd_error; // @[dma_ctrl.scala 126:114]
|
|
wire _T_3075 = _T_3073 & _T_831; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3076 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 126:198]
|
|
wire _T_3078 = _T_3076 & _T_834; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3079 = _T_3075 | _T_3078; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3080 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[dma_ctrl.scala 126:318]
|
|
wire _T_3082 = _T_3080 & _T_837; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3083 = _T_3079 | _T_3082; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3089 = _T_3073 & _T_849; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3092 = _T_3076 & _T_852; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3093 = _T_3089 | _T_3092; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3096 = _T_3080 & _T_855; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3097 = _T_3093 | _T_3096; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3103 = _T_3073 & _T_867; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3106 = _T_3076 & _T_870; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3107 = _T_3103 | _T_3106; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3110 = _T_3080 & _T_873; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3111 = _T_3107 | _T_3110; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3117 = _T_3073 & _T_885; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3120 = _T_3076 & _T_888; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3121 = _T_3117 | _T_3120; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3124 = _T_3080 & _T_891; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3125 = _T_3121 | _T_3124; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3131 = _T_3073 & _T_903; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3134 = _T_3076 & _T_906; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3135 = _T_3131 | _T_3134; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3138 = _T_3080 & _T_909; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3139 = _T_3135 | _T_3138; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3145 = _T_3073 & _T_921; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3148 = _T_3076 & _T_924; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3149 = _T_3145 | _T_3148; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3152 = _T_3080 & _T_927; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3153 = _T_3149 | _T_3152; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3159 = _T_3073 & _T_939; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3162 = _T_3076 & _T_942; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3163 = _T_3159 | _T_3162; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3166 = _T_3080 & _T_945; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3167 = _T_3163 | _T_3166; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3173 = _T_3073 & _T_957; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3176 = _T_3076 & _T_960; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3177 = _T_3173 | _T_3176; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3180 = _T_3080 & _T_963; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3181 = _T_3177 | _T_3180; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3187 = _T_3073 & _T_975; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3190 = _T_3076 & _T_978; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3191 = _T_3187 | _T_3190; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3194 = _T_3080 & _T_981; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3195 = _T_3191 | _T_3194; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3201 = _T_3073 & _T_993; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3204 = _T_3076 & _T_996; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3205 = _T_3201 | _T_3204; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3208 = _T_3080 & _T_999; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3209 = _T_3205 | _T_3208; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3215 = _T_3073 & _T_1011; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3218 = _T_3076 & _T_1014; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3219 = _T_3215 | _T_3218; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3222 = _T_3080 & _T_1017; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3223 = _T_3219 | _T_3222; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3229 = _T_3073 & _T_1029; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3232 = _T_3076 & _T_1032; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3233 = _T_3229 | _T_3232; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3236 = _T_3080 & _T_1035; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3237 = _T_3233 | _T_3236; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3243 = _T_3073 & _T_1047; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3246 = _T_3076 & _T_1050; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3247 = _T_3243 | _T_3246; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3250 = _T_3080 & _T_1053; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3251 = _T_3247 | _T_3250; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3257 = _T_3073 & _T_1065; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3260 = _T_3076 & _T_1068; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3261 = _T_3257 | _T_3260; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3264 = _T_3080 & _T_1071; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3265 = _T_3261 | _T_3264; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3271 = _T_3073 & _T_1083; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3274 = _T_3076 & _T_1086; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3275 = _T_3271 | _T_3274; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3278 = _T_3080 & _T_1089; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3279 = _T_3275 | _T_3278; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3285 = _T_3073 & _T_1101; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3288 = _T_3076 & _T_1104; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3289 = _T_3285 | _T_3288; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3292 = _T_3080 & _T_1107; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3293 = _T_3289 | _T_3292; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3299 = _T_3073 & _T_1119; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3302 = _T_3076 & _T_1122; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3303 = _T_3299 | _T_3302; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3306 = _T_3080 & _T_1125; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3307 = _T_3303 | _T_3306; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3313 = _T_3073 & _T_1137; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3316 = _T_3076 & _T_1140; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3317 = _T_3313 | _T_3316; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3320 = _T_3080 & _T_1143; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3321 = _T_3317 | _T_3320; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3327 = _T_3073 & _T_1155; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3330 = _T_3076 & _T_1158; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3331 = _T_3327 | _T_3330; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3334 = _T_3080 & _T_1161; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3335 = _T_3331 | _T_3334; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3341 = _T_3073 & _T_1173; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3344 = _T_3076 & _T_1176; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3345 = _T_3341 | _T_3344; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3348 = _T_3080 & _T_1179; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3349 = _T_3345 | _T_3348; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3355 = _T_3073 & _T_1191; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3358 = _T_3076 & _T_1194; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3359 = _T_3355 | _T_3358; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3362 = _T_3080 & _T_1197; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3363 = _T_3359 | _T_3362; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3369 = _T_3073 & _T_1209; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3372 = _T_3076 & _T_1212; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3373 = _T_3369 | _T_3372; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3376 = _T_3080 & _T_1215; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3377 = _T_3373 | _T_3376; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3383 = _T_3073 & _T_1227; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3386 = _T_3076 & _T_1230; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3387 = _T_3383 | _T_3386; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3390 = _T_3080 & _T_1233; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3391 = _T_3387 | _T_3390; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3397 = _T_3073 & _T_1245; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3400 = _T_3076 & _T_1248; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3401 = _T_3397 | _T_3400; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3404 = _T_3080 & _T_1251; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3405 = _T_3401 | _T_3404; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3411 = _T_3073 & _T_1263; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3414 = _T_3076 & _T_1266; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3415 = _T_3411 | _T_3414; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3418 = _T_3080 & _T_1269; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3419 = _T_3415 | _T_3418; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3425 = _T_3073 & _T_1281; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3428 = _T_3076 & _T_1284; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3429 = _T_3425 | _T_3428; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3432 = _T_3080 & _T_1287; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3433 = _T_3429 | _T_3432; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3439 = _T_3073 & _T_1299; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3442 = _T_3076 & _T_1302; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3443 = _T_3439 | _T_3442; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3446 = _T_3080 & _T_1305; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3447 = _T_3443 | _T_3446; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3453 = _T_3073 & _T_1317; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3456 = _T_3076 & _T_1320; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3457 = _T_3453 | _T_3456; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3460 = _T_3080 & _T_1323; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3461 = _T_3457 | _T_3460; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3467 = _T_3073 & _T_1335; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3470 = _T_3076 & _T_1338; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3471 = _T_3467 | _T_3470; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3474 = _T_3080 & _T_1341; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3475 = _T_3471 | _T_3474; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3481 = _T_3073 & _T_1353; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3484 = _T_3076 & _T_1356; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3485 = _T_3481 | _T_3484; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3488 = _T_3080 & _T_1359; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3489 = _T_3485 | _T_3488; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3495 = _T_3073 & _T_1371; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3498 = _T_3076 & _T_1374; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3499 = _T_3495 | _T_3498; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3502 = _T_3080 & _T_1377; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3503 = _T_3499 | _T_3502; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3509 = _T_3073 & _T_1389; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3512 = _T_3076 & _T_1392; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3513 = _T_3509 | _T_3512; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3516 = _T_3080 & _T_1395; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3517 = _T_3513 | _T_3516; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3523 = _T_3073 & _T_1407; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3526 = _T_3076 & _T_1410; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3527 = _T_3523 | _T_3526; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3530 = _T_3080 & _T_1413; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3531 = _T_3527 | _T_3530; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3537 = _T_3073 & _T_1425; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3540 = _T_3076 & _T_1428; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3541 = _T_3537 | _T_3540; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3544 = _T_3080 & _T_1431; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3545 = _T_3541 | _T_3544; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3551 = _T_3073 & _T_1443; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3554 = _T_3076 & _T_1446; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3555 = _T_3551 | _T_3554; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3558 = _T_3080 & _T_1449; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3559 = _T_3555 | _T_3558; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3565 = _T_3073 & _T_1461; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3568 = _T_3076 & _T_1464; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3569 = _T_3565 | _T_3568; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3572 = _T_3080 & _T_1467; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3573 = _T_3569 | _T_3572; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3579 = _T_3073 & _T_1479; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3582 = _T_3076 & _T_1482; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3583 = _T_3579 | _T_3582; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3586 = _T_3080 & _T_1485; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3587 = _T_3583 | _T_3586; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3593 = _T_3073 & _T_1497; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3596 = _T_3076 & _T_1500; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3597 = _T_3593 | _T_3596; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3600 = _T_3080 & _T_1503; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3601 = _T_3597 | _T_3600; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3607 = _T_3073 & _T_1515; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3610 = _T_3076 & _T_1518; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3611 = _T_3607 | _T_3610; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3614 = _T_3080 & _T_1521; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3615 = _T_3611 | _T_3614; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3621 = _T_3073 & _T_1533; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3624 = _T_3076 & _T_1536; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3625 = _T_3621 | _T_3624; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3628 = _T_3080 & _T_1539; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3629 = _T_3625 | _T_3628; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3635 = _T_3073 & _T_1551; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3638 = _T_3076 & _T_1554; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3639 = _T_3635 | _T_3638; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3642 = _T_3080 & _T_1557; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3643 = _T_3639 | _T_3642; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3649 = _T_3073 & _T_1569; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3652 = _T_3076 & _T_1572; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3653 = _T_3649 | _T_3652; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3656 = _T_3080 & _T_1575; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3657 = _T_3653 | _T_3656; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3663 = _T_3073 & _T_1587; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3666 = _T_3076 & _T_1590; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3667 = _T_3663 | _T_3666; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3670 = _T_3080 & _T_1593; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3671 = _T_3667 | _T_3670; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3677 = _T_3073 & _T_1605; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3680 = _T_3076 & _T_1608; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3681 = _T_3677 | _T_3680; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3684 = _T_3080 & _T_1611; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3685 = _T_3681 | _T_3684; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3691 = _T_3073 & _T_1623; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3694 = _T_3076 & _T_1626; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3695 = _T_3691 | _T_3694; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3698 = _T_3080 & _T_1629; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3699 = _T_3695 | _T_3698; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3705 = _T_3073 & _T_1641; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3708 = _T_3076 & _T_1644; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3709 = _T_3705 | _T_3708; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3712 = _T_3080 & _T_1647; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3713 = _T_3709 | _T_3712; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3719 = _T_3073 & _T_1659; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3722 = _T_3076 & _T_1662; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3723 = _T_3719 | _T_3722; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3726 = _T_3080 & _T_1665; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3727 = _T_3723 | _T_3726; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3733 = _T_3073 & _T_1677; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3736 = _T_3076 & _T_1680; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3737 = _T_3733 | _T_3736; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3740 = _T_3080 & _T_1683; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3741 = _T_3737 | _T_3740; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3747 = _T_3073 & _T_1695; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3750 = _T_3076 & _T_1698; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3751 = _T_3747 | _T_3750; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3754 = _T_3080 & _T_1701; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3755 = _T_3751 | _T_3754; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3761 = _T_3073 & _T_1713; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3764 = _T_3076 & _T_1716; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3765 = _T_3761 | _T_3764; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3768 = _T_3080 & _T_1719; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3769 = _T_3765 | _T_3768; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3775 = _T_3073 & _T_1731; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3778 = _T_3076 & _T_1734; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3779 = _T_3775 | _T_3778; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3782 = _T_3080 & _T_1737; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3783 = _T_3779 | _T_3782; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3789 = _T_3073 & _T_1749; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3792 = _T_3076 & _T_1752; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3793 = _T_3789 | _T_3792; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3796 = _T_3080 & _T_1755; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3797 = _T_3793 | _T_3796; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3803 = _T_3073 & _T_1767; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3806 = _T_3076 & _T_1770; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3807 = _T_3803 | _T_3806; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3810 = _T_3080 & _T_1773; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3811 = _T_3807 | _T_3810; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3817 = _T_3073 & _T_1785; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3820 = _T_3076 & _T_1788; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3821 = _T_3817 | _T_3820; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3824 = _T_3080 & _T_1791; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3825 = _T_3821 | _T_3824; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3831 = _T_3073 & _T_1803; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3834 = _T_3076 & _T_1806; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3835 = _T_3831 | _T_3834; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3838 = _T_3080 & _T_1809; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3839 = _T_3835 | _T_3838; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3845 = _T_3073 & _T_1821; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3848 = _T_3076 & _T_1824; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3849 = _T_3845 | _T_3848; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3852 = _T_3080 & _T_1827; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3853 = _T_3849 | _T_3852; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3859 = _T_3073 & _T_1839; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3862 = _T_3076 & _T_1842; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3863 = _T_3859 | _T_3862; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3866 = _T_3080 & _T_1845; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3867 = _T_3863 | _T_3866; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3873 = _T_3073 & _T_1857; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3876 = _T_3076 & _T_1860; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3877 = _T_3873 | _T_3876; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3880 = _T_3080 & _T_1863; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3881 = _T_3877 | _T_3880; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3887 = _T_3073 & _T_1875; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3890 = _T_3076 & _T_1878; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3891 = _T_3887 | _T_3890; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3894 = _T_3080 & _T_1881; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3895 = _T_3891 | _T_3894; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3901 = _T_3073 & _T_1893; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3904 = _T_3076 & _T_1896; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3905 = _T_3901 | _T_3904; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3908 = _T_3080 & _T_1899; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3909 = _T_3905 | _T_3908; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3915 = _T_3073 & _T_1911; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3918 = _T_3076 & _T_1914; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3919 = _T_3915 | _T_3918; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3922 = _T_3080 & _T_1917; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3923 = _T_3919 | _T_3922; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3929 = _T_3073 & _T_1929; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3932 = _T_3076 & _T_1932; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3933 = _T_3929 | _T_3932; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3936 = _T_3080 & _T_1935; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3937 = _T_3933 | _T_3936; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3943 = _T_3073 & _T_1947; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3946 = _T_3076 & _T_1950; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3947 = _T_3943 | _T_3946; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3950 = _T_3080 & _T_1953; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3951 = _T_3947 | _T_3950; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3957 = _T_3073 & _T_1965; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3960 = _T_3076 & _T_1968; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3961 = _T_3957 | _T_3960; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3964 = _T_3080 & _T_1971; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3965 = _T_3961 | _T_3964; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3971 = _T_3073 & _T_1983; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3974 = _T_3076 & _T_1986; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3975 = _T_3971 | _T_3974; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3978 = _T_3080 & _T_1989; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3979 = _T_3975 | _T_3978; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3985 = _T_3073 & _T_2001; // @[dma_ctrl.scala 126:135]
|
|
wire _T_3988 = _T_3076 & _T_2004; // @[dma_ctrl.scala 126:244]
|
|
wire _T_3989 = _T_3985 | _T_3988; // @[dma_ctrl.scala 126:154]
|
|
wire _T_3992 = _T_3080 & _T_2007; // @[dma_ctrl.scala 126:343]
|
|
wire _T_3993 = _T_3989 | _T_3992; // @[dma_ctrl.scala 126:295]
|
|
wire _T_3999 = _T_3073 & _T_2019; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4002 = _T_3076 & _T_2022; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4003 = _T_3999 | _T_4002; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4006 = _T_3080 & _T_2025; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4007 = _T_4003 | _T_4006; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4013 = _T_3073 & _T_2037; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4016 = _T_3076 & _T_2040; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4017 = _T_4013 | _T_4016; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4020 = _T_3080 & _T_2043; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4021 = _T_4017 | _T_4020; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4027 = _T_3073 & _T_2055; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4030 = _T_3076 & _T_2058; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4031 = _T_4027 | _T_4030; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4034 = _T_3080 & _T_2061; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4035 = _T_4031 | _T_4034; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4041 = _T_3073 & _T_2073; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4044 = _T_3076 & _T_2076; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4045 = _T_4041 | _T_4044; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4048 = _T_3080 & _T_2079; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4049 = _T_4045 | _T_4048; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4055 = _T_3073 & _T_2091; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4058 = _T_3076 & _T_2094; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4059 = _T_4055 | _T_4058; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4062 = _T_3080 & _T_2097; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4063 = _T_4059 | _T_4062; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4069 = _T_3073 & _T_2109; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4072 = _T_3076 & _T_2112; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4073 = _T_4069 | _T_4072; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4076 = _T_3080 & _T_2115; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4077 = _T_4073 | _T_4076; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4083 = _T_3073 & _T_2127; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4086 = _T_3076 & _T_2130; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4087 = _T_4083 | _T_4086; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4090 = _T_3080 & _T_2133; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4091 = _T_4087 | _T_4090; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4097 = _T_3073 & _T_2145; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4100 = _T_3076 & _T_2148; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4101 = _T_4097 | _T_4100; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4104 = _T_3080 & _T_2151; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4105 = _T_4101 | _T_4104; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4111 = _T_3073 & _T_2163; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4114 = _T_3076 & _T_2166; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4115 = _T_4111 | _T_4114; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4118 = _T_3080 & _T_2169; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4119 = _T_4115 | _T_4118; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4125 = _T_3073 & _T_2181; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4128 = _T_3076 & _T_2184; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4129 = _T_4125 | _T_4128; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4132 = _T_3080 & _T_2187; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4133 = _T_4129 | _T_4132; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4139 = _T_3073 & _T_2199; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4142 = _T_3076 & _T_2202; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4143 = _T_4139 | _T_4142; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4146 = _T_3080 & _T_2205; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4147 = _T_4143 | _T_4146; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4153 = _T_3073 & _T_2217; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4156 = _T_3076 & _T_2220; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4157 = _T_4153 | _T_4156; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4160 = _T_3080 & _T_2223; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4161 = _T_4157 | _T_4160; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4167 = _T_3073 & _T_2235; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4170 = _T_3076 & _T_2238; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4171 = _T_4167 | _T_4170; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4174 = _T_3080 & _T_2241; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4175 = _T_4171 | _T_4174; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4181 = _T_3073 & _T_2253; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4184 = _T_3076 & _T_2256; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4185 = _T_4181 | _T_4184; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4188 = _T_3080 & _T_2259; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4189 = _T_4185 | _T_4188; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4195 = _T_3073 & _T_2271; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4198 = _T_3076 & _T_2274; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4199 = _T_4195 | _T_4198; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4202 = _T_3080 & _T_2277; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4203 = _T_4199 | _T_4202; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4209 = _T_3073 & _T_2289; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4212 = _T_3076 & _T_2292; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4213 = _T_4209 | _T_4212; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4216 = _T_3080 & _T_2295; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4217 = _T_4213 | _T_4216; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4223 = _T_3073 & _T_2307; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4226 = _T_3076 & _T_2310; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4227 = _T_4223 | _T_4226; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4230 = _T_3080 & _T_2313; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4231 = _T_4227 | _T_4230; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4237 = _T_3073 & _T_2325; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4240 = _T_3076 & _T_2328; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4241 = _T_4237 | _T_4240; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4244 = _T_3080 & _T_2331; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4245 = _T_4241 | _T_4244; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4251 = _T_3073 & _T_2343; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4254 = _T_3076 & _T_2346; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4255 = _T_4251 | _T_4254; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4258 = _T_3080 & _T_2349; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4259 = _T_4255 | _T_4258; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4265 = _T_3073 & _T_2361; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4268 = _T_3076 & _T_2364; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4269 = _T_4265 | _T_4268; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4272 = _T_3080 & _T_2367; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4273 = _T_4269 | _T_4272; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4279 = _T_3073 & _T_2379; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4282 = _T_3076 & _T_2382; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4283 = _T_4279 | _T_4282; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4286 = _T_3080 & _T_2385; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4287 = _T_4283 | _T_4286; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4293 = _T_3073 & _T_2397; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4296 = _T_3076 & _T_2400; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4297 = _T_4293 | _T_4296; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4300 = _T_3080 & _T_2403; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4301 = _T_4297 | _T_4300; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4307 = _T_3073 & _T_2415; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4310 = _T_3076 & _T_2418; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4311 = _T_4307 | _T_4310; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4314 = _T_3080 & _T_2421; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4315 = _T_4311 | _T_4314; // @[dma_ctrl.scala 126:295]
|
|
wire _T_4321 = _T_3073 & _T_2433; // @[dma_ctrl.scala 126:135]
|
|
wire _T_4324 = _T_3076 & _T_2436; // @[dma_ctrl.scala 126:244]
|
|
wire _T_4325 = _T_4321 | _T_4324; // @[dma_ctrl.scala 126:154]
|
|
wire _T_4328 = _T_3080 & _T_2439; // @[dma_ctrl.scala 126:343]
|
|
wire _T_4329 = _T_4325 | _T_4328; // @[dma_ctrl.scala 126:295]
|
|
wire [9:0] _T_4338 = {_T_4329,_T_4315,_T_4301,_T_4287,_T_4273,_T_4259,_T_4245,_T_4231,_T_4217,_T_4203}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_4347 = {_T_4338,_T_4189,_T_4175,_T_4161,_T_4147,_T_4133,_T_4119,_T_4105,_T_4091,_T_4077}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_4356 = {_T_4347,_T_4063,_T_4049,_T_4035,_T_4021,_T_4007,_T_3993,_T_3979,_T_3965,_T_3951}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_4365 = {_T_4356,_T_3937,_T_3923,_T_3909,_T_3895,_T_3881,_T_3867,_T_3853,_T_3839,_T_3825}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_4374 = {_T_4365,_T_3811,_T_3797,_T_3783,_T_3769,_T_3755,_T_3741,_T_3727,_T_3713,_T_3699}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_4383 = {_T_4374,_T_3685,_T_3671,_T_3657,_T_3643,_T_3629,_T_3615,_T_3601,_T_3587,_T_3573}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_4392 = {_T_4383,_T_3559,_T_3545,_T_3531,_T_3517,_T_3503,_T_3489,_T_3475,_T_3461,_T_3447}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_4401 = {_T_4392,_T_3433,_T_3419,_T_3405,_T_3391,_T_3377,_T_3363,_T_3349,_T_3335,_T_3321}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_4410 = {_T_4401,_T_3307,_T_3293,_T_3279,_T_3265,_T_3251,_T_3237,_T_3223,_T_3209,_T_3195}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_error_en = {_T_4410,_T_3181,_T_3167,_T_3153,_T_3139,_T_3125,_T_3111,_T_3097,_T_3083}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_7477 = {1'h0,io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_7480 = {1'h0,io_iccm_dma_ecc_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_7483 = {_T_3073,dma_alignment_error}; // @[Cat.scala 29:58]
|
|
wire [1:0] _T_7484 = _T_838 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_0 = _T_835 ? _T_7477 : _T_7484; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4420 = |fifo_error_in_0; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_0; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4423 = |fifo_error_0; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7495 = _T_856 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_1 = _T_853 ? _T_7477 : _T_7495; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4427 = |fifo_error_in_1; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_1; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4430 = |fifo_error_1; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7506 = _T_874 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_2 = _T_871 ? _T_7477 : _T_7506; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4434 = |fifo_error_in_2; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_2; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4437 = |fifo_error_2; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7517 = _T_892 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_3 = _T_889 ? _T_7477 : _T_7517; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4441 = |fifo_error_in_3; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_3; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4444 = |fifo_error_3; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7528 = _T_910 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_4 = _T_907 ? _T_7477 : _T_7528; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4448 = |fifo_error_in_4; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_4; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4451 = |fifo_error_4; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7539 = _T_928 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_5 = _T_925 ? _T_7477 : _T_7539; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4455 = |fifo_error_in_5; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_5; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4458 = |fifo_error_5; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7550 = _T_946 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_6 = _T_943 ? _T_7477 : _T_7550; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4462 = |fifo_error_in_6; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_6; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4465 = |fifo_error_6; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7561 = _T_964 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_7 = _T_961 ? _T_7477 : _T_7561; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4469 = |fifo_error_in_7; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_7; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4472 = |fifo_error_7; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7572 = _T_982 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_8 = _T_979 ? _T_7477 : _T_7572; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4476 = |fifo_error_in_8; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_8; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4479 = |fifo_error_8; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7583 = _T_1000 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_9 = _T_997 ? _T_7477 : _T_7583; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4483 = |fifo_error_in_9; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_9; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4486 = |fifo_error_9; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7594 = _T_1018 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_10 = _T_1015 ? _T_7477 : _T_7594; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4490 = |fifo_error_in_10; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_10; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4493 = |fifo_error_10; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7605 = _T_1036 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_11 = _T_1033 ? _T_7477 : _T_7605; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4497 = |fifo_error_in_11; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_11; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4500 = |fifo_error_11; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7616 = _T_1054 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_12 = _T_1051 ? _T_7477 : _T_7616; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4504 = |fifo_error_in_12; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_12; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4507 = |fifo_error_12; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7627 = _T_1072 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_13 = _T_1069 ? _T_7477 : _T_7627; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4511 = |fifo_error_in_13; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_13; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4514 = |fifo_error_13; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7638 = _T_1090 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_14 = _T_1087 ? _T_7477 : _T_7638; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4518 = |fifo_error_in_14; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_14; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4521 = |fifo_error_14; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7649 = _T_1108 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_15 = _T_1105 ? _T_7477 : _T_7649; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4525 = |fifo_error_in_15; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_15; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4528 = |fifo_error_15; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7660 = _T_1126 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_16 = _T_1123 ? _T_7477 : _T_7660; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4532 = |fifo_error_in_16; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_16; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4535 = |fifo_error_16; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7671 = _T_1144 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_17 = _T_1141 ? _T_7477 : _T_7671; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4539 = |fifo_error_in_17; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_17; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4542 = |fifo_error_17; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7682 = _T_1162 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_18 = _T_1159 ? _T_7477 : _T_7682; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4546 = |fifo_error_in_18; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_18; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4549 = |fifo_error_18; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7693 = _T_1180 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_19 = _T_1177 ? _T_7477 : _T_7693; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4553 = |fifo_error_in_19; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_19; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4556 = |fifo_error_19; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7704 = _T_1198 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_20 = _T_1195 ? _T_7477 : _T_7704; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4560 = |fifo_error_in_20; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_20; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4563 = |fifo_error_20; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7715 = _T_1216 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_21 = _T_1213 ? _T_7477 : _T_7715; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4567 = |fifo_error_in_21; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_21; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4570 = |fifo_error_21; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7726 = _T_1234 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_22 = _T_1231 ? _T_7477 : _T_7726; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4574 = |fifo_error_in_22; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_22; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4577 = |fifo_error_22; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7737 = _T_1252 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_23 = _T_1249 ? _T_7477 : _T_7737; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4581 = |fifo_error_in_23; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_23; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4584 = |fifo_error_23; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7748 = _T_1270 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_24 = _T_1267 ? _T_7477 : _T_7748; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4588 = |fifo_error_in_24; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_24; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4591 = |fifo_error_24; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7759 = _T_1288 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_25 = _T_1285 ? _T_7477 : _T_7759; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4595 = |fifo_error_in_25; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_25; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4598 = |fifo_error_25; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7770 = _T_1306 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_26 = _T_1303 ? _T_7477 : _T_7770; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4602 = |fifo_error_in_26; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_26; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4605 = |fifo_error_26; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7781 = _T_1324 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_27 = _T_1321 ? _T_7477 : _T_7781; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4609 = |fifo_error_in_27; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_27; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4612 = |fifo_error_27; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7792 = _T_1342 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_28 = _T_1339 ? _T_7477 : _T_7792; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4616 = |fifo_error_in_28; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_28; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4619 = |fifo_error_28; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7803 = _T_1360 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_29 = _T_1357 ? _T_7477 : _T_7803; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4623 = |fifo_error_in_29; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_29; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4626 = |fifo_error_29; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7814 = _T_1378 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_30 = _T_1375 ? _T_7477 : _T_7814; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4630 = |fifo_error_in_30; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_30; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4633 = |fifo_error_30; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7825 = _T_1396 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_31 = _T_1393 ? _T_7477 : _T_7825; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4637 = |fifo_error_in_31; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_31; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4640 = |fifo_error_31; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7836 = _T_1414 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_32 = _T_1411 ? _T_7477 : _T_7836; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4644 = |fifo_error_in_32; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_32; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4647 = |fifo_error_32; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7847 = _T_1432 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_33 = _T_1429 ? _T_7477 : _T_7847; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4651 = |fifo_error_in_33; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_33; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4654 = |fifo_error_33; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7858 = _T_1450 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_34 = _T_1447 ? _T_7477 : _T_7858; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4658 = |fifo_error_in_34; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_34; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4661 = |fifo_error_34; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7869 = _T_1468 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_35 = _T_1465 ? _T_7477 : _T_7869; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4665 = |fifo_error_in_35; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_35; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4668 = |fifo_error_35; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7880 = _T_1486 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_36 = _T_1483 ? _T_7477 : _T_7880; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4672 = |fifo_error_in_36; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_36; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4675 = |fifo_error_36; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7891 = _T_1504 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_37 = _T_1501 ? _T_7477 : _T_7891; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4679 = |fifo_error_in_37; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_37; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4682 = |fifo_error_37; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7902 = _T_1522 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_38 = _T_1519 ? _T_7477 : _T_7902; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4686 = |fifo_error_in_38; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_38; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4689 = |fifo_error_38; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7913 = _T_1540 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_39 = _T_1537 ? _T_7477 : _T_7913; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4693 = |fifo_error_in_39; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_39; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4696 = |fifo_error_39; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7924 = _T_1558 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_40 = _T_1555 ? _T_7477 : _T_7924; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4700 = |fifo_error_in_40; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_40; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4703 = |fifo_error_40; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7935 = _T_1576 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_41 = _T_1573 ? _T_7477 : _T_7935; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4707 = |fifo_error_in_41; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_41; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4710 = |fifo_error_41; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7946 = _T_1594 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_42 = _T_1591 ? _T_7477 : _T_7946; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4714 = |fifo_error_in_42; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_42; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4717 = |fifo_error_42; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7957 = _T_1612 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_43 = _T_1609 ? _T_7477 : _T_7957; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4721 = |fifo_error_in_43; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_43; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4724 = |fifo_error_43; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7968 = _T_1630 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_44 = _T_1627 ? _T_7477 : _T_7968; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4728 = |fifo_error_in_44; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_44; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4731 = |fifo_error_44; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7979 = _T_1648 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_45 = _T_1645 ? _T_7477 : _T_7979; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4735 = |fifo_error_in_45; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_45; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4738 = |fifo_error_45; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_7990 = _T_1666 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_46 = _T_1663 ? _T_7477 : _T_7990; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4742 = |fifo_error_in_46; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_46; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4745 = |fifo_error_46; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8001 = _T_1684 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_47 = _T_1681 ? _T_7477 : _T_8001; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4749 = |fifo_error_in_47; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_47; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4752 = |fifo_error_47; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8012 = _T_1702 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_48 = _T_1699 ? _T_7477 : _T_8012; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4756 = |fifo_error_in_48; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_48; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4759 = |fifo_error_48; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8023 = _T_1720 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_49 = _T_1717 ? _T_7477 : _T_8023; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4763 = |fifo_error_in_49; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_49; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4766 = |fifo_error_49; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8034 = _T_1738 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_50 = _T_1735 ? _T_7477 : _T_8034; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4770 = |fifo_error_in_50; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_50; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4773 = |fifo_error_50; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8045 = _T_1756 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_51 = _T_1753 ? _T_7477 : _T_8045; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4777 = |fifo_error_in_51; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_51; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4780 = |fifo_error_51; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8056 = _T_1774 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_52 = _T_1771 ? _T_7477 : _T_8056; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4784 = |fifo_error_in_52; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_52; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4787 = |fifo_error_52; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8067 = _T_1792 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_53 = _T_1789 ? _T_7477 : _T_8067; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4791 = |fifo_error_in_53; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_53; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4794 = |fifo_error_53; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8078 = _T_1810 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_54 = _T_1807 ? _T_7477 : _T_8078; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4798 = |fifo_error_in_54; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_54; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4801 = |fifo_error_54; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8089 = _T_1828 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_55 = _T_1825 ? _T_7477 : _T_8089; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4805 = |fifo_error_in_55; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_55; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4808 = |fifo_error_55; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8100 = _T_1846 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_56 = _T_1843 ? _T_7477 : _T_8100; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4812 = |fifo_error_in_56; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_56; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4815 = |fifo_error_56; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8111 = _T_1864 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_57 = _T_1861 ? _T_7477 : _T_8111; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4819 = |fifo_error_in_57; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_57; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4822 = |fifo_error_57; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8122 = _T_1882 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_58 = _T_1879 ? _T_7477 : _T_8122; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4826 = |fifo_error_in_58; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_58; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4829 = |fifo_error_58; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8133 = _T_1900 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_59 = _T_1897 ? _T_7477 : _T_8133; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4833 = |fifo_error_in_59; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_59; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4836 = |fifo_error_59; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8144 = _T_1918 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_60 = _T_1915 ? _T_7477 : _T_8144; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4840 = |fifo_error_in_60; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_60; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4843 = |fifo_error_60; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8155 = _T_1936 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_61 = _T_1933 ? _T_7477 : _T_8155; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4847 = |fifo_error_in_61; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_61; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4850 = |fifo_error_61; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8166 = _T_1954 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_62 = _T_1951 ? _T_7477 : _T_8166; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4854 = |fifo_error_in_62; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_62; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4857 = |fifo_error_62; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8177 = _T_1972 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_63 = _T_1969 ? _T_7477 : _T_8177; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4861 = |fifo_error_in_63; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_63; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4864 = |fifo_error_63; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8188 = _T_1990 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_64 = _T_1987 ? _T_7477 : _T_8188; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4868 = |fifo_error_in_64; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_64; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4871 = |fifo_error_64; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8199 = _T_2008 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_65 = _T_2005 ? _T_7477 : _T_8199; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4875 = |fifo_error_in_65; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_65; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4878 = |fifo_error_65; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8210 = _T_2026 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_66 = _T_2023 ? _T_7477 : _T_8210; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4882 = |fifo_error_in_66; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_66; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4885 = |fifo_error_66; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8221 = _T_2044 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_67 = _T_2041 ? _T_7477 : _T_8221; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4889 = |fifo_error_in_67; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_67; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4892 = |fifo_error_67; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8232 = _T_2062 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_68 = _T_2059 ? _T_7477 : _T_8232; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4896 = |fifo_error_in_68; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_68; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4899 = |fifo_error_68; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8243 = _T_2080 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_69 = _T_2077 ? _T_7477 : _T_8243; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4903 = |fifo_error_in_69; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_69; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4906 = |fifo_error_69; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8254 = _T_2098 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_70 = _T_2095 ? _T_7477 : _T_8254; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4910 = |fifo_error_in_70; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_70; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4913 = |fifo_error_70; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8265 = _T_2116 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_71 = _T_2113 ? _T_7477 : _T_8265; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4917 = |fifo_error_in_71; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_71; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4920 = |fifo_error_71; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8276 = _T_2134 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_72 = _T_2131 ? _T_7477 : _T_8276; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4924 = |fifo_error_in_72; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_72; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4927 = |fifo_error_72; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8287 = _T_2152 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_73 = _T_2149 ? _T_7477 : _T_8287; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4931 = |fifo_error_in_73; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_73; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4934 = |fifo_error_73; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8298 = _T_2170 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_74 = _T_2167 ? _T_7477 : _T_8298; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4938 = |fifo_error_in_74; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_74; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4941 = |fifo_error_74; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8309 = _T_2188 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_75 = _T_2185 ? _T_7477 : _T_8309; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4945 = |fifo_error_in_75; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_75; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4948 = |fifo_error_75; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8320 = _T_2206 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_76 = _T_2203 ? _T_7477 : _T_8320; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4952 = |fifo_error_in_76; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_76; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4955 = |fifo_error_76; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8331 = _T_2224 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_77 = _T_2221 ? _T_7477 : _T_8331; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4959 = |fifo_error_in_77; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_77; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4962 = |fifo_error_77; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8342 = _T_2242 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_78 = _T_2239 ? _T_7477 : _T_8342; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4966 = |fifo_error_in_78; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_78; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4969 = |fifo_error_78; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8353 = _T_2260 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_79 = _T_2257 ? _T_7477 : _T_8353; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4973 = |fifo_error_in_79; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_79; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4976 = |fifo_error_79; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8364 = _T_2278 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_80 = _T_2275 ? _T_7477 : _T_8364; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4980 = |fifo_error_in_80; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_80; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4983 = |fifo_error_80; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8375 = _T_2296 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_81 = _T_2293 ? _T_7477 : _T_8375; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4987 = |fifo_error_in_81; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_81; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4990 = |fifo_error_81; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8386 = _T_2314 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_82 = _T_2311 ? _T_7477 : _T_8386; // @[dma_ctrl.scala 136:60]
|
|
wire _T_4994 = |fifo_error_in_82; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_82; // @[dma_ctrl.scala 143:85]
|
|
wire _T_4997 = |fifo_error_82; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8397 = _T_2332 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_83 = _T_2329 ? _T_7477 : _T_8397; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5001 = |fifo_error_in_83; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_83; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5004 = |fifo_error_83; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8408 = _T_2350 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_84 = _T_2347 ? _T_7477 : _T_8408; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5008 = |fifo_error_in_84; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_84; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5011 = |fifo_error_84; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8419 = _T_2368 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_85 = _T_2365 ? _T_7477 : _T_8419; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5015 = |fifo_error_in_85; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_85; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5018 = |fifo_error_85; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8430 = _T_2386 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_86 = _T_2383 ? _T_7477 : _T_8430; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5022 = |fifo_error_in_86; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_86; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5025 = |fifo_error_86; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8441 = _T_2404 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_87 = _T_2401 ? _T_7477 : _T_8441; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5029 = |fifo_error_in_87; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_87; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5032 = |fifo_error_87; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8452 = _T_2422 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_88 = _T_2419 ? _T_7477 : _T_8452; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5036 = |fifo_error_in_88; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_88; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5039 = |fifo_error_88; // @[dma_ctrl.scala 128:125]
|
|
wire [1:0] _T_8463 = _T_2440 ? _T_7480 : _T_7483; // @[dma_ctrl.scala 136:209]
|
|
wire [1:0] fifo_error_in_89 = _T_2437 ? _T_7477 : _T_8463; // @[dma_ctrl.scala 136:60]
|
|
wire _T_5043 = |fifo_error_in_89; // @[dma_ctrl.scala 128:83]
|
|
reg [1:0] fifo_error_89; // @[dma_ctrl.scala 143:85]
|
|
wire _T_5046 = |fifo_error_89; // @[dma_ctrl.scala 128:125]
|
|
wire _T_5140 = _T_4423 | fifo_error_en[0]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5142 = _T_2531 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 130:176]
|
|
wire _T_5143 = _T_5140 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5145 = _T_5143 & _T_831; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5148 = _T_5145 | _T_835; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5151 = _T_5148 | _T_838; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5154 = _T_4430 | fifo_error_en[1]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5157 = _T_5154 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5159 = _T_5157 & _T_849; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5162 = _T_5159 | _T_853; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5165 = _T_5162 | _T_856; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5168 = _T_4437 | fifo_error_en[2]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5171 = _T_5168 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5173 = _T_5171 & _T_867; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5176 = _T_5173 | _T_871; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5179 = _T_5176 | _T_874; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5182 = _T_4444 | fifo_error_en[3]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5185 = _T_5182 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5187 = _T_5185 & _T_885; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5190 = _T_5187 | _T_889; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5193 = _T_5190 | _T_892; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5196 = _T_4451 | fifo_error_en[4]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5199 = _T_5196 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5201 = _T_5199 & _T_903; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5204 = _T_5201 | _T_907; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5207 = _T_5204 | _T_910; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5210 = _T_4458 | fifo_error_en[5]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5213 = _T_5210 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5215 = _T_5213 & _T_921; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5218 = _T_5215 | _T_925; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5221 = _T_5218 | _T_928; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5224 = _T_4465 | fifo_error_en[6]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5227 = _T_5224 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5229 = _T_5227 & _T_939; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5232 = _T_5229 | _T_943; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5235 = _T_5232 | _T_946; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5238 = _T_4472 | fifo_error_en[7]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5241 = _T_5238 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5243 = _T_5241 & _T_957; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5246 = _T_5243 | _T_961; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5249 = _T_5246 | _T_964; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5252 = _T_4479 | fifo_error_en[8]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5255 = _T_5252 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5257 = _T_5255 & _T_975; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5260 = _T_5257 | _T_979; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5263 = _T_5260 | _T_982; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5266 = _T_4486 | fifo_error_en[9]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5269 = _T_5266 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5271 = _T_5269 & _T_993; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5274 = _T_5271 | _T_997; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5277 = _T_5274 | _T_1000; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5280 = _T_4493 | fifo_error_en[10]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5283 = _T_5280 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5285 = _T_5283 & _T_1011; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5288 = _T_5285 | _T_1015; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5291 = _T_5288 | _T_1018; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5294 = _T_4500 | fifo_error_en[11]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5297 = _T_5294 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5299 = _T_5297 & _T_1029; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5302 = _T_5299 | _T_1033; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5305 = _T_5302 | _T_1036; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5308 = _T_4507 | fifo_error_en[12]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5311 = _T_5308 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5313 = _T_5311 & _T_1047; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5316 = _T_5313 | _T_1051; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5319 = _T_5316 | _T_1054; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5322 = _T_4514 | fifo_error_en[13]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5325 = _T_5322 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5327 = _T_5325 & _T_1065; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5330 = _T_5327 | _T_1069; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5333 = _T_5330 | _T_1072; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5336 = _T_4521 | fifo_error_en[14]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5339 = _T_5336 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5341 = _T_5339 & _T_1083; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5344 = _T_5341 | _T_1087; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5347 = _T_5344 | _T_1090; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5350 = _T_4528 | fifo_error_en[15]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5353 = _T_5350 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5355 = _T_5353 & _T_1101; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5358 = _T_5355 | _T_1105; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5361 = _T_5358 | _T_1108; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5364 = _T_4535 | fifo_error_en[16]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5367 = _T_5364 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5369 = _T_5367 & _T_1119; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5372 = _T_5369 | _T_1123; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5375 = _T_5372 | _T_1126; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5378 = _T_4542 | fifo_error_en[17]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5381 = _T_5378 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5383 = _T_5381 & _T_1137; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5386 = _T_5383 | _T_1141; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5389 = _T_5386 | _T_1144; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5392 = _T_4549 | fifo_error_en[18]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5395 = _T_5392 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5397 = _T_5395 & _T_1155; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5400 = _T_5397 | _T_1159; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5403 = _T_5400 | _T_1162; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5406 = _T_4556 | fifo_error_en[19]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5409 = _T_5406 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5411 = _T_5409 & _T_1173; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5414 = _T_5411 | _T_1177; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5417 = _T_5414 | _T_1180; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5420 = _T_4563 | fifo_error_en[20]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5423 = _T_5420 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5425 = _T_5423 & _T_1191; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5428 = _T_5425 | _T_1195; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5431 = _T_5428 | _T_1198; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5434 = _T_4570 | fifo_error_en[21]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5437 = _T_5434 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5439 = _T_5437 & _T_1209; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5442 = _T_5439 | _T_1213; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5445 = _T_5442 | _T_1216; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5448 = _T_4577 | fifo_error_en[22]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5451 = _T_5448 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5453 = _T_5451 & _T_1227; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5456 = _T_5453 | _T_1231; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5459 = _T_5456 | _T_1234; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5462 = _T_4584 | fifo_error_en[23]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5465 = _T_5462 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5467 = _T_5465 & _T_1245; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5470 = _T_5467 | _T_1249; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5473 = _T_5470 | _T_1252; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5476 = _T_4591 | fifo_error_en[24]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5479 = _T_5476 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5481 = _T_5479 & _T_1263; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5484 = _T_5481 | _T_1267; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5487 = _T_5484 | _T_1270; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5490 = _T_4598 | fifo_error_en[25]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5493 = _T_5490 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5495 = _T_5493 & _T_1281; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5498 = _T_5495 | _T_1285; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5501 = _T_5498 | _T_1288; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5504 = _T_4605 | fifo_error_en[26]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5507 = _T_5504 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5509 = _T_5507 & _T_1299; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5512 = _T_5509 | _T_1303; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5515 = _T_5512 | _T_1306; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5518 = _T_4612 | fifo_error_en[27]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5521 = _T_5518 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5523 = _T_5521 & _T_1317; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5526 = _T_5523 | _T_1321; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5529 = _T_5526 | _T_1324; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5532 = _T_4619 | fifo_error_en[28]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5535 = _T_5532 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5537 = _T_5535 & _T_1335; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5540 = _T_5537 | _T_1339; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5543 = _T_5540 | _T_1342; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5546 = _T_4626 | fifo_error_en[29]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5549 = _T_5546 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5551 = _T_5549 & _T_1353; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5554 = _T_5551 | _T_1357; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5557 = _T_5554 | _T_1360; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5560 = _T_4633 | fifo_error_en[30]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5563 = _T_5560 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5565 = _T_5563 & _T_1371; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5568 = _T_5565 | _T_1375; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5571 = _T_5568 | _T_1378; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5574 = _T_4640 | fifo_error_en[31]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5577 = _T_5574 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5579 = _T_5577 & _T_1389; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5582 = _T_5579 | _T_1393; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5585 = _T_5582 | _T_1396; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5588 = _T_4647 | fifo_error_en[32]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5591 = _T_5588 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5593 = _T_5591 & _T_1407; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5596 = _T_5593 | _T_1411; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5599 = _T_5596 | _T_1414; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5602 = _T_4654 | fifo_error_en[33]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5605 = _T_5602 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5607 = _T_5605 & _T_1425; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5610 = _T_5607 | _T_1429; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5613 = _T_5610 | _T_1432; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5616 = _T_4661 | fifo_error_en[34]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5619 = _T_5616 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5621 = _T_5619 & _T_1443; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5624 = _T_5621 | _T_1447; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5627 = _T_5624 | _T_1450; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5630 = _T_4668 | fifo_error_en[35]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5633 = _T_5630 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5635 = _T_5633 & _T_1461; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5638 = _T_5635 | _T_1465; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5641 = _T_5638 | _T_1468; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5644 = _T_4675 | fifo_error_en[36]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5647 = _T_5644 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5649 = _T_5647 & _T_1479; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5652 = _T_5649 | _T_1483; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5655 = _T_5652 | _T_1486; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5658 = _T_4682 | fifo_error_en[37]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5661 = _T_5658 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5663 = _T_5661 & _T_1497; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5666 = _T_5663 | _T_1501; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5669 = _T_5666 | _T_1504; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5672 = _T_4689 | fifo_error_en[38]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5675 = _T_5672 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5677 = _T_5675 & _T_1515; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5680 = _T_5677 | _T_1519; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5683 = _T_5680 | _T_1522; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5686 = _T_4696 | fifo_error_en[39]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5689 = _T_5686 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5691 = _T_5689 & _T_1533; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5694 = _T_5691 | _T_1537; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5697 = _T_5694 | _T_1540; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5700 = _T_4703 | fifo_error_en[40]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5703 = _T_5700 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5705 = _T_5703 & _T_1551; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5708 = _T_5705 | _T_1555; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5711 = _T_5708 | _T_1558; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5714 = _T_4710 | fifo_error_en[41]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5717 = _T_5714 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5719 = _T_5717 & _T_1569; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5722 = _T_5719 | _T_1573; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5725 = _T_5722 | _T_1576; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5728 = _T_4717 | fifo_error_en[42]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5731 = _T_5728 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5733 = _T_5731 & _T_1587; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5736 = _T_5733 | _T_1591; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5739 = _T_5736 | _T_1594; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5742 = _T_4724 | fifo_error_en[43]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5745 = _T_5742 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5747 = _T_5745 & _T_1605; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5750 = _T_5747 | _T_1609; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5753 = _T_5750 | _T_1612; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5756 = _T_4731 | fifo_error_en[44]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5759 = _T_5756 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5761 = _T_5759 & _T_1623; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5764 = _T_5761 | _T_1627; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5767 = _T_5764 | _T_1630; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5770 = _T_4738 | fifo_error_en[45]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5773 = _T_5770 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5775 = _T_5773 & _T_1641; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5778 = _T_5775 | _T_1645; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5781 = _T_5778 | _T_1648; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5784 = _T_4745 | fifo_error_en[46]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5787 = _T_5784 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5789 = _T_5787 & _T_1659; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5792 = _T_5789 | _T_1663; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5795 = _T_5792 | _T_1666; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5798 = _T_4752 | fifo_error_en[47]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5801 = _T_5798 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5803 = _T_5801 & _T_1677; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5806 = _T_5803 | _T_1681; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5809 = _T_5806 | _T_1684; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5812 = _T_4759 | fifo_error_en[48]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5815 = _T_5812 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5817 = _T_5815 & _T_1695; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5820 = _T_5817 | _T_1699; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5823 = _T_5820 | _T_1702; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5826 = _T_4766 | fifo_error_en[49]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5829 = _T_5826 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5831 = _T_5829 & _T_1713; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5834 = _T_5831 | _T_1717; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5837 = _T_5834 | _T_1720; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5840 = _T_4773 | fifo_error_en[50]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5843 = _T_5840 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5845 = _T_5843 & _T_1731; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5848 = _T_5845 | _T_1735; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5851 = _T_5848 | _T_1738; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5854 = _T_4780 | fifo_error_en[51]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5857 = _T_5854 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5859 = _T_5857 & _T_1749; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5862 = _T_5859 | _T_1753; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5865 = _T_5862 | _T_1756; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5868 = _T_4787 | fifo_error_en[52]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5871 = _T_5868 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5873 = _T_5871 & _T_1767; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5876 = _T_5873 | _T_1771; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5879 = _T_5876 | _T_1774; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5882 = _T_4794 | fifo_error_en[53]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5885 = _T_5882 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5887 = _T_5885 & _T_1785; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5890 = _T_5887 | _T_1789; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5893 = _T_5890 | _T_1792; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5896 = _T_4801 | fifo_error_en[54]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5899 = _T_5896 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5901 = _T_5899 & _T_1803; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5904 = _T_5901 | _T_1807; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5907 = _T_5904 | _T_1810; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5910 = _T_4808 | fifo_error_en[55]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5913 = _T_5910 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5915 = _T_5913 & _T_1821; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5918 = _T_5915 | _T_1825; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5921 = _T_5918 | _T_1828; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5924 = _T_4815 | fifo_error_en[56]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5927 = _T_5924 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5929 = _T_5927 & _T_1839; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5932 = _T_5929 | _T_1843; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5935 = _T_5932 | _T_1846; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5938 = _T_4822 | fifo_error_en[57]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5941 = _T_5938 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5943 = _T_5941 & _T_1857; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5946 = _T_5943 | _T_1861; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5949 = _T_5946 | _T_1864; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5952 = _T_4829 | fifo_error_en[58]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5955 = _T_5952 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5957 = _T_5955 & _T_1875; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5960 = _T_5957 | _T_1879; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5963 = _T_5960 | _T_1882; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5966 = _T_4836 | fifo_error_en[59]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5969 = _T_5966 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5971 = _T_5969 & _T_1893; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5974 = _T_5971 | _T_1897; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5977 = _T_5974 | _T_1900; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5980 = _T_4843 | fifo_error_en[60]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5983 = _T_5980 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5985 = _T_5983 & _T_1911; // @[dma_ctrl.scala 130:217]
|
|
wire _T_5988 = _T_5985 | _T_1915; // @[dma_ctrl.scala 130:236]
|
|
wire _T_5991 = _T_5988 | _T_1918; // @[dma_ctrl.scala 130:330]
|
|
wire _T_5994 = _T_4850 | fifo_error_en[61]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_5997 = _T_5994 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_5999 = _T_5997 & _T_1929; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6002 = _T_5999 | _T_1933; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6005 = _T_6002 | _T_1936; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6008 = _T_4857 | fifo_error_en[62]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6011 = _T_6008 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6013 = _T_6011 & _T_1947; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6016 = _T_6013 | _T_1951; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6019 = _T_6016 | _T_1954; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6022 = _T_4864 | fifo_error_en[63]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6025 = _T_6022 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6027 = _T_6025 & _T_1965; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6030 = _T_6027 | _T_1969; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6033 = _T_6030 | _T_1972; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6036 = _T_4871 | fifo_error_en[64]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6039 = _T_6036 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6041 = _T_6039 & _T_1983; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6044 = _T_6041 | _T_1987; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6047 = _T_6044 | _T_1990; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6050 = _T_4878 | fifo_error_en[65]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6053 = _T_6050 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6055 = _T_6053 & _T_2001; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6058 = _T_6055 | _T_2005; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6061 = _T_6058 | _T_2008; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6064 = _T_4885 | fifo_error_en[66]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6067 = _T_6064 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6069 = _T_6067 & _T_2019; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6072 = _T_6069 | _T_2023; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6075 = _T_6072 | _T_2026; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6078 = _T_4892 | fifo_error_en[67]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6081 = _T_6078 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6083 = _T_6081 & _T_2037; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6086 = _T_6083 | _T_2041; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6089 = _T_6086 | _T_2044; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6092 = _T_4899 | fifo_error_en[68]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6095 = _T_6092 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6097 = _T_6095 & _T_2055; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6100 = _T_6097 | _T_2059; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6103 = _T_6100 | _T_2062; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6106 = _T_4906 | fifo_error_en[69]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6109 = _T_6106 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6111 = _T_6109 & _T_2073; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6114 = _T_6111 | _T_2077; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6117 = _T_6114 | _T_2080; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6120 = _T_4913 | fifo_error_en[70]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6123 = _T_6120 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6125 = _T_6123 & _T_2091; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6128 = _T_6125 | _T_2095; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6131 = _T_6128 | _T_2098; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6134 = _T_4920 | fifo_error_en[71]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6137 = _T_6134 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6139 = _T_6137 & _T_2109; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6142 = _T_6139 | _T_2113; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6145 = _T_6142 | _T_2116; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6148 = _T_4927 | fifo_error_en[72]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6151 = _T_6148 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6153 = _T_6151 & _T_2127; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6156 = _T_6153 | _T_2131; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6159 = _T_6156 | _T_2134; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6162 = _T_4934 | fifo_error_en[73]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6165 = _T_6162 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6167 = _T_6165 & _T_2145; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6170 = _T_6167 | _T_2149; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6173 = _T_6170 | _T_2152; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6176 = _T_4941 | fifo_error_en[74]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6179 = _T_6176 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6181 = _T_6179 & _T_2163; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6184 = _T_6181 | _T_2167; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6187 = _T_6184 | _T_2170; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6190 = _T_4948 | fifo_error_en[75]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6193 = _T_6190 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6195 = _T_6193 & _T_2181; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6198 = _T_6195 | _T_2185; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6201 = _T_6198 | _T_2188; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6204 = _T_4955 | fifo_error_en[76]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6207 = _T_6204 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6209 = _T_6207 & _T_2199; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6212 = _T_6209 | _T_2203; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6215 = _T_6212 | _T_2206; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6218 = _T_4962 | fifo_error_en[77]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6221 = _T_6218 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6223 = _T_6221 & _T_2217; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6226 = _T_6223 | _T_2221; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6229 = _T_6226 | _T_2224; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6232 = _T_4969 | fifo_error_en[78]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6235 = _T_6232 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6237 = _T_6235 & _T_2235; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6240 = _T_6237 | _T_2239; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6243 = _T_6240 | _T_2242; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6246 = _T_4976 | fifo_error_en[79]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6249 = _T_6246 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6251 = _T_6249 & _T_2253; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6254 = _T_6251 | _T_2257; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6257 = _T_6254 | _T_2260; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6260 = _T_4983 | fifo_error_en[80]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6263 = _T_6260 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6265 = _T_6263 & _T_2271; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6268 = _T_6265 | _T_2275; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6271 = _T_6268 | _T_2278; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6274 = _T_4990 | fifo_error_en[81]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6277 = _T_6274 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6279 = _T_6277 & _T_2289; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6282 = _T_6279 | _T_2293; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6285 = _T_6282 | _T_2296; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6288 = _T_4997 | fifo_error_en[82]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6291 = _T_6288 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6293 = _T_6291 & _T_2307; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6296 = _T_6293 | _T_2311; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6299 = _T_6296 | _T_2314; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6302 = _T_5004 | fifo_error_en[83]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6305 = _T_6302 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6307 = _T_6305 & _T_2325; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6310 = _T_6307 | _T_2329; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6313 = _T_6310 | _T_2332; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6316 = _T_5011 | fifo_error_en[84]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6319 = _T_6316 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6321 = _T_6319 & _T_2343; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6324 = _T_6321 | _T_2347; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6327 = _T_6324 | _T_2350; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6330 = _T_5018 | fifo_error_en[85]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6333 = _T_6330 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6335 = _T_6333 & _T_2361; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6338 = _T_6335 | _T_2365; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6341 = _T_6338 | _T_2368; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6344 = _T_5025 | fifo_error_en[86]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6347 = _T_6344 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6349 = _T_6347 & _T_2379; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6352 = _T_6349 | _T_2383; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6355 = _T_6352 | _T_2386; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6358 = _T_5032 | fifo_error_en[87]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6361 = _T_6358 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6363 = _T_6361 & _T_2397; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6366 = _T_6363 | _T_2401; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6369 = _T_6366 | _T_2404; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6372 = _T_5039 | fifo_error_en[88]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6375 = _T_6372 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6377 = _T_6375 & _T_2415; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6380 = _T_6377 | _T_2419; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6383 = _T_6380 | _T_2422; // @[dma_ctrl.scala 130:330]
|
|
wire _T_6386 = _T_5046 | fifo_error_en[89]; // @[dma_ctrl.scala 130:78]
|
|
wire _T_6389 = _T_6386 | _T_5142; // @[dma_ctrl.scala 130:97]
|
|
wire _T_6391 = _T_6389 & _T_2433; // @[dma_ctrl.scala 130:217]
|
|
wire _T_6394 = _T_6391 | _T_2437; // @[dma_ctrl.scala 130:236]
|
|
wire _T_6397 = _T_6394 | _T_2440; // @[dma_ctrl.scala 130:330]
|
|
wire [9:0] _T_6406 = {_T_6397,_T_6383,_T_6369,_T_6355,_T_6341,_T_6327,_T_6313,_T_6299,_T_6285,_T_6271}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_6415 = {_T_6406,_T_6257,_T_6243,_T_6229,_T_6215,_T_6201,_T_6187,_T_6173,_T_6159,_T_6145}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_6424 = {_T_6415,_T_6131,_T_6117,_T_6103,_T_6089,_T_6075,_T_6061,_T_6047,_T_6033,_T_6019}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_6433 = {_T_6424,_T_6005,_T_5991,_T_5977,_T_5963,_T_5949,_T_5935,_T_5921,_T_5907,_T_5893}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_6442 = {_T_6433,_T_5879,_T_5865,_T_5851,_T_5837,_T_5823,_T_5809,_T_5795,_T_5781,_T_5767}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_6451 = {_T_6442,_T_5753,_T_5739,_T_5725,_T_5711,_T_5697,_T_5683,_T_5669,_T_5655,_T_5641}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_6460 = {_T_6451,_T_5627,_T_5613,_T_5599,_T_5585,_T_5571,_T_5557,_T_5543,_T_5529,_T_5515}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_6469 = {_T_6460,_T_5501,_T_5487,_T_5473,_T_5459,_T_5445,_T_5431,_T_5417,_T_5403,_T_5389}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_6478 = {_T_6469,_T_5375,_T_5361,_T_5347,_T_5333,_T_5319,_T_5305,_T_5291,_T_5277,_T_5263}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_done_en = {_T_6478,_T_5249,_T_5235,_T_5221,_T_5207,_T_5193,_T_5179,_T_5165,_T_5151}; // @[Cat.scala 29:58]
|
|
wire _T_6489 = fifo_done_en[0] | fifo_done[0]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6490 = _T_6489 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6493 = fifo_done_en[1] | fifo_done[1]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6494 = _T_6493 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6497 = fifo_done_en[2] | fifo_done[2]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6498 = _T_6497 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6501 = fifo_done_en[3] | fifo_done[3]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6502 = _T_6501 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6505 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6506 = _T_6505 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6509 = fifo_done_en[5] | fifo_done[5]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6510 = _T_6509 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6513 = fifo_done_en[6] | fifo_done[6]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6514 = _T_6513 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6517 = fifo_done_en[7] | fifo_done[7]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6518 = _T_6517 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6521 = fifo_done_en[8] | fifo_done[8]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6522 = _T_6521 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6525 = fifo_done_en[9] | fifo_done[9]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6526 = _T_6525 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6529 = fifo_done_en[10] | fifo_done[10]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6530 = _T_6529 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6533 = fifo_done_en[11] | fifo_done[11]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6534 = _T_6533 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6537 = fifo_done_en[12] | fifo_done[12]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6538 = _T_6537 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6541 = fifo_done_en[13] | fifo_done[13]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6542 = _T_6541 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6545 = fifo_done_en[14] | fifo_done[14]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6546 = _T_6545 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6549 = fifo_done_en[15] | fifo_done[15]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6550 = _T_6549 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6553 = fifo_done_en[16] | fifo_done[16]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6554 = _T_6553 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6557 = fifo_done_en[17] | fifo_done[17]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6558 = _T_6557 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6561 = fifo_done_en[18] | fifo_done[18]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6562 = _T_6561 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6565 = fifo_done_en[19] | fifo_done[19]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6566 = _T_6565 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6569 = fifo_done_en[20] | fifo_done[20]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6570 = _T_6569 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6573 = fifo_done_en[21] | fifo_done[21]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6574 = _T_6573 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6577 = fifo_done_en[22] | fifo_done[22]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6578 = _T_6577 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6581 = fifo_done_en[23] | fifo_done[23]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6582 = _T_6581 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6585 = fifo_done_en[24] | fifo_done[24]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6586 = _T_6585 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6589 = fifo_done_en[25] | fifo_done[25]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6590 = _T_6589 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6593 = fifo_done_en[26] | fifo_done[26]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6594 = _T_6593 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6597 = fifo_done_en[27] | fifo_done[27]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6598 = _T_6597 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6601 = fifo_done_en[28] | fifo_done[28]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6602 = _T_6601 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6605 = fifo_done_en[29] | fifo_done[29]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6606 = _T_6605 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6609 = fifo_done_en[30] | fifo_done[30]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6610 = _T_6609 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6613 = fifo_done_en[31] | fifo_done[31]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6614 = _T_6613 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6617 = fifo_done_en[32] | fifo_done[32]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6618 = _T_6617 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6621 = fifo_done_en[33] | fifo_done[33]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6622 = _T_6621 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6625 = fifo_done_en[34] | fifo_done[34]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6626 = _T_6625 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6629 = fifo_done_en[35] | fifo_done[35]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6630 = _T_6629 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6633 = fifo_done_en[36] | fifo_done[36]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6634 = _T_6633 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6637 = fifo_done_en[37] | fifo_done[37]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6638 = _T_6637 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6641 = fifo_done_en[38] | fifo_done[38]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6642 = _T_6641 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6645 = fifo_done_en[39] | fifo_done[39]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6646 = _T_6645 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6649 = fifo_done_en[40] | fifo_done[40]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6650 = _T_6649 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6653 = fifo_done_en[41] | fifo_done[41]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6654 = _T_6653 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6657 = fifo_done_en[42] | fifo_done[42]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6658 = _T_6657 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6661 = fifo_done_en[43] | fifo_done[43]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6662 = _T_6661 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6665 = fifo_done_en[44] | fifo_done[44]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6666 = _T_6665 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6669 = fifo_done_en[45] | fifo_done[45]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6670 = _T_6669 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6673 = fifo_done_en[46] | fifo_done[46]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6674 = _T_6673 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6677 = fifo_done_en[47] | fifo_done[47]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6678 = _T_6677 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6681 = fifo_done_en[48] | fifo_done[48]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6682 = _T_6681 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6685 = fifo_done_en[49] | fifo_done[49]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6686 = _T_6685 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6689 = fifo_done_en[50] | fifo_done[50]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6690 = _T_6689 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6693 = fifo_done_en[51] | fifo_done[51]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6694 = _T_6693 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6697 = fifo_done_en[52] | fifo_done[52]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6698 = _T_6697 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6701 = fifo_done_en[53] | fifo_done[53]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6702 = _T_6701 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6705 = fifo_done_en[54] | fifo_done[54]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6706 = _T_6705 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6709 = fifo_done_en[55] | fifo_done[55]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6710 = _T_6709 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6713 = fifo_done_en[56] | fifo_done[56]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6714 = _T_6713 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6717 = fifo_done_en[57] | fifo_done[57]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6718 = _T_6717 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6721 = fifo_done_en[58] | fifo_done[58]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6722 = _T_6721 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6725 = fifo_done_en[59] | fifo_done[59]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6726 = _T_6725 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6729 = fifo_done_en[60] | fifo_done[60]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6730 = _T_6729 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6733 = fifo_done_en[61] | fifo_done[61]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6734 = _T_6733 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6737 = fifo_done_en[62] | fifo_done[62]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6738 = _T_6737 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6741 = fifo_done_en[63] | fifo_done[63]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6742 = _T_6741 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6745 = fifo_done_en[64] | fifo_done[64]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6746 = _T_6745 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6749 = fifo_done_en[65] | fifo_done[65]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6750 = _T_6749 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6753 = fifo_done_en[66] | fifo_done[66]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6754 = _T_6753 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6757 = fifo_done_en[67] | fifo_done[67]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6758 = _T_6757 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6761 = fifo_done_en[68] | fifo_done[68]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6762 = _T_6761 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6765 = fifo_done_en[69] | fifo_done[69]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6766 = _T_6765 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6769 = fifo_done_en[70] | fifo_done[70]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6770 = _T_6769 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6773 = fifo_done_en[71] | fifo_done[71]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6774 = _T_6773 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6777 = fifo_done_en[72] | fifo_done[72]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6778 = _T_6777 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6781 = fifo_done_en[73] | fifo_done[73]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6782 = _T_6781 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6785 = fifo_done_en[74] | fifo_done[74]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6786 = _T_6785 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6789 = fifo_done_en[75] | fifo_done[75]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6790 = _T_6789 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6793 = fifo_done_en[76] | fifo_done[76]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6794 = _T_6793 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6797 = fifo_done_en[77] | fifo_done[77]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6798 = _T_6797 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6801 = fifo_done_en[78] | fifo_done[78]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6802 = _T_6801 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6805 = fifo_done_en[79] | fifo_done[79]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6806 = _T_6805 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6809 = fifo_done_en[80] | fifo_done[80]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6810 = _T_6809 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6813 = fifo_done_en[81] | fifo_done[81]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6814 = _T_6813 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6817 = fifo_done_en[82] | fifo_done[82]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6818 = _T_6817 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6821 = fifo_done_en[83] | fifo_done[83]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6822 = _T_6821 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6825 = fifo_done_en[84] | fifo_done[84]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6826 = _T_6825 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6829 = fifo_done_en[85] | fifo_done[85]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6830 = _T_6829 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6833 = fifo_done_en[86] | fifo_done[86]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6834 = _T_6833 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6837 = fifo_done_en[87] | fifo_done[87]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6838 = _T_6837 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6841 = fifo_done_en[88] | fifo_done[88]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6842 = _T_6841 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire _T_6845 = fifo_done_en[89] | fifo_done[89]; // @[dma_ctrl.scala 132:75]
|
|
wire _T_6846 = _T_6845 & io_dma_bus_clk_en; // @[dma_ctrl.scala 132:91]
|
|
wire [9:0] _T_6855 = {_T_6846,_T_6842,_T_6838,_T_6834,_T_6830,_T_6826,_T_6822,_T_6818,_T_6814,_T_6810}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_6864 = {_T_6855,_T_6806,_T_6802,_T_6798,_T_6794,_T_6790,_T_6786,_T_6782,_T_6778,_T_6774}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_6873 = {_T_6864,_T_6770,_T_6766,_T_6762,_T_6758,_T_6754,_T_6750,_T_6746,_T_6742,_T_6738}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_6882 = {_T_6873,_T_6734,_T_6730,_T_6726,_T_6722,_T_6718,_T_6714,_T_6710,_T_6706,_T_6702}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_6891 = {_T_6882,_T_6698,_T_6694,_T_6690,_T_6686,_T_6682,_T_6678,_T_6674,_T_6670,_T_6666}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_6900 = {_T_6891,_T_6662,_T_6658,_T_6654,_T_6650,_T_6646,_T_6642,_T_6638,_T_6634,_T_6630}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_6909 = {_T_6900,_T_6626,_T_6622,_T_6618,_T_6614,_T_6610,_T_6606,_T_6602,_T_6598,_T_6594}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_6918 = {_T_6909,_T_6590,_T_6586,_T_6582,_T_6578,_T_6574,_T_6570,_T_6566,_T_6562,_T_6558}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_6927 = {_T_6918,_T_6554,_T_6550,_T_6546,_T_6542,_T_6538,_T_6534,_T_6530,_T_6526,_T_6522}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_done_bus_en = {_T_6927,_T_6518,_T_6514,_T_6510,_T_6506,_T_6502,_T_6498,_T_6494,_T_6490}; // @[Cat.scala 29:58]
|
|
wire _T_17304 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 388:45]
|
|
wire _T_17305 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 388:89]
|
|
wire bus_rsp_sent = _T_17304 | _T_17305; // @[dma_ctrl.scala 388:67]
|
|
wire _T_6937 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 134:99]
|
|
wire _T_6938 = _T_6937 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 134:120]
|
|
reg [6:0] RspPtr; // @[Reg.scala 27:20]
|
|
wire _T_6939 = 7'h0 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6940 = _T_6938 & _T_6939; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6944 = 7'h1 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6945 = _T_6938 & _T_6944; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6949 = 7'h2 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6950 = _T_6938 & _T_6949; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6954 = 7'h3 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6955 = _T_6938 & _T_6954; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6959 = 7'h4 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6960 = _T_6938 & _T_6959; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6964 = 7'h5 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6965 = _T_6938 & _T_6964; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6969 = 7'h6 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6970 = _T_6938 & _T_6969; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6974 = 7'h7 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6975 = _T_6938 & _T_6974; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6979 = 7'h8 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6980 = _T_6938 & _T_6979; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6984 = 7'h9 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6985 = _T_6938 & _T_6984; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6989 = 7'ha == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6990 = _T_6938 & _T_6989; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6994 = 7'hb == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_6995 = _T_6938 & _T_6994; // @[dma_ctrl.scala 134:143]
|
|
wire _T_6999 = 7'hc == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7000 = _T_6938 & _T_6999; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7004 = 7'hd == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7005 = _T_6938 & _T_7004; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7009 = 7'he == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7010 = _T_6938 & _T_7009; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7014 = 7'hf == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7015 = _T_6938 & _T_7014; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7019 = 7'h10 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7020 = _T_6938 & _T_7019; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7024 = 7'h11 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7025 = _T_6938 & _T_7024; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7029 = 7'h12 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7030 = _T_6938 & _T_7029; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7034 = 7'h13 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7035 = _T_6938 & _T_7034; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7039 = 7'h14 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7040 = _T_6938 & _T_7039; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7044 = 7'h15 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7045 = _T_6938 & _T_7044; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7049 = 7'h16 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7050 = _T_6938 & _T_7049; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7054 = 7'h17 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7055 = _T_6938 & _T_7054; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7059 = 7'h18 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7060 = _T_6938 & _T_7059; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7064 = 7'h19 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7065 = _T_6938 & _T_7064; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7069 = 7'h1a == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7070 = _T_6938 & _T_7069; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7074 = 7'h1b == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7075 = _T_6938 & _T_7074; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7079 = 7'h1c == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7080 = _T_6938 & _T_7079; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7084 = 7'h1d == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7085 = _T_6938 & _T_7084; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7089 = 7'h1e == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7090 = _T_6938 & _T_7089; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7094 = 7'h1f == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7095 = _T_6938 & _T_7094; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7099 = 7'h20 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7100 = _T_6938 & _T_7099; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7104 = 7'h21 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7105 = _T_6938 & _T_7104; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7109 = 7'h22 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7110 = _T_6938 & _T_7109; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7114 = 7'h23 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7115 = _T_6938 & _T_7114; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7119 = 7'h24 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7120 = _T_6938 & _T_7119; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7124 = 7'h25 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7125 = _T_6938 & _T_7124; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7129 = 7'h26 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7130 = _T_6938 & _T_7129; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7134 = 7'h27 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7135 = _T_6938 & _T_7134; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7139 = 7'h28 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7140 = _T_6938 & _T_7139; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7144 = 7'h29 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7145 = _T_6938 & _T_7144; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7149 = 7'h2a == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7150 = _T_6938 & _T_7149; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7154 = 7'h2b == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7155 = _T_6938 & _T_7154; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7159 = 7'h2c == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7160 = _T_6938 & _T_7159; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7164 = 7'h2d == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7165 = _T_6938 & _T_7164; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7169 = 7'h2e == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7170 = _T_6938 & _T_7169; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7174 = 7'h2f == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7175 = _T_6938 & _T_7174; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7179 = 7'h30 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7180 = _T_6938 & _T_7179; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7184 = 7'h31 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7185 = _T_6938 & _T_7184; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7189 = 7'h32 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7190 = _T_6938 & _T_7189; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7194 = 7'h33 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7195 = _T_6938 & _T_7194; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7199 = 7'h34 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7200 = _T_6938 & _T_7199; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7204 = 7'h35 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7205 = _T_6938 & _T_7204; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7209 = 7'h36 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7210 = _T_6938 & _T_7209; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7214 = 7'h37 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7215 = _T_6938 & _T_7214; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7219 = 7'h38 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7220 = _T_6938 & _T_7219; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7224 = 7'h39 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7225 = _T_6938 & _T_7224; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7229 = 7'h3a == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7230 = _T_6938 & _T_7229; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7234 = 7'h3b == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7235 = _T_6938 & _T_7234; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7239 = 7'h3c == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7240 = _T_6938 & _T_7239; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7244 = 7'h3d == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7245 = _T_6938 & _T_7244; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7249 = 7'h3e == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7250 = _T_6938 & _T_7249; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7254 = 7'h3f == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7255 = _T_6938 & _T_7254; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7259 = 7'h40 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7260 = _T_6938 & _T_7259; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7264 = 7'h41 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7265 = _T_6938 & _T_7264; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7269 = 7'h42 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7270 = _T_6938 & _T_7269; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7274 = 7'h43 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7275 = _T_6938 & _T_7274; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7279 = 7'h44 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7280 = _T_6938 & _T_7279; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7284 = 7'h45 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7285 = _T_6938 & _T_7284; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7289 = 7'h46 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7290 = _T_6938 & _T_7289; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7294 = 7'h47 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7295 = _T_6938 & _T_7294; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7299 = 7'h48 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7300 = _T_6938 & _T_7299; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7304 = 7'h49 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7305 = _T_6938 & _T_7304; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7309 = 7'h4a == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7310 = _T_6938 & _T_7309; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7314 = 7'h4b == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7315 = _T_6938 & _T_7314; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7319 = 7'h4c == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7320 = _T_6938 & _T_7319; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7324 = 7'h4d == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7325 = _T_6938 & _T_7324; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7329 = 7'h4e == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7330 = _T_6938 & _T_7329; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7334 = 7'h4f == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7335 = _T_6938 & _T_7334; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7339 = 7'h50 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7340 = _T_6938 & _T_7339; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7344 = 7'h51 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7345 = _T_6938 & _T_7344; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7349 = 7'h52 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7350 = _T_6938 & _T_7349; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7354 = 7'h53 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7355 = _T_6938 & _T_7354; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7359 = 7'h54 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7360 = _T_6938 & _T_7359; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7364 = 7'h55 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7365 = _T_6938 & _T_7364; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7369 = 7'h56 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7370 = _T_6938 & _T_7369; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7374 = 7'h57 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7375 = _T_6938 & _T_7374; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7379 = 7'h58 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7380 = _T_6938 & _T_7379; // @[dma_ctrl.scala 134:143]
|
|
wire _T_7384 = 7'h59 == RspPtr; // @[dma_ctrl.scala 134:150]
|
|
wire _T_7385 = _T_6938 & _T_7384; // @[dma_ctrl.scala 134:143]
|
|
wire [9:0] _T_7394 = {_T_7385,_T_7380,_T_7375,_T_7370,_T_7365,_T_7360,_T_7355,_T_7350,_T_7345,_T_7340}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_7403 = {_T_7394,_T_7335,_T_7330,_T_7325,_T_7320,_T_7315,_T_7310,_T_7305,_T_7300,_T_7295}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_7412 = {_T_7403,_T_7290,_T_7285,_T_7280,_T_7275,_T_7270,_T_7265,_T_7260,_T_7255,_T_7250}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_7421 = {_T_7412,_T_7245,_T_7240,_T_7235,_T_7230,_T_7225,_T_7220,_T_7215,_T_7210,_T_7205}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_7430 = {_T_7421,_T_7200,_T_7195,_T_7190,_T_7185,_T_7180,_T_7175,_T_7170,_T_7165,_T_7160}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_7439 = {_T_7430,_T_7155,_T_7150,_T_7145,_T_7140,_T_7135,_T_7130,_T_7125,_T_7120,_T_7115}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_7448 = {_T_7439,_T_7110,_T_7105,_T_7100,_T_7095,_T_7090,_T_7085,_T_7080,_T_7075,_T_7070}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_7457 = {_T_7448,_T_7065,_T_7060,_T_7055,_T_7050,_T_7045,_T_7040,_T_7035,_T_7030,_T_7025}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_7466 = {_T_7457,_T_7020,_T_7015,_T_7010,_T_7005,_T_7000,_T_6995,_T_6990,_T_6985,_T_6980}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_reset = {_T_7466,_T_6975,_T_6970,_T_6965,_T_6960,_T_6955,_T_6950,_T_6945,_T_6940}; // @[Cat.scala 29:58]
|
|
wire _T_8467 = fifo_error_en[0] & _T_4420; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8469 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58]
|
|
wire _T_17121 = io_dbg_cmd_size == 2'h0; // @[dma_ctrl.scala 241:27]
|
|
wire [31:0] _T_17124 = {io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[7:0],io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[7:0],io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[7:0],io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[7:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_17131 = _T_17121 ? _T_17124 : 32'h0; // @[Mux.scala 27:72]
|
|
wire _T_17126 = io_dbg_cmd_size == 2'h1; // @[dma_ctrl.scala 242:27]
|
|
wire [31:0] _T_17128 = {io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[15:0],io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata[15:0]}; // @[Cat.scala 29:58]
|
|
wire [31:0] _T_17132 = _T_17126 ? _T_17128 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_17134 = _T_17131 | _T_17132; // @[Mux.scala 27:72]
|
|
wire _T_17130 = io_dbg_cmd_size == 2'h2; // @[dma_ctrl.scala 243:27]
|
|
wire [31:0] _T_17133 = _T_17130 ? io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] dma_dbg_mem_wrdata = _T_17134 | _T_17133; // @[Mux.scala 27:72]
|
|
wire [63:0] _T_8474 = {dma_dbg_mem_wrdata,dma_dbg_mem_wrdata}; // @[Cat.scala 29:58]
|
|
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
|
|
wire [63:0] _T_8476 = io_dbg_dec_dma_dbg_ib_dbg_cmd_valid ? _T_8474 : wrbuf_data; // @[dma_ctrl.scala 140:350]
|
|
wire _T_8482 = fifo_error_en[1] & _T_4427; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8484 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58]
|
|
wire _T_8497 = fifo_error_en[2] & _T_4434; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8499 = {32'h0,fifo_addr_2}; // @[Cat.scala 29:58]
|
|
wire _T_8512 = fifo_error_en[3] & _T_4441; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8514 = {32'h0,fifo_addr_3}; // @[Cat.scala 29:58]
|
|
wire _T_8527 = fifo_error_en[4] & _T_4448; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8529 = {32'h0,fifo_addr_4}; // @[Cat.scala 29:58]
|
|
wire _T_8542 = fifo_error_en[5] & _T_4455; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8544 = {32'h0,fifo_addr_5}; // @[Cat.scala 29:58]
|
|
wire _T_8557 = fifo_error_en[6] & _T_4462; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8559 = {32'h0,fifo_addr_6}; // @[Cat.scala 29:58]
|
|
wire _T_8572 = fifo_error_en[7] & _T_4469; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8574 = {32'h0,fifo_addr_7}; // @[Cat.scala 29:58]
|
|
wire _T_8587 = fifo_error_en[8] & _T_4476; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8589 = {32'h0,fifo_addr_8}; // @[Cat.scala 29:58]
|
|
wire _T_8602 = fifo_error_en[9] & _T_4483; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8604 = {32'h0,fifo_addr_9}; // @[Cat.scala 29:58]
|
|
wire _T_8617 = fifo_error_en[10] & _T_4490; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8619 = {32'h0,fifo_addr_10}; // @[Cat.scala 29:58]
|
|
wire _T_8632 = fifo_error_en[11] & _T_4497; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8634 = {32'h0,fifo_addr_11}; // @[Cat.scala 29:58]
|
|
wire _T_8647 = fifo_error_en[12] & _T_4504; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8649 = {32'h0,fifo_addr_12}; // @[Cat.scala 29:58]
|
|
wire _T_8662 = fifo_error_en[13] & _T_4511; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8664 = {32'h0,fifo_addr_13}; // @[Cat.scala 29:58]
|
|
wire _T_8677 = fifo_error_en[14] & _T_4518; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8679 = {32'h0,fifo_addr_14}; // @[Cat.scala 29:58]
|
|
wire _T_8692 = fifo_error_en[15] & _T_4525; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8694 = {32'h0,fifo_addr_15}; // @[Cat.scala 29:58]
|
|
wire _T_8707 = fifo_error_en[16] & _T_4532; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8709 = {32'h0,fifo_addr_16}; // @[Cat.scala 29:58]
|
|
wire _T_8722 = fifo_error_en[17] & _T_4539; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8724 = {32'h0,fifo_addr_17}; // @[Cat.scala 29:58]
|
|
wire _T_8737 = fifo_error_en[18] & _T_4546; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8739 = {32'h0,fifo_addr_18}; // @[Cat.scala 29:58]
|
|
wire _T_8752 = fifo_error_en[19] & _T_4553; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8754 = {32'h0,fifo_addr_19}; // @[Cat.scala 29:58]
|
|
wire _T_8767 = fifo_error_en[20] & _T_4560; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8769 = {32'h0,fifo_addr_20}; // @[Cat.scala 29:58]
|
|
wire _T_8782 = fifo_error_en[21] & _T_4567; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8784 = {32'h0,fifo_addr_21}; // @[Cat.scala 29:58]
|
|
wire _T_8797 = fifo_error_en[22] & _T_4574; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8799 = {32'h0,fifo_addr_22}; // @[Cat.scala 29:58]
|
|
wire _T_8812 = fifo_error_en[23] & _T_4581; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8814 = {32'h0,fifo_addr_23}; // @[Cat.scala 29:58]
|
|
wire _T_8827 = fifo_error_en[24] & _T_4588; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8829 = {32'h0,fifo_addr_24}; // @[Cat.scala 29:58]
|
|
wire _T_8842 = fifo_error_en[25] & _T_4595; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8844 = {32'h0,fifo_addr_25}; // @[Cat.scala 29:58]
|
|
wire _T_8857 = fifo_error_en[26] & _T_4602; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8859 = {32'h0,fifo_addr_26}; // @[Cat.scala 29:58]
|
|
wire _T_8872 = fifo_error_en[27] & _T_4609; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8874 = {32'h0,fifo_addr_27}; // @[Cat.scala 29:58]
|
|
wire _T_8887 = fifo_error_en[28] & _T_4616; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8889 = {32'h0,fifo_addr_28}; // @[Cat.scala 29:58]
|
|
wire _T_8902 = fifo_error_en[29] & _T_4623; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8904 = {32'h0,fifo_addr_29}; // @[Cat.scala 29:58]
|
|
wire _T_8917 = fifo_error_en[30] & _T_4630; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8919 = {32'h0,fifo_addr_30}; // @[Cat.scala 29:58]
|
|
wire _T_8932 = fifo_error_en[31] & _T_4637; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8934 = {32'h0,fifo_addr_31}; // @[Cat.scala 29:58]
|
|
wire _T_8947 = fifo_error_en[32] & _T_4644; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8949 = {32'h0,fifo_addr_32}; // @[Cat.scala 29:58]
|
|
wire _T_8962 = fifo_error_en[33] & _T_4651; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8964 = {32'h0,fifo_addr_33}; // @[Cat.scala 29:58]
|
|
wire _T_8977 = fifo_error_en[34] & _T_4658; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8979 = {32'h0,fifo_addr_34}; // @[Cat.scala 29:58]
|
|
wire _T_8992 = fifo_error_en[35] & _T_4665; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_8994 = {32'h0,fifo_addr_35}; // @[Cat.scala 29:58]
|
|
wire _T_9007 = fifo_error_en[36] & _T_4672; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9009 = {32'h0,fifo_addr_36}; // @[Cat.scala 29:58]
|
|
wire _T_9022 = fifo_error_en[37] & _T_4679; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9024 = {32'h0,fifo_addr_37}; // @[Cat.scala 29:58]
|
|
wire _T_9037 = fifo_error_en[38] & _T_4686; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9039 = {32'h0,fifo_addr_38}; // @[Cat.scala 29:58]
|
|
wire _T_9052 = fifo_error_en[39] & _T_4693; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9054 = {32'h0,fifo_addr_39}; // @[Cat.scala 29:58]
|
|
wire _T_9067 = fifo_error_en[40] & _T_4700; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9069 = {32'h0,fifo_addr_40}; // @[Cat.scala 29:58]
|
|
wire _T_9082 = fifo_error_en[41] & _T_4707; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9084 = {32'h0,fifo_addr_41}; // @[Cat.scala 29:58]
|
|
wire _T_9097 = fifo_error_en[42] & _T_4714; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9099 = {32'h0,fifo_addr_42}; // @[Cat.scala 29:58]
|
|
wire _T_9112 = fifo_error_en[43] & _T_4721; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9114 = {32'h0,fifo_addr_43}; // @[Cat.scala 29:58]
|
|
wire _T_9127 = fifo_error_en[44] & _T_4728; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9129 = {32'h0,fifo_addr_44}; // @[Cat.scala 29:58]
|
|
wire _T_9142 = fifo_error_en[45] & _T_4735; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9144 = {32'h0,fifo_addr_45}; // @[Cat.scala 29:58]
|
|
wire _T_9157 = fifo_error_en[46] & _T_4742; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9159 = {32'h0,fifo_addr_46}; // @[Cat.scala 29:58]
|
|
wire _T_9172 = fifo_error_en[47] & _T_4749; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9174 = {32'h0,fifo_addr_47}; // @[Cat.scala 29:58]
|
|
wire _T_9187 = fifo_error_en[48] & _T_4756; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9189 = {32'h0,fifo_addr_48}; // @[Cat.scala 29:58]
|
|
wire _T_9202 = fifo_error_en[49] & _T_4763; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9204 = {32'h0,fifo_addr_49}; // @[Cat.scala 29:58]
|
|
wire _T_9217 = fifo_error_en[50] & _T_4770; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9219 = {32'h0,fifo_addr_50}; // @[Cat.scala 29:58]
|
|
wire _T_9232 = fifo_error_en[51] & _T_4777; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9234 = {32'h0,fifo_addr_51}; // @[Cat.scala 29:58]
|
|
wire _T_9247 = fifo_error_en[52] & _T_4784; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9249 = {32'h0,fifo_addr_52}; // @[Cat.scala 29:58]
|
|
wire _T_9262 = fifo_error_en[53] & _T_4791; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9264 = {32'h0,fifo_addr_53}; // @[Cat.scala 29:58]
|
|
wire _T_9277 = fifo_error_en[54] & _T_4798; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9279 = {32'h0,fifo_addr_54}; // @[Cat.scala 29:58]
|
|
wire _T_9292 = fifo_error_en[55] & _T_4805; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9294 = {32'h0,fifo_addr_55}; // @[Cat.scala 29:58]
|
|
wire _T_9307 = fifo_error_en[56] & _T_4812; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9309 = {32'h0,fifo_addr_56}; // @[Cat.scala 29:58]
|
|
wire _T_9322 = fifo_error_en[57] & _T_4819; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9324 = {32'h0,fifo_addr_57}; // @[Cat.scala 29:58]
|
|
wire _T_9337 = fifo_error_en[58] & _T_4826; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9339 = {32'h0,fifo_addr_58}; // @[Cat.scala 29:58]
|
|
wire _T_9352 = fifo_error_en[59] & _T_4833; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9354 = {32'h0,fifo_addr_59}; // @[Cat.scala 29:58]
|
|
wire _T_9367 = fifo_error_en[60] & _T_4840; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9369 = {32'h0,fifo_addr_60}; // @[Cat.scala 29:58]
|
|
wire _T_9382 = fifo_error_en[61] & _T_4847; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9384 = {32'h0,fifo_addr_61}; // @[Cat.scala 29:58]
|
|
wire _T_9397 = fifo_error_en[62] & _T_4854; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9399 = {32'h0,fifo_addr_62}; // @[Cat.scala 29:58]
|
|
wire _T_9412 = fifo_error_en[63] & _T_4861; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9414 = {32'h0,fifo_addr_63}; // @[Cat.scala 29:58]
|
|
wire _T_9427 = fifo_error_en[64] & _T_4868; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9429 = {32'h0,fifo_addr_64}; // @[Cat.scala 29:58]
|
|
wire _T_9442 = fifo_error_en[65] & _T_4875; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9444 = {32'h0,fifo_addr_65}; // @[Cat.scala 29:58]
|
|
wire _T_9457 = fifo_error_en[66] & _T_4882; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9459 = {32'h0,fifo_addr_66}; // @[Cat.scala 29:58]
|
|
wire _T_9472 = fifo_error_en[67] & _T_4889; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9474 = {32'h0,fifo_addr_67}; // @[Cat.scala 29:58]
|
|
wire _T_9487 = fifo_error_en[68] & _T_4896; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9489 = {32'h0,fifo_addr_68}; // @[Cat.scala 29:58]
|
|
wire _T_9502 = fifo_error_en[69] & _T_4903; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9504 = {32'h0,fifo_addr_69}; // @[Cat.scala 29:58]
|
|
wire _T_9517 = fifo_error_en[70] & _T_4910; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9519 = {32'h0,fifo_addr_70}; // @[Cat.scala 29:58]
|
|
wire _T_9532 = fifo_error_en[71] & _T_4917; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9534 = {32'h0,fifo_addr_71}; // @[Cat.scala 29:58]
|
|
wire _T_9547 = fifo_error_en[72] & _T_4924; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9549 = {32'h0,fifo_addr_72}; // @[Cat.scala 29:58]
|
|
wire _T_9562 = fifo_error_en[73] & _T_4931; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9564 = {32'h0,fifo_addr_73}; // @[Cat.scala 29:58]
|
|
wire _T_9577 = fifo_error_en[74] & _T_4938; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9579 = {32'h0,fifo_addr_74}; // @[Cat.scala 29:58]
|
|
wire _T_9592 = fifo_error_en[75] & _T_4945; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9594 = {32'h0,fifo_addr_75}; // @[Cat.scala 29:58]
|
|
wire _T_9607 = fifo_error_en[76] & _T_4952; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9609 = {32'h0,fifo_addr_76}; // @[Cat.scala 29:58]
|
|
wire _T_9622 = fifo_error_en[77] & _T_4959; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9624 = {32'h0,fifo_addr_77}; // @[Cat.scala 29:58]
|
|
wire _T_9637 = fifo_error_en[78] & _T_4966; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9639 = {32'h0,fifo_addr_78}; // @[Cat.scala 29:58]
|
|
wire _T_9652 = fifo_error_en[79] & _T_4973; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9654 = {32'h0,fifo_addr_79}; // @[Cat.scala 29:58]
|
|
wire _T_9667 = fifo_error_en[80] & _T_4980; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9669 = {32'h0,fifo_addr_80}; // @[Cat.scala 29:58]
|
|
wire _T_9682 = fifo_error_en[81] & _T_4987; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9684 = {32'h0,fifo_addr_81}; // @[Cat.scala 29:58]
|
|
wire _T_9697 = fifo_error_en[82] & _T_4994; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9699 = {32'h0,fifo_addr_82}; // @[Cat.scala 29:58]
|
|
wire _T_9712 = fifo_error_en[83] & _T_5001; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9714 = {32'h0,fifo_addr_83}; // @[Cat.scala 29:58]
|
|
wire _T_9727 = fifo_error_en[84] & _T_5008; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9729 = {32'h0,fifo_addr_84}; // @[Cat.scala 29:58]
|
|
wire _T_9742 = fifo_error_en[85] & _T_5015; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9744 = {32'h0,fifo_addr_85}; // @[Cat.scala 29:58]
|
|
wire _T_9757 = fifo_error_en[86] & _T_5022; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9759 = {32'h0,fifo_addr_86}; // @[Cat.scala 29:58]
|
|
wire _T_9772 = fifo_error_en[87] & _T_5029; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9774 = {32'h0,fifo_addr_87}; // @[Cat.scala 29:58]
|
|
wire _T_9787 = fifo_error_en[88] & _T_5036; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9789 = {32'h0,fifo_addr_88}; // @[Cat.scala 29:58]
|
|
wire _T_9802 = fifo_error_en[89] & _T_5043; // @[dma_ctrl.scala 140:80]
|
|
wire [63:0] _T_9804 = {32'h0,fifo_addr_89}; // @[Cat.scala 29:58]
|
|
wire _T_9817 = fifo_cmd_en[0] | fifo_valid[0]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9819 = ~fifo_reset[0]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9824 = fifo_cmd_en[1] | fifo_valid[1]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9826 = ~fifo_reset[1]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9831 = fifo_cmd_en[2] | fifo_valid[2]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9833 = ~fifo_reset[2]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9838 = fifo_cmd_en[3] | fifo_valid[3]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9840 = ~fifo_reset[3]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9845 = fifo_cmd_en[4] | fifo_valid[4]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9847 = ~fifo_reset[4]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9852 = fifo_cmd_en[5] | fifo_valid[5]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9854 = ~fifo_reset[5]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9859 = fifo_cmd_en[6] | fifo_valid[6]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9861 = ~fifo_reset[6]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9866 = fifo_cmd_en[7] | fifo_valid[7]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9868 = ~fifo_reset[7]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9873 = fifo_cmd_en[8] | fifo_valid[8]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9875 = ~fifo_reset[8]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9880 = fifo_cmd_en[9] | fifo_valid[9]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9882 = ~fifo_reset[9]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9887 = fifo_cmd_en[10] | fifo_valid[10]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9889 = ~fifo_reset[10]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9894 = fifo_cmd_en[11] | fifo_valid[11]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9896 = ~fifo_reset[11]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9901 = fifo_cmd_en[12] | fifo_valid[12]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9903 = ~fifo_reset[12]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9908 = fifo_cmd_en[13] | fifo_valid[13]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9910 = ~fifo_reset[13]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9915 = fifo_cmd_en[14] | fifo_valid[14]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9917 = ~fifo_reset[14]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9922 = fifo_cmd_en[15] | fifo_valid[15]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9924 = ~fifo_reset[15]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9929 = fifo_cmd_en[16] | fifo_valid[16]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9931 = ~fifo_reset[16]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9936 = fifo_cmd_en[17] | fifo_valid[17]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9938 = ~fifo_reset[17]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9943 = fifo_cmd_en[18] | fifo_valid[18]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9945 = ~fifo_reset[18]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9950 = fifo_cmd_en[19] | fifo_valid[19]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9952 = ~fifo_reset[19]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9957 = fifo_cmd_en[20] | fifo_valid[20]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9959 = ~fifo_reset[20]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9964 = fifo_cmd_en[21] | fifo_valid[21]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9966 = ~fifo_reset[21]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9971 = fifo_cmd_en[22] | fifo_valid[22]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9973 = ~fifo_reset[22]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9978 = fifo_cmd_en[23] | fifo_valid[23]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9980 = ~fifo_reset[23]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9985 = fifo_cmd_en[24] | fifo_valid[24]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9987 = ~fifo_reset[24]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9992 = fifo_cmd_en[25] | fifo_valid[25]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_9994 = ~fifo_reset[25]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_9999 = fifo_cmd_en[26] | fifo_valid[26]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10001 = ~fifo_reset[26]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10006 = fifo_cmd_en[27] | fifo_valid[27]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10008 = ~fifo_reset[27]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10013 = fifo_cmd_en[28] | fifo_valid[28]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10015 = ~fifo_reset[28]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10020 = fifo_cmd_en[29] | fifo_valid[29]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10022 = ~fifo_reset[29]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10027 = fifo_cmd_en[30] | fifo_valid[30]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10029 = ~fifo_reset[30]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10034 = fifo_cmd_en[31] | fifo_valid[31]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10036 = ~fifo_reset[31]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10041 = fifo_cmd_en[32] | fifo_valid[32]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10043 = ~fifo_reset[32]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10048 = fifo_cmd_en[33] | fifo_valid[33]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10050 = ~fifo_reset[33]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10055 = fifo_cmd_en[34] | fifo_valid[34]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10057 = ~fifo_reset[34]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10062 = fifo_cmd_en[35] | fifo_valid[35]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10064 = ~fifo_reset[35]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10069 = fifo_cmd_en[36] | fifo_valid[36]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10071 = ~fifo_reset[36]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10076 = fifo_cmd_en[37] | fifo_valid[37]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10078 = ~fifo_reset[37]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10083 = fifo_cmd_en[38] | fifo_valid[38]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10085 = ~fifo_reset[38]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10090 = fifo_cmd_en[39] | fifo_valid[39]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10092 = ~fifo_reset[39]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10097 = fifo_cmd_en[40] | fifo_valid[40]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10099 = ~fifo_reset[40]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10104 = fifo_cmd_en[41] | fifo_valid[41]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10106 = ~fifo_reset[41]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10111 = fifo_cmd_en[42] | fifo_valid[42]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10113 = ~fifo_reset[42]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10118 = fifo_cmd_en[43] | fifo_valid[43]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10120 = ~fifo_reset[43]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10125 = fifo_cmd_en[44] | fifo_valid[44]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10127 = ~fifo_reset[44]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10132 = fifo_cmd_en[45] | fifo_valid[45]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10134 = ~fifo_reset[45]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10139 = fifo_cmd_en[46] | fifo_valid[46]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10141 = ~fifo_reset[46]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10146 = fifo_cmd_en[47] | fifo_valid[47]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10148 = ~fifo_reset[47]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10153 = fifo_cmd_en[48] | fifo_valid[48]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10155 = ~fifo_reset[48]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10160 = fifo_cmd_en[49] | fifo_valid[49]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10162 = ~fifo_reset[49]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10167 = fifo_cmd_en[50] | fifo_valid[50]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10169 = ~fifo_reset[50]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10174 = fifo_cmd_en[51] | fifo_valid[51]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10176 = ~fifo_reset[51]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10181 = fifo_cmd_en[52] | fifo_valid[52]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10183 = ~fifo_reset[52]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10188 = fifo_cmd_en[53] | fifo_valid[53]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10190 = ~fifo_reset[53]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10195 = fifo_cmd_en[54] | fifo_valid[54]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10197 = ~fifo_reset[54]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10202 = fifo_cmd_en[55] | fifo_valid[55]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10204 = ~fifo_reset[55]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10209 = fifo_cmd_en[56] | fifo_valid[56]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10211 = ~fifo_reset[56]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10216 = fifo_cmd_en[57] | fifo_valid[57]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10218 = ~fifo_reset[57]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10223 = fifo_cmd_en[58] | fifo_valid[58]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10225 = ~fifo_reset[58]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10230 = fifo_cmd_en[59] | fifo_valid[59]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10232 = ~fifo_reset[59]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10237 = fifo_cmd_en[60] | fifo_valid[60]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10239 = ~fifo_reset[60]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10244 = fifo_cmd_en[61] | fifo_valid[61]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10246 = ~fifo_reset[61]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10251 = fifo_cmd_en[62] | fifo_valid[62]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10253 = ~fifo_reset[62]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10258 = fifo_cmd_en[63] | fifo_valid[63]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10260 = ~fifo_reset[63]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10265 = fifo_cmd_en[64] | fifo_valid[64]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10267 = ~fifo_reset[64]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10272 = fifo_cmd_en[65] | fifo_valid[65]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10274 = ~fifo_reset[65]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10279 = fifo_cmd_en[66] | fifo_valid[66]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10281 = ~fifo_reset[66]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10286 = fifo_cmd_en[67] | fifo_valid[67]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10288 = ~fifo_reset[67]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10293 = fifo_cmd_en[68] | fifo_valid[68]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10295 = ~fifo_reset[68]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10300 = fifo_cmd_en[69] | fifo_valid[69]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10302 = ~fifo_reset[69]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10307 = fifo_cmd_en[70] | fifo_valid[70]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10309 = ~fifo_reset[70]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10314 = fifo_cmd_en[71] | fifo_valid[71]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10316 = ~fifo_reset[71]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10321 = fifo_cmd_en[72] | fifo_valid[72]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10323 = ~fifo_reset[72]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10328 = fifo_cmd_en[73] | fifo_valid[73]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10330 = ~fifo_reset[73]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10335 = fifo_cmd_en[74] | fifo_valid[74]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10337 = ~fifo_reset[74]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10342 = fifo_cmd_en[75] | fifo_valid[75]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10344 = ~fifo_reset[75]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10349 = fifo_cmd_en[76] | fifo_valid[76]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10351 = ~fifo_reset[76]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10356 = fifo_cmd_en[77] | fifo_valid[77]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10358 = ~fifo_reset[77]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10363 = fifo_cmd_en[78] | fifo_valid[78]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10365 = ~fifo_reset[78]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10370 = fifo_cmd_en[79] | fifo_valid[79]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10372 = ~fifo_reset[79]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10377 = fifo_cmd_en[80] | fifo_valid[80]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10379 = ~fifo_reset[80]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10384 = fifo_cmd_en[81] | fifo_valid[81]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10386 = ~fifo_reset[81]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10391 = fifo_cmd_en[82] | fifo_valid[82]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10393 = ~fifo_reset[82]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10398 = fifo_cmd_en[83] | fifo_valid[83]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10400 = ~fifo_reset[83]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10405 = fifo_cmd_en[84] | fifo_valid[84]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10407 = ~fifo_reset[84]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10412 = fifo_cmd_en[85] | fifo_valid[85]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10414 = ~fifo_reset[85]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10419 = fifo_cmd_en[86] | fifo_valid[86]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10421 = ~fifo_reset[86]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10426 = fifo_cmd_en[87] | fifo_valid[87]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10428 = ~fifo_reset[87]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10433 = fifo_cmd_en[88] | fifo_valid[88]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10435 = ~fifo_reset[88]; // @[dma_ctrl.scala 142:125]
|
|
wire _T_10440 = fifo_cmd_en[89] | fifo_valid[89]; // @[dma_ctrl.scala 142:86]
|
|
wire _T_10442 = ~fifo_reset[89]; // @[dma_ctrl.scala 142:125]
|
|
wire [1:0] _T_10536 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10540 = _T_9819 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10545 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10549 = _T_9826 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10554 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10558 = _T_9833 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10563 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10567 = _T_9840 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10572 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10576 = _T_9847 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10581 = fifo_error_en[5] ? fifo_error_in_5 : fifo_error_5; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10585 = _T_9854 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10590 = fifo_error_en[6] ? fifo_error_in_6 : fifo_error_6; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10594 = _T_9861 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10599 = fifo_error_en[7] ? fifo_error_in_7 : fifo_error_7; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10603 = _T_9868 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10608 = fifo_error_en[8] ? fifo_error_in_8 : fifo_error_8; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10612 = _T_9875 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10617 = fifo_error_en[9] ? fifo_error_in_9 : fifo_error_9; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10621 = _T_9882 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10626 = fifo_error_en[10] ? fifo_error_in_10 : fifo_error_10; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10630 = _T_9889 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10635 = fifo_error_en[11] ? fifo_error_in_11 : fifo_error_11; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10639 = _T_9896 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10644 = fifo_error_en[12] ? fifo_error_in_12 : fifo_error_12; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10648 = _T_9903 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10653 = fifo_error_en[13] ? fifo_error_in_13 : fifo_error_13; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10657 = _T_9910 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10662 = fifo_error_en[14] ? fifo_error_in_14 : fifo_error_14; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10666 = _T_9917 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10671 = fifo_error_en[15] ? fifo_error_in_15 : fifo_error_15; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10675 = _T_9924 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10680 = fifo_error_en[16] ? fifo_error_in_16 : fifo_error_16; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10684 = _T_9931 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10689 = fifo_error_en[17] ? fifo_error_in_17 : fifo_error_17; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10693 = _T_9938 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10698 = fifo_error_en[18] ? fifo_error_in_18 : fifo_error_18; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10702 = _T_9945 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10707 = fifo_error_en[19] ? fifo_error_in_19 : fifo_error_19; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10711 = _T_9952 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10716 = fifo_error_en[20] ? fifo_error_in_20 : fifo_error_20; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10720 = _T_9959 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10725 = fifo_error_en[21] ? fifo_error_in_21 : fifo_error_21; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10729 = _T_9966 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10734 = fifo_error_en[22] ? fifo_error_in_22 : fifo_error_22; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10738 = _T_9973 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10743 = fifo_error_en[23] ? fifo_error_in_23 : fifo_error_23; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10747 = _T_9980 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10752 = fifo_error_en[24] ? fifo_error_in_24 : fifo_error_24; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10756 = _T_9987 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10761 = fifo_error_en[25] ? fifo_error_in_25 : fifo_error_25; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10765 = _T_9994 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10770 = fifo_error_en[26] ? fifo_error_in_26 : fifo_error_26; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10774 = _T_10001 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10779 = fifo_error_en[27] ? fifo_error_in_27 : fifo_error_27; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10783 = _T_10008 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10788 = fifo_error_en[28] ? fifo_error_in_28 : fifo_error_28; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10792 = _T_10015 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10797 = fifo_error_en[29] ? fifo_error_in_29 : fifo_error_29; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10801 = _T_10022 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10806 = fifo_error_en[30] ? fifo_error_in_30 : fifo_error_30; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10810 = _T_10029 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10815 = fifo_error_en[31] ? fifo_error_in_31 : fifo_error_31; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10819 = _T_10036 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10824 = fifo_error_en[32] ? fifo_error_in_32 : fifo_error_32; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10828 = _T_10043 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10833 = fifo_error_en[33] ? fifo_error_in_33 : fifo_error_33; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10837 = _T_10050 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10842 = fifo_error_en[34] ? fifo_error_in_34 : fifo_error_34; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10846 = _T_10057 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10851 = fifo_error_en[35] ? fifo_error_in_35 : fifo_error_35; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10855 = _T_10064 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10860 = fifo_error_en[36] ? fifo_error_in_36 : fifo_error_36; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10864 = _T_10071 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10869 = fifo_error_en[37] ? fifo_error_in_37 : fifo_error_37; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10873 = _T_10078 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10878 = fifo_error_en[38] ? fifo_error_in_38 : fifo_error_38; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10882 = _T_10085 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10887 = fifo_error_en[39] ? fifo_error_in_39 : fifo_error_39; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10891 = _T_10092 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10896 = fifo_error_en[40] ? fifo_error_in_40 : fifo_error_40; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10900 = _T_10099 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10905 = fifo_error_en[41] ? fifo_error_in_41 : fifo_error_41; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10909 = _T_10106 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10914 = fifo_error_en[42] ? fifo_error_in_42 : fifo_error_42; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10918 = _T_10113 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10923 = fifo_error_en[43] ? fifo_error_in_43 : fifo_error_43; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10927 = _T_10120 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10932 = fifo_error_en[44] ? fifo_error_in_44 : fifo_error_44; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10936 = _T_10127 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10941 = fifo_error_en[45] ? fifo_error_in_45 : fifo_error_45; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10945 = _T_10134 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10950 = fifo_error_en[46] ? fifo_error_in_46 : fifo_error_46; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10954 = _T_10141 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10959 = fifo_error_en[47] ? fifo_error_in_47 : fifo_error_47; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10963 = _T_10148 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10968 = fifo_error_en[48] ? fifo_error_in_48 : fifo_error_48; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10972 = _T_10155 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10977 = fifo_error_en[49] ? fifo_error_in_49 : fifo_error_49; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10981 = _T_10162 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10986 = fifo_error_en[50] ? fifo_error_in_50 : fifo_error_50; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10990 = _T_10169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_10995 = fifo_error_en[51] ? fifo_error_in_51 : fifo_error_51; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_10999 = _T_10176 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11004 = fifo_error_en[52] ? fifo_error_in_52 : fifo_error_52; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11008 = _T_10183 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11013 = fifo_error_en[53] ? fifo_error_in_53 : fifo_error_53; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11017 = _T_10190 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11022 = fifo_error_en[54] ? fifo_error_in_54 : fifo_error_54; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11026 = _T_10197 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11031 = fifo_error_en[55] ? fifo_error_in_55 : fifo_error_55; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11035 = _T_10204 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11040 = fifo_error_en[56] ? fifo_error_in_56 : fifo_error_56; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11044 = _T_10211 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11049 = fifo_error_en[57] ? fifo_error_in_57 : fifo_error_57; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11053 = _T_10218 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11058 = fifo_error_en[58] ? fifo_error_in_58 : fifo_error_58; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11062 = _T_10225 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11067 = fifo_error_en[59] ? fifo_error_in_59 : fifo_error_59; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11071 = _T_10232 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11076 = fifo_error_en[60] ? fifo_error_in_60 : fifo_error_60; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11080 = _T_10239 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11085 = fifo_error_en[61] ? fifo_error_in_61 : fifo_error_61; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11089 = _T_10246 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11094 = fifo_error_en[62] ? fifo_error_in_62 : fifo_error_62; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11098 = _T_10253 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11103 = fifo_error_en[63] ? fifo_error_in_63 : fifo_error_63; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11107 = _T_10260 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11112 = fifo_error_en[64] ? fifo_error_in_64 : fifo_error_64; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11116 = _T_10267 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11121 = fifo_error_en[65] ? fifo_error_in_65 : fifo_error_65; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11125 = _T_10274 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11130 = fifo_error_en[66] ? fifo_error_in_66 : fifo_error_66; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11134 = _T_10281 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11139 = fifo_error_en[67] ? fifo_error_in_67 : fifo_error_67; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11143 = _T_10288 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11148 = fifo_error_en[68] ? fifo_error_in_68 : fifo_error_68; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11152 = _T_10295 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11157 = fifo_error_en[69] ? fifo_error_in_69 : fifo_error_69; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11161 = _T_10302 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11166 = fifo_error_en[70] ? fifo_error_in_70 : fifo_error_70; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11170 = _T_10309 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11175 = fifo_error_en[71] ? fifo_error_in_71 : fifo_error_71; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11179 = _T_10316 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11184 = fifo_error_en[72] ? fifo_error_in_72 : fifo_error_72; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11188 = _T_10323 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11193 = fifo_error_en[73] ? fifo_error_in_73 : fifo_error_73; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11197 = _T_10330 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11202 = fifo_error_en[74] ? fifo_error_in_74 : fifo_error_74; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11206 = _T_10337 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11211 = fifo_error_en[75] ? fifo_error_in_75 : fifo_error_75; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11215 = _T_10344 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11220 = fifo_error_en[76] ? fifo_error_in_76 : fifo_error_76; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11224 = _T_10351 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11229 = fifo_error_en[77] ? fifo_error_in_77 : fifo_error_77; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11233 = _T_10358 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11238 = fifo_error_en[78] ? fifo_error_in_78 : fifo_error_78; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11242 = _T_10365 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11247 = fifo_error_en[79] ? fifo_error_in_79 : fifo_error_79; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11251 = _T_10372 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11256 = fifo_error_en[80] ? fifo_error_in_80 : fifo_error_80; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11260 = _T_10379 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11265 = fifo_error_en[81] ? fifo_error_in_81 : fifo_error_81; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11269 = _T_10386 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11274 = fifo_error_en[82] ? fifo_error_in_82 : fifo_error_82; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11278 = _T_10393 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11283 = fifo_error_en[83] ? fifo_error_in_83 : fifo_error_83; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11287 = _T_10400 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11292 = fifo_error_en[84] ? fifo_error_in_84 : fifo_error_84; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11296 = _T_10407 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11301 = fifo_error_en[85] ? fifo_error_in_85 : fifo_error_85; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11305 = _T_10414 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11310 = fifo_error_en[86] ? fifo_error_in_86 : fifo_error_86; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11314 = _T_10421 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11319 = fifo_error_en[87] ? fifo_error_in_87 : fifo_error_87; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11323 = _T_10428 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11328 = fifo_error_en[88] ? fifo_error_in_88 : fifo_error_88; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11332 = _T_10435 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
wire [1:0] _T_11337 = fifo_error_en[89] ? fifo_error_in_89 : fifo_error_89; // @[dma_ctrl.scala 143:89]
|
|
wire [1:0] _T_11341 = _T_10442 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
|
reg _T_12692; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12685; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12678; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12671; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12664; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12657; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12650; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12643; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12636; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12629; // @[dma_ctrl.scala 147:88]
|
|
wire [9:0] _T_12701 = {_T_12692,_T_12685,_T_12678,_T_12671,_T_12664,_T_12657,_T_12650,_T_12643,_T_12636,_T_12629}; // @[Cat.scala 29:58]
|
|
reg _T_12622; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12615; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12608; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12601; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12594; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12587; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12580; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12573; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12566; // @[dma_ctrl.scala 147:88]
|
|
wire [18:0] _T_12710 = {_T_12701,_T_12622,_T_12615,_T_12608,_T_12601,_T_12594,_T_12587,_T_12580,_T_12573,_T_12566}; // @[Cat.scala 29:58]
|
|
reg _T_12559; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12552; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12545; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12538; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12531; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12524; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12517; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12510; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12503; // @[dma_ctrl.scala 147:88]
|
|
wire [27:0] _T_12719 = {_T_12710,_T_12559,_T_12552,_T_12545,_T_12538,_T_12531,_T_12524,_T_12517,_T_12510,_T_12503}; // @[Cat.scala 29:58]
|
|
reg _T_12496; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12489; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12482; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12475; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12468; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12461; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12454; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12447; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12440; // @[dma_ctrl.scala 147:88]
|
|
wire [36:0] _T_12728 = {_T_12719,_T_12496,_T_12489,_T_12482,_T_12475,_T_12468,_T_12461,_T_12454,_T_12447,_T_12440}; // @[Cat.scala 29:58]
|
|
reg _T_12433; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12426; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12419; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12412; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12405; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12398; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12391; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12384; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12377; // @[dma_ctrl.scala 147:88]
|
|
wire [45:0] _T_12737 = {_T_12728,_T_12433,_T_12426,_T_12419,_T_12412,_T_12405,_T_12398,_T_12391,_T_12384,_T_12377}; // @[Cat.scala 29:58]
|
|
reg _T_12370; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12363; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12356; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12349; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12342; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12335; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12328; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12321; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12314; // @[dma_ctrl.scala 147:88]
|
|
wire [54:0] _T_12746 = {_T_12737,_T_12370,_T_12363,_T_12356,_T_12349,_T_12342,_T_12335,_T_12328,_T_12321,_T_12314}; // @[Cat.scala 29:58]
|
|
reg _T_12307; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12300; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12293; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12286; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12279; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12272; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12265; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12258; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12251; // @[dma_ctrl.scala 147:88]
|
|
wire [63:0] _T_12755 = {_T_12746,_T_12307,_T_12300,_T_12293,_T_12286,_T_12279,_T_12272,_T_12265,_T_12258,_T_12251}; // @[Cat.scala 29:58]
|
|
reg _T_12244; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12237; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12230; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12223; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12216; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12209; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12202; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12195; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12188; // @[dma_ctrl.scala 147:88]
|
|
wire [72:0] _T_12764 = {_T_12755,_T_12244,_T_12237,_T_12230,_T_12223,_T_12216,_T_12209,_T_12202,_T_12195,_T_12188}; // @[Cat.scala 29:58]
|
|
reg _T_12181; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12174; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12167; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12160; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12153; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12146; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12139; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12132; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12125; // @[dma_ctrl.scala 147:88]
|
|
wire [81:0] _T_12773 = {_T_12764,_T_12181,_T_12174,_T_12167,_T_12160,_T_12153,_T_12146,_T_12139,_T_12132,_T_12125}; // @[Cat.scala 29:58]
|
|
reg _T_12118; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12111; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12104; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12097; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12090; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12083; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12076; // @[dma_ctrl.scala 147:88]
|
|
reg _T_12069; // @[dma_ctrl.scala 147:88]
|
|
wire [89:0] fifo_rpend = {_T_12773,_T_12118,_T_12111,_T_12104,_T_12097,_T_12090,_T_12083,_T_12076,_T_12069}; // @[Cat.scala 29:58]
|
|
wire _T_12065 = fifo_pend_en[0] | fifo_rpend[0]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12072 = fifo_pend_en[1] | fifo_rpend[1]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12079 = fifo_pend_en[2] | fifo_rpend[2]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12086 = fifo_pend_en[3] | fifo_rpend[3]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12093 = fifo_pend_en[4] | fifo_rpend[4]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12100 = fifo_pend_en[5] | fifo_rpend[5]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12107 = fifo_pend_en[6] | fifo_rpend[6]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12114 = fifo_pend_en[7] | fifo_rpend[7]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12121 = fifo_pend_en[8] | fifo_rpend[8]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12128 = fifo_pend_en[9] | fifo_rpend[9]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12135 = fifo_pend_en[10] | fifo_rpend[10]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12142 = fifo_pend_en[11] | fifo_rpend[11]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12149 = fifo_pend_en[12] | fifo_rpend[12]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12156 = fifo_pend_en[13] | fifo_rpend[13]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12163 = fifo_pend_en[14] | fifo_rpend[14]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12170 = fifo_pend_en[15] | fifo_rpend[15]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12177 = fifo_pend_en[16] | fifo_rpend[16]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12184 = fifo_pend_en[17] | fifo_rpend[17]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12191 = fifo_pend_en[18] | fifo_rpend[18]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12198 = fifo_pend_en[19] | fifo_rpend[19]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12205 = fifo_pend_en[20] | fifo_rpend[20]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12212 = fifo_pend_en[21] | fifo_rpend[21]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12219 = fifo_pend_en[22] | fifo_rpend[22]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12226 = fifo_pend_en[23] | fifo_rpend[23]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12233 = fifo_pend_en[24] | fifo_rpend[24]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12240 = fifo_pend_en[25] | fifo_rpend[25]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12247 = fifo_pend_en[26] | fifo_rpend[26]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12254 = fifo_pend_en[27] | fifo_rpend[27]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12261 = fifo_pend_en[28] | fifo_rpend[28]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12268 = fifo_pend_en[29] | fifo_rpend[29]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12275 = fifo_pend_en[30] | fifo_rpend[30]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12282 = fifo_pend_en[31] | fifo_rpend[31]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12289 = fifo_pend_en[32] | fifo_rpend[32]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12296 = fifo_pend_en[33] | fifo_rpend[33]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12303 = fifo_pend_en[34] | fifo_rpend[34]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12310 = fifo_pend_en[35] | fifo_rpend[35]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12317 = fifo_pend_en[36] | fifo_rpend[36]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12324 = fifo_pend_en[37] | fifo_rpend[37]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12331 = fifo_pend_en[38] | fifo_rpend[38]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12338 = fifo_pend_en[39] | fifo_rpend[39]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12345 = fifo_pend_en[40] | fifo_rpend[40]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12352 = fifo_pend_en[41] | fifo_rpend[41]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12359 = fifo_pend_en[42] | fifo_rpend[42]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12366 = fifo_pend_en[43] | fifo_rpend[43]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12373 = fifo_pend_en[44] | fifo_rpend[44]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12380 = fifo_pend_en[45] | fifo_rpend[45]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12387 = fifo_pend_en[46] | fifo_rpend[46]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12394 = fifo_pend_en[47] | fifo_rpend[47]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12401 = fifo_pend_en[48] | fifo_rpend[48]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12408 = fifo_pend_en[49] | fifo_rpend[49]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12415 = fifo_pend_en[50] | fifo_rpend[50]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12422 = fifo_pend_en[51] | fifo_rpend[51]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12429 = fifo_pend_en[52] | fifo_rpend[52]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12436 = fifo_pend_en[53] | fifo_rpend[53]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12443 = fifo_pend_en[54] | fifo_rpend[54]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12450 = fifo_pend_en[55] | fifo_rpend[55]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12457 = fifo_pend_en[56] | fifo_rpend[56]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12464 = fifo_pend_en[57] | fifo_rpend[57]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12471 = fifo_pend_en[58] | fifo_rpend[58]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12478 = fifo_pend_en[59] | fifo_rpend[59]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12485 = fifo_pend_en[60] | fifo_rpend[60]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12492 = fifo_pend_en[61] | fifo_rpend[61]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12499 = fifo_pend_en[62] | fifo_rpend[62]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12506 = fifo_pend_en[63] | fifo_rpend[63]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12513 = fifo_pend_en[64] | fifo_rpend[64]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12520 = fifo_pend_en[65] | fifo_rpend[65]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12527 = fifo_pend_en[66] | fifo_rpend[66]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12534 = fifo_pend_en[67] | fifo_rpend[67]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12541 = fifo_pend_en[68] | fifo_rpend[68]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12548 = fifo_pend_en[69] | fifo_rpend[69]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12555 = fifo_pend_en[70] | fifo_rpend[70]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12562 = fifo_pend_en[71] | fifo_rpend[71]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12569 = fifo_pend_en[72] | fifo_rpend[72]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12576 = fifo_pend_en[73] | fifo_rpend[73]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12583 = fifo_pend_en[74] | fifo_rpend[74]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12590 = fifo_pend_en[75] | fifo_rpend[75]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12597 = fifo_pend_en[76] | fifo_rpend[76]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12604 = fifo_pend_en[77] | fifo_rpend[77]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12611 = fifo_pend_en[78] | fifo_rpend[78]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12618 = fifo_pend_en[79] | fifo_rpend[79]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12625 = fifo_pend_en[80] | fifo_rpend[80]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12632 = fifo_pend_en[81] | fifo_rpend[81]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12639 = fifo_pend_en[82] | fifo_rpend[82]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12646 = fifo_pend_en[83] | fifo_rpend[83]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12653 = fifo_pend_en[84] | fifo_rpend[84]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12660 = fifo_pend_en[85] | fifo_rpend[85]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12667 = fifo_pend_en[86] | fifo_rpend[86]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12674 = fifo_pend_en[87] | fifo_rpend[87]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12681 = fifo_pend_en[88] | fifo_rpend[88]; // @[dma_ctrl.scala 147:92]
|
|
wire _T_12688 = fifo_pend_en[89] | fifo_rpend[89]; // @[dma_ctrl.scala 147:92]
|
|
reg _T_14130; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14123; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14116; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14109; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14102; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14095; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14088; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14081; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14074; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14067; // @[dma_ctrl.scala 150:88]
|
|
wire [9:0] _T_14139 = {_T_14130,_T_14123,_T_14116,_T_14109,_T_14102,_T_14095,_T_14088,_T_14081,_T_14074,_T_14067}; // @[Cat.scala 29:58]
|
|
reg _T_14060; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14053; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14046; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14039; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14032; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14025; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14018; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14011; // @[dma_ctrl.scala 150:88]
|
|
reg _T_14004; // @[dma_ctrl.scala 150:88]
|
|
wire [18:0] _T_14148 = {_T_14139,_T_14060,_T_14053,_T_14046,_T_14039,_T_14032,_T_14025,_T_14018,_T_14011,_T_14004}; // @[Cat.scala 29:58]
|
|
reg _T_13997; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13990; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13983; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13976; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13969; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13962; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13955; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13948; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13941; // @[dma_ctrl.scala 150:88]
|
|
wire [27:0] _T_14157 = {_T_14148,_T_13997,_T_13990,_T_13983,_T_13976,_T_13969,_T_13962,_T_13955,_T_13948,_T_13941}; // @[Cat.scala 29:58]
|
|
reg _T_13934; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13927; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13920; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13913; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13906; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13899; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13892; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13885; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13878; // @[dma_ctrl.scala 150:88]
|
|
wire [36:0] _T_14166 = {_T_14157,_T_13934,_T_13927,_T_13920,_T_13913,_T_13906,_T_13899,_T_13892,_T_13885,_T_13878}; // @[Cat.scala 29:58]
|
|
reg _T_13871; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13864; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13857; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13850; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13843; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13836; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13829; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13822; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13815; // @[dma_ctrl.scala 150:88]
|
|
wire [45:0] _T_14175 = {_T_14166,_T_13871,_T_13864,_T_13857,_T_13850,_T_13843,_T_13836,_T_13829,_T_13822,_T_13815}; // @[Cat.scala 29:58]
|
|
reg _T_13808; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13801; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13794; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13787; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13780; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13773; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13766; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13759; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13752; // @[dma_ctrl.scala 150:88]
|
|
wire [54:0] _T_14184 = {_T_14175,_T_13808,_T_13801,_T_13794,_T_13787,_T_13780,_T_13773,_T_13766,_T_13759,_T_13752}; // @[Cat.scala 29:58]
|
|
reg _T_13745; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13738; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13731; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13724; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13717; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13710; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13703; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13696; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13689; // @[dma_ctrl.scala 150:88]
|
|
wire [63:0] _T_14193 = {_T_14184,_T_13745,_T_13738,_T_13731,_T_13724,_T_13717,_T_13710,_T_13703,_T_13696,_T_13689}; // @[Cat.scala 29:58]
|
|
reg _T_13682; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13675; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13668; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13661; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13654; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13647; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13640; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13633; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13626; // @[dma_ctrl.scala 150:88]
|
|
wire [72:0] _T_14202 = {_T_14193,_T_13682,_T_13675,_T_13668,_T_13661,_T_13654,_T_13647,_T_13640,_T_13633,_T_13626}; // @[Cat.scala 29:58]
|
|
reg _T_13619; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13612; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13605; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13598; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13591; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13584; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13577; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13570; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13563; // @[dma_ctrl.scala 150:88]
|
|
wire [81:0] _T_14211 = {_T_14202,_T_13619,_T_13612,_T_13605,_T_13598,_T_13591,_T_13584,_T_13577,_T_13570,_T_13563}; // @[Cat.scala 29:58]
|
|
reg _T_13556; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13549; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13542; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13535; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13528; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13521; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13514; // @[dma_ctrl.scala 150:88]
|
|
reg _T_13507; // @[dma_ctrl.scala 150:88]
|
|
wire [89:0] fifo_done_bus = {_T_14211,_T_13556,_T_13549,_T_13542,_T_13535,_T_13528,_T_13521,_T_13514,_T_13507}; // @[Cat.scala 29:58]
|
|
wire _T_13503 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13510 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13517 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13524 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13531 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13538 = fifo_done_bus_en[5] | fifo_done_bus[5]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13545 = fifo_done_bus_en[6] | fifo_done_bus[6]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13552 = fifo_done_bus_en[7] | fifo_done_bus[7]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13559 = fifo_done_bus_en[8] | fifo_done_bus[8]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13566 = fifo_done_bus_en[9] | fifo_done_bus[9]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13573 = fifo_done_bus_en[10] | fifo_done_bus[10]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13580 = fifo_done_bus_en[11] | fifo_done_bus[11]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13587 = fifo_done_bus_en[12] | fifo_done_bus[12]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13594 = fifo_done_bus_en[13] | fifo_done_bus[13]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13601 = fifo_done_bus_en[14] | fifo_done_bus[14]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13608 = fifo_done_bus_en[15] | fifo_done_bus[15]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13615 = fifo_done_bus_en[16] | fifo_done_bus[16]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13622 = fifo_done_bus_en[17] | fifo_done_bus[17]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13629 = fifo_done_bus_en[18] | fifo_done_bus[18]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13636 = fifo_done_bus_en[19] | fifo_done_bus[19]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13643 = fifo_done_bus_en[20] | fifo_done_bus[20]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13650 = fifo_done_bus_en[21] | fifo_done_bus[21]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13657 = fifo_done_bus_en[22] | fifo_done_bus[22]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13664 = fifo_done_bus_en[23] | fifo_done_bus[23]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13671 = fifo_done_bus_en[24] | fifo_done_bus[24]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13678 = fifo_done_bus_en[25] | fifo_done_bus[25]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13685 = fifo_done_bus_en[26] | fifo_done_bus[26]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13692 = fifo_done_bus_en[27] | fifo_done_bus[27]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13699 = fifo_done_bus_en[28] | fifo_done_bus[28]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13706 = fifo_done_bus_en[29] | fifo_done_bus[29]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13713 = fifo_done_bus_en[30] | fifo_done_bus[30]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13720 = fifo_done_bus_en[31] | fifo_done_bus[31]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13727 = fifo_done_bus_en[32] | fifo_done_bus[32]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13734 = fifo_done_bus_en[33] | fifo_done_bus[33]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13741 = fifo_done_bus_en[34] | fifo_done_bus[34]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13748 = fifo_done_bus_en[35] | fifo_done_bus[35]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13755 = fifo_done_bus_en[36] | fifo_done_bus[36]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13762 = fifo_done_bus_en[37] | fifo_done_bus[37]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13769 = fifo_done_bus_en[38] | fifo_done_bus[38]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13776 = fifo_done_bus_en[39] | fifo_done_bus[39]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13783 = fifo_done_bus_en[40] | fifo_done_bus[40]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13790 = fifo_done_bus_en[41] | fifo_done_bus[41]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13797 = fifo_done_bus_en[42] | fifo_done_bus[42]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13804 = fifo_done_bus_en[43] | fifo_done_bus[43]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13811 = fifo_done_bus_en[44] | fifo_done_bus[44]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13818 = fifo_done_bus_en[45] | fifo_done_bus[45]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13825 = fifo_done_bus_en[46] | fifo_done_bus[46]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13832 = fifo_done_bus_en[47] | fifo_done_bus[47]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13839 = fifo_done_bus_en[48] | fifo_done_bus[48]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13846 = fifo_done_bus_en[49] | fifo_done_bus[49]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13853 = fifo_done_bus_en[50] | fifo_done_bus[50]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13860 = fifo_done_bus_en[51] | fifo_done_bus[51]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13867 = fifo_done_bus_en[52] | fifo_done_bus[52]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13874 = fifo_done_bus_en[53] | fifo_done_bus[53]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13881 = fifo_done_bus_en[54] | fifo_done_bus[54]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13888 = fifo_done_bus_en[55] | fifo_done_bus[55]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13895 = fifo_done_bus_en[56] | fifo_done_bus[56]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13902 = fifo_done_bus_en[57] | fifo_done_bus[57]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13909 = fifo_done_bus_en[58] | fifo_done_bus[58]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13916 = fifo_done_bus_en[59] | fifo_done_bus[59]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13923 = fifo_done_bus_en[60] | fifo_done_bus[60]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13930 = fifo_done_bus_en[61] | fifo_done_bus[61]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13937 = fifo_done_bus_en[62] | fifo_done_bus[62]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13944 = fifo_done_bus_en[63] | fifo_done_bus[63]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13951 = fifo_done_bus_en[64] | fifo_done_bus[64]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13958 = fifo_done_bus_en[65] | fifo_done_bus[65]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13965 = fifo_done_bus_en[66] | fifo_done_bus[66]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13972 = fifo_done_bus_en[67] | fifo_done_bus[67]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13979 = fifo_done_bus_en[68] | fifo_done_bus[68]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13986 = fifo_done_bus_en[69] | fifo_done_bus[69]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_13993 = fifo_done_bus_en[70] | fifo_done_bus[70]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14000 = fifo_done_bus_en[71] | fifo_done_bus[71]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14007 = fifo_done_bus_en[72] | fifo_done_bus[72]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14014 = fifo_done_bus_en[73] | fifo_done_bus[73]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14021 = fifo_done_bus_en[74] | fifo_done_bus[74]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14028 = fifo_done_bus_en[75] | fifo_done_bus[75]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14035 = fifo_done_bus_en[76] | fifo_done_bus[76]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14042 = fifo_done_bus_en[77] | fifo_done_bus[77]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14049 = fifo_done_bus_en[78] | fifo_done_bus[78]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14056 = fifo_done_bus_en[79] | fifo_done_bus[79]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14063 = fifo_done_bus_en[80] | fifo_done_bus[80]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14070 = fifo_done_bus_en[81] | fifo_done_bus[81]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14077 = fifo_done_bus_en[82] | fifo_done_bus[82]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14084 = fifo_done_bus_en[83] | fifo_done_bus[83]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14091 = fifo_done_bus_en[84] | fifo_done_bus[84]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14098 = fifo_done_bus_en[85] | fifo_done_bus[85]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14105 = fifo_done_bus_en[86] | fifo_done_bus[86]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14112 = fifo_done_bus_en[87] | fifo_done_bus[87]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14119 = fifo_done_bus_en[88] | fifo_done_bus[88]; // @[dma_ctrl.scala 150:92]
|
|
wire _T_14126 = fifo_done_bus_en[89] | fifo_done_bus[89]; // @[dma_ctrl.scala 150:92]
|
|
reg _T_15031; // @[Reg.scala 27:20]
|
|
reg _T_15033; // @[Reg.scala 27:20]
|
|
reg _T_15035; // @[Reg.scala 27:20]
|
|
reg _T_15037; // @[Reg.scala 27:20]
|
|
reg _T_15039; // @[Reg.scala 27:20]
|
|
reg _T_15041; // @[Reg.scala 27:20]
|
|
reg _T_15043; // @[Reg.scala 27:20]
|
|
reg _T_15045; // @[Reg.scala 27:20]
|
|
reg _T_15047; // @[Reg.scala 27:20]
|
|
reg _T_15049; // @[Reg.scala 27:20]
|
|
reg _T_15051; // @[Reg.scala 27:20]
|
|
reg _T_15053; // @[Reg.scala 27:20]
|
|
reg _T_15055; // @[Reg.scala 27:20]
|
|
reg _T_15057; // @[Reg.scala 27:20]
|
|
reg _T_15059; // @[Reg.scala 27:20]
|
|
reg _T_15061; // @[Reg.scala 27:20]
|
|
reg _T_15063; // @[Reg.scala 27:20]
|
|
reg _T_15065; // @[Reg.scala 27:20]
|
|
reg _T_15067; // @[Reg.scala 27:20]
|
|
reg _T_15069; // @[Reg.scala 27:20]
|
|
reg _T_15071; // @[Reg.scala 27:20]
|
|
reg _T_15073; // @[Reg.scala 27:20]
|
|
reg _T_15075; // @[Reg.scala 27:20]
|
|
reg _T_15077; // @[Reg.scala 27:20]
|
|
reg _T_15079; // @[Reg.scala 27:20]
|
|
reg _T_15081; // @[Reg.scala 27:20]
|
|
reg _T_15083; // @[Reg.scala 27:20]
|
|
reg _T_15085; // @[Reg.scala 27:20]
|
|
reg _T_15087; // @[Reg.scala 27:20]
|
|
reg _T_15089; // @[Reg.scala 27:20]
|
|
reg _T_15091; // @[Reg.scala 27:20]
|
|
reg _T_15093; // @[Reg.scala 27:20]
|
|
reg _T_15095; // @[Reg.scala 27:20]
|
|
reg _T_15097; // @[Reg.scala 27:20]
|
|
reg _T_15099; // @[Reg.scala 27:20]
|
|
reg _T_15101; // @[Reg.scala 27:20]
|
|
reg _T_15103; // @[Reg.scala 27:20]
|
|
reg _T_15105; // @[Reg.scala 27:20]
|
|
reg _T_15107; // @[Reg.scala 27:20]
|
|
reg _T_15109; // @[Reg.scala 27:20]
|
|
reg _T_15111; // @[Reg.scala 27:20]
|
|
reg _T_15113; // @[Reg.scala 27:20]
|
|
reg _T_15115; // @[Reg.scala 27:20]
|
|
reg _T_15117; // @[Reg.scala 27:20]
|
|
reg _T_15119; // @[Reg.scala 27:20]
|
|
reg _T_15121; // @[Reg.scala 27:20]
|
|
reg _T_15123; // @[Reg.scala 27:20]
|
|
reg _T_15125; // @[Reg.scala 27:20]
|
|
reg _T_15127; // @[Reg.scala 27:20]
|
|
reg _T_15129; // @[Reg.scala 27:20]
|
|
reg _T_15131; // @[Reg.scala 27:20]
|
|
reg _T_15133; // @[Reg.scala 27:20]
|
|
reg _T_15135; // @[Reg.scala 27:20]
|
|
reg _T_15137; // @[Reg.scala 27:20]
|
|
reg _T_15139; // @[Reg.scala 27:20]
|
|
reg _T_15141; // @[Reg.scala 27:20]
|
|
reg _T_15143; // @[Reg.scala 27:20]
|
|
reg _T_15145; // @[Reg.scala 27:20]
|
|
reg _T_15147; // @[Reg.scala 27:20]
|
|
reg _T_15149; // @[Reg.scala 27:20]
|
|
reg _T_15151; // @[Reg.scala 27:20]
|
|
reg _T_15153; // @[Reg.scala 27:20]
|
|
reg _T_15155; // @[Reg.scala 27:20]
|
|
reg _T_15157; // @[Reg.scala 27:20]
|
|
reg _T_15159; // @[Reg.scala 27:20]
|
|
reg _T_15161; // @[Reg.scala 27:20]
|
|
reg _T_15163; // @[Reg.scala 27:20]
|
|
reg _T_15165; // @[Reg.scala 27:20]
|
|
reg _T_15167; // @[Reg.scala 27:20]
|
|
reg _T_15169; // @[Reg.scala 27:20]
|
|
reg _T_15171; // @[Reg.scala 27:20]
|
|
reg _T_15173; // @[Reg.scala 27:20]
|
|
reg _T_15175; // @[Reg.scala 27:20]
|
|
reg _T_15177; // @[Reg.scala 27:20]
|
|
reg _T_15179; // @[Reg.scala 27:20]
|
|
reg _T_15181; // @[Reg.scala 27:20]
|
|
reg _T_15183; // @[Reg.scala 27:20]
|
|
reg _T_15185; // @[Reg.scala 27:20]
|
|
reg _T_15187; // @[Reg.scala 27:20]
|
|
reg _T_15189; // @[Reg.scala 27:20]
|
|
reg _T_15191; // @[Reg.scala 27:20]
|
|
reg _T_15193; // @[Reg.scala 27:20]
|
|
reg _T_15195; // @[Reg.scala 27:20]
|
|
reg _T_15197; // @[Reg.scala 27:20]
|
|
reg _T_15199; // @[Reg.scala 27:20]
|
|
reg _T_15201; // @[Reg.scala 27:20]
|
|
reg _T_15203; // @[Reg.scala 27:20]
|
|
reg _T_15205; // @[Reg.scala 27:20]
|
|
reg _T_15207; // @[Reg.scala 27:20]
|
|
reg _T_15209; // @[Reg.scala 27:20]
|
|
wire [9:0] _T_15218 = {_T_15209,_T_15207,_T_15205,_T_15203,_T_15201,_T_15199,_T_15197,_T_15195,_T_15193,_T_15191}; // @[Cat.scala 29:58]
|
|
wire [18:0] _T_15227 = {_T_15218,_T_15189,_T_15187,_T_15185,_T_15183,_T_15181,_T_15179,_T_15177,_T_15175,_T_15173}; // @[Cat.scala 29:58]
|
|
wire [27:0] _T_15236 = {_T_15227,_T_15171,_T_15169,_T_15167,_T_15165,_T_15163,_T_15161,_T_15159,_T_15157,_T_15155}; // @[Cat.scala 29:58]
|
|
wire [36:0] _T_15245 = {_T_15236,_T_15153,_T_15151,_T_15149,_T_15147,_T_15145,_T_15143,_T_15141,_T_15139,_T_15137}; // @[Cat.scala 29:58]
|
|
wire [45:0] _T_15254 = {_T_15245,_T_15135,_T_15133,_T_15131,_T_15129,_T_15127,_T_15125,_T_15123,_T_15121,_T_15119}; // @[Cat.scala 29:58]
|
|
wire [54:0] _T_15263 = {_T_15254,_T_15117,_T_15115,_T_15113,_T_15111,_T_15109,_T_15107,_T_15105,_T_15103,_T_15101}; // @[Cat.scala 29:58]
|
|
wire [63:0] _T_15272 = {_T_15263,_T_15099,_T_15097,_T_15095,_T_15093,_T_15091,_T_15089,_T_15087,_T_15085,_T_15083}; // @[Cat.scala 29:58]
|
|
wire [72:0] _T_15281 = {_T_15272,_T_15081,_T_15079,_T_15077,_T_15075,_T_15073,_T_15071,_T_15069,_T_15067,_T_15065}; // @[Cat.scala 29:58]
|
|
wire [81:0] _T_15290 = {_T_15281,_T_15063,_T_15061,_T_15059,_T_15057,_T_15055,_T_15053,_T_15051,_T_15049,_T_15047}; // @[Cat.scala 29:58]
|
|
wire [89:0] fifo_write = {_T_15290,_T_15045,_T_15043,_T_15041,_T_15039,_T_15037,_T_15035,_T_15033,_T_15031}; // @[Cat.scala 29:58]
|
|
reg [63:0] fifo_data_0; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_1; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_2; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_3; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_4; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_5; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_6; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_7; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_8; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_9; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_10; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_11; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_12; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_13; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_14; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_15; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_16; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_17; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_18; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_19; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_20; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_21; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_22; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_23; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_24; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_25; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_26; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_27; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_28; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_29; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_30; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_31; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_32; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_33; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_34; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_35; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_36; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_37; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_38; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_39; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_40; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_41; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_42; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_43; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_44; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_45; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_46; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_47; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_48; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_49; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_50; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_51; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_52; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_53; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_54; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_55; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_56; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_57; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_58; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_59; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_60; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_61; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_62; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_63; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_64; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_65; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_66; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_67; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_68; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_69; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_70; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_71; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_72; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_73; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_74; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_75; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_76; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_77; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_78; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_79; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_80; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_81; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_82; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_83; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_84; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_85; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_86; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_87; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_88; // @[Reg.scala 27:20]
|
|
reg [63:0] fifo_data_89; // @[Reg.scala 27:20]
|
|
reg fifo_tag_0; // @[Reg.scala 27:20]
|
|
reg wrbuf_tag; // @[Reg.scala 27:20]
|
|
reg rdbuf_tag; // @[Reg.scala 27:20]
|
|
wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 358:37]
|
|
reg fifo_tag_1; // @[Reg.scala 27:20]
|
|
reg fifo_tag_2; // @[Reg.scala 27:20]
|
|
reg fifo_tag_3; // @[Reg.scala 27:20]
|
|
reg fifo_tag_4; // @[Reg.scala 27:20]
|
|
reg fifo_tag_5; // @[Reg.scala 27:20]
|
|
reg fifo_tag_6; // @[Reg.scala 27:20]
|
|
reg fifo_tag_7; // @[Reg.scala 27:20]
|
|
reg fifo_tag_8; // @[Reg.scala 27:20]
|
|
reg fifo_tag_9; // @[Reg.scala 27:20]
|
|
reg fifo_tag_10; // @[Reg.scala 27:20]
|
|
reg fifo_tag_11; // @[Reg.scala 27:20]
|
|
reg fifo_tag_12; // @[Reg.scala 27:20]
|
|
reg fifo_tag_13; // @[Reg.scala 27:20]
|
|
reg fifo_tag_14; // @[Reg.scala 27:20]
|
|
reg fifo_tag_15; // @[Reg.scala 27:20]
|
|
reg fifo_tag_16; // @[Reg.scala 27:20]
|
|
reg fifo_tag_17; // @[Reg.scala 27:20]
|
|
reg fifo_tag_18; // @[Reg.scala 27:20]
|
|
reg fifo_tag_19; // @[Reg.scala 27:20]
|
|
reg fifo_tag_20; // @[Reg.scala 27:20]
|
|
reg fifo_tag_21; // @[Reg.scala 27:20]
|
|
reg fifo_tag_22; // @[Reg.scala 27:20]
|
|
reg fifo_tag_23; // @[Reg.scala 27:20]
|
|
reg fifo_tag_24; // @[Reg.scala 27:20]
|
|
reg fifo_tag_25; // @[Reg.scala 27:20]
|
|
reg fifo_tag_26; // @[Reg.scala 27:20]
|
|
reg fifo_tag_27; // @[Reg.scala 27:20]
|
|
reg fifo_tag_28; // @[Reg.scala 27:20]
|
|
reg fifo_tag_29; // @[Reg.scala 27:20]
|
|
reg fifo_tag_30; // @[Reg.scala 27:20]
|
|
reg fifo_tag_31; // @[Reg.scala 27:20]
|
|
reg fifo_tag_32; // @[Reg.scala 27:20]
|
|
reg fifo_tag_33; // @[Reg.scala 27:20]
|
|
reg fifo_tag_34; // @[Reg.scala 27:20]
|
|
reg fifo_tag_35; // @[Reg.scala 27:20]
|
|
reg fifo_tag_36; // @[Reg.scala 27:20]
|
|
reg fifo_tag_37; // @[Reg.scala 27:20]
|
|
reg fifo_tag_38; // @[Reg.scala 27:20]
|
|
reg fifo_tag_39; // @[Reg.scala 27:20]
|
|
reg fifo_tag_40; // @[Reg.scala 27:20]
|
|
reg fifo_tag_41; // @[Reg.scala 27:20]
|
|
reg fifo_tag_42; // @[Reg.scala 27:20]
|
|
reg fifo_tag_43; // @[Reg.scala 27:20]
|
|
reg fifo_tag_44; // @[Reg.scala 27:20]
|
|
reg fifo_tag_45; // @[Reg.scala 27:20]
|
|
reg fifo_tag_46; // @[Reg.scala 27:20]
|
|
reg fifo_tag_47; // @[Reg.scala 27:20]
|
|
reg fifo_tag_48; // @[Reg.scala 27:20]
|
|
reg fifo_tag_49; // @[Reg.scala 27:20]
|
|
reg fifo_tag_50; // @[Reg.scala 27:20]
|
|
reg fifo_tag_51; // @[Reg.scala 27:20]
|
|
reg fifo_tag_52; // @[Reg.scala 27:20]
|
|
reg fifo_tag_53; // @[Reg.scala 27:20]
|
|
reg fifo_tag_54; // @[Reg.scala 27:20]
|
|
reg fifo_tag_55; // @[Reg.scala 27:20]
|
|
reg fifo_tag_56; // @[Reg.scala 27:20]
|
|
reg fifo_tag_57; // @[Reg.scala 27:20]
|
|
reg fifo_tag_58; // @[Reg.scala 27:20]
|
|
reg fifo_tag_59; // @[Reg.scala 27:20]
|
|
reg fifo_tag_60; // @[Reg.scala 27:20]
|
|
reg fifo_tag_61; // @[Reg.scala 27:20]
|
|
reg fifo_tag_62; // @[Reg.scala 27:20]
|
|
reg fifo_tag_63; // @[Reg.scala 27:20]
|
|
reg fifo_tag_64; // @[Reg.scala 27:20]
|
|
reg fifo_tag_65; // @[Reg.scala 27:20]
|
|
reg fifo_tag_66; // @[Reg.scala 27:20]
|
|
reg fifo_tag_67; // @[Reg.scala 27:20]
|
|
reg fifo_tag_68; // @[Reg.scala 27:20]
|
|
reg fifo_tag_69; // @[Reg.scala 27:20]
|
|
reg fifo_tag_70; // @[Reg.scala 27:20]
|
|
reg fifo_tag_71; // @[Reg.scala 27:20]
|
|
reg fifo_tag_72; // @[Reg.scala 27:20]
|
|
reg fifo_tag_73; // @[Reg.scala 27:20]
|
|
reg fifo_tag_74; // @[Reg.scala 27:20]
|
|
reg fifo_tag_75; // @[Reg.scala 27:20]
|
|
reg fifo_tag_76; // @[Reg.scala 27:20]
|
|
reg fifo_tag_77; // @[Reg.scala 27:20]
|
|
reg fifo_tag_78; // @[Reg.scala 27:20]
|
|
reg fifo_tag_79; // @[Reg.scala 27:20]
|
|
reg fifo_tag_80; // @[Reg.scala 27:20]
|
|
reg fifo_tag_81; // @[Reg.scala 27:20]
|
|
reg fifo_tag_82; // @[Reg.scala 27:20]
|
|
reg fifo_tag_83; // @[Reg.scala 27:20]
|
|
reg fifo_tag_84; // @[Reg.scala 27:20]
|
|
reg fifo_tag_85; // @[Reg.scala 27:20]
|
|
reg fifo_tag_86; // @[Reg.scala 27:20]
|
|
reg fifo_tag_87; // @[Reg.scala 27:20]
|
|
reg fifo_tag_88; // @[Reg.scala 27:20]
|
|
reg fifo_tag_89; // @[Reg.scala 27:20]
|
|
wire _T_16554 = WrPtr == 7'h59; // @[dma_ctrl.scala 169:31]
|
|
wire [6:0] _T_16556 = WrPtr + 7'h1; // @[dma_ctrl.scala 169:59]
|
|
wire _T_16557 = RdPtr == 7'h59; // @[dma_ctrl.scala 170:31]
|
|
wire [6:0] _T_16559 = RdPtr + 7'h1; // @[dma_ctrl.scala 170:59]
|
|
wire _T_16560 = RspPtr == 7'h59; // @[dma_ctrl.scala 171:31]
|
|
wire [6:0] _T_16562 = RspPtr + 7'h1; // @[dma_ctrl.scala 171:61]
|
|
wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 173:29]
|
|
wire RdPtrEn = _T_2531 | _T_3073; // @[dma_ctrl.scala 174:91]
|
|
wire RspPtrEn = io_dma_dbg_cmd_done | _T_6937; // @[dma_ctrl.scala 175:39]
|
|
wire _T_17058 = _T_6 | axi_mstr_prty_en; // @[dma_ctrl.scala 216:41]
|
|
wire fifo_empty = ~_T_17058; // @[dma_ctrl.scala 216:24]
|
|
wire [89:0] _T_17060 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 220:37]
|
|
wire [89:0] _T_17062 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 220:56]
|
|
wire _T_17064 = _T_17060[0] & _T_17062[0]; // @[dma_ctrl.scala 220:46]
|
|
wire [89:0] _T_17065 = fifo_done >> RspPtr; // @[dma_ctrl.scala 220:76]
|
|
wire [1:0] _GEN_904 = 7'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_905 = 7'h2 == RspPtr ? fifo_error_2 : _GEN_904; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_906 = 7'h3 == RspPtr ? fifo_error_3 : _GEN_905; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_907 = 7'h4 == RspPtr ? fifo_error_4 : _GEN_906; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_908 = 7'h5 == RspPtr ? fifo_error_5 : _GEN_907; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_909 = 7'h6 == RspPtr ? fifo_error_6 : _GEN_908; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_910 = 7'h7 == RspPtr ? fifo_error_7 : _GEN_909; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_911 = 7'h8 == RspPtr ? fifo_error_8 : _GEN_910; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_912 = 7'h9 == RspPtr ? fifo_error_9 : _GEN_911; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_913 = 7'ha == RspPtr ? fifo_error_10 : _GEN_912; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_914 = 7'hb == RspPtr ? fifo_error_11 : _GEN_913; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_915 = 7'hc == RspPtr ? fifo_error_12 : _GEN_914; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_916 = 7'hd == RspPtr ? fifo_error_13 : _GEN_915; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_917 = 7'he == RspPtr ? fifo_error_14 : _GEN_916; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_918 = 7'hf == RspPtr ? fifo_error_15 : _GEN_917; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_919 = 7'h10 == RspPtr ? fifo_error_16 : _GEN_918; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_920 = 7'h11 == RspPtr ? fifo_error_17 : _GEN_919; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_921 = 7'h12 == RspPtr ? fifo_error_18 : _GEN_920; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_922 = 7'h13 == RspPtr ? fifo_error_19 : _GEN_921; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_923 = 7'h14 == RspPtr ? fifo_error_20 : _GEN_922; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_924 = 7'h15 == RspPtr ? fifo_error_21 : _GEN_923; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_925 = 7'h16 == RspPtr ? fifo_error_22 : _GEN_924; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_926 = 7'h17 == RspPtr ? fifo_error_23 : _GEN_925; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_927 = 7'h18 == RspPtr ? fifo_error_24 : _GEN_926; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_928 = 7'h19 == RspPtr ? fifo_error_25 : _GEN_927; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_929 = 7'h1a == RspPtr ? fifo_error_26 : _GEN_928; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_930 = 7'h1b == RspPtr ? fifo_error_27 : _GEN_929; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_931 = 7'h1c == RspPtr ? fifo_error_28 : _GEN_930; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_932 = 7'h1d == RspPtr ? fifo_error_29 : _GEN_931; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_933 = 7'h1e == RspPtr ? fifo_error_30 : _GEN_932; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_934 = 7'h1f == RspPtr ? fifo_error_31 : _GEN_933; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_935 = 7'h20 == RspPtr ? fifo_error_32 : _GEN_934; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_936 = 7'h21 == RspPtr ? fifo_error_33 : _GEN_935; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_937 = 7'h22 == RspPtr ? fifo_error_34 : _GEN_936; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_938 = 7'h23 == RspPtr ? fifo_error_35 : _GEN_937; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_939 = 7'h24 == RspPtr ? fifo_error_36 : _GEN_938; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_940 = 7'h25 == RspPtr ? fifo_error_37 : _GEN_939; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_941 = 7'h26 == RspPtr ? fifo_error_38 : _GEN_940; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_942 = 7'h27 == RspPtr ? fifo_error_39 : _GEN_941; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_943 = 7'h28 == RspPtr ? fifo_error_40 : _GEN_942; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_944 = 7'h29 == RspPtr ? fifo_error_41 : _GEN_943; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_945 = 7'h2a == RspPtr ? fifo_error_42 : _GEN_944; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_946 = 7'h2b == RspPtr ? fifo_error_43 : _GEN_945; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_947 = 7'h2c == RspPtr ? fifo_error_44 : _GEN_946; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_948 = 7'h2d == RspPtr ? fifo_error_45 : _GEN_947; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_949 = 7'h2e == RspPtr ? fifo_error_46 : _GEN_948; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_950 = 7'h2f == RspPtr ? fifo_error_47 : _GEN_949; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_951 = 7'h30 == RspPtr ? fifo_error_48 : _GEN_950; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_952 = 7'h31 == RspPtr ? fifo_error_49 : _GEN_951; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_953 = 7'h32 == RspPtr ? fifo_error_50 : _GEN_952; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_954 = 7'h33 == RspPtr ? fifo_error_51 : _GEN_953; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_955 = 7'h34 == RspPtr ? fifo_error_52 : _GEN_954; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_956 = 7'h35 == RspPtr ? fifo_error_53 : _GEN_955; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_957 = 7'h36 == RspPtr ? fifo_error_54 : _GEN_956; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_958 = 7'h37 == RspPtr ? fifo_error_55 : _GEN_957; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_959 = 7'h38 == RspPtr ? fifo_error_56 : _GEN_958; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_960 = 7'h39 == RspPtr ? fifo_error_57 : _GEN_959; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_961 = 7'h3a == RspPtr ? fifo_error_58 : _GEN_960; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_962 = 7'h3b == RspPtr ? fifo_error_59 : _GEN_961; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_963 = 7'h3c == RspPtr ? fifo_error_60 : _GEN_962; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_964 = 7'h3d == RspPtr ? fifo_error_61 : _GEN_963; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_965 = 7'h3e == RspPtr ? fifo_error_62 : _GEN_964; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_966 = 7'h3f == RspPtr ? fifo_error_63 : _GEN_965; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_967 = 7'h40 == RspPtr ? fifo_error_64 : _GEN_966; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_968 = 7'h41 == RspPtr ? fifo_error_65 : _GEN_967; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_969 = 7'h42 == RspPtr ? fifo_error_66 : _GEN_968; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_970 = 7'h43 == RspPtr ? fifo_error_67 : _GEN_969; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_971 = 7'h44 == RspPtr ? fifo_error_68 : _GEN_970; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_972 = 7'h45 == RspPtr ? fifo_error_69 : _GEN_971; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_973 = 7'h46 == RspPtr ? fifo_error_70 : _GEN_972; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_974 = 7'h47 == RspPtr ? fifo_error_71 : _GEN_973; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_975 = 7'h48 == RspPtr ? fifo_error_72 : _GEN_974; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_976 = 7'h49 == RspPtr ? fifo_error_73 : _GEN_975; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_977 = 7'h4a == RspPtr ? fifo_error_74 : _GEN_976; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_978 = 7'h4b == RspPtr ? fifo_error_75 : _GEN_977; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_979 = 7'h4c == RspPtr ? fifo_error_76 : _GEN_978; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_980 = 7'h4d == RspPtr ? fifo_error_77 : _GEN_979; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_981 = 7'h4e == RspPtr ? fifo_error_78 : _GEN_980; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_982 = 7'h4f == RspPtr ? fifo_error_79 : _GEN_981; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_983 = 7'h50 == RspPtr ? fifo_error_80 : _GEN_982; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_984 = 7'h51 == RspPtr ? fifo_error_81 : _GEN_983; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_985 = 7'h52 == RspPtr ? fifo_error_82 : _GEN_984; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_986 = 7'h53 == RspPtr ? fifo_error_83 : _GEN_985; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_987 = 7'h54 == RspPtr ? fifo_error_84 : _GEN_986; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_988 = 7'h55 == RspPtr ? fifo_error_85 : _GEN_987; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_989 = 7'h56 == RspPtr ? fifo_error_86 : _GEN_988; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_990 = 7'h57 == RspPtr ? fifo_error_87 : _GEN_989; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_991 = 7'h58 == RspPtr ? fifo_error_88 : _GEN_990; // @[dma_ctrl.scala 221:49]
|
|
wire [1:0] _GEN_992 = 7'h59 == RspPtr ? fifo_error_89 : _GEN_991; // @[dma_ctrl.scala 221:49]
|
|
wire [2:0] _GEN_994 = 7'h1 == RspPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_995 = 7'h2 == RspPtr ? fifo_sz_2 : _GEN_994; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_996 = 7'h3 == RspPtr ? fifo_sz_3 : _GEN_995; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_997 = 7'h4 == RspPtr ? fifo_sz_4 : _GEN_996; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_998 = 7'h5 == RspPtr ? fifo_sz_5 : _GEN_997; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_999 = 7'h6 == RspPtr ? fifo_sz_6 : _GEN_998; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1000 = 7'h7 == RspPtr ? fifo_sz_7 : _GEN_999; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1001 = 7'h8 == RspPtr ? fifo_sz_8 : _GEN_1000; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1002 = 7'h9 == RspPtr ? fifo_sz_9 : _GEN_1001; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1003 = 7'ha == RspPtr ? fifo_sz_10 : _GEN_1002; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1004 = 7'hb == RspPtr ? fifo_sz_11 : _GEN_1003; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1005 = 7'hc == RspPtr ? fifo_sz_12 : _GEN_1004; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1006 = 7'hd == RspPtr ? fifo_sz_13 : _GEN_1005; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1007 = 7'he == RspPtr ? fifo_sz_14 : _GEN_1006; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1008 = 7'hf == RspPtr ? fifo_sz_15 : _GEN_1007; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1009 = 7'h10 == RspPtr ? fifo_sz_16 : _GEN_1008; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1010 = 7'h11 == RspPtr ? fifo_sz_17 : _GEN_1009; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1011 = 7'h12 == RspPtr ? fifo_sz_18 : _GEN_1010; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1012 = 7'h13 == RspPtr ? fifo_sz_19 : _GEN_1011; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1013 = 7'h14 == RspPtr ? fifo_sz_20 : _GEN_1012; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1014 = 7'h15 == RspPtr ? fifo_sz_21 : _GEN_1013; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1015 = 7'h16 == RspPtr ? fifo_sz_22 : _GEN_1014; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1016 = 7'h17 == RspPtr ? fifo_sz_23 : _GEN_1015; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1017 = 7'h18 == RspPtr ? fifo_sz_24 : _GEN_1016; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1018 = 7'h19 == RspPtr ? fifo_sz_25 : _GEN_1017; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1019 = 7'h1a == RspPtr ? fifo_sz_26 : _GEN_1018; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1020 = 7'h1b == RspPtr ? fifo_sz_27 : _GEN_1019; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1021 = 7'h1c == RspPtr ? fifo_sz_28 : _GEN_1020; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1022 = 7'h1d == RspPtr ? fifo_sz_29 : _GEN_1021; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1023 = 7'h1e == RspPtr ? fifo_sz_30 : _GEN_1022; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1024 = 7'h1f == RspPtr ? fifo_sz_31 : _GEN_1023; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1025 = 7'h20 == RspPtr ? fifo_sz_32 : _GEN_1024; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1026 = 7'h21 == RspPtr ? fifo_sz_33 : _GEN_1025; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1027 = 7'h22 == RspPtr ? fifo_sz_34 : _GEN_1026; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1028 = 7'h23 == RspPtr ? fifo_sz_35 : _GEN_1027; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1029 = 7'h24 == RspPtr ? fifo_sz_36 : _GEN_1028; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1030 = 7'h25 == RspPtr ? fifo_sz_37 : _GEN_1029; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1031 = 7'h26 == RspPtr ? fifo_sz_38 : _GEN_1030; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1032 = 7'h27 == RspPtr ? fifo_sz_39 : _GEN_1031; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1033 = 7'h28 == RspPtr ? fifo_sz_40 : _GEN_1032; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1034 = 7'h29 == RspPtr ? fifo_sz_41 : _GEN_1033; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1035 = 7'h2a == RspPtr ? fifo_sz_42 : _GEN_1034; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1036 = 7'h2b == RspPtr ? fifo_sz_43 : _GEN_1035; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1037 = 7'h2c == RspPtr ? fifo_sz_44 : _GEN_1036; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1038 = 7'h2d == RspPtr ? fifo_sz_45 : _GEN_1037; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1039 = 7'h2e == RspPtr ? fifo_sz_46 : _GEN_1038; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1040 = 7'h2f == RspPtr ? fifo_sz_47 : _GEN_1039; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1041 = 7'h30 == RspPtr ? fifo_sz_48 : _GEN_1040; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1042 = 7'h31 == RspPtr ? fifo_sz_49 : _GEN_1041; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1043 = 7'h32 == RspPtr ? fifo_sz_50 : _GEN_1042; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1044 = 7'h33 == RspPtr ? fifo_sz_51 : _GEN_1043; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1045 = 7'h34 == RspPtr ? fifo_sz_52 : _GEN_1044; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1046 = 7'h35 == RspPtr ? fifo_sz_53 : _GEN_1045; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1047 = 7'h36 == RspPtr ? fifo_sz_54 : _GEN_1046; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1048 = 7'h37 == RspPtr ? fifo_sz_55 : _GEN_1047; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1049 = 7'h38 == RspPtr ? fifo_sz_56 : _GEN_1048; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1050 = 7'h39 == RspPtr ? fifo_sz_57 : _GEN_1049; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1051 = 7'h3a == RspPtr ? fifo_sz_58 : _GEN_1050; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1052 = 7'h3b == RspPtr ? fifo_sz_59 : _GEN_1051; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1053 = 7'h3c == RspPtr ? fifo_sz_60 : _GEN_1052; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1054 = 7'h3d == RspPtr ? fifo_sz_61 : _GEN_1053; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1055 = 7'h3e == RspPtr ? fifo_sz_62 : _GEN_1054; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1056 = 7'h3f == RspPtr ? fifo_sz_63 : _GEN_1055; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1057 = 7'h40 == RspPtr ? fifo_sz_64 : _GEN_1056; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1058 = 7'h41 == RspPtr ? fifo_sz_65 : _GEN_1057; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1059 = 7'h42 == RspPtr ? fifo_sz_66 : _GEN_1058; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1060 = 7'h43 == RspPtr ? fifo_sz_67 : _GEN_1059; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1061 = 7'h44 == RspPtr ? fifo_sz_68 : _GEN_1060; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1062 = 7'h45 == RspPtr ? fifo_sz_69 : _GEN_1061; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1063 = 7'h46 == RspPtr ? fifo_sz_70 : _GEN_1062; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1064 = 7'h47 == RspPtr ? fifo_sz_71 : _GEN_1063; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1065 = 7'h48 == RspPtr ? fifo_sz_72 : _GEN_1064; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1066 = 7'h49 == RspPtr ? fifo_sz_73 : _GEN_1065; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1067 = 7'h4a == RspPtr ? fifo_sz_74 : _GEN_1066; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1068 = 7'h4b == RspPtr ? fifo_sz_75 : _GEN_1067; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1069 = 7'h4c == RspPtr ? fifo_sz_76 : _GEN_1068; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1070 = 7'h4d == RspPtr ? fifo_sz_77 : _GEN_1069; // @[dma_ctrl.scala 223:44]
|
|
wire [2:0] _GEN_1071 = 7'h4e == RspPtr ? fifo_sz_78 : _GEN_1070; // @[dma_ctrl.scala 223:44]
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|
wire [2:0] _GEN_1072 = 7'h4f == RspPtr ? fifo_sz_79 : _GEN_1071; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1073 = 7'h50 == RspPtr ? fifo_sz_80 : _GEN_1072; // @[dma_ctrl.scala 223:44]
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|
wire [2:0] _GEN_1074 = 7'h51 == RspPtr ? fifo_sz_81 : _GEN_1073; // @[dma_ctrl.scala 223:44]
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|
wire [2:0] _GEN_1075 = 7'h52 == RspPtr ? fifo_sz_82 : _GEN_1074; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1076 = 7'h53 == RspPtr ? fifo_sz_83 : _GEN_1075; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1077 = 7'h54 == RspPtr ? fifo_sz_84 : _GEN_1076; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1078 = 7'h55 == RspPtr ? fifo_sz_85 : _GEN_1077; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1079 = 7'h56 == RspPtr ? fifo_sz_86 : _GEN_1078; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1080 = 7'h57 == RspPtr ? fifo_sz_87 : _GEN_1079; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1081 = 7'h58 == RspPtr ? fifo_sz_88 : _GEN_1080; // @[dma_ctrl.scala 223:44]
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wire [2:0] _GEN_1082 = 7'h59 == RspPtr ? fifo_sz_89 : _GEN_1081; // @[dma_ctrl.scala 223:44]
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|
wire [1:0] dma_dbg_sz = _GEN_1082[1:0]; // @[dma_ctrl.scala 223:44]
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wire [31:0] _GEN_1084 = 7'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1085 = 7'h2 == RspPtr ? fifo_addr_2 : _GEN_1084; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1086 = 7'h3 == RspPtr ? fifo_addr_3 : _GEN_1085; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1087 = 7'h4 == RspPtr ? fifo_addr_4 : _GEN_1086; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1088 = 7'h5 == RspPtr ? fifo_addr_5 : _GEN_1087; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1089 = 7'h6 == RspPtr ? fifo_addr_6 : _GEN_1088; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1090 = 7'h7 == RspPtr ? fifo_addr_7 : _GEN_1089; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1091 = 7'h8 == RspPtr ? fifo_addr_8 : _GEN_1090; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1092 = 7'h9 == RspPtr ? fifo_addr_9 : _GEN_1091; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1093 = 7'ha == RspPtr ? fifo_addr_10 : _GEN_1092; // @[dma_ctrl.scala 224:46]
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wire [31:0] _GEN_1094 = 7'hb == RspPtr ? fifo_addr_11 : _GEN_1093; // @[dma_ctrl.scala 224:46]
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|
wire [31:0] _GEN_1095 = 7'hc == RspPtr ? fifo_addr_12 : _GEN_1094; // @[dma_ctrl.scala 224:46]
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|
wire [31:0] _GEN_1096 = 7'hd == RspPtr ? fifo_addr_13 : _GEN_1095; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1097 = 7'he == RspPtr ? fifo_addr_14 : _GEN_1096; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1098 = 7'hf == RspPtr ? fifo_addr_15 : _GEN_1097; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1099 = 7'h10 == RspPtr ? fifo_addr_16 : _GEN_1098; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1100 = 7'h11 == RspPtr ? fifo_addr_17 : _GEN_1099; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1101 = 7'h12 == RspPtr ? fifo_addr_18 : _GEN_1100; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1102 = 7'h13 == RspPtr ? fifo_addr_19 : _GEN_1101; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1103 = 7'h14 == RspPtr ? fifo_addr_20 : _GEN_1102; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1104 = 7'h15 == RspPtr ? fifo_addr_21 : _GEN_1103; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1105 = 7'h16 == RspPtr ? fifo_addr_22 : _GEN_1104; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1106 = 7'h17 == RspPtr ? fifo_addr_23 : _GEN_1105; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1107 = 7'h18 == RspPtr ? fifo_addr_24 : _GEN_1106; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1108 = 7'h19 == RspPtr ? fifo_addr_25 : _GEN_1107; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1109 = 7'h1a == RspPtr ? fifo_addr_26 : _GEN_1108; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1110 = 7'h1b == RspPtr ? fifo_addr_27 : _GEN_1109; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1111 = 7'h1c == RspPtr ? fifo_addr_28 : _GEN_1110; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1112 = 7'h1d == RspPtr ? fifo_addr_29 : _GEN_1111; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1113 = 7'h1e == RspPtr ? fifo_addr_30 : _GEN_1112; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1114 = 7'h1f == RspPtr ? fifo_addr_31 : _GEN_1113; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1115 = 7'h20 == RspPtr ? fifo_addr_32 : _GEN_1114; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1116 = 7'h21 == RspPtr ? fifo_addr_33 : _GEN_1115; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1117 = 7'h22 == RspPtr ? fifo_addr_34 : _GEN_1116; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1118 = 7'h23 == RspPtr ? fifo_addr_35 : _GEN_1117; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1119 = 7'h24 == RspPtr ? fifo_addr_36 : _GEN_1118; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1120 = 7'h25 == RspPtr ? fifo_addr_37 : _GEN_1119; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1121 = 7'h26 == RspPtr ? fifo_addr_38 : _GEN_1120; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1122 = 7'h27 == RspPtr ? fifo_addr_39 : _GEN_1121; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1123 = 7'h28 == RspPtr ? fifo_addr_40 : _GEN_1122; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1124 = 7'h29 == RspPtr ? fifo_addr_41 : _GEN_1123; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1125 = 7'h2a == RspPtr ? fifo_addr_42 : _GEN_1124; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1126 = 7'h2b == RspPtr ? fifo_addr_43 : _GEN_1125; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1127 = 7'h2c == RspPtr ? fifo_addr_44 : _GEN_1126; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1128 = 7'h2d == RspPtr ? fifo_addr_45 : _GEN_1127; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1129 = 7'h2e == RspPtr ? fifo_addr_46 : _GEN_1128; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1130 = 7'h2f == RspPtr ? fifo_addr_47 : _GEN_1129; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1131 = 7'h30 == RspPtr ? fifo_addr_48 : _GEN_1130; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1132 = 7'h31 == RspPtr ? fifo_addr_49 : _GEN_1131; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1133 = 7'h32 == RspPtr ? fifo_addr_50 : _GEN_1132; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1134 = 7'h33 == RspPtr ? fifo_addr_51 : _GEN_1133; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1135 = 7'h34 == RspPtr ? fifo_addr_52 : _GEN_1134; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1136 = 7'h35 == RspPtr ? fifo_addr_53 : _GEN_1135; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1137 = 7'h36 == RspPtr ? fifo_addr_54 : _GEN_1136; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1138 = 7'h37 == RspPtr ? fifo_addr_55 : _GEN_1137; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1139 = 7'h38 == RspPtr ? fifo_addr_56 : _GEN_1138; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1140 = 7'h39 == RspPtr ? fifo_addr_57 : _GEN_1139; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1141 = 7'h3a == RspPtr ? fifo_addr_58 : _GEN_1140; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1142 = 7'h3b == RspPtr ? fifo_addr_59 : _GEN_1141; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1143 = 7'h3c == RspPtr ? fifo_addr_60 : _GEN_1142; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1144 = 7'h3d == RspPtr ? fifo_addr_61 : _GEN_1143; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1145 = 7'h3e == RspPtr ? fifo_addr_62 : _GEN_1144; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1146 = 7'h3f == RspPtr ? fifo_addr_63 : _GEN_1145; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1147 = 7'h40 == RspPtr ? fifo_addr_64 : _GEN_1146; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1148 = 7'h41 == RspPtr ? fifo_addr_65 : _GEN_1147; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1149 = 7'h42 == RspPtr ? fifo_addr_66 : _GEN_1148; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1150 = 7'h43 == RspPtr ? fifo_addr_67 : _GEN_1149; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1151 = 7'h44 == RspPtr ? fifo_addr_68 : _GEN_1150; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1152 = 7'h45 == RspPtr ? fifo_addr_69 : _GEN_1151; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1153 = 7'h46 == RspPtr ? fifo_addr_70 : _GEN_1152; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1154 = 7'h47 == RspPtr ? fifo_addr_71 : _GEN_1153; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1155 = 7'h48 == RspPtr ? fifo_addr_72 : _GEN_1154; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1156 = 7'h49 == RspPtr ? fifo_addr_73 : _GEN_1155; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1157 = 7'h4a == RspPtr ? fifo_addr_74 : _GEN_1156; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1158 = 7'h4b == RspPtr ? fifo_addr_75 : _GEN_1157; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1159 = 7'h4c == RspPtr ? fifo_addr_76 : _GEN_1158; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1160 = 7'h4d == RspPtr ? fifo_addr_77 : _GEN_1159; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1161 = 7'h4e == RspPtr ? fifo_addr_78 : _GEN_1160; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1162 = 7'h4f == RspPtr ? fifo_addr_79 : _GEN_1161; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1163 = 7'h50 == RspPtr ? fifo_addr_80 : _GEN_1162; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1164 = 7'h51 == RspPtr ? fifo_addr_81 : _GEN_1163; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1165 = 7'h52 == RspPtr ? fifo_addr_82 : _GEN_1164; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1166 = 7'h53 == RspPtr ? fifo_addr_83 : _GEN_1165; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1167 = 7'h54 == RspPtr ? fifo_addr_84 : _GEN_1166; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1168 = 7'h55 == RspPtr ? fifo_addr_85 : _GEN_1167; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1169 = 7'h56 == RspPtr ? fifo_addr_86 : _GEN_1168; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1170 = 7'h57 == RspPtr ? fifo_addr_87 : _GEN_1169; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1171 = 7'h58 == RspPtr ? fifo_addr_88 : _GEN_1170; // @[dma_ctrl.scala 224:46]
|
|
wire [31:0] _GEN_1172 = 7'h59 == RspPtr ? fifo_addr_89 : _GEN_1171; // @[dma_ctrl.scala 224:46]
|
|
wire [1:0] dma_dbg_addr = _GEN_1172[1:0]; // @[dma_ctrl.scala 224:46]
|
|
wire [63:0] _GEN_1174 = 7'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1175 = 7'h2 == RspPtr ? fifo_data_2 : _GEN_1174; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1176 = 7'h3 == RspPtr ? fifo_data_3 : _GEN_1175; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1177 = 7'h4 == RspPtr ? fifo_data_4 : _GEN_1176; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1178 = 7'h5 == RspPtr ? fifo_data_5 : _GEN_1177; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1179 = 7'h6 == RspPtr ? fifo_data_6 : _GEN_1178; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1180 = 7'h7 == RspPtr ? fifo_data_7 : _GEN_1179; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1181 = 7'h8 == RspPtr ? fifo_data_8 : _GEN_1180; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1182 = 7'h9 == RspPtr ? fifo_data_9 : _GEN_1181; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1183 = 7'ha == RspPtr ? fifo_data_10 : _GEN_1182; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1184 = 7'hb == RspPtr ? fifo_data_11 : _GEN_1183; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1185 = 7'hc == RspPtr ? fifo_data_12 : _GEN_1184; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1186 = 7'hd == RspPtr ? fifo_data_13 : _GEN_1185; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1187 = 7'he == RspPtr ? fifo_data_14 : _GEN_1186; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1188 = 7'hf == RspPtr ? fifo_data_15 : _GEN_1187; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1189 = 7'h10 == RspPtr ? fifo_data_16 : _GEN_1188; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1190 = 7'h11 == RspPtr ? fifo_data_17 : _GEN_1189; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1191 = 7'h12 == RspPtr ? fifo_data_18 : _GEN_1190; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1192 = 7'h13 == RspPtr ? fifo_data_19 : _GEN_1191; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1193 = 7'h14 == RspPtr ? fifo_data_20 : _GEN_1192; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1194 = 7'h15 == RspPtr ? fifo_data_21 : _GEN_1193; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1195 = 7'h16 == RspPtr ? fifo_data_22 : _GEN_1194; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1196 = 7'h17 == RspPtr ? fifo_data_23 : _GEN_1195; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1197 = 7'h18 == RspPtr ? fifo_data_24 : _GEN_1196; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1198 = 7'h19 == RspPtr ? fifo_data_25 : _GEN_1197; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1199 = 7'h1a == RspPtr ? fifo_data_26 : _GEN_1198; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1200 = 7'h1b == RspPtr ? fifo_data_27 : _GEN_1199; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1201 = 7'h1c == RspPtr ? fifo_data_28 : _GEN_1200; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1202 = 7'h1d == RspPtr ? fifo_data_29 : _GEN_1201; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1203 = 7'h1e == RspPtr ? fifo_data_30 : _GEN_1202; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1204 = 7'h1f == RspPtr ? fifo_data_31 : _GEN_1203; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1205 = 7'h20 == RspPtr ? fifo_data_32 : _GEN_1204; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1206 = 7'h21 == RspPtr ? fifo_data_33 : _GEN_1205; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1207 = 7'h22 == RspPtr ? fifo_data_34 : _GEN_1206; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1208 = 7'h23 == RspPtr ? fifo_data_35 : _GEN_1207; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1209 = 7'h24 == RspPtr ? fifo_data_36 : _GEN_1208; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1210 = 7'h25 == RspPtr ? fifo_data_37 : _GEN_1209; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1211 = 7'h26 == RspPtr ? fifo_data_38 : _GEN_1210; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1212 = 7'h27 == RspPtr ? fifo_data_39 : _GEN_1211; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1213 = 7'h28 == RspPtr ? fifo_data_40 : _GEN_1212; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1214 = 7'h29 == RspPtr ? fifo_data_41 : _GEN_1213; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1215 = 7'h2a == RspPtr ? fifo_data_42 : _GEN_1214; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1216 = 7'h2b == RspPtr ? fifo_data_43 : _GEN_1215; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1217 = 7'h2c == RspPtr ? fifo_data_44 : _GEN_1216; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1218 = 7'h2d == RspPtr ? fifo_data_45 : _GEN_1217; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1219 = 7'h2e == RspPtr ? fifo_data_46 : _GEN_1218; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1220 = 7'h2f == RspPtr ? fifo_data_47 : _GEN_1219; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1221 = 7'h30 == RspPtr ? fifo_data_48 : _GEN_1220; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1222 = 7'h31 == RspPtr ? fifo_data_49 : _GEN_1221; // @[dma_ctrl.scala 225:72]
|
|
wire [63:0] _GEN_1223 = 7'h32 == RspPtr ? fifo_data_50 : _GEN_1222; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1224 = 7'h33 == RspPtr ? fifo_data_51 : _GEN_1223; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1225 = 7'h34 == RspPtr ? fifo_data_52 : _GEN_1224; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1226 = 7'h35 == RspPtr ? fifo_data_53 : _GEN_1225; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1227 = 7'h36 == RspPtr ? fifo_data_54 : _GEN_1226; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1228 = 7'h37 == RspPtr ? fifo_data_55 : _GEN_1227; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1229 = 7'h38 == RspPtr ? fifo_data_56 : _GEN_1228; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1230 = 7'h39 == RspPtr ? fifo_data_57 : _GEN_1229; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1231 = 7'h3a == RspPtr ? fifo_data_58 : _GEN_1230; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1232 = 7'h3b == RspPtr ? fifo_data_59 : _GEN_1231; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1233 = 7'h3c == RspPtr ? fifo_data_60 : _GEN_1232; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1234 = 7'h3d == RspPtr ? fifo_data_61 : _GEN_1233; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1235 = 7'h3e == RspPtr ? fifo_data_62 : _GEN_1234; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1236 = 7'h3f == RspPtr ? fifo_data_63 : _GEN_1235; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1237 = 7'h40 == RspPtr ? fifo_data_64 : _GEN_1236; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1238 = 7'h41 == RspPtr ? fifo_data_65 : _GEN_1237; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1239 = 7'h42 == RspPtr ? fifo_data_66 : _GEN_1238; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1240 = 7'h43 == RspPtr ? fifo_data_67 : _GEN_1239; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1241 = 7'h44 == RspPtr ? fifo_data_68 : _GEN_1240; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1242 = 7'h45 == RspPtr ? fifo_data_69 : _GEN_1241; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1243 = 7'h46 == RspPtr ? fifo_data_70 : _GEN_1242; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1244 = 7'h47 == RspPtr ? fifo_data_71 : _GEN_1243; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1245 = 7'h48 == RspPtr ? fifo_data_72 : _GEN_1244; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1246 = 7'h49 == RspPtr ? fifo_data_73 : _GEN_1245; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1247 = 7'h4a == RspPtr ? fifo_data_74 : _GEN_1246; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1248 = 7'h4b == RspPtr ? fifo_data_75 : _GEN_1247; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1249 = 7'h4c == RspPtr ? fifo_data_76 : _GEN_1248; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1250 = 7'h4d == RspPtr ? fifo_data_77 : _GEN_1249; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1251 = 7'h4e == RspPtr ? fifo_data_78 : _GEN_1250; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1252 = 7'h4f == RspPtr ? fifo_data_79 : _GEN_1251; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1253 = 7'h50 == RspPtr ? fifo_data_80 : _GEN_1252; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1254 = 7'h51 == RspPtr ? fifo_data_81 : _GEN_1253; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1255 = 7'h52 == RspPtr ? fifo_data_82 : _GEN_1254; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1256 = 7'h53 == RspPtr ? fifo_data_83 : _GEN_1255; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1257 = 7'h54 == RspPtr ? fifo_data_84 : _GEN_1256; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1258 = 7'h55 == RspPtr ? fifo_data_85 : _GEN_1257; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1259 = 7'h56 == RspPtr ? fifo_data_86 : _GEN_1258; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1260 = 7'h57 == RspPtr ? fifo_data_87 : _GEN_1259; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1261 = 7'h58 == RspPtr ? fifo_data_88 : _GEN_1260; // @[dma_ctrl.scala 225:72]
|
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wire [63:0] _GEN_1262 = 7'h59 == RspPtr ? fifo_data_89 : _GEN_1261; // @[dma_ctrl.scala 225:72]
|
|
wire [31:0] dma_dbg_mem_rddata = _GEN_1172[2] ? _GEN_1262[63:32] : _GEN_1262[31:0]; // @[dma_ctrl.scala 225:32]
|
|
wire _T_17073 = dma_dbg_sz == 2'h0; // @[dma_ctrl.scala 227:22]
|
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wire [3:0] _GEN_2551 = {{2'd0}, dma_dbg_addr}; // @[dma_ctrl.scala 227:72]
|
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wire [5:0] _T_17075 = 4'h8 * _GEN_2551; // @[dma_ctrl.scala 227:72]
|
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wire [31:0] _T_17076 = dma_dbg_mem_rddata >> _T_17075; // @[dma_ctrl.scala 227:63]
|
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wire [31:0] _T_17077 = _T_17076 & 32'hff; // @[dma_ctrl.scala 227:93]
|
|
wire _T_17079 = dma_dbg_sz == 2'h1; // @[dma_ctrl.scala 228:22]
|
|
wire [4:0] _GEN_2552 = {{4'd0}, dma_dbg_addr[1]}; // @[dma_ctrl.scala 228:73]
|
|
wire [5:0] _T_17081 = 5'h10 * _GEN_2552; // @[dma_ctrl.scala 228:73]
|
|
wire [31:0] _T_17082 = dma_dbg_mem_rddata >> _T_17081; // @[dma_ctrl.scala 228:63]
|
|
wire [31:0] _T_17083 = _T_17082 & 32'hffff; // @[dma_ctrl.scala 228:92]
|
|
wire _T_17085 = dma_dbg_sz == 2'h2; // @[dma_ctrl.scala 229:22]
|
|
wire [31:0] _T_17086 = _T_17073 ? _T_17077 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_17087 = _T_17079 ? _T_17083 : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_17088 = _T_17085 ? dma_dbg_mem_rddata : 32'h0; // @[Mux.scala 27:72]
|
|
wire [31:0] _T_17089 = _T_17086 | _T_17087; // @[Mux.scala 27:72]
|
|
wire _T_17137 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 250:81]
|
|
wire [89:0] _T_17160 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 262:58]
|
|
wire _T_17162 = ~_T_17160[0]; // @[dma_ctrl.scala 262:47]
|
|
wire _T_17163 = _T_16938[0] & _T_17162; // @[dma_ctrl.scala 262:45]
|
|
wire _T_17167 = _T_17163 & _T_16942; // @[dma_ctrl.scala 262:66]
|
|
wire _T_17170 = ~_T_3073; // @[dma_ctrl.scala 262:88]
|
|
wire dma_mem_req = _T_17167 & _T_17170; // @[dma_ctrl.scala 262:86]
|
|
wire _T_17138 = dma_mem_req & _T_17137; // @[dma_ctrl.scala 250:57]
|
|
reg [2:0] dma_nack_count; // @[Reg.scala 27:20]
|
|
wire _T_17139 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 250:122]
|
|
wire _T_17141 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 252:56]
|
|
wire _T_17146 = ~_T_2531; // @[dma_ctrl.scala 256:78]
|
|
wire [2:0] _T_17148 = _T_17146 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
|
wire [2:0] _T_17149 = _T_17148 & dma_nack_count; // @[dma_ctrl.scala 256:157]
|
|
wire _T_17152 = dma_mem_req & _T_17146; // @[dma_ctrl.scala 257:22]
|
|
wire [2:0] _T_17154 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 257:119]
|
|
wire _T_17180 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_16946; // @[dma_ctrl.scala 269:90]
|
|
wire _T_17182 = _T_17180 & _T_17048; // @[dma_ctrl.scala 269:109]
|
|
wire [31:0] _T_17186 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
|
|
wire _T_17195 = _T_17180 & _T_17049; // @[dma_ctrl.scala 272:107]
|
|
wire [89:0] _T_17197 = fifo_write >> RdPtr; // @[dma_ctrl.scala 275:57]
|
|
wire [63:0] _GEN_1535 = 7'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1536 = 7'h2 == RdPtr ? fifo_data_2 : _GEN_1535; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1537 = 7'h3 == RdPtr ? fifo_data_3 : _GEN_1536; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1538 = 7'h4 == RdPtr ? fifo_data_4 : _GEN_1537; // @[dma_ctrl.scala 277:45]
|
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wire [63:0] _GEN_1539 = 7'h5 == RdPtr ? fifo_data_5 : _GEN_1538; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1540 = 7'h6 == RdPtr ? fifo_data_6 : _GEN_1539; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1541 = 7'h7 == RdPtr ? fifo_data_7 : _GEN_1540; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1542 = 7'h8 == RdPtr ? fifo_data_8 : _GEN_1541; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1543 = 7'h9 == RdPtr ? fifo_data_9 : _GEN_1542; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1544 = 7'ha == RdPtr ? fifo_data_10 : _GEN_1543; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1545 = 7'hb == RdPtr ? fifo_data_11 : _GEN_1544; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1546 = 7'hc == RdPtr ? fifo_data_12 : _GEN_1545; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1547 = 7'hd == RdPtr ? fifo_data_13 : _GEN_1546; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1548 = 7'he == RdPtr ? fifo_data_14 : _GEN_1547; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1549 = 7'hf == RdPtr ? fifo_data_15 : _GEN_1548; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1550 = 7'h10 == RdPtr ? fifo_data_16 : _GEN_1549; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1551 = 7'h11 == RdPtr ? fifo_data_17 : _GEN_1550; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1552 = 7'h12 == RdPtr ? fifo_data_18 : _GEN_1551; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1553 = 7'h13 == RdPtr ? fifo_data_19 : _GEN_1552; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1554 = 7'h14 == RdPtr ? fifo_data_20 : _GEN_1553; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1555 = 7'h15 == RdPtr ? fifo_data_21 : _GEN_1554; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1556 = 7'h16 == RdPtr ? fifo_data_22 : _GEN_1555; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1557 = 7'h17 == RdPtr ? fifo_data_23 : _GEN_1556; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1558 = 7'h18 == RdPtr ? fifo_data_24 : _GEN_1557; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1559 = 7'h19 == RdPtr ? fifo_data_25 : _GEN_1558; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1560 = 7'h1a == RdPtr ? fifo_data_26 : _GEN_1559; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1561 = 7'h1b == RdPtr ? fifo_data_27 : _GEN_1560; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1562 = 7'h1c == RdPtr ? fifo_data_28 : _GEN_1561; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1563 = 7'h1d == RdPtr ? fifo_data_29 : _GEN_1562; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1564 = 7'h1e == RdPtr ? fifo_data_30 : _GEN_1563; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1565 = 7'h1f == RdPtr ? fifo_data_31 : _GEN_1564; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1566 = 7'h20 == RdPtr ? fifo_data_32 : _GEN_1565; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1567 = 7'h21 == RdPtr ? fifo_data_33 : _GEN_1566; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1568 = 7'h22 == RdPtr ? fifo_data_34 : _GEN_1567; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1569 = 7'h23 == RdPtr ? fifo_data_35 : _GEN_1568; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1570 = 7'h24 == RdPtr ? fifo_data_36 : _GEN_1569; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1571 = 7'h25 == RdPtr ? fifo_data_37 : _GEN_1570; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1572 = 7'h26 == RdPtr ? fifo_data_38 : _GEN_1571; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1573 = 7'h27 == RdPtr ? fifo_data_39 : _GEN_1572; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1574 = 7'h28 == RdPtr ? fifo_data_40 : _GEN_1573; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1575 = 7'h29 == RdPtr ? fifo_data_41 : _GEN_1574; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1576 = 7'h2a == RdPtr ? fifo_data_42 : _GEN_1575; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1577 = 7'h2b == RdPtr ? fifo_data_43 : _GEN_1576; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1578 = 7'h2c == RdPtr ? fifo_data_44 : _GEN_1577; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1579 = 7'h2d == RdPtr ? fifo_data_45 : _GEN_1578; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1580 = 7'h2e == RdPtr ? fifo_data_46 : _GEN_1579; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1581 = 7'h2f == RdPtr ? fifo_data_47 : _GEN_1580; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1582 = 7'h30 == RdPtr ? fifo_data_48 : _GEN_1581; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1583 = 7'h31 == RdPtr ? fifo_data_49 : _GEN_1582; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1584 = 7'h32 == RdPtr ? fifo_data_50 : _GEN_1583; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1585 = 7'h33 == RdPtr ? fifo_data_51 : _GEN_1584; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1586 = 7'h34 == RdPtr ? fifo_data_52 : _GEN_1585; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1587 = 7'h35 == RdPtr ? fifo_data_53 : _GEN_1586; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1588 = 7'h36 == RdPtr ? fifo_data_54 : _GEN_1587; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1589 = 7'h37 == RdPtr ? fifo_data_55 : _GEN_1588; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1590 = 7'h38 == RdPtr ? fifo_data_56 : _GEN_1589; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1591 = 7'h39 == RdPtr ? fifo_data_57 : _GEN_1590; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1592 = 7'h3a == RdPtr ? fifo_data_58 : _GEN_1591; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1593 = 7'h3b == RdPtr ? fifo_data_59 : _GEN_1592; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1594 = 7'h3c == RdPtr ? fifo_data_60 : _GEN_1593; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1595 = 7'h3d == RdPtr ? fifo_data_61 : _GEN_1594; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1596 = 7'h3e == RdPtr ? fifo_data_62 : _GEN_1595; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1597 = 7'h3f == RdPtr ? fifo_data_63 : _GEN_1596; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1598 = 7'h40 == RdPtr ? fifo_data_64 : _GEN_1597; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1599 = 7'h41 == RdPtr ? fifo_data_65 : _GEN_1598; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1600 = 7'h42 == RdPtr ? fifo_data_66 : _GEN_1599; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1601 = 7'h43 == RdPtr ? fifo_data_67 : _GEN_1600; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1602 = 7'h44 == RdPtr ? fifo_data_68 : _GEN_1601; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1603 = 7'h45 == RdPtr ? fifo_data_69 : _GEN_1602; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1604 = 7'h46 == RdPtr ? fifo_data_70 : _GEN_1603; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1605 = 7'h47 == RdPtr ? fifo_data_71 : _GEN_1604; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1606 = 7'h48 == RdPtr ? fifo_data_72 : _GEN_1605; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1607 = 7'h49 == RdPtr ? fifo_data_73 : _GEN_1606; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1608 = 7'h4a == RdPtr ? fifo_data_74 : _GEN_1607; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1609 = 7'h4b == RdPtr ? fifo_data_75 : _GEN_1608; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1610 = 7'h4c == RdPtr ? fifo_data_76 : _GEN_1609; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1611 = 7'h4d == RdPtr ? fifo_data_77 : _GEN_1610; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1612 = 7'h4e == RdPtr ? fifo_data_78 : _GEN_1611; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1613 = 7'h4f == RdPtr ? fifo_data_79 : _GEN_1612; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1614 = 7'h50 == RdPtr ? fifo_data_80 : _GEN_1613; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1615 = 7'h51 == RdPtr ? fifo_data_81 : _GEN_1614; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1616 = 7'h52 == RdPtr ? fifo_data_82 : _GEN_1615; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1617 = 7'h53 == RdPtr ? fifo_data_83 : _GEN_1616; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1618 = 7'h54 == RdPtr ? fifo_data_84 : _GEN_1617; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1619 = 7'h55 == RdPtr ? fifo_data_85 : _GEN_1618; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1620 = 7'h56 == RdPtr ? fifo_data_86 : _GEN_1619; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1621 = 7'h57 == RdPtr ? fifo_data_87 : _GEN_1620; // @[dma_ctrl.scala 277:45]
|
|
wire [63:0] _GEN_1622 = 7'h58 == RdPtr ? fifo_data_88 : _GEN_1621; // @[dma_ctrl.scala 277:45]
|
|
wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 320:44]
|
|
wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 321:43]
|
|
wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 322:37]
|
|
wire _T_17235 = ~wrbuf_en; // @[dma_ctrl.scala 323:41]
|
|
wire wrbuf_rst = wrbuf_cmd_sent & _T_17235; // @[dma_ctrl.scala 323:39]
|
|
wire _T_17236 = ~wrbuf_data_en; // @[dma_ctrl.scala 324:41]
|
|
wire wrbuf_data_rst = wrbuf_cmd_sent & _T_17236; // @[dma_ctrl.scala 324:39]
|
|
wire _T_17237 = ~wrbuf_rst; // @[lib.scala 414:73]
|
|
wire _T_17239 = wrbuf_en | wrbuf_rst; // @[lib.scala 414:92]
|
|
wire _T_17240 = _T_17239 & io_dma_bus_clk_en; // @[lib.scala 414:99]
|
|
wire _T_17243 = ~wrbuf_data_rst; // @[lib.scala 414:73]
|
|
wire _T_17245 = wrbuf_data_en | wrbuf_data_rst; // @[lib.scala 414:92]
|
|
wire _T_17246 = _T_17245 & io_dma_bus_clk_en; // @[lib.scala 414:99]
|
|
wire _T_17249 = io_dma_bus_clk_en & wrbuf_en; // @[lib.scala 399:57]
|
|
wire _T_17251 = wrbuf_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 330:60]
|
|
wire _T_17252 = wrbuf_data_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 331:64]
|
|
wire _T_17253 = io_dma_bus_clk_en & wrbuf_data_en; // @[lib.scala 399:57]
|
|
wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 335:41]
|
|
wire _T_17254 = ~axi_mstr_sel; // @[dma_ctrl.scala 336:39]
|
|
wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_17254; // @[dma_ctrl.scala 336:37]
|
|
wire _T_17255 = ~rdbuf_en; // @[dma_ctrl.scala 337:38]
|
|
wire rdbuf_rst = rdbuf_cmd_sent & _T_17255; // @[dma_ctrl.scala 337:36]
|
|
wire _T_17256 = ~rdbuf_rst; // @[lib.scala 414:73]
|
|
wire _T_17258 = rdbuf_en | rdbuf_rst; // @[lib.scala 414:92]
|
|
wire _T_17259 = _T_17258 & io_dma_bus_clk_en; // @[lib.scala 414:99]
|
|
wire _T_17262 = io_dma_bus_clk_en & rdbuf_en; // @[lib.scala 399:57]
|
|
wire _T_17264 = rdbuf_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 342:60]
|
|
wire _T_17265 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 344:40]
|
|
wire _T_17266 = wrbuf_vld & _T_17265; // @[dma_ctrl.scala 344:38]
|
|
wire _T_17269 = wrbuf_data_vld & _T_17265; // @[dma_ctrl.scala 345:43]
|
|
wire _T_17271 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 346:40]
|
|
wire _T_17272 = rdbuf_vld & _T_17271; // @[dma_ctrl.scala 346:38]
|
|
wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 365:26]
|
|
wire _T_17286 = io_dma_bus_clk_en & axi_mstr_prty_en; // @[lib.scala 399:57]
|
|
wire _T_17292 = ~_T_17062[0]; // @[dma_ctrl.scala 369:51]
|
|
wire _T_17293 = _T_17060[0] & _T_17292; // @[dma_ctrl.scala 369:49]
|
|
wire [89:0] _T_17294 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 369:84]
|
|
wire axi_rsp_valid = _T_17293 & _T_17294[0]; // @[dma_ctrl.scala 369:69]
|
|
wire [89:0] _T_17296 = fifo_write >> RspPtr; // @[dma_ctrl.scala 371:40]
|
|
wire axi_rsp_write = _T_17296[0]; // @[dma_ctrl.scala 371:40]
|
|
wire [1:0] _T_17299 = _GEN_992[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 372:64]
|
|
wire _GEN_1639 = 7'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1640 = 7'h2 == RspPtr ? fifo_tag_2 : _GEN_1639; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1641 = 7'h3 == RspPtr ? fifo_tag_3 : _GEN_1640; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1642 = 7'h4 == RspPtr ? fifo_tag_4 : _GEN_1641; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1643 = 7'h5 == RspPtr ? fifo_tag_5 : _GEN_1642; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1644 = 7'h6 == RspPtr ? fifo_tag_6 : _GEN_1643; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1645 = 7'h7 == RspPtr ? fifo_tag_7 : _GEN_1644; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1646 = 7'h8 == RspPtr ? fifo_tag_8 : _GEN_1645; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1647 = 7'h9 == RspPtr ? fifo_tag_9 : _GEN_1646; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1648 = 7'ha == RspPtr ? fifo_tag_10 : _GEN_1647; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1649 = 7'hb == RspPtr ? fifo_tag_11 : _GEN_1648; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1650 = 7'hc == RspPtr ? fifo_tag_12 : _GEN_1649; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1651 = 7'hd == RspPtr ? fifo_tag_13 : _GEN_1650; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1652 = 7'he == RspPtr ? fifo_tag_14 : _GEN_1651; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1653 = 7'hf == RspPtr ? fifo_tag_15 : _GEN_1652; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1654 = 7'h10 == RspPtr ? fifo_tag_16 : _GEN_1653; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1655 = 7'h11 == RspPtr ? fifo_tag_17 : _GEN_1654; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1656 = 7'h12 == RspPtr ? fifo_tag_18 : _GEN_1655; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1657 = 7'h13 == RspPtr ? fifo_tag_19 : _GEN_1656; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1658 = 7'h14 == RspPtr ? fifo_tag_20 : _GEN_1657; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1659 = 7'h15 == RspPtr ? fifo_tag_21 : _GEN_1658; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1660 = 7'h16 == RspPtr ? fifo_tag_22 : _GEN_1659; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1661 = 7'h17 == RspPtr ? fifo_tag_23 : _GEN_1660; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1662 = 7'h18 == RspPtr ? fifo_tag_24 : _GEN_1661; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1663 = 7'h19 == RspPtr ? fifo_tag_25 : _GEN_1662; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1664 = 7'h1a == RspPtr ? fifo_tag_26 : _GEN_1663; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1665 = 7'h1b == RspPtr ? fifo_tag_27 : _GEN_1664; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1666 = 7'h1c == RspPtr ? fifo_tag_28 : _GEN_1665; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1667 = 7'h1d == RspPtr ? fifo_tag_29 : _GEN_1666; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1668 = 7'h1e == RspPtr ? fifo_tag_30 : _GEN_1667; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1669 = 7'h1f == RspPtr ? fifo_tag_31 : _GEN_1668; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1670 = 7'h20 == RspPtr ? fifo_tag_32 : _GEN_1669; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1671 = 7'h21 == RspPtr ? fifo_tag_33 : _GEN_1670; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1672 = 7'h22 == RspPtr ? fifo_tag_34 : _GEN_1671; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1673 = 7'h23 == RspPtr ? fifo_tag_35 : _GEN_1672; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1674 = 7'h24 == RspPtr ? fifo_tag_36 : _GEN_1673; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1675 = 7'h25 == RspPtr ? fifo_tag_37 : _GEN_1674; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1676 = 7'h26 == RspPtr ? fifo_tag_38 : _GEN_1675; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1677 = 7'h27 == RspPtr ? fifo_tag_39 : _GEN_1676; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1678 = 7'h28 == RspPtr ? fifo_tag_40 : _GEN_1677; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1679 = 7'h29 == RspPtr ? fifo_tag_41 : _GEN_1678; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1680 = 7'h2a == RspPtr ? fifo_tag_42 : _GEN_1679; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1681 = 7'h2b == RspPtr ? fifo_tag_43 : _GEN_1680; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1682 = 7'h2c == RspPtr ? fifo_tag_44 : _GEN_1681; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1683 = 7'h2d == RspPtr ? fifo_tag_45 : _GEN_1682; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1684 = 7'h2e == RspPtr ? fifo_tag_46 : _GEN_1683; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1685 = 7'h2f == RspPtr ? fifo_tag_47 : _GEN_1684; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1686 = 7'h30 == RspPtr ? fifo_tag_48 : _GEN_1685; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1687 = 7'h31 == RspPtr ? fifo_tag_49 : _GEN_1686; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1688 = 7'h32 == RspPtr ? fifo_tag_50 : _GEN_1687; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1689 = 7'h33 == RspPtr ? fifo_tag_51 : _GEN_1688; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1690 = 7'h34 == RspPtr ? fifo_tag_52 : _GEN_1689; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1691 = 7'h35 == RspPtr ? fifo_tag_53 : _GEN_1690; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1692 = 7'h36 == RspPtr ? fifo_tag_54 : _GEN_1691; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1693 = 7'h37 == RspPtr ? fifo_tag_55 : _GEN_1692; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1694 = 7'h38 == RspPtr ? fifo_tag_56 : _GEN_1693; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1695 = 7'h39 == RspPtr ? fifo_tag_57 : _GEN_1694; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1696 = 7'h3a == RspPtr ? fifo_tag_58 : _GEN_1695; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1697 = 7'h3b == RspPtr ? fifo_tag_59 : _GEN_1696; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1698 = 7'h3c == RspPtr ? fifo_tag_60 : _GEN_1697; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1699 = 7'h3d == RspPtr ? fifo_tag_61 : _GEN_1698; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1700 = 7'h3e == RspPtr ? fifo_tag_62 : _GEN_1699; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1701 = 7'h3f == RspPtr ? fifo_tag_63 : _GEN_1700; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1702 = 7'h40 == RspPtr ? fifo_tag_64 : _GEN_1701; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1703 = 7'h41 == RspPtr ? fifo_tag_65 : _GEN_1702; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1704 = 7'h42 == RspPtr ? fifo_tag_66 : _GEN_1703; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1705 = 7'h43 == RspPtr ? fifo_tag_67 : _GEN_1704; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1706 = 7'h44 == RspPtr ? fifo_tag_68 : _GEN_1705; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1707 = 7'h45 == RspPtr ? fifo_tag_69 : _GEN_1706; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1708 = 7'h46 == RspPtr ? fifo_tag_70 : _GEN_1707; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1709 = 7'h47 == RspPtr ? fifo_tag_71 : _GEN_1708; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1710 = 7'h48 == RspPtr ? fifo_tag_72 : _GEN_1709; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1711 = 7'h49 == RspPtr ? fifo_tag_73 : _GEN_1710; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1712 = 7'h4a == RspPtr ? fifo_tag_74 : _GEN_1711; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1713 = 7'h4b == RspPtr ? fifo_tag_75 : _GEN_1712; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1714 = 7'h4c == RspPtr ? fifo_tag_76 : _GEN_1713; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1715 = 7'h4d == RspPtr ? fifo_tag_77 : _GEN_1714; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1716 = 7'h4e == RspPtr ? fifo_tag_78 : _GEN_1715; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1717 = 7'h4f == RspPtr ? fifo_tag_79 : _GEN_1716; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1718 = 7'h50 == RspPtr ? fifo_tag_80 : _GEN_1717; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1719 = 7'h51 == RspPtr ? fifo_tag_81 : _GEN_1718; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1720 = 7'h52 == RspPtr ? fifo_tag_82 : _GEN_1719; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1721 = 7'h53 == RspPtr ? fifo_tag_83 : _GEN_1720; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1722 = 7'h54 == RspPtr ? fifo_tag_84 : _GEN_1721; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1723 = 7'h55 == RspPtr ? fifo_tag_85 : _GEN_1722; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1724 = 7'h56 == RspPtr ? fifo_tag_86 : _GEN_1723; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1725 = 7'h57 == RspPtr ? fifo_tag_87 : _GEN_1724; // @[dma_ctrl.scala 378:34]
|
|
wire _GEN_1726 = 7'h58 == RspPtr ? fifo_tag_88 : _GEN_1725; // @[dma_ctrl.scala 378:34]
|
|
wire _T_17301 = ~axi_rsp_write; // @[dma_ctrl.scala 380:48]
|
|
rvclkhdr rvclkhdr ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_io_clk),
|
|
.io_en(rvclkhdr_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_1_io_clk),
|
|
.io_en(rvclkhdr_1_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_2_io_clk),
|
|
.io_en(rvclkhdr_2_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_3_io_clk),
|
|
.io_en(rvclkhdr_3_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_4_io_clk),
|
|
.io_en(rvclkhdr_4_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_5_io_clk),
|
|
.io_en(rvclkhdr_5_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_6_io_clk),
|
|
.io_en(rvclkhdr_6_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_7_io_clk),
|
|
.io_en(rvclkhdr_7_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_8 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_8_io_clk),
|
|
.io_en(rvclkhdr_8_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_9_io_clk),
|
|
.io_en(rvclkhdr_9_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_10 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_10_io_clk),
|
|
.io_en(rvclkhdr_10_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_11_io_clk),
|
|
.io_en(rvclkhdr_11_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_12 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_12_io_clk),
|
|
.io_en(rvclkhdr_12_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_13 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_13_io_clk),
|
|
.io_en(rvclkhdr_13_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_14 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_14_io_clk),
|
|
.io_en(rvclkhdr_14_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_15 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_15_io_clk),
|
|
.io_en(rvclkhdr_15_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_16 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_16_io_clk),
|
|
.io_en(rvclkhdr_16_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_17 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_17_io_clk),
|
|
.io_en(rvclkhdr_17_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_18 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_18_io_clk),
|
|
.io_en(rvclkhdr_18_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_19 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_19_io_clk),
|
|
.io_en(rvclkhdr_19_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_20 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_20_io_clk),
|
|
.io_en(rvclkhdr_20_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_21 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_21_io_clk),
|
|
.io_en(rvclkhdr_21_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_22 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_22_io_clk),
|
|
.io_en(rvclkhdr_22_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_23 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_23_io_clk),
|
|
.io_en(rvclkhdr_23_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_24 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_24_io_clk),
|
|
.io_en(rvclkhdr_24_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_25 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_25_io_clk),
|
|
.io_en(rvclkhdr_25_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_26 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_26_io_clk),
|
|
.io_en(rvclkhdr_26_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_27 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_27_io_clk),
|
|
.io_en(rvclkhdr_27_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_28 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_28_io_clk),
|
|
.io_en(rvclkhdr_28_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_29 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_29_io_clk),
|
|
.io_en(rvclkhdr_29_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_30 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_30_io_clk),
|
|
.io_en(rvclkhdr_30_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_31 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_31_io_clk),
|
|
.io_en(rvclkhdr_31_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_32 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_32_io_clk),
|
|
.io_en(rvclkhdr_32_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_33 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_33_io_clk),
|
|
.io_en(rvclkhdr_33_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_34 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_34_io_clk),
|
|
.io_en(rvclkhdr_34_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_35 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_35_io_clk),
|
|
.io_en(rvclkhdr_35_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_36 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_36_io_clk),
|
|
.io_en(rvclkhdr_36_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_37 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_37_io_clk),
|
|
.io_en(rvclkhdr_37_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_38 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_38_io_clk),
|
|
.io_en(rvclkhdr_38_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_39 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_39_io_clk),
|
|
.io_en(rvclkhdr_39_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_40 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_40_io_clk),
|
|
.io_en(rvclkhdr_40_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_41 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_41_io_clk),
|
|
.io_en(rvclkhdr_41_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_42 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_42_io_clk),
|
|
.io_en(rvclkhdr_42_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_43 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_43_io_clk),
|
|
.io_en(rvclkhdr_43_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_44 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_44_io_clk),
|
|
.io_en(rvclkhdr_44_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_45 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_45_io_clk),
|
|
.io_en(rvclkhdr_45_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_46 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_46_io_clk),
|
|
.io_en(rvclkhdr_46_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_47 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_47_io_clk),
|
|
.io_en(rvclkhdr_47_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_48 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_48_io_clk),
|
|
.io_en(rvclkhdr_48_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_49 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_49_io_clk),
|
|
.io_en(rvclkhdr_49_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_50 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_50_io_clk),
|
|
.io_en(rvclkhdr_50_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_51 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_51_io_clk),
|
|
.io_en(rvclkhdr_51_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_52 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_52_io_clk),
|
|
.io_en(rvclkhdr_52_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_53 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_53_io_clk),
|
|
.io_en(rvclkhdr_53_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_54 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_54_io_clk),
|
|
.io_en(rvclkhdr_54_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_55 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_55_io_clk),
|
|
.io_en(rvclkhdr_55_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_56 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_56_io_clk),
|
|
.io_en(rvclkhdr_56_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_57 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_57_io_clk),
|
|
.io_en(rvclkhdr_57_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_58 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_58_io_clk),
|
|
.io_en(rvclkhdr_58_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_59 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_59_io_clk),
|
|
.io_en(rvclkhdr_59_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_60 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_60_io_clk),
|
|
.io_en(rvclkhdr_60_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_61 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_61_io_clk),
|
|
.io_en(rvclkhdr_61_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_62 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_62_io_clk),
|
|
.io_en(rvclkhdr_62_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_63 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_63_io_clk),
|
|
.io_en(rvclkhdr_63_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_64 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_64_io_clk),
|
|
.io_en(rvclkhdr_64_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_65 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_65_io_clk),
|
|
.io_en(rvclkhdr_65_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_66 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_66_io_clk),
|
|
.io_en(rvclkhdr_66_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_67 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_67_io_clk),
|
|
.io_en(rvclkhdr_67_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_68 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_68_io_clk),
|
|
.io_en(rvclkhdr_68_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_69 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_69_io_clk),
|
|
.io_en(rvclkhdr_69_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_70 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_70_io_clk),
|
|
.io_en(rvclkhdr_70_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_71 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_71_io_clk),
|
|
.io_en(rvclkhdr_71_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_72 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_72_io_clk),
|
|
.io_en(rvclkhdr_72_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_73 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_73_io_clk),
|
|
.io_en(rvclkhdr_73_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_74 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_74_io_clk),
|
|
.io_en(rvclkhdr_74_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_75 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_75_io_clk),
|
|
.io_en(rvclkhdr_75_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_76 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_76_io_clk),
|
|
.io_en(rvclkhdr_76_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_77 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_77_io_clk),
|
|
.io_en(rvclkhdr_77_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_78 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_78_io_clk),
|
|
.io_en(rvclkhdr_78_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_79 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_79_io_clk),
|
|
.io_en(rvclkhdr_79_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_80 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_80_io_clk),
|
|
.io_en(rvclkhdr_80_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_81 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_81_io_clk),
|
|
.io_en(rvclkhdr_81_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_82 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_82_io_clk),
|
|
.io_en(rvclkhdr_82_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_83 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_83_io_clk),
|
|
.io_en(rvclkhdr_83_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_84 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_84_io_clk),
|
|
.io_en(rvclkhdr_84_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_85 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_85_io_clk),
|
|
.io_en(rvclkhdr_85_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_86 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_86_io_clk),
|
|
.io_en(rvclkhdr_86_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_87 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_87_io_clk),
|
|
.io_en(rvclkhdr_87_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_88 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_88_io_clk),
|
|
.io_en(rvclkhdr_88_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_89 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_89_io_clk),
|
|
.io_en(rvclkhdr_89_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_90 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_90_io_clk),
|
|
.io_en(rvclkhdr_90_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_91 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_91_io_clk),
|
|
.io_en(rvclkhdr_91_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_92 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_92_io_clk),
|
|
.io_en(rvclkhdr_92_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_93 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_93_io_clk),
|
|
.io_en(rvclkhdr_93_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_94 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_94_io_clk),
|
|
.io_en(rvclkhdr_94_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_95 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_95_io_clk),
|
|
.io_en(rvclkhdr_95_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_96 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_96_io_clk),
|
|
.io_en(rvclkhdr_96_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_97 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_97_io_clk),
|
|
.io_en(rvclkhdr_97_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_98 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_98_io_clk),
|
|
.io_en(rvclkhdr_98_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_99 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_99_io_clk),
|
|
.io_en(rvclkhdr_99_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_100 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_100_io_clk),
|
|
.io_en(rvclkhdr_100_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_101 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_101_io_clk),
|
|
.io_en(rvclkhdr_101_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_102 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_102_io_clk),
|
|
.io_en(rvclkhdr_102_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_103 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_103_io_clk),
|
|
.io_en(rvclkhdr_103_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_104 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_104_io_clk),
|
|
.io_en(rvclkhdr_104_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_105 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_105_io_clk),
|
|
.io_en(rvclkhdr_105_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_106 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_106_io_clk),
|
|
.io_en(rvclkhdr_106_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_107 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_107_io_clk),
|
|
.io_en(rvclkhdr_107_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_108 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_108_io_clk),
|
|
.io_en(rvclkhdr_108_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_109 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_109_io_clk),
|
|
.io_en(rvclkhdr_109_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_110 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_110_io_clk),
|
|
.io_en(rvclkhdr_110_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_111 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_111_io_clk),
|
|
.io_en(rvclkhdr_111_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_112 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_112_io_clk),
|
|
.io_en(rvclkhdr_112_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_113 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_113_io_clk),
|
|
.io_en(rvclkhdr_113_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_114 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_114_io_clk),
|
|
.io_en(rvclkhdr_114_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_115 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_115_io_clk),
|
|
.io_en(rvclkhdr_115_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_116 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_116_io_clk),
|
|
.io_en(rvclkhdr_116_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_117 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_117_io_clk),
|
|
.io_en(rvclkhdr_117_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_118 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_118_io_clk),
|
|
.io_en(rvclkhdr_118_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_119 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_119_io_clk),
|
|
.io_en(rvclkhdr_119_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_120 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_120_io_clk),
|
|
.io_en(rvclkhdr_120_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_121 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_121_io_clk),
|
|
.io_en(rvclkhdr_121_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_122 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_122_io_clk),
|
|
.io_en(rvclkhdr_122_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_123 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_123_io_clk),
|
|
.io_en(rvclkhdr_123_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_124 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_124_io_clk),
|
|
.io_en(rvclkhdr_124_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_125 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_125_io_clk),
|
|
.io_en(rvclkhdr_125_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_126 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_126_io_clk),
|
|
.io_en(rvclkhdr_126_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_127 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_127_io_clk),
|
|
.io_en(rvclkhdr_127_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_128 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_128_io_clk),
|
|
.io_en(rvclkhdr_128_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_129 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_129_io_clk),
|
|
.io_en(rvclkhdr_129_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_130 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_130_io_clk),
|
|
.io_en(rvclkhdr_130_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_131 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_131_io_clk),
|
|
.io_en(rvclkhdr_131_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_132 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_132_io_clk),
|
|
.io_en(rvclkhdr_132_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_133 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_133_io_clk),
|
|
.io_en(rvclkhdr_133_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_134 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_134_io_clk),
|
|
.io_en(rvclkhdr_134_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_135 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_135_io_clk),
|
|
.io_en(rvclkhdr_135_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_136 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_136_io_clk),
|
|
.io_en(rvclkhdr_136_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_137 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_137_io_clk),
|
|
.io_en(rvclkhdr_137_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_138 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_138_io_clk),
|
|
.io_en(rvclkhdr_138_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_139 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_139_io_clk),
|
|
.io_en(rvclkhdr_139_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_140 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_140_io_clk),
|
|
.io_en(rvclkhdr_140_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_141 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_141_io_clk),
|
|
.io_en(rvclkhdr_141_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_142 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_142_io_clk),
|
|
.io_en(rvclkhdr_142_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_143 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_143_io_clk),
|
|
.io_en(rvclkhdr_143_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_144 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_144_io_clk),
|
|
.io_en(rvclkhdr_144_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_145 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_145_io_clk),
|
|
.io_en(rvclkhdr_145_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_146 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_146_io_clk),
|
|
.io_en(rvclkhdr_146_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_147 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_147_io_clk),
|
|
.io_en(rvclkhdr_147_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_148 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_148_io_clk),
|
|
.io_en(rvclkhdr_148_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_149 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_149_io_clk),
|
|
.io_en(rvclkhdr_149_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_150 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_150_io_clk),
|
|
.io_en(rvclkhdr_150_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_151 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_151_io_clk),
|
|
.io_en(rvclkhdr_151_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_152 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_152_io_clk),
|
|
.io_en(rvclkhdr_152_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_153 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_153_io_clk),
|
|
.io_en(rvclkhdr_153_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_154 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_154_io_clk),
|
|
.io_en(rvclkhdr_154_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_155 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_155_io_clk),
|
|
.io_en(rvclkhdr_155_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_156 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_156_io_clk),
|
|
.io_en(rvclkhdr_156_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_157 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_157_io_clk),
|
|
.io_en(rvclkhdr_157_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_158 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_158_io_clk),
|
|
.io_en(rvclkhdr_158_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_159 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_159_io_clk),
|
|
.io_en(rvclkhdr_159_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_160 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_160_io_clk),
|
|
.io_en(rvclkhdr_160_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_161 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_161_io_clk),
|
|
.io_en(rvclkhdr_161_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_162 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_162_io_clk),
|
|
.io_en(rvclkhdr_162_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_163 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_163_io_clk),
|
|
.io_en(rvclkhdr_163_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_164 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_164_io_clk),
|
|
.io_en(rvclkhdr_164_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_165 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_165_io_clk),
|
|
.io_en(rvclkhdr_165_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_166 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_166_io_clk),
|
|
.io_en(rvclkhdr_166_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_167 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_167_io_clk),
|
|
.io_en(rvclkhdr_167_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_168 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_168_io_clk),
|
|
.io_en(rvclkhdr_168_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_169 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_169_io_clk),
|
|
.io_en(rvclkhdr_169_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_170 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_170_io_clk),
|
|
.io_en(rvclkhdr_170_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_171 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_171_io_clk),
|
|
.io_en(rvclkhdr_171_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_172 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_172_io_clk),
|
|
.io_en(rvclkhdr_172_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_173 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_173_io_clk),
|
|
.io_en(rvclkhdr_173_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_174 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_174_io_clk),
|
|
.io_en(rvclkhdr_174_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_175 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_175_io_clk),
|
|
.io_en(rvclkhdr_175_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_176 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_176_io_clk),
|
|
.io_en(rvclkhdr_176_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_177 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_177_io_clk),
|
|
.io_en(rvclkhdr_177_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_178 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_178_io_clk),
|
|
.io_en(rvclkhdr_178_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_179 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_179_io_clk),
|
|
.io_en(rvclkhdr_179_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_180 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_180_io_clk),
|
|
.io_en(rvclkhdr_180_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_181 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_181_io_clk),
|
|
.io_en(rvclkhdr_181_io_en)
|
|
);
|
|
rvclkhdr rvclkhdr_182 ( // @[lib.scala 422:23]
|
|
.io_clk(rvclkhdr_182_io_clk),
|
|
.io_en(rvclkhdr_182_io_en)
|
|
);
|
|
assign io_dma_dbg_cmd_done = _T_17064 & _T_17065[0]; // @[dma_ctrl.scala 220:23]
|
|
assign io_dma_dbg_cmd_fail = |_GEN_992; // @[dma_ctrl.scala 221:27]
|
|
assign io_dma_dbg_rddata = _T_17089 | _T_17088; // @[dma_ctrl.scala 226:26]
|
|
assign io_dbg_dma_dma_dbg_ready = fifo_empty & io_dbg_dma_dbg_dma_bubble; // @[dma_ctrl.scala 219:31]
|
|
assign io_dec_dma_dctl_dma_dma_dccm_stall_any = _T_17138 & _T_17139; // @[dma_ctrl.scala 250:42]
|
|
assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_2532; // @[dma_ctrl.scala 282:42]
|
|
assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 283:42]
|
|
assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_2531 & _T_2532; // @[dma_ctrl.scala 284:42]
|
|
assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_2531 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 285:42]
|
|
assign io_dec_dma_tlu_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 251:41]
|
|
assign io_dec_dma_tlu_dma_dma_iccm_stall_any = _T_17141 & _T_17139; // @[dma_ctrl.scala 252:41]
|
|
assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_17138 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 263:44]
|
|
assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[dma_ctrl.scala 270:39]
|
|
assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_17195 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 272:44]
|
|
assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_17197[0]; // @[dma_ctrl.scala 275:44]
|
|
assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[dma_ctrl.scala 278:40]
|
|
assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = _T_17182 ? _T_17186 : dma_mem_addr_int; // @[dma_ctrl.scala 269:45]
|
|
assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = 7'h59 == RdPtr ? fifo_data_89 : _GEN_1622; // @[dma_ctrl.scala 277:45]
|
|
assign io_lsu_dma_dma_mem_tag = RdPtr[2:0]; // @[dma_ctrl.scala 265:32]
|
|
assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dma_ctrl.scala 253:41]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_17141 & io_iccm_ready; // @[dma_ctrl.scala 264:44]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[dma_ctrl.scala 271:39]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 273:37]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 276:40]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[dma_ctrl.scala 279:40]
|
|
assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 266:38]
|
|
assign io_dma_axi_aw_ready = ~_T_17266; // @[dma_ctrl.scala 344:23]
|
|
assign io_dma_axi_w_ready = ~_T_17269; // @[dma_ctrl.scala 345:23]
|
|
assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 376:29]
|
|
assign io_dma_axi_b_bits_resp = _GEN_992[0] ? 2'h2 : _T_17299; // @[dma_ctrl.scala 377:34]
|
|
assign io_dma_axi_b_bits_id = 7'h59 == RspPtr ? fifo_tag_89 : _GEN_1726; // @[dma_ctrl.scala 378:34]
|
|
assign io_dma_axi_ar_ready = ~_T_17272; // @[dma_ctrl.scala 346:23]
|
|
assign io_dma_axi_r_valid = axi_rsp_valid & _T_17301; // @[dma_ctrl.scala 380:29]
|
|
assign io_dma_axi_r_bits_id = 7'h59 == RspPtr ? fifo_tag_89 : _GEN_1726; // @[dma_ctrl.scala 384:34]
|
|
assign io_dma_axi_r_bits_data = 7'h59 == RspPtr ? fifo_data_89 : _GEN_1261; // @[dma_ctrl.scala 382:34]
|
|
assign io_dma_axi_r_bits_resp = _GEN_992[0] ? 2'h2 : _T_17299; // @[dma_ctrl.scala 381:34]
|
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_5_io_en = fifo_cmd_en[5]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_6_io_en = fifo_cmd_en[6]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_7_io_en = fifo_cmd_en[7]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_8_io_en = fifo_cmd_en[8]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_9_io_en = fifo_cmd_en[9]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_10_io_en = fifo_cmd_en[10]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_11_io_en = fifo_cmd_en[11]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_12_io_en = fifo_cmd_en[12]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_13_io_en = fifo_cmd_en[13]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_14_io_en = fifo_cmd_en[14]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_15_io_en = fifo_cmd_en[15]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_16_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_16_io_en = fifo_cmd_en[16]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_17_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_17_io_en = fifo_cmd_en[17]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_18_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_18_io_en = fifo_cmd_en[18]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_19_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_19_io_en = fifo_cmd_en[19]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_20_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_20_io_en = fifo_cmd_en[20]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_21_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_21_io_en = fifo_cmd_en[21]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_22_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_22_io_en = fifo_cmd_en[22]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_23_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_23_io_en = fifo_cmd_en[23]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_24_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_24_io_en = fifo_cmd_en[24]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_25_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_25_io_en = fifo_cmd_en[25]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_26_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_26_io_en = fifo_cmd_en[26]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_27_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_27_io_en = fifo_cmd_en[27]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_28_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_28_io_en = fifo_cmd_en[28]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_29_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_29_io_en = fifo_cmd_en[29]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_30_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_30_io_en = fifo_cmd_en[30]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_31_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_31_io_en = fifo_cmd_en[31]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_32_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_32_io_en = fifo_cmd_en[32]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_33_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_33_io_en = fifo_cmd_en[33]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_34_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_34_io_en = fifo_cmd_en[34]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_35_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_35_io_en = fifo_cmd_en[35]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_36_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_36_io_en = fifo_cmd_en[36]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_37_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_37_io_en = fifo_cmd_en[37]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_38_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_38_io_en = fifo_cmd_en[38]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_39_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_39_io_en = fifo_cmd_en[39]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_40_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_40_io_en = fifo_cmd_en[40]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_41_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_41_io_en = fifo_cmd_en[41]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_42_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_42_io_en = fifo_cmd_en[42]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_43_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_43_io_en = fifo_cmd_en[43]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_44_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_44_io_en = fifo_cmd_en[44]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_45_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_45_io_en = fifo_cmd_en[45]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_46_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_46_io_en = fifo_cmd_en[46]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_47_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_47_io_en = fifo_cmd_en[47]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_48_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_48_io_en = fifo_cmd_en[48]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_49_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_49_io_en = fifo_cmd_en[49]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_50_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_50_io_en = fifo_cmd_en[50]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_51_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_51_io_en = fifo_cmd_en[51]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_52_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_52_io_en = fifo_cmd_en[52]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_53_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_53_io_en = fifo_cmd_en[53]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_54_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_54_io_en = fifo_cmd_en[54]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_55_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_55_io_en = fifo_cmd_en[55]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_56_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_56_io_en = fifo_cmd_en[56]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_57_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_57_io_en = fifo_cmd_en[57]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_58_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_58_io_en = fifo_cmd_en[58]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_59_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_59_io_en = fifo_cmd_en[59]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_60_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_60_io_en = fifo_cmd_en[60]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_61_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_61_io_en = fifo_cmd_en[61]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_62_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_62_io_en = fifo_cmd_en[62]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_63_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_63_io_en = fifo_cmd_en[63]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_64_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_64_io_en = fifo_cmd_en[64]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_65_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_65_io_en = fifo_cmd_en[65]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_66_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_66_io_en = fifo_cmd_en[66]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_67_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_67_io_en = fifo_cmd_en[67]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_68_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_68_io_en = fifo_cmd_en[68]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_69_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_69_io_en = fifo_cmd_en[69]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_70_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_70_io_en = fifo_cmd_en[70]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_71_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_71_io_en = fifo_cmd_en[71]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_72_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_72_io_en = fifo_cmd_en[72]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_73_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_73_io_en = fifo_cmd_en[73]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_74_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_74_io_en = fifo_cmd_en[74]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_75_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_75_io_en = fifo_cmd_en[75]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_76_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_76_io_en = fifo_cmd_en[76]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_77_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_77_io_en = fifo_cmd_en[77]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_78_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_78_io_en = fifo_cmd_en[78]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_79_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_79_io_en = fifo_cmd_en[79]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_80_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_80_io_en = fifo_cmd_en[80]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_81_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_81_io_en = fifo_cmd_en[81]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_82_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_82_io_en = fifo_cmd_en[82]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_83_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_83_io_en = fifo_cmd_en[83]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_84_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_84_io_en = fifo_cmd_en[84]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_85_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_85_io_en = fifo_cmd_en[85]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_86_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_86_io_en = fifo_cmd_en[86]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_87_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_87_io_en = fifo_cmd_en[87]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_88_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_88_io_en = fifo_cmd_en[88]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_89_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_89_io_en = fifo_cmd_en[89]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_90_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_90_io_en = fifo_data_en[0]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_91_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_91_io_en = fifo_data_en[1]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_92_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_92_io_en = fifo_data_en[2]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_93_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_93_io_en = fifo_data_en[3]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_94_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_94_io_en = fifo_data_en[4]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_95_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_95_io_en = fifo_data_en[5]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_96_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_96_io_en = fifo_data_en[6]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_97_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_97_io_en = fifo_data_en[7]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_98_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_98_io_en = fifo_data_en[8]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_99_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_99_io_en = fifo_data_en[9]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_100_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_100_io_en = fifo_data_en[10]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_101_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_101_io_en = fifo_data_en[11]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_102_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_102_io_en = fifo_data_en[12]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_103_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_103_io_en = fifo_data_en[13]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_104_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_104_io_en = fifo_data_en[14]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_105_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_105_io_en = fifo_data_en[15]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_106_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_106_io_en = fifo_data_en[16]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_107_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_107_io_en = fifo_data_en[17]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_108_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_108_io_en = fifo_data_en[18]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_109_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_109_io_en = fifo_data_en[19]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_110_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_110_io_en = fifo_data_en[20]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_111_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_111_io_en = fifo_data_en[21]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_112_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_112_io_en = fifo_data_en[22]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_113_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_113_io_en = fifo_data_en[23]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_114_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_114_io_en = fifo_data_en[24]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_115_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_115_io_en = fifo_data_en[25]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_116_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_116_io_en = fifo_data_en[26]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_117_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_117_io_en = fifo_data_en[27]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_118_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_118_io_en = fifo_data_en[28]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_119_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_119_io_en = fifo_data_en[29]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_120_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_120_io_en = fifo_data_en[30]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_121_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_121_io_en = fifo_data_en[31]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_122_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_122_io_en = fifo_data_en[32]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_123_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_123_io_en = fifo_data_en[33]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_124_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_124_io_en = fifo_data_en[34]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_125_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_125_io_en = fifo_data_en[35]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_126_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_126_io_en = fifo_data_en[36]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_127_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_127_io_en = fifo_data_en[37]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_128_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_128_io_en = fifo_data_en[38]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_129_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_129_io_en = fifo_data_en[39]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_130_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_130_io_en = fifo_data_en[40]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_131_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_131_io_en = fifo_data_en[41]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_132_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_132_io_en = fifo_data_en[42]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_133_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_133_io_en = fifo_data_en[43]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_134_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_134_io_en = fifo_data_en[44]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_135_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_135_io_en = fifo_data_en[45]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_136_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_136_io_en = fifo_data_en[46]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_137_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_137_io_en = fifo_data_en[47]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_138_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_138_io_en = fifo_data_en[48]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_139_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_139_io_en = fifo_data_en[49]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_140_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_140_io_en = fifo_data_en[50]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_141_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_141_io_en = fifo_data_en[51]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_142_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_142_io_en = fifo_data_en[52]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_143_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_143_io_en = fifo_data_en[53]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_144_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_144_io_en = fifo_data_en[54]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_145_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_145_io_en = fifo_data_en[55]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_146_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_146_io_en = fifo_data_en[56]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_147_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_147_io_en = fifo_data_en[57]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_148_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_148_io_en = fifo_data_en[58]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_149_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_149_io_en = fifo_data_en[59]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_150_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_150_io_en = fifo_data_en[60]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_151_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_151_io_en = fifo_data_en[61]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_152_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_152_io_en = fifo_data_en[62]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_153_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_153_io_en = fifo_data_en[63]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_154_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_154_io_en = fifo_data_en[64]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_155_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_155_io_en = fifo_data_en[65]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_156_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_156_io_en = fifo_data_en[66]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_157_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_157_io_en = fifo_data_en[67]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_158_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_158_io_en = fifo_data_en[68]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_159_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_159_io_en = fifo_data_en[69]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_160_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_160_io_en = fifo_data_en[70]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_161_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_161_io_en = fifo_data_en[71]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_162_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_162_io_en = fifo_data_en[72]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_163_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_163_io_en = fifo_data_en[73]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_164_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_164_io_en = fifo_data_en[74]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_165_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_165_io_en = fifo_data_en[75]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_166_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_166_io_en = fifo_data_en[76]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_167_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_167_io_en = fifo_data_en[77]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_168_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_168_io_en = fifo_data_en[78]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_169_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_169_io_en = fifo_data_en[79]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_170_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_170_io_en = fifo_data_en[80]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_171_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_171_io_en = fifo_data_en[81]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_172_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_172_io_en = fifo_data_en[82]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_173_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_173_io_en = fifo_data_en[83]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_174_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_174_io_en = fifo_data_en[84]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_175_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_175_io_en = fifo_data_en[85]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_176_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_176_io_en = fifo_data_en[86]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_177_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_177_io_en = fifo_data_en[87]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_178_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_178_io_en = fifo_data_en[88]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_179_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_179_io_en = fifo_data_en[89]; // @[lib.scala 425:17]
|
|
assign rvclkhdr_180_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_180_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 425:17]
|
|
assign rvclkhdr_181_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_181_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 425:17]
|
|
assign rvclkhdr_182_io_clk = clock; // @[lib.scala 424:18]
|
|
assign rvclkhdr_182_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 425:17]
|
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
integer initvar;
|
|
`endif
|
|
`ifndef SYNTHESIS
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif
|
|
initial begin
|
|
`ifdef RANDOMIZE
|
|
`ifdef INIT_RANDOM
|
|
`INIT_RANDOM
|
|
`endif
|
|
`ifndef VERILATOR
|
|
`ifdef RANDOMIZE_DELAY
|
|
#`RANDOMIZE_DELAY begin end
|
|
`else
|
|
#0.002 begin end
|
|
`endif
|
|
`endif
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RAND_0 = {1{`RANDOM}};
|
|
wrbuf_vld = _RAND_0[0:0];
|
|
_RAND_1 = {1{`RANDOM}};
|
|
wrbuf_data_vld = _RAND_1[0:0];
|
|
_RAND_2 = {1{`RANDOM}};
|
|
rdbuf_vld = _RAND_2[0:0];
|
|
_RAND_3 = {1{`RANDOM}};
|
|
_T_10444 = _RAND_3[0:0];
|
|
_RAND_4 = {1{`RANDOM}};
|
|
_T_10437 = _RAND_4[0:0];
|
|
_RAND_5 = {1{`RANDOM}};
|
|
_T_10430 = _RAND_5[0:0];
|
|
_RAND_6 = {1{`RANDOM}};
|
|
_T_10423 = _RAND_6[0:0];
|
|
_RAND_7 = {1{`RANDOM}};
|
|
_T_10416 = _RAND_7[0:0];
|
|
_RAND_8 = {1{`RANDOM}};
|
|
_T_10409 = _RAND_8[0:0];
|
|
_RAND_9 = {1{`RANDOM}};
|
|
_T_10402 = _RAND_9[0:0];
|
|
_RAND_10 = {1{`RANDOM}};
|
|
_T_10395 = _RAND_10[0:0];
|
|
_RAND_11 = {1{`RANDOM}};
|
|
_T_10388 = _RAND_11[0:0];
|
|
_RAND_12 = {1{`RANDOM}};
|
|
_T_10381 = _RAND_12[0:0];
|
|
_RAND_13 = {1{`RANDOM}};
|
|
_T_10374 = _RAND_13[0:0];
|
|
_RAND_14 = {1{`RANDOM}};
|
|
_T_10367 = _RAND_14[0:0];
|
|
_RAND_15 = {1{`RANDOM}};
|
|
_T_10360 = _RAND_15[0:0];
|
|
_RAND_16 = {1{`RANDOM}};
|
|
_T_10353 = _RAND_16[0:0];
|
|
_RAND_17 = {1{`RANDOM}};
|
|
_T_10346 = _RAND_17[0:0];
|
|
_RAND_18 = {1{`RANDOM}};
|
|
_T_10339 = _RAND_18[0:0];
|
|
_RAND_19 = {1{`RANDOM}};
|
|
_T_10332 = _RAND_19[0:0];
|
|
_RAND_20 = {1{`RANDOM}};
|
|
_T_10325 = _RAND_20[0:0];
|
|
_RAND_21 = {1{`RANDOM}};
|
|
_T_10318 = _RAND_21[0:0];
|
|
_RAND_22 = {1{`RANDOM}};
|
|
_T_10311 = _RAND_22[0:0];
|
|
_RAND_23 = {1{`RANDOM}};
|
|
_T_10304 = _RAND_23[0:0];
|
|
_RAND_24 = {1{`RANDOM}};
|
|
_T_10297 = _RAND_24[0:0];
|
|
_RAND_25 = {1{`RANDOM}};
|
|
_T_10290 = _RAND_25[0:0];
|
|
_RAND_26 = {1{`RANDOM}};
|
|
_T_10283 = _RAND_26[0:0];
|
|
_RAND_27 = {1{`RANDOM}};
|
|
_T_10276 = _RAND_27[0:0];
|
|
_RAND_28 = {1{`RANDOM}};
|
|
_T_10269 = _RAND_28[0:0];
|
|
_RAND_29 = {1{`RANDOM}};
|
|
_T_10262 = _RAND_29[0:0];
|
|
_RAND_30 = {1{`RANDOM}};
|
|
_T_10255 = _RAND_30[0:0];
|
|
_RAND_31 = {1{`RANDOM}};
|
|
_T_10248 = _RAND_31[0:0];
|
|
_RAND_32 = {1{`RANDOM}};
|
|
_T_10241 = _RAND_32[0:0];
|
|
_RAND_33 = {1{`RANDOM}};
|
|
_T_10234 = _RAND_33[0:0];
|
|
_RAND_34 = {1{`RANDOM}};
|
|
_T_10227 = _RAND_34[0:0];
|
|
_RAND_35 = {1{`RANDOM}};
|
|
_T_10220 = _RAND_35[0:0];
|
|
_RAND_36 = {1{`RANDOM}};
|
|
_T_10213 = _RAND_36[0:0];
|
|
_RAND_37 = {1{`RANDOM}};
|
|
_T_10206 = _RAND_37[0:0];
|
|
_RAND_38 = {1{`RANDOM}};
|
|
_T_10199 = _RAND_38[0:0];
|
|
_RAND_39 = {1{`RANDOM}};
|
|
_T_10192 = _RAND_39[0:0];
|
|
_RAND_40 = {1{`RANDOM}};
|
|
_T_10185 = _RAND_40[0:0];
|
|
_RAND_41 = {1{`RANDOM}};
|
|
_T_10178 = _RAND_41[0:0];
|
|
_RAND_42 = {1{`RANDOM}};
|
|
_T_10171 = _RAND_42[0:0];
|
|
_RAND_43 = {1{`RANDOM}};
|
|
_T_10164 = _RAND_43[0:0];
|
|
_RAND_44 = {1{`RANDOM}};
|
|
_T_10157 = _RAND_44[0:0];
|
|
_RAND_45 = {1{`RANDOM}};
|
|
_T_10150 = _RAND_45[0:0];
|
|
_RAND_46 = {1{`RANDOM}};
|
|
_T_10143 = _RAND_46[0:0];
|
|
_RAND_47 = {1{`RANDOM}};
|
|
_T_10136 = _RAND_47[0:0];
|
|
_RAND_48 = {1{`RANDOM}};
|
|
_T_10129 = _RAND_48[0:0];
|
|
_RAND_49 = {1{`RANDOM}};
|
|
_T_10122 = _RAND_49[0:0];
|
|
_RAND_50 = {1{`RANDOM}};
|
|
_T_10115 = _RAND_50[0:0];
|
|
_RAND_51 = {1{`RANDOM}};
|
|
_T_10108 = _RAND_51[0:0];
|
|
_RAND_52 = {1{`RANDOM}};
|
|
_T_10101 = _RAND_52[0:0];
|
|
_RAND_53 = {1{`RANDOM}};
|
|
_T_10094 = _RAND_53[0:0];
|
|
_RAND_54 = {1{`RANDOM}};
|
|
_T_10087 = _RAND_54[0:0];
|
|
_RAND_55 = {1{`RANDOM}};
|
|
_T_10080 = _RAND_55[0:0];
|
|
_RAND_56 = {1{`RANDOM}};
|
|
_T_10073 = _RAND_56[0:0];
|
|
_RAND_57 = {1{`RANDOM}};
|
|
_T_10066 = _RAND_57[0:0];
|
|
_RAND_58 = {1{`RANDOM}};
|
|
_T_10059 = _RAND_58[0:0];
|
|
_RAND_59 = {1{`RANDOM}};
|
|
_T_10052 = _RAND_59[0:0];
|
|
_RAND_60 = {1{`RANDOM}};
|
|
_T_10045 = _RAND_60[0:0];
|
|
_RAND_61 = {1{`RANDOM}};
|
|
_T_10038 = _RAND_61[0:0];
|
|
_RAND_62 = {1{`RANDOM}};
|
|
_T_10031 = _RAND_62[0:0];
|
|
_RAND_63 = {1{`RANDOM}};
|
|
_T_10024 = _RAND_63[0:0];
|
|
_RAND_64 = {1{`RANDOM}};
|
|
_T_10017 = _RAND_64[0:0];
|
|
_RAND_65 = {1{`RANDOM}};
|
|
_T_10010 = _RAND_65[0:0];
|
|
_RAND_66 = {1{`RANDOM}};
|
|
_T_10003 = _RAND_66[0:0];
|
|
_RAND_67 = {1{`RANDOM}};
|
|
_T_9996 = _RAND_67[0:0];
|
|
_RAND_68 = {1{`RANDOM}};
|
|
_T_9989 = _RAND_68[0:0];
|
|
_RAND_69 = {1{`RANDOM}};
|
|
_T_9982 = _RAND_69[0:0];
|
|
_RAND_70 = {1{`RANDOM}};
|
|
_T_9975 = _RAND_70[0:0];
|
|
_RAND_71 = {1{`RANDOM}};
|
|
_T_9968 = _RAND_71[0:0];
|
|
_RAND_72 = {1{`RANDOM}};
|
|
_T_9961 = _RAND_72[0:0];
|
|
_RAND_73 = {1{`RANDOM}};
|
|
_T_9954 = _RAND_73[0:0];
|
|
_RAND_74 = {1{`RANDOM}};
|
|
_T_9947 = _RAND_74[0:0];
|
|
_RAND_75 = {1{`RANDOM}};
|
|
_T_9940 = _RAND_75[0:0];
|
|
_RAND_76 = {1{`RANDOM}};
|
|
_T_9933 = _RAND_76[0:0];
|
|
_RAND_77 = {1{`RANDOM}};
|
|
_T_9926 = _RAND_77[0:0];
|
|
_RAND_78 = {1{`RANDOM}};
|
|
_T_9919 = _RAND_78[0:0];
|
|
_RAND_79 = {1{`RANDOM}};
|
|
_T_9912 = _RAND_79[0:0];
|
|
_RAND_80 = {1{`RANDOM}};
|
|
_T_9905 = _RAND_80[0:0];
|
|
_RAND_81 = {1{`RANDOM}};
|
|
_T_9898 = _RAND_81[0:0];
|
|
_RAND_82 = {1{`RANDOM}};
|
|
_T_9891 = _RAND_82[0:0];
|
|
_RAND_83 = {1{`RANDOM}};
|
|
_T_9884 = _RAND_83[0:0];
|
|
_RAND_84 = {1{`RANDOM}};
|
|
_T_9877 = _RAND_84[0:0];
|
|
_RAND_85 = {1{`RANDOM}};
|
|
_T_9870 = _RAND_85[0:0];
|
|
_RAND_86 = {1{`RANDOM}};
|
|
_T_9863 = _RAND_86[0:0];
|
|
_RAND_87 = {1{`RANDOM}};
|
|
_T_9856 = _RAND_87[0:0];
|
|
_RAND_88 = {1{`RANDOM}};
|
|
_T_9849 = _RAND_88[0:0];
|
|
_RAND_89 = {1{`RANDOM}};
|
|
_T_9842 = _RAND_89[0:0];
|
|
_RAND_90 = {1{`RANDOM}};
|
|
_T_9835 = _RAND_90[0:0];
|
|
_RAND_91 = {1{`RANDOM}};
|
|
_T_9828 = _RAND_91[0:0];
|
|
_RAND_92 = {1{`RANDOM}};
|
|
_T_9821 = _RAND_92[0:0];
|
|
_RAND_93 = {1{`RANDOM}};
|
|
axi_mstr_priority = _RAND_93[0:0];
|
|
_RAND_94 = {1{`RANDOM}};
|
|
wrbuf_addr = _RAND_94[31:0];
|
|
_RAND_95 = {1{`RANDOM}};
|
|
rdbuf_addr = _RAND_95[31:0];
|
|
_RAND_96 = {1{`RANDOM}};
|
|
wrbuf_byteen = _RAND_96[7:0];
|
|
_RAND_97 = {1{`RANDOM}};
|
|
wrbuf_sz = _RAND_97[2:0];
|
|
_RAND_98 = {1{`RANDOM}};
|
|
rdbuf_sz = _RAND_98[2:0];
|
|
_RAND_99 = {1{`RANDOM}};
|
|
dbg_dma_bubble_bus = _RAND_99[0:0];
|
|
_RAND_100 = {1{`RANDOM}};
|
|
WrPtr = _RAND_100[6:0];
|
|
_RAND_101 = {1{`RANDOM}};
|
|
RdPtr = _RAND_101[6:0];
|
|
_RAND_102 = {1{`RANDOM}};
|
|
_T_13411 = _RAND_102[0:0];
|
|
_RAND_103 = {1{`RANDOM}};
|
|
_T_13404 = _RAND_103[0:0];
|
|
_RAND_104 = {1{`RANDOM}};
|
|
_T_13397 = _RAND_104[0:0];
|
|
_RAND_105 = {1{`RANDOM}};
|
|
_T_13390 = _RAND_105[0:0];
|
|
_RAND_106 = {1{`RANDOM}};
|
|
_T_13383 = _RAND_106[0:0];
|
|
_RAND_107 = {1{`RANDOM}};
|
|
_T_13376 = _RAND_107[0:0];
|
|
_RAND_108 = {1{`RANDOM}};
|
|
_T_13369 = _RAND_108[0:0];
|
|
_RAND_109 = {1{`RANDOM}};
|
|
_T_13362 = _RAND_109[0:0];
|
|
_RAND_110 = {1{`RANDOM}};
|
|
_T_13355 = _RAND_110[0:0];
|
|
_RAND_111 = {1{`RANDOM}};
|
|
_T_13348 = _RAND_111[0:0];
|
|
_RAND_112 = {1{`RANDOM}};
|
|
_T_13341 = _RAND_112[0:0];
|
|
_RAND_113 = {1{`RANDOM}};
|
|
_T_13334 = _RAND_113[0:0];
|
|
_RAND_114 = {1{`RANDOM}};
|
|
_T_13327 = _RAND_114[0:0];
|
|
_RAND_115 = {1{`RANDOM}};
|
|
_T_13320 = _RAND_115[0:0];
|
|
_RAND_116 = {1{`RANDOM}};
|
|
_T_13313 = _RAND_116[0:0];
|
|
_RAND_117 = {1{`RANDOM}};
|
|
_T_13306 = _RAND_117[0:0];
|
|
_RAND_118 = {1{`RANDOM}};
|
|
_T_13299 = _RAND_118[0:0];
|
|
_RAND_119 = {1{`RANDOM}};
|
|
_T_13292 = _RAND_119[0:0];
|
|
_RAND_120 = {1{`RANDOM}};
|
|
_T_13285 = _RAND_120[0:0];
|
|
_RAND_121 = {1{`RANDOM}};
|
|
_T_13278 = _RAND_121[0:0];
|
|
_RAND_122 = {1{`RANDOM}};
|
|
_T_13271 = _RAND_122[0:0];
|
|
_RAND_123 = {1{`RANDOM}};
|
|
_T_13264 = _RAND_123[0:0];
|
|
_RAND_124 = {1{`RANDOM}};
|
|
_T_13257 = _RAND_124[0:0];
|
|
_RAND_125 = {1{`RANDOM}};
|
|
_T_13250 = _RAND_125[0:0];
|
|
_RAND_126 = {1{`RANDOM}};
|
|
_T_13243 = _RAND_126[0:0];
|
|
_RAND_127 = {1{`RANDOM}};
|
|
_T_13236 = _RAND_127[0:0];
|
|
_RAND_128 = {1{`RANDOM}};
|
|
_T_13229 = _RAND_128[0:0];
|
|
_RAND_129 = {1{`RANDOM}};
|
|
_T_13222 = _RAND_129[0:0];
|
|
_RAND_130 = {1{`RANDOM}};
|
|
_T_13215 = _RAND_130[0:0];
|
|
_RAND_131 = {1{`RANDOM}};
|
|
_T_13208 = _RAND_131[0:0];
|
|
_RAND_132 = {1{`RANDOM}};
|
|
_T_13201 = _RAND_132[0:0];
|
|
_RAND_133 = {1{`RANDOM}};
|
|
_T_13194 = _RAND_133[0:0];
|
|
_RAND_134 = {1{`RANDOM}};
|
|
_T_13187 = _RAND_134[0:0];
|
|
_RAND_135 = {1{`RANDOM}};
|
|
_T_13180 = _RAND_135[0:0];
|
|
_RAND_136 = {1{`RANDOM}};
|
|
_T_13173 = _RAND_136[0:0];
|
|
_RAND_137 = {1{`RANDOM}};
|
|
_T_13166 = _RAND_137[0:0];
|
|
_RAND_138 = {1{`RANDOM}};
|
|
_T_13159 = _RAND_138[0:0];
|
|
_RAND_139 = {1{`RANDOM}};
|
|
_T_13152 = _RAND_139[0:0];
|
|
_RAND_140 = {1{`RANDOM}};
|
|
_T_13145 = _RAND_140[0:0];
|
|
_RAND_141 = {1{`RANDOM}};
|
|
_T_13138 = _RAND_141[0:0];
|
|
_RAND_142 = {1{`RANDOM}};
|
|
_T_13131 = _RAND_142[0:0];
|
|
_RAND_143 = {1{`RANDOM}};
|
|
_T_13124 = _RAND_143[0:0];
|
|
_RAND_144 = {1{`RANDOM}};
|
|
_T_13117 = _RAND_144[0:0];
|
|
_RAND_145 = {1{`RANDOM}};
|
|
_T_13110 = _RAND_145[0:0];
|
|
_RAND_146 = {1{`RANDOM}};
|
|
_T_13103 = _RAND_146[0:0];
|
|
_RAND_147 = {1{`RANDOM}};
|
|
_T_13096 = _RAND_147[0:0];
|
|
_RAND_148 = {1{`RANDOM}};
|
|
_T_13089 = _RAND_148[0:0];
|
|
_RAND_149 = {1{`RANDOM}};
|
|
_T_13082 = _RAND_149[0:0];
|
|
_RAND_150 = {1{`RANDOM}};
|
|
_T_13075 = _RAND_150[0:0];
|
|
_RAND_151 = {1{`RANDOM}};
|
|
_T_13068 = _RAND_151[0:0];
|
|
_RAND_152 = {1{`RANDOM}};
|
|
_T_13061 = _RAND_152[0:0];
|
|
_RAND_153 = {1{`RANDOM}};
|
|
_T_13054 = _RAND_153[0:0];
|
|
_RAND_154 = {1{`RANDOM}};
|
|
_T_13047 = _RAND_154[0:0];
|
|
_RAND_155 = {1{`RANDOM}};
|
|
_T_13040 = _RAND_155[0:0];
|
|
_RAND_156 = {1{`RANDOM}};
|
|
_T_13033 = _RAND_156[0:0];
|
|
_RAND_157 = {1{`RANDOM}};
|
|
_T_13026 = _RAND_157[0:0];
|
|
_RAND_158 = {1{`RANDOM}};
|
|
_T_13019 = _RAND_158[0:0];
|
|
_RAND_159 = {1{`RANDOM}};
|
|
_T_13012 = _RAND_159[0:0];
|
|
_RAND_160 = {1{`RANDOM}};
|
|
_T_13005 = _RAND_160[0:0];
|
|
_RAND_161 = {1{`RANDOM}};
|
|
_T_12998 = _RAND_161[0:0];
|
|
_RAND_162 = {1{`RANDOM}};
|
|
_T_12991 = _RAND_162[0:0];
|
|
_RAND_163 = {1{`RANDOM}};
|
|
_T_12984 = _RAND_163[0:0];
|
|
_RAND_164 = {1{`RANDOM}};
|
|
_T_12977 = _RAND_164[0:0];
|
|
_RAND_165 = {1{`RANDOM}};
|
|
_T_12970 = _RAND_165[0:0];
|
|
_RAND_166 = {1{`RANDOM}};
|
|
_T_12963 = _RAND_166[0:0];
|
|
_RAND_167 = {1{`RANDOM}};
|
|
_T_12956 = _RAND_167[0:0];
|
|
_RAND_168 = {1{`RANDOM}};
|
|
_T_12949 = _RAND_168[0:0];
|
|
_RAND_169 = {1{`RANDOM}};
|
|
_T_12942 = _RAND_169[0:0];
|
|
_RAND_170 = {1{`RANDOM}};
|
|
_T_12935 = _RAND_170[0:0];
|
|
_RAND_171 = {1{`RANDOM}};
|
|
_T_12928 = _RAND_171[0:0];
|
|
_RAND_172 = {1{`RANDOM}};
|
|
_T_12921 = _RAND_172[0:0];
|
|
_RAND_173 = {1{`RANDOM}};
|
|
_T_12914 = _RAND_173[0:0];
|
|
_RAND_174 = {1{`RANDOM}};
|
|
_T_12907 = _RAND_174[0:0];
|
|
_RAND_175 = {1{`RANDOM}};
|
|
_T_12900 = _RAND_175[0:0];
|
|
_RAND_176 = {1{`RANDOM}};
|
|
_T_12893 = _RAND_176[0:0];
|
|
_RAND_177 = {1{`RANDOM}};
|
|
_T_12886 = _RAND_177[0:0];
|
|
_RAND_178 = {1{`RANDOM}};
|
|
_T_12879 = _RAND_178[0:0];
|
|
_RAND_179 = {1{`RANDOM}};
|
|
_T_12872 = _RAND_179[0:0];
|
|
_RAND_180 = {1{`RANDOM}};
|
|
_T_12865 = _RAND_180[0:0];
|
|
_RAND_181 = {1{`RANDOM}};
|
|
_T_12858 = _RAND_181[0:0];
|
|
_RAND_182 = {1{`RANDOM}};
|
|
_T_12851 = _RAND_182[0:0];
|
|
_RAND_183 = {1{`RANDOM}};
|
|
_T_12844 = _RAND_183[0:0];
|
|
_RAND_184 = {1{`RANDOM}};
|
|
_T_12837 = _RAND_184[0:0];
|
|
_RAND_185 = {1{`RANDOM}};
|
|
_T_12830 = _RAND_185[0:0];
|
|
_RAND_186 = {1{`RANDOM}};
|
|
_T_12823 = _RAND_186[0:0];
|
|
_RAND_187 = {1{`RANDOM}};
|
|
_T_12816 = _RAND_187[0:0];
|
|
_RAND_188 = {1{`RANDOM}};
|
|
_T_12809 = _RAND_188[0:0];
|
|
_RAND_189 = {1{`RANDOM}};
|
|
_T_12802 = _RAND_189[0:0];
|
|
_RAND_190 = {1{`RANDOM}};
|
|
_T_12795 = _RAND_190[0:0];
|
|
_RAND_191 = {1{`RANDOM}};
|
|
_T_12788 = _RAND_191[0:0];
|
|
_RAND_192 = {1{`RANDOM}};
|
|
_T_15745 = _RAND_192[0:0];
|
|
_RAND_193 = {1{`RANDOM}};
|
|
_T_15743 = _RAND_193[0:0];
|
|
_RAND_194 = {1{`RANDOM}};
|
|
_T_15741 = _RAND_194[0:0];
|
|
_RAND_195 = {1{`RANDOM}};
|
|
_T_15739 = _RAND_195[0:0];
|
|
_RAND_196 = {1{`RANDOM}};
|
|
_T_15737 = _RAND_196[0:0];
|
|
_RAND_197 = {1{`RANDOM}};
|
|
_T_15735 = _RAND_197[0:0];
|
|
_RAND_198 = {1{`RANDOM}};
|
|
_T_15733 = _RAND_198[0:0];
|
|
_RAND_199 = {1{`RANDOM}};
|
|
_T_15731 = _RAND_199[0:0];
|
|
_RAND_200 = {1{`RANDOM}};
|
|
_T_15729 = _RAND_200[0:0];
|
|
_RAND_201 = {1{`RANDOM}};
|
|
_T_15727 = _RAND_201[0:0];
|
|
_RAND_202 = {1{`RANDOM}};
|
|
_T_15725 = _RAND_202[0:0];
|
|
_RAND_203 = {1{`RANDOM}};
|
|
_T_15723 = _RAND_203[0:0];
|
|
_RAND_204 = {1{`RANDOM}};
|
|
_T_15721 = _RAND_204[0:0];
|
|
_RAND_205 = {1{`RANDOM}};
|
|
_T_15719 = _RAND_205[0:0];
|
|
_RAND_206 = {1{`RANDOM}};
|
|
_T_15717 = _RAND_206[0:0];
|
|
_RAND_207 = {1{`RANDOM}};
|
|
_T_15715 = _RAND_207[0:0];
|
|
_RAND_208 = {1{`RANDOM}};
|
|
_T_15713 = _RAND_208[0:0];
|
|
_RAND_209 = {1{`RANDOM}};
|
|
_T_15711 = _RAND_209[0:0];
|
|
_RAND_210 = {1{`RANDOM}};
|
|
_T_15709 = _RAND_210[0:0];
|
|
_RAND_211 = {1{`RANDOM}};
|
|
_T_15707 = _RAND_211[0:0];
|
|
_RAND_212 = {1{`RANDOM}};
|
|
_T_15705 = _RAND_212[0:0];
|
|
_RAND_213 = {1{`RANDOM}};
|
|
_T_15703 = _RAND_213[0:0];
|
|
_RAND_214 = {1{`RANDOM}};
|
|
_T_15701 = _RAND_214[0:0];
|
|
_RAND_215 = {1{`RANDOM}};
|
|
_T_15699 = _RAND_215[0:0];
|
|
_RAND_216 = {1{`RANDOM}};
|
|
_T_15697 = _RAND_216[0:0];
|
|
_RAND_217 = {1{`RANDOM}};
|
|
_T_15695 = _RAND_217[0:0];
|
|
_RAND_218 = {1{`RANDOM}};
|
|
_T_15693 = _RAND_218[0:0];
|
|
_RAND_219 = {1{`RANDOM}};
|
|
_T_15691 = _RAND_219[0:0];
|
|
_RAND_220 = {1{`RANDOM}};
|
|
_T_15689 = _RAND_220[0:0];
|
|
_RAND_221 = {1{`RANDOM}};
|
|
_T_15687 = _RAND_221[0:0];
|
|
_RAND_222 = {1{`RANDOM}};
|
|
_T_15685 = _RAND_222[0:0];
|
|
_RAND_223 = {1{`RANDOM}};
|
|
_T_15683 = _RAND_223[0:0];
|
|
_RAND_224 = {1{`RANDOM}};
|
|
_T_15681 = _RAND_224[0:0];
|
|
_RAND_225 = {1{`RANDOM}};
|
|
_T_15679 = _RAND_225[0:0];
|
|
_RAND_226 = {1{`RANDOM}};
|
|
_T_15677 = _RAND_226[0:0];
|
|
_RAND_227 = {1{`RANDOM}};
|
|
_T_15675 = _RAND_227[0:0];
|
|
_RAND_228 = {1{`RANDOM}};
|
|
_T_15673 = _RAND_228[0:0];
|
|
_RAND_229 = {1{`RANDOM}};
|
|
_T_15671 = _RAND_229[0:0];
|
|
_RAND_230 = {1{`RANDOM}};
|
|
_T_15669 = _RAND_230[0:0];
|
|
_RAND_231 = {1{`RANDOM}};
|
|
_T_15667 = _RAND_231[0:0];
|
|
_RAND_232 = {1{`RANDOM}};
|
|
_T_15665 = _RAND_232[0:0];
|
|
_RAND_233 = {1{`RANDOM}};
|
|
_T_15663 = _RAND_233[0:0];
|
|
_RAND_234 = {1{`RANDOM}};
|
|
_T_15661 = _RAND_234[0:0];
|
|
_RAND_235 = {1{`RANDOM}};
|
|
_T_15659 = _RAND_235[0:0];
|
|
_RAND_236 = {1{`RANDOM}};
|
|
_T_15657 = _RAND_236[0:0];
|
|
_RAND_237 = {1{`RANDOM}};
|
|
_T_15655 = _RAND_237[0:0];
|
|
_RAND_238 = {1{`RANDOM}};
|
|
_T_15653 = _RAND_238[0:0];
|
|
_RAND_239 = {1{`RANDOM}};
|
|
_T_15651 = _RAND_239[0:0];
|
|
_RAND_240 = {1{`RANDOM}};
|
|
_T_15649 = _RAND_240[0:0];
|
|
_RAND_241 = {1{`RANDOM}};
|
|
_T_15647 = _RAND_241[0:0];
|
|
_RAND_242 = {1{`RANDOM}};
|
|
_T_15645 = _RAND_242[0:0];
|
|
_RAND_243 = {1{`RANDOM}};
|
|
_T_15643 = _RAND_243[0:0];
|
|
_RAND_244 = {1{`RANDOM}};
|
|
_T_15641 = _RAND_244[0:0];
|
|
_RAND_245 = {1{`RANDOM}};
|
|
_T_15639 = _RAND_245[0:0];
|
|
_RAND_246 = {1{`RANDOM}};
|
|
_T_15637 = _RAND_246[0:0];
|
|
_RAND_247 = {1{`RANDOM}};
|
|
_T_15635 = _RAND_247[0:0];
|
|
_RAND_248 = {1{`RANDOM}};
|
|
_T_15633 = _RAND_248[0:0];
|
|
_RAND_249 = {1{`RANDOM}};
|
|
_T_15631 = _RAND_249[0:0];
|
|
_RAND_250 = {1{`RANDOM}};
|
|
_T_15629 = _RAND_250[0:0];
|
|
_RAND_251 = {1{`RANDOM}};
|
|
_T_15627 = _RAND_251[0:0];
|
|
_RAND_252 = {1{`RANDOM}};
|
|
_T_15625 = _RAND_252[0:0];
|
|
_RAND_253 = {1{`RANDOM}};
|
|
_T_15623 = _RAND_253[0:0];
|
|
_RAND_254 = {1{`RANDOM}};
|
|
_T_15621 = _RAND_254[0:0];
|
|
_RAND_255 = {1{`RANDOM}};
|
|
_T_15619 = _RAND_255[0:0];
|
|
_RAND_256 = {1{`RANDOM}};
|
|
_T_15617 = _RAND_256[0:0];
|
|
_RAND_257 = {1{`RANDOM}};
|
|
_T_15615 = _RAND_257[0:0];
|
|
_RAND_258 = {1{`RANDOM}};
|
|
_T_15613 = _RAND_258[0:0];
|
|
_RAND_259 = {1{`RANDOM}};
|
|
_T_15611 = _RAND_259[0:0];
|
|
_RAND_260 = {1{`RANDOM}};
|
|
_T_15609 = _RAND_260[0:0];
|
|
_RAND_261 = {1{`RANDOM}};
|
|
_T_15607 = _RAND_261[0:0];
|
|
_RAND_262 = {1{`RANDOM}};
|
|
_T_15605 = _RAND_262[0:0];
|
|
_RAND_263 = {1{`RANDOM}};
|
|
_T_15603 = _RAND_263[0:0];
|
|
_RAND_264 = {1{`RANDOM}};
|
|
_T_15601 = _RAND_264[0:0];
|
|
_RAND_265 = {1{`RANDOM}};
|
|
_T_15599 = _RAND_265[0:0];
|
|
_RAND_266 = {1{`RANDOM}};
|
|
_T_15597 = _RAND_266[0:0];
|
|
_RAND_267 = {1{`RANDOM}};
|
|
_T_15595 = _RAND_267[0:0];
|
|
_RAND_268 = {1{`RANDOM}};
|
|
_T_15593 = _RAND_268[0:0];
|
|
_RAND_269 = {1{`RANDOM}};
|
|
_T_15591 = _RAND_269[0:0];
|
|
_RAND_270 = {1{`RANDOM}};
|
|
_T_15589 = _RAND_270[0:0];
|
|
_RAND_271 = {1{`RANDOM}};
|
|
_T_15587 = _RAND_271[0:0];
|
|
_RAND_272 = {1{`RANDOM}};
|
|
_T_15585 = _RAND_272[0:0];
|
|
_RAND_273 = {1{`RANDOM}};
|
|
_T_15583 = _RAND_273[0:0];
|
|
_RAND_274 = {1{`RANDOM}};
|
|
_T_15581 = _RAND_274[0:0];
|
|
_RAND_275 = {1{`RANDOM}};
|
|
_T_15579 = _RAND_275[0:0];
|
|
_RAND_276 = {1{`RANDOM}};
|
|
_T_15577 = _RAND_276[0:0];
|
|
_RAND_277 = {1{`RANDOM}};
|
|
_T_15575 = _RAND_277[0:0];
|
|
_RAND_278 = {1{`RANDOM}};
|
|
_T_15573 = _RAND_278[0:0];
|
|
_RAND_279 = {1{`RANDOM}};
|
|
_T_15571 = _RAND_279[0:0];
|
|
_RAND_280 = {1{`RANDOM}};
|
|
_T_15569 = _RAND_280[0:0];
|
|
_RAND_281 = {1{`RANDOM}};
|
|
_T_15567 = _RAND_281[0:0];
|
|
_RAND_282 = {1{`RANDOM}};
|
|
fifo_addr_89 = _RAND_282[31:0];
|
|
_RAND_283 = {1{`RANDOM}};
|
|
fifo_addr_88 = _RAND_283[31:0];
|
|
_RAND_284 = {1{`RANDOM}};
|
|
fifo_addr_87 = _RAND_284[31:0];
|
|
_RAND_285 = {1{`RANDOM}};
|
|
fifo_addr_86 = _RAND_285[31:0];
|
|
_RAND_286 = {1{`RANDOM}};
|
|
fifo_addr_85 = _RAND_286[31:0];
|
|
_RAND_287 = {1{`RANDOM}};
|
|
fifo_addr_84 = _RAND_287[31:0];
|
|
_RAND_288 = {1{`RANDOM}};
|
|
fifo_addr_83 = _RAND_288[31:0];
|
|
_RAND_289 = {1{`RANDOM}};
|
|
fifo_addr_82 = _RAND_289[31:0];
|
|
_RAND_290 = {1{`RANDOM}};
|
|
fifo_addr_81 = _RAND_290[31:0];
|
|
_RAND_291 = {1{`RANDOM}};
|
|
fifo_addr_80 = _RAND_291[31:0];
|
|
_RAND_292 = {1{`RANDOM}};
|
|
fifo_addr_79 = _RAND_292[31:0];
|
|
_RAND_293 = {1{`RANDOM}};
|
|
fifo_addr_78 = _RAND_293[31:0];
|
|
_RAND_294 = {1{`RANDOM}};
|
|
fifo_addr_77 = _RAND_294[31:0];
|
|
_RAND_295 = {1{`RANDOM}};
|
|
fifo_addr_76 = _RAND_295[31:0];
|
|
_RAND_296 = {1{`RANDOM}};
|
|
fifo_addr_75 = _RAND_296[31:0];
|
|
_RAND_297 = {1{`RANDOM}};
|
|
fifo_addr_74 = _RAND_297[31:0];
|
|
_RAND_298 = {1{`RANDOM}};
|
|
fifo_addr_73 = _RAND_298[31:0];
|
|
_RAND_299 = {1{`RANDOM}};
|
|
fifo_addr_72 = _RAND_299[31:0];
|
|
_RAND_300 = {1{`RANDOM}};
|
|
fifo_addr_71 = _RAND_300[31:0];
|
|
_RAND_301 = {1{`RANDOM}};
|
|
fifo_addr_70 = _RAND_301[31:0];
|
|
_RAND_302 = {1{`RANDOM}};
|
|
fifo_addr_69 = _RAND_302[31:0];
|
|
_RAND_303 = {1{`RANDOM}};
|
|
fifo_addr_68 = _RAND_303[31:0];
|
|
_RAND_304 = {1{`RANDOM}};
|
|
fifo_addr_67 = _RAND_304[31:0];
|
|
_RAND_305 = {1{`RANDOM}};
|
|
fifo_addr_66 = _RAND_305[31:0];
|
|
_RAND_306 = {1{`RANDOM}};
|
|
fifo_addr_65 = _RAND_306[31:0];
|
|
_RAND_307 = {1{`RANDOM}};
|
|
fifo_addr_64 = _RAND_307[31:0];
|
|
_RAND_308 = {1{`RANDOM}};
|
|
fifo_addr_63 = _RAND_308[31:0];
|
|
_RAND_309 = {1{`RANDOM}};
|
|
fifo_addr_62 = _RAND_309[31:0];
|
|
_RAND_310 = {1{`RANDOM}};
|
|
fifo_addr_61 = _RAND_310[31:0];
|
|
_RAND_311 = {1{`RANDOM}};
|
|
fifo_addr_60 = _RAND_311[31:0];
|
|
_RAND_312 = {1{`RANDOM}};
|
|
fifo_addr_59 = _RAND_312[31:0];
|
|
_RAND_313 = {1{`RANDOM}};
|
|
fifo_addr_58 = _RAND_313[31:0];
|
|
_RAND_314 = {1{`RANDOM}};
|
|
fifo_addr_57 = _RAND_314[31:0];
|
|
_RAND_315 = {1{`RANDOM}};
|
|
fifo_addr_56 = _RAND_315[31:0];
|
|
_RAND_316 = {1{`RANDOM}};
|
|
fifo_addr_55 = _RAND_316[31:0];
|
|
_RAND_317 = {1{`RANDOM}};
|
|
fifo_addr_54 = _RAND_317[31:0];
|
|
_RAND_318 = {1{`RANDOM}};
|
|
fifo_addr_53 = _RAND_318[31:0];
|
|
_RAND_319 = {1{`RANDOM}};
|
|
fifo_addr_52 = _RAND_319[31:0];
|
|
_RAND_320 = {1{`RANDOM}};
|
|
fifo_addr_51 = _RAND_320[31:0];
|
|
_RAND_321 = {1{`RANDOM}};
|
|
fifo_addr_50 = _RAND_321[31:0];
|
|
_RAND_322 = {1{`RANDOM}};
|
|
fifo_addr_49 = _RAND_322[31:0];
|
|
_RAND_323 = {1{`RANDOM}};
|
|
fifo_addr_48 = _RAND_323[31:0];
|
|
_RAND_324 = {1{`RANDOM}};
|
|
fifo_addr_47 = _RAND_324[31:0];
|
|
_RAND_325 = {1{`RANDOM}};
|
|
fifo_addr_46 = _RAND_325[31:0];
|
|
_RAND_326 = {1{`RANDOM}};
|
|
fifo_addr_45 = _RAND_326[31:0];
|
|
_RAND_327 = {1{`RANDOM}};
|
|
fifo_addr_44 = _RAND_327[31:0];
|
|
_RAND_328 = {1{`RANDOM}};
|
|
fifo_addr_43 = _RAND_328[31:0];
|
|
_RAND_329 = {1{`RANDOM}};
|
|
fifo_addr_42 = _RAND_329[31:0];
|
|
_RAND_330 = {1{`RANDOM}};
|
|
fifo_addr_41 = _RAND_330[31:0];
|
|
_RAND_331 = {1{`RANDOM}};
|
|
fifo_addr_40 = _RAND_331[31:0];
|
|
_RAND_332 = {1{`RANDOM}};
|
|
fifo_addr_39 = _RAND_332[31:0];
|
|
_RAND_333 = {1{`RANDOM}};
|
|
fifo_addr_38 = _RAND_333[31:0];
|
|
_RAND_334 = {1{`RANDOM}};
|
|
fifo_addr_37 = _RAND_334[31:0];
|
|
_RAND_335 = {1{`RANDOM}};
|
|
fifo_addr_36 = _RAND_335[31:0];
|
|
_RAND_336 = {1{`RANDOM}};
|
|
fifo_addr_35 = _RAND_336[31:0];
|
|
_RAND_337 = {1{`RANDOM}};
|
|
fifo_addr_34 = _RAND_337[31:0];
|
|
_RAND_338 = {1{`RANDOM}};
|
|
fifo_addr_33 = _RAND_338[31:0];
|
|
_RAND_339 = {1{`RANDOM}};
|
|
fifo_addr_32 = _RAND_339[31:0];
|
|
_RAND_340 = {1{`RANDOM}};
|
|
fifo_addr_31 = _RAND_340[31:0];
|
|
_RAND_341 = {1{`RANDOM}};
|
|
fifo_addr_30 = _RAND_341[31:0];
|
|
_RAND_342 = {1{`RANDOM}};
|
|
fifo_addr_29 = _RAND_342[31:0];
|
|
_RAND_343 = {1{`RANDOM}};
|
|
fifo_addr_28 = _RAND_343[31:0];
|
|
_RAND_344 = {1{`RANDOM}};
|
|
fifo_addr_27 = _RAND_344[31:0];
|
|
_RAND_345 = {1{`RANDOM}};
|
|
fifo_addr_26 = _RAND_345[31:0];
|
|
_RAND_346 = {1{`RANDOM}};
|
|
fifo_addr_25 = _RAND_346[31:0];
|
|
_RAND_347 = {1{`RANDOM}};
|
|
fifo_addr_24 = _RAND_347[31:0];
|
|
_RAND_348 = {1{`RANDOM}};
|
|
fifo_addr_23 = _RAND_348[31:0];
|
|
_RAND_349 = {1{`RANDOM}};
|
|
fifo_addr_22 = _RAND_349[31:0];
|
|
_RAND_350 = {1{`RANDOM}};
|
|
fifo_addr_21 = _RAND_350[31:0];
|
|
_RAND_351 = {1{`RANDOM}};
|
|
fifo_addr_20 = _RAND_351[31:0];
|
|
_RAND_352 = {1{`RANDOM}};
|
|
fifo_addr_19 = _RAND_352[31:0];
|
|
_RAND_353 = {1{`RANDOM}};
|
|
fifo_addr_18 = _RAND_353[31:0];
|
|
_RAND_354 = {1{`RANDOM}};
|
|
fifo_addr_17 = _RAND_354[31:0];
|
|
_RAND_355 = {1{`RANDOM}};
|
|
fifo_addr_16 = _RAND_355[31:0];
|
|
_RAND_356 = {1{`RANDOM}};
|
|
fifo_addr_15 = _RAND_356[31:0];
|
|
_RAND_357 = {1{`RANDOM}};
|
|
fifo_addr_14 = _RAND_357[31:0];
|
|
_RAND_358 = {1{`RANDOM}};
|
|
fifo_addr_13 = _RAND_358[31:0];
|
|
_RAND_359 = {1{`RANDOM}};
|
|
fifo_addr_12 = _RAND_359[31:0];
|
|
_RAND_360 = {1{`RANDOM}};
|
|
fifo_addr_11 = _RAND_360[31:0];
|
|
_RAND_361 = {1{`RANDOM}};
|
|
fifo_addr_10 = _RAND_361[31:0];
|
|
_RAND_362 = {1{`RANDOM}};
|
|
fifo_addr_9 = _RAND_362[31:0];
|
|
_RAND_363 = {1{`RANDOM}};
|
|
fifo_addr_8 = _RAND_363[31:0];
|
|
_RAND_364 = {1{`RANDOM}};
|
|
fifo_addr_7 = _RAND_364[31:0];
|
|
_RAND_365 = {1{`RANDOM}};
|
|
fifo_addr_6 = _RAND_365[31:0];
|
|
_RAND_366 = {1{`RANDOM}};
|
|
fifo_addr_5 = _RAND_366[31:0];
|
|
_RAND_367 = {1{`RANDOM}};
|
|
fifo_addr_4 = _RAND_367[31:0];
|
|
_RAND_368 = {1{`RANDOM}};
|
|
fifo_addr_3 = _RAND_368[31:0];
|
|
_RAND_369 = {1{`RANDOM}};
|
|
fifo_addr_2 = _RAND_369[31:0];
|
|
_RAND_370 = {1{`RANDOM}};
|
|
fifo_addr_1 = _RAND_370[31:0];
|
|
_RAND_371 = {1{`RANDOM}};
|
|
fifo_addr_0 = _RAND_371[31:0];
|
|
_RAND_372 = {1{`RANDOM}};
|
|
fifo_sz_89 = _RAND_372[2:0];
|
|
_RAND_373 = {1{`RANDOM}};
|
|
fifo_sz_88 = _RAND_373[2:0];
|
|
_RAND_374 = {1{`RANDOM}};
|
|
fifo_sz_87 = _RAND_374[2:0];
|
|
_RAND_375 = {1{`RANDOM}};
|
|
fifo_sz_86 = _RAND_375[2:0];
|
|
_RAND_376 = {1{`RANDOM}};
|
|
fifo_sz_85 = _RAND_376[2:0];
|
|
_RAND_377 = {1{`RANDOM}};
|
|
fifo_sz_84 = _RAND_377[2:0];
|
|
_RAND_378 = {1{`RANDOM}};
|
|
fifo_sz_83 = _RAND_378[2:0];
|
|
_RAND_379 = {1{`RANDOM}};
|
|
fifo_sz_82 = _RAND_379[2:0];
|
|
_RAND_380 = {1{`RANDOM}};
|
|
fifo_sz_81 = _RAND_380[2:0];
|
|
_RAND_381 = {1{`RANDOM}};
|
|
fifo_sz_80 = _RAND_381[2:0];
|
|
_RAND_382 = {1{`RANDOM}};
|
|
fifo_sz_79 = _RAND_382[2:0];
|
|
_RAND_383 = {1{`RANDOM}};
|
|
fifo_sz_78 = _RAND_383[2:0];
|
|
_RAND_384 = {1{`RANDOM}};
|
|
fifo_sz_77 = _RAND_384[2:0];
|
|
_RAND_385 = {1{`RANDOM}};
|
|
fifo_sz_76 = _RAND_385[2:0];
|
|
_RAND_386 = {1{`RANDOM}};
|
|
fifo_sz_75 = _RAND_386[2:0];
|
|
_RAND_387 = {1{`RANDOM}};
|
|
fifo_sz_74 = _RAND_387[2:0];
|
|
_RAND_388 = {1{`RANDOM}};
|
|
fifo_sz_73 = _RAND_388[2:0];
|
|
_RAND_389 = {1{`RANDOM}};
|
|
fifo_sz_72 = _RAND_389[2:0];
|
|
_RAND_390 = {1{`RANDOM}};
|
|
fifo_sz_71 = _RAND_390[2:0];
|
|
_RAND_391 = {1{`RANDOM}};
|
|
fifo_sz_70 = _RAND_391[2:0];
|
|
_RAND_392 = {1{`RANDOM}};
|
|
fifo_sz_69 = _RAND_392[2:0];
|
|
_RAND_393 = {1{`RANDOM}};
|
|
fifo_sz_68 = _RAND_393[2:0];
|
|
_RAND_394 = {1{`RANDOM}};
|
|
fifo_sz_67 = _RAND_394[2:0];
|
|
_RAND_395 = {1{`RANDOM}};
|
|
fifo_sz_66 = _RAND_395[2:0];
|
|
_RAND_396 = {1{`RANDOM}};
|
|
fifo_sz_65 = _RAND_396[2:0];
|
|
_RAND_397 = {1{`RANDOM}};
|
|
fifo_sz_64 = _RAND_397[2:0];
|
|
_RAND_398 = {1{`RANDOM}};
|
|
fifo_sz_63 = _RAND_398[2:0];
|
|
_RAND_399 = {1{`RANDOM}};
|
|
fifo_sz_62 = _RAND_399[2:0];
|
|
_RAND_400 = {1{`RANDOM}};
|
|
fifo_sz_61 = _RAND_400[2:0];
|
|
_RAND_401 = {1{`RANDOM}};
|
|
fifo_sz_60 = _RAND_401[2:0];
|
|
_RAND_402 = {1{`RANDOM}};
|
|
fifo_sz_59 = _RAND_402[2:0];
|
|
_RAND_403 = {1{`RANDOM}};
|
|
fifo_sz_58 = _RAND_403[2:0];
|
|
_RAND_404 = {1{`RANDOM}};
|
|
fifo_sz_57 = _RAND_404[2:0];
|
|
_RAND_405 = {1{`RANDOM}};
|
|
fifo_sz_56 = _RAND_405[2:0];
|
|
_RAND_406 = {1{`RANDOM}};
|
|
fifo_sz_55 = _RAND_406[2:0];
|
|
_RAND_407 = {1{`RANDOM}};
|
|
fifo_sz_54 = _RAND_407[2:0];
|
|
_RAND_408 = {1{`RANDOM}};
|
|
fifo_sz_53 = _RAND_408[2:0];
|
|
_RAND_409 = {1{`RANDOM}};
|
|
fifo_sz_52 = _RAND_409[2:0];
|
|
_RAND_410 = {1{`RANDOM}};
|
|
fifo_sz_51 = _RAND_410[2:0];
|
|
_RAND_411 = {1{`RANDOM}};
|
|
fifo_sz_50 = _RAND_411[2:0];
|
|
_RAND_412 = {1{`RANDOM}};
|
|
fifo_sz_49 = _RAND_412[2:0];
|
|
_RAND_413 = {1{`RANDOM}};
|
|
fifo_sz_48 = _RAND_413[2:0];
|
|
_RAND_414 = {1{`RANDOM}};
|
|
fifo_sz_47 = _RAND_414[2:0];
|
|
_RAND_415 = {1{`RANDOM}};
|
|
fifo_sz_46 = _RAND_415[2:0];
|
|
_RAND_416 = {1{`RANDOM}};
|
|
fifo_sz_45 = _RAND_416[2:0];
|
|
_RAND_417 = {1{`RANDOM}};
|
|
fifo_sz_44 = _RAND_417[2:0];
|
|
_RAND_418 = {1{`RANDOM}};
|
|
fifo_sz_43 = _RAND_418[2:0];
|
|
_RAND_419 = {1{`RANDOM}};
|
|
fifo_sz_42 = _RAND_419[2:0];
|
|
_RAND_420 = {1{`RANDOM}};
|
|
fifo_sz_41 = _RAND_420[2:0];
|
|
_RAND_421 = {1{`RANDOM}};
|
|
fifo_sz_40 = _RAND_421[2:0];
|
|
_RAND_422 = {1{`RANDOM}};
|
|
fifo_sz_39 = _RAND_422[2:0];
|
|
_RAND_423 = {1{`RANDOM}};
|
|
fifo_sz_38 = _RAND_423[2:0];
|
|
_RAND_424 = {1{`RANDOM}};
|
|
fifo_sz_37 = _RAND_424[2:0];
|
|
_RAND_425 = {1{`RANDOM}};
|
|
fifo_sz_36 = _RAND_425[2:0];
|
|
_RAND_426 = {1{`RANDOM}};
|
|
fifo_sz_35 = _RAND_426[2:0];
|
|
_RAND_427 = {1{`RANDOM}};
|
|
fifo_sz_34 = _RAND_427[2:0];
|
|
_RAND_428 = {1{`RANDOM}};
|
|
fifo_sz_33 = _RAND_428[2:0];
|
|
_RAND_429 = {1{`RANDOM}};
|
|
fifo_sz_32 = _RAND_429[2:0];
|
|
_RAND_430 = {1{`RANDOM}};
|
|
fifo_sz_31 = _RAND_430[2:0];
|
|
_RAND_431 = {1{`RANDOM}};
|
|
fifo_sz_30 = _RAND_431[2:0];
|
|
_RAND_432 = {1{`RANDOM}};
|
|
fifo_sz_29 = _RAND_432[2:0];
|
|
_RAND_433 = {1{`RANDOM}};
|
|
fifo_sz_28 = _RAND_433[2:0];
|
|
_RAND_434 = {1{`RANDOM}};
|
|
fifo_sz_27 = _RAND_434[2:0];
|
|
_RAND_435 = {1{`RANDOM}};
|
|
fifo_sz_26 = _RAND_435[2:0];
|
|
_RAND_436 = {1{`RANDOM}};
|
|
fifo_sz_25 = _RAND_436[2:0];
|
|
_RAND_437 = {1{`RANDOM}};
|
|
fifo_sz_24 = _RAND_437[2:0];
|
|
_RAND_438 = {1{`RANDOM}};
|
|
fifo_sz_23 = _RAND_438[2:0];
|
|
_RAND_439 = {1{`RANDOM}};
|
|
fifo_sz_22 = _RAND_439[2:0];
|
|
_RAND_440 = {1{`RANDOM}};
|
|
fifo_sz_21 = _RAND_440[2:0];
|
|
_RAND_441 = {1{`RANDOM}};
|
|
fifo_sz_20 = _RAND_441[2:0];
|
|
_RAND_442 = {1{`RANDOM}};
|
|
fifo_sz_19 = _RAND_442[2:0];
|
|
_RAND_443 = {1{`RANDOM}};
|
|
fifo_sz_18 = _RAND_443[2:0];
|
|
_RAND_444 = {1{`RANDOM}};
|
|
fifo_sz_17 = _RAND_444[2:0];
|
|
_RAND_445 = {1{`RANDOM}};
|
|
fifo_sz_16 = _RAND_445[2:0];
|
|
_RAND_446 = {1{`RANDOM}};
|
|
fifo_sz_15 = _RAND_446[2:0];
|
|
_RAND_447 = {1{`RANDOM}};
|
|
fifo_sz_14 = _RAND_447[2:0];
|
|
_RAND_448 = {1{`RANDOM}};
|
|
fifo_sz_13 = _RAND_448[2:0];
|
|
_RAND_449 = {1{`RANDOM}};
|
|
fifo_sz_12 = _RAND_449[2:0];
|
|
_RAND_450 = {1{`RANDOM}};
|
|
fifo_sz_11 = _RAND_450[2:0];
|
|
_RAND_451 = {1{`RANDOM}};
|
|
fifo_sz_10 = _RAND_451[2:0];
|
|
_RAND_452 = {1{`RANDOM}};
|
|
fifo_sz_9 = _RAND_452[2:0];
|
|
_RAND_453 = {1{`RANDOM}};
|
|
fifo_sz_8 = _RAND_453[2:0];
|
|
_RAND_454 = {1{`RANDOM}};
|
|
fifo_sz_7 = _RAND_454[2:0];
|
|
_RAND_455 = {1{`RANDOM}};
|
|
fifo_sz_6 = _RAND_455[2:0];
|
|
_RAND_456 = {1{`RANDOM}};
|
|
fifo_sz_5 = _RAND_456[2:0];
|
|
_RAND_457 = {1{`RANDOM}};
|
|
fifo_sz_4 = _RAND_457[2:0];
|
|
_RAND_458 = {1{`RANDOM}};
|
|
fifo_sz_3 = _RAND_458[2:0];
|
|
_RAND_459 = {1{`RANDOM}};
|
|
fifo_sz_2 = _RAND_459[2:0];
|
|
_RAND_460 = {1{`RANDOM}};
|
|
fifo_sz_1 = _RAND_460[2:0];
|
|
_RAND_461 = {1{`RANDOM}};
|
|
fifo_sz_0 = _RAND_461[2:0];
|
|
_RAND_462 = {1{`RANDOM}};
|
|
fifo_byteen_89 = _RAND_462[7:0];
|
|
_RAND_463 = {1{`RANDOM}};
|
|
fifo_byteen_88 = _RAND_463[7:0];
|
|
_RAND_464 = {1{`RANDOM}};
|
|
fifo_byteen_87 = _RAND_464[7:0];
|
|
_RAND_465 = {1{`RANDOM}};
|
|
fifo_byteen_86 = _RAND_465[7:0];
|
|
_RAND_466 = {1{`RANDOM}};
|
|
fifo_byteen_85 = _RAND_466[7:0];
|
|
_RAND_467 = {1{`RANDOM}};
|
|
fifo_byteen_84 = _RAND_467[7:0];
|
|
_RAND_468 = {1{`RANDOM}};
|
|
fifo_byteen_83 = _RAND_468[7:0];
|
|
_RAND_469 = {1{`RANDOM}};
|
|
fifo_byteen_82 = _RAND_469[7:0];
|
|
_RAND_470 = {1{`RANDOM}};
|
|
fifo_byteen_81 = _RAND_470[7:0];
|
|
_RAND_471 = {1{`RANDOM}};
|
|
fifo_byteen_80 = _RAND_471[7:0];
|
|
_RAND_472 = {1{`RANDOM}};
|
|
fifo_byteen_79 = _RAND_472[7:0];
|
|
_RAND_473 = {1{`RANDOM}};
|
|
fifo_byteen_78 = _RAND_473[7:0];
|
|
_RAND_474 = {1{`RANDOM}};
|
|
fifo_byteen_77 = _RAND_474[7:0];
|
|
_RAND_475 = {1{`RANDOM}};
|
|
fifo_byteen_76 = _RAND_475[7:0];
|
|
_RAND_476 = {1{`RANDOM}};
|
|
fifo_byteen_75 = _RAND_476[7:0];
|
|
_RAND_477 = {1{`RANDOM}};
|
|
fifo_byteen_74 = _RAND_477[7:0];
|
|
_RAND_478 = {1{`RANDOM}};
|
|
fifo_byteen_73 = _RAND_478[7:0];
|
|
_RAND_479 = {1{`RANDOM}};
|
|
fifo_byteen_72 = _RAND_479[7:0];
|
|
_RAND_480 = {1{`RANDOM}};
|
|
fifo_byteen_71 = _RAND_480[7:0];
|
|
_RAND_481 = {1{`RANDOM}};
|
|
fifo_byteen_70 = _RAND_481[7:0];
|
|
_RAND_482 = {1{`RANDOM}};
|
|
fifo_byteen_69 = _RAND_482[7:0];
|
|
_RAND_483 = {1{`RANDOM}};
|
|
fifo_byteen_68 = _RAND_483[7:0];
|
|
_RAND_484 = {1{`RANDOM}};
|
|
fifo_byteen_67 = _RAND_484[7:0];
|
|
_RAND_485 = {1{`RANDOM}};
|
|
fifo_byteen_66 = _RAND_485[7:0];
|
|
_RAND_486 = {1{`RANDOM}};
|
|
fifo_byteen_65 = _RAND_486[7:0];
|
|
_RAND_487 = {1{`RANDOM}};
|
|
fifo_byteen_64 = _RAND_487[7:0];
|
|
_RAND_488 = {1{`RANDOM}};
|
|
fifo_byteen_63 = _RAND_488[7:0];
|
|
_RAND_489 = {1{`RANDOM}};
|
|
fifo_byteen_62 = _RAND_489[7:0];
|
|
_RAND_490 = {1{`RANDOM}};
|
|
fifo_byteen_61 = _RAND_490[7:0];
|
|
_RAND_491 = {1{`RANDOM}};
|
|
fifo_byteen_60 = _RAND_491[7:0];
|
|
_RAND_492 = {1{`RANDOM}};
|
|
fifo_byteen_59 = _RAND_492[7:0];
|
|
_RAND_493 = {1{`RANDOM}};
|
|
fifo_byteen_58 = _RAND_493[7:0];
|
|
_RAND_494 = {1{`RANDOM}};
|
|
fifo_byteen_57 = _RAND_494[7:0];
|
|
_RAND_495 = {1{`RANDOM}};
|
|
fifo_byteen_56 = _RAND_495[7:0];
|
|
_RAND_496 = {1{`RANDOM}};
|
|
fifo_byteen_55 = _RAND_496[7:0];
|
|
_RAND_497 = {1{`RANDOM}};
|
|
fifo_byteen_54 = _RAND_497[7:0];
|
|
_RAND_498 = {1{`RANDOM}};
|
|
fifo_byteen_53 = _RAND_498[7:0];
|
|
_RAND_499 = {1{`RANDOM}};
|
|
fifo_byteen_52 = _RAND_499[7:0];
|
|
_RAND_500 = {1{`RANDOM}};
|
|
fifo_byteen_51 = _RAND_500[7:0];
|
|
_RAND_501 = {1{`RANDOM}};
|
|
fifo_byteen_50 = _RAND_501[7:0];
|
|
_RAND_502 = {1{`RANDOM}};
|
|
fifo_byteen_49 = _RAND_502[7:0];
|
|
_RAND_503 = {1{`RANDOM}};
|
|
fifo_byteen_48 = _RAND_503[7:0];
|
|
_RAND_504 = {1{`RANDOM}};
|
|
fifo_byteen_47 = _RAND_504[7:0];
|
|
_RAND_505 = {1{`RANDOM}};
|
|
fifo_byteen_46 = _RAND_505[7:0];
|
|
_RAND_506 = {1{`RANDOM}};
|
|
fifo_byteen_45 = _RAND_506[7:0];
|
|
_RAND_507 = {1{`RANDOM}};
|
|
fifo_byteen_44 = _RAND_507[7:0];
|
|
_RAND_508 = {1{`RANDOM}};
|
|
fifo_byteen_43 = _RAND_508[7:0];
|
|
_RAND_509 = {1{`RANDOM}};
|
|
fifo_byteen_42 = _RAND_509[7:0];
|
|
_RAND_510 = {1{`RANDOM}};
|
|
fifo_byteen_41 = _RAND_510[7:0];
|
|
_RAND_511 = {1{`RANDOM}};
|
|
fifo_byteen_40 = _RAND_511[7:0];
|
|
_RAND_512 = {1{`RANDOM}};
|
|
fifo_byteen_39 = _RAND_512[7:0];
|
|
_RAND_513 = {1{`RANDOM}};
|
|
fifo_byteen_38 = _RAND_513[7:0];
|
|
_RAND_514 = {1{`RANDOM}};
|
|
fifo_byteen_37 = _RAND_514[7:0];
|
|
_RAND_515 = {1{`RANDOM}};
|
|
fifo_byteen_36 = _RAND_515[7:0];
|
|
_RAND_516 = {1{`RANDOM}};
|
|
fifo_byteen_35 = _RAND_516[7:0];
|
|
_RAND_517 = {1{`RANDOM}};
|
|
fifo_byteen_34 = _RAND_517[7:0];
|
|
_RAND_518 = {1{`RANDOM}};
|
|
fifo_byteen_33 = _RAND_518[7:0];
|
|
_RAND_519 = {1{`RANDOM}};
|
|
fifo_byteen_32 = _RAND_519[7:0];
|
|
_RAND_520 = {1{`RANDOM}};
|
|
fifo_byteen_31 = _RAND_520[7:0];
|
|
_RAND_521 = {1{`RANDOM}};
|
|
fifo_byteen_30 = _RAND_521[7:0];
|
|
_RAND_522 = {1{`RANDOM}};
|
|
fifo_byteen_29 = _RAND_522[7:0];
|
|
_RAND_523 = {1{`RANDOM}};
|
|
fifo_byteen_28 = _RAND_523[7:0];
|
|
_RAND_524 = {1{`RANDOM}};
|
|
fifo_byteen_27 = _RAND_524[7:0];
|
|
_RAND_525 = {1{`RANDOM}};
|
|
fifo_byteen_26 = _RAND_525[7:0];
|
|
_RAND_526 = {1{`RANDOM}};
|
|
fifo_byteen_25 = _RAND_526[7:0];
|
|
_RAND_527 = {1{`RANDOM}};
|
|
fifo_byteen_24 = _RAND_527[7:0];
|
|
_RAND_528 = {1{`RANDOM}};
|
|
fifo_byteen_23 = _RAND_528[7:0];
|
|
_RAND_529 = {1{`RANDOM}};
|
|
fifo_byteen_22 = _RAND_529[7:0];
|
|
_RAND_530 = {1{`RANDOM}};
|
|
fifo_byteen_21 = _RAND_530[7:0];
|
|
_RAND_531 = {1{`RANDOM}};
|
|
fifo_byteen_20 = _RAND_531[7:0];
|
|
_RAND_532 = {1{`RANDOM}};
|
|
fifo_byteen_19 = _RAND_532[7:0];
|
|
_RAND_533 = {1{`RANDOM}};
|
|
fifo_byteen_18 = _RAND_533[7:0];
|
|
_RAND_534 = {1{`RANDOM}};
|
|
fifo_byteen_17 = _RAND_534[7:0];
|
|
_RAND_535 = {1{`RANDOM}};
|
|
fifo_byteen_16 = _RAND_535[7:0];
|
|
_RAND_536 = {1{`RANDOM}};
|
|
fifo_byteen_15 = _RAND_536[7:0];
|
|
_RAND_537 = {1{`RANDOM}};
|
|
fifo_byteen_14 = _RAND_537[7:0];
|
|
_RAND_538 = {1{`RANDOM}};
|
|
fifo_byteen_13 = _RAND_538[7:0];
|
|
_RAND_539 = {1{`RANDOM}};
|
|
fifo_byteen_12 = _RAND_539[7:0];
|
|
_RAND_540 = {1{`RANDOM}};
|
|
fifo_byteen_11 = _RAND_540[7:0];
|
|
_RAND_541 = {1{`RANDOM}};
|
|
fifo_byteen_10 = _RAND_541[7:0];
|
|
_RAND_542 = {1{`RANDOM}};
|
|
fifo_byteen_9 = _RAND_542[7:0];
|
|
_RAND_543 = {1{`RANDOM}};
|
|
fifo_byteen_8 = _RAND_543[7:0];
|
|
_RAND_544 = {1{`RANDOM}};
|
|
fifo_byteen_7 = _RAND_544[7:0];
|
|
_RAND_545 = {1{`RANDOM}};
|
|
fifo_byteen_6 = _RAND_545[7:0];
|
|
_RAND_546 = {1{`RANDOM}};
|
|
fifo_byteen_5 = _RAND_546[7:0];
|
|
_RAND_547 = {1{`RANDOM}};
|
|
fifo_byteen_4 = _RAND_547[7:0];
|
|
_RAND_548 = {1{`RANDOM}};
|
|
fifo_byteen_3 = _RAND_548[7:0];
|
|
_RAND_549 = {1{`RANDOM}};
|
|
fifo_byteen_2 = _RAND_549[7:0];
|
|
_RAND_550 = {1{`RANDOM}};
|
|
fifo_byteen_1 = _RAND_550[7:0];
|
|
_RAND_551 = {1{`RANDOM}};
|
|
fifo_byteen_0 = _RAND_551[7:0];
|
|
_RAND_552 = {1{`RANDOM}};
|
|
fifo_error_0 = _RAND_552[1:0];
|
|
_RAND_553 = {1{`RANDOM}};
|
|
fifo_error_1 = _RAND_553[1:0];
|
|
_RAND_554 = {1{`RANDOM}};
|
|
fifo_error_2 = _RAND_554[1:0];
|
|
_RAND_555 = {1{`RANDOM}};
|
|
fifo_error_3 = _RAND_555[1:0];
|
|
_RAND_556 = {1{`RANDOM}};
|
|
fifo_error_4 = _RAND_556[1:0];
|
|
_RAND_557 = {1{`RANDOM}};
|
|
fifo_error_5 = _RAND_557[1:0];
|
|
_RAND_558 = {1{`RANDOM}};
|
|
fifo_error_6 = _RAND_558[1:0];
|
|
_RAND_559 = {1{`RANDOM}};
|
|
fifo_error_7 = _RAND_559[1:0];
|
|
_RAND_560 = {1{`RANDOM}};
|
|
fifo_error_8 = _RAND_560[1:0];
|
|
_RAND_561 = {1{`RANDOM}};
|
|
fifo_error_9 = _RAND_561[1:0];
|
|
_RAND_562 = {1{`RANDOM}};
|
|
fifo_error_10 = _RAND_562[1:0];
|
|
_RAND_563 = {1{`RANDOM}};
|
|
fifo_error_11 = _RAND_563[1:0];
|
|
_RAND_564 = {1{`RANDOM}};
|
|
fifo_error_12 = _RAND_564[1:0];
|
|
_RAND_565 = {1{`RANDOM}};
|
|
fifo_error_13 = _RAND_565[1:0];
|
|
_RAND_566 = {1{`RANDOM}};
|
|
fifo_error_14 = _RAND_566[1:0];
|
|
_RAND_567 = {1{`RANDOM}};
|
|
fifo_error_15 = _RAND_567[1:0];
|
|
_RAND_568 = {1{`RANDOM}};
|
|
fifo_error_16 = _RAND_568[1:0];
|
|
_RAND_569 = {1{`RANDOM}};
|
|
fifo_error_17 = _RAND_569[1:0];
|
|
_RAND_570 = {1{`RANDOM}};
|
|
fifo_error_18 = _RAND_570[1:0];
|
|
_RAND_571 = {1{`RANDOM}};
|
|
fifo_error_19 = _RAND_571[1:0];
|
|
_RAND_572 = {1{`RANDOM}};
|
|
fifo_error_20 = _RAND_572[1:0];
|
|
_RAND_573 = {1{`RANDOM}};
|
|
fifo_error_21 = _RAND_573[1:0];
|
|
_RAND_574 = {1{`RANDOM}};
|
|
fifo_error_22 = _RAND_574[1:0];
|
|
_RAND_575 = {1{`RANDOM}};
|
|
fifo_error_23 = _RAND_575[1:0];
|
|
_RAND_576 = {1{`RANDOM}};
|
|
fifo_error_24 = _RAND_576[1:0];
|
|
_RAND_577 = {1{`RANDOM}};
|
|
fifo_error_25 = _RAND_577[1:0];
|
|
_RAND_578 = {1{`RANDOM}};
|
|
fifo_error_26 = _RAND_578[1:0];
|
|
_RAND_579 = {1{`RANDOM}};
|
|
fifo_error_27 = _RAND_579[1:0];
|
|
_RAND_580 = {1{`RANDOM}};
|
|
fifo_error_28 = _RAND_580[1:0];
|
|
_RAND_581 = {1{`RANDOM}};
|
|
fifo_error_29 = _RAND_581[1:0];
|
|
_RAND_582 = {1{`RANDOM}};
|
|
fifo_error_30 = _RAND_582[1:0];
|
|
_RAND_583 = {1{`RANDOM}};
|
|
fifo_error_31 = _RAND_583[1:0];
|
|
_RAND_584 = {1{`RANDOM}};
|
|
fifo_error_32 = _RAND_584[1:0];
|
|
_RAND_585 = {1{`RANDOM}};
|
|
fifo_error_33 = _RAND_585[1:0];
|
|
_RAND_586 = {1{`RANDOM}};
|
|
fifo_error_34 = _RAND_586[1:0];
|
|
_RAND_587 = {1{`RANDOM}};
|
|
fifo_error_35 = _RAND_587[1:0];
|
|
_RAND_588 = {1{`RANDOM}};
|
|
fifo_error_36 = _RAND_588[1:0];
|
|
_RAND_589 = {1{`RANDOM}};
|
|
fifo_error_37 = _RAND_589[1:0];
|
|
_RAND_590 = {1{`RANDOM}};
|
|
fifo_error_38 = _RAND_590[1:0];
|
|
_RAND_591 = {1{`RANDOM}};
|
|
fifo_error_39 = _RAND_591[1:0];
|
|
_RAND_592 = {1{`RANDOM}};
|
|
fifo_error_40 = _RAND_592[1:0];
|
|
_RAND_593 = {1{`RANDOM}};
|
|
fifo_error_41 = _RAND_593[1:0];
|
|
_RAND_594 = {1{`RANDOM}};
|
|
fifo_error_42 = _RAND_594[1:0];
|
|
_RAND_595 = {1{`RANDOM}};
|
|
fifo_error_43 = _RAND_595[1:0];
|
|
_RAND_596 = {1{`RANDOM}};
|
|
fifo_error_44 = _RAND_596[1:0];
|
|
_RAND_597 = {1{`RANDOM}};
|
|
fifo_error_45 = _RAND_597[1:0];
|
|
_RAND_598 = {1{`RANDOM}};
|
|
fifo_error_46 = _RAND_598[1:0];
|
|
_RAND_599 = {1{`RANDOM}};
|
|
fifo_error_47 = _RAND_599[1:0];
|
|
_RAND_600 = {1{`RANDOM}};
|
|
fifo_error_48 = _RAND_600[1:0];
|
|
_RAND_601 = {1{`RANDOM}};
|
|
fifo_error_49 = _RAND_601[1:0];
|
|
_RAND_602 = {1{`RANDOM}};
|
|
fifo_error_50 = _RAND_602[1:0];
|
|
_RAND_603 = {1{`RANDOM}};
|
|
fifo_error_51 = _RAND_603[1:0];
|
|
_RAND_604 = {1{`RANDOM}};
|
|
fifo_error_52 = _RAND_604[1:0];
|
|
_RAND_605 = {1{`RANDOM}};
|
|
fifo_error_53 = _RAND_605[1:0];
|
|
_RAND_606 = {1{`RANDOM}};
|
|
fifo_error_54 = _RAND_606[1:0];
|
|
_RAND_607 = {1{`RANDOM}};
|
|
fifo_error_55 = _RAND_607[1:0];
|
|
_RAND_608 = {1{`RANDOM}};
|
|
fifo_error_56 = _RAND_608[1:0];
|
|
_RAND_609 = {1{`RANDOM}};
|
|
fifo_error_57 = _RAND_609[1:0];
|
|
_RAND_610 = {1{`RANDOM}};
|
|
fifo_error_58 = _RAND_610[1:0];
|
|
_RAND_611 = {1{`RANDOM}};
|
|
fifo_error_59 = _RAND_611[1:0];
|
|
_RAND_612 = {1{`RANDOM}};
|
|
fifo_error_60 = _RAND_612[1:0];
|
|
_RAND_613 = {1{`RANDOM}};
|
|
fifo_error_61 = _RAND_613[1:0];
|
|
_RAND_614 = {1{`RANDOM}};
|
|
fifo_error_62 = _RAND_614[1:0];
|
|
_RAND_615 = {1{`RANDOM}};
|
|
fifo_error_63 = _RAND_615[1:0];
|
|
_RAND_616 = {1{`RANDOM}};
|
|
fifo_error_64 = _RAND_616[1:0];
|
|
_RAND_617 = {1{`RANDOM}};
|
|
fifo_error_65 = _RAND_617[1:0];
|
|
_RAND_618 = {1{`RANDOM}};
|
|
fifo_error_66 = _RAND_618[1:0];
|
|
_RAND_619 = {1{`RANDOM}};
|
|
fifo_error_67 = _RAND_619[1:0];
|
|
_RAND_620 = {1{`RANDOM}};
|
|
fifo_error_68 = _RAND_620[1:0];
|
|
_RAND_621 = {1{`RANDOM}};
|
|
fifo_error_69 = _RAND_621[1:0];
|
|
_RAND_622 = {1{`RANDOM}};
|
|
fifo_error_70 = _RAND_622[1:0];
|
|
_RAND_623 = {1{`RANDOM}};
|
|
fifo_error_71 = _RAND_623[1:0];
|
|
_RAND_624 = {1{`RANDOM}};
|
|
fifo_error_72 = _RAND_624[1:0];
|
|
_RAND_625 = {1{`RANDOM}};
|
|
fifo_error_73 = _RAND_625[1:0];
|
|
_RAND_626 = {1{`RANDOM}};
|
|
fifo_error_74 = _RAND_626[1:0];
|
|
_RAND_627 = {1{`RANDOM}};
|
|
fifo_error_75 = _RAND_627[1:0];
|
|
_RAND_628 = {1{`RANDOM}};
|
|
fifo_error_76 = _RAND_628[1:0];
|
|
_RAND_629 = {1{`RANDOM}};
|
|
fifo_error_77 = _RAND_629[1:0];
|
|
_RAND_630 = {1{`RANDOM}};
|
|
fifo_error_78 = _RAND_630[1:0];
|
|
_RAND_631 = {1{`RANDOM}};
|
|
fifo_error_79 = _RAND_631[1:0];
|
|
_RAND_632 = {1{`RANDOM}};
|
|
fifo_error_80 = _RAND_632[1:0];
|
|
_RAND_633 = {1{`RANDOM}};
|
|
fifo_error_81 = _RAND_633[1:0];
|
|
_RAND_634 = {1{`RANDOM}};
|
|
fifo_error_82 = _RAND_634[1:0];
|
|
_RAND_635 = {1{`RANDOM}};
|
|
fifo_error_83 = _RAND_635[1:0];
|
|
_RAND_636 = {1{`RANDOM}};
|
|
fifo_error_84 = _RAND_636[1:0];
|
|
_RAND_637 = {1{`RANDOM}};
|
|
fifo_error_85 = _RAND_637[1:0];
|
|
_RAND_638 = {1{`RANDOM}};
|
|
fifo_error_86 = _RAND_638[1:0];
|
|
_RAND_639 = {1{`RANDOM}};
|
|
fifo_error_87 = _RAND_639[1:0];
|
|
_RAND_640 = {1{`RANDOM}};
|
|
fifo_error_88 = _RAND_640[1:0];
|
|
_RAND_641 = {1{`RANDOM}};
|
|
fifo_error_89 = _RAND_641[1:0];
|
|
_RAND_642 = {1{`RANDOM}};
|
|
RspPtr = _RAND_642[6:0];
|
|
_RAND_643 = {2{`RANDOM}};
|
|
wrbuf_data = _RAND_643[63:0];
|
|
_RAND_644 = {1{`RANDOM}};
|
|
_T_12692 = _RAND_644[0:0];
|
|
_RAND_645 = {1{`RANDOM}};
|
|
_T_12685 = _RAND_645[0:0];
|
|
_RAND_646 = {1{`RANDOM}};
|
|
_T_12678 = _RAND_646[0:0];
|
|
_RAND_647 = {1{`RANDOM}};
|
|
_T_12671 = _RAND_647[0:0];
|
|
_RAND_648 = {1{`RANDOM}};
|
|
_T_12664 = _RAND_648[0:0];
|
|
_RAND_649 = {1{`RANDOM}};
|
|
_T_12657 = _RAND_649[0:0];
|
|
_RAND_650 = {1{`RANDOM}};
|
|
_T_12650 = _RAND_650[0:0];
|
|
_RAND_651 = {1{`RANDOM}};
|
|
_T_12643 = _RAND_651[0:0];
|
|
_RAND_652 = {1{`RANDOM}};
|
|
_T_12636 = _RAND_652[0:0];
|
|
_RAND_653 = {1{`RANDOM}};
|
|
_T_12629 = _RAND_653[0:0];
|
|
_RAND_654 = {1{`RANDOM}};
|
|
_T_12622 = _RAND_654[0:0];
|
|
_RAND_655 = {1{`RANDOM}};
|
|
_T_12615 = _RAND_655[0:0];
|
|
_RAND_656 = {1{`RANDOM}};
|
|
_T_12608 = _RAND_656[0:0];
|
|
_RAND_657 = {1{`RANDOM}};
|
|
_T_12601 = _RAND_657[0:0];
|
|
_RAND_658 = {1{`RANDOM}};
|
|
_T_12594 = _RAND_658[0:0];
|
|
_RAND_659 = {1{`RANDOM}};
|
|
_T_12587 = _RAND_659[0:0];
|
|
_RAND_660 = {1{`RANDOM}};
|
|
_T_12580 = _RAND_660[0:0];
|
|
_RAND_661 = {1{`RANDOM}};
|
|
_T_12573 = _RAND_661[0:0];
|
|
_RAND_662 = {1{`RANDOM}};
|
|
_T_12566 = _RAND_662[0:0];
|
|
_RAND_663 = {1{`RANDOM}};
|
|
_T_12559 = _RAND_663[0:0];
|
|
_RAND_664 = {1{`RANDOM}};
|
|
_T_12552 = _RAND_664[0:0];
|
|
_RAND_665 = {1{`RANDOM}};
|
|
_T_12545 = _RAND_665[0:0];
|
|
_RAND_666 = {1{`RANDOM}};
|
|
_T_12538 = _RAND_666[0:0];
|
|
_RAND_667 = {1{`RANDOM}};
|
|
_T_12531 = _RAND_667[0:0];
|
|
_RAND_668 = {1{`RANDOM}};
|
|
_T_12524 = _RAND_668[0:0];
|
|
_RAND_669 = {1{`RANDOM}};
|
|
_T_12517 = _RAND_669[0:0];
|
|
_RAND_670 = {1{`RANDOM}};
|
|
_T_12510 = _RAND_670[0:0];
|
|
_RAND_671 = {1{`RANDOM}};
|
|
_T_12503 = _RAND_671[0:0];
|
|
_RAND_672 = {1{`RANDOM}};
|
|
_T_12496 = _RAND_672[0:0];
|
|
_RAND_673 = {1{`RANDOM}};
|
|
_T_12489 = _RAND_673[0:0];
|
|
_RAND_674 = {1{`RANDOM}};
|
|
_T_12482 = _RAND_674[0:0];
|
|
_RAND_675 = {1{`RANDOM}};
|
|
_T_12475 = _RAND_675[0:0];
|
|
_RAND_676 = {1{`RANDOM}};
|
|
_T_12468 = _RAND_676[0:0];
|
|
_RAND_677 = {1{`RANDOM}};
|
|
_T_12461 = _RAND_677[0:0];
|
|
_RAND_678 = {1{`RANDOM}};
|
|
_T_12454 = _RAND_678[0:0];
|
|
_RAND_679 = {1{`RANDOM}};
|
|
_T_12447 = _RAND_679[0:0];
|
|
_RAND_680 = {1{`RANDOM}};
|
|
_T_12440 = _RAND_680[0:0];
|
|
_RAND_681 = {1{`RANDOM}};
|
|
_T_12433 = _RAND_681[0:0];
|
|
_RAND_682 = {1{`RANDOM}};
|
|
_T_12426 = _RAND_682[0:0];
|
|
_RAND_683 = {1{`RANDOM}};
|
|
_T_12419 = _RAND_683[0:0];
|
|
_RAND_684 = {1{`RANDOM}};
|
|
_T_12412 = _RAND_684[0:0];
|
|
_RAND_685 = {1{`RANDOM}};
|
|
_T_12405 = _RAND_685[0:0];
|
|
_RAND_686 = {1{`RANDOM}};
|
|
_T_12398 = _RAND_686[0:0];
|
|
_RAND_687 = {1{`RANDOM}};
|
|
_T_12391 = _RAND_687[0:0];
|
|
_RAND_688 = {1{`RANDOM}};
|
|
_T_12384 = _RAND_688[0:0];
|
|
_RAND_689 = {1{`RANDOM}};
|
|
_T_12377 = _RAND_689[0:0];
|
|
_RAND_690 = {1{`RANDOM}};
|
|
_T_12370 = _RAND_690[0:0];
|
|
_RAND_691 = {1{`RANDOM}};
|
|
_T_12363 = _RAND_691[0:0];
|
|
_RAND_692 = {1{`RANDOM}};
|
|
_T_12356 = _RAND_692[0:0];
|
|
_RAND_693 = {1{`RANDOM}};
|
|
_T_12349 = _RAND_693[0:0];
|
|
_RAND_694 = {1{`RANDOM}};
|
|
_T_12342 = _RAND_694[0:0];
|
|
_RAND_695 = {1{`RANDOM}};
|
|
_T_12335 = _RAND_695[0:0];
|
|
_RAND_696 = {1{`RANDOM}};
|
|
_T_12328 = _RAND_696[0:0];
|
|
_RAND_697 = {1{`RANDOM}};
|
|
_T_12321 = _RAND_697[0:0];
|
|
_RAND_698 = {1{`RANDOM}};
|
|
_T_12314 = _RAND_698[0:0];
|
|
_RAND_699 = {1{`RANDOM}};
|
|
_T_12307 = _RAND_699[0:0];
|
|
_RAND_700 = {1{`RANDOM}};
|
|
_T_12300 = _RAND_700[0:0];
|
|
_RAND_701 = {1{`RANDOM}};
|
|
_T_12293 = _RAND_701[0:0];
|
|
_RAND_702 = {1{`RANDOM}};
|
|
_T_12286 = _RAND_702[0:0];
|
|
_RAND_703 = {1{`RANDOM}};
|
|
_T_12279 = _RAND_703[0:0];
|
|
_RAND_704 = {1{`RANDOM}};
|
|
_T_12272 = _RAND_704[0:0];
|
|
_RAND_705 = {1{`RANDOM}};
|
|
_T_12265 = _RAND_705[0:0];
|
|
_RAND_706 = {1{`RANDOM}};
|
|
_T_12258 = _RAND_706[0:0];
|
|
_RAND_707 = {1{`RANDOM}};
|
|
_T_12251 = _RAND_707[0:0];
|
|
_RAND_708 = {1{`RANDOM}};
|
|
_T_12244 = _RAND_708[0:0];
|
|
_RAND_709 = {1{`RANDOM}};
|
|
_T_12237 = _RAND_709[0:0];
|
|
_RAND_710 = {1{`RANDOM}};
|
|
_T_12230 = _RAND_710[0:0];
|
|
_RAND_711 = {1{`RANDOM}};
|
|
_T_12223 = _RAND_711[0:0];
|
|
_RAND_712 = {1{`RANDOM}};
|
|
_T_12216 = _RAND_712[0:0];
|
|
_RAND_713 = {1{`RANDOM}};
|
|
_T_12209 = _RAND_713[0:0];
|
|
_RAND_714 = {1{`RANDOM}};
|
|
_T_12202 = _RAND_714[0:0];
|
|
_RAND_715 = {1{`RANDOM}};
|
|
_T_12195 = _RAND_715[0:0];
|
|
_RAND_716 = {1{`RANDOM}};
|
|
_T_12188 = _RAND_716[0:0];
|
|
_RAND_717 = {1{`RANDOM}};
|
|
_T_12181 = _RAND_717[0:0];
|
|
_RAND_718 = {1{`RANDOM}};
|
|
_T_12174 = _RAND_718[0:0];
|
|
_RAND_719 = {1{`RANDOM}};
|
|
_T_12167 = _RAND_719[0:0];
|
|
_RAND_720 = {1{`RANDOM}};
|
|
_T_12160 = _RAND_720[0:0];
|
|
_RAND_721 = {1{`RANDOM}};
|
|
_T_12153 = _RAND_721[0:0];
|
|
_RAND_722 = {1{`RANDOM}};
|
|
_T_12146 = _RAND_722[0:0];
|
|
_RAND_723 = {1{`RANDOM}};
|
|
_T_12139 = _RAND_723[0:0];
|
|
_RAND_724 = {1{`RANDOM}};
|
|
_T_12132 = _RAND_724[0:0];
|
|
_RAND_725 = {1{`RANDOM}};
|
|
_T_12125 = _RAND_725[0:0];
|
|
_RAND_726 = {1{`RANDOM}};
|
|
_T_12118 = _RAND_726[0:0];
|
|
_RAND_727 = {1{`RANDOM}};
|
|
_T_12111 = _RAND_727[0:0];
|
|
_RAND_728 = {1{`RANDOM}};
|
|
_T_12104 = _RAND_728[0:0];
|
|
_RAND_729 = {1{`RANDOM}};
|
|
_T_12097 = _RAND_729[0:0];
|
|
_RAND_730 = {1{`RANDOM}};
|
|
_T_12090 = _RAND_730[0:0];
|
|
_RAND_731 = {1{`RANDOM}};
|
|
_T_12083 = _RAND_731[0:0];
|
|
_RAND_732 = {1{`RANDOM}};
|
|
_T_12076 = _RAND_732[0:0];
|
|
_RAND_733 = {1{`RANDOM}};
|
|
_T_12069 = _RAND_733[0:0];
|
|
_RAND_734 = {1{`RANDOM}};
|
|
_T_14130 = _RAND_734[0:0];
|
|
_RAND_735 = {1{`RANDOM}};
|
|
_T_14123 = _RAND_735[0:0];
|
|
_RAND_736 = {1{`RANDOM}};
|
|
_T_14116 = _RAND_736[0:0];
|
|
_RAND_737 = {1{`RANDOM}};
|
|
_T_14109 = _RAND_737[0:0];
|
|
_RAND_738 = {1{`RANDOM}};
|
|
_T_14102 = _RAND_738[0:0];
|
|
_RAND_739 = {1{`RANDOM}};
|
|
_T_14095 = _RAND_739[0:0];
|
|
_RAND_740 = {1{`RANDOM}};
|
|
_T_14088 = _RAND_740[0:0];
|
|
_RAND_741 = {1{`RANDOM}};
|
|
_T_14081 = _RAND_741[0:0];
|
|
_RAND_742 = {1{`RANDOM}};
|
|
_T_14074 = _RAND_742[0:0];
|
|
_RAND_743 = {1{`RANDOM}};
|
|
_T_14067 = _RAND_743[0:0];
|
|
_RAND_744 = {1{`RANDOM}};
|
|
_T_14060 = _RAND_744[0:0];
|
|
_RAND_745 = {1{`RANDOM}};
|
|
_T_14053 = _RAND_745[0:0];
|
|
_RAND_746 = {1{`RANDOM}};
|
|
_T_14046 = _RAND_746[0:0];
|
|
_RAND_747 = {1{`RANDOM}};
|
|
_T_14039 = _RAND_747[0:0];
|
|
_RAND_748 = {1{`RANDOM}};
|
|
_T_14032 = _RAND_748[0:0];
|
|
_RAND_749 = {1{`RANDOM}};
|
|
_T_14025 = _RAND_749[0:0];
|
|
_RAND_750 = {1{`RANDOM}};
|
|
_T_14018 = _RAND_750[0:0];
|
|
_RAND_751 = {1{`RANDOM}};
|
|
_T_14011 = _RAND_751[0:0];
|
|
_RAND_752 = {1{`RANDOM}};
|
|
_T_14004 = _RAND_752[0:0];
|
|
_RAND_753 = {1{`RANDOM}};
|
|
_T_13997 = _RAND_753[0:0];
|
|
_RAND_754 = {1{`RANDOM}};
|
|
_T_13990 = _RAND_754[0:0];
|
|
_RAND_755 = {1{`RANDOM}};
|
|
_T_13983 = _RAND_755[0:0];
|
|
_RAND_756 = {1{`RANDOM}};
|
|
_T_13976 = _RAND_756[0:0];
|
|
_RAND_757 = {1{`RANDOM}};
|
|
_T_13969 = _RAND_757[0:0];
|
|
_RAND_758 = {1{`RANDOM}};
|
|
_T_13962 = _RAND_758[0:0];
|
|
_RAND_759 = {1{`RANDOM}};
|
|
_T_13955 = _RAND_759[0:0];
|
|
_RAND_760 = {1{`RANDOM}};
|
|
_T_13948 = _RAND_760[0:0];
|
|
_RAND_761 = {1{`RANDOM}};
|
|
_T_13941 = _RAND_761[0:0];
|
|
_RAND_762 = {1{`RANDOM}};
|
|
_T_13934 = _RAND_762[0:0];
|
|
_RAND_763 = {1{`RANDOM}};
|
|
_T_13927 = _RAND_763[0:0];
|
|
_RAND_764 = {1{`RANDOM}};
|
|
_T_13920 = _RAND_764[0:0];
|
|
_RAND_765 = {1{`RANDOM}};
|
|
_T_13913 = _RAND_765[0:0];
|
|
_RAND_766 = {1{`RANDOM}};
|
|
_T_13906 = _RAND_766[0:0];
|
|
_RAND_767 = {1{`RANDOM}};
|
|
_T_13899 = _RAND_767[0:0];
|
|
_RAND_768 = {1{`RANDOM}};
|
|
_T_13892 = _RAND_768[0:0];
|
|
_RAND_769 = {1{`RANDOM}};
|
|
_T_13885 = _RAND_769[0:0];
|
|
_RAND_770 = {1{`RANDOM}};
|
|
_T_13878 = _RAND_770[0:0];
|
|
_RAND_771 = {1{`RANDOM}};
|
|
_T_13871 = _RAND_771[0:0];
|
|
_RAND_772 = {1{`RANDOM}};
|
|
_T_13864 = _RAND_772[0:0];
|
|
_RAND_773 = {1{`RANDOM}};
|
|
_T_13857 = _RAND_773[0:0];
|
|
_RAND_774 = {1{`RANDOM}};
|
|
_T_13850 = _RAND_774[0:0];
|
|
_RAND_775 = {1{`RANDOM}};
|
|
_T_13843 = _RAND_775[0:0];
|
|
_RAND_776 = {1{`RANDOM}};
|
|
_T_13836 = _RAND_776[0:0];
|
|
_RAND_777 = {1{`RANDOM}};
|
|
_T_13829 = _RAND_777[0:0];
|
|
_RAND_778 = {1{`RANDOM}};
|
|
_T_13822 = _RAND_778[0:0];
|
|
_RAND_779 = {1{`RANDOM}};
|
|
_T_13815 = _RAND_779[0:0];
|
|
_RAND_780 = {1{`RANDOM}};
|
|
_T_13808 = _RAND_780[0:0];
|
|
_RAND_781 = {1{`RANDOM}};
|
|
_T_13801 = _RAND_781[0:0];
|
|
_RAND_782 = {1{`RANDOM}};
|
|
_T_13794 = _RAND_782[0:0];
|
|
_RAND_783 = {1{`RANDOM}};
|
|
_T_13787 = _RAND_783[0:0];
|
|
_RAND_784 = {1{`RANDOM}};
|
|
_T_13780 = _RAND_784[0:0];
|
|
_RAND_785 = {1{`RANDOM}};
|
|
_T_13773 = _RAND_785[0:0];
|
|
_RAND_786 = {1{`RANDOM}};
|
|
_T_13766 = _RAND_786[0:0];
|
|
_RAND_787 = {1{`RANDOM}};
|
|
_T_13759 = _RAND_787[0:0];
|
|
_RAND_788 = {1{`RANDOM}};
|
|
_T_13752 = _RAND_788[0:0];
|
|
_RAND_789 = {1{`RANDOM}};
|
|
_T_13745 = _RAND_789[0:0];
|
|
_RAND_790 = {1{`RANDOM}};
|
|
_T_13738 = _RAND_790[0:0];
|
|
_RAND_791 = {1{`RANDOM}};
|
|
_T_13731 = _RAND_791[0:0];
|
|
_RAND_792 = {1{`RANDOM}};
|
|
_T_13724 = _RAND_792[0:0];
|
|
_RAND_793 = {1{`RANDOM}};
|
|
_T_13717 = _RAND_793[0:0];
|
|
_RAND_794 = {1{`RANDOM}};
|
|
_T_13710 = _RAND_794[0:0];
|
|
_RAND_795 = {1{`RANDOM}};
|
|
_T_13703 = _RAND_795[0:0];
|
|
_RAND_796 = {1{`RANDOM}};
|
|
_T_13696 = _RAND_796[0:0];
|
|
_RAND_797 = {1{`RANDOM}};
|
|
_T_13689 = _RAND_797[0:0];
|
|
_RAND_798 = {1{`RANDOM}};
|
|
_T_13682 = _RAND_798[0:0];
|
|
_RAND_799 = {1{`RANDOM}};
|
|
_T_13675 = _RAND_799[0:0];
|
|
_RAND_800 = {1{`RANDOM}};
|
|
_T_13668 = _RAND_800[0:0];
|
|
_RAND_801 = {1{`RANDOM}};
|
|
_T_13661 = _RAND_801[0:0];
|
|
_RAND_802 = {1{`RANDOM}};
|
|
_T_13654 = _RAND_802[0:0];
|
|
_RAND_803 = {1{`RANDOM}};
|
|
_T_13647 = _RAND_803[0:0];
|
|
_RAND_804 = {1{`RANDOM}};
|
|
_T_13640 = _RAND_804[0:0];
|
|
_RAND_805 = {1{`RANDOM}};
|
|
_T_13633 = _RAND_805[0:0];
|
|
_RAND_806 = {1{`RANDOM}};
|
|
_T_13626 = _RAND_806[0:0];
|
|
_RAND_807 = {1{`RANDOM}};
|
|
_T_13619 = _RAND_807[0:0];
|
|
_RAND_808 = {1{`RANDOM}};
|
|
_T_13612 = _RAND_808[0:0];
|
|
_RAND_809 = {1{`RANDOM}};
|
|
_T_13605 = _RAND_809[0:0];
|
|
_RAND_810 = {1{`RANDOM}};
|
|
_T_13598 = _RAND_810[0:0];
|
|
_RAND_811 = {1{`RANDOM}};
|
|
_T_13591 = _RAND_811[0:0];
|
|
_RAND_812 = {1{`RANDOM}};
|
|
_T_13584 = _RAND_812[0:0];
|
|
_RAND_813 = {1{`RANDOM}};
|
|
_T_13577 = _RAND_813[0:0];
|
|
_RAND_814 = {1{`RANDOM}};
|
|
_T_13570 = _RAND_814[0:0];
|
|
_RAND_815 = {1{`RANDOM}};
|
|
_T_13563 = _RAND_815[0:0];
|
|
_RAND_816 = {1{`RANDOM}};
|
|
_T_13556 = _RAND_816[0:0];
|
|
_RAND_817 = {1{`RANDOM}};
|
|
_T_13549 = _RAND_817[0:0];
|
|
_RAND_818 = {1{`RANDOM}};
|
|
_T_13542 = _RAND_818[0:0];
|
|
_RAND_819 = {1{`RANDOM}};
|
|
_T_13535 = _RAND_819[0:0];
|
|
_RAND_820 = {1{`RANDOM}};
|
|
_T_13528 = _RAND_820[0:0];
|
|
_RAND_821 = {1{`RANDOM}};
|
|
_T_13521 = _RAND_821[0:0];
|
|
_RAND_822 = {1{`RANDOM}};
|
|
_T_13514 = _RAND_822[0:0];
|
|
_RAND_823 = {1{`RANDOM}};
|
|
_T_13507 = _RAND_823[0:0];
|
|
_RAND_824 = {1{`RANDOM}};
|
|
_T_15031 = _RAND_824[0:0];
|
|
_RAND_825 = {1{`RANDOM}};
|
|
_T_15033 = _RAND_825[0:0];
|
|
_RAND_826 = {1{`RANDOM}};
|
|
_T_15035 = _RAND_826[0:0];
|
|
_RAND_827 = {1{`RANDOM}};
|
|
_T_15037 = _RAND_827[0:0];
|
|
_RAND_828 = {1{`RANDOM}};
|
|
_T_15039 = _RAND_828[0:0];
|
|
_RAND_829 = {1{`RANDOM}};
|
|
_T_15041 = _RAND_829[0:0];
|
|
_RAND_830 = {1{`RANDOM}};
|
|
_T_15043 = _RAND_830[0:0];
|
|
_RAND_831 = {1{`RANDOM}};
|
|
_T_15045 = _RAND_831[0:0];
|
|
_RAND_832 = {1{`RANDOM}};
|
|
_T_15047 = _RAND_832[0:0];
|
|
_RAND_833 = {1{`RANDOM}};
|
|
_T_15049 = _RAND_833[0:0];
|
|
_RAND_834 = {1{`RANDOM}};
|
|
_T_15051 = _RAND_834[0:0];
|
|
_RAND_835 = {1{`RANDOM}};
|
|
_T_15053 = _RAND_835[0:0];
|
|
_RAND_836 = {1{`RANDOM}};
|
|
_T_15055 = _RAND_836[0:0];
|
|
_RAND_837 = {1{`RANDOM}};
|
|
_T_15057 = _RAND_837[0:0];
|
|
_RAND_838 = {1{`RANDOM}};
|
|
_T_15059 = _RAND_838[0:0];
|
|
_RAND_839 = {1{`RANDOM}};
|
|
_T_15061 = _RAND_839[0:0];
|
|
_RAND_840 = {1{`RANDOM}};
|
|
_T_15063 = _RAND_840[0:0];
|
|
_RAND_841 = {1{`RANDOM}};
|
|
_T_15065 = _RAND_841[0:0];
|
|
_RAND_842 = {1{`RANDOM}};
|
|
_T_15067 = _RAND_842[0:0];
|
|
_RAND_843 = {1{`RANDOM}};
|
|
_T_15069 = _RAND_843[0:0];
|
|
_RAND_844 = {1{`RANDOM}};
|
|
_T_15071 = _RAND_844[0:0];
|
|
_RAND_845 = {1{`RANDOM}};
|
|
_T_15073 = _RAND_845[0:0];
|
|
_RAND_846 = {1{`RANDOM}};
|
|
_T_15075 = _RAND_846[0:0];
|
|
_RAND_847 = {1{`RANDOM}};
|
|
_T_15077 = _RAND_847[0:0];
|
|
_RAND_848 = {1{`RANDOM}};
|
|
_T_15079 = _RAND_848[0:0];
|
|
_RAND_849 = {1{`RANDOM}};
|
|
_T_15081 = _RAND_849[0:0];
|
|
_RAND_850 = {1{`RANDOM}};
|
|
_T_15083 = _RAND_850[0:0];
|
|
_RAND_851 = {1{`RANDOM}};
|
|
_T_15085 = _RAND_851[0:0];
|
|
_RAND_852 = {1{`RANDOM}};
|
|
_T_15087 = _RAND_852[0:0];
|
|
_RAND_853 = {1{`RANDOM}};
|
|
_T_15089 = _RAND_853[0:0];
|
|
_RAND_854 = {1{`RANDOM}};
|
|
_T_15091 = _RAND_854[0:0];
|
|
_RAND_855 = {1{`RANDOM}};
|
|
_T_15093 = _RAND_855[0:0];
|
|
_RAND_856 = {1{`RANDOM}};
|
|
_T_15095 = _RAND_856[0:0];
|
|
_RAND_857 = {1{`RANDOM}};
|
|
_T_15097 = _RAND_857[0:0];
|
|
_RAND_858 = {1{`RANDOM}};
|
|
_T_15099 = _RAND_858[0:0];
|
|
_RAND_859 = {1{`RANDOM}};
|
|
_T_15101 = _RAND_859[0:0];
|
|
_RAND_860 = {1{`RANDOM}};
|
|
_T_15103 = _RAND_860[0:0];
|
|
_RAND_861 = {1{`RANDOM}};
|
|
_T_15105 = _RAND_861[0:0];
|
|
_RAND_862 = {1{`RANDOM}};
|
|
_T_15107 = _RAND_862[0:0];
|
|
_RAND_863 = {1{`RANDOM}};
|
|
_T_15109 = _RAND_863[0:0];
|
|
_RAND_864 = {1{`RANDOM}};
|
|
_T_15111 = _RAND_864[0:0];
|
|
_RAND_865 = {1{`RANDOM}};
|
|
_T_15113 = _RAND_865[0:0];
|
|
_RAND_866 = {1{`RANDOM}};
|
|
_T_15115 = _RAND_866[0:0];
|
|
_RAND_867 = {1{`RANDOM}};
|
|
_T_15117 = _RAND_867[0:0];
|
|
_RAND_868 = {1{`RANDOM}};
|
|
_T_15119 = _RAND_868[0:0];
|
|
_RAND_869 = {1{`RANDOM}};
|
|
_T_15121 = _RAND_869[0:0];
|
|
_RAND_870 = {1{`RANDOM}};
|
|
_T_15123 = _RAND_870[0:0];
|
|
_RAND_871 = {1{`RANDOM}};
|
|
_T_15125 = _RAND_871[0:0];
|
|
_RAND_872 = {1{`RANDOM}};
|
|
_T_15127 = _RAND_872[0:0];
|
|
_RAND_873 = {1{`RANDOM}};
|
|
_T_15129 = _RAND_873[0:0];
|
|
_RAND_874 = {1{`RANDOM}};
|
|
_T_15131 = _RAND_874[0:0];
|
|
_RAND_875 = {1{`RANDOM}};
|
|
_T_15133 = _RAND_875[0:0];
|
|
_RAND_876 = {1{`RANDOM}};
|
|
_T_15135 = _RAND_876[0:0];
|
|
_RAND_877 = {1{`RANDOM}};
|
|
_T_15137 = _RAND_877[0:0];
|
|
_RAND_878 = {1{`RANDOM}};
|
|
_T_15139 = _RAND_878[0:0];
|
|
_RAND_879 = {1{`RANDOM}};
|
|
_T_15141 = _RAND_879[0:0];
|
|
_RAND_880 = {1{`RANDOM}};
|
|
_T_15143 = _RAND_880[0:0];
|
|
_RAND_881 = {1{`RANDOM}};
|
|
_T_15145 = _RAND_881[0:0];
|
|
_RAND_882 = {1{`RANDOM}};
|
|
_T_15147 = _RAND_882[0:0];
|
|
_RAND_883 = {1{`RANDOM}};
|
|
_T_15149 = _RAND_883[0:0];
|
|
_RAND_884 = {1{`RANDOM}};
|
|
_T_15151 = _RAND_884[0:0];
|
|
_RAND_885 = {1{`RANDOM}};
|
|
_T_15153 = _RAND_885[0:0];
|
|
_RAND_886 = {1{`RANDOM}};
|
|
_T_15155 = _RAND_886[0:0];
|
|
_RAND_887 = {1{`RANDOM}};
|
|
_T_15157 = _RAND_887[0:0];
|
|
_RAND_888 = {1{`RANDOM}};
|
|
_T_15159 = _RAND_888[0:0];
|
|
_RAND_889 = {1{`RANDOM}};
|
|
_T_15161 = _RAND_889[0:0];
|
|
_RAND_890 = {1{`RANDOM}};
|
|
_T_15163 = _RAND_890[0:0];
|
|
_RAND_891 = {1{`RANDOM}};
|
|
_T_15165 = _RAND_891[0:0];
|
|
_RAND_892 = {1{`RANDOM}};
|
|
_T_15167 = _RAND_892[0:0];
|
|
_RAND_893 = {1{`RANDOM}};
|
|
_T_15169 = _RAND_893[0:0];
|
|
_RAND_894 = {1{`RANDOM}};
|
|
_T_15171 = _RAND_894[0:0];
|
|
_RAND_895 = {1{`RANDOM}};
|
|
_T_15173 = _RAND_895[0:0];
|
|
_RAND_896 = {1{`RANDOM}};
|
|
_T_15175 = _RAND_896[0:0];
|
|
_RAND_897 = {1{`RANDOM}};
|
|
_T_15177 = _RAND_897[0:0];
|
|
_RAND_898 = {1{`RANDOM}};
|
|
_T_15179 = _RAND_898[0:0];
|
|
_RAND_899 = {1{`RANDOM}};
|
|
_T_15181 = _RAND_899[0:0];
|
|
_RAND_900 = {1{`RANDOM}};
|
|
_T_15183 = _RAND_900[0:0];
|
|
_RAND_901 = {1{`RANDOM}};
|
|
_T_15185 = _RAND_901[0:0];
|
|
_RAND_902 = {1{`RANDOM}};
|
|
_T_15187 = _RAND_902[0:0];
|
|
_RAND_903 = {1{`RANDOM}};
|
|
_T_15189 = _RAND_903[0:0];
|
|
_RAND_904 = {1{`RANDOM}};
|
|
_T_15191 = _RAND_904[0:0];
|
|
_RAND_905 = {1{`RANDOM}};
|
|
_T_15193 = _RAND_905[0:0];
|
|
_RAND_906 = {1{`RANDOM}};
|
|
_T_15195 = _RAND_906[0:0];
|
|
_RAND_907 = {1{`RANDOM}};
|
|
_T_15197 = _RAND_907[0:0];
|
|
_RAND_908 = {1{`RANDOM}};
|
|
_T_15199 = _RAND_908[0:0];
|
|
_RAND_909 = {1{`RANDOM}};
|
|
_T_15201 = _RAND_909[0:0];
|
|
_RAND_910 = {1{`RANDOM}};
|
|
_T_15203 = _RAND_910[0:0];
|
|
_RAND_911 = {1{`RANDOM}};
|
|
_T_15205 = _RAND_911[0:0];
|
|
_RAND_912 = {1{`RANDOM}};
|
|
_T_15207 = _RAND_912[0:0];
|
|
_RAND_913 = {1{`RANDOM}};
|
|
_T_15209 = _RAND_913[0:0];
|
|
_RAND_914 = {2{`RANDOM}};
|
|
fifo_data_0 = _RAND_914[63:0];
|
|
_RAND_915 = {2{`RANDOM}};
|
|
fifo_data_1 = _RAND_915[63:0];
|
|
_RAND_916 = {2{`RANDOM}};
|
|
fifo_data_2 = _RAND_916[63:0];
|
|
_RAND_917 = {2{`RANDOM}};
|
|
fifo_data_3 = _RAND_917[63:0];
|
|
_RAND_918 = {2{`RANDOM}};
|
|
fifo_data_4 = _RAND_918[63:0];
|
|
_RAND_919 = {2{`RANDOM}};
|
|
fifo_data_5 = _RAND_919[63:0];
|
|
_RAND_920 = {2{`RANDOM}};
|
|
fifo_data_6 = _RAND_920[63:0];
|
|
_RAND_921 = {2{`RANDOM}};
|
|
fifo_data_7 = _RAND_921[63:0];
|
|
_RAND_922 = {2{`RANDOM}};
|
|
fifo_data_8 = _RAND_922[63:0];
|
|
_RAND_923 = {2{`RANDOM}};
|
|
fifo_data_9 = _RAND_923[63:0];
|
|
_RAND_924 = {2{`RANDOM}};
|
|
fifo_data_10 = _RAND_924[63:0];
|
|
_RAND_925 = {2{`RANDOM}};
|
|
fifo_data_11 = _RAND_925[63:0];
|
|
_RAND_926 = {2{`RANDOM}};
|
|
fifo_data_12 = _RAND_926[63:0];
|
|
_RAND_927 = {2{`RANDOM}};
|
|
fifo_data_13 = _RAND_927[63:0];
|
|
_RAND_928 = {2{`RANDOM}};
|
|
fifo_data_14 = _RAND_928[63:0];
|
|
_RAND_929 = {2{`RANDOM}};
|
|
fifo_data_15 = _RAND_929[63:0];
|
|
_RAND_930 = {2{`RANDOM}};
|
|
fifo_data_16 = _RAND_930[63:0];
|
|
_RAND_931 = {2{`RANDOM}};
|
|
fifo_data_17 = _RAND_931[63:0];
|
|
_RAND_932 = {2{`RANDOM}};
|
|
fifo_data_18 = _RAND_932[63:0];
|
|
_RAND_933 = {2{`RANDOM}};
|
|
fifo_data_19 = _RAND_933[63:0];
|
|
_RAND_934 = {2{`RANDOM}};
|
|
fifo_data_20 = _RAND_934[63:0];
|
|
_RAND_935 = {2{`RANDOM}};
|
|
fifo_data_21 = _RAND_935[63:0];
|
|
_RAND_936 = {2{`RANDOM}};
|
|
fifo_data_22 = _RAND_936[63:0];
|
|
_RAND_937 = {2{`RANDOM}};
|
|
fifo_data_23 = _RAND_937[63:0];
|
|
_RAND_938 = {2{`RANDOM}};
|
|
fifo_data_24 = _RAND_938[63:0];
|
|
_RAND_939 = {2{`RANDOM}};
|
|
fifo_data_25 = _RAND_939[63:0];
|
|
_RAND_940 = {2{`RANDOM}};
|
|
fifo_data_26 = _RAND_940[63:0];
|
|
_RAND_941 = {2{`RANDOM}};
|
|
fifo_data_27 = _RAND_941[63:0];
|
|
_RAND_942 = {2{`RANDOM}};
|
|
fifo_data_28 = _RAND_942[63:0];
|
|
_RAND_943 = {2{`RANDOM}};
|
|
fifo_data_29 = _RAND_943[63:0];
|
|
_RAND_944 = {2{`RANDOM}};
|
|
fifo_data_30 = _RAND_944[63:0];
|
|
_RAND_945 = {2{`RANDOM}};
|
|
fifo_data_31 = _RAND_945[63:0];
|
|
_RAND_946 = {2{`RANDOM}};
|
|
fifo_data_32 = _RAND_946[63:0];
|
|
_RAND_947 = {2{`RANDOM}};
|
|
fifo_data_33 = _RAND_947[63:0];
|
|
_RAND_948 = {2{`RANDOM}};
|
|
fifo_data_34 = _RAND_948[63:0];
|
|
_RAND_949 = {2{`RANDOM}};
|
|
fifo_data_35 = _RAND_949[63:0];
|
|
_RAND_950 = {2{`RANDOM}};
|
|
fifo_data_36 = _RAND_950[63:0];
|
|
_RAND_951 = {2{`RANDOM}};
|
|
fifo_data_37 = _RAND_951[63:0];
|
|
_RAND_952 = {2{`RANDOM}};
|
|
fifo_data_38 = _RAND_952[63:0];
|
|
_RAND_953 = {2{`RANDOM}};
|
|
fifo_data_39 = _RAND_953[63:0];
|
|
_RAND_954 = {2{`RANDOM}};
|
|
fifo_data_40 = _RAND_954[63:0];
|
|
_RAND_955 = {2{`RANDOM}};
|
|
fifo_data_41 = _RAND_955[63:0];
|
|
_RAND_956 = {2{`RANDOM}};
|
|
fifo_data_42 = _RAND_956[63:0];
|
|
_RAND_957 = {2{`RANDOM}};
|
|
fifo_data_43 = _RAND_957[63:0];
|
|
_RAND_958 = {2{`RANDOM}};
|
|
fifo_data_44 = _RAND_958[63:0];
|
|
_RAND_959 = {2{`RANDOM}};
|
|
fifo_data_45 = _RAND_959[63:0];
|
|
_RAND_960 = {2{`RANDOM}};
|
|
fifo_data_46 = _RAND_960[63:0];
|
|
_RAND_961 = {2{`RANDOM}};
|
|
fifo_data_47 = _RAND_961[63:0];
|
|
_RAND_962 = {2{`RANDOM}};
|
|
fifo_data_48 = _RAND_962[63:0];
|
|
_RAND_963 = {2{`RANDOM}};
|
|
fifo_data_49 = _RAND_963[63:0];
|
|
_RAND_964 = {2{`RANDOM}};
|
|
fifo_data_50 = _RAND_964[63:0];
|
|
_RAND_965 = {2{`RANDOM}};
|
|
fifo_data_51 = _RAND_965[63:0];
|
|
_RAND_966 = {2{`RANDOM}};
|
|
fifo_data_52 = _RAND_966[63:0];
|
|
_RAND_967 = {2{`RANDOM}};
|
|
fifo_data_53 = _RAND_967[63:0];
|
|
_RAND_968 = {2{`RANDOM}};
|
|
fifo_data_54 = _RAND_968[63:0];
|
|
_RAND_969 = {2{`RANDOM}};
|
|
fifo_data_55 = _RAND_969[63:0];
|
|
_RAND_970 = {2{`RANDOM}};
|
|
fifo_data_56 = _RAND_970[63:0];
|
|
_RAND_971 = {2{`RANDOM}};
|
|
fifo_data_57 = _RAND_971[63:0];
|
|
_RAND_972 = {2{`RANDOM}};
|
|
fifo_data_58 = _RAND_972[63:0];
|
|
_RAND_973 = {2{`RANDOM}};
|
|
fifo_data_59 = _RAND_973[63:0];
|
|
_RAND_974 = {2{`RANDOM}};
|
|
fifo_data_60 = _RAND_974[63:0];
|
|
_RAND_975 = {2{`RANDOM}};
|
|
fifo_data_61 = _RAND_975[63:0];
|
|
_RAND_976 = {2{`RANDOM}};
|
|
fifo_data_62 = _RAND_976[63:0];
|
|
_RAND_977 = {2{`RANDOM}};
|
|
fifo_data_63 = _RAND_977[63:0];
|
|
_RAND_978 = {2{`RANDOM}};
|
|
fifo_data_64 = _RAND_978[63:0];
|
|
_RAND_979 = {2{`RANDOM}};
|
|
fifo_data_65 = _RAND_979[63:0];
|
|
_RAND_980 = {2{`RANDOM}};
|
|
fifo_data_66 = _RAND_980[63:0];
|
|
_RAND_981 = {2{`RANDOM}};
|
|
fifo_data_67 = _RAND_981[63:0];
|
|
_RAND_982 = {2{`RANDOM}};
|
|
fifo_data_68 = _RAND_982[63:0];
|
|
_RAND_983 = {2{`RANDOM}};
|
|
fifo_data_69 = _RAND_983[63:0];
|
|
_RAND_984 = {2{`RANDOM}};
|
|
fifo_data_70 = _RAND_984[63:0];
|
|
_RAND_985 = {2{`RANDOM}};
|
|
fifo_data_71 = _RAND_985[63:0];
|
|
_RAND_986 = {2{`RANDOM}};
|
|
fifo_data_72 = _RAND_986[63:0];
|
|
_RAND_987 = {2{`RANDOM}};
|
|
fifo_data_73 = _RAND_987[63:0];
|
|
_RAND_988 = {2{`RANDOM}};
|
|
fifo_data_74 = _RAND_988[63:0];
|
|
_RAND_989 = {2{`RANDOM}};
|
|
fifo_data_75 = _RAND_989[63:0];
|
|
_RAND_990 = {2{`RANDOM}};
|
|
fifo_data_76 = _RAND_990[63:0];
|
|
_RAND_991 = {2{`RANDOM}};
|
|
fifo_data_77 = _RAND_991[63:0];
|
|
_RAND_992 = {2{`RANDOM}};
|
|
fifo_data_78 = _RAND_992[63:0];
|
|
_RAND_993 = {2{`RANDOM}};
|
|
fifo_data_79 = _RAND_993[63:0];
|
|
_RAND_994 = {2{`RANDOM}};
|
|
fifo_data_80 = _RAND_994[63:0];
|
|
_RAND_995 = {2{`RANDOM}};
|
|
fifo_data_81 = _RAND_995[63:0];
|
|
_RAND_996 = {2{`RANDOM}};
|
|
fifo_data_82 = _RAND_996[63:0];
|
|
_RAND_997 = {2{`RANDOM}};
|
|
fifo_data_83 = _RAND_997[63:0];
|
|
_RAND_998 = {2{`RANDOM}};
|
|
fifo_data_84 = _RAND_998[63:0];
|
|
_RAND_999 = {2{`RANDOM}};
|
|
fifo_data_85 = _RAND_999[63:0];
|
|
_RAND_1000 = {2{`RANDOM}};
|
|
fifo_data_86 = _RAND_1000[63:0];
|
|
_RAND_1001 = {2{`RANDOM}};
|
|
fifo_data_87 = _RAND_1001[63:0];
|
|
_RAND_1002 = {2{`RANDOM}};
|
|
fifo_data_88 = _RAND_1002[63:0];
|
|
_RAND_1003 = {2{`RANDOM}};
|
|
fifo_data_89 = _RAND_1003[63:0];
|
|
_RAND_1004 = {1{`RANDOM}};
|
|
fifo_tag_0 = _RAND_1004[0:0];
|
|
_RAND_1005 = {1{`RANDOM}};
|
|
wrbuf_tag = _RAND_1005[0:0];
|
|
_RAND_1006 = {1{`RANDOM}};
|
|
rdbuf_tag = _RAND_1006[0:0];
|
|
_RAND_1007 = {1{`RANDOM}};
|
|
fifo_tag_1 = _RAND_1007[0:0];
|
|
_RAND_1008 = {1{`RANDOM}};
|
|
fifo_tag_2 = _RAND_1008[0:0];
|
|
_RAND_1009 = {1{`RANDOM}};
|
|
fifo_tag_3 = _RAND_1009[0:0];
|
|
_RAND_1010 = {1{`RANDOM}};
|
|
fifo_tag_4 = _RAND_1010[0:0];
|
|
_RAND_1011 = {1{`RANDOM}};
|
|
fifo_tag_5 = _RAND_1011[0:0];
|
|
_RAND_1012 = {1{`RANDOM}};
|
|
fifo_tag_6 = _RAND_1012[0:0];
|
|
_RAND_1013 = {1{`RANDOM}};
|
|
fifo_tag_7 = _RAND_1013[0:0];
|
|
_RAND_1014 = {1{`RANDOM}};
|
|
fifo_tag_8 = _RAND_1014[0:0];
|
|
_RAND_1015 = {1{`RANDOM}};
|
|
fifo_tag_9 = _RAND_1015[0:0];
|
|
_RAND_1016 = {1{`RANDOM}};
|
|
fifo_tag_10 = _RAND_1016[0:0];
|
|
_RAND_1017 = {1{`RANDOM}};
|
|
fifo_tag_11 = _RAND_1017[0:0];
|
|
_RAND_1018 = {1{`RANDOM}};
|
|
fifo_tag_12 = _RAND_1018[0:0];
|
|
_RAND_1019 = {1{`RANDOM}};
|
|
fifo_tag_13 = _RAND_1019[0:0];
|
|
_RAND_1020 = {1{`RANDOM}};
|
|
fifo_tag_14 = _RAND_1020[0:0];
|
|
_RAND_1021 = {1{`RANDOM}};
|
|
fifo_tag_15 = _RAND_1021[0:0];
|
|
_RAND_1022 = {1{`RANDOM}};
|
|
fifo_tag_16 = _RAND_1022[0:0];
|
|
_RAND_1023 = {1{`RANDOM}};
|
|
fifo_tag_17 = _RAND_1023[0:0];
|
|
_RAND_1024 = {1{`RANDOM}};
|
|
fifo_tag_18 = _RAND_1024[0:0];
|
|
_RAND_1025 = {1{`RANDOM}};
|
|
fifo_tag_19 = _RAND_1025[0:0];
|
|
_RAND_1026 = {1{`RANDOM}};
|
|
fifo_tag_20 = _RAND_1026[0:0];
|
|
_RAND_1027 = {1{`RANDOM}};
|
|
fifo_tag_21 = _RAND_1027[0:0];
|
|
_RAND_1028 = {1{`RANDOM}};
|
|
fifo_tag_22 = _RAND_1028[0:0];
|
|
_RAND_1029 = {1{`RANDOM}};
|
|
fifo_tag_23 = _RAND_1029[0:0];
|
|
_RAND_1030 = {1{`RANDOM}};
|
|
fifo_tag_24 = _RAND_1030[0:0];
|
|
_RAND_1031 = {1{`RANDOM}};
|
|
fifo_tag_25 = _RAND_1031[0:0];
|
|
_RAND_1032 = {1{`RANDOM}};
|
|
fifo_tag_26 = _RAND_1032[0:0];
|
|
_RAND_1033 = {1{`RANDOM}};
|
|
fifo_tag_27 = _RAND_1033[0:0];
|
|
_RAND_1034 = {1{`RANDOM}};
|
|
fifo_tag_28 = _RAND_1034[0:0];
|
|
_RAND_1035 = {1{`RANDOM}};
|
|
fifo_tag_29 = _RAND_1035[0:0];
|
|
_RAND_1036 = {1{`RANDOM}};
|
|
fifo_tag_30 = _RAND_1036[0:0];
|
|
_RAND_1037 = {1{`RANDOM}};
|
|
fifo_tag_31 = _RAND_1037[0:0];
|
|
_RAND_1038 = {1{`RANDOM}};
|
|
fifo_tag_32 = _RAND_1038[0:0];
|
|
_RAND_1039 = {1{`RANDOM}};
|
|
fifo_tag_33 = _RAND_1039[0:0];
|
|
_RAND_1040 = {1{`RANDOM}};
|
|
fifo_tag_34 = _RAND_1040[0:0];
|
|
_RAND_1041 = {1{`RANDOM}};
|
|
fifo_tag_35 = _RAND_1041[0:0];
|
|
_RAND_1042 = {1{`RANDOM}};
|
|
fifo_tag_36 = _RAND_1042[0:0];
|
|
_RAND_1043 = {1{`RANDOM}};
|
|
fifo_tag_37 = _RAND_1043[0:0];
|
|
_RAND_1044 = {1{`RANDOM}};
|
|
fifo_tag_38 = _RAND_1044[0:0];
|
|
_RAND_1045 = {1{`RANDOM}};
|
|
fifo_tag_39 = _RAND_1045[0:0];
|
|
_RAND_1046 = {1{`RANDOM}};
|
|
fifo_tag_40 = _RAND_1046[0:0];
|
|
_RAND_1047 = {1{`RANDOM}};
|
|
fifo_tag_41 = _RAND_1047[0:0];
|
|
_RAND_1048 = {1{`RANDOM}};
|
|
fifo_tag_42 = _RAND_1048[0:0];
|
|
_RAND_1049 = {1{`RANDOM}};
|
|
fifo_tag_43 = _RAND_1049[0:0];
|
|
_RAND_1050 = {1{`RANDOM}};
|
|
fifo_tag_44 = _RAND_1050[0:0];
|
|
_RAND_1051 = {1{`RANDOM}};
|
|
fifo_tag_45 = _RAND_1051[0:0];
|
|
_RAND_1052 = {1{`RANDOM}};
|
|
fifo_tag_46 = _RAND_1052[0:0];
|
|
_RAND_1053 = {1{`RANDOM}};
|
|
fifo_tag_47 = _RAND_1053[0:0];
|
|
_RAND_1054 = {1{`RANDOM}};
|
|
fifo_tag_48 = _RAND_1054[0:0];
|
|
_RAND_1055 = {1{`RANDOM}};
|
|
fifo_tag_49 = _RAND_1055[0:0];
|
|
_RAND_1056 = {1{`RANDOM}};
|
|
fifo_tag_50 = _RAND_1056[0:0];
|
|
_RAND_1057 = {1{`RANDOM}};
|
|
fifo_tag_51 = _RAND_1057[0:0];
|
|
_RAND_1058 = {1{`RANDOM}};
|
|
fifo_tag_52 = _RAND_1058[0:0];
|
|
_RAND_1059 = {1{`RANDOM}};
|
|
fifo_tag_53 = _RAND_1059[0:0];
|
|
_RAND_1060 = {1{`RANDOM}};
|
|
fifo_tag_54 = _RAND_1060[0:0];
|
|
_RAND_1061 = {1{`RANDOM}};
|
|
fifo_tag_55 = _RAND_1061[0:0];
|
|
_RAND_1062 = {1{`RANDOM}};
|
|
fifo_tag_56 = _RAND_1062[0:0];
|
|
_RAND_1063 = {1{`RANDOM}};
|
|
fifo_tag_57 = _RAND_1063[0:0];
|
|
_RAND_1064 = {1{`RANDOM}};
|
|
fifo_tag_58 = _RAND_1064[0:0];
|
|
_RAND_1065 = {1{`RANDOM}};
|
|
fifo_tag_59 = _RAND_1065[0:0];
|
|
_RAND_1066 = {1{`RANDOM}};
|
|
fifo_tag_60 = _RAND_1066[0:0];
|
|
_RAND_1067 = {1{`RANDOM}};
|
|
fifo_tag_61 = _RAND_1067[0:0];
|
|
_RAND_1068 = {1{`RANDOM}};
|
|
fifo_tag_62 = _RAND_1068[0:0];
|
|
_RAND_1069 = {1{`RANDOM}};
|
|
fifo_tag_63 = _RAND_1069[0:0];
|
|
_RAND_1070 = {1{`RANDOM}};
|
|
fifo_tag_64 = _RAND_1070[0:0];
|
|
_RAND_1071 = {1{`RANDOM}};
|
|
fifo_tag_65 = _RAND_1071[0:0];
|
|
_RAND_1072 = {1{`RANDOM}};
|
|
fifo_tag_66 = _RAND_1072[0:0];
|
|
_RAND_1073 = {1{`RANDOM}};
|
|
fifo_tag_67 = _RAND_1073[0:0];
|
|
_RAND_1074 = {1{`RANDOM}};
|
|
fifo_tag_68 = _RAND_1074[0:0];
|
|
_RAND_1075 = {1{`RANDOM}};
|
|
fifo_tag_69 = _RAND_1075[0:0];
|
|
_RAND_1076 = {1{`RANDOM}};
|
|
fifo_tag_70 = _RAND_1076[0:0];
|
|
_RAND_1077 = {1{`RANDOM}};
|
|
fifo_tag_71 = _RAND_1077[0:0];
|
|
_RAND_1078 = {1{`RANDOM}};
|
|
fifo_tag_72 = _RAND_1078[0:0];
|
|
_RAND_1079 = {1{`RANDOM}};
|
|
fifo_tag_73 = _RAND_1079[0:0];
|
|
_RAND_1080 = {1{`RANDOM}};
|
|
fifo_tag_74 = _RAND_1080[0:0];
|
|
_RAND_1081 = {1{`RANDOM}};
|
|
fifo_tag_75 = _RAND_1081[0:0];
|
|
_RAND_1082 = {1{`RANDOM}};
|
|
fifo_tag_76 = _RAND_1082[0:0];
|
|
_RAND_1083 = {1{`RANDOM}};
|
|
fifo_tag_77 = _RAND_1083[0:0];
|
|
_RAND_1084 = {1{`RANDOM}};
|
|
fifo_tag_78 = _RAND_1084[0:0];
|
|
_RAND_1085 = {1{`RANDOM}};
|
|
fifo_tag_79 = _RAND_1085[0:0];
|
|
_RAND_1086 = {1{`RANDOM}};
|
|
fifo_tag_80 = _RAND_1086[0:0];
|
|
_RAND_1087 = {1{`RANDOM}};
|
|
fifo_tag_81 = _RAND_1087[0:0];
|
|
_RAND_1088 = {1{`RANDOM}};
|
|
fifo_tag_82 = _RAND_1088[0:0];
|
|
_RAND_1089 = {1{`RANDOM}};
|
|
fifo_tag_83 = _RAND_1089[0:0];
|
|
_RAND_1090 = {1{`RANDOM}};
|
|
fifo_tag_84 = _RAND_1090[0:0];
|
|
_RAND_1091 = {1{`RANDOM}};
|
|
fifo_tag_85 = _RAND_1091[0:0];
|
|
_RAND_1092 = {1{`RANDOM}};
|
|
fifo_tag_86 = _RAND_1092[0:0];
|
|
_RAND_1093 = {1{`RANDOM}};
|
|
fifo_tag_87 = _RAND_1093[0:0];
|
|
_RAND_1094 = {1{`RANDOM}};
|
|
fifo_tag_88 = _RAND_1094[0:0];
|
|
_RAND_1095 = {1{`RANDOM}};
|
|
fifo_tag_89 = _RAND_1095[0:0];
|
|
_RAND_1096 = {1{`RANDOM}};
|
|
dma_nack_count = _RAND_1096[2:0];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
wrbuf_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_data_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_vld = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10444 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10437 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10430 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10423 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10416 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10409 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10402 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10395 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10388 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10381 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10374 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10367 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10360 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10353 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10346 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10339 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10332 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10325 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10318 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10311 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10304 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10297 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10290 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10283 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10276 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10269 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10262 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10255 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10248 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10241 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10234 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10227 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10220 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10213 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10206 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10199 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10192 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10185 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10178 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10171 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10164 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10157 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10150 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10143 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10136 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10129 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10122 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10108 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10094 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10087 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10080 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10073 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10066 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10059 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10052 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10045 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10038 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10031 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10024 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10017 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10010 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_10003 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9996 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9989 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9982 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9975 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9968 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9961 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9954 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9947 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9940 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9933 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9926 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9919 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9912 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9905 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9898 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9891 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9884 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9877 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9870 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9863 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9856 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9849 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9842 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9835 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9828 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_9821 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
axi_mstr_priority = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_addr = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_byteen = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_sz = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_sz = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
dbg_dma_bubble_bus = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
WrPtr = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
RdPtr = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13411 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13404 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13397 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13390 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13383 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13376 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13369 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13362 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13355 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13348 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13341 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13334 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13327 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13320 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13313 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13306 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13299 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13292 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13285 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13278 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13271 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13264 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13257 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13250 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13243 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13236 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13229 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13222 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13215 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13208 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13201 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13194 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13187 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13180 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13173 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13166 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13159 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13152 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13145 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13138 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13131 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13124 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13110 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13096 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13089 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13082 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13075 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13068 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13061 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13054 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13047 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13040 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13033 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13026 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13019 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13012 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13005 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12998 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12991 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12984 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12977 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12970 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12963 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12956 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12949 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12942 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12935 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12928 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12921 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12914 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12907 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12900 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12893 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12886 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12879 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12872 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12865 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12858 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12851 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12844 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12837 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12830 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12823 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12816 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12809 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12802 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12795 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12788 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15745 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15743 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15741 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15739 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15737 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15735 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15733 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15731 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15729 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15727 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15725 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15723 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15721 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15719 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15717 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15715 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15713 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15711 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15709 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15707 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15705 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15703 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15701 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15699 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15697 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15695 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15693 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15691 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15689 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15687 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15685 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15683 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15681 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15679 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15677 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15675 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15673 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15671 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15669 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15667 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15665 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15663 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15661 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15659 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15657 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15655 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15653 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15651 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15649 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15647 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15645 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15643 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15641 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15639 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15637 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15635 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15633 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15631 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15629 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15627 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15625 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15623 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15621 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15619 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15617 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15615 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15613 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15611 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15609 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15607 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15605 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15603 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15601 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15599 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15597 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15595 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15593 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15591 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15589 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15587 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15585 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15583 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15581 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15579 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15577 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15575 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15573 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15571 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15569 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15567 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_89 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_88 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_87 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_86 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_85 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_84 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_83 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_82 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_81 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_80 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_79 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_78 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_77 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_76 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_75 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_74 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_73 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_72 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_71 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_70 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_69 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_68 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_67 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_66 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_65 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_64 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_63 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_62 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_61 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_60 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_59 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_58 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_57 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_56 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_55 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_54 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_53 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_52 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_51 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_50 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_49 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_48 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_47 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_46 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_45 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_44 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_43 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_42 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_41 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_40 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_39 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_38 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_37 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_36 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_35 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_34 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_33 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_32 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_31 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_30 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_29 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_28 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_27 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_26 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_25 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_24 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_23 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_22 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_21 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_20 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_19 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_18 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_17 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_16 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_15 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_14 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_13 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_12 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_11 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_10 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_9 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_8 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_7 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_6 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_5 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_4 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_3 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_2 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_1 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_addr_0 = 32'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_89 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_88 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_87 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_86 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_85 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_84 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_83 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_82 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_81 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_80 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_79 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_78 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_77 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_76 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_75 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_74 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_73 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_72 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_71 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_70 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_69 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_68 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_67 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_66 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_65 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_64 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_63 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_62 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_61 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_60 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_59 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_58 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_57 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_56 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_55 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_54 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_53 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_52 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_51 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_50 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_49 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_48 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_47 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_46 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_45 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_44 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_43 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_42 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_41 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_40 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_39 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_38 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_37 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_36 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_35 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_34 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_33 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_32 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_31 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_30 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_29 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_28 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_27 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_26 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_25 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_24 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_23 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_22 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_21 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_20 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_19 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_18 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_17 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_16 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_15 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_14 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_13 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_12 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_11 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_10 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_9 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_8 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_7 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_6 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_5 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_4 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_3 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_2 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_1 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_sz_0 = 3'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_89 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_88 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_87 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_86 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_85 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_84 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_83 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_82 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_81 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_80 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_79 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_78 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_77 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_76 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_75 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_74 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_73 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_72 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_71 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_70 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_69 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_68 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_67 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_66 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_65 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_64 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_63 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_62 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_61 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_60 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_59 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_58 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_57 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_56 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_55 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_54 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_53 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_52 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_51 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_50 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_49 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_48 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_47 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_46 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_45 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_44 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_43 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_42 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_41 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_40 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_39 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_38 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_37 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_36 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_35 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_34 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_33 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_32 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_31 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_30 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_29 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_28 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_27 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_26 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_25 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_24 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_23 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_22 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_21 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_20 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_19 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_18 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_17 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_16 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_15 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_14 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_13 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_12 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_11 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_10 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_9 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_8 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_7 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_6 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_5 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_4 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_3 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_2 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_1 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_byteen_0 = 8'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_0 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_1 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_2 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_3 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_4 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_5 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_6 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_7 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_8 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_9 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_10 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_11 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_12 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_13 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_14 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_15 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_16 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_17 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_18 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_19 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_20 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_21 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_22 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_23 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_24 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_25 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_26 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_27 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_28 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_29 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_30 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_31 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_32 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_33 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_34 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_35 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_36 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_37 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_38 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_39 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_40 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_41 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_42 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_43 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_44 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_45 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_46 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_47 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_48 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_49 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_50 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_51 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_52 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_53 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_54 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_55 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_56 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_57 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_58 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_59 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_60 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_61 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_62 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_63 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_64 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_65 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_66 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_67 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_68 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_69 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_70 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_71 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_72 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_73 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_74 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_75 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_76 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_77 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_78 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_79 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_80 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_81 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_82 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_83 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_84 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_85 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_86 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_87 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_88 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_error_89 = 2'h0;
|
|
end
|
|
if (reset) begin
|
|
RspPtr = 7'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_data = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12692 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12685 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12678 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12671 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12664 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12657 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12650 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12643 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12636 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12629 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12622 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12615 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12608 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12601 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12594 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12587 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12580 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12573 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12566 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12559 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12552 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12545 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12538 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12531 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12524 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12517 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12510 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12503 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12496 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12489 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12482 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12475 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12468 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12461 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12454 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12447 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12440 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12433 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12426 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12419 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12412 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12405 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12398 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12391 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12384 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12377 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12370 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12363 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12356 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12349 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12342 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12335 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12328 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12321 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12314 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12307 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12300 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12293 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12286 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12279 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12272 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12265 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12258 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12251 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12244 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12237 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12230 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12223 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12216 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12209 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12202 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12195 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12188 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12181 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12174 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12167 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12160 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12153 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12146 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12139 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12132 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12118 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12104 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12097 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12090 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12083 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12076 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_12069 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14130 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14116 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14102 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14095 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14088 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14081 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14074 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14067 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14060 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14053 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14046 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14039 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14032 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14025 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14018 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14011 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_14004 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13997 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13990 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13983 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13976 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13969 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13962 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13955 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13948 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13941 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13934 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13927 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13920 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13913 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13906 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13899 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13892 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13885 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13878 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13871 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13864 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13857 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13850 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13843 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13836 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13829 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13822 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13815 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13808 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13801 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13794 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13787 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13780 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13773 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13766 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13759 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13752 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13745 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13738 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13731 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13724 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13717 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13710 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13703 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13696 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13689 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13682 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13675 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13668 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13661 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13654 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13647 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13640 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13633 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13626 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13619 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13612 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13605 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13598 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13591 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13584 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13577 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13570 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13563 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13556 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13549 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13542 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13535 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13528 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13521 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13514 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_13507 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15031 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15033 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15035 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15037 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15039 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15041 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15043 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15045 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15047 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15049 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15051 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15053 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15055 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15057 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15059 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15061 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15063 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15065 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15067 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15069 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15071 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15073 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15075 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15077 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15079 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15081 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15083 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15085 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15087 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15089 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15091 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15093 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15095 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15097 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15099 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15101 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15103 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15105 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15107 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15109 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15111 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15113 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15115 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15117 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15119 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15121 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15123 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15125 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15127 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15129 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15131 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15133 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15135 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15137 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15139 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15141 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15143 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15145 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15147 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15149 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15151 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15153 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15155 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15157 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15159 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15161 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15163 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15165 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15167 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15169 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15171 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15173 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15175 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15177 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15179 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15181 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15183 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15185 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15187 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15189 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15191 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15193 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15195 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15197 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15199 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15201 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15203 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15205 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15207 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
_T_15209 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_0 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_1 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_2 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_3 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_4 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_5 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_6 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_7 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_8 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_9 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_10 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_11 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_12 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_13 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_14 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_15 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_16 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_17 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_18 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_19 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_20 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_21 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_22 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_23 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_24 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_25 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_26 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_27 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_28 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_29 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_30 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_31 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_32 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_33 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_34 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_35 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_36 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_37 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_38 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_39 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_40 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_41 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_42 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_43 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_44 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_45 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_46 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_47 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_48 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_49 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_50 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_51 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_52 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_53 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_54 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_55 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_56 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_57 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_58 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_59 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_60 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_61 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_62 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_63 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_64 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_65 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_66 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_67 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_68 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_69 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_70 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_71 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_72 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_73 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_74 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_75 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_76 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_77 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_78 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_79 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_80 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_81 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_82 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_83 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_84 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_85 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_86 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_87 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_88 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_data_89 = 64'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_0 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
wrbuf_tag = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
rdbuf_tag = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_1 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_2 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_3 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_4 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_5 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_6 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_7 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_8 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_9 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_10 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_11 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_12 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_13 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_14 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_15 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_16 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_17 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_18 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_19 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_20 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_21 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_22 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_23 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_24 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_25 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_26 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_27 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_28 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_29 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_30 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_31 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_32 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_33 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_34 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_35 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_36 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_37 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_38 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_39 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_40 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_41 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_42 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_43 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_44 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_45 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_46 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_47 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_48 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_49 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_50 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_51 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_52 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_53 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_54 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_55 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_56 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_57 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_58 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_59 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_60 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_61 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_62 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_63 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_64 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_65 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_66 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_67 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_68 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_69 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_70 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_71 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_72 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_73 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_74 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_75 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_76 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_77 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_78 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_79 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_80 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_81 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_82 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_83 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_84 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_85 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_86 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_87 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_88 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
fifo_tag_89 = 1'h0;
|
|
end
|
|
if (reset) begin
|
|
dma_nack_count = 3'h0;
|
|
end
|
|
`endif // RANDOMIZE
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif
|
|
`endif // SYNTHESIS
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_vld <= 1'h0;
|
|
end else if (_T_17240) begin
|
|
wrbuf_vld <= _T_17237;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_data_vld <= 1'h0;
|
|
end else if (_T_17246) begin
|
|
wrbuf_data_vld <= _T_17243;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_vld <= 1'h0;
|
|
end else if (_T_17259) begin
|
|
rdbuf_vld <= _T_17256;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10444 <= 1'h0;
|
|
end else begin
|
|
_T_10444 <= _T_10440 & _T_10442;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10437 <= 1'h0;
|
|
end else begin
|
|
_T_10437 <= _T_10433 & _T_10435;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10430 <= 1'h0;
|
|
end else begin
|
|
_T_10430 <= _T_10426 & _T_10428;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10423 <= 1'h0;
|
|
end else begin
|
|
_T_10423 <= _T_10419 & _T_10421;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10416 <= 1'h0;
|
|
end else begin
|
|
_T_10416 <= _T_10412 & _T_10414;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10409 <= 1'h0;
|
|
end else begin
|
|
_T_10409 <= _T_10405 & _T_10407;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10402 <= 1'h0;
|
|
end else begin
|
|
_T_10402 <= _T_10398 & _T_10400;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10395 <= 1'h0;
|
|
end else begin
|
|
_T_10395 <= _T_10391 & _T_10393;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10388 <= 1'h0;
|
|
end else begin
|
|
_T_10388 <= _T_10384 & _T_10386;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10381 <= 1'h0;
|
|
end else begin
|
|
_T_10381 <= _T_10377 & _T_10379;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10374 <= 1'h0;
|
|
end else begin
|
|
_T_10374 <= _T_10370 & _T_10372;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10367 <= 1'h0;
|
|
end else begin
|
|
_T_10367 <= _T_10363 & _T_10365;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10360 <= 1'h0;
|
|
end else begin
|
|
_T_10360 <= _T_10356 & _T_10358;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10353 <= 1'h0;
|
|
end else begin
|
|
_T_10353 <= _T_10349 & _T_10351;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10346 <= 1'h0;
|
|
end else begin
|
|
_T_10346 <= _T_10342 & _T_10344;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10339 <= 1'h0;
|
|
end else begin
|
|
_T_10339 <= _T_10335 & _T_10337;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10332 <= 1'h0;
|
|
end else begin
|
|
_T_10332 <= _T_10328 & _T_10330;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10325 <= 1'h0;
|
|
end else begin
|
|
_T_10325 <= _T_10321 & _T_10323;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10318 <= 1'h0;
|
|
end else begin
|
|
_T_10318 <= _T_10314 & _T_10316;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10311 <= 1'h0;
|
|
end else begin
|
|
_T_10311 <= _T_10307 & _T_10309;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10304 <= 1'h0;
|
|
end else begin
|
|
_T_10304 <= _T_10300 & _T_10302;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10297 <= 1'h0;
|
|
end else begin
|
|
_T_10297 <= _T_10293 & _T_10295;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10290 <= 1'h0;
|
|
end else begin
|
|
_T_10290 <= _T_10286 & _T_10288;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10283 <= 1'h0;
|
|
end else begin
|
|
_T_10283 <= _T_10279 & _T_10281;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10276 <= 1'h0;
|
|
end else begin
|
|
_T_10276 <= _T_10272 & _T_10274;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10269 <= 1'h0;
|
|
end else begin
|
|
_T_10269 <= _T_10265 & _T_10267;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10262 <= 1'h0;
|
|
end else begin
|
|
_T_10262 <= _T_10258 & _T_10260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10255 <= 1'h0;
|
|
end else begin
|
|
_T_10255 <= _T_10251 & _T_10253;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10248 <= 1'h0;
|
|
end else begin
|
|
_T_10248 <= _T_10244 & _T_10246;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10241 <= 1'h0;
|
|
end else begin
|
|
_T_10241 <= _T_10237 & _T_10239;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10234 <= 1'h0;
|
|
end else begin
|
|
_T_10234 <= _T_10230 & _T_10232;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10227 <= 1'h0;
|
|
end else begin
|
|
_T_10227 <= _T_10223 & _T_10225;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10220 <= 1'h0;
|
|
end else begin
|
|
_T_10220 <= _T_10216 & _T_10218;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10213 <= 1'h0;
|
|
end else begin
|
|
_T_10213 <= _T_10209 & _T_10211;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10206 <= 1'h0;
|
|
end else begin
|
|
_T_10206 <= _T_10202 & _T_10204;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10199 <= 1'h0;
|
|
end else begin
|
|
_T_10199 <= _T_10195 & _T_10197;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10192 <= 1'h0;
|
|
end else begin
|
|
_T_10192 <= _T_10188 & _T_10190;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10185 <= 1'h0;
|
|
end else begin
|
|
_T_10185 <= _T_10181 & _T_10183;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10178 <= 1'h0;
|
|
end else begin
|
|
_T_10178 <= _T_10174 & _T_10176;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10171 <= 1'h0;
|
|
end else begin
|
|
_T_10171 <= _T_10167 & _T_10169;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10164 <= 1'h0;
|
|
end else begin
|
|
_T_10164 <= _T_10160 & _T_10162;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10157 <= 1'h0;
|
|
end else begin
|
|
_T_10157 <= _T_10153 & _T_10155;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10150 <= 1'h0;
|
|
end else begin
|
|
_T_10150 <= _T_10146 & _T_10148;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10143 <= 1'h0;
|
|
end else begin
|
|
_T_10143 <= _T_10139 & _T_10141;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10136 <= 1'h0;
|
|
end else begin
|
|
_T_10136 <= _T_10132 & _T_10134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10129 <= 1'h0;
|
|
end else begin
|
|
_T_10129 <= _T_10125 & _T_10127;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10122 <= 1'h0;
|
|
end else begin
|
|
_T_10122 <= _T_10118 & _T_10120;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10115 <= 1'h0;
|
|
end else begin
|
|
_T_10115 <= _T_10111 & _T_10113;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10108 <= 1'h0;
|
|
end else begin
|
|
_T_10108 <= _T_10104 & _T_10106;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10101 <= 1'h0;
|
|
end else begin
|
|
_T_10101 <= _T_10097 & _T_10099;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10094 <= 1'h0;
|
|
end else begin
|
|
_T_10094 <= _T_10090 & _T_10092;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10087 <= 1'h0;
|
|
end else begin
|
|
_T_10087 <= _T_10083 & _T_10085;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10080 <= 1'h0;
|
|
end else begin
|
|
_T_10080 <= _T_10076 & _T_10078;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10073 <= 1'h0;
|
|
end else begin
|
|
_T_10073 <= _T_10069 & _T_10071;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10066 <= 1'h0;
|
|
end else begin
|
|
_T_10066 <= _T_10062 & _T_10064;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10059 <= 1'h0;
|
|
end else begin
|
|
_T_10059 <= _T_10055 & _T_10057;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10052 <= 1'h0;
|
|
end else begin
|
|
_T_10052 <= _T_10048 & _T_10050;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10045 <= 1'h0;
|
|
end else begin
|
|
_T_10045 <= _T_10041 & _T_10043;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10038 <= 1'h0;
|
|
end else begin
|
|
_T_10038 <= _T_10034 & _T_10036;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10031 <= 1'h0;
|
|
end else begin
|
|
_T_10031 <= _T_10027 & _T_10029;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10024 <= 1'h0;
|
|
end else begin
|
|
_T_10024 <= _T_10020 & _T_10022;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10017 <= 1'h0;
|
|
end else begin
|
|
_T_10017 <= _T_10013 & _T_10015;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10010 <= 1'h0;
|
|
end else begin
|
|
_T_10010 <= _T_10006 & _T_10008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_10003 <= 1'h0;
|
|
end else begin
|
|
_T_10003 <= _T_9999 & _T_10001;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9996 <= 1'h0;
|
|
end else begin
|
|
_T_9996 <= _T_9992 & _T_9994;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9989 <= 1'h0;
|
|
end else begin
|
|
_T_9989 <= _T_9985 & _T_9987;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9982 <= 1'h0;
|
|
end else begin
|
|
_T_9982 <= _T_9978 & _T_9980;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9975 <= 1'h0;
|
|
end else begin
|
|
_T_9975 <= _T_9971 & _T_9973;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9968 <= 1'h0;
|
|
end else begin
|
|
_T_9968 <= _T_9964 & _T_9966;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9961 <= 1'h0;
|
|
end else begin
|
|
_T_9961 <= _T_9957 & _T_9959;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9954 <= 1'h0;
|
|
end else begin
|
|
_T_9954 <= _T_9950 & _T_9952;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9947 <= 1'h0;
|
|
end else begin
|
|
_T_9947 <= _T_9943 & _T_9945;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9940 <= 1'h0;
|
|
end else begin
|
|
_T_9940 <= _T_9936 & _T_9938;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9933 <= 1'h0;
|
|
end else begin
|
|
_T_9933 <= _T_9929 & _T_9931;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9926 <= 1'h0;
|
|
end else begin
|
|
_T_9926 <= _T_9922 & _T_9924;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9919 <= 1'h0;
|
|
end else begin
|
|
_T_9919 <= _T_9915 & _T_9917;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9912 <= 1'h0;
|
|
end else begin
|
|
_T_9912 <= _T_9908 & _T_9910;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9905 <= 1'h0;
|
|
end else begin
|
|
_T_9905 <= _T_9901 & _T_9903;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9898 <= 1'h0;
|
|
end else begin
|
|
_T_9898 <= _T_9894 & _T_9896;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9891 <= 1'h0;
|
|
end else begin
|
|
_T_9891 <= _T_9887 & _T_9889;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9884 <= 1'h0;
|
|
end else begin
|
|
_T_9884 <= _T_9880 & _T_9882;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9877 <= 1'h0;
|
|
end else begin
|
|
_T_9877 <= _T_9873 & _T_9875;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9870 <= 1'h0;
|
|
end else begin
|
|
_T_9870 <= _T_9866 & _T_9868;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9863 <= 1'h0;
|
|
end else begin
|
|
_T_9863 <= _T_9859 & _T_9861;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9856 <= 1'h0;
|
|
end else begin
|
|
_T_9856 <= _T_9852 & _T_9854;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9849 <= 1'h0;
|
|
end else begin
|
|
_T_9849 <= _T_9845 & _T_9847;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9842 <= 1'h0;
|
|
end else begin
|
|
_T_9842 <= _T_9838 & _T_9840;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9835 <= 1'h0;
|
|
end else begin
|
|
_T_9835 <= _T_9831 & _T_9833;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9828 <= 1'h0;
|
|
end else begin
|
|
_T_9828 <= _T_9824 & _T_9826;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_9821 <= 1'h0;
|
|
end else begin
|
|
_T_9821 <= _T_9817 & _T_9819;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
axi_mstr_priority <= 1'h0;
|
|
end else if (_T_17286) begin
|
|
axi_mstr_priority <= axi_mstr_prty_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_addr <= 32'h0;
|
|
end else if (_T_17251) begin
|
|
wrbuf_addr <= io_dma_axi_aw_bits_addr;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_addr <= 32'h0;
|
|
end else if (_T_17264) begin
|
|
rdbuf_addr <= io_dma_axi_ar_bits_addr;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_byteen <= 8'h0;
|
|
end else if (_T_17253) begin
|
|
wrbuf_byteen <= io_dma_axi_w_bits_strb;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_sz <= 3'h0;
|
|
end else if (_T_17249) begin
|
|
wrbuf_sz <= io_dma_axi_aw_bits_size;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_sz <= 3'h0;
|
|
end else if (_T_17262) begin
|
|
rdbuf_sz <= io_dma_axi_ar_bits_size;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dbg_dma_bubble_bus <= 1'h0;
|
|
end else if (io_dma_bus_clk_en) begin
|
|
dbg_dma_bubble_bus <= io_dbg_dma_dbg_dma_bubble;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
WrPtr <= 7'h0;
|
|
end else if (WrPtrEn) begin
|
|
if (_T_16554) begin
|
|
WrPtr <= 7'h0;
|
|
end else begin
|
|
WrPtr <= _T_16556;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
RdPtr <= 7'h0;
|
|
end else if (RdPtrEn) begin
|
|
if (_T_16557) begin
|
|
RdPtr <= 7'h0;
|
|
end else begin
|
|
RdPtr <= _T_16559;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13411 <= 1'h0;
|
|
end else begin
|
|
_T_13411 <= _T_6845 & _T_10442;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13404 <= 1'h0;
|
|
end else begin
|
|
_T_13404 <= _T_6841 & _T_10435;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13397 <= 1'h0;
|
|
end else begin
|
|
_T_13397 <= _T_6837 & _T_10428;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13390 <= 1'h0;
|
|
end else begin
|
|
_T_13390 <= _T_6833 & _T_10421;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13383 <= 1'h0;
|
|
end else begin
|
|
_T_13383 <= _T_6829 & _T_10414;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13376 <= 1'h0;
|
|
end else begin
|
|
_T_13376 <= _T_6825 & _T_10407;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13369 <= 1'h0;
|
|
end else begin
|
|
_T_13369 <= _T_6821 & _T_10400;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13362 <= 1'h0;
|
|
end else begin
|
|
_T_13362 <= _T_6817 & _T_10393;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13355 <= 1'h0;
|
|
end else begin
|
|
_T_13355 <= _T_6813 & _T_10386;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13348 <= 1'h0;
|
|
end else begin
|
|
_T_13348 <= _T_6809 & _T_10379;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13341 <= 1'h0;
|
|
end else begin
|
|
_T_13341 <= _T_6805 & _T_10372;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13334 <= 1'h0;
|
|
end else begin
|
|
_T_13334 <= _T_6801 & _T_10365;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13327 <= 1'h0;
|
|
end else begin
|
|
_T_13327 <= _T_6797 & _T_10358;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13320 <= 1'h0;
|
|
end else begin
|
|
_T_13320 <= _T_6793 & _T_10351;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13313 <= 1'h0;
|
|
end else begin
|
|
_T_13313 <= _T_6789 & _T_10344;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13306 <= 1'h0;
|
|
end else begin
|
|
_T_13306 <= _T_6785 & _T_10337;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13299 <= 1'h0;
|
|
end else begin
|
|
_T_13299 <= _T_6781 & _T_10330;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13292 <= 1'h0;
|
|
end else begin
|
|
_T_13292 <= _T_6777 & _T_10323;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13285 <= 1'h0;
|
|
end else begin
|
|
_T_13285 <= _T_6773 & _T_10316;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13278 <= 1'h0;
|
|
end else begin
|
|
_T_13278 <= _T_6769 & _T_10309;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13271 <= 1'h0;
|
|
end else begin
|
|
_T_13271 <= _T_6765 & _T_10302;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13264 <= 1'h0;
|
|
end else begin
|
|
_T_13264 <= _T_6761 & _T_10295;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13257 <= 1'h0;
|
|
end else begin
|
|
_T_13257 <= _T_6757 & _T_10288;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13250 <= 1'h0;
|
|
end else begin
|
|
_T_13250 <= _T_6753 & _T_10281;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13243 <= 1'h0;
|
|
end else begin
|
|
_T_13243 <= _T_6749 & _T_10274;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13236 <= 1'h0;
|
|
end else begin
|
|
_T_13236 <= _T_6745 & _T_10267;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13229 <= 1'h0;
|
|
end else begin
|
|
_T_13229 <= _T_6741 & _T_10260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13222 <= 1'h0;
|
|
end else begin
|
|
_T_13222 <= _T_6737 & _T_10253;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13215 <= 1'h0;
|
|
end else begin
|
|
_T_13215 <= _T_6733 & _T_10246;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13208 <= 1'h0;
|
|
end else begin
|
|
_T_13208 <= _T_6729 & _T_10239;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13201 <= 1'h0;
|
|
end else begin
|
|
_T_13201 <= _T_6725 & _T_10232;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13194 <= 1'h0;
|
|
end else begin
|
|
_T_13194 <= _T_6721 & _T_10225;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13187 <= 1'h0;
|
|
end else begin
|
|
_T_13187 <= _T_6717 & _T_10218;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13180 <= 1'h0;
|
|
end else begin
|
|
_T_13180 <= _T_6713 & _T_10211;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13173 <= 1'h0;
|
|
end else begin
|
|
_T_13173 <= _T_6709 & _T_10204;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13166 <= 1'h0;
|
|
end else begin
|
|
_T_13166 <= _T_6705 & _T_10197;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13159 <= 1'h0;
|
|
end else begin
|
|
_T_13159 <= _T_6701 & _T_10190;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13152 <= 1'h0;
|
|
end else begin
|
|
_T_13152 <= _T_6697 & _T_10183;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13145 <= 1'h0;
|
|
end else begin
|
|
_T_13145 <= _T_6693 & _T_10176;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13138 <= 1'h0;
|
|
end else begin
|
|
_T_13138 <= _T_6689 & _T_10169;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13131 <= 1'h0;
|
|
end else begin
|
|
_T_13131 <= _T_6685 & _T_10162;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13124 <= 1'h0;
|
|
end else begin
|
|
_T_13124 <= _T_6681 & _T_10155;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13117 <= 1'h0;
|
|
end else begin
|
|
_T_13117 <= _T_6677 & _T_10148;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13110 <= 1'h0;
|
|
end else begin
|
|
_T_13110 <= _T_6673 & _T_10141;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13103 <= 1'h0;
|
|
end else begin
|
|
_T_13103 <= _T_6669 & _T_10134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13096 <= 1'h0;
|
|
end else begin
|
|
_T_13096 <= _T_6665 & _T_10127;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13089 <= 1'h0;
|
|
end else begin
|
|
_T_13089 <= _T_6661 & _T_10120;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13082 <= 1'h0;
|
|
end else begin
|
|
_T_13082 <= _T_6657 & _T_10113;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13075 <= 1'h0;
|
|
end else begin
|
|
_T_13075 <= _T_6653 & _T_10106;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13068 <= 1'h0;
|
|
end else begin
|
|
_T_13068 <= _T_6649 & _T_10099;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13061 <= 1'h0;
|
|
end else begin
|
|
_T_13061 <= _T_6645 & _T_10092;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13054 <= 1'h0;
|
|
end else begin
|
|
_T_13054 <= _T_6641 & _T_10085;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13047 <= 1'h0;
|
|
end else begin
|
|
_T_13047 <= _T_6637 & _T_10078;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13040 <= 1'h0;
|
|
end else begin
|
|
_T_13040 <= _T_6633 & _T_10071;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13033 <= 1'h0;
|
|
end else begin
|
|
_T_13033 <= _T_6629 & _T_10064;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13026 <= 1'h0;
|
|
end else begin
|
|
_T_13026 <= _T_6625 & _T_10057;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13019 <= 1'h0;
|
|
end else begin
|
|
_T_13019 <= _T_6621 & _T_10050;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13012 <= 1'h0;
|
|
end else begin
|
|
_T_13012 <= _T_6617 & _T_10043;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13005 <= 1'h0;
|
|
end else begin
|
|
_T_13005 <= _T_6613 & _T_10036;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12998 <= 1'h0;
|
|
end else begin
|
|
_T_12998 <= _T_6609 & _T_10029;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12991 <= 1'h0;
|
|
end else begin
|
|
_T_12991 <= _T_6605 & _T_10022;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12984 <= 1'h0;
|
|
end else begin
|
|
_T_12984 <= _T_6601 & _T_10015;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12977 <= 1'h0;
|
|
end else begin
|
|
_T_12977 <= _T_6597 & _T_10008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12970 <= 1'h0;
|
|
end else begin
|
|
_T_12970 <= _T_6593 & _T_10001;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12963 <= 1'h0;
|
|
end else begin
|
|
_T_12963 <= _T_6589 & _T_9994;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12956 <= 1'h0;
|
|
end else begin
|
|
_T_12956 <= _T_6585 & _T_9987;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12949 <= 1'h0;
|
|
end else begin
|
|
_T_12949 <= _T_6581 & _T_9980;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12942 <= 1'h0;
|
|
end else begin
|
|
_T_12942 <= _T_6577 & _T_9973;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12935 <= 1'h0;
|
|
end else begin
|
|
_T_12935 <= _T_6573 & _T_9966;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12928 <= 1'h0;
|
|
end else begin
|
|
_T_12928 <= _T_6569 & _T_9959;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12921 <= 1'h0;
|
|
end else begin
|
|
_T_12921 <= _T_6565 & _T_9952;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12914 <= 1'h0;
|
|
end else begin
|
|
_T_12914 <= _T_6561 & _T_9945;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12907 <= 1'h0;
|
|
end else begin
|
|
_T_12907 <= _T_6557 & _T_9938;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12900 <= 1'h0;
|
|
end else begin
|
|
_T_12900 <= _T_6553 & _T_9931;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12893 <= 1'h0;
|
|
end else begin
|
|
_T_12893 <= _T_6549 & _T_9924;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12886 <= 1'h0;
|
|
end else begin
|
|
_T_12886 <= _T_6545 & _T_9917;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12879 <= 1'h0;
|
|
end else begin
|
|
_T_12879 <= _T_6541 & _T_9910;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12872 <= 1'h0;
|
|
end else begin
|
|
_T_12872 <= _T_6537 & _T_9903;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12865 <= 1'h0;
|
|
end else begin
|
|
_T_12865 <= _T_6533 & _T_9896;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12858 <= 1'h0;
|
|
end else begin
|
|
_T_12858 <= _T_6529 & _T_9889;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12851 <= 1'h0;
|
|
end else begin
|
|
_T_12851 <= _T_6525 & _T_9882;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12844 <= 1'h0;
|
|
end else begin
|
|
_T_12844 <= _T_6521 & _T_9875;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12837 <= 1'h0;
|
|
end else begin
|
|
_T_12837 <= _T_6517 & _T_9868;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12830 <= 1'h0;
|
|
end else begin
|
|
_T_12830 <= _T_6513 & _T_9861;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12823 <= 1'h0;
|
|
end else begin
|
|
_T_12823 <= _T_6509 & _T_9854;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12816 <= 1'h0;
|
|
end else begin
|
|
_T_12816 <= _T_6505 & _T_9847;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12809 <= 1'h0;
|
|
end else begin
|
|
_T_12809 <= _T_6501 & _T_9840;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12802 <= 1'h0;
|
|
end else begin
|
|
_T_12802 <= _T_6497 & _T_9833;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12795 <= 1'h0;
|
|
end else begin
|
|
_T_12795 <= _T_6493 & _T_9826;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12788 <= 1'h0;
|
|
end else begin
|
|
_T_12788 <= _T_6489 & _T_9819;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15745 <= 1'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
_T_15745 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15743 <= 1'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
_T_15743 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15741 <= 1'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
_T_15741 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15739 <= 1'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
_T_15739 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15737 <= 1'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
_T_15737 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15735 <= 1'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
_T_15735 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15733 <= 1'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
_T_15733 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15731 <= 1'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
_T_15731 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15729 <= 1'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
_T_15729 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15727 <= 1'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
_T_15727 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15725 <= 1'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
_T_15725 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15723 <= 1'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
_T_15723 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15721 <= 1'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
_T_15721 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15719 <= 1'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
_T_15719 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15717 <= 1'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
_T_15717 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15715 <= 1'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
_T_15715 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15713 <= 1'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
_T_15713 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15711 <= 1'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
_T_15711 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15709 <= 1'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
_T_15709 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15707 <= 1'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
_T_15707 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15705 <= 1'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
_T_15705 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15703 <= 1'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
_T_15703 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15701 <= 1'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
_T_15701 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15699 <= 1'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
_T_15699 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15697 <= 1'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
_T_15697 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15695 <= 1'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
_T_15695 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15693 <= 1'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
_T_15693 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15691 <= 1'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
_T_15691 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15689 <= 1'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
_T_15689 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15687 <= 1'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
_T_15687 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15685 <= 1'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
_T_15685 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15683 <= 1'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
_T_15683 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15681 <= 1'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
_T_15681 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15679 <= 1'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
_T_15679 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15677 <= 1'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
_T_15677 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15675 <= 1'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
_T_15675 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15673 <= 1'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
_T_15673 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15671 <= 1'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
_T_15671 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15669 <= 1'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
_T_15669 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15667 <= 1'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
_T_15667 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15665 <= 1'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
_T_15665 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15663 <= 1'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
_T_15663 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15661 <= 1'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
_T_15661 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15659 <= 1'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
_T_15659 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15657 <= 1'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
_T_15657 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15655 <= 1'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
_T_15655 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15653 <= 1'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
_T_15653 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15651 <= 1'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
_T_15651 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15649 <= 1'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
_T_15649 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15647 <= 1'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
_T_15647 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15645 <= 1'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
_T_15645 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15643 <= 1'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
_T_15643 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15641 <= 1'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
_T_15641 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15639 <= 1'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
_T_15639 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15637 <= 1'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
_T_15637 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15635 <= 1'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
_T_15635 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15633 <= 1'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
_T_15633 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15631 <= 1'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
_T_15631 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15629 <= 1'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
_T_15629 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15627 <= 1'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
_T_15627 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15625 <= 1'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
_T_15625 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15623 <= 1'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
_T_15623 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15621 <= 1'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
_T_15621 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15619 <= 1'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
_T_15619 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15617 <= 1'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
_T_15617 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15615 <= 1'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
_T_15615 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15613 <= 1'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
_T_15613 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15611 <= 1'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
_T_15611 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15609 <= 1'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
_T_15609 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15607 <= 1'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
_T_15607 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15605 <= 1'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
_T_15605 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15603 <= 1'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
_T_15603 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15601 <= 1'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
_T_15601 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15599 <= 1'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
_T_15599 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15597 <= 1'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
_T_15597 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15595 <= 1'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
_T_15595 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15593 <= 1'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
_T_15593 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15591 <= 1'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
_T_15591 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15589 <= 1'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
_T_15589 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15587 <= 1'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
_T_15587 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15585 <= 1'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
_T_15585 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15583 <= 1'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
_T_15583 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15581 <= 1'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
_T_15581 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15579 <= 1'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
_T_15579 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15577 <= 1'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
_T_15577 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15575 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
_T_15575 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15573 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
_T_15573 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15571 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
_T_15571 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15569 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
_T_15569 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15567 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
_T_15567 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_valid;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_89 <= 32'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_addr_89 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_89 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_89 <= rdbuf_addr;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_88 <= 32'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_addr_88 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_88 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_88 <= rdbuf_addr;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_87 <= 32'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_addr_87 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_87 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_87 <= rdbuf_addr;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_86 <= 32'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_addr_86 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_addr;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_addr_86 <= wrbuf_addr;
|
|
end else begin
|
|
fifo_addr_86 <= rdbuf_addr;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_85 <= 32'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
fifo_addr_85 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_84 <= 32'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
fifo_addr_84 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_83 <= 32'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
fifo_addr_83 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_82 <= 32'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
fifo_addr_82 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_81 <= 32'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
fifo_addr_81 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_80 <= 32'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
fifo_addr_80 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_79 <= 32'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
fifo_addr_79 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_78 <= 32'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
fifo_addr_78 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_77 <= 32'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
fifo_addr_77 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_76 <= 32'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
fifo_addr_76 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_75 <= 32'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
fifo_addr_75 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_74 <= 32'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
fifo_addr_74 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_73 <= 32'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
fifo_addr_73 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_72 <= 32'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
fifo_addr_72 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_71 <= 32'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
fifo_addr_71 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_70 <= 32'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
fifo_addr_70 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_69 <= 32'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
fifo_addr_69 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_68 <= 32'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
fifo_addr_68 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_67 <= 32'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
fifo_addr_67 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_66 <= 32'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
fifo_addr_66 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_65 <= 32'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
fifo_addr_65 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_64 <= 32'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
fifo_addr_64 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_63 <= 32'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
fifo_addr_63 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_62 <= 32'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
fifo_addr_62 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_61 <= 32'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
fifo_addr_61 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_60 <= 32'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
fifo_addr_60 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_59 <= 32'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
fifo_addr_59 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_58 <= 32'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
fifo_addr_58 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_57 <= 32'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
fifo_addr_57 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_56 <= 32'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
fifo_addr_56 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_55 <= 32'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
fifo_addr_55 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_54 <= 32'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
fifo_addr_54 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_53 <= 32'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
fifo_addr_53 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_52 <= 32'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
fifo_addr_52 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_51 <= 32'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
fifo_addr_51 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_50 <= 32'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
fifo_addr_50 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_49 <= 32'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
fifo_addr_49 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_48 <= 32'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
fifo_addr_48 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_47 <= 32'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
fifo_addr_47 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_46 <= 32'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
fifo_addr_46 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_45 <= 32'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
fifo_addr_45 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_44 <= 32'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
fifo_addr_44 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_43 <= 32'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
fifo_addr_43 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_42 <= 32'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
fifo_addr_42 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_41 <= 32'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
fifo_addr_41 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_40 <= 32'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
fifo_addr_40 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_39 <= 32'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
fifo_addr_39 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_38 <= 32'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
fifo_addr_38 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_37 <= 32'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
fifo_addr_37 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_36 <= 32'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
fifo_addr_36 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_35 <= 32'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
fifo_addr_35 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_34 <= 32'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
fifo_addr_34 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_33 <= 32'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
fifo_addr_33 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_32 <= 32'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
fifo_addr_32 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_31 <= 32'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
fifo_addr_31 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_30 <= 32'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
fifo_addr_30 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_29 <= 32'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
fifo_addr_29 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_28 <= 32'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
fifo_addr_28 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_27 <= 32'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
fifo_addr_27 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_26 <= 32'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
fifo_addr_26 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_25 <= 32'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
fifo_addr_25 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_24 <= 32'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
fifo_addr_24 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_23 <= 32'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
fifo_addr_23 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_22 <= 32'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
fifo_addr_22 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_21 <= 32'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
fifo_addr_21 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_20 <= 32'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
fifo_addr_20 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_19 <= 32'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
fifo_addr_19 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_18 <= 32'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
fifo_addr_18 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_17 <= 32'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
fifo_addr_17 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_16 <= 32'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
fifo_addr_16 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_15 <= 32'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
fifo_addr_15 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_14 <= 32'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
fifo_addr_14 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_13 <= 32'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
fifo_addr_13 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_12 <= 32'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
fifo_addr_12 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_11 <= 32'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
fifo_addr_11 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_10 <= 32'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
fifo_addr_10 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_9 <= 32'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
fifo_addr_9 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_8 <= 32'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
fifo_addr_8 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_7 <= 32'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
fifo_addr_7 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_6 <= 32'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
fifo_addr_6 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_5 <= 32'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
fifo_addr_5 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_4 <= 32'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_addr_4 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_3 <= 32'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
fifo_addr_3 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_2 <= 32'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
fifo_addr_2 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_1 <= 32'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
fifo_addr_1 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_addr_0 <= 32'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
fifo_addr_0 <= fifo_addr_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_89 <= 3'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_sz_89 <= _T_11;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_89 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_89 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_88 <= 3'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_sz_88 <= _T_11;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_88 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_88 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_87 <= 3'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_sz_87 <= _T_11;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_87 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_87 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_86 <= 3'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_sz_86 <= _T_11;
|
|
end else if (axi_mstr_sel) begin
|
|
fifo_sz_86 <= wrbuf_sz;
|
|
end else begin
|
|
fifo_sz_86 <= rdbuf_sz;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_85 <= 3'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
fifo_sz_85 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_84 <= 3'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
fifo_sz_84 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_83 <= 3'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
fifo_sz_83 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_82 <= 3'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
fifo_sz_82 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_81 <= 3'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
fifo_sz_81 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_80 <= 3'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
fifo_sz_80 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_79 <= 3'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
fifo_sz_79 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_78 <= 3'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
fifo_sz_78 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_77 <= 3'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
fifo_sz_77 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_76 <= 3'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
fifo_sz_76 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_75 <= 3'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
fifo_sz_75 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_74 <= 3'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
fifo_sz_74 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_73 <= 3'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
fifo_sz_73 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_72 <= 3'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
fifo_sz_72 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_71 <= 3'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
fifo_sz_71 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_70 <= 3'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
fifo_sz_70 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_69 <= 3'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
fifo_sz_69 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_68 <= 3'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
fifo_sz_68 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_67 <= 3'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
fifo_sz_67 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_66 <= 3'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
fifo_sz_66 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_65 <= 3'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
fifo_sz_65 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_64 <= 3'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
fifo_sz_64 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_63 <= 3'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
fifo_sz_63 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_62 <= 3'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
fifo_sz_62 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_61 <= 3'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
fifo_sz_61 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_60 <= 3'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
fifo_sz_60 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_59 <= 3'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
fifo_sz_59 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_58 <= 3'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
fifo_sz_58 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_57 <= 3'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
fifo_sz_57 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_56 <= 3'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
fifo_sz_56 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_55 <= 3'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
fifo_sz_55 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_54 <= 3'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
fifo_sz_54 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_53 <= 3'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
fifo_sz_53 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_52 <= 3'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
fifo_sz_52 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_51 <= 3'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
fifo_sz_51 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_50 <= 3'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
fifo_sz_50 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_49 <= 3'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
fifo_sz_49 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_48 <= 3'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
fifo_sz_48 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_47 <= 3'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
fifo_sz_47 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_46 <= 3'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
fifo_sz_46 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_45 <= 3'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
fifo_sz_45 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_44 <= 3'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
fifo_sz_44 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_43 <= 3'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
fifo_sz_43 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_42 <= 3'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
fifo_sz_42 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_41 <= 3'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
fifo_sz_41 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_40 <= 3'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
fifo_sz_40 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_39 <= 3'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
fifo_sz_39 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_38 <= 3'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
fifo_sz_38 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_37 <= 3'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
fifo_sz_37 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_36 <= 3'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
fifo_sz_36 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_35 <= 3'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
fifo_sz_35 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_34 <= 3'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
fifo_sz_34 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_33 <= 3'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
fifo_sz_33 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_32 <= 3'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
fifo_sz_32 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_31 <= 3'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
fifo_sz_31 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_30 <= 3'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
fifo_sz_30 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_29 <= 3'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
fifo_sz_29 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_28 <= 3'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
fifo_sz_28 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_27 <= 3'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
fifo_sz_27 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_26 <= 3'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
fifo_sz_26 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_25 <= 3'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
fifo_sz_25 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_24 <= 3'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
fifo_sz_24 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_23 <= 3'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
fifo_sz_23 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_22 <= 3'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
fifo_sz_22 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_21 <= 3'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
fifo_sz_21 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_20 <= 3'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
fifo_sz_20 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_19 <= 3'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
fifo_sz_19 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_18 <= 3'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
fifo_sz_18 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_17 <= 3'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
fifo_sz_17 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_16 <= 3'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
fifo_sz_16 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_15 <= 3'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
fifo_sz_15 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_14 <= 3'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
fifo_sz_14 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_13 <= 3'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
fifo_sz_13 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_12 <= 3'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
fifo_sz_12 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_11 <= 3'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
fifo_sz_11 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_10 <= 3'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
fifo_sz_10 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_9 <= 3'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
fifo_sz_9 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_8 <= 3'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
fifo_sz_8 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_7 <= 3'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
fifo_sz_7 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_6 <= 3'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
fifo_sz_6 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_5 <= 3'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
fifo_sz_5 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_4 <= 3'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_sz_4 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_3 <= 3'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
fifo_sz_3 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_2 <= 3'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
fifo_sz_2 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_1 <= 3'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
fifo_sz_1 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_sz_0 <= 3'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
fifo_sz_0 <= fifo_sz_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_89 <= 8'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
fifo_byteen_89 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_88 <= 8'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
fifo_byteen_88 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_87 <= 8'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
fifo_byteen_87 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_86 <= 8'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
fifo_byteen_86 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_85 <= 8'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
fifo_byteen_85 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_84 <= 8'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
fifo_byteen_84 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_83 <= 8'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
fifo_byteen_83 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_82 <= 8'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
fifo_byteen_82 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_81 <= 8'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
fifo_byteen_81 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_80 <= 8'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
fifo_byteen_80 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_79 <= 8'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
fifo_byteen_79 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_78 <= 8'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
fifo_byteen_78 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_77 <= 8'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
fifo_byteen_77 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_76 <= 8'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
fifo_byteen_76 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_75 <= 8'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
fifo_byteen_75 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_74 <= 8'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
fifo_byteen_74 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_73 <= 8'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
fifo_byteen_73 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_72 <= 8'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
fifo_byteen_72 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_71 <= 8'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
fifo_byteen_71 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_70 <= 8'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
fifo_byteen_70 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_69 <= 8'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
fifo_byteen_69 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_68 <= 8'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
fifo_byteen_68 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_67 <= 8'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
fifo_byteen_67 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_66 <= 8'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
fifo_byteen_66 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_65 <= 8'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
fifo_byteen_65 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_64 <= 8'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
fifo_byteen_64 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_63 <= 8'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
fifo_byteen_63 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_62 <= 8'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
fifo_byteen_62 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_61 <= 8'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
fifo_byteen_61 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_60 <= 8'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
fifo_byteen_60 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_59 <= 8'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
fifo_byteen_59 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_58 <= 8'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
fifo_byteen_58 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_57 <= 8'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
fifo_byteen_57 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_56 <= 8'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
fifo_byteen_56 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_55 <= 8'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
fifo_byteen_55 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_54 <= 8'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
fifo_byteen_54 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_53 <= 8'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
fifo_byteen_53 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_52 <= 8'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
fifo_byteen_52 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_51 <= 8'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
fifo_byteen_51 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_50 <= 8'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
fifo_byteen_50 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_49 <= 8'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
fifo_byteen_49 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_48 <= 8'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
fifo_byteen_48 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_47 <= 8'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
fifo_byteen_47 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_46 <= 8'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
fifo_byteen_46 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_45 <= 8'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
fifo_byteen_45 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_44 <= 8'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
fifo_byteen_44 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_43 <= 8'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
fifo_byteen_43 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_42 <= 8'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
fifo_byteen_42 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_41 <= 8'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
fifo_byteen_41 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_40 <= 8'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
fifo_byteen_40 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_39 <= 8'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
fifo_byteen_39 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_38 <= 8'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
fifo_byteen_38 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_37 <= 8'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
fifo_byteen_37 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_36 <= 8'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
fifo_byteen_36 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_35 <= 8'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
fifo_byteen_35 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_34 <= 8'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
fifo_byteen_34 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_33 <= 8'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
fifo_byteen_33 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_32 <= 8'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
fifo_byteen_32 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_31 <= 8'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
fifo_byteen_31 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_30 <= 8'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
fifo_byteen_30 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_29 <= 8'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
fifo_byteen_29 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_28 <= 8'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
fifo_byteen_28 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_27 <= 8'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
fifo_byteen_27 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_26 <= 8'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
fifo_byteen_26 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_25 <= 8'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
fifo_byteen_25 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_24 <= 8'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
fifo_byteen_24 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_23 <= 8'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
fifo_byteen_23 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_22 <= 8'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
fifo_byteen_22 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_21 <= 8'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
fifo_byteen_21 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_20 <= 8'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
fifo_byteen_20 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_19 <= 8'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
fifo_byteen_19 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_18 <= 8'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
fifo_byteen_18 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_17 <= 8'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
fifo_byteen_17 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_16 <= 8'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
fifo_byteen_16 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_15 <= 8'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
fifo_byteen_15 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_14 <= 8'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
fifo_byteen_14 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_13 <= 8'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
fifo_byteen_13 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_12 <= 8'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
fifo_byteen_12 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_11 <= 8'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
fifo_byteen_11 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_10 <= 8'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
fifo_byteen_10 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_9 <= 8'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
fifo_byteen_9 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_8 <= 8'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
fifo_byteen_8 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_7 <= 8'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
fifo_byteen_7 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_6 <= 8'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
fifo_byteen_6 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_5 <= 8'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
fifo_byteen_5 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_4 <= 8'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_byteen_4 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_3 <= 8'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
fifo_byteen_3 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_2 <= 8'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
fifo_byteen_2 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_1 <= 8'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
fifo_byteen_1 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_byteen_0 <= 8'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
fifo_byteen_0 <= fifo_byteen_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_0 <= 2'h0;
|
|
end else begin
|
|
fifo_error_0 <= _T_10536 & _T_10540;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_1 <= 2'h0;
|
|
end else begin
|
|
fifo_error_1 <= _T_10545 & _T_10549;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_2 <= 2'h0;
|
|
end else begin
|
|
fifo_error_2 <= _T_10554 & _T_10558;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_3 <= 2'h0;
|
|
end else begin
|
|
fifo_error_3 <= _T_10563 & _T_10567;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_4 <= 2'h0;
|
|
end else begin
|
|
fifo_error_4 <= _T_10572 & _T_10576;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_5 <= 2'h0;
|
|
end else begin
|
|
fifo_error_5 <= _T_10581 & _T_10585;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_6 <= 2'h0;
|
|
end else begin
|
|
fifo_error_6 <= _T_10590 & _T_10594;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_7 <= 2'h0;
|
|
end else begin
|
|
fifo_error_7 <= _T_10599 & _T_10603;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_8 <= 2'h0;
|
|
end else begin
|
|
fifo_error_8 <= _T_10608 & _T_10612;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_9 <= 2'h0;
|
|
end else begin
|
|
fifo_error_9 <= _T_10617 & _T_10621;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_10 <= 2'h0;
|
|
end else begin
|
|
fifo_error_10 <= _T_10626 & _T_10630;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_11 <= 2'h0;
|
|
end else begin
|
|
fifo_error_11 <= _T_10635 & _T_10639;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_12 <= 2'h0;
|
|
end else begin
|
|
fifo_error_12 <= _T_10644 & _T_10648;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_13 <= 2'h0;
|
|
end else begin
|
|
fifo_error_13 <= _T_10653 & _T_10657;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_14 <= 2'h0;
|
|
end else begin
|
|
fifo_error_14 <= _T_10662 & _T_10666;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_15 <= 2'h0;
|
|
end else begin
|
|
fifo_error_15 <= _T_10671 & _T_10675;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_16 <= 2'h0;
|
|
end else begin
|
|
fifo_error_16 <= _T_10680 & _T_10684;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_17 <= 2'h0;
|
|
end else begin
|
|
fifo_error_17 <= _T_10689 & _T_10693;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_18 <= 2'h0;
|
|
end else begin
|
|
fifo_error_18 <= _T_10698 & _T_10702;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_19 <= 2'h0;
|
|
end else begin
|
|
fifo_error_19 <= _T_10707 & _T_10711;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_20 <= 2'h0;
|
|
end else begin
|
|
fifo_error_20 <= _T_10716 & _T_10720;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_21 <= 2'h0;
|
|
end else begin
|
|
fifo_error_21 <= _T_10725 & _T_10729;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_22 <= 2'h0;
|
|
end else begin
|
|
fifo_error_22 <= _T_10734 & _T_10738;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_23 <= 2'h0;
|
|
end else begin
|
|
fifo_error_23 <= _T_10743 & _T_10747;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_24 <= 2'h0;
|
|
end else begin
|
|
fifo_error_24 <= _T_10752 & _T_10756;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_25 <= 2'h0;
|
|
end else begin
|
|
fifo_error_25 <= _T_10761 & _T_10765;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_26 <= 2'h0;
|
|
end else begin
|
|
fifo_error_26 <= _T_10770 & _T_10774;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_27 <= 2'h0;
|
|
end else begin
|
|
fifo_error_27 <= _T_10779 & _T_10783;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_28 <= 2'h0;
|
|
end else begin
|
|
fifo_error_28 <= _T_10788 & _T_10792;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_29 <= 2'h0;
|
|
end else begin
|
|
fifo_error_29 <= _T_10797 & _T_10801;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_30 <= 2'h0;
|
|
end else begin
|
|
fifo_error_30 <= _T_10806 & _T_10810;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_31 <= 2'h0;
|
|
end else begin
|
|
fifo_error_31 <= _T_10815 & _T_10819;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_32 <= 2'h0;
|
|
end else begin
|
|
fifo_error_32 <= _T_10824 & _T_10828;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_33 <= 2'h0;
|
|
end else begin
|
|
fifo_error_33 <= _T_10833 & _T_10837;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_34 <= 2'h0;
|
|
end else begin
|
|
fifo_error_34 <= _T_10842 & _T_10846;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_35 <= 2'h0;
|
|
end else begin
|
|
fifo_error_35 <= _T_10851 & _T_10855;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_36 <= 2'h0;
|
|
end else begin
|
|
fifo_error_36 <= _T_10860 & _T_10864;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_37 <= 2'h0;
|
|
end else begin
|
|
fifo_error_37 <= _T_10869 & _T_10873;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_38 <= 2'h0;
|
|
end else begin
|
|
fifo_error_38 <= _T_10878 & _T_10882;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_39 <= 2'h0;
|
|
end else begin
|
|
fifo_error_39 <= _T_10887 & _T_10891;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_40 <= 2'h0;
|
|
end else begin
|
|
fifo_error_40 <= _T_10896 & _T_10900;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_41 <= 2'h0;
|
|
end else begin
|
|
fifo_error_41 <= _T_10905 & _T_10909;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_42 <= 2'h0;
|
|
end else begin
|
|
fifo_error_42 <= _T_10914 & _T_10918;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_43 <= 2'h0;
|
|
end else begin
|
|
fifo_error_43 <= _T_10923 & _T_10927;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_44 <= 2'h0;
|
|
end else begin
|
|
fifo_error_44 <= _T_10932 & _T_10936;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_45 <= 2'h0;
|
|
end else begin
|
|
fifo_error_45 <= _T_10941 & _T_10945;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_46 <= 2'h0;
|
|
end else begin
|
|
fifo_error_46 <= _T_10950 & _T_10954;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_47 <= 2'h0;
|
|
end else begin
|
|
fifo_error_47 <= _T_10959 & _T_10963;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_48 <= 2'h0;
|
|
end else begin
|
|
fifo_error_48 <= _T_10968 & _T_10972;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_49 <= 2'h0;
|
|
end else begin
|
|
fifo_error_49 <= _T_10977 & _T_10981;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_50 <= 2'h0;
|
|
end else begin
|
|
fifo_error_50 <= _T_10986 & _T_10990;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_51 <= 2'h0;
|
|
end else begin
|
|
fifo_error_51 <= _T_10995 & _T_10999;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_52 <= 2'h0;
|
|
end else begin
|
|
fifo_error_52 <= _T_11004 & _T_11008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_53 <= 2'h0;
|
|
end else begin
|
|
fifo_error_53 <= _T_11013 & _T_11017;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_54 <= 2'h0;
|
|
end else begin
|
|
fifo_error_54 <= _T_11022 & _T_11026;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_55 <= 2'h0;
|
|
end else begin
|
|
fifo_error_55 <= _T_11031 & _T_11035;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_56 <= 2'h0;
|
|
end else begin
|
|
fifo_error_56 <= _T_11040 & _T_11044;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_57 <= 2'h0;
|
|
end else begin
|
|
fifo_error_57 <= _T_11049 & _T_11053;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_58 <= 2'h0;
|
|
end else begin
|
|
fifo_error_58 <= _T_11058 & _T_11062;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_59 <= 2'h0;
|
|
end else begin
|
|
fifo_error_59 <= _T_11067 & _T_11071;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_60 <= 2'h0;
|
|
end else begin
|
|
fifo_error_60 <= _T_11076 & _T_11080;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_61 <= 2'h0;
|
|
end else begin
|
|
fifo_error_61 <= _T_11085 & _T_11089;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_62 <= 2'h0;
|
|
end else begin
|
|
fifo_error_62 <= _T_11094 & _T_11098;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_63 <= 2'h0;
|
|
end else begin
|
|
fifo_error_63 <= _T_11103 & _T_11107;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_64 <= 2'h0;
|
|
end else begin
|
|
fifo_error_64 <= _T_11112 & _T_11116;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_65 <= 2'h0;
|
|
end else begin
|
|
fifo_error_65 <= _T_11121 & _T_11125;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_66 <= 2'h0;
|
|
end else begin
|
|
fifo_error_66 <= _T_11130 & _T_11134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_67 <= 2'h0;
|
|
end else begin
|
|
fifo_error_67 <= _T_11139 & _T_11143;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_68 <= 2'h0;
|
|
end else begin
|
|
fifo_error_68 <= _T_11148 & _T_11152;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_69 <= 2'h0;
|
|
end else begin
|
|
fifo_error_69 <= _T_11157 & _T_11161;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_70 <= 2'h0;
|
|
end else begin
|
|
fifo_error_70 <= _T_11166 & _T_11170;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_71 <= 2'h0;
|
|
end else begin
|
|
fifo_error_71 <= _T_11175 & _T_11179;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_72 <= 2'h0;
|
|
end else begin
|
|
fifo_error_72 <= _T_11184 & _T_11188;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_73 <= 2'h0;
|
|
end else begin
|
|
fifo_error_73 <= _T_11193 & _T_11197;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_74 <= 2'h0;
|
|
end else begin
|
|
fifo_error_74 <= _T_11202 & _T_11206;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_75 <= 2'h0;
|
|
end else begin
|
|
fifo_error_75 <= _T_11211 & _T_11215;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_76 <= 2'h0;
|
|
end else begin
|
|
fifo_error_76 <= _T_11220 & _T_11224;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_77 <= 2'h0;
|
|
end else begin
|
|
fifo_error_77 <= _T_11229 & _T_11233;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_78 <= 2'h0;
|
|
end else begin
|
|
fifo_error_78 <= _T_11238 & _T_11242;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_79 <= 2'h0;
|
|
end else begin
|
|
fifo_error_79 <= _T_11247 & _T_11251;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_80 <= 2'h0;
|
|
end else begin
|
|
fifo_error_80 <= _T_11256 & _T_11260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_81 <= 2'h0;
|
|
end else begin
|
|
fifo_error_81 <= _T_11265 & _T_11269;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_82 <= 2'h0;
|
|
end else begin
|
|
fifo_error_82 <= _T_11274 & _T_11278;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_83 <= 2'h0;
|
|
end else begin
|
|
fifo_error_83 <= _T_11283 & _T_11287;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_84 <= 2'h0;
|
|
end else begin
|
|
fifo_error_84 <= _T_11292 & _T_11296;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_85 <= 2'h0;
|
|
end else begin
|
|
fifo_error_85 <= _T_11301 & _T_11305;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_86 <= 2'h0;
|
|
end else begin
|
|
fifo_error_86 <= _T_11310 & _T_11314;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_87 <= 2'h0;
|
|
end else begin
|
|
fifo_error_87 <= _T_11319 & _T_11323;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_88 <= 2'h0;
|
|
end else begin
|
|
fifo_error_88 <= _T_11328 & _T_11332;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_error_89 <= 2'h0;
|
|
end else begin
|
|
fifo_error_89 <= _T_11337 & _T_11341;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
RspPtr <= 7'h0;
|
|
end else if (RspPtrEn) begin
|
|
if (_T_16560) begin
|
|
RspPtr <= 7'h0;
|
|
end else begin
|
|
RspPtr <= _T_16562;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_data <= 64'h0;
|
|
end else if (_T_17252) begin
|
|
wrbuf_data <= io_dma_axi_w_bits_data;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12692 <= 1'h0;
|
|
end else begin
|
|
_T_12692 <= _T_12688 & _T_10442;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12685 <= 1'h0;
|
|
end else begin
|
|
_T_12685 <= _T_12681 & _T_10435;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12678 <= 1'h0;
|
|
end else begin
|
|
_T_12678 <= _T_12674 & _T_10428;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12671 <= 1'h0;
|
|
end else begin
|
|
_T_12671 <= _T_12667 & _T_10421;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12664 <= 1'h0;
|
|
end else begin
|
|
_T_12664 <= _T_12660 & _T_10414;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12657 <= 1'h0;
|
|
end else begin
|
|
_T_12657 <= _T_12653 & _T_10407;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12650 <= 1'h0;
|
|
end else begin
|
|
_T_12650 <= _T_12646 & _T_10400;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12643 <= 1'h0;
|
|
end else begin
|
|
_T_12643 <= _T_12639 & _T_10393;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12636 <= 1'h0;
|
|
end else begin
|
|
_T_12636 <= _T_12632 & _T_10386;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12629 <= 1'h0;
|
|
end else begin
|
|
_T_12629 <= _T_12625 & _T_10379;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12622 <= 1'h0;
|
|
end else begin
|
|
_T_12622 <= _T_12618 & _T_10372;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12615 <= 1'h0;
|
|
end else begin
|
|
_T_12615 <= _T_12611 & _T_10365;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12608 <= 1'h0;
|
|
end else begin
|
|
_T_12608 <= _T_12604 & _T_10358;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12601 <= 1'h0;
|
|
end else begin
|
|
_T_12601 <= _T_12597 & _T_10351;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12594 <= 1'h0;
|
|
end else begin
|
|
_T_12594 <= _T_12590 & _T_10344;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12587 <= 1'h0;
|
|
end else begin
|
|
_T_12587 <= _T_12583 & _T_10337;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12580 <= 1'h0;
|
|
end else begin
|
|
_T_12580 <= _T_12576 & _T_10330;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12573 <= 1'h0;
|
|
end else begin
|
|
_T_12573 <= _T_12569 & _T_10323;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12566 <= 1'h0;
|
|
end else begin
|
|
_T_12566 <= _T_12562 & _T_10316;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12559 <= 1'h0;
|
|
end else begin
|
|
_T_12559 <= _T_12555 & _T_10309;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12552 <= 1'h0;
|
|
end else begin
|
|
_T_12552 <= _T_12548 & _T_10302;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12545 <= 1'h0;
|
|
end else begin
|
|
_T_12545 <= _T_12541 & _T_10295;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12538 <= 1'h0;
|
|
end else begin
|
|
_T_12538 <= _T_12534 & _T_10288;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12531 <= 1'h0;
|
|
end else begin
|
|
_T_12531 <= _T_12527 & _T_10281;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12524 <= 1'h0;
|
|
end else begin
|
|
_T_12524 <= _T_12520 & _T_10274;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12517 <= 1'h0;
|
|
end else begin
|
|
_T_12517 <= _T_12513 & _T_10267;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12510 <= 1'h0;
|
|
end else begin
|
|
_T_12510 <= _T_12506 & _T_10260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12503 <= 1'h0;
|
|
end else begin
|
|
_T_12503 <= _T_12499 & _T_10253;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12496 <= 1'h0;
|
|
end else begin
|
|
_T_12496 <= _T_12492 & _T_10246;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12489 <= 1'h0;
|
|
end else begin
|
|
_T_12489 <= _T_12485 & _T_10239;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12482 <= 1'h0;
|
|
end else begin
|
|
_T_12482 <= _T_12478 & _T_10232;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12475 <= 1'h0;
|
|
end else begin
|
|
_T_12475 <= _T_12471 & _T_10225;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12468 <= 1'h0;
|
|
end else begin
|
|
_T_12468 <= _T_12464 & _T_10218;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12461 <= 1'h0;
|
|
end else begin
|
|
_T_12461 <= _T_12457 & _T_10211;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12454 <= 1'h0;
|
|
end else begin
|
|
_T_12454 <= _T_12450 & _T_10204;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12447 <= 1'h0;
|
|
end else begin
|
|
_T_12447 <= _T_12443 & _T_10197;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12440 <= 1'h0;
|
|
end else begin
|
|
_T_12440 <= _T_12436 & _T_10190;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12433 <= 1'h0;
|
|
end else begin
|
|
_T_12433 <= _T_12429 & _T_10183;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12426 <= 1'h0;
|
|
end else begin
|
|
_T_12426 <= _T_12422 & _T_10176;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12419 <= 1'h0;
|
|
end else begin
|
|
_T_12419 <= _T_12415 & _T_10169;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12412 <= 1'h0;
|
|
end else begin
|
|
_T_12412 <= _T_12408 & _T_10162;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12405 <= 1'h0;
|
|
end else begin
|
|
_T_12405 <= _T_12401 & _T_10155;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12398 <= 1'h0;
|
|
end else begin
|
|
_T_12398 <= _T_12394 & _T_10148;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12391 <= 1'h0;
|
|
end else begin
|
|
_T_12391 <= _T_12387 & _T_10141;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12384 <= 1'h0;
|
|
end else begin
|
|
_T_12384 <= _T_12380 & _T_10134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12377 <= 1'h0;
|
|
end else begin
|
|
_T_12377 <= _T_12373 & _T_10127;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12370 <= 1'h0;
|
|
end else begin
|
|
_T_12370 <= _T_12366 & _T_10120;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12363 <= 1'h0;
|
|
end else begin
|
|
_T_12363 <= _T_12359 & _T_10113;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12356 <= 1'h0;
|
|
end else begin
|
|
_T_12356 <= _T_12352 & _T_10106;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12349 <= 1'h0;
|
|
end else begin
|
|
_T_12349 <= _T_12345 & _T_10099;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12342 <= 1'h0;
|
|
end else begin
|
|
_T_12342 <= _T_12338 & _T_10092;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12335 <= 1'h0;
|
|
end else begin
|
|
_T_12335 <= _T_12331 & _T_10085;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12328 <= 1'h0;
|
|
end else begin
|
|
_T_12328 <= _T_12324 & _T_10078;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12321 <= 1'h0;
|
|
end else begin
|
|
_T_12321 <= _T_12317 & _T_10071;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12314 <= 1'h0;
|
|
end else begin
|
|
_T_12314 <= _T_12310 & _T_10064;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12307 <= 1'h0;
|
|
end else begin
|
|
_T_12307 <= _T_12303 & _T_10057;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12300 <= 1'h0;
|
|
end else begin
|
|
_T_12300 <= _T_12296 & _T_10050;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12293 <= 1'h0;
|
|
end else begin
|
|
_T_12293 <= _T_12289 & _T_10043;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12286 <= 1'h0;
|
|
end else begin
|
|
_T_12286 <= _T_12282 & _T_10036;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12279 <= 1'h0;
|
|
end else begin
|
|
_T_12279 <= _T_12275 & _T_10029;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12272 <= 1'h0;
|
|
end else begin
|
|
_T_12272 <= _T_12268 & _T_10022;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12265 <= 1'h0;
|
|
end else begin
|
|
_T_12265 <= _T_12261 & _T_10015;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12258 <= 1'h0;
|
|
end else begin
|
|
_T_12258 <= _T_12254 & _T_10008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12251 <= 1'h0;
|
|
end else begin
|
|
_T_12251 <= _T_12247 & _T_10001;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12244 <= 1'h0;
|
|
end else begin
|
|
_T_12244 <= _T_12240 & _T_9994;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12237 <= 1'h0;
|
|
end else begin
|
|
_T_12237 <= _T_12233 & _T_9987;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12230 <= 1'h0;
|
|
end else begin
|
|
_T_12230 <= _T_12226 & _T_9980;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12223 <= 1'h0;
|
|
end else begin
|
|
_T_12223 <= _T_12219 & _T_9973;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12216 <= 1'h0;
|
|
end else begin
|
|
_T_12216 <= _T_12212 & _T_9966;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12209 <= 1'h0;
|
|
end else begin
|
|
_T_12209 <= _T_12205 & _T_9959;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12202 <= 1'h0;
|
|
end else begin
|
|
_T_12202 <= _T_12198 & _T_9952;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12195 <= 1'h0;
|
|
end else begin
|
|
_T_12195 <= _T_12191 & _T_9945;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12188 <= 1'h0;
|
|
end else begin
|
|
_T_12188 <= _T_12184 & _T_9938;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12181 <= 1'h0;
|
|
end else begin
|
|
_T_12181 <= _T_12177 & _T_9931;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12174 <= 1'h0;
|
|
end else begin
|
|
_T_12174 <= _T_12170 & _T_9924;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12167 <= 1'h0;
|
|
end else begin
|
|
_T_12167 <= _T_12163 & _T_9917;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12160 <= 1'h0;
|
|
end else begin
|
|
_T_12160 <= _T_12156 & _T_9910;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12153 <= 1'h0;
|
|
end else begin
|
|
_T_12153 <= _T_12149 & _T_9903;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12146 <= 1'h0;
|
|
end else begin
|
|
_T_12146 <= _T_12142 & _T_9896;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12139 <= 1'h0;
|
|
end else begin
|
|
_T_12139 <= _T_12135 & _T_9889;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12132 <= 1'h0;
|
|
end else begin
|
|
_T_12132 <= _T_12128 & _T_9882;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12125 <= 1'h0;
|
|
end else begin
|
|
_T_12125 <= _T_12121 & _T_9875;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12118 <= 1'h0;
|
|
end else begin
|
|
_T_12118 <= _T_12114 & _T_9868;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12111 <= 1'h0;
|
|
end else begin
|
|
_T_12111 <= _T_12107 & _T_9861;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12104 <= 1'h0;
|
|
end else begin
|
|
_T_12104 <= _T_12100 & _T_9854;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12097 <= 1'h0;
|
|
end else begin
|
|
_T_12097 <= _T_12093 & _T_9847;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12090 <= 1'h0;
|
|
end else begin
|
|
_T_12090 <= _T_12086 & _T_9840;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12083 <= 1'h0;
|
|
end else begin
|
|
_T_12083 <= _T_12079 & _T_9833;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12076 <= 1'h0;
|
|
end else begin
|
|
_T_12076 <= _T_12072 & _T_9826;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_12069 <= 1'h0;
|
|
end else begin
|
|
_T_12069 <= _T_12065 & _T_9819;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14130 <= 1'h0;
|
|
end else begin
|
|
_T_14130 <= _T_14126 & _T_10442;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14123 <= 1'h0;
|
|
end else begin
|
|
_T_14123 <= _T_14119 & _T_10435;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14116 <= 1'h0;
|
|
end else begin
|
|
_T_14116 <= _T_14112 & _T_10428;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14109 <= 1'h0;
|
|
end else begin
|
|
_T_14109 <= _T_14105 & _T_10421;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14102 <= 1'h0;
|
|
end else begin
|
|
_T_14102 <= _T_14098 & _T_10414;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14095 <= 1'h0;
|
|
end else begin
|
|
_T_14095 <= _T_14091 & _T_10407;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14088 <= 1'h0;
|
|
end else begin
|
|
_T_14088 <= _T_14084 & _T_10400;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14081 <= 1'h0;
|
|
end else begin
|
|
_T_14081 <= _T_14077 & _T_10393;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14074 <= 1'h0;
|
|
end else begin
|
|
_T_14074 <= _T_14070 & _T_10386;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14067 <= 1'h0;
|
|
end else begin
|
|
_T_14067 <= _T_14063 & _T_10379;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14060 <= 1'h0;
|
|
end else begin
|
|
_T_14060 <= _T_14056 & _T_10372;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14053 <= 1'h0;
|
|
end else begin
|
|
_T_14053 <= _T_14049 & _T_10365;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14046 <= 1'h0;
|
|
end else begin
|
|
_T_14046 <= _T_14042 & _T_10358;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14039 <= 1'h0;
|
|
end else begin
|
|
_T_14039 <= _T_14035 & _T_10351;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14032 <= 1'h0;
|
|
end else begin
|
|
_T_14032 <= _T_14028 & _T_10344;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14025 <= 1'h0;
|
|
end else begin
|
|
_T_14025 <= _T_14021 & _T_10337;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14018 <= 1'h0;
|
|
end else begin
|
|
_T_14018 <= _T_14014 & _T_10330;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14011 <= 1'h0;
|
|
end else begin
|
|
_T_14011 <= _T_14007 & _T_10323;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_14004 <= 1'h0;
|
|
end else begin
|
|
_T_14004 <= _T_14000 & _T_10316;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13997 <= 1'h0;
|
|
end else begin
|
|
_T_13997 <= _T_13993 & _T_10309;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13990 <= 1'h0;
|
|
end else begin
|
|
_T_13990 <= _T_13986 & _T_10302;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13983 <= 1'h0;
|
|
end else begin
|
|
_T_13983 <= _T_13979 & _T_10295;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13976 <= 1'h0;
|
|
end else begin
|
|
_T_13976 <= _T_13972 & _T_10288;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13969 <= 1'h0;
|
|
end else begin
|
|
_T_13969 <= _T_13965 & _T_10281;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13962 <= 1'h0;
|
|
end else begin
|
|
_T_13962 <= _T_13958 & _T_10274;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13955 <= 1'h0;
|
|
end else begin
|
|
_T_13955 <= _T_13951 & _T_10267;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13948 <= 1'h0;
|
|
end else begin
|
|
_T_13948 <= _T_13944 & _T_10260;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13941 <= 1'h0;
|
|
end else begin
|
|
_T_13941 <= _T_13937 & _T_10253;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13934 <= 1'h0;
|
|
end else begin
|
|
_T_13934 <= _T_13930 & _T_10246;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13927 <= 1'h0;
|
|
end else begin
|
|
_T_13927 <= _T_13923 & _T_10239;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13920 <= 1'h0;
|
|
end else begin
|
|
_T_13920 <= _T_13916 & _T_10232;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13913 <= 1'h0;
|
|
end else begin
|
|
_T_13913 <= _T_13909 & _T_10225;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13906 <= 1'h0;
|
|
end else begin
|
|
_T_13906 <= _T_13902 & _T_10218;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13899 <= 1'h0;
|
|
end else begin
|
|
_T_13899 <= _T_13895 & _T_10211;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13892 <= 1'h0;
|
|
end else begin
|
|
_T_13892 <= _T_13888 & _T_10204;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13885 <= 1'h0;
|
|
end else begin
|
|
_T_13885 <= _T_13881 & _T_10197;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13878 <= 1'h0;
|
|
end else begin
|
|
_T_13878 <= _T_13874 & _T_10190;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13871 <= 1'h0;
|
|
end else begin
|
|
_T_13871 <= _T_13867 & _T_10183;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13864 <= 1'h0;
|
|
end else begin
|
|
_T_13864 <= _T_13860 & _T_10176;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13857 <= 1'h0;
|
|
end else begin
|
|
_T_13857 <= _T_13853 & _T_10169;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13850 <= 1'h0;
|
|
end else begin
|
|
_T_13850 <= _T_13846 & _T_10162;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13843 <= 1'h0;
|
|
end else begin
|
|
_T_13843 <= _T_13839 & _T_10155;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13836 <= 1'h0;
|
|
end else begin
|
|
_T_13836 <= _T_13832 & _T_10148;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13829 <= 1'h0;
|
|
end else begin
|
|
_T_13829 <= _T_13825 & _T_10141;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13822 <= 1'h0;
|
|
end else begin
|
|
_T_13822 <= _T_13818 & _T_10134;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13815 <= 1'h0;
|
|
end else begin
|
|
_T_13815 <= _T_13811 & _T_10127;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13808 <= 1'h0;
|
|
end else begin
|
|
_T_13808 <= _T_13804 & _T_10120;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13801 <= 1'h0;
|
|
end else begin
|
|
_T_13801 <= _T_13797 & _T_10113;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13794 <= 1'h0;
|
|
end else begin
|
|
_T_13794 <= _T_13790 & _T_10106;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13787 <= 1'h0;
|
|
end else begin
|
|
_T_13787 <= _T_13783 & _T_10099;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13780 <= 1'h0;
|
|
end else begin
|
|
_T_13780 <= _T_13776 & _T_10092;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13773 <= 1'h0;
|
|
end else begin
|
|
_T_13773 <= _T_13769 & _T_10085;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13766 <= 1'h0;
|
|
end else begin
|
|
_T_13766 <= _T_13762 & _T_10078;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13759 <= 1'h0;
|
|
end else begin
|
|
_T_13759 <= _T_13755 & _T_10071;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13752 <= 1'h0;
|
|
end else begin
|
|
_T_13752 <= _T_13748 & _T_10064;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13745 <= 1'h0;
|
|
end else begin
|
|
_T_13745 <= _T_13741 & _T_10057;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13738 <= 1'h0;
|
|
end else begin
|
|
_T_13738 <= _T_13734 & _T_10050;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13731 <= 1'h0;
|
|
end else begin
|
|
_T_13731 <= _T_13727 & _T_10043;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13724 <= 1'h0;
|
|
end else begin
|
|
_T_13724 <= _T_13720 & _T_10036;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13717 <= 1'h0;
|
|
end else begin
|
|
_T_13717 <= _T_13713 & _T_10029;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13710 <= 1'h0;
|
|
end else begin
|
|
_T_13710 <= _T_13706 & _T_10022;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13703 <= 1'h0;
|
|
end else begin
|
|
_T_13703 <= _T_13699 & _T_10015;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13696 <= 1'h0;
|
|
end else begin
|
|
_T_13696 <= _T_13692 & _T_10008;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13689 <= 1'h0;
|
|
end else begin
|
|
_T_13689 <= _T_13685 & _T_10001;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13682 <= 1'h0;
|
|
end else begin
|
|
_T_13682 <= _T_13678 & _T_9994;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13675 <= 1'h0;
|
|
end else begin
|
|
_T_13675 <= _T_13671 & _T_9987;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13668 <= 1'h0;
|
|
end else begin
|
|
_T_13668 <= _T_13664 & _T_9980;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13661 <= 1'h0;
|
|
end else begin
|
|
_T_13661 <= _T_13657 & _T_9973;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13654 <= 1'h0;
|
|
end else begin
|
|
_T_13654 <= _T_13650 & _T_9966;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13647 <= 1'h0;
|
|
end else begin
|
|
_T_13647 <= _T_13643 & _T_9959;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13640 <= 1'h0;
|
|
end else begin
|
|
_T_13640 <= _T_13636 & _T_9952;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13633 <= 1'h0;
|
|
end else begin
|
|
_T_13633 <= _T_13629 & _T_9945;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13626 <= 1'h0;
|
|
end else begin
|
|
_T_13626 <= _T_13622 & _T_9938;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13619 <= 1'h0;
|
|
end else begin
|
|
_T_13619 <= _T_13615 & _T_9931;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13612 <= 1'h0;
|
|
end else begin
|
|
_T_13612 <= _T_13608 & _T_9924;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13605 <= 1'h0;
|
|
end else begin
|
|
_T_13605 <= _T_13601 & _T_9917;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13598 <= 1'h0;
|
|
end else begin
|
|
_T_13598 <= _T_13594 & _T_9910;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13591 <= 1'h0;
|
|
end else begin
|
|
_T_13591 <= _T_13587 & _T_9903;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13584 <= 1'h0;
|
|
end else begin
|
|
_T_13584 <= _T_13580 & _T_9896;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13577 <= 1'h0;
|
|
end else begin
|
|
_T_13577 <= _T_13573 & _T_9889;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13570 <= 1'h0;
|
|
end else begin
|
|
_T_13570 <= _T_13566 & _T_9882;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13563 <= 1'h0;
|
|
end else begin
|
|
_T_13563 <= _T_13559 & _T_9875;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13556 <= 1'h0;
|
|
end else begin
|
|
_T_13556 <= _T_13552 & _T_9868;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13549 <= 1'h0;
|
|
end else begin
|
|
_T_13549 <= _T_13545 & _T_9861;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13542 <= 1'h0;
|
|
end else begin
|
|
_T_13542 <= _T_13538 & _T_9854;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13535 <= 1'h0;
|
|
end else begin
|
|
_T_13535 <= _T_13531 & _T_9847;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13528 <= 1'h0;
|
|
end else begin
|
|
_T_13528 <= _T_13524 & _T_9840;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13521 <= 1'h0;
|
|
end else begin
|
|
_T_13521 <= _T_13517 & _T_9833;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13514 <= 1'h0;
|
|
end else begin
|
|
_T_13514 <= _T_13510 & _T_9826;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_13507 <= 1'h0;
|
|
end else begin
|
|
_T_13507 <= _T_13503 & _T_9819;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15031 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
_T_15031 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_write;
|
|
end else if (_T_17281) begin
|
|
_T_15031 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_15031 <= _T_17274;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15033 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
_T_15033 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_write;
|
|
end else if (_T_17281) begin
|
|
_T_15033 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_15033 <= _T_17274;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15035 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
_T_15035 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_write;
|
|
end else if (_T_17281) begin
|
|
_T_15035 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_15035 <= _T_17274;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15037 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
_T_15037 <= io_dbg_dec_dma_dbg_ib_dbg_cmd_write;
|
|
end else if (_T_17281) begin
|
|
_T_15037 <= axi_mstr_priority;
|
|
end else begin
|
|
_T_15037 <= _T_17274;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15039 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
_T_15039 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15041 <= 1'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
_T_15041 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15043 <= 1'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
_T_15043 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15045 <= 1'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
_T_15045 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15047 <= 1'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
_T_15047 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15049 <= 1'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
_T_15049 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15051 <= 1'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
_T_15051 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15053 <= 1'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
_T_15053 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15055 <= 1'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
_T_15055 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15057 <= 1'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
_T_15057 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15059 <= 1'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
_T_15059 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15061 <= 1'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
_T_15061 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15063 <= 1'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
_T_15063 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15065 <= 1'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
_T_15065 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15067 <= 1'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
_T_15067 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15069 <= 1'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
_T_15069 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15071 <= 1'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
_T_15071 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15073 <= 1'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
_T_15073 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15075 <= 1'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
_T_15075 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15077 <= 1'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
_T_15077 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15079 <= 1'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
_T_15079 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15081 <= 1'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
_T_15081 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15083 <= 1'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
_T_15083 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15085 <= 1'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
_T_15085 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15087 <= 1'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
_T_15087 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15089 <= 1'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
_T_15089 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15091 <= 1'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
_T_15091 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15093 <= 1'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
_T_15093 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15095 <= 1'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
_T_15095 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15097 <= 1'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
_T_15097 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15099 <= 1'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
_T_15099 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15101 <= 1'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
_T_15101 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15103 <= 1'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
_T_15103 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15105 <= 1'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
_T_15105 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15107 <= 1'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
_T_15107 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15109 <= 1'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
_T_15109 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15111 <= 1'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
_T_15111 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15113 <= 1'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
_T_15113 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15115 <= 1'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
_T_15115 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15117 <= 1'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
_T_15117 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15119 <= 1'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
_T_15119 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15121 <= 1'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
_T_15121 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15123 <= 1'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
_T_15123 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15125 <= 1'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
_T_15125 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15127 <= 1'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
_T_15127 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15129 <= 1'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
_T_15129 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15131 <= 1'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
_T_15131 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15133 <= 1'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
_T_15133 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15135 <= 1'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
_T_15135 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15137 <= 1'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
_T_15137 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15139 <= 1'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
_T_15139 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15141 <= 1'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
_T_15141 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15143 <= 1'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
_T_15143 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15145 <= 1'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
_T_15145 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15147 <= 1'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
_T_15147 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15149 <= 1'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
_T_15149 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15151 <= 1'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
_T_15151 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15153 <= 1'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
_T_15153 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15155 <= 1'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
_T_15155 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15157 <= 1'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
_T_15157 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15159 <= 1'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
_T_15159 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15161 <= 1'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
_T_15161 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15163 <= 1'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
_T_15163 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15165 <= 1'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
_T_15165 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15167 <= 1'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
_T_15167 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15169 <= 1'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
_T_15169 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15171 <= 1'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
_T_15171 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15173 <= 1'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
_T_15173 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15175 <= 1'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
_T_15175 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15177 <= 1'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
_T_15177 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15179 <= 1'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
_T_15179 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15181 <= 1'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
_T_15181 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15183 <= 1'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
_T_15183 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15185 <= 1'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
_T_15185 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15187 <= 1'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
_T_15187 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15189 <= 1'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
_T_15189 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15191 <= 1'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
_T_15191 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15193 <= 1'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
_T_15193 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15195 <= 1'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
_T_15195 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15197 <= 1'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
_T_15197 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15199 <= 1'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
_T_15199 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15201 <= 1'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
_T_15201 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15203 <= 1'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
_T_15203 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15205 <= 1'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
_T_15205 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15207 <= 1'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
_T_15207 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
_T_15209 <= 1'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
_T_15209 <= fifo_write_in;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_0 <= 64'h0;
|
|
end else if (fifo_data_en[0]) begin
|
|
if (_T_8467) begin
|
|
fifo_data_0 <= _T_8469;
|
|
end else if (_T_835) begin
|
|
fifo_data_0 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_838) begin
|
|
fifo_data_0 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_data_0 <= _T_8474;
|
|
end else begin
|
|
fifo_data_0 <= wrbuf_data;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_1 <= 64'h0;
|
|
end else if (fifo_data_en[1]) begin
|
|
if (_T_8482) begin
|
|
fifo_data_1 <= _T_8484;
|
|
end else if (_T_853) begin
|
|
fifo_data_1 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_856) begin
|
|
fifo_data_1 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_data_1 <= _T_8474;
|
|
end else begin
|
|
fifo_data_1 <= wrbuf_data;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_2 <= 64'h0;
|
|
end else if (fifo_data_en[2]) begin
|
|
if (_T_8497) begin
|
|
fifo_data_2 <= _T_8499;
|
|
end else if (_T_871) begin
|
|
fifo_data_2 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_874) begin
|
|
fifo_data_2 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_data_2 <= _T_8474;
|
|
end else begin
|
|
fifo_data_2 <= wrbuf_data;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_3 <= 64'h0;
|
|
end else if (fifo_data_en[3]) begin
|
|
if (_T_8512) begin
|
|
fifo_data_3 <= _T_8514;
|
|
end else if (_T_889) begin
|
|
fifo_data_3 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_892) begin
|
|
fifo_data_3 <= io_iccm_dma_rdata;
|
|
end else if (io_dbg_dec_dma_dbg_ib_dbg_cmd_valid) begin
|
|
fifo_data_3 <= _T_8474;
|
|
end else begin
|
|
fifo_data_3 <= wrbuf_data;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_4 <= 64'h0;
|
|
end else if (fifo_data_en[4]) begin
|
|
if (_T_8527) begin
|
|
fifo_data_4 <= _T_8529;
|
|
end else if (_T_907) begin
|
|
fifo_data_4 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_910) begin
|
|
fifo_data_4 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_4 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_5 <= 64'h0;
|
|
end else if (fifo_data_en[5]) begin
|
|
if (_T_8542) begin
|
|
fifo_data_5 <= _T_8544;
|
|
end else if (_T_925) begin
|
|
fifo_data_5 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_928) begin
|
|
fifo_data_5 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_5 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_6 <= 64'h0;
|
|
end else if (fifo_data_en[6]) begin
|
|
if (_T_8557) begin
|
|
fifo_data_6 <= _T_8559;
|
|
end else if (_T_943) begin
|
|
fifo_data_6 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_946) begin
|
|
fifo_data_6 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_6 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_7 <= 64'h0;
|
|
end else if (fifo_data_en[7]) begin
|
|
if (_T_8572) begin
|
|
fifo_data_7 <= _T_8574;
|
|
end else if (_T_961) begin
|
|
fifo_data_7 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_964) begin
|
|
fifo_data_7 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_7 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_8 <= 64'h0;
|
|
end else if (fifo_data_en[8]) begin
|
|
if (_T_8587) begin
|
|
fifo_data_8 <= _T_8589;
|
|
end else if (_T_979) begin
|
|
fifo_data_8 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_982) begin
|
|
fifo_data_8 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_8 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_9 <= 64'h0;
|
|
end else if (fifo_data_en[9]) begin
|
|
if (_T_8602) begin
|
|
fifo_data_9 <= _T_8604;
|
|
end else if (_T_997) begin
|
|
fifo_data_9 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1000) begin
|
|
fifo_data_9 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_9 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_10 <= 64'h0;
|
|
end else if (fifo_data_en[10]) begin
|
|
if (_T_8617) begin
|
|
fifo_data_10 <= _T_8619;
|
|
end else if (_T_1015) begin
|
|
fifo_data_10 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1018) begin
|
|
fifo_data_10 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_10 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_11 <= 64'h0;
|
|
end else if (fifo_data_en[11]) begin
|
|
if (_T_8632) begin
|
|
fifo_data_11 <= _T_8634;
|
|
end else if (_T_1033) begin
|
|
fifo_data_11 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1036) begin
|
|
fifo_data_11 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_11 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_12 <= 64'h0;
|
|
end else if (fifo_data_en[12]) begin
|
|
if (_T_8647) begin
|
|
fifo_data_12 <= _T_8649;
|
|
end else if (_T_1051) begin
|
|
fifo_data_12 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1054) begin
|
|
fifo_data_12 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_12 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_13 <= 64'h0;
|
|
end else if (fifo_data_en[13]) begin
|
|
if (_T_8662) begin
|
|
fifo_data_13 <= _T_8664;
|
|
end else if (_T_1069) begin
|
|
fifo_data_13 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1072) begin
|
|
fifo_data_13 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_13 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_14 <= 64'h0;
|
|
end else if (fifo_data_en[14]) begin
|
|
if (_T_8677) begin
|
|
fifo_data_14 <= _T_8679;
|
|
end else if (_T_1087) begin
|
|
fifo_data_14 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1090) begin
|
|
fifo_data_14 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_14 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_15 <= 64'h0;
|
|
end else if (fifo_data_en[15]) begin
|
|
if (_T_8692) begin
|
|
fifo_data_15 <= _T_8694;
|
|
end else if (_T_1105) begin
|
|
fifo_data_15 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1108) begin
|
|
fifo_data_15 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_15 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_16 <= 64'h0;
|
|
end else if (fifo_data_en[16]) begin
|
|
if (_T_8707) begin
|
|
fifo_data_16 <= _T_8709;
|
|
end else if (_T_1123) begin
|
|
fifo_data_16 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1126) begin
|
|
fifo_data_16 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_16 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_17 <= 64'h0;
|
|
end else if (fifo_data_en[17]) begin
|
|
if (_T_8722) begin
|
|
fifo_data_17 <= _T_8724;
|
|
end else if (_T_1141) begin
|
|
fifo_data_17 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1144) begin
|
|
fifo_data_17 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_17 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_18 <= 64'h0;
|
|
end else if (fifo_data_en[18]) begin
|
|
if (_T_8737) begin
|
|
fifo_data_18 <= _T_8739;
|
|
end else if (_T_1159) begin
|
|
fifo_data_18 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1162) begin
|
|
fifo_data_18 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_18 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_19 <= 64'h0;
|
|
end else if (fifo_data_en[19]) begin
|
|
if (_T_8752) begin
|
|
fifo_data_19 <= _T_8754;
|
|
end else if (_T_1177) begin
|
|
fifo_data_19 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1180) begin
|
|
fifo_data_19 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_19 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_20 <= 64'h0;
|
|
end else if (fifo_data_en[20]) begin
|
|
if (_T_8767) begin
|
|
fifo_data_20 <= _T_8769;
|
|
end else if (_T_1195) begin
|
|
fifo_data_20 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1198) begin
|
|
fifo_data_20 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_20 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_21 <= 64'h0;
|
|
end else if (fifo_data_en[21]) begin
|
|
if (_T_8782) begin
|
|
fifo_data_21 <= _T_8784;
|
|
end else if (_T_1213) begin
|
|
fifo_data_21 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1216) begin
|
|
fifo_data_21 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_21 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_22 <= 64'h0;
|
|
end else if (fifo_data_en[22]) begin
|
|
if (_T_8797) begin
|
|
fifo_data_22 <= _T_8799;
|
|
end else if (_T_1231) begin
|
|
fifo_data_22 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1234) begin
|
|
fifo_data_22 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_22 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_23 <= 64'h0;
|
|
end else if (fifo_data_en[23]) begin
|
|
if (_T_8812) begin
|
|
fifo_data_23 <= _T_8814;
|
|
end else if (_T_1249) begin
|
|
fifo_data_23 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1252) begin
|
|
fifo_data_23 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_23 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_24 <= 64'h0;
|
|
end else if (fifo_data_en[24]) begin
|
|
if (_T_8827) begin
|
|
fifo_data_24 <= _T_8829;
|
|
end else if (_T_1267) begin
|
|
fifo_data_24 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1270) begin
|
|
fifo_data_24 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_24 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_25 <= 64'h0;
|
|
end else if (fifo_data_en[25]) begin
|
|
if (_T_8842) begin
|
|
fifo_data_25 <= _T_8844;
|
|
end else if (_T_1285) begin
|
|
fifo_data_25 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1288) begin
|
|
fifo_data_25 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_25 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_26 <= 64'h0;
|
|
end else if (fifo_data_en[26]) begin
|
|
if (_T_8857) begin
|
|
fifo_data_26 <= _T_8859;
|
|
end else if (_T_1303) begin
|
|
fifo_data_26 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1306) begin
|
|
fifo_data_26 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_26 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_27 <= 64'h0;
|
|
end else if (fifo_data_en[27]) begin
|
|
if (_T_8872) begin
|
|
fifo_data_27 <= _T_8874;
|
|
end else if (_T_1321) begin
|
|
fifo_data_27 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1324) begin
|
|
fifo_data_27 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_27 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_28 <= 64'h0;
|
|
end else if (fifo_data_en[28]) begin
|
|
if (_T_8887) begin
|
|
fifo_data_28 <= _T_8889;
|
|
end else if (_T_1339) begin
|
|
fifo_data_28 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1342) begin
|
|
fifo_data_28 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_28 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_29 <= 64'h0;
|
|
end else if (fifo_data_en[29]) begin
|
|
if (_T_8902) begin
|
|
fifo_data_29 <= _T_8904;
|
|
end else if (_T_1357) begin
|
|
fifo_data_29 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1360) begin
|
|
fifo_data_29 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_29 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_30 <= 64'h0;
|
|
end else if (fifo_data_en[30]) begin
|
|
if (_T_8917) begin
|
|
fifo_data_30 <= _T_8919;
|
|
end else if (_T_1375) begin
|
|
fifo_data_30 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1378) begin
|
|
fifo_data_30 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_30 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_31 <= 64'h0;
|
|
end else if (fifo_data_en[31]) begin
|
|
if (_T_8932) begin
|
|
fifo_data_31 <= _T_8934;
|
|
end else if (_T_1393) begin
|
|
fifo_data_31 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1396) begin
|
|
fifo_data_31 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_31 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_32 <= 64'h0;
|
|
end else if (fifo_data_en[32]) begin
|
|
if (_T_8947) begin
|
|
fifo_data_32 <= _T_8949;
|
|
end else if (_T_1411) begin
|
|
fifo_data_32 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1414) begin
|
|
fifo_data_32 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_32 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_33 <= 64'h0;
|
|
end else if (fifo_data_en[33]) begin
|
|
if (_T_8962) begin
|
|
fifo_data_33 <= _T_8964;
|
|
end else if (_T_1429) begin
|
|
fifo_data_33 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1432) begin
|
|
fifo_data_33 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_33 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_34 <= 64'h0;
|
|
end else if (fifo_data_en[34]) begin
|
|
if (_T_8977) begin
|
|
fifo_data_34 <= _T_8979;
|
|
end else if (_T_1447) begin
|
|
fifo_data_34 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1450) begin
|
|
fifo_data_34 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_34 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_35 <= 64'h0;
|
|
end else if (fifo_data_en[35]) begin
|
|
if (_T_8992) begin
|
|
fifo_data_35 <= _T_8994;
|
|
end else if (_T_1465) begin
|
|
fifo_data_35 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1468) begin
|
|
fifo_data_35 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_35 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_36 <= 64'h0;
|
|
end else if (fifo_data_en[36]) begin
|
|
if (_T_9007) begin
|
|
fifo_data_36 <= _T_9009;
|
|
end else if (_T_1483) begin
|
|
fifo_data_36 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1486) begin
|
|
fifo_data_36 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_36 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_37 <= 64'h0;
|
|
end else if (fifo_data_en[37]) begin
|
|
if (_T_9022) begin
|
|
fifo_data_37 <= _T_9024;
|
|
end else if (_T_1501) begin
|
|
fifo_data_37 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1504) begin
|
|
fifo_data_37 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_37 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_38 <= 64'h0;
|
|
end else if (fifo_data_en[38]) begin
|
|
if (_T_9037) begin
|
|
fifo_data_38 <= _T_9039;
|
|
end else if (_T_1519) begin
|
|
fifo_data_38 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1522) begin
|
|
fifo_data_38 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_38 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_39 <= 64'h0;
|
|
end else if (fifo_data_en[39]) begin
|
|
if (_T_9052) begin
|
|
fifo_data_39 <= _T_9054;
|
|
end else if (_T_1537) begin
|
|
fifo_data_39 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1540) begin
|
|
fifo_data_39 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_39 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_40 <= 64'h0;
|
|
end else if (fifo_data_en[40]) begin
|
|
if (_T_9067) begin
|
|
fifo_data_40 <= _T_9069;
|
|
end else if (_T_1555) begin
|
|
fifo_data_40 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1558) begin
|
|
fifo_data_40 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_40 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_41 <= 64'h0;
|
|
end else if (fifo_data_en[41]) begin
|
|
if (_T_9082) begin
|
|
fifo_data_41 <= _T_9084;
|
|
end else if (_T_1573) begin
|
|
fifo_data_41 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1576) begin
|
|
fifo_data_41 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_41 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_42 <= 64'h0;
|
|
end else if (fifo_data_en[42]) begin
|
|
if (_T_9097) begin
|
|
fifo_data_42 <= _T_9099;
|
|
end else if (_T_1591) begin
|
|
fifo_data_42 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1594) begin
|
|
fifo_data_42 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_42 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_43 <= 64'h0;
|
|
end else if (fifo_data_en[43]) begin
|
|
if (_T_9112) begin
|
|
fifo_data_43 <= _T_9114;
|
|
end else if (_T_1609) begin
|
|
fifo_data_43 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1612) begin
|
|
fifo_data_43 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_43 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_44 <= 64'h0;
|
|
end else if (fifo_data_en[44]) begin
|
|
if (_T_9127) begin
|
|
fifo_data_44 <= _T_9129;
|
|
end else if (_T_1627) begin
|
|
fifo_data_44 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1630) begin
|
|
fifo_data_44 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_44 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_45 <= 64'h0;
|
|
end else if (fifo_data_en[45]) begin
|
|
if (_T_9142) begin
|
|
fifo_data_45 <= _T_9144;
|
|
end else if (_T_1645) begin
|
|
fifo_data_45 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1648) begin
|
|
fifo_data_45 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_45 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_46 <= 64'h0;
|
|
end else if (fifo_data_en[46]) begin
|
|
if (_T_9157) begin
|
|
fifo_data_46 <= _T_9159;
|
|
end else if (_T_1663) begin
|
|
fifo_data_46 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1666) begin
|
|
fifo_data_46 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_46 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_47 <= 64'h0;
|
|
end else if (fifo_data_en[47]) begin
|
|
if (_T_9172) begin
|
|
fifo_data_47 <= _T_9174;
|
|
end else if (_T_1681) begin
|
|
fifo_data_47 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1684) begin
|
|
fifo_data_47 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_47 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_48 <= 64'h0;
|
|
end else if (fifo_data_en[48]) begin
|
|
if (_T_9187) begin
|
|
fifo_data_48 <= _T_9189;
|
|
end else if (_T_1699) begin
|
|
fifo_data_48 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1702) begin
|
|
fifo_data_48 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_48 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_49 <= 64'h0;
|
|
end else if (fifo_data_en[49]) begin
|
|
if (_T_9202) begin
|
|
fifo_data_49 <= _T_9204;
|
|
end else if (_T_1717) begin
|
|
fifo_data_49 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1720) begin
|
|
fifo_data_49 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_49 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_50 <= 64'h0;
|
|
end else if (fifo_data_en[50]) begin
|
|
if (_T_9217) begin
|
|
fifo_data_50 <= _T_9219;
|
|
end else if (_T_1735) begin
|
|
fifo_data_50 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1738) begin
|
|
fifo_data_50 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_50 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_51 <= 64'h0;
|
|
end else if (fifo_data_en[51]) begin
|
|
if (_T_9232) begin
|
|
fifo_data_51 <= _T_9234;
|
|
end else if (_T_1753) begin
|
|
fifo_data_51 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1756) begin
|
|
fifo_data_51 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_51 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_52 <= 64'h0;
|
|
end else if (fifo_data_en[52]) begin
|
|
if (_T_9247) begin
|
|
fifo_data_52 <= _T_9249;
|
|
end else if (_T_1771) begin
|
|
fifo_data_52 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1774) begin
|
|
fifo_data_52 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_52 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_53 <= 64'h0;
|
|
end else if (fifo_data_en[53]) begin
|
|
if (_T_9262) begin
|
|
fifo_data_53 <= _T_9264;
|
|
end else if (_T_1789) begin
|
|
fifo_data_53 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1792) begin
|
|
fifo_data_53 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_53 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_54 <= 64'h0;
|
|
end else if (fifo_data_en[54]) begin
|
|
if (_T_9277) begin
|
|
fifo_data_54 <= _T_9279;
|
|
end else if (_T_1807) begin
|
|
fifo_data_54 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1810) begin
|
|
fifo_data_54 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_54 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_55 <= 64'h0;
|
|
end else if (fifo_data_en[55]) begin
|
|
if (_T_9292) begin
|
|
fifo_data_55 <= _T_9294;
|
|
end else if (_T_1825) begin
|
|
fifo_data_55 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1828) begin
|
|
fifo_data_55 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_55 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_56 <= 64'h0;
|
|
end else if (fifo_data_en[56]) begin
|
|
if (_T_9307) begin
|
|
fifo_data_56 <= _T_9309;
|
|
end else if (_T_1843) begin
|
|
fifo_data_56 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1846) begin
|
|
fifo_data_56 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_56 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_57 <= 64'h0;
|
|
end else if (fifo_data_en[57]) begin
|
|
if (_T_9322) begin
|
|
fifo_data_57 <= _T_9324;
|
|
end else if (_T_1861) begin
|
|
fifo_data_57 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1864) begin
|
|
fifo_data_57 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_57 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_58 <= 64'h0;
|
|
end else if (fifo_data_en[58]) begin
|
|
if (_T_9337) begin
|
|
fifo_data_58 <= _T_9339;
|
|
end else if (_T_1879) begin
|
|
fifo_data_58 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1882) begin
|
|
fifo_data_58 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_58 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_59 <= 64'h0;
|
|
end else if (fifo_data_en[59]) begin
|
|
if (_T_9352) begin
|
|
fifo_data_59 <= _T_9354;
|
|
end else if (_T_1897) begin
|
|
fifo_data_59 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1900) begin
|
|
fifo_data_59 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_59 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_60 <= 64'h0;
|
|
end else if (fifo_data_en[60]) begin
|
|
if (_T_9367) begin
|
|
fifo_data_60 <= _T_9369;
|
|
end else if (_T_1915) begin
|
|
fifo_data_60 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1918) begin
|
|
fifo_data_60 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_60 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_61 <= 64'h0;
|
|
end else if (fifo_data_en[61]) begin
|
|
if (_T_9382) begin
|
|
fifo_data_61 <= _T_9384;
|
|
end else if (_T_1933) begin
|
|
fifo_data_61 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1936) begin
|
|
fifo_data_61 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_61 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_62 <= 64'h0;
|
|
end else if (fifo_data_en[62]) begin
|
|
if (_T_9397) begin
|
|
fifo_data_62 <= _T_9399;
|
|
end else if (_T_1951) begin
|
|
fifo_data_62 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1954) begin
|
|
fifo_data_62 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_62 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_63 <= 64'h0;
|
|
end else if (fifo_data_en[63]) begin
|
|
if (_T_9412) begin
|
|
fifo_data_63 <= _T_9414;
|
|
end else if (_T_1969) begin
|
|
fifo_data_63 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1972) begin
|
|
fifo_data_63 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_63 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_64 <= 64'h0;
|
|
end else if (fifo_data_en[64]) begin
|
|
if (_T_9427) begin
|
|
fifo_data_64 <= _T_9429;
|
|
end else if (_T_1987) begin
|
|
fifo_data_64 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_1990) begin
|
|
fifo_data_64 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_64 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_65 <= 64'h0;
|
|
end else if (fifo_data_en[65]) begin
|
|
if (_T_9442) begin
|
|
fifo_data_65 <= _T_9444;
|
|
end else if (_T_2005) begin
|
|
fifo_data_65 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2008) begin
|
|
fifo_data_65 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_65 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_66 <= 64'h0;
|
|
end else if (fifo_data_en[66]) begin
|
|
if (_T_9457) begin
|
|
fifo_data_66 <= _T_9459;
|
|
end else if (_T_2023) begin
|
|
fifo_data_66 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2026) begin
|
|
fifo_data_66 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_66 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_67 <= 64'h0;
|
|
end else if (fifo_data_en[67]) begin
|
|
if (_T_9472) begin
|
|
fifo_data_67 <= _T_9474;
|
|
end else if (_T_2041) begin
|
|
fifo_data_67 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2044) begin
|
|
fifo_data_67 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_67 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_68 <= 64'h0;
|
|
end else if (fifo_data_en[68]) begin
|
|
if (_T_9487) begin
|
|
fifo_data_68 <= _T_9489;
|
|
end else if (_T_2059) begin
|
|
fifo_data_68 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2062) begin
|
|
fifo_data_68 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_68 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_69 <= 64'h0;
|
|
end else if (fifo_data_en[69]) begin
|
|
if (_T_9502) begin
|
|
fifo_data_69 <= _T_9504;
|
|
end else if (_T_2077) begin
|
|
fifo_data_69 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2080) begin
|
|
fifo_data_69 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_69 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_70 <= 64'h0;
|
|
end else if (fifo_data_en[70]) begin
|
|
if (_T_9517) begin
|
|
fifo_data_70 <= _T_9519;
|
|
end else if (_T_2095) begin
|
|
fifo_data_70 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2098) begin
|
|
fifo_data_70 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_70 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_71 <= 64'h0;
|
|
end else if (fifo_data_en[71]) begin
|
|
if (_T_9532) begin
|
|
fifo_data_71 <= _T_9534;
|
|
end else if (_T_2113) begin
|
|
fifo_data_71 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2116) begin
|
|
fifo_data_71 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_71 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_72 <= 64'h0;
|
|
end else if (fifo_data_en[72]) begin
|
|
if (_T_9547) begin
|
|
fifo_data_72 <= _T_9549;
|
|
end else if (_T_2131) begin
|
|
fifo_data_72 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2134) begin
|
|
fifo_data_72 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_72 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_73 <= 64'h0;
|
|
end else if (fifo_data_en[73]) begin
|
|
if (_T_9562) begin
|
|
fifo_data_73 <= _T_9564;
|
|
end else if (_T_2149) begin
|
|
fifo_data_73 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2152) begin
|
|
fifo_data_73 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_73 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_74 <= 64'h0;
|
|
end else if (fifo_data_en[74]) begin
|
|
if (_T_9577) begin
|
|
fifo_data_74 <= _T_9579;
|
|
end else if (_T_2167) begin
|
|
fifo_data_74 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2170) begin
|
|
fifo_data_74 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_74 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_75 <= 64'h0;
|
|
end else if (fifo_data_en[75]) begin
|
|
if (_T_9592) begin
|
|
fifo_data_75 <= _T_9594;
|
|
end else if (_T_2185) begin
|
|
fifo_data_75 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2188) begin
|
|
fifo_data_75 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_75 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_76 <= 64'h0;
|
|
end else if (fifo_data_en[76]) begin
|
|
if (_T_9607) begin
|
|
fifo_data_76 <= _T_9609;
|
|
end else if (_T_2203) begin
|
|
fifo_data_76 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2206) begin
|
|
fifo_data_76 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_76 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_77 <= 64'h0;
|
|
end else if (fifo_data_en[77]) begin
|
|
if (_T_9622) begin
|
|
fifo_data_77 <= _T_9624;
|
|
end else if (_T_2221) begin
|
|
fifo_data_77 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2224) begin
|
|
fifo_data_77 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_77 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_78 <= 64'h0;
|
|
end else if (fifo_data_en[78]) begin
|
|
if (_T_9637) begin
|
|
fifo_data_78 <= _T_9639;
|
|
end else if (_T_2239) begin
|
|
fifo_data_78 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2242) begin
|
|
fifo_data_78 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_78 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_79 <= 64'h0;
|
|
end else if (fifo_data_en[79]) begin
|
|
if (_T_9652) begin
|
|
fifo_data_79 <= _T_9654;
|
|
end else if (_T_2257) begin
|
|
fifo_data_79 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2260) begin
|
|
fifo_data_79 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_79 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_80 <= 64'h0;
|
|
end else if (fifo_data_en[80]) begin
|
|
if (_T_9667) begin
|
|
fifo_data_80 <= _T_9669;
|
|
end else if (_T_2275) begin
|
|
fifo_data_80 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2278) begin
|
|
fifo_data_80 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_80 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_81 <= 64'h0;
|
|
end else if (fifo_data_en[81]) begin
|
|
if (_T_9682) begin
|
|
fifo_data_81 <= _T_9684;
|
|
end else if (_T_2293) begin
|
|
fifo_data_81 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2296) begin
|
|
fifo_data_81 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_81 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_82 <= 64'h0;
|
|
end else if (fifo_data_en[82]) begin
|
|
if (_T_9697) begin
|
|
fifo_data_82 <= _T_9699;
|
|
end else if (_T_2311) begin
|
|
fifo_data_82 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2314) begin
|
|
fifo_data_82 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_82 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_83 <= 64'h0;
|
|
end else if (fifo_data_en[83]) begin
|
|
if (_T_9712) begin
|
|
fifo_data_83 <= _T_9714;
|
|
end else if (_T_2329) begin
|
|
fifo_data_83 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2332) begin
|
|
fifo_data_83 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_83 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_84 <= 64'h0;
|
|
end else if (fifo_data_en[84]) begin
|
|
if (_T_9727) begin
|
|
fifo_data_84 <= _T_9729;
|
|
end else if (_T_2347) begin
|
|
fifo_data_84 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2350) begin
|
|
fifo_data_84 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_84 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_85 <= 64'h0;
|
|
end else if (fifo_data_en[85]) begin
|
|
if (_T_9742) begin
|
|
fifo_data_85 <= _T_9744;
|
|
end else if (_T_2365) begin
|
|
fifo_data_85 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2368) begin
|
|
fifo_data_85 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_85 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_86 <= 64'h0;
|
|
end else if (fifo_data_en[86]) begin
|
|
if (_T_9757) begin
|
|
fifo_data_86 <= _T_9759;
|
|
end else if (_T_2383) begin
|
|
fifo_data_86 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2386) begin
|
|
fifo_data_86 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_86 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_87 <= 64'h0;
|
|
end else if (fifo_data_en[87]) begin
|
|
if (_T_9772) begin
|
|
fifo_data_87 <= _T_9774;
|
|
end else if (_T_2401) begin
|
|
fifo_data_87 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2404) begin
|
|
fifo_data_87 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_87 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_88 <= 64'h0;
|
|
end else if (fifo_data_en[88]) begin
|
|
if (_T_9787) begin
|
|
fifo_data_88 <= _T_9789;
|
|
end else if (_T_2419) begin
|
|
fifo_data_88 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2422) begin
|
|
fifo_data_88 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_88 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_data_89 <= 64'h0;
|
|
end else if (fifo_data_en[89]) begin
|
|
if (_T_9802) begin
|
|
fifo_data_89 <= _T_9804;
|
|
end else if (_T_2437) begin
|
|
fifo_data_89 <= io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata;
|
|
end else if (_T_2440) begin
|
|
fifo_data_89 <= io_iccm_dma_rdata;
|
|
end else begin
|
|
fifo_data_89 <= _T_8476;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_0 <= 1'h0;
|
|
end else if (fifo_cmd_en[0]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_0 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_0 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
wrbuf_tag <= 1'h0;
|
|
end else if (_T_17249) begin
|
|
wrbuf_tag <= io_dma_axi_aw_bits_id;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
rdbuf_tag <= 1'h0;
|
|
end else if (_T_17262) begin
|
|
rdbuf_tag <= io_dma_axi_ar_bits_id;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_1 <= 1'h0;
|
|
end else if (fifo_cmd_en[1]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_1 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_1 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_2 <= 1'h0;
|
|
end else if (fifo_cmd_en[2]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_2 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_2 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_3 <= 1'h0;
|
|
end else if (fifo_cmd_en[3]) begin
|
|
if (axi_mstr_sel) begin
|
|
fifo_tag_3 <= wrbuf_tag;
|
|
end else begin
|
|
fifo_tag_3 <= rdbuf_tag;
|
|
end
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_4 <= 1'h0;
|
|
end else if (fifo_cmd_en[4]) begin
|
|
fifo_tag_4 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_5 <= 1'h0;
|
|
end else if (fifo_cmd_en[5]) begin
|
|
fifo_tag_5 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_6 <= 1'h0;
|
|
end else if (fifo_cmd_en[6]) begin
|
|
fifo_tag_6 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_7 <= 1'h0;
|
|
end else if (fifo_cmd_en[7]) begin
|
|
fifo_tag_7 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_8 <= 1'h0;
|
|
end else if (fifo_cmd_en[8]) begin
|
|
fifo_tag_8 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_9 <= 1'h0;
|
|
end else if (fifo_cmd_en[9]) begin
|
|
fifo_tag_9 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_10 <= 1'h0;
|
|
end else if (fifo_cmd_en[10]) begin
|
|
fifo_tag_10 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_11 <= 1'h0;
|
|
end else if (fifo_cmd_en[11]) begin
|
|
fifo_tag_11 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_12 <= 1'h0;
|
|
end else if (fifo_cmd_en[12]) begin
|
|
fifo_tag_12 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_13 <= 1'h0;
|
|
end else if (fifo_cmd_en[13]) begin
|
|
fifo_tag_13 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_14 <= 1'h0;
|
|
end else if (fifo_cmd_en[14]) begin
|
|
fifo_tag_14 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_15 <= 1'h0;
|
|
end else if (fifo_cmd_en[15]) begin
|
|
fifo_tag_15 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_16 <= 1'h0;
|
|
end else if (fifo_cmd_en[16]) begin
|
|
fifo_tag_16 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_17 <= 1'h0;
|
|
end else if (fifo_cmd_en[17]) begin
|
|
fifo_tag_17 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_18 <= 1'h0;
|
|
end else if (fifo_cmd_en[18]) begin
|
|
fifo_tag_18 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_19 <= 1'h0;
|
|
end else if (fifo_cmd_en[19]) begin
|
|
fifo_tag_19 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_20 <= 1'h0;
|
|
end else if (fifo_cmd_en[20]) begin
|
|
fifo_tag_20 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_21 <= 1'h0;
|
|
end else if (fifo_cmd_en[21]) begin
|
|
fifo_tag_21 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_22 <= 1'h0;
|
|
end else if (fifo_cmd_en[22]) begin
|
|
fifo_tag_22 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_23 <= 1'h0;
|
|
end else if (fifo_cmd_en[23]) begin
|
|
fifo_tag_23 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_24 <= 1'h0;
|
|
end else if (fifo_cmd_en[24]) begin
|
|
fifo_tag_24 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_25 <= 1'h0;
|
|
end else if (fifo_cmd_en[25]) begin
|
|
fifo_tag_25 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_26 <= 1'h0;
|
|
end else if (fifo_cmd_en[26]) begin
|
|
fifo_tag_26 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_27 <= 1'h0;
|
|
end else if (fifo_cmd_en[27]) begin
|
|
fifo_tag_27 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_28 <= 1'h0;
|
|
end else if (fifo_cmd_en[28]) begin
|
|
fifo_tag_28 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_29 <= 1'h0;
|
|
end else if (fifo_cmd_en[29]) begin
|
|
fifo_tag_29 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_30 <= 1'h0;
|
|
end else if (fifo_cmd_en[30]) begin
|
|
fifo_tag_30 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_31 <= 1'h0;
|
|
end else if (fifo_cmd_en[31]) begin
|
|
fifo_tag_31 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_32 <= 1'h0;
|
|
end else if (fifo_cmd_en[32]) begin
|
|
fifo_tag_32 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_33 <= 1'h0;
|
|
end else if (fifo_cmd_en[33]) begin
|
|
fifo_tag_33 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_34 <= 1'h0;
|
|
end else if (fifo_cmd_en[34]) begin
|
|
fifo_tag_34 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_35 <= 1'h0;
|
|
end else if (fifo_cmd_en[35]) begin
|
|
fifo_tag_35 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_36 <= 1'h0;
|
|
end else if (fifo_cmd_en[36]) begin
|
|
fifo_tag_36 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_37 <= 1'h0;
|
|
end else if (fifo_cmd_en[37]) begin
|
|
fifo_tag_37 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_38 <= 1'h0;
|
|
end else if (fifo_cmd_en[38]) begin
|
|
fifo_tag_38 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_39 <= 1'h0;
|
|
end else if (fifo_cmd_en[39]) begin
|
|
fifo_tag_39 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_40 <= 1'h0;
|
|
end else if (fifo_cmd_en[40]) begin
|
|
fifo_tag_40 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_41 <= 1'h0;
|
|
end else if (fifo_cmd_en[41]) begin
|
|
fifo_tag_41 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_42 <= 1'h0;
|
|
end else if (fifo_cmd_en[42]) begin
|
|
fifo_tag_42 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_43 <= 1'h0;
|
|
end else if (fifo_cmd_en[43]) begin
|
|
fifo_tag_43 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_44 <= 1'h0;
|
|
end else if (fifo_cmd_en[44]) begin
|
|
fifo_tag_44 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_45 <= 1'h0;
|
|
end else if (fifo_cmd_en[45]) begin
|
|
fifo_tag_45 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_46 <= 1'h0;
|
|
end else if (fifo_cmd_en[46]) begin
|
|
fifo_tag_46 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_47 <= 1'h0;
|
|
end else if (fifo_cmd_en[47]) begin
|
|
fifo_tag_47 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_48 <= 1'h0;
|
|
end else if (fifo_cmd_en[48]) begin
|
|
fifo_tag_48 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_49 <= 1'h0;
|
|
end else if (fifo_cmd_en[49]) begin
|
|
fifo_tag_49 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_50 <= 1'h0;
|
|
end else if (fifo_cmd_en[50]) begin
|
|
fifo_tag_50 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_51 <= 1'h0;
|
|
end else if (fifo_cmd_en[51]) begin
|
|
fifo_tag_51 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_52 <= 1'h0;
|
|
end else if (fifo_cmd_en[52]) begin
|
|
fifo_tag_52 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_53 <= 1'h0;
|
|
end else if (fifo_cmd_en[53]) begin
|
|
fifo_tag_53 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_54 <= 1'h0;
|
|
end else if (fifo_cmd_en[54]) begin
|
|
fifo_tag_54 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_55 <= 1'h0;
|
|
end else if (fifo_cmd_en[55]) begin
|
|
fifo_tag_55 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_56 <= 1'h0;
|
|
end else if (fifo_cmd_en[56]) begin
|
|
fifo_tag_56 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_57 <= 1'h0;
|
|
end else if (fifo_cmd_en[57]) begin
|
|
fifo_tag_57 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_58 <= 1'h0;
|
|
end else if (fifo_cmd_en[58]) begin
|
|
fifo_tag_58 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_59 <= 1'h0;
|
|
end else if (fifo_cmd_en[59]) begin
|
|
fifo_tag_59 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_60 <= 1'h0;
|
|
end else if (fifo_cmd_en[60]) begin
|
|
fifo_tag_60 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_61 <= 1'h0;
|
|
end else if (fifo_cmd_en[61]) begin
|
|
fifo_tag_61 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_62 <= 1'h0;
|
|
end else if (fifo_cmd_en[62]) begin
|
|
fifo_tag_62 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_63 <= 1'h0;
|
|
end else if (fifo_cmd_en[63]) begin
|
|
fifo_tag_63 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_64 <= 1'h0;
|
|
end else if (fifo_cmd_en[64]) begin
|
|
fifo_tag_64 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_65 <= 1'h0;
|
|
end else if (fifo_cmd_en[65]) begin
|
|
fifo_tag_65 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_66 <= 1'h0;
|
|
end else if (fifo_cmd_en[66]) begin
|
|
fifo_tag_66 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_67 <= 1'h0;
|
|
end else if (fifo_cmd_en[67]) begin
|
|
fifo_tag_67 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_68 <= 1'h0;
|
|
end else if (fifo_cmd_en[68]) begin
|
|
fifo_tag_68 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_69 <= 1'h0;
|
|
end else if (fifo_cmd_en[69]) begin
|
|
fifo_tag_69 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_70 <= 1'h0;
|
|
end else if (fifo_cmd_en[70]) begin
|
|
fifo_tag_70 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_71 <= 1'h0;
|
|
end else if (fifo_cmd_en[71]) begin
|
|
fifo_tag_71 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_72 <= 1'h0;
|
|
end else if (fifo_cmd_en[72]) begin
|
|
fifo_tag_72 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_73 <= 1'h0;
|
|
end else if (fifo_cmd_en[73]) begin
|
|
fifo_tag_73 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_74 <= 1'h0;
|
|
end else if (fifo_cmd_en[74]) begin
|
|
fifo_tag_74 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_75 <= 1'h0;
|
|
end else if (fifo_cmd_en[75]) begin
|
|
fifo_tag_75 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_76 <= 1'h0;
|
|
end else if (fifo_cmd_en[76]) begin
|
|
fifo_tag_76 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_77 <= 1'h0;
|
|
end else if (fifo_cmd_en[77]) begin
|
|
fifo_tag_77 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_78 <= 1'h0;
|
|
end else if (fifo_cmd_en[78]) begin
|
|
fifo_tag_78 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_79 <= 1'h0;
|
|
end else if (fifo_cmd_en[79]) begin
|
|
fifo_tag_79 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_80 <= 1'h0;
|
|
end else if (fifo_cmd_en[80]) begin
|
|
fifo_tag_80 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_81 <= 1'h0;
|
|
end else if (fifo_cmd_en[81]) begin
|
|
fifo_tag_81 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_82 <= 1'h0;
|
|
end else if (fifo_cmd_en[82]) begin
|
|
fifo_tag_82 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_83 <= 1'h0;
|
|
end else if (fifo_cmd_en[83]) begin
|
|
fifo_tag_83 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_84 <= 1'h0;
|
|
end else if (fifo_cmd_en[84]) begin
|
|
fifo_tag_84 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_85 <= 1'h0;
|
|
end else if (fifo_cmd_en[85]) begin
|
|
fifo_tag_85 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_86 <= 1'h0;
|
|
end else if (fifo_cmd_en[86]) begin
|
|
fifo_tag_86 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_87 <= 1'h0;
|
|
end else if (fifo_cmd_en[87]) begin
|
|
fifo_tag_87 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_88 <= 1'h0;
|
|
end else if (fifo_cmd_en[88]) begin
|
|
fifo_tag_88 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
fifo_tag_89 <= 1'h0;
|
|
end else if (fifo_cmd_en[89]) begin
|
|
fifo_tag_89 <= bus_cmd_tag;
|
|
end
|
|
end
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
dma_nack_count <= 3'h0;
|
|
end else if (dma_mem_req) begin
|
|
if (_T_17139) begin
|
|
dma_nack_count <= _T_17149;
|
|
end else if (_T_17152) begin
|
|
dma_nack_count <= _T_17154;
|
|
end else begin
|
|
dma_nack_count <= 3'h0;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
module quasar(
|
|
input clock,
|
|
input reset,
|
|
input io_lsu_axi_aw_ready,
|
|
output io_lsu_axi_aw_valid,
|
|
output [2:0] io_lsu_axi_aw_bits_id,
|
|
output [31:0] io_lsu_axi_aw_bits_addr,
|
|
output [3:0] io_lsu_axi_aw_bits_region,
|
|
output [2:0] io_lsu_axi_aw_bits_size,
|
|
output [3:0] io_lsu_axi_aw_bits_cache,
|
|
input io_lsu_axi_w_ready,
|
|
output io_lsu_axi_w_valid,
|
|
output [63:0] io_lsu_axi_w_bits_data,
|
|
output [7:0] io_lsu_axi_w_bits_strb,
|
|
input io_lsu_axi_b_valid,
|
|
input [1:0] io_lsu_axi_b_bits_resp,
|
|
input [2:0] io_lsu_axi_b_bits_id,
|
|
input io_lsu_axi_ar_ready,
|
|
output io_lsu_axi_ar_valid,
|
|
output [2:0] io_lsu_axi_ar_bits_id,
|
|
output [31:0] io_lsu_axi_ar_bits_addr,
|
|
output [3:0] io_lsu_axi_ar_bits_region,
|
|
output [2:0] io_lsu_axi_ar_bits_size,
|
|
output [3:0] io_lsu_axi_ar_bits_cache,
|
|
input io_lsu_axi_r_valid,
|
|
input [2:0] io_lsu_axi_r_bits_id,
|
|
input [63:0] io_lsu_axi_r_bits_data,
|
|
input [1:0] io_lsu_axi_r_bits_resp,
|
|
input io_ifu_axi_ar_ready,
|
|
output io_ifu_axi_ar_valid,
|
|
output [2:0] io_ifu_axi_ar_bits_id,
|
|
output [31:0] io_ifu_axi_ar_bits_addr,
|
|
output [3:0] io_ifu_axi_ar_bits_region,
|
|
input io_ifu_axi_r_valid,
|
|
input [2:0] io_ifu_axi_r_bits_id,
|
|
input [63:0] io_ifu_axi_r_bits_data,
|
|
input [1:0] io_ifu_axi_r_bits_resp,
|
|
input io_sb_axi_aw_ready,
|
|
output io_sb_axi_aw_valid,
|
|
output [31:0] io_sb_axi_aw_bits_addr,
|
|
output [3:0] io_sb_axi_aw_bits_region,
|
|
output [2:0] io_sb_axi_aw_bits_size,
|
|
input io_sb_axi_w_ready,
|
|
output io_sb_axi_w_valid,
|
|
output [63:0] io_sb_axi_w_bits_data,
|
|
output [7:0] io_sb_axi_w_bits_strb,
|
|
input io_sb_axi_b_valid,
|
|
input [1:0] io_sb_axi_b_bits_resp,
|
|
input io_sb_axi_ar_ready,
|
|
output io_sb_axi_ar_valid,
|
|
output [31:0] io_sb_axi_ar_bits_addr,
|
|
output [3:0] io_sb_axi_ar_bits_region,
|
|
output [2:0] io_sb_axi_ar_bits_size,
|
|
input io_sb_axi_r_valid,
|
|
input [63:0] io_sb_axi_r_bits_data,
|
|
input [1:0] io_sb_axi_r_bits_resp,
|
|
output io_dma_axi_aw_ready,
|
|
input io_dma_axi_aw_valid,
|
|
input io_dma_axi_aw_bits_id,
|
|
input [31:0] io_dma_axi_aw_bits_addr,
|
|
input [2:0] io_dma_axi_aw_bits_size,
|
|
output io_dma_axi_w_ready,
|
|
input io_dma_axi_w_valid,
|
|
input [63:0] io_dma_axi_w_bits_data,
|
|
input [7:0] io_dma_axi_w_bits_strb,
|
|
input io_dma_axi_b_ready,
|
|
output io_dma_axi_b_valid,
|
|
output [1:0] io_dma_axi_b_bits_resp,
|
|
output io_dma_axi_b_bits_id,
|
|
output io_dma_axi_ar_ready,
|
|
input io_dma_axi_ar_valid,
|
|
input io_dma_axi_ar_bits_id,
|
|
input [31:0] io_dma_axi_ar_bits_addr,
|
|
input [2:0] io_dma_axi_ar_bits_size,
|
|
input io_dma_axi_r_ready,
|
|
output io_dma_axi_r_valid,
|
|
output io_dma_axi_r_bits_id,
|
|
output [63:0] io_dma_axi_r_bits_data,
|
|
output [1:0] io_dma_axi_r_bits_resp,
|
|
output io_active_l2clk,
|
|
output io_free_l2clk,
|
|
input io_dbg_rst_l,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
output io_core_rst_l,
|
|
output io_rv_trace_pkt_rv_i_valid_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_insn_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_address_ip,
|
|
output io_rv_trace_pkt_rv_i_exception_ip,
|
|
output [4:0] io_rv_trace_pkt_rv_i_ecause_ip,
|
|
output io_rv_trace_pkt_rv_i_interrupt_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_tval_ip,
|
|
output io_dccm_clk_override,
|
|
output io_icm_clk_override,
|
|
output io_dec_tlu_core_ecc_disable,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_cpu_run_ack,
|
|
output io_o_debug_mode_status,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
output io_dccm_wren,
|
|
output io_dccm_rden,
|
|
output [15:0] io_dccm_wr_addr_lo,
|
|
output [15:0] io_dccm_wr_addr_hi,
|
|
output [15:0] io_dccm_rd_addr_lo,
|
|
output [15:0] io_dccm_rd_addr_hi,
|
|
output [38:0] io_dccm_wr_data_lo,
|
|
output [38:0] io_dccm_wr_data_hi,
|
|
input [38:0] io_dccm_rd_data_lo,
|
|
input [38:0] io_dccm_rd_data_hi,
|
|
output [30:0] io_ic_rw_addr,
|
|
output [1:0] io_ic_tag_valid,
|
|
output [1:0] io_ic_wr_en,
|
|
output io_ic_rd_en,
|
|
output [70:0] io_ic_wr_data_0,
|
|
output [70:0] io_ic_wr_data_1,
|
|
output [70:0] io_ic_debug_wr_data,
|
|
output [9:0] io_ic_debug_addr,
|
|
input [63:0] io_ic_rd_data,
|
|
input [70:0] io_ic_debug_rd_data,
|
|
input [25:0] io_ic_tag_debug_rd_data,
|
|
input [1:0] io_ic_eccerr,
|
|
input [1:0] io_ic_rd_hit,
|
|
input io_ic_tag_perr,
|
|
output io_ic_debug_rd_en,
|
|
output io_ic_debug_wr_en,
|
|
output io_ic_debug_tag_array,
|
|
output [1:0] io_ic_debug_way,
|
|
output [63:0] io_ic_premux_data,
|
|
output io_ic_sel_premux_data,
|
|
output [14:0] io_iccm_rw_addr,
|
|
output io_iccm_buf_correct_ecc,
|
|
output io_iccm_correction_state,
|
|
output io_iccm_wren,
|
|
output io_iccm_rden,
|
|
output [2:0] io_iccm_wr_size,
|
|
output [77:0] io_iccm_wr_data,
|
|
input [63:0] io_iccm_rd_data,
|
|
input [77:0] io_iccm_rd_data_ecc,
|
|
input io_lsu_bus_clk_en,
|
|
input io_ifu_bus_clk_en,
|
|
input io_dbg_bus_clk_en,
|
|
input io_dma_bus_clk_en,
|
|
input io_dmi_reg_en,
|
|
input [6:0] io_dmi_reg_addr,
|
|
input io_dmi_reg_wr_en,
|
|
input [31:0] io_dmi_reg_wdata,
|
|
output [31:0] io_dmi_reg_rdata,
|
|
input [30:0] io_extintsrc_req,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
input io_scan_mode
|
|
);
|
|
wire ifu_clock; // @[quasar.scala 76:19]
|
|
wire ifu_reset; // @[quasar.scala 76:19]
|
|
wire ifu_io_dec_i0_decode_d; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_flush_final; // @[quasar.scala 76:19]
|
|
wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 76:19]
|
|
wire ifu_io_free_l2clk; // @[quasar.scala 76:19]
|
|
wire ifu_io_active_clk; // @[quasar.scala 76:19]
|
|
wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 76:19]
|
|
wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 76:19]
|
|
wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 76:19]
|
|
wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 76:19]
|
|
wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 76:19]
|
|
wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 76:19]
|
|
wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 76:19]
|
|
wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_valid; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 76:19]
|
|
wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 76:19]
|
|
wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 76:19]
|
|
wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 76:19]
|
|
wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 76:19]
|
|
wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_correction_state; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_wren; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_rden; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 76:19]
|
|
wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 76:19]
|
|
wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 76:19]
|
|
wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_rd_en; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 76:19]
|
|
wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 76:19]
|
|
wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 76:19]
|
|
wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_tag_perr; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_debug_rd_en; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_debug_wr_en; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_debug_tag_array; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 76:19]
|
|
wire ifu_io_ic_sel_premux_data; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_ar_ready; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_ar_valid; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 76:19]
|
|
wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 76:19]
|
|
wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_r_valid; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 76:19]
|
|
wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 76:19]
|
|
wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 76:19]
|
|
wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 76:19]
|
|
wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 76:19]
|
|
wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_ready; // @[quasar.scala 76:19]
|
|
wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 76:19]
|
|
wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 76:19]
|
|
wire dec_clock; // @[quasar.scala 77:19]
|
|
wire dec_reset; // @[quasar.scala 77:19]
|
|
wire dec_io_free_clk; // @[quasar.scala 77:19]
|
|
wire dec_io_active_clk; // @[quasar.scala 77:19]
|
|
wire dec_io_free_l2clk; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_rst_vec; // @[quasar.scala 77:19]
|
|
wire dec_io_nmi_int; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_nmi_vec; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_lsu_nonblock_load_data; // @[quasar.scala 77:19]
|
|
wire dec_io_i_cpu_halt_req; // @[quasar.scala 77:19]
|
|
wire dec_io_i_cpu_run_req; // @[quasar.scala 77:19]
|
|
wire dec_io_o_cpu_halt_status; // @[quasar.scala 77:19]
|
|
wire dec_io_o_cpu_halt_ack; // @[quasar.scala 77:19]
|
|
wire dec_io_o_cpu_run_ack; // @[quasar.scala 77:19]
|
|
wire dec_io_o_debug_mode_status; // @[quasar.scala 77:19]
|
|
wire [27:0] dec_io_core_id; // @[quasar.scala 77:19]
|
|
wire dec_io_mpc_debug_halt_req; // @[quasar.scala 77:19]
|
|
wire dec_io_mpc_debug_run_req; // @[quasar.scala 77:19]
|
|
wire dec_io_mpc_reset_run_req; // @[quasar.scala 77:19]
|
|
wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 77:19]
|
|
wire dec_io_mpc_debug_run_ack; // @[quasar.scala 77:19]
|
|
wire dec_io_debug_brkpt_status; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 77:19]
|
|
wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_idle_any; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 77:19]
|
|
wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_exu_div_result; // @[quasar.scala 77:19]
|
|
wire dec_io_exu_div_wren; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_load_stall_any; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_store_stall_any; // @[quasar.scala 77:19]
|
|
wire dec_io_iccm_dma_sb_error; // @[quasar.scala 77:19]
|
|
wire dec_io_exu_flush_final; // @[quasar.scala 77:19]
|
|
wire dec_io_timer_int; // @[quasar.scala 77:19]
|
|
wire dec_io_soft_int; // @[quasar.scala 77:19]
|
|
wire dec_io_dbg_halt_req; // @[quasar.scala 77:19]
|
|
wire dec_io_dbg_resume_req; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_dec_csr_rddata_d; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_0_m; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_1_m; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_2_m; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 77:19]
|
|
wire dec_io_trigger_pkt_any_3_m; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 77:19]
|
|
wire dec_io_exu_i0_br_way_r; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_by; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_half; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_word; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_load; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_store; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 77:19]
|
|
wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 77:19]
|
|
wire dec_io_trace_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trace_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trace_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 77:19]
|
|
wire dec_io_trace_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 77:19]
|
|
wire [4:0] dec_io_trace_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 77:19]
|
|
wire dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_trace_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_picio_clk_override; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_i0_decode_d; // @[quasar.scala 77:19]
|
|
wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 77:19]
|
|
wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 77:19]
|
|
wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 77:19]
|
|
wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 77:19]
|
|
wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 77:19]
|
|
wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 77:19]
|
|
wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 77:19]
|
|
wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 77:19]
|
|
wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 77:19]
|
|
wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_clz; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_ctz; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_pcnt; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sext_b; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sext_h; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_min; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_max; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_pack; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_packu; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_packh; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_rol; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_ror; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_grev; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_gorc; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_zbb; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sbset; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sbclr; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sbinv; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sbext; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 77:19]
|
|
wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 77:19]
|
|
wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 77:19]
|
|
wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 77:19]
|
|
wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 77:19]
|
|
wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 77:19]
|
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wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 77:19]
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|
wire dec_io_dec_exu_decode_exu_dec_i0_branch_d; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_result_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_dec_qual_lsu_d; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 77:19]
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wire [3:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 77:19]
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wire [3:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 77:19]
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wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 77:19]
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wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 77:19]
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wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 77:19]
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wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 77:19]
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wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 77:19]
|
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wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 77:19]
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wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 77:19]
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wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 77:19]
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|
wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 77:19]
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wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 77:19]
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|
wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 77:19]
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|
wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 77:19]
|
|
wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 77:19]
|
|
wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 77:19]
|
|
wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 77:19]
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|
wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 77:19]
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|
wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 77:19]
|
|
wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 77:19]
|
|
wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 77:19]
|
|
wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 77:19]
|
|
wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 77:19]
|
|
wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 77:19]
|
|
wire dec_io_dec_pic_mexintpend; // @[quasar.scala 77:19]
|
|
wire dbg_clock; // @[quasar.scala 78:19]
|
|
wire dbg_reset; // @[quasar.scala 78:19]
|
|
wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_core_rst_l; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 78:19]
|
|
wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 78:19]
|
|
wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_halt_req; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_resume_req; // @[quasar.scala 78:19]
|
|
wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 78:19]
|
|
wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 78:19]
|
|
wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 78:19]
|
|
wire dbg_io_dmi_reg_en; // @[quasar.scala 78:19]
|
|
wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 78:19]
|
|
wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_dmi_reg_rdata; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 78:19]
|
|
wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 78:19]
|
|
wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_w_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_w_valid; // @[quasar.scala 78:19]
|
|
wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 78:19]
|
|
wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_b_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_b_valid; // @[quasar.scala 78:19]
|
|
wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 78:19]
|
|
wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 78:19]
|
|
wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_r_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_sb_axi_r_valid; // @[quasar.scala 78:19]
|
|
wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 78:19]
|
|
wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 78:19]
|
|
wire [1:0] dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 78:19]
|
|
wire [31:0] dbg_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_dma_dbg_dma_bubble; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 78:19]
|
|
wire dbg_io_dbg_rst_l; // @[quasar.scala 78:19]
|
|
wire dbg_io_scan_mode; // @[quasar.scala 78:19]
|
|
wire exu_clock; // @[quasar.scala 79:19]
|
|
wire exu_reset; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 79:19]
|
|
wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 79:19]
|
|
wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 79:19]
|
|
wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 79:19]
|
|
wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_clz; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_ctz; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_pcnt; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sext_b; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sext_h; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_min; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_max; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_pack; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_packu; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_packh; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_rol; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_ror; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_grev; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_gorc; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_zbb; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sbset; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sbclr; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sbinv; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sbext; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 79:19]
|
|
wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 79:19]
|
|
wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 79:19]
|
|
wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 79:19]
|
|
wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 79:19]
|
|
wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 79:19]
|
|
wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 79:19]
|
|
wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_dec_i0_branch_d; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_result_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_dec_qual_lsu_d; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 79:19]
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wire [3:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 79:19]
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wire [3:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 79:19]
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wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 79:19]
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wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 79:19]
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wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 79:19]
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wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 79:19]
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wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 79:19]
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wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 79:19]
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wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 79:19]
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wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 79:19]
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wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_valid; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 79:19]
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wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 79:19]
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wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 79:19]
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wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 79:19]
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wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 79:19]
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wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 79:19]
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wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 79:19]
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wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 79:19]
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wire exu_io_exu_flush_final; // @[quasar.scala 79:19]
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wire [31:0] exu_io_exu_div_result; // @[quasar.scala 79:19]
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wire exu_io_exu_div_wren; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 79:19]
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wire [31:0] exu_io_dec_csr_rddata_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_lsu_nonblock_load_data; // @[quasar.scala 79:19]
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wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 79:19]
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wire [31:0] exu_io_lsu_exu_lsu_result_m; // @[quasar.scala 79:19]
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wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 79:19]
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wire lsu_clock; // @[quasar.scala 80:19]
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wire lsu_reset; // @[quasar.scala 80:19]
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wire lsu_io_clk_override; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 80:19]
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wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 80:19]
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wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 80:19]
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wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 80:19]
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wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 80:19]
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wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 80:19]
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wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_exu_lsu_result_m; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 80:19]
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wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 80:19]
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wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 80:19]
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wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 80:19]
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wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 80:19]
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wire lsu_io_dccm_wren; // @[quasar.scala 80:19]
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wire lsu_io_dccm_rden; // @[quasar.scala 80:19]
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wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 80:19]
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wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 80:19]
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wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 80:19]
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wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 80:19]
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wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 80:19]
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wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 80:19]
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wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 80:19]
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wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 80:19]
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wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 80:19]
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wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 80:19]
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wire lsu_io_axi_aw_ready; // @[quasar.scala 80:19]
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wire lsu_io_axi_aw_valid; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 80:19]
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wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 80:19]
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wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 80:19]
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wire lsu_io_axi_w_ready; // @[quasar.scala 80:19]
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wire lsu_io_axi_w_valid; // @[quasar.scala 80:19]
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wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 80:19]
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wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 80:19]
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wire lsu_io_axi_b_valid; // @[quasar.scala 80:19]
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wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 80:19]
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wire lsu_io_axi_ar_ready; // @[quasar.scala 80:19]
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wire lsu_io_axi_ar_valid; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 80:19]
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wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 80:19]
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wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 80:19]
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wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 80:19]
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wire lsu_io_axi_r_valid; // @[quasar.scala 80:19]
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wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 80:19]
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wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 80:19]
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wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 80:19]
|
|
wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 80:19]
|
|
wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 80:19]
|
|
wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 80:19]
|
|
wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 80:19]
|
|
wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_valid; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_by; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_half; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_word; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_load; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_store; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_0_m; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_1_m; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_2_m; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 80:19]
|
|
wire lsu_io_trigger_pkt_any_3_m; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 80:19]
|
|
wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_load_stall_any; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_store_stall_any; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_idle_any; // @[quasar.scala 80:19]
|
|
wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 80:19]
|
|
wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 80:19]
|
|
wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 80:19]
|
|
wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 80:19]
|
|
wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 80:19]
|
|
wire lsu_io_active_clk; // @[quasar.scala 80:19]
|
|
wire [31:0] lsu_io_lsu_nonblock_load_data; // @[quasar.scala 80:19]
|
|
wire pic_ctrl_inst_clock; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_reset; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_io_clk_override; // @[quasar.scala 81:29]
|
|
wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 81:29]
|
|
wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 81:29]
|
|
wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 81:29]
|
|
wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 81:29]
|
|
wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 81:29]
|
|
wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 81:29]
|
|
wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 81:29]
|
|
wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 81:29]
|
|
wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 81:29]
|
|
wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 81:29]
|
|
wire dma_ctrl_clock; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_reset; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 82:24]
|
|
wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_iccm_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 82:24]
|
|
wire [1:0] dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dbg_dma_dbg_dma_bubble; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 82:24]
|
|
wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 82:24]
|
|
wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 82:24]
|
|
wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 82:24]
|
|
wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 82:24]
|
|
wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 82:24]
|
|
wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 82:24]
|
|
wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 82:24]
|
|
wire _T_6 = dbg_io_dbg_core_rst_l; // @[quasar.scala 89:67]
|
|
wire _T_7 = _T_6 | io_scan_mode; // @[quasar.scala 89:70]
|
|
ifu ifu ( // @[quasar.scala 76:19]
|
|
.clock(ifu_clock),
|
|
.reset(ifu_reset),
|
|
.io_dec_i0_decode_d(ifu_io_dec_i0_decode_d),
|
|
.io_exu_flush_final(ifu_io_exu_flush_final),
|
|
.io_exu_flush_path_final(ifu_io_exu_flush_path_final),
|
|
.io_free_l2clk(ifu_io_free_l2clk),
|
|
.io_active_clk(ifu_io_active_clk),
|
|
.io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst(ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4(ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_valid(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret),
|
|
.io_ifu_dec_dec_aln_ifu_pmu_instr_aligned(ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid),
|
|
.io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle(ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle),
|
|
.io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb(ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb),
|
|
.io_ifu_dec_dec_ifc_dec_tlu_mrac_ff(ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff),
|
|
.io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall(ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle),
|
|
.io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb(ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb),
|
|
.io_ifu_dec_dec_bp_dec_tlu_bpred_disable(ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable),
|
|
.io_exu_ifu_exu_bp_exu_i0_br_index_r(ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r),
|
|
.io_exu_ifu_exu_bp_exu_i0_br_fghr_r(ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_valid(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_valid),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_way(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way),
|
|
.io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret(ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret),
|
|
.io_exu_ifu_exu_bp_exu_mp_eghr(ifu_io_exu_ifu_exu_bp_exu_mp_eghr),
|
|
.io_exu_ifu_exu_bp_exu_mp_fghr(ifu_io_exu_ifu_exu_bp_exu_mp_fghr),
|
|
.io_exu_ifu_exu_bp_exu_mp_index(ifu_io_exu_ifu_exu_bp_exu_mp_index),
|
|
.io_exu_ifu_exu_bp_exu_mp_btag(ifu_io_exu_ifu_exu_bp_exu_mp_btag),
|
|
.io_iccm_rw_addr(ifu_io_iccm_rw_addr),
|
|
.io_iccm_buf_correct_ecc(ifu_io_iccm_buf_correct_ecc),
|
|
.io_iccm_correction_state(ifu_io_iccm_correction_state),
|
|
.io_iccm_wren(ifu_io_iccm_wren),
|
|
.io_iccm_rden(ifu_io_iccm_rden),
|
|
.io_iccm_wr_size(ifu_io_iccm_wr_size),
|
|
.io_iccm_wr_data(ifu_io_iccm_wr_data),
|
|
.io_iccm_rd_data(ifu_io_iccm_rd_data),
|
|
.io_iccm_rd_data_ecc(ifu_io_iccm_rd_data_ecc),
|
|
.io_ic_rw_addr(ifu_io_ic_rw_addr),
|
|
.io_ic_tag_valid(ifu_io_ic_tag_valid),
|
|
.io_ic_wr_en(ifu_io_ic_wr_en),
|
|
.io_ic_rd_en(ifu_io_ic_rd_en),
|
|
.io_ic_wr_data_0(ifu_io_ic_wr_data_0),
|
|
.io_ic_wr_data_1(ifu_io_ic_wr_data_1),
|
|
.io_ic_debug_wr_data(ifu_io_ic_debug_wr_data),
|
|
.io_ic_debug_addr(ifu_io_ic_debug_addr),
|
|
.io_ic_rd_data(ifu_io_ic_rd_data),
|
|
.io_ic_debug_rd_data(ifu_io_ic_debug_rd_data),
|
|
.io_ic_tag_debug_rd_data(ifu_io_ic_tag_debug_rd_data),
|
|
.io_ic_eccerr(ifu_io_ic_eccerr),
|
|
.io_ic_rd_hit(ifu_io_ic_rd_hit),
|
|
.io_ic_tag_perr(ifu_io_ic_tag_perr),
|
|
.io_ic_debug_rd_en(ifu_io_ic_debug_rd_en),
|
|
.io_ic_debug_wr_en(ifu_io_ic_debug_wr_en),
|
|
.io_ic_debug_tag_array(ifu_io_ic_debug_tag_array),
|
|
.io_ic_debug_way(ifu_io_ic_debug_way),
|
|
.io_ic_premux_data(ifu_io_ic_premux_data),
|
|
.io_ic_sel_premux_data(ifu_io_ic_sel_premux_data),
|
|
.io_ifu_ar_ready(ifu_io_ifu_ar_ready),
|
|
.io_ifu_ar_valid(ifu_io_ifu_ar_valid),
|
|
.io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id),
|
|
.io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr),
|
|
.io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region),
|
|
.io_ifu_r_valid(ifu_io_ifu_r_valid),
|
|
.io_ifu_r_bits_id(ifu_io_ifu_r_bits_id),
|
|
.io_ifu_r_bits_data(ifu_io_ifu_r_bits_data),
|
|
.io_ifu_r_bits_resp(ifu_io_ifu_r_bits_resp),
|
|
.io_ifu_bus_clk_en(ifu_io_ifu_bus_clk_en),
|
|
.io_ifu_dma_dma_ifc_dma_iccm_stall_any(ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any),
|
|
.io_ifu_dma_dma_mem_ctl_dma_iccm_req(ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req),
|
|
.io_ifu_dma_dma_mem_ctl_dma_mem_addr(ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr),
|
|
.io_ifu_dma_dma_mem_ctl_dma_mem_sz(ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz),
|
|
.io_ifu_dma_dma_mem_ctl_dma_mem_write(ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write),
|
|
.io_ifu_dma_dma_mem_ctl_dma_mem_wdata(ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata),
|
|
.io_ifu_dma_dma_mem_ctl_dma_mem_tag(ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag),
|
|
.io_iccm_dma_ecc_error(ifu_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rvalid(ifu_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_rdata(ifu_io_iccm_dma_rdata),
|
|
.io_iccm_dma_rtag(ifu_io_iccm_dma_rtag),
|
|
.io_iccm_ready(ifu_io_iccm_ready),
|
|
.io_iccm_dma_sb_error(ifu_io_iccm_dma_sb_error),
|
|
.io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb)
|
|
);
|
|
dec dec ( // @[quasar.scala 77:19]
|
|
.clock(dec_clock),
|
|
.reset(dec_reset),
|
|
.io_free_clk(dec_io_free_clk),
|
|
.io_active_clk(dec_io_active_clk),
|
|
.io_free_l2clk(dec_io_free_l2clk),
|
|
.io_lsu_fastint_stall_any(dec_io_lsu_fastint_stall_any),
|
|
.io_rst_vec(dec_io_rst_vec),
|
|
.io_nmi_int(dec_io_nmi_int),
|
|
.io_nmi_vec(dec_io_nmi_vec),
|
|
.io_lsu_nonblock_load_data(dec_io_lsu_nonblock_load_data),
|
|
.io_i_cpu_halt_req(dec_io_i_cpu_halt_req),
|
|
.io_i_cpu_run_req(dec_io_i_cpu_run_req),
|
|
.io_o_cpu_halt_status(dec_io_o_cpu_halt_status),
|
|
.io_o_cpu_halt_ack(dec_io_o_cpu_halt_ack),
|
|
.io_o_cpu_run_ack(dec_io_o_cpu_run_ack),
|
|
.io_o_debug_mode_status(dec_io_o_debug_mode_status),
|
|
.io_core_id(dec_io_core_id),
|
|
.io_mpc_debug_halt_req(dec_io_mpc_debug_halt_req),
|
|
.io_mpc_debug_run_req(dec_io_mpc_debug_run_req),
|
|
.io_mpc_reset_run_req(dec_io_mpc_reset_run_req),
|
|
.io_mpc_debug_halt_ack(dec_io_mpc_debug_halt_ack),
|
|
.io_mpc_debug_run_ack(dec_io_mpc_debug_run_ack),
|
|
.io_debug_brkpt_status(dec_io_debug_brkpt_status),
|
|
.io_lsu_pmu_misaligned_m(dec_io_lsu_pmu_misaligned_m),
|
|
.io_lsu_fir_addr(dec_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(dec_io_lsu_fir_error),
|
|
.io_lsu_trigger_match_m(dec_io_lsu_trigger_match_m),
|
|
.io_lsu_idle_any(dec_io_lsu_idle_any),
|
|
.io_lsu_error_pkt_r_valid(dec_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(dec_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(dec_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(dec_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(dec_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(dec_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_single_ecc_error_incr(dec_io_lsu_single_ecc_error_incr),
|
|
.io_exu_div_result(dec_io_exu_div_result),
|
|
.io_exu_div_wren(dec_io_exu_div_wren),
|
|
.io_lsu_result_m(dec_io_lsu_result_m),
|
|
.io_lsu_result_corr_r(dec_io_lsu_result_corr_r),
|
|
.io_lsu_load_stall_any(dec_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(dec_io_lsu_store_stall_any),
|
|
.io_iccm_dma_sb_error(dec_io_iccm_dma_sb_error),
|
|
.io_exu_flush_final(dec_io_exu_flush_final),
|
|
.io_timer_int(dec_io_timer_int),
|
|
.io_soft_int(dec_io_soft_int),
|
|
.io_dbg_halt_req(dec_io_dbg_halt_req),
|
|
.io_dbg_resume_req(dec_io_dbg_resume_req),
|
|
.io_dec_tlu_dbg_halted(dec_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_resume_ack(dec_io_dec_tlu_resume_ack),
|
|
.io_dec_tlu_mpc_halted_only(dec_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_dbg_rddata(dec_io_dec_dbg_rddata),
|
|
.io_dec_csr_rddata_d(dec_io_dec_csr_rddata_d),
|
|
.io_dec_dbg_cmd_done(dec_io_dec_dbg_cmd_done),
|
|
.io_dec_dbg_cmd_fail(dec_io_dec_dbg_cmd_fail),
|
|
.io_trigger_pkt_any_0_select(dec_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(dec_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(dec_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(dec_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_m(dec_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(dec_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(dec_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(dec_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(dec_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(dec_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_m(dec_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(dec_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(dec_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(dec_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(dec_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(dec_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_m(dec_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(dec_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(dec_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(dec_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(dec_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(dec_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_m(dec_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(dec_io_trigger_pkt_any_3_tdata2),
|
|
.io_exu_i0_br_way_r(dec_io_exu_i0_br_way_r),
|
|
.io_lsu_p_valid(dec_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(dec_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(dec_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(dec_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(dec_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(dec_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(dec_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(dec_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(dec_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(dec_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_dec_lsu_offset_d(dec_io_dec_lsu_offset_d),
|
|
.io_dec_tlu_i0_kill_writeb_r(dec_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_perfcnt0(dec_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(dec_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(dec_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(dec_io_dec_tlu_perfcnt3),
|
|
.io_dec_lsu_valid_raw_d(dec_io_dec_lsu_valid_raw_d),
|
|
.io_trace_rv_trace_pkt_rv_i_valid_ip(dec_io_trace_rv_trace_pkt_rv_i_valid_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_insn_ip(dec_io_trace_rv_trace_pkt_rv_i_insn_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_address_ip(dec_io_trace_rv_trace_pkt_rv_i_address_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_exception_ip(dec_io_trace_rv_trace_pkt_rv_i_exception_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_ecause_ip(dec_io_trace_rv_trace_pkt_rv_i_ecause_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_interrupt_ip(dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip),
|
|
.io_trace_rv_trace_pkt_rv_i_tval_ip(dec_io_trace_rv_trace_pkt_rv_i_tval_ip),
|
|
.io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override),
|
|
.io_dec_tlu_picio_clk_override(dec_io_dec_tlu_picio_clk_override),
|
|
.io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override),
|
|
.io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override),
|
|
.io_dec_i0_decode_d(dec_io_dec_i0_decode_d),
|
|
.io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst(dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc),
|
|
.io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4(dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_valid(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way),
|
|
.io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret(dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret),
|
|
.io_ifu_dec_dec_aln_ifu_pmu_instr_aligned(dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid),
|
|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid),
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|
.io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable(dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid),
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|
.io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle(dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle),
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|
.io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb(dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb),
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|
.io_ifu_dec_dec_ifc_dec_tlu_mrac_ff(dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff),
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|
.io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall(dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall),
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|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid),
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|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error),
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|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way),
|
|
.io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle),
|
|
.io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb(dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb),
|
|
.io_ifu_dec_dec_bp_dec_tlu_bpred_disable(dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable),
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|
.io_dec_exu_dec_alu_dec_i0_alu_decode_d(dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d),
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|
.io_dec_exu_dec_alu_dec_csr_ren_d(dec_io_dec_exu_dec_alu_dec_csr_ren_d),
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|
.io_dec_exu_dec_alu_dec_i0_br_immed_d(dec_io_dec_exu_dec_alu_dec_i0_br_immed_d),
|
|
.io_dec_exu_dec_alu_exu_i0_pc_x(dec_io_dec_exu_dec_alu_exu_i0_pc_x),
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|
.io_dec_exu_dec_div_div_p_valid(dec_io_dec_exu_dec_div_div_p_valid),
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|
.io_dec_exu_dec_div_div_p_bits_unsign(dec_io_dec_exu_dec_div_div_p_bits_unsign),
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|
.io_dec_exu_dec_div_div_p_bits_rem(dec_io_dec_exu_dec_div_div_p_bits_rem),
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|
.io_dec_exu_dec_div_dec_div_cancel(dec_io_dec_exu_dec_div_dec_div_cancel),
|
|
.io_dec_exu_decode_exu_dec_data_en(dec_io_dec_exu_decode_exu_dec_data_en),
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|
.io_dec_exu_decode_exu_dec_ctl_en(dec_io_dec_exu_decode_exu_dec_ctl_en),
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|
.io_dec_exu_decode_exu_i0_ap_clz(dec_io_dec_exu_decode_exu_i0_ap_clz),
|
|
.io_dec_exu_decode_exu_i0_ap_ctz(dec_io_dec_exu_decode_exu_i0_ap_ctz),
|
|
.io_dec_exu_decode_exu_i0_ap_pcnt(dec_io_dec_exu_decode_exu_i0_ap_pcnt),
|
|
.io_dec_exu_decode_exu_i0_ap_sext_b(dec_io_dec_exu_decode_exu_i0_ap_sext_b),
|
|
.io_dec_exu_decode_exu_i0_ap_sext_h(dec_io_dec_exu_decode_exu_i0_ap_sext_h),
|
|
.io_dec_exu_decode_exu_i0_ap_min(dec_io_dec_exu_decode_exu_i0_ap_min),
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|
.io_dec_exu_decode_exu_i0_ap_max(dec_io_dec_exu_decode_exu_i0_ap_max),
|
|
.io_dec_exu_decode_exu_i0_ap_pack(dec_io_dec_exu_decode_exu_i0_ap_pack),
|
|
.io_dec_exu_decode_exu_i0_ap_packu(dec_io_dec_exu_decode_exu_i0_ap_packu),
|
|
.io_dec_exu_decode_exu_i0_ap_packh(dec_io_dec_exu_decode_exu_i0_ap_packh),
|
|
.io_dec_exu_decode_exu_i0_ap_rol(dec_io_dec_exu_decode_exu_i0_ap_rol),
|
|
.io_dec_exu_decode_exu_i0_ap_ror(dec_io_dec_exu_decode_exu_i0_ap_ror),
|
|
.io_dec_exu_decode_exu_i0_ap_grev(dec_io_dec_exu_decode_exu_i0_ap_grev),
|
|
.io_dec_exu_decode_exu_i0_ap_gorc(dec_io_dec_exu_decode_exu_i0_ap_gorc),
|
|
.io_dec_exu_decode_exu_i0_ap_zbb(dec_io_dec_exu_decode_exu_i0_ap_zbb),
|
|
.io_dec_exu_decode_exu_i0_ap_sbset(dec_io_dec_exu_decode_exu_i0_ap_sbset),
|
|
.io_dec_exu_decode_exu_i0_ap_sbclr(dec_io_dec_exu_decode_exu_i0_ap_sbclr),
|
|
.io_dec_exu_decode_exu_i0_ap_sbinv(dec_io_dec_exu_decode_exu_i0_ap_sbinv),
|
|
.io_dec_exu_decode_exu_i0_ap_sbext(dec_io_dec_exu_decode_exu_i0_ap_sbext),
|
|
.io_dec_exu_decode_exu_i0_ap_land(dec_io_dec_exu_decode_exu_i0_ap_land),
|
|
.io_dec_exu_decode_exu_i0_ap_lor(dec_io_dec_exu_decode_exu_i0_ap_lor),
|
|
.io_dec_exu_decode_exu_i0_ap_lxor(dec_io_dec_exu_decode_exu_i0_ap_lxor),
|
|
.io_dec_exu_decode_exu_i0_ap_sll(dec_io_dec_exu_decode_exu_i0_ap_sll),
|
|
.io_dec_exu_decode_exu_i0_ap_srl(dec_io_dec_exu_decode_exu_i0_ap_srl),
|
|
.io_dec_exu_decode_exu_i0_ap_sra(dec_io_dec_exu_decode_exu_i0_ap_sra),
|
|
.io_dec_exu_decode_exu_i0_ap_beq(dec_io_dec_exu_decode_exu_i0_ap_beq),
|
|
.io_dec_exu_decode_exu_i0_ap_bne(dec_io_dec_exu_decode_exu_i0_ap_bne),
|
|
.io_dec_exu_decode_exu_i0_ap_blt(dec_io_dec_exu_decode_exu_i0_ap_blt),
|
|
.io_dec_exu_decode_exu_i0_ap_bge(dec_io_dec_exu_decode_exu_i0_ap_bge),
|
|
.io_dec_exu_decode_exu_i0_ap_add(dec_io_dec_exu_decode_exu_i0_ap_add),
|
|
.io_dec_exu_decode_exu_i0_ap_sub(dec_io_dec_exu_decode_exu_i0_ap_sub),
|
|
.io_dec_exu_decode_exu_i0_ap_slt(dec_io_dec_exu_decode_exu_i0_ap_slt),
|
|
.io_dec_exu_decode_exu_i0_ap_unsign(dec_io_dec_exu_decode_exu_i0_ap_unsign),
|
|
.io_dec_exu_decode_exu_i0_ap_jal(dec_io_dec_exu_decode_exu_i0_ap_jal),
|
|
.io_dec_exu_decode_exu_i0_ap_predict_t(dec_io_dec_exu_decode_exu_i0_ap_predict_t),
|
|
.io_dec_exu_decode_exu_i0_ap_predict_nt(dec_io_dec_exu_decode_exu_i0_ap_predict_nt),
|
|
.io_dec_exu_decode_exu_i0_ap_csr_write(dec_io_dec_exu_decode_exu_i0_ap_csr_write),
|
|
.io_dec_exu_decode_exu_i0_ap_csr_imm(dec_io_dec_exu_decode_exu_i0_ap_csr_imm),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_valid(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett(dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett),
|
|
.io_dec_exu_decode_exu_i0_predict_fghr_d(dec_io_dec_exu_decode_exu_i0_predict_fghr_d),
|
|
.io_dec_exu_decode_exu_i0_predict_index_d(dec_io_dec_exu_decode_exu_i0_predict_index_d),
|
|
.io_dec_exu_decode_exu_i0_predict_btag_d(dec_io_dec_exu_decode_exu_i0_predict_btag_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs1_en_d(dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_branch_d(dec_io_dec_exu_decode_exu_dec_i0_branch_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs2_en_d(dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_immed_d(dec_io_dec_exu_decode_exu_dec_i0_immed_d),
|
|
.io_dec_exu_decode_exu_dec_i0_result_r(dec_io_dec_exu_decode_exu_dec_i0_result_r),
|
|
.io_dec_exu_decode_exu_dec_qual_lsu_d(dec_io_dec_exu_decode_exu_dec_qual_lsu_d),
|
|
.io_dec_exu_decode_exu_dec_i0_select_pc_d(dec_io_dec_exu_decode_exu_dec_i0_select_pc_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d(dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d(dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d),
|
|
.io_dec_exu_decode_exu_mul_p_valid(dec_io_dec_exu_decode_exu_mul_p_valid),
|
|
.io_dec_exu_decode_exu_mul_p_bits_rs1_sign(dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign),
|
|
.io_dec_exu_decode_exu_mul_p_bits_rs2_sign(dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign),
|
|
.io_dec_exu_decode_exu_mul_p_bits_low(dec_io_dec_exu_decode_exu_mul_p_bits_low),
|
|
.io_dec_exu_decode_exu_pred_correct_npc_x(dec_io_dec_exu_decode_exu_pred_correct_npc_x),
|
|
.io_dec_exu_decode_exu_dec_extint_stall(dec_io_dec_exu_decode_exu_dec_extint_stall),
|
|
.io_dec_exu_decode_exu_exu_i0_result_x(dec_io_dec_exu_decode_exu_exu_i0_result_x),
|
|
.io_dec_exu_decode_exu_exu_csr_rs1_x(dec_io_dec_exu_decode_exu_exu_csr_rs1_x),
|
|
.io_dec_exu_tlu_exu_dec_tlu_meihap(dec_io_dec_exu_tlu_exu_dec_tlu_meihap),
|
|
.io_dec_exu_tlu_exu_dec_tlu_flush_lower_r(dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r),
|
|
.io_dec_exu_tlu_exu_dec_tlu_flush_path_r(dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_hist_r(dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_error_r(dec_io_dec_exu_tlu_exu_exu_i0_br_error_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_start_error_r(dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_valid_r(dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_mp_r(dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_middle_r(dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_br_misp(dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken(dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_pc4(dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4),
|
|
.io_dec_exu_tlu_exu_exu_npc_r(dec_io_dec_exu_tlu_exu_exu_npc_r),
|
|
.io_dec_exu_ib_exu_dec_i0_pc_d(dec_io_dec_exu_ib_exu_dec_i0_pc_d),
|
|
.io_dec_exu_ib_exu_dec_debug_wdata_rs1_d(dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d),
|
|
.io_dec_exu_gpr_exu_gpr_i0_rs1_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d),
|
|
.io_dec_exu_gpr_exu_gpr_i0_rs2_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag(dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag),
|
|
.io_lsu_tlu_lsu_pmu_load_external_m(dec_io_lsu_tlu_lsu_pmu_load_external_m),
|
|
.io_lsu_tlu_lsu_pmu_store_external_m(dec_io_lsu_tlu_lsu_pmu_store_external_m),
|
|
.io_dec_dbg_dbg_ib_dbg_cmd_valid(dec_io_dec_dbg_dbg_ib_dbg_cmd_valid),
|
|
.io_dec_dbg_dbg_ib_dbg_cmd_write(dec_io_dec_dbg_dbg_ib_dbg_cmd_write),
|
|
.io_dec_dbg_dbg_ib_dbg_cmd_type(dec_io_dec_dbg_dbg_ib_dbg_cmd_type),
|
|
.io_dec_dbg_dbg_ib_dbg_cmd_addr(dec_io_dec_dbg_dbg_ib_dbg_cmd_addr),
|
|
.io_dec_dbg_dbg_dctl_dbg_cmd_wrdata(dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata),
|
|
.io_dec_dma_dctl_dma_dma_dccm_stall_any(dec_io_dec_dma_dctl_dma_dma_dccm_stall_any),
|
|
.io_dec_dma_tlu_dma_dma_pmu_dccm_read(dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read),
|
|
.io_dec_dma_tlu_dma_dma_pmu_dccm_write(dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write),
|
|
.io_dec_dma_tlu_dma_dma_pmu_any_read(dec_io_dec_dma_tlu_dma_dma_pmu_any_read),
|
|
.io_dec_dma_tlu_dma_dma_pmu_any_write(dec_io_dec_dma_tlu_dma_dma_pmu_any_write),
|
|
.io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty(dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty),
|
|
.io_dec_dma_tlu_dma_dma_dccm_stall_any(dec_io_dec_dma_tlu_dma_dma_dccm_stall_any),
|
|
.io_dec_dma_tlu_dma_dma_iccm_stall_any(dec_io_dec_dma_tlu_dma_dma_iccm_stall_any),
|
|
.io_dec_pic_pic_claimid(dec_io_dec_pic_pic_claimid),
|
|
.io_dec_pic_pic_pl(dec_io_dec_pic_pic_pl),
|
|
.io_dec_pic_mhwakeup(dec_io_dec_pic_mhwakeup),
|
|
.io_dec_pic_dec_tlu_meicurpl(dec_io_dec_pic_dec_tlu_meicurpl),
|
|
.io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt),
|
|
.io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend)
|
|
);
|
|
dbg dbg ( // @[quasar.scala 78:19]
|
|
.clock(dbg_clock),
|
|
.reset(dbg_reset),
|
|
.io_dbg_cmd_size(dbg_io_dbg_cmd_size),
|
|
.io_dbg_core_rst_l(dbg_io_dbg_core_rst_l),
|
|
.io_core_dbg_rddata(dbg_io_core_dbg_rddata),
|
|
.io_core_dbg_cmd_done(dbg_io_core_dbg_cmd_done),
|
|
.io_core_dbg_cmd_fail(dbg_io_core_dbg_cmd_fail),
|
|
.io_dbg_halt_req(dbg_io_dbg_halt_req),
|
|
.io_dbg_resume_req(dbg_io_dbg_resume_req),
|
|
.io_dec_tlu_dbg_halted(dbg_io_dec_tlu_dbg_halted),
|
|
.io_dec_tlu_mpc_halted_only(dbg_io_dec_tlu_mpc_halted_only),
|
|
.io_dec_tlu_resume_ack(dbg_io_dec_tlu_resume_ack),
|
|
.io_dmi_reg_en(dbg_io_dmi_reg_en),
|
|
.io_dmi_reg_addr(dbg_io_dmi_reg_addr),
|
|
.io_dmi_reg_wr_en(dbg_io_dmi_reg_wr_en),
|
|
.io_dmi_reg_wdata(dbg_io_dmi_reg_wdata),
|
|
.io_dmi_reg_rdata(dbg_io_dmi_reg_rdata),
|
|
.io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready),
|
|
.io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid),
|
|
.io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr),
|
|
.io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region),
|
|
.io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size),
|
|
.io_sb_axi_w_ready(dbg_io_sb_axi_w_ready),
|
|
.io_sb_axi_w_valid(dbg_io_sb_axi_w_valid),
|
|
.io_sb_axi_w_bits_data(dbg_io_sb_axi_w_bits_data),
|
|
.io_sb_axi_w_bits_strb(dbg_io_sb_axi_w_bits_strb),
|
|
.io_sb_axi_b_ready(dbg_io_sb_axi_b_ready),
|
|
.io_sb_axi_b_valid(dbg_io_sb_axi_b_valid),
|
|
.io_sb_axi_b_bits_resp(dbg_io_sb_axi_b_bits_resp),
|
|
.io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready),
|
|
.io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid),
|
|
.io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr),
|
|
.io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region),
|
|
.io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size),
|
|
.io_sb_axi_r_ready(dbg_io_sb_axi_r_ready),
|
|
.io_sb_axi_r_valid(dbg_io_sb_axi_r_valid),
|
|
.io_sb_axi_r_bits_data(dbg_io_sb_axi_r_bits_data),
|
|
.io_sb_axi_r_bits_resp(dbg_io_sb_axi_r_bits_resp),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_valid(dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_write(dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_write),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_type(dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_type),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_addr(dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr),
|
|
.io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata(dbg_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata),
|
|
.io_dbg_dma_dbg_dma_bubble(dbg_io_dbg_dma_dbg_dma_bubble),
|
|
.io_dbg_dma_dma_dbg_ready(dbg_io_dbg_dma_dma_dbg_ready),
|
|
.io_dbg_bus_clk_en(dbg_io_dbg_bus_clk_en),
|
|
.io_dbg_rst_l(dbg_io_dbg_rst_l),
|
|
.io_scan_mode(dbg_io_scan_mode)
|
|
);
|
|
exu exu ( // @[quasar.scala 79:19]
|
|
.clock(exu_clock),
|
|
.reset(exu_reset),
|
|
.io_dec_exu_dec_alu_dec_i0_alu_decode_d(exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d),
|
|
.io_dec_exu_dec_alu_dec_csr_ren_d(exu_io_dec_exu_dec_alu_dec_csr_ren_d),
|
|
.io_dec_exu_dec_alu_dec_i0_br_immed_d(exu_io_dec_exu_dec_alu_dec_i0_br_immed_d),
|
|
.io_dec_exu_dec_alu_exu_i0_pc_x(exu_io_dec_exu_dec_alu_exu_i0_pc_x),
|
|
.io_dec_exu_dec_div_div_p_valid(exu_io_dec_exu_dec_div_div_p_valid),
|
|
.io_dec_exu_dec_div_div_p_bits_unsign(exu_io_dec_exu_dec_div_div_p_bits_unsign),
|
|
.io_dec_exu_dec_div_div_p_bits_rem(exu_io_dec_exu_dec_div_div_p_bits_rem),
|
|
.io_dec_exu_dec_div_dec_div_cancel(exu_io_dec_exu_dec_div_dec_div_cancel),
|
|
.io_dec_exu_decode_exu_dec_data_en(exu_io_dec_exu_decode_exu_dec_data_en),
|
|
.io_dec_exu_decode_exu_dec_ctl_en(exu_io_dec_exu_decode_exu_dec_ctl_en),
|
|
.io_dec_exu_decode_exu_i0_ap_clz(exu_io_dec_exu_decode_exu_i0_ap_clz),
|
|
.io_dec_exu_decode_exu_i0_ap_ctz(exu_io_dec_exu_decode_exu_i0_ap_ctz),
|
|
.io_dec_exu_decode_exu_i0_ap_pcnt(exu_io_dec_exu_decode_exu_i0_ap_pcnt),
|
|
.io_dec_exu_decode_exu_i0_ap_sext_b(exu_io_dec_exu_decode_exu_i0_ap_sext_b),
|
|
.io_dec_exu_decode_exu_i0_ap_sext_h(exu_io_dec_exu_decode_exu_i0_ap_sext_h),
|
|
.io_dec_exu_decode_exu_i0_ap_min(exu_io_dec_exu_decode_exu_i0_ap_min),
|
|
.io_dec_exu_decode_exu_i0_ap_max(exu_io_dec_exu_decode_exu_i0_ap_max),
|
|
.io_dec_exu_decode_exu_i0_ap_pack(exu_io_dec_exu_decode_exu_i0_ap_pack),
|
|
.io_dec_exu_decode_exu_i0_ap_packu(exu_io_dec_exu_decode_exu_i0_ap_packu),
|
|
.io_dec_exu_decode_exu_i0_ap_packh(exu_io_dec_exu_decode_exu_i0_ap_packh),
|
|
.io_dec_exu_decode_exu_i0_ap_rol(exu_io_dec_exu_decode_exu_i0_ap_rol),
|
|
.io_dec_exu_decode_exu_i0_ap_ror(exu_io_dec_exu_decode_exu_i0_ap_ror),
|
|
.io_dec_exu_decode_exu_i0_ap_grev(exu_io_dec_exu_decode_exu_i0_ap_grev),
|
|
.io_dec_exu_decode_exu_i0_ap_gorc(exu_io_dec_exu_decode_exu_i0_ap_gorc),
|
|
.io_dec_exu_decode_exu_i0_ap_zbb(exu_io_dec_exu_decode_exu_i0_ap_zbb),
|
|
.io_dec_exu_decode_exu_i0_ap_sbset(exu_io_dec_exu_decode_exu_i0_ap_sbset),
|
|
.io_dec_exu_decode_exu_i0_ap_sbclr(exu_io_dec_exu_decode_exu_i0_ap_sbclr),
|
|
.io_dec_exu_decode_exu_i0_ap_sbinv(exu_io_dec_exu_decode_exu_i0_ap_sbinv),
|
|
.io_dec_exu_decode_exu_i0_ap_sbext(exu_io_dec_exu_decode_exu_i0_ap_sbext),
|
|
.io_dec_exu_decode_exu_i0_ap_land(exu_io_dec_exu_decode_exu_i0_ap_land),
|
|
.io_dec_exu_decode_exu_i0_ap_lor(exu_io_dec_exu_decode_exu_i0_ap_lor),
|
|
.io_dec_exu_decode_exu_i0_ap_lxor(exu_io_dec_exu_decode_exu_i0_ap_lxor),
|
|
.io_dec_exu_decode_exu_i0_ap_sll(exu_io_dec_exu_decode_exu_i0_ap_sll),
|
|
.io_dec_exu_decode_exu_i0_ap_srl(exu_io_dec_exu_decode_exu_i0_ap_srl),
|
|
.io_dec_exu_decode_exu_i0_ap_sra(exu_io_dec_exu_decode_exu_i0_ap_sra),
|
|
.io_dec_exu_decode_exu_i0_ap_beq(exu_io_dec_exu_decode_exu_i0_ap_beq),
|
|
.io_dec_exu_decode_exu_i0_ap_bne(exu_io_dec_exu_decode_exu_i0_ap_bne),
|
|
.io_dec_exu_decode_exu_i0_ap_blt(exu_io_dec_exu_decode_exu_i0_ap_blt),
|
|
.io_dec_exu_decode_exu_i0_ap_bge(exu_io_dec_exu_decode_exu_i0_ap_bge),
|
|
.io_dec_exu_decode_exu_i0_ap_add(exu_io_dec_exu_decode_exu_i0_ap_add),
|
|
.io_dec_exu_decode_exu_i0_ap_sub(exu_io_dec_exu_decode_exu_i0_ap_sub),
|
|
.io_dec_exu_decode_exu_i0_ap_slt(exu_io_dec_exu_decode_exu_i0_ap_slt),
|
|
.io_dec_exu_decode_exu_i0_ap_unsign(exu_io_dec_exu_decode_exu_i0_ap_unsign),
|
|
.io_dec_exu_decode_exu_i0_ap_jal(exu_io_dec_exu_decode_exu_i0_ap_jal),
|
|
.io_dec_exu_decode_exu_i0_ap_predict_t(exu_io_dec_exu_decode_exu_i0_ap_predict_t),
|
|
.io_dec_exu_decode_exu_i0_ap_predict_nt(exu_io_dec_exu_decode_exu_i0_ap_predict_nt),
|
|
.io_dec_exu_decode_exu_i0_ap_csr_write(exu_io_dec_exu_decode_exu_i0_ap_csr_write),
|
|
.io_dec_exu_decode_exu_i0_ap_csr_imm(exu_io_dec_exu_decode_exu_i0_ap_csr_imm),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_valid(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret),
|
|
.io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett(exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett),
|
|
.io_dec_exu_decode_exu_i0_predict_fghr_d(exu_io_dec_exu_decode_exu_i0_predict_fghr_d),
|
|
.io_dec_exu_decode_exu_i0_predict_index_d(exu_io_dec_exu_decode_exu_i0_predict_index_d),
|
|
.io_dec_exu_decode_exu_i0_predict_btag_d(exu_io_dec_exu_decode_exu_i0_predict_btag_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs1_en_d(exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_branch_d(exu_io_dec_exu_decode_exu_dec_i0_branch_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs2_en_d(exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_immed_d(exu_io_dec_exu_decode_exu_dec_i0_immed_d),
|
|
.io_dec_exu_decode_exu_dec_i0_result_r(exu_io_dec_exu_decode_exu_dec_i0_result_r),
|
|
.io_dec_exu_decode_exu_dec_qual_lsu_d(exu_io_dec_exu_decode_exu_dec_qual_lsu_d),
|
|
.io_dec_exu_decode_exu_dec_i0_select_pc_d(exu_io_dec_exu_decode_exu_dec_i0_select_pc_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d(exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d),
|
|
.io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d(exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d),
|
|
.io_dec_exu_decode_exu_mul_p_valid(exu_io_dec_exu_decode_exu_mul_p_valid),
|
|
.io_dec_exu_decode_exu_mul_p_bits_rs1_sign(exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign),
|
|
.io_dec_exu_decode_exu_mul_p_bits_rs2_sign(exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign),
|
|
.io_dec_exu_decode_exu_mul_p_bits_low(exu_io_dec_exu_decode_exu_mul_p_bits_low),
|
|
.io_dec_exu_decode_exu_pred_correct_npc_x(exu_io_dec_exu_decode_exu_pred_correct_npc_x),
|
|
.io_dec_exu_decode_exu_dec_extint_stall(exu_io_dec_exu_decode_exu_dec_extint_stall),
|
|
.io_dec_exu_decode_exu_exu_i0_result_x(exu_io_dec_exu_decode_exu_exu_i0_result_x),
|
|
.io_dec_exu_decode_exu_exu_csr_rs1_x(exu_io_dec_exu_decode_exu_exu_csr_rs1_x),
|
|
.io_dec_exu_tlu_exu_dec_tlu_meihap(exu_io_dec_exu_tlu_exu_dec_tlu_meihap),
|
|
.io_dec_exu_tlu_exu_dec_tlu_flush_lower_r(exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r),
|
|
.io_dec_exu_tlu_exu_dec_tlu_flush_path_r(exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_hist_r(exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_error_r(exu_io_dec_exu_tlu_exu_exu_i0_br_error_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_start_error_r(exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_index_r(exu_io_dec_exu_tlu_exu_exu_i0_br_index_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_valid_r(exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_mp_r(exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r),
|
|
.io_dec_exu_tlu_exu_exu_i0_br_middle_r(exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_br_misp(exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken(exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken),
|
|
.io_dec_exu_tlu_exu_exu_pmu_i0_pc4(exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4),
|
|
.io_dec_exu_tlu_exu_exu_npc_r(exu_io_dec_exu_tlu_exu_exu_npc_r),
|
|
.io_dec_exu_ib_exu_dec_i0_pc_d(exu_io_dec_exu_ib_exu_dec_i0_pc_d),
|
|
.io_dec_exu_ib_exu_dec_debug_wdata_rs1_d(exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d),
|
|
.io_dec_exu_gpr_exu_gpr_i0_rs1_d(exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d),
|
|
.io_dec_exu_gpr_exu_gpr_i0_rs2_d(exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d),
|
|
.io_exu_bp_exu_i0_br_fghr_r(exu_io_exu_bp_exu_i0_br_fghr_r),
|
|
.io_exu_bp_exu_i0_br_way_r(exu_io_exu_bp_exu_i0_br_way_r),
|
|
.io_exu_bp_exu_mp_pkt_valid(exu_io_exu_bp_exu_mp_pkt_valid),
|
|
.io_exu_bp_exu_mp_pkt_bits_misp(exu_io_exu_bp_exu_mp_pkt_bits_misp),
|
|
.io_exu_bp_exu_mp_pkt_bits_ataken(exu_io_exu_bp_exu_mp_pkt_bits_ataken),
|
|
.io_exu_bp_exu_mp_pkt_bits_boffset(exu_io_exu_bp_exu_mp_pkt_bits_boffset),
|
|
.io_exu_bp_exu_mp_pkt_bits_pc4(exu_io_exu_bp_exu_mp_pkt_bits_pc4),
|
|
.io_exu_bp_exu_mp_pkt_bits_hist(exu_io_exu_bp_exu_mp_pkt_bits_hist),
|
|
.io_exu_bp_exu_mp_pkt_bits_toffset(exu_io_exu_bp_exu_mp_pkt_bits_toffset),
|
|
.io_exu_bp_exu_mp_pkt_bits_pcall(exu_io_exu_bp_exu_mp_pkt_bits_pcall),
|
|
.io_exu_bp_exu_mp_pkt_bits_pja(exu_io_exu_bp_exu_mp_pkt_bits_pja),
|
|
.io_exu_bp_exu_mp_pkt_bits_way(exu_io_exu_bp_exu_mp_pkt_bits_way),
|
|
.io_exu_bp_exu_mp_pkt_bits_pret(exu_io_exu_bp_exu_mp_pkt_bits_pret),
|
|
.io_exu_bp_exu_mp_eghr(exu_io_exu_bp_exu_mp_eghr),
|
|
.io_exu_bp_exu_mp_fghr(exu_io_exu_bp_exu_mp_fghr),
|
|
.io_exu_bp_exu_mp_index(exu_io_exu_bp_exu_mp_index),
|
|
.io_exu_bp_exu_mp_btag(exu_io_exu_bp_exu_mp_btag),
|
|
.io_exu_flush_final(exu_io_exu_flush_final),
|
|
.io_exu_div_result(exu_io_exu_div_result),
|
|
.io_exu_div_wren(exu_io_exu_div_wren),
|
|
.io_dbg_cmd_wrdata(exu_io_dbg_cmd_wrdata),
|
|
.io_dec_csr_rddata_d(exu_io_dec_csr_rddata_d),
|
|
.io_lsu_nonblock_load_data(exu_io_lsu_nonblock_load_data),
|
|
.io_lsu_exu_exu_lsu_rs1_d(exu_io_lsu_exu_exu_lsu_rs1_d),
|
|
.io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d),
|
|
.io_lsu_exu_lsu_result_m(exu_io_lsu_exu_lsu_result_m),
|
|
.io_exu_flush_path_final(exu_io_exu_flush_path_final)
|
|
);
|
|
lsu lsu ( // @[quasar.scala 80:19]
|
|
.clock(lsu_clock),
|
|
.reset(lsu_reset),
|
|
.io_clk_override(lsu_io_clk_override),
|
|
.io_lsu_dma_dma_lsc_ctl_dma_dccm_req(lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req),
|
|
.io_lsu_dma_dma_lsc_ctl_dma_mem_addr(lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr),
|
|
.io_lsu_dma_dma_lsc_ctl_dma_mem_sz(lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz),
|
|
.io_lsu_dma_dma_lsc_ctl_dma_mem_write(lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write),
|
|
.io_lsu_dma_dma_lsc_ctl_dma_mem_wdata(lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata),
|
|
.io_lsu_dma_dma_dccm_ctl_dma_mem_addr(lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr),
|
|
.io_lsu_dma_dma_dccm_ctl_dma_mem_wdata(lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata),
|
|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid(lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid),
|
|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error(lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error),
|
|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag(lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag),
|
|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata(lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata),
|
|
.io_lsu_dma_dccm_ready(lsu_io_lsu_dma_dccm_ready),
|
|
.io_lsu_dma_dma_mem_tag(lsu_io_lsu_dma_dma_mem_tag),
|
|
.io_lsu_pic_picm_wren(lsu_io_lsu_pic_picm_wren),
|
|
.io_lsu_pic_picm_rden(lsu_io_lsu_pic_picm_rden),
|
|
.io_lsu_pic_picm_mken(lsu_io_lsu_pic_picm_mken),
|
|
.io_lsu_pic_picm_rdaddr(lsu_io_lsu_pic_picm_rdaddr),
|
|
.io_lsu_pic_picm_wraddr(lsu_io_lsu_pic_picm_wraddr),
|
|
.io_lsu_pic_picm_wr_data(lsu_io_lsu_pic_picm_wr_data),
|
|
.io_lsu_pic_picm_rd_data(lsu_io_lsu_pic_picm_rd_data),
|
|
.io_lsu_exu_exu_lsu_rs1_d(lsu_io_lsu_exu_exu_lsu_rs1_d),
|
|
.io_lsu_exu_exu_lsu_rs2_d(lsu_io_lsu_exu_exu_lsu_rs2_d),
|
|
.io_lsu_exu_lsu_result_m(lsu_io_lsu_exu_lsu_result_m),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
|
|
.io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable),
|
|
.io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any),
|
|
.io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error),
|
|
.io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag(lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag),
|
|
.io_dccm_wren(lsu_io_dccm_wren),
|
|
.io_dccm_rden(lsu_io_dccm_rden),
|
|
.io_dccm_wr_addr_lo(lsu_io_dccm_wr_addr_lo),
|
|
.io_dccm_wr_addr_hi(lsu_io_dccm_wr_addr_hi),
|
|
.io_dccm_rd_addr_lo(lsu_io_dccm_rd_addr_lo),
|
|
.io_dccm_rd_addr_hi(lsu_io_dccm_rd_addr_hi),
|
|
.io_dccm_wr_data_lo(lsu_io_dccm_wr_data_lo),
|
|
.io_dccm_wr_data_hi(lsu_io_dccm_wr_data_hi),
|
|
.io_dccm_rd_data_lo(lsu_io_dccm_rd_data_lo),
|
|
.io_dccm_rd_data_hi(lsu_io_dccm_rd_data_hi),
|
|
.io_lsu_tlu_lsu_pmu_load_external_m(lsu_io_lsu_tlu_lsu_pmu_load_external_m),
|
|
.io_lsu_tlu_lsu_pmu_store_external_m(lsu_io_lsu_tlu_lsu_pmu_store_external_m),
|
|
.io_axi_aw_ready(lsu_io_axi_aw_ready),
|
|
.io_axi_aw_valid(lsu_io_axi_aw_valid),
|
|
.io_axi_aw_bits_id(lsu_io_axi_aw_bits_id),
|
|
.io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr),
|
|
.io_axi_aw_bits_region(lsu_io_axi_aw_bits_region),
|
|
.io_axi_aw_bits_size(lsu_io_axi_aw_bits_size),
|
|
.io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache),
|
|
.io_axi_w_ready(lsu_io_axi_w_ready),
|
|
.io_axi_w_valid(lsu_io_axi_w_valid),
|
|
.io_axi_w_bits_data(lsu_io_axi_w_bits_data),
|
|
.io_axi_w_bits_strb(lsu_io_axi_w_bits_strb),
|
|
.io_axi_b_valid(lsu_io_axi_b_valid),
|
|
.io_axi_b_bits_resp(lsu_io_axi_b_bits_resp),
|
|
.io_axi_b_bits_id(lsu_io_axi_b_bits_id),
|
|
.io_axi_ar_ready(lsu_io_axi_ar_ready),
|
|
.io_axi_ar_valid(lsu_io_axi_ar_valid),
|
|
.io_axi_ar_bits_id(lsu_io_axi_ar_bits_id),
|
|
.io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr),
|
|
.io_axi_ar_bits_region(lsu_io_axi_ar_bits_region),
|
|
.io_axi_ar_bits_size(lsu_io_axi_ar_bits_size),
|
|
.io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache),
|
|
.io_axi_r_valid(lsu_io_axi_r_valid),
|
|
.io_axi_r_bits_id(lsu_io_axi_r_bits_id),
|
|
.io_axi_r_bits_data(lsu_io_axi_r_bits_data),
|
|
.io_axi_r_bits_resp(lsu_io_axi_r_bits_resp),
|
|
.io_dec_tlu_flush_lower_r(lsu_io_dec_tlu_flush_lower_r),
|
|
.io_dec_tlu_i0_kill_writeb_r(lsu_io_dec_tlu_i0_kill_writeb_r),
|
|
.io_dec_tlu_force_halt(lsu_io_dec_tlu_force_halt),
|
|
.io_dec_tlu_core_ecc_disable(lsu_io_dec_tlu_core_ecc_disable),
|
|
.io_dec_lsu_offset_d(lsu_io_dec_lsu_offset_d),
|
|
.io_lsu_p_valid(lsu_io_lsu_p_valid),
|
|
.io_lsu_p_bits_fast_int(lsu_io_lsu_p_bits_fast_int),
|
|
.io_lsu_p_bits_by(lsu_io_lsu_p_bits_by),
|
|
.io_lsu_p_bits_half(lsu_io_lsu_p_bits_half),
|
|
.io_lsu_p_bits_word(lsu_io_lsu_p_bits_word),
|
|
.io_lsu_p_bits_load(lsu_io_lsu_p_bits_load),
|
|
.io_lsu_p_bits_store(lsu_io_lsu_p_bits_store),
|
|
.io_lsu_p_bits_unsign(lsu_io_lsu_p_bits_unsign),
|
|
.io_lsu_p_bits_store_data_bypass_d(lsu_io_lsu_p_bits_store_data_bypass_d),
|
|
.io_lsu_p_bits_load_ldst_bypass_d(lsu_io_lsu_p_bits_load_ldst_bypass_d),
|
|
.io_trigger_pkt_any_0_select(lsu_io_trigger_pkt_any_0_select),
|
|
.io_trigger_pkt_any_0_match_pkt(lsu_io_trigger_pkt_any_0_match_pkt),
|
|
.io_trigger_pkt_any_0_store(lsu_io_trigger_pkt_any_0_store),
|
|
.io_trigger_pkt_any_0_load(lsu_io_trigger_pkt_any_0_load),
|
|
.io_trigger_pkt_any_0_m(lsu_io_trigger_pkt_any_0_m),
|
|
.io_trigger_pkt_any_0_tdata2(lsu_io_trigger_pkt_any_0_tdata2),
|
|
.io_trigger_pkt_any_1_select(lsu_io_trigger_pkt_any_1_select),
|
|
.io_trigger_pkt_any_1_match_pkt(lsu_io_trigger_pkt_any_1_match_pkt),
|
|
.io_trigger_pkt_any_1_store(lsu_io_trigger_pkt_any_1_store),
|
|
.io_trigger_pkt_any_1_load(lsu_io_trigger_pkt_any_1_load),
|
|
.io_trigger_pkt_any_1_m(lsu_io_trigger_pkt_any_1_m),
|
|
.io_trigger_pkt_any_1_tdata2(lsu_io_trigger_pkt_any_1_tdata2),
|
|
.io_trigger_pkt_any_2_select(lsu_io_trigger_pkt_any_2_select),
|
|
.io_trigger_pkt_any_2_match_pkt(lsu_io_trigger_pkt_any_2_match_pkt),
|
|
.io_trigger_pkt_any_2_store(lsu_io_trigger_pkt_any_2_store),
|
|
.io_trigger_pkt_any_2_load(lsu_io_trigger_pkt_any_2_load),
|
|
.io_trigger_pkt_any_2_m(lsu_io_trigger_pkt_any_2_m),
|
|
.io_trigger_pkt_any_2_tdata2(lsu_io_trigger_pkt_any_2_tdata2),
|
|
.io_trigger_pkt_any_3_select(lsu_io_trigger_pkt_any_3_select),
|
|
.io_trigger_pkt_any_3_match_pkt(lsu_io_trigger_pkt_any_3_match_pkt),
|
|
.io_trigger_pkt_any_3_store(lsu_io_trigger_pkt_any_3_store),
|
|
.io_trigger_pkt_any_3_load(lsu_io_trigger_pkt_any_3_load),
|
|
.io_trigger_pkt_any_3_m(lsu_io_trigger_pkt_any_3_m),
|
|
.io_trigger_pkt_any_3_tdata2(lsu_io_trigger_pkt_any_3_tdata2),
|
|
.io_dec_lsu_valid_raw_d(lsu_io_dec_lsu_valid_raw_d),
|
|
.io_dec_tlu_mrac_ff(lsu_io_dec_tlu_mrac_ff),
|
|
.io_lsu_result_corr_r(lsu_io_lsu_result_corr_r),
|
|
.io_lsu_load_stall_any(lsu_io_lsu_load_stall_any),
|
|
.io_lsu_store_stall_any(lsu_io_lsu_store_stall_any),
|
|
.io_lsu_fastint_stall_any(lsu_io_lsu_fastint_stall_any),
|
|
.io_lsu_idle_any(lsu_io_lsu_idle_any),
|
|
.io_lsu_fir_addr(lsu_io_lsu_fir_addr),
|
|
.io_lsu_fir_error(lsu_io_lsu_fir_error),
|
|
.io_lsu_single_ecc_error_incr(lsu_io_lsu_single_ecc_error_incr),
|
|
.io_lsu_error_pkt_r_valid(lsu_io_lsu_error_pkt_r_valid),
|
|
.io_lsu_error_pkt_r_bits_single_ecc_error(lsu_io_lsu_error_pkt_r_bits_single_ecc_error),
|
|
.io_lsu_error_pkt_r_bits_inst_type(lsu_io_lsu_error_pkt_r_bits_inst_type),
|
|
.io_lsu_error_pkt_r_bits_exc_type(lsu_io_lsu_error_pkt_r_bits_exc_type),
|
|
.io_lsu_error_pkt_r_bits_mscause(lsu_io_lsu_error_pkt_r_bits_mscause),
|
|
.io_lsu_error_pkt_r_bits_addr(lsu_io_lsu_error_pkt_r_bits_addr),
|
|
.io_lsu_pmu_misaligned_m(lsu_io_lsu_pmu_misaligned_m),
|
|
.io_lsu_trigger_match_m(lsu_io_lsu_trigger_match_m),
|
|
.io_lsu_bus_clk_en(lsu_io_lsu_bus_clk_en),
|
|
.io_active_clk(lsu_io_active_clk),
|
|
.io_lsu_nonblock_load_data(lsu_io_lsu_nonblock_load_data)
|
|
);
|
|
pic_ctrl pic_ctrl_inst ( // @[quasar.scala 81:29]
|
|
.clock(pic_ctrl_inst_clock),
|
|
.reset(pic_ctrl_inst_reset),
|
|
.io_free_clk(pic_ctrl_inst_io_free_clk),
|
|
.io_io_clk_override(pic_ctrl_inst_io_io_clk_override),
|
|
.io_extintsrc_req(pic_ctrl_inst_io_extintsrc_req),
|
|
.io_lsu_pic_picm_wren(pic_ctrl_inst_io_lsu_pic_picm_wren),
|
|
.io_lsu_pic_picm_rden(pic_ctrl_inst_io_lsu_pic_picm_rden),
|
|
.io_lsu_pic_picm_mken(pic_ctrl_inst_io_lsu_pic_picm_mken),
|
|
.io_lsu_pic_picm_rdaddr(pic_ctrl_inst_io_lsu_pic_picm_rdaddr),
|
|
.io_lsu_pic_picm_wraddr(pic_ctrl_inst_io_lsu_pic_picm_wraddr),
|
|
.io_lsu_pic_picm_wr_data(pic_ctrl_inst_io_lsu_pic_picm_wr_data),
|
|
.io_lsu_pic_picm_rd_data(pic_ctrl_inst_io_lsu_pic_picm_rd_data),
|
|
.io_dec_pic_pic_claimid(pic_ctrl_inst_io_dec_pic_pic_claimid),
|
|
.io_dec_pic_pic_pl(pic_ctrl_inst_io_dec_pic_pic_pl),
|
|
.io_dec_pic_mhwakeup(pic_ctrl_inst_io_dec_pic_mhwakeup),
|
|
.io_dec_pic_dec_tlu_meicurpl(pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl),
|
|
.io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt),
|
|
.io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend)
|
|
);
|
|
dma_ctrl dma_ctrl ( // @[quasar.scala 82:24]
|
|
.clock(dma_ctrl_clock),
|
|
.reset(dma_ctrl_reset),
|
|
.io_dma_bus_clk_en(dma_ctrl_io_dma_bus_clk_en),
|
|
.io_dbg_cmd_size(dma_ctrl_io_dbg_cmd_size),
|
|
.io_dma_dbg_cmd_done(dma_ctrl_io_dma_dbg_cmd_done),
|
|
.io_dma_dbg_cmd_fail(dma_ctrl_io_dma_dbg_cmd_fail),
|
|
.io_dma_dbg_rddata(dma_ctrl_io_dma_dbg_rddata),
|
|
.io_iccm_dma_rvalid(dma_ctrl_io_iccm_dma_rvalid),
|
|
.io_iccm_dma_ecc_error(dma_ctrl_io_iccm_dma_ecc_error),
|
|
.io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag),
|
|
.io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata),
|
|
.io_iccm_ready(dma_ctrl_io_iccm_ready),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_valid(dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_write(dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_write),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_type(dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_type),
|
|
.io_dbg_dec_dma_dbg_ib_dbg_cmd_addr(dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr),
|
|
.io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata(dma_ctrl_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata),
|
|
.io_dbg_dma_dbg_dma_bubble(dma_ctrl_io_dbg_dma_dbg_dma_bubble),
|
|
.io_dbg_dma_dma_dbg_ready(dma_ctrl_io_dbg_dma_dma_dbg_ready),
|
|
.io_dec_dma_dctl_dma_dma_dccm_stall_any(dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any),
|
|
.io_dec_dma_tlu_dma_dma_pmu_dccm_read(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read),
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|
.io_dec_dma_tlu_dma_dma_pmu_dccm_write(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write),
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|
.io_dec_dma_tlu_dma_dma_pmu_any_read(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read),
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|
.io_dec_dma_tlu_dma_dma_pmu_any_write(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write),
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|
.io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty(dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty),
|
|
.io_dec_dma_tlu_dma_dma_dccm_stall_any(dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any),
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|
.io_dec_dma_tlu_dma_dma_iccm_stall_any(dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any),
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|
.io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req),
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|
.io_lsu_dma_dma_lsc_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr),
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|
.io_lsu_dma_dma_lsc_ctl_dma_mem_sz(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz),
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|
.io_lsu_dma_dma_lsc_ctl_dma_mem_write(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write),
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|
.io_lsu_dma_dma_lsc_ctl_dma_mem_wdata(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata),
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|
.io_lsu_dma_dma_dccm_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr),
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|
.io_lsu_dma_dma_dccm_ctl_dma_mem_wdata(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata),
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|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid),
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|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error),
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|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag),
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|
.io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata(dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata),
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|
.io_lsu_dma_dccm_ready(dma_ctrl_io_lsu_dma_dccm_ready),
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|
.io_lsu_dma_dma_mem_tag(dma_ctrl_io_lsu_dma_dma_mem_tag),
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|
.io_ifu_dma_dma_ifc_dma_iccm_stall_any(dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any),
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|
.io_ifu_dma_dma_mem_ctl_dma_iccm_req(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req),
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|
.io_ifu_dma_dma_mem_ctl_dma_mem_addr(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr),
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|
.io_ifu_dma_dma_mem_ctl_dma_mem_sz(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz),
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|
.io_ifu_dma_dma_mem_ctl_dma_mem_write(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write),
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|
.io_ifu_dma_dma_mem_ctl_dma_mem_wdata(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata),
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|
.io_ifu_dma_dma_mem_ctl_dma_mem_tag(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag),
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|
.io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready),
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|
.io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid),
|
|
.io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id),
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|
.io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr),
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|
.io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size),
|
|
.io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready),
|
|
.io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid),
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|
.io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data),
|
|
.io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb),
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|
.io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready),
|
|
.io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid),
|
|
.io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp),
|
|
.io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id),
|
|
.io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready),
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|
.io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid),
|
|
.io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id),
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|
.io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr),
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|
.io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size),
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|
.io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready),
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|
.io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid),
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|
.io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id),
|
|
.io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data),
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|
.io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp)
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|
);
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assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 322:25]
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assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 322:25]
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assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 322:25]
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assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 322:25]
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assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 322:25]
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assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 322:25]
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assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 322:25]
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assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 322:25]
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assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 322:25]
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assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 322:25]
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assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 321:25]
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assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 321:25]
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assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 321:25]
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assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 321:25]
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|
assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 320:25]
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assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 320:25]
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|
assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 320:25]
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assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 320:25]
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assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 320:25]
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assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 320:25]
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assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 320:25]
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assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 320:25]
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assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 320:25]
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assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 320:25]
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assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 320:25]
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|
assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 319:25]
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assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 319:25]
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assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 319:25]
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assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 319:25]
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assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 319:25]
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assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 319:25]
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assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 319:25]
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assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 319:25]
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assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 319:25]
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assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 319:25]
|
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assign io_active_l2clk = clock; // @[quasar.scala 93:19]
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assign io_free_l2clk = clock; // @[quasar.scala 92:17]
|
|
assign io_core_rst_l = reset & _T_7; // @[quasar.scala 89:17]
|
|
assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_trace_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 241:19]
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|
assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_trace_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 241:19]
|
|
assign io_rv_trace_pkt_rv_i_address_ip = dec_io_trace_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 241:19]
|
|
assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_trace_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 241:19]
|
|
assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_trace_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 241:19]
|
|
assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 241:19]
|
|
assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_trace_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 241:19]
|
|
assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 244:24]
|
|
assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 245:23]
|
|
assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 246:31]
|
|
assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 247:21]
|
|
assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 248:24]
|
|
assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 249:20]
|
|
assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 250:26]
|
|
assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 251:25]
|
|
assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 252:24]
|
|
assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 253:25]
|
|
assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 254:23]
|
|
assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 255:23]
|
|
assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 256:23]
|
|
assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 257:23]
|
|
assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 261:11]
|
|
assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 261:11]
|
|
assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 261:11]
|
|
assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 261:11]
|
|
assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 261:11]
|
|
assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 261:11]
|
|
assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 261:11]
|
|
assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 261:11]
|
|
assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 111:13]
|
|
assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 111:13]
|
|
assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 111:13]
|
|
assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 111:13]
|
|
assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 111:13]
|
|
assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 111:13]
|
|
assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 111:13]
|
|
assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 111:13]
|
|
assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 111:13]
|
|
assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 112:15]
|
|
assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 112:15]
|
|
assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 112:15]
|
|
assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 112:15]
|
|
assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 112:15]
|
|
assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 112:15]
|
|
assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 112:15]
|
|
assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 258:20]
|
|
assign ifu_clock = io_active_l2clk; // @[quasar.scala 100:13]
|
|
assign ifu_reset = io_core_rst_l; // @[quasar.scala 102:13]
|
|
assign ifu_io_dec_i0_decode_d = dec_io_dec_i0_decode_d; // @[quasar.scala 99:26]
|
|
assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 106:26]
|
|
assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 107:31]
|
|
assign ifu_io_free_l2clk = io_free_l2clk; // @[quasar.scala 101:21]
|
|
assign ifu_io_active_clk = io_active_l2clk; // @[quasar.scala 104:21]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 98:18 quasar.scala 117:51]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 98:18 quasar.scala 117:51]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 98:18 quasar.scala 117:51]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 98:18 quasar.scala 117:51]
|
|
assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 98:18]
|
|
assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 98:18]
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assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 98:18]
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assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 113:25 quasar.scala 115:43]
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assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 113:25 quasar.scala 114:42]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_valid = exu_io_exu_bp_exu_mp_pkt_valid; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 113:25]
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assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 113:25]
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assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 112:15]
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assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 112:15]
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assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 111:13]
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assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 111:13]
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assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 111:13]
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assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 111:13]
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assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 111:13]
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assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 111:13]
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assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 321:25]
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assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 321:25]
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assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 321:25]
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assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 321:25]
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assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 321:25]
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assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 109:25]
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assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 110:18]
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assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 110:18]
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assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 116:33]
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assign dec_clock = io_active_l2clk; // @[quasar.scala 124:13]
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assign dec_reset = io_core_rst_l; // @[quasar.scala 123:13]
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assign dec_io_free_clk = io_free_l2clk; // @[quasar.scala 126:19]
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assign dec_io_active_clk = io_active_l2clk; // @[quasar.scala 125:21]
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assign dec_io_free_l2clk = io_free_l2clk; // @[quasar.scala 122:21]
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assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 127:32]
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assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 128:18]
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assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 129:18]
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assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 130:18]
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assign dec_io_lsu_nonblock_load_data = lsu_io_lsu_nonblock_load_data; // @[quasar.scala 121:33]
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assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 131:25]
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assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 132:24]
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assign dec_io_core_id = io_core_id; // @[quasar.scala 133:18]
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assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 134:29]
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assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 135:28]
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assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 136:28]
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assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 139:31]
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assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 142:23]
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assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 143:24]
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assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 144:30]
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assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 146:23]
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assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 147:26]
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assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 147:26]
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assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 147:26]
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assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 147:26]
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assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 147:26]
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assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 147:26]
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assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 148:36]
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assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 149:25]
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assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 150:23]
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assign dec_io_lsu_result_m = lsu_io_lsu_exu_lsu_result_m; // @[quasar.scala 151:23]
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assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 152:28]
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assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 153:29]
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assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 154:30]
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assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 155:28]
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assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 156:26]
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assign dec_io_timer_int = io_timer_int; // @[quasar.scala 162:20]
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assign dec_io_soft_int = io_soft_int; // @[quasar.scala 158:19]
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assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 159:23]
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assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 160:25]
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assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 161:26]
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assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 98:18]
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assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 98:18]
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assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 166:18]
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assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 166:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 137:18]
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assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 137:18]
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assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 138:18]
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assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 138:18]
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assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 145:18]
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assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 145:18]
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assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 145:18]
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assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 145:18]
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assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 145:18]
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assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 140:18]
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assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 140:18]
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assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 239:28]
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assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 239:28]
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assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 239:28]
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assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 239:28]
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assign dbg_clock = io_free_l2clk; // @[quasar.scala 210:13]
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assign dbg_reset = io_core_rst_l; // @[quasar.scala 211:13]
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assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 195:26]
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assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 196:28]
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assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 197:28]
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assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 199:29]
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assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 200:34]
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assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 201:29]
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assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 202:21]
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assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 203:23]
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assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 204:24]
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assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 205:24]
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assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 320:25]
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assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 320:25]
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assign dbg_io_dbg_dma_dma_dbg_ready = dma_ctrl_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 221:23]
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assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 206:25]
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assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 207:20]
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assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 209:20]
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assign exu_clock = io_active_l2clk; // @[quasar.scala 170:13]
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assign exu_reset = io_core_rst_l; // @[quasar.scala 169:13]
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assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_clz = dec_io_dec_exu_decode_exu_i0_ap_clz; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_ctz = dec_io_dec_exu_decode_exu_i0_ap_ctz; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_pcnt = dec_io_dec_exu_decode_exu_i0_ap_pcnt; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sext_b = dec_io_dec_exu_decode_exu_i0_ap_sext_b; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sext_h = dec_io_dec_exu_decode_exu_i0_ap_sext_h; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_min = dec_io_dec_exu_decode_exu_i0_ap_min; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_max = dec_io_dec_exu_decode_exu_i0_ap_max; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_pack = dec_io_dec_exu_decode_exu_i0_ap_pack; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_packu = dec_io_dec_exu_decode_exu_i0_ap_packu; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_packh = dec_io_dec_exu_decode_exu_i0_ap_packh; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_rol = dec_io_dec_exu_decode_exu_i0_ap_rol; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_ror = dec_io_dec_exu_decode_exu_i0_ap_ror; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_grev = dec_io_dec_exu_decode_exu_i0_ap_grev; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_gorc = dec_io_dec_exu_decode_exu_i0_ap_gorc; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_zbb = dec_io_dec_exu_decode_exu_i0_ap_zbb; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sbset = dec_io_dec_exu_decode_exu_i0_ap_sbset; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sbclr = dec_io_dec_exu_decode_exu_i0_ap_sbclr; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sbinv = dec_io_dec_exu_decode_exu_i0_ap_sbinv; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sbext = dec_io_dec_exu_decode_exu_i0_ap_sbext; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_branch_d = dec_io_dec_exu_decode_exu_dec_i0_branch_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_result_r = dec_io_dec_exu_decode_exu_dec_i0_result_r; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_qual_lsu_d = dec_io_dec_exu_decode_exu_dec_qual_lsu_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 166:18]
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assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 166:18]
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assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 172:25]
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assign exu_io_dec_csr_rddata_d = dec_io_dec_csr_rddata_d; // @[quasar.scala 167:27]
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assign exu_io_lsu_nonblock_load_data = lsu_io_lsu_nonblock_load_data; // @[quasar.scala 168:33]
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assign exu_io_lsu_exu_lsu_result_m = lsu_io_lsu_exu_lsu_result_m; // @[quasar.scala 182:18]
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assign lsu_clock = io_active_l2clk; // @[quasar.scala 175:13]
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assign lsu_reset = io_core_rst_l; // @[quasar.scala 176:13]
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assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 177:23]
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assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 190:18]
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assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 190:18]
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assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 238:28]
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assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 182:18]
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assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 182:18]
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assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 137:18]
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assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 137:18]
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assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 137:18]
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assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 261:11]
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assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 261:11]
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assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 322:25]
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assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 322:25]
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assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 322:25]
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assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 322:25]
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assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 322:25]
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assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 322:25]
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assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 322:25]
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assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 322:25]
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assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 322:25]
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assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 322:25]
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assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 178:32]
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assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 179:35]
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assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 180:29]
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assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 181:35]
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assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 183:27]
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assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 184:16]
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assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 184:16]
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assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_0_m = dec_io_trigger_pkt_any_0_m; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_m = dec_io_trigger_pkt_any_1_m; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_m = dec_io_trigger_pkt_any_2_m; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_m = dec_io_trigger_pkt_any_3_m; // @[quasar.scala 187:26]
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assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 187:26]
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assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 185:30]
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assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 186:26]
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assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 189:25]
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assign lsu_io_active_clk = io_active_l2clk; // @[quasar.scala 192:21]
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assign pic_ctrl_inst_clock = io_free_l2clk; // @[quasar.scala 232:23]
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assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 233:23]
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assign pic_ctrl_inst_io_free_clk = io_free_l2clk; // @[quasar.scala 234:29]
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assign pic_ctrl_inst_io_io_clk_override = dec_io_dec_tlu_picio_clk_override; // @[quasar.scala 235:36]
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assign pic_ctrl_inst_io_extintsrc_req = {io_extintsrc_req,1'h0}; // @[quasar.scala 237:34]
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assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 238:28]
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assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 239:28]
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assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 239:28]
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assign dma_ctrl_clock = io_free_l2clk; // @[quasar.scala 215:18]
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assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 216:18]
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assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 218:30]
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assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 223:28]
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assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 224:31]
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assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 228:34]
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assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 225:29]
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assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 226:30]
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assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 227:26]
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assign dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 222:27]
|
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assign dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 222:27]
|
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assign dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 222:27]
|
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assign dma_ctrl_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 222:27]
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assign dma_ctrl_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 222:27]
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assign dma_ctrl_io_dbg_dma_dbg_dma_bubble = dbg_io_dbg_dma_dbg_dma_bubble; // @[quasar.scala 221:23]
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assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 140:18]
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assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 190:18]
|
|
assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 190:18]
|
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assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 190:18]
|
|
assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 190:18]
|
|
assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 190:18]
|
|
assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 319:25]
|
|
assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 319:25]
|
|
endmodule
|
|
module quasar_wrapper(
|
|
input clock,
|
|
input reset,
|
|
input io_dbg_rst_l,
|
|
input [30:0] io_rst_vec,
|
|
input io_nmi_int,
|
|
input [30:0] io_nmi_vec,
|
|
input [30:0] io_jtag_id,
|
|
input io_lsu_brg_aw_ready,
|
|
output io_lsu_brg_aw_valid,
|
|
output [2:0] io_lsu_brg_aw_bits_id,
|
|
output [31:0] io_lsu_brg_aw_bits_addr,
|
|
output [3:0] io_lsu_brg_aw_bits_region,
|
|
output [7:0] io_lsu_brg_aw_bits_len,
|
|
output [2:0] io_lsu_brg_aw_bits_size,
|
|
output [1:0] io_lsu_brg_aw_bits_burst,
|
|
output io_lsu_brg_aw_bits_lock,
|
|
output [3:0] io_lsu_brg_aw_bits_cache,
|
|
output [2:0] io_lsu_brg_aw_bits_prot,
|
|
output [3:0] io_lsu_brg_aw_bits_qos,
|
|
input io_lsu_brg_w_ready,
|
|
output io_lsu_brg_w_valid,
|
|
output [63:0] io_lsu_brg_w_bits_data,
|
|
output [7:0] io_lsu_brg_w_bits_strb,
|
|
output io_lsu_brg_w_bits_last,
|
|
output io_lsu_brg_b_ready,
|
|
input io_lsu_brg_b_valid,
|
|
input [1:0] io_lsu_brg_b_bits_resp,
|
|
input [2:0] io_lsu_brg_b_bits_id,
|
|
input io_lsu_brg_ar_ready,
|
|
output io_lsu_brg_ar_valid,
|
|
output [2:0] io_lsu_brg_ar_bits_id,
|
|
output [31:0] io_lsu_brg_ar_bits_addr,
|
|
output [3:0] io_lsu_brg_ar_bits_region,
|
|
output [7:0] io_lsu_brg_ar_bits_len,
|
|
output [2:0] io_lsu_brg_ar_bits_size,
|
|
output [1:0] io_lsu_brg_ar_bits_burst,
|
|
output io_lsu_brg_ar_bits_lock,
|
|
output [3:0] io_lsu_brg_ar_bits_cache,
|
|
output [2:0] io_lsu_brg_ar_bits_prot,
|
|
output [3:0] io_lsu_brg_ar_bits_qos,
|
|
output io_lsu_brg_r_ready,
|
|
input io_lsu_brg_r_valid,
|
|
input [2:0] io_lsu_brg_r_bits_id,
|
|
input [63:0] io_lsu_brg_r_bits_data,
|
|
input [1:0] io_lsu_brg_r_bits_resp,
|
|
input io_lsu_brg_r_bits_last,
|
|
input io_ifu_brg_aw_ready,
|
|
output io_ifu_brg_aw_valid,
|
|
output [2:0] io_ifu_brg_aw_bits_id,
|
|
output [31:0] io_ifu_brg_aw_bits_addr,
|
|
output [3:0] io_ifu_brg_aw_bits_region,
|
|
output [7:0] io_ifu_brg_aw_bits_len,
|
|
output [2:0] io_ifu_brg_aw_bits_size,
|
|
output [1:0] io_ifu_brg_aw_bits_burst,
|
|
output io_ifu_brg_aw_bits_lock,
|
|
output [3:0] io_ifu_brg_aw_bits_cache,
|
|
output [2:0] io_ifu_brg_aw_bits_prot,
|
|
output [3:0] io_ifu_brg_aw_bits_qos,
|
|
input io_ifu_brg_w_ready,
|
|
output io_ifu_brg_w_valid,
|
|
output [63:0] io_ifu_brg_w_bits_data,
|
|
output [7:0] io_ifu_brg_w_bits_strb,
|
|
output io_ifu_brg_w_bits_last,
|
|
output io_ifu_brg_b_ready,
|
|
input io_ifu_brg_b_valid,
|
|
input [1:0] io_ifu_brg_b_bits_resp,
|
|
input [2:0] io_ifu_brg_b_bits_id,
|
|
input io_ifu_brg_ar_ready,
|
|
output io_ifu_brg_ar_valid,
|
|
output [2:0] io_ifu_brg_ar_bits_id,
|
|
output [31:0] io_ifu_brg_ar_bits_addr,
|
|
output [3:0] io_ifu_brg_ar_bits_region,
|
|
output [7:0] io_ifu_brg_ar_bits_len,
|
|
output [2:0] io_ifu_brg_ar_bits_size,
|
|
output [1:0] io_ifu_brg_ar_bits_burst,
|
|
output io_ifu_brg_ar_bits_lock,
|
|
output [3:0] io_ifu_brg_ar_bits_cache,
|
|
output [2:0] io_ifu_brg_ar_bits_prot,
|
|
output [3:0] io_ifu_brg_ar_bits_qos,
|
|
output io_ifu_brg_r_ready,
|
|
input io_ifu_brg_r_valid,
|
|
input [2:0] io_ifu_brg_r_bits_id,
|
|
input [63:0] io_ifu_brg_r_bits_data,
|
|
input [1:0] io_ifu_brg_r_bits_resp,
|
|
input io_ifu_brg_r_bits_last,
|
|
input io_sb_brg_aw_ready,
|
|
output io_sb_brg_aw_valid,
|
|
output io_sb_brg_aw_bits_id,
|
|
output [31:0] io_sb_brg_aw_bits_addr,
|
|
output [3:0] io_sb_brg_aw_bits_region,
|
|
output [7:0] io_sb_brg_aw_bits_len,
|
|
output [2:0] io_sb_brg_aw_bits_size,
|
|
output [1:0] io_sb_brg_aw_bits_burst,
|
|
output io_sb_brg_aw_bits_lock,
|
|
output [3:0] io_sb_brg_aw_bits_cache,
|
|
output [2:0] io_sb_brg_aw_bits_prot,
|
|
output [3:0] io_sb_brg_aw_bits_qos,
|
|
input io_sb_brg_w_ready,
|
|
output io_sb_brg_w_valid,
|
|
output [63:0] io_sb_brg_w_bits_data,
|
|
output [7:0] io_sb_brg_w_bits_strb,
|
|
output io_sb_brg_w_bits_last,
|
|
output io_sb_brg_b_ready,
|
|
input io_sb_brg_b_valid,
|
|
input [1:0] io_sb_brg_b_bits_resp,
|
|
input io_sb_brg_b_bits_id,
|
|
input io_sb_brg_ar_ready,
|
|
output io_sb_brg_ar_valid,
|
|
output io_sb_brg_ar_bits_id,
|
|
output [31:0] io_sb_brg_ar_bits_addr,
|
|
output [3:0] io_sb_brg_ar_bits_region,
|
|
output [7:0] io_sb_brg_ar_bits_len,
|
|
output [2:0] io_sb_brg_ar_bits_size,
|
|
output [1:0] io_sb_brg_ar_bits_burst,
|
|
output io_sb_brg_ar_bits_lock,
|
|
output [3:0] io_sb_brg_ar_bits_cache,
|
|
output [2:0] io_sb_brg_ar_bits_prot,
|
|
output [3:0] io_sb_brg_ar_bits_qos,
|
|
output io_sb_brg_r_ready,
|
|
input io_sb_brg_r_valid,
|
|
input io_sb_brg_r_bits_id,
|
|
input [63:0] io_sb_brg_r_bits_data,
|
|
input [1:0] io_sb_brg_r_bits_resp,
|
|
input io_sb_brg_r_bits_last,
|
|
output io_dma_brg_aw_ready,
|
|
input io_dma_brg_aw_valid,
|
|
input io_dma_brg_aw_bits_id,
|
|
input [31:0] io_dma_brg_aw_bits_addr,
|
|
input [3:0] io_dma_brg_aw_bits_region,
|
|
input [7:0] io_dma_brg_aw_bits_len,
|
|
input [2:0] io_dma_brg_aw_bits_size,
|
|
input [1:0] io_dma_brg_aw_bits_burst,
|
|
input io_dma_brg_aw_bits_lock,
|
|
input [3:0] io_dma_brg_aw_bits_cache,
|
|
input [2:0] io_dma_brg_aw_bits_prot,
|
|
input [3:0] io_dma_brg_aw_bits_qos,
|
|
output io_dma_brg_w_ready,
|
|
input io_dma_brg_w_valid,
|
|
input [63:0] io_dma_brg_w_bits_data,
|
|
input [7:0] io_dma_brg_w_bits_strb,
|
|
input io_dma_brg_w_bits_last,
|
|
input io_dma_brg_b_ready,
|
|
output io_dma_brg_b_valid,
|
|
output [1:0] io_dma_brg_b_bits_resp,
|
|
output io_dma_brg_b_bits_id,
|
|
output io_dma_brg_ar_ready,
|
|
input io_dma_brg_ar_valid,
|
|
input io_dma_brg_ar_bits_id,
|
|
input [31:0] io_dma_brg_ar_bits_addr,
|
|
input [3:0] io_dma_brg_ar_bits_region,
|
|
input [7:0] io_dma_brg_ar_bits_len,
|
|
input [2:0] io_dma_brg_ar_bits_size,
|
|
input [1:0] io_dma_brg_ar_bits_burst,
|
|
input io_dma_brg_ar_bits_lock,
|
|
input [3:0] io_dma_brg_ar_bits_cache,
|
|
input [2:0] io_dma_brg_ar_bits_prot,
|
|
input [3:0] io_dma_brg_ar_bits_qos,
|
|
input io_dma_brg_r_ready,
|
|
output io_dma_brg_r_valid,
|
|
output io_dma_brg_r_bits_id,
|
|
output [63:0] io_dma_brg_r_bits_data,
|
|
output [1:0] io_dma_brg_r_bits_resp,
|
|
output io_dma_brg_r_bits_last,
|
|
input io_lsu_bus_clk_en,
|
|
input io_ifu_bus_clk_en,
|
|
input io_dbg_bus_clk_en,
|
|
input io_dma_bus_clk_en,
|
|
input io_timer_int,
|
|
input io_soft_int,
|
|
input [30:0] io_extintsrc_req,
|
|
output io_dec_tlu_perfcnt0,
|
|
output io_dec_tlu_perfcnt1,
|
|
output io_dec_tlu_perfcnt2,
|
|
output io_dec_tlu_perfcnt3,
|
|
input io_jtag_tck,
|
|
input io_jtag_tms,
|
|
input io_jtag_tdi,
|
|
input io_jtag_trst_n,
|
|
output io_jtag_tdo,
|
|
input [27:0] io_core_id,
|
|
input io_mpc_debug_halt_req,
|
|
input io_mpc_debug_run_req,
|
|
input io_mpc_reset_run_req,
|
|
output io_mpc_debug_halt_ack,
|
|
output io_mpc_debug_run_ack,
|
|
output io_debug_brkpt_status,
|
|
input io_i_cpu_halt_req,
|
|
input io_i_cpu_run_req,
|
|
output io_o_cpu_halt_ack,
|
|
output io_o_cpu_halt_status,
|
|
output io_o_debug_mode_status,
|
|
output io_o_cpu_run_ack,
|
|
input io_mbist_mode,
|
|
input [3:0] io_dccm_ext_in_pkt_TEST1,
|
|
input [3:0] io_dccm_ext_in_pkt_RME,
|
|
input [3:0] io_dccm_ext_in_pkt_RM_0,
|
|
input [3:0] io_dccm_ext_in_pkt_RM_1,
|
|
input [3:0] io_dccm_ext_in_pkt_RM_2,
|
|
input [3:0] io_dccm_ext_in_pkt_RM_3,
|
|
input [3:0] io_dccm_ext_in_pkt_LS,
|
|
input [3:0] io_dccm_ext_in_pkt_DS,
|
|
input [3:0] io_dccm_ext_in_pkt_SD,
|
|
input [3:0] io_dccm_ext_in_pkt_TEST_RNM,
|
|
input [3:0] io_dccm_ext_in_pkt_BC1,
|
|
input [3:0] io_dccm_ext_in_pkt_BC2,
|
|
input [3:0] io_iccm_ext_in_pkt_TEST1,
|
|
input [3:0] io_iccm_ext_in_pkt_RME,
|
|
input [3:0] io_iccm_ext_in_pkt_RM_0,
|
|
input [3:0] io_iccm_ext_in_pkt_RM_1,
|
|
input [3:0] io_iccm_ext_in_pkt_RM_2,
|
|
input [3:0] io_iccm_ext_in_pkt_RM_3,
|
|
input [3:0] io_iccm_ext_in_pkt_LS,
|
|
input [3:0] io_iccm_ext_in_pkt_DS,
|
|
input [3:0] io_iccm_ext_in_pkt_SD,
|
|
input [3:0] io_iccm_ext_in_pkt_TEST_RNM,
|
|
input [3:0] io_iccm_ext_in_pkt_BC1,
|
|
input [3:0] io_iccm_ext_in_pkt_BC2,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_TEST1,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_RME,
|
|
input [3:0] io_ic_data_ext_in_pkt_0_RM_0,
|
|
input [3:0] io_ic_data_ext_in_pkt_0_RM_1,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_LS,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_DS,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_SD,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_TEST_RNM,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_BC1,
|
|
input [1:0] io_ic_data_ext_in_pkt_0_BC2,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_TEST1,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_RME,
|
|
input [3:0] io_ic_data_ext_in_pkt_1_RM_0,
|
|
input [3:0] io_ic_data_ext_in_pkt_1_RM_1,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_LS,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_DS,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_SD,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_TEST_RNM,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_BC1,
|
|
input [1:0] io_ic_data_ext_in_pkt_1_BC2,
|
|
input [1:0] io_ic_tag_ext_in_pkt_TEST1,
|
|
input [1:0] io_ic_tag_ext_in_pkt_RME,
|
|
input [3:0] io_ic_tag_ext_in_pkt_RM_0,
|
|
input [3:0] io_ic_tag_ext_in_pkt_RM_1,
|
|
input [1:0] io_ic_tag_ext_in_pkt_LS,
|
|
input [1:0] io_ic_tag_ext_in_pkt_DS,
|
|
input [1:0] io_ic_tag_ext_in_pkt_SD,
|
|
input [1:0] io_ic_tag_ext_in_pkt_TEST_RNM,
|
|
input [1:0] io_ic_tag_ext_in_pkt_BC1,
|
|
input [1:0] io_ic_tag_ext_in_pkt_BC2,
|
|
output io_rv_trace_pkt_rv_i_valid_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_insn_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_address_ip,
|
|
output io_rv_trace_pkt_rv_i_exception_ip,
|
|
output [4:0] io_rv_trace_pkt_rv_i_ecause_ip,
|
|
output io_rv_trace_pkt_rv_i_interrupt_ip,
|
|
output [31:0] io_rv_trace_pkt_rv_i_tval_ip,
|
|
input io_scan_mode
|
|
);
|
|
wire mem_clk; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_rst_l; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_dccm_clk_override; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_icm_clk_override; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_dccm_wren; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_dccm_rden; // @[quasar_wrapper.scala 68:19]
|
|
wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 68:19]
|
|
wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 68:19]
|
|
wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 68:19]
|
|
wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 68:19]
|
|
wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 68:19]
|
|
wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 68:19]
|
|
wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 68:19]
|
|
wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_RME; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_RM_2; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_RM_3; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_LS; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_DS; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_SD; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_BC1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_dccm_ext_in_pkt_BC2; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_RME; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_RM_2; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_RM_3; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_LS; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_DS; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_SD; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_BC1; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_iccm_ext_in_pkt_BC2; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_TEST1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_RME; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_data_ext_in_pkt_0_RM_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_data_ext_in_pkt_0_RM_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_LS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_DS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_SD; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_TEST_RNM; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_BC1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_0_BC2; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_TEST1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_RME; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_data_ext_in_pkt_1_RM_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_data_ext_in_pkt_1_RM_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_LS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_DS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_SD; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_TEST_RNM; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_BC1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_data_ext_in_pkt_1_BC2; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_RME; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_tag_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [3:0] mem_ic_tag_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_LS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_DS; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_SD; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_BC1; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_ext_in_pkt_BC2; // @[quasar_wrapper.scala 68:19]
|
|
wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_iccm_correction_state; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_iccm_wren; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_iccm_rden; // @[quasar_wrapper.scala 68:19]
|
|
wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 68:19]
|
|
wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 68:19]
|
|
wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_rd_en; // @[quasar_wrapper.scala 68:19]
|
|
wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 68:19]
|
|
wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 68:19]
|
|
wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 68:19]
|
|
wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_tag_perr; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 68:19]
|
|
wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 68:19]
|
|
wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 68:19]
|
|
wire mem_scan_mode; // @[quasar_wrapper.scala 68:19]
|
|
wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_tck; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_tms; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 69:27]
|
|
wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 69:27]
|
|
wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 69:27]
|
|
wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 69:27]
|
|
wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 69:27]
|
|
wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 69:27]
|
|
wire core_clock; // @[quasar_wrapper.scala 70:20]
|
|
wire core_reset; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_active_l2clk; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_free_l2clk; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 70:20]
|
|
wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_nmi_int; // @[quasar_wrapper.scala 70:20]
|
|
wire [30:0] core_io_nmi_vec; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_core_rst_l; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire [4:0] core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dccm_clk_override; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_icm_clk_override; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_i_cpu_halt_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_i_cpu_run_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_o_debug_mode_status; // @[quasar_wrapper.scala 70:20]
|
|
wire [27:0] core_io_core_id; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_mpc_debug_run_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_mpc_reset_run_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_debug_brkpt_status; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dccm_wren; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dccm_rden; // @[quasar_wrapper.scala 70:20]
|
|
wire [15:0] core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 70:20]
|
|
wire [15:0] core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 70:20]
|
|
wire [15:0] core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 70:20]
|
|
wire [15:0] core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 70:20]
|
|
wire [38:0] core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 70:20]
|
|
wire [38:0] core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 70:20]
|
|
wire [38:0] core_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 70:20]
|
|
wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 70:20]
|
|
wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ic_wr_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_rd_en; // @[quasar_wrapper.scala 70:20]
|
|
wire [70:0] core_io_ic_wr_data_0; // @[quasar_wrapper.scala 70:20]
|
|
wire [70:0] core_io_ic_wr_data_1; // @[quasar_wrapper.scala 70:20]
|
|
wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [70:0] core_io_ic_debug_rd_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [25:0] core_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ic_eccerr; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ic_rd_hit; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_tag_perr; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 70:20]
|
|
wire [1:0] core_io_ic_debug_way; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_ic_premux_data; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [14:0] core_io_iccm_rw_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_iccm_correction_state; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_iccm_wren; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_iccm_rden; // @[quasar_wrapper.scala 70:20]
|
|
wire [2:0] core_io_iccm_wr_size; // @[quasar_wrapper.scala 70:20]
|
|
wire [77:0] core_io_iccm_wr_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [63:0] core_io_iccm_rd_data; // @[quasar_wrapper.scala 70:20]
|
|
wire [77:0] core_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dma_bus_clk_en; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dmi_reg_en; // @[quasar_wrapper.scala 70:20]
|
|
wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 70:20]
|
|
wire [31:0] core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 70:20]
|
|
wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_timer_int; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_soft_int; // @[quasar_wrapper.scala 70:20]
|
|
wire core_io_scan_mode; // @[quasar_wrapper.scala 70:20]
|
|
mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICACHE_LN_SZ(64), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_TAG_NUM_BYPASS_WIDTH(2), .ICACHE_TAG_NUM_BYPASS(2), .ICACHE_BANK_LO(3), .ICACHE_TAG_BYPASS_ENABLE(1), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .DCCM_WIDTH_BITS(2), .ICACHE_DATA_INDEX_LO(4), .ICACHE_NUM_BYPASS_WIDTH(2), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICACHE_BYPASS_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(1), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 68:19]
|
|
.clk(mem_clk),
|
|
.rst_l(mem_rst_l),
|
|
.dccm_clk_override(mem_dccm_clk_override),
|
|
.icm_clk_override(mem_icm_clk_override),
|
|
.dec_tlu_core_ecc_disable(mem_dec_tlu_core_ecc_disable),
|
|
.dccm_wren(mem_dccm_wren),
|
|
.dccm_rden(mem_dccm_rden),
|
|
.dccm_wr_addr_lo(mem_dccm_wr_addr_lo),
|
|
.dccm_wr_addr_hi(mem_dccm_wr_addr_hi),
|
|
.dccm_rd_addr_lo(mem_dccm_rd_addr_lo),
|
|
.dccm_rd_addr_hi(mem_dccm_rd_addr_hi),
|
|
.dccm_wr_data_lo(mem_dccm_wr_data_lo),
|
|
.dccm_wr_data_hi(mem_dccm_wr_data_hi),
|
|
.dccm_rd_data_lo(mem_dccm_rd_data_lo),
|
|
.dccm_rd_data_hi(mem_dccm_rd_data_hi),
|
|
.dccm_ext_in_pkt_TEST1(mem_dccm_ext_in_pkt_TEST1),
|
|
.dccm_ext_in_pkt_RME(mem_dccm_ext_in_pkt_RME),
|
|
.dccm_ext_in_pkt_RM_0(mem_dccm_ext_in_pkt_RM_0),
|
|
.dccm_ext_in_pkt_RM_1(mem_dccm_ext_in_pkt_RM_1),
|
|
.dccm_ext_in_pkt_RM_2(mem_dccm_ext_in_pkt_RM_2),
|
|
.dccm_ext_in_pkt_RM_3(mem_dccm_ext_in_pkt_RM_3),
|
|
.dccm_ext_in_pkt_LS(mem_dccm_ext_in_pkt_LS),
|
|
.dccm_ext_in_pkt_DS(mem_dccm_ext_in_pkt_DS),
|
|
.dccm_ext_in_pkt_SD(mem_dccm_ext_in_pkt_SD),
|
|
.dccm_ext_in_pkt_TEST_RNM(mem_dccm_ext_in_pkt_TEST_RNM),
|
|
.dccm_ext_in_pkt_BC1(mem_dccm_ext_in_pkt_BC1),
|
|
.dccm_ext_in_pkt_BC2(mem_dccm_ext_in_pkt_BC2),
|
|
.iccm_ext_in_pkt_TEST1(mem_iccm_ext_in_pkt_TEST1),
|
|
.iccm_ext_in_pkt_RME(mem_iccm_ext_in_pkt_RME),
|
|
.iccm_ext_in_pkt_RM_0(mem_iccm_ext_in_pkt_RM_0),
|
|
.iccm_ext_in_pkt_RM_1(mem_iccm_ext_in_pkt_RM_1),
|
|
.iccm_ext_in_pkt_RM_2(mem_iccm_ext_in_pkt_RM_2),
|
|
.iccm_ext_in_pkt_RM_3(mem_iccm_ext_in_pkt_RM_3),
|
|
.iccm_ext_in_pkt_LS(mem_iccm_ext_in_pkt_LS),
|
|
.iccm_ext_in_pkt_DS(mem_iccm_ext_in_pkt_DS),
|
|
.iccm_ext_in_pkt_SD(mem_iccm_ext_in_pkt_SD),
|
|
.iccm_ext_in_pkt_TEST_RNM(mem_iccm_ext_in_pkt_TEST_RNM),
|
|
.iccm_ext_in_pkt_BC1(mem_iccm_ext_in_pkt_BC1),
|
|
.iccm_ext_in_pkt_BC2(mem_iccm_ext_in_pkt_BC2),
|
|
.ic_data_ext_in_pkt_0_TEST1(mem_ic_data_ext_in_pkt_0_TEST1),
|
|
.ic_data_ext_in_pkt_0_RME(mem_ic_data_ext_in_pkt_0_RME),
|
|
.ic_data_ext_in_pkt_0_RM_0(mem_ic_data_ext_in_pkt_0_RM_0),
|
|
.ic_data_ext_in_pkt_0_RM_1(mem_ic_data_ext_in_pkt_0_RM_1),
|
|
.ic_data_ext_in_pkt_0_LS(mem_ic_data_ext_in_pkt_0_LS),
|
|
.ic_data_ext_in_pkt_0_DS(mem_ic_data_ext_in_pkt_0_DS),
|
|
.ic_data_ext_in_pkt_0_SD(mem_ic_data_ext_in_pkt_0_SD),
|
|
.ic_data_ext_in_pkt_0_TEST_RNM(mem_ic_data_ext_in_pkt_0_TEST_RNM),
|
|
.ic_data_ext_in_pkt_0_BC1(mem_ic_data_ext_in_pkt_0_BC1),
|
|
.ic_data_ext_in_pkt_0_BC2(mem_ic_data_ext_in_pkt_0_BC2),
|
|
.ic_data_ext_in_pkt_1_TEST1(mem_ic_data_ext_in_pkt_1_TEST1),
|
|
.ic_data_ext_in_pkt_1_RME(mem_ic_data_ext_in_pkt_1_RME),
|
|
.ic_data_ext_in_pkt_1_RM_0(mem_ic_data_ext_in_pkt_1_RM_0),
|
|
.ic_data_ext_in_pkt_1_RM_1(mem_ic_data_ext_in_pkt_1_RM_1),
|
|
.ic_data_ext_in_pkt_1_LS(mem_ic_data_ext_in_pkt_1_LS),
|
|
.ic_data_ext_in_pkt_1_DS(mem_ic_data_ext_in_pkt_1_DS),
|
|
.ic_data_ext_in_pkt_1_SD(mem_ic_data_ext_in_pkt_1_SD),
|
|
.ic_data_ext_in_pkt_1_TEST_RNM(mem_ic_data_ext_in_pkt_1_TEST_RNM),
|
|
.ic_data_ext_in_pkt_1_BC1(mem_ic_data_ext_in_pkt_1_BC1),
|
|
.ic_data_ext_in_pkt_1_BC2(mem_ic_data_ext_in_pkt_1_BC2),
|
|
.ic_tag_ext_in_pkt_TEST1(mem_ic_tag_ext_in_pkt_TEST1),
|
|
.ic_tag_ext_in_pkt_RME(mem_ic_tag_ext_in_pkt_RME),
|
|
.ic_tag_ext_in_pkt_RM_0(mem_ic_tag_ext_in_pkt_RM_0),
|
|
.ic_tag_ext_in_pkt_RM_1(mem_ic_tag_ext_in_pkt_RM_1),
|
|
.ic_tag_ext_in_pkt_LS(mem_ic_tag_ext_in_pkt_LS),
|
|
.ic_tag_ext_in_pkt_DS(mem_ic_tag_ext_in_pkt_DS),
|
|
.ic_tag_ext_in_pkt_SD(mem_ic_tag_ext_in_pkt_SD),
|
|
.ic_tag_ext_in_pkt_TEST_RNM(mem_ic_tag_ext_in_pkt_TEST_RNM),
|
|
.ic_tag_ext_in_pkt_BC1(mem_ic_tag_ext_in_pkt_BC1),
|
|
.ic_tag_ext_in_pkt_BC2(mem_ic_tag_ext_in_pkt_BC2),
|
|
.iccm_rw_addr(mem_iccm_rw_addr),
|
|
.iccm_buf_correct_ecc(mem_iccm_buf_correct_ecc),
|
|
.iccm_correction_state(mem_iccm_correction_state),
|
|
.iccm_wren(mem_iccm_wren),
|
|
.iccm_rden(mem_iccm_rden),
|
|
.iccm_wr_size(mem_iccm_wr_size),
|
|
.iccm_wr_data(mem_iccm_wr_data),
|
|
.iccm_rd_data(mem_iccm_rd_data),
|
|
.iccm_rd_data_ecc(mem_iccm_rd_data_ecc),
|
|
.ic_rw_addr(mem_ic_rw_addr),
|
|
.ic_tag_valid(mem_ic_tag_valid),
|
|
.ic_wr_en(mem_ic_wr_en),
|
|
.ic_rd_en(mem_ic_rd_en),
|
|
.ic_wr_data_0(mem_ic_wr_data_0),
|
|
.ic_wr_data_1(mem_ic_wr_data_1),
|
|
.ic_debug_wr_data(mem_ic_debug_wr_data),
|
|
.ic_debug_addr(mem_ic_debug_addr),
|
|
.ic_rd_data(mem_ic_rd_data),
|
|
.ic_debug_rd_data(mem_ic_debug_rd_data),
|
|
.ic_tag_debug_rd_data(mem_ic_tag_debug_rd_data),
|
|
.ic_eccerr(mem_ic_eccerr),
|
|
.ic_parerr(mem_ic_parerr),
|
|
.ic_rd_hit(mem_ic_rd_hit),
|
|
.ic_tag_perr(mem_ic_tag_perr),
|
|
.ic_debug_rd_en(mem_ic_debug_rd_en),
|
|
.ic_debug_wr_en(mem_ic_debug_wr_en),
|
|
.ic_debug_tag_array(mem_ic_debug_tag_array),
|
|
.ic_debug_way(mem_ic_debug_way),
|
|
.ic_premux_data(mem_ic_premux_data),
|
|
.ic_sel_premux_data(mem_ic_sel_premux_data),
|
|
.scan_mode(mem_scan_mode)
|
|
);
|
|
dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 69:27]
|
|
.trst_n(dmi_wrapper_trst_n),
|
|
.tck(dmi_wrapper_tck),
|
|
.tms(dmi_wrapper_tms),
|
|
.tdi(dmi_wrapper_tdi),
|
|
.tdo(dmi_wrapper_tdo),
|
|
.tdoEnable(dmi_wrapper_tdoEnable),
|
|
.core_rst_n(dmi_wrapper_core_rst_n),
|
|
.core_clk(dmi_wrapper_core_clk),
|
|
.jtag_id(dmi_wrapper_jtag_id),
|
|
.rd_data(dmi_wrapper_rd_data),
|
|
.reg_wr_data(dmi_wrapper_reg_wr_data),
|
|
.reg_wr_addr(dmi_wrapper_reg_wr_addr),
|
|
.reg_en(dmi_wrapper_reg_en),
|
|
.reg_wr_en(dmi_wrapper_reg_wr_en),
|
|
.dmi_hard_reset(dmi_wrapper_dmi_hard_reset)
|
|
);
|
|
quasar core ( // @[quasar_wrapper.scala 70:20]
|
|
.clock(core_clock),
|
|
.reset(core_reset),
|
|
.io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready),
|
|
.io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid),
|
|
.io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id),
|
|
.io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr),
|
|
.io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region),
|
|
.io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size),
|
|
.io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache),
|
|
.io_lsu_axi_w_ready(core_io_lsu_axi_w_ready),
|
|
.io_lsu_axi_w_valid(core_io_lsu_axi_w_valid),
|
|
.io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data),
|
|
.io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb),
|
|
.io_lsu_axi_b_valid(core_io_lsu_axi_b_valid),
|
|
.io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp),
|
|
.io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id),
|
|
.io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready),
|
|
.io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid),
|
|
.io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id),
|
|
.io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr),
|
|
.io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region),
|
|
.io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size),
|
|
.io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache),
|
|
.io_lsu_axi_r_valid(core_io_lsu_axi_r_valid),
|
|
.io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id),
|
|
.io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data),
|
|
.io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp),
|
|
.io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready),
|
|
.io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid),
|
|
.io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id),
|
|
.io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr),
|
|
.io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region),
|
|
.io_ifu_axi_r_valid(core_io_ifu_axi_r_valid),
|
|
.io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id),
|
|
.io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data),
|
|
.io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp),
|
|
.io_sb_axi_aw_ready(core_io_sb_axi_aw_ready),
|
|
.io_sb_axi_aw_valid(core_io_sb_axi_aw_valid),
|
|
.io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr),
|
|
.io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region),
|
|
.io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size),
|
|
.io_sb_axi_w_ready(core_io_sb_axi_w_ready),
|
|
.io_sb_axi_w_valid(core_io_sb_axi_w_valid),
|
|
.io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data),
|
|
.io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb),
|
|
.io_sb_axi_b_valid(core_io_sb_axi_b_valid),
|
|
.io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp),
|
|
.io_sb_axi_ar_ready(core_io_sb_axi_ar_ready),
|
|
.io_sb_axi_ar_valid(core_io_sb_axi_ar_valid),
|
|
.io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr),
|
|
.io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region),
|
|
.io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size),
|
|
.io_sb_axi_r_valid(core_io_sb_axi_r_valid),
|
|
.io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data),
|
|
.io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp),
|
|
.io_dma_axi_aw_ready(core_io_dma_axi_aw_ready),
|
|
.io_dma_axi_aw_valid(core_io_dma_axi_aw_valid),
|
|
.io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id),
|
|
.io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr),
|
|
.io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size),
|
|
.io_dma_axi_w_ready(core_io_dma_axi_w_ready),
|
|
.io_dma_axi_w_valid(core_io_dma_axi_w_valid),
|
|
.io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data),
|
|
.io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb),
|
|
.io_dma_axi_b_ready(core_io_dma_axi_b_ready),
|
|
.io_dma_axi_b_valid(core_io_dma_axi_b_valid),
|
|
.io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp),
|
|
.io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id),
|
|
.io_dma_axi_ar_ready(core_io_dma_axi_ar_ready),
|
|
.io_dma_axi_ar_valid(core_io_dma_axi_ar_valid),
|
|
.io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id),
|
|
.io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr),
|
|
.io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size),
|
|
.io_dma_axi_r_ready(core_io_dma_axi_r_ready),
|
|
.io_dma_axi_r_valid(core_io_dma_axi_r_valid),
|
|
.io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id),
|
|
.io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data),
|
|
.io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp),
|
|
.io_active_l2clk(core_io_active_l2clk),
|
|
.io_free_l2clk(core_io_free_l2clk),
|
|
.io_dbg_rst_l(core_io_dbg_rst_l),
|
|
.io_rst_vec(core_io_rst_vec),
|
|
.io_nmi_int(core_io_nmi_int),
|
|
.io_nmi_vec(core_io_nmi_vec),
|
|
.io_core_rst_l(core_io_core_rst_l),
|
|
.io_rv_trace_pkt_rv_i_valid_ip(core_io_rv_trace_pkt_rv_i_valid_ip),
|
|
.io_rv_trace_pkt_rv_i_insn_ip(core_io_rv_trace_pkt_rv_i_insn_ip),
|
|
.io_rv_trace_pkt_rv_i_address_ip(core_io_rv_trace_pkt_rv_i_address_ip),
|
|
.io_rv_trace_pkt_rv_i_exception_ip(core_io_rv_trace_pkt_rv_i_exception_ip),
|
|
.io_rv_trace_pkt_rv_i_ecause_ip(core_io_rv_trace_pkt_rv_i_ecause_ip),
|
|
.io_rv_trace_pkt_rv_i_interrupt_ip(core_io_rv_trace_pkt_rv_i_interrupt_ip),
|
|
.io_rv_trace_pkt_rv_i_tval_ip(core_io_rv_trace_pkt_rv_i_tval_ip),
|
|
.io_dccm_clk_override(core_io_dccm_clk_override),
|
|
.io_icm_clk_override(core_io_icm_clk_override),
|
|
.io_dec_tlu_core_ecc_disable(core_io_dec_tlu_core_ecc_disable),
|
|
.io_i_cpu_halt_req(core_io_i_cpu_halt_req),
|
|
.io_i_cpu_run_req(core_io_i_cpu_run_req),
|
|
.io_o_cpu_halt_ack(core_io_o_cpu_halt_ack),
|
|
.io_o_cpu_halt_status(core_io_o_cpu_halt_status),
|
|
.io_o_cpu_run_ack(core_io_o_cpu_run_ack),
|
|
.io_o_debug_mode_status(core_io_o_debug_mode_status),
|
|
.io_core_id(core_io_core_id),
|
|
.io_mpc_debug_halt_req(core_io_mpc_debug_halt_req),
|
|
.io_mpc_debug_run_req(core_io_mpc_debug_run_req),
|
|
.io_mpc_reset_run_req(core_io_mpc_reset_run_req),
|
|
.io_mpc_debug_halt_ack(core_io_mpc_debug_halt_ack),
|
|
.io_mpc_debug_run_ack(core_io_mpc_debug_run_ack),
|
|
.io_debug_brkpt_status(core_io_debug_brkpt_status),
|
|
.io_dec_tlu_perfcnt0(core_io_dec_tlu_perfcnt0),
|
|
.io_dec_tlu_perfcnt1(core_io_dec_tlu_perfcnt1),
|
|
.io_dec_tlu_perfcnt2(core_io_dec_tlu_perfcnt2),
|
|
.io_dec_tlu_perfcnt3(core_io_dec_tlu_perfcnt3),
|
|
.io_dccm_wren(core_io_dccm_wren),
|
|
.io_dccm_rden(core_io_dccm_rden),
|
|
.io_dccm_wr_addr_lo(core_io_dccm_wr_addr_lo),
|
|
.io_dccm_wr_addr_hi(core_io_dccm_wr_addr_hi),
|
|
.io_dccm_rd_addr_lo(core_io_dccm_rd_addr_lo),
|
|
.io_dccm_rd_addr_hi(core_io_dccm_rd_addr_hi),
|
|
.io_dccm_wr_data_lo(core_io_dccm_wr_data_lo),
|
|
.io_dccm_wr_data_hi(core_io_dccm_wr_data_hi),
|
|
.io_dccm_rd_data_lo(core_io_dccm_rd_data_lo),
|
|
.io_dccm_rd_data_hi(core_io_dccm_rd_data_hi),
|
|
.io_ic_rw_addr(core_io_ic_rw_addr),
|
|
.io_ic_tag_valid(core_io_ic_tag_valid),
|
|
.io_ic_wr_en(core_io_ic_wr_en),
|
|
.io_ic_rd_en(core_io_ic_rd_en),
|
|
.io_ic_wr_data_0(core_io_ic_wr_data_0),
|
|
.io_ic_wr_data_1(core_io_ic_wr_data_1),
|
|
.io_ic_debug_wr_data(core_io_ic_debug_wr_data),
|
|
.io_ic_debug_addr(core_io_ic_debug_addr),
|
|
.io_ic_rd_data(core_io_ic_rd_data),
|
|
.io_ic_debug_rd_data(core_io_ic_debug_rd_data),
|
|
.io_ic_tag_debug_rd_data(core_io_ic_tag_debug_rd_data),
|
|
.io_ic_eccerr(core_io_ic_eccerr),
|
|
.io_ic_rd_hit(core_io_ic_rd_hit),
|
|
.io_ic_tag_perr(core_io_ic_tag_perr),
|
|
.io_ic_debug_rd_en(core_io_ic_debug_rd_en),
|
|
.io_ic_debug_wr_en(core_io_ic_debug_wr_en),
|
|
.io_ic_debug_tag_array(core_io_ic_debug_tag_array),
|
|
.io_ic_debug_way(core_io_ic_debug_way),
|
|
.io_ic_premux_data(core_io_ic_premux_data),
|
|
.io_ic_sel_premux_data(core_io_ic_sel_premux_data),
|
|
.io_iccm_rw_addr(core_io_iccm_rw_addr),
|
|
.io_iccm_buf_correct_ecc(core_io_iccm_buf_correct_ecc),
|
|
.io_iccm_correction_state(core_io_iccm_correction_state),
|
|
.io_iccm_wren(core_io_iccm_wren),
|
|
.io_iccm_rden(core_io_iccm_rden),
|
|
.io_iccm_wr_size(core_io_iccm_wr_size),
|
|
.io_iccm_wr_data(core_io_iccm_wr_data),
|
|
.io_iccm_rd_data(core_io_iccm_rd_data),
|
|
.io_iccm_rd_data_ecc(core_io_iccm_rd_data_ecc),
|
|
.io_lsu_bus_clk_en(core_io_lsu_bus_clk_en),
|
|
.io_ifu_bus_clk_en(core_io_ifu_bus_clk_en),
|
|
.io_dbg_bus_clk_en(core_io_dbg_bus_clk_en),
|
|
.io_dma_bus_clk_en(core_io_dma_bus_clk_en),
|
|
.io_dmi_reg_en(core_io_dmi_reg_en),
|
|
.io_dmi_reg_addr(core_io_dmi_reg_addr),
|
|
.io_dmi_reg_wr_en(core_io_dmi_reg_wr_en),
|
|
.io_dmi_reg_wdata(core_io_dmi_reg_wdata),
|
|
.io_dmi_reg_rdata(core_io_dmi_reg_rdata),
|
|
.io_extintsrc_req(core_io_extintsrc_req),
|
|
.io_timer_int(core_io_timer_int),
|
|
.io_soft_int(core_io_soft_int),
|
|
.io_scan_mode(core_io_scan_mode)
|
|
);
|
|
assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_prot = 3'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_prot = 3'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 111:21]
|
|
assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 111:21]
|
|
assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_prot = 3'h5; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 112:21]
|
|
assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 112:21]
|
|
assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_prot = 3'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_prot = 3'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 113:21]
|
|
assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 113:21]
|
|
assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 114:21]
|
|
assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 166:23]
|
|
assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 167:23]
|
|
assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 168:23]
|
|
assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 169:23]
|
|
assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 85:15]
|
|
assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 162:25]
|
|
assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 163:24]
|
|
assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 164:25]
|
|
assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 157:21]
|
|
assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 158:24]
|
|
assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 160:26]
|
|
assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 159:20]
|
|
assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 154:19]
|
|
assign mem_clk = core_io_active_l2clk; // @[quasar_wrapper.scala 93:14]
|
|
assign mem_rst_l = core_io_core_rst_l; // @[quasar_wrapper.scala 92:16]
|
|
assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 88:28]
|
|
assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 89:27]
|
|
assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 90:35]
|
|
assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 91:15]
|
|
assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 91:15]
|
|
assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 91:15]
|
|
assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 91:15]
|
|
assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 91:15]
|
|
assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 91:15]
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assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 91:15]
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assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 91:15]
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assign mem_dccm_ext_in_pkt_TEST1 = io_dccm_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_RME = io_dccm_ext_in_pkt_RME; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_RM_0 = io_dccm_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_RM_1 = io_dccm_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_RM_2 = io_dccm_ext_in_pkt_RM_2; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_RM_3 = io_dccm_ext_in_pkt_RM_3; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_LS = io_dccm_ext_in_pkt_LS; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_DS = io_dccm_ext_in_pkt_DS; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_SD = io_dccm_ext_in_pkt_SD; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_TEST_RNM = io_dccm_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_BC1 = io_dccm_ext_in_pkt_BC1; // @[quasar_wrapper.scala 95:26]
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assign mem_dccm_ext_in_pkt_BC2 = io_dccm_ext_in_pkt_BC2; // @[quasar_wrapper.scala 95:26]
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assign mem_iccm_ext_in_pkt_TEST1 = io_iccm_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_RME = io_iccm_ext_in_pkt_RME; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_RM_0 = io_iccm_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_RM_1 = io_iccm_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_RM_2 = io_iccm_ext_in_pkt_RM_2; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_RM_3 = io_iccm_ext_in_pkt_RM_3; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_LS = io_iccm_ext_in_pkt_LS; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_DS = io_iccm_ext_in_pkt_DS; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_SD = io_iccm_ext_in_pkt_SD; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_TEST_RNM = io_iccm_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_BC1 = io_iccm_ext_in_pkt_BC1; // @[quasar_wrapper.scala 96:26]
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assign mem_iccm_ext_in_pkt_BC2 = io_iccm_ext_in_pkt_BC2; // @[quasar_wrapper.scala 96:26]
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assign mem_ic_data_ext_in_pkt_0_TEST1 = io_ic_data_ext_in_pkt_0_TEST1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_RME = io_ic_data_ext_in_pkt_0_RME; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_RM_0 = io_ic_data_ext_in_pkt_0_RM_0; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_RM_1 = io_ic_data_ext_in_pkt_0_RM_1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_LS = io_ic_data_ext_in_pkt_0_LS; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_DS = io_ic_data_ext_in_pkt_0_DS; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_SD = io_ic_data_ext_in_pkt_0_SD; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_TEST_RNM = io_ic_data_ext_in_pkt_0_TEST_RNM; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_BC1 = io_ic_data_ext_in_pkt_0_BC1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_0_BC2 = io_ic_data_ext_in_pkt_0_BC2; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_TEST1 = io_ic_data_ext_in_pkt_1_TEST1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_RME = io_ic_data_ext_in_pkt_1_RME; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_RM_0 = io_ic_data_ext_in_pkt_1_RM_0; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_RM_1 = io_ic_data_ext_in_pkt_1_RM_1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_LS = io_ic_data_ext_in_pkt_1_LS; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_DS = io_ic_data_ext_in_pkt_1_DS; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_SD = io_ic_data_ext_in_pkt_1_SD; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_TEST_RNM = io_ic_data_ext_in_pkt_1_TEST_RNM; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_BC1 = io_ic_data_ext_in_pkt_1_BC1; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_data_ext_in_pkt_1_BC2 = io_ic_data_ext_in_pkt_1_BC2; // @[quasar_wrapper.scala 97:29]
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assign mem_ic_tag_ext_in_pkt_TEST1 = io_ic_tag_ext_in_pkt_TEST1; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_RME = io_ic_tag_ext_in_pkt_RME; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_RM_0 = io_ic_tag_ext_in_pkt_RM_0; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_RM_1 = io_ic_tag_ext_in_pkt_RM_1; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_LS = io_ic_tag_ext_in_pkt_LS; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_DS = io_ic_tag_ext_in_pkt_DS; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_SD = io_ic_tag_ext_in_pkt_SD; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_TEST_RNM = io_ic_tag_ext_in_pkt_TEST_RNM; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_BC1 = io_ic_tag_ext_in_pkt_BC1; // @[quasar_wrapper.scala 98:28]
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assign mem_ic_tag_ext_in_pkt_BC2 = io_ic_tag_ext_in_pkt_BC2; // @[quasar_wrapper.scala 98:28]
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assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 102:16]
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assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 102:16]
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assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 101:14]
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assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 101:14]
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assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 94:20]
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assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 72:25]
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assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 73:22]
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assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 74:22]
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assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 75:22]
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assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 79:29]
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assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 76:27]
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assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 77:26]
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assign dmi_wrapper_rd_data = core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 78:26]
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assign core_clock = clock;
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assign core_reset = reset;
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assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 111:21]
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assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 111:21]
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assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 112:21]
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assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 112:21]
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assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 112:21]
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assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 112:21]
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assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 112:21]
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assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 113:21]
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assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 113:21]
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assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 113:21]
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assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 113:21]
|
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assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 113:21]
|
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assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 113:21]
|
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assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 113:21]
|
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assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 113:21]
|
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assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 114:21]
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assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 114:21]
|
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assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 114:21]
|
|
assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 100:21 quasar_wrapper.scala 128:21]
|
|
assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 129:19]
|
|
assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 130:19]
|
|
assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 131:19]
|
|
assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 134:26]
|
|
assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 135:25]
|
|
assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 136:19]
|
|
assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 139:30]
|
|
assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 140:29]
|
|
assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 141:29]
|
|
assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 91:15]
|
|
assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 91:15]
|
|
assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 101:14]
|
|
assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 102:16]
|
|
assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 102:16]
|
|
assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 143:26]
|
|
assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 144:26]
|
|
assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 145:26]
|
|
assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 146:26]
|
|
assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 82:22]
|
|
assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 81:24]
|
|
assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 83:25]
|
|
assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 80:25]
|
|
assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 150:25]
|
|
assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 148:21]
|
|
assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 149:20]
|
|
assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 71:21]
|
|
endmodule
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