13675 lines
968 KiB
Plaintext
13675 lines
968 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_mem_ctl :
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extmodule TEC_RV_ICG :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[el2_lib.scala 452:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
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clkhdr.EN <= io.en @[el2_lib.scala 455:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
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extmodule TEC_RV_ICG_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 452:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
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clkhdr.EN <= io.en @[el2_lib.scala 455:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
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extmodule TEC_RV_ICG_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 452:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
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clkhdr.EN <= io.en @[el2_lib.scala 455:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
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extmodule TEC_RV_ICG_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 452:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
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clkhdr.EN <= io.en @[el2_lib.scala 455:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
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module el2_ifu_mem_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, flip ifu_axi_arready : UInt<1>, flip ifu_axi_rvalid : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, ifu_axi_rready : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
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io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:21]
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io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
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io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:20]
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io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:21]
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io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:21]
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io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:20]
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io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:21]
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io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:23]
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io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:19]
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io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:22]
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io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:20]
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io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:22]
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io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:20]
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io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:21]
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io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:21]
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io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
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io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:21]
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io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:21]
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io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:22]
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io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:20]
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wire iccm_single_ecc_error : UInt<2>
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iccm_single_ecc_error <= UInt<1>("h00")
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wire ifc_fetch_req_f : UInt<1>
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ifc_fetch_req_f <= UInt<1>("h00")
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wire miss_pending : UInt<1>
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miss_pending <= UInt<1>("h00")
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wire scnd_miss_req : UInt<1>
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scnd_miss_req <= UInt<1>("h00")
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wire dma_iccm_req_f : UInt<1>
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dma_iccm_req_f <= UInt<1>("h00")
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wire iccm_correct_ecc : UInt<1>
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iccm_correct_ecc <= UInt<1>("h00")
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wire perr_state : UInt<3>
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perr_state <= UInt<1>("h00")
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wire err_stop_state : UInt<2>
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err_stop_state <= UInt<1>("h00")
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wire err_stop_fetch : UInt<1>
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err_stop_fetch <= UInt<1>("h00")
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wire miss_state : UInt<3>
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miss_state <= UInt<1>("h00")
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wire miss_nxtstate : UInt<3>
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miss_nxtstate <= UInt<1>("h00")
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wire miss_state_en : UInt<1>
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miss_state_en <= UInt<1>("h00")
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wire ifu_bus_rsp_valid : UInt<1>
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ifu_bus_rsp_valid <= UInt<1>("h00")
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wire bus_ifu_bus_clk_en : UInt<1>
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bus_ifu_bus_clk_en <= UInt<1>("h00")
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wire ifu_bus_rsp_ready : UInt<1>
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ifu_bus_rsp_ready <= UInt<1>("h00")
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wire uncacheable_miss_ff : UInt<1>
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uncacheable_miss_ff <= UInt<1>("h00")
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wire ic_act_miss_f : UInt<1>
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ic_act_miss_f <= UInt<1>("h00")
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wire ic_byp_hit_f : UInt<1>
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ic_byp_hit_f <= UInt<1>("h00")
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wire bus_new_data_beat_count : UInt<3>
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bus_new_data_beat_count <= UInt<1>("h00")
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wire bus_ifu_wr_en_ff : UInt<1>
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bus_ifu_wr_en_ff <= UInt<1>("h00")
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wire last_beat : UInt<1>
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last_beat <= UInt<1>("h00")
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wire last_data_recieved_ff : UInt<1>
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last_data_recieved_ff <= UInt<1>("h00")
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wire stream_eol_f : UInt<1>
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stream_eol_f <= UInt<1>("h00")
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wire ic_miss_under_miss_f : UInt<1>
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ic_miss_under_miss_f <= UInt<1>("h00")
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wire ic_ignore_2nd_miss_f : UInt<1>
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ic_ignore_2nd_miss_f <= UInt<1>("h00")
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wire ic_debug_rd_en_ff : UInt<1>
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ic_debug_rd_en_ff <= UInt<1>("h00")
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inst rvclkhdr of rvclkhdr @[el2_lib.scala 461:22]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[el2_lib.scala 462:17]
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rvclkhdr.io.en <= ic_debug_rd_en_ff @[el2_lib.scala 463:16]
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rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23]
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reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 185:30]
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flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 185:30]
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node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 186:53]
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node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 186:71]
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node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 186:86]
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node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 186:107]
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node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 187:42]
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inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 461:22]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[el2_lib.scala 462:17]
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rvclkhdr_1.io.en <= debug_c1_clken @[el2_lib.scala 463:16]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23]
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inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 461:22]
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rvclkhdr_2.clock <= clock
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rvclkhdr_2.reset <= reset
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rvclkhdr_2.io.clk <= clock @[el2_lib.scala 462:17]
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rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[el2_lib.scala 463:16]
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rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23]
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node _T_3 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 190:52]
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node _T_4 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 190:78]
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node _T_5 = and(_T_3, _T_4) @[el2_ifu_mem_ctl.scala 190:55]
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io.iccm_dma_sb_error <= _T_5 @[el2_ifu_mem_ctl.scala 190:24]
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node _T_6 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 191:57]
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io.ifu_async_error_start <= _T_6 @[el2_ifu_mem_ctl.scala 191:28]
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node _T_7 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 192:54]
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node _T_8 = or(iccm_correct_ecc, _T_7) @[el2_ifu_mem_ctl.scala 192:40]
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node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 192:90]
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node _T_10 = or(_T_8, _T_9) @[el2_ifu_mem_ctl.scala 192:72]
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node _T_11 = or(_T_10, err_stop_fetch) @[el2_ifu_mem_ctl.scala 192:112]
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node _T_12 = or(_T_11, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 192:129]
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io.ic_dma_active <= _T_12 @[el2_ifu_mem_ctl.scala 192:20]
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node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 194:44]
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node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 194:65]
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node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 194:112]
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node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 194:85]
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node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 195:5]
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node _T_18 = and(_T_16, _T_17) @[el2_ifu_mem_ctl.scala 194:118]
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node _T_19 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 195:41]
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node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 195:73]
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node _T_21 = or(_T_19, _T_20) @[el2_ifu_mem_ctl.scala 195:57]
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node _T_22 = and(_T_18, _T_21) @[el2_ifu_mem_ctl.scala 195:26]
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node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 195:93]
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node scnd_miss_req_in = and(_T_22, _T_23) @[el2_ifu_mem_ctl.scala 195:91]
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node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 197:52]
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node _T_24 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
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when _T_24 : @[Conditional.scala 40:58]
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node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:45]
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node _T_26 = and(ic_act_miss_f, _T_25) @[el2_ifu_mem_ctl.scala 201:43]
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node _T_27 = bits(_T_26, 0, 0) @[el2_ifu_mem_ctl.scala 201:66]
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node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 201:27]
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miss_nxtstate <= _T_28 @[el2_ifu_mem_ctl.scala 201:21]
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node _T_29 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:40]
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node _T_30 = and(ic_act_miss_f, _T_29) @[el2_ifu_mem_ctl.scala 202:38]
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miss_state_en <= _T_30 @[el2_ifu_mem_ctl.scala 202:21]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_31 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
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when _T_31 : @[Conditional.scala 39:67]
|
|
node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 205:113]
|
|
node _T_33 = or(last_data_recieved_ff, _T_32) @[el2_ifu_mem_ctl.scala 205:93]
|
|
node _T_34 = and(ic_byp_hit_f, _T_33) @[el2_ifu_mem_ctl.scala 205:67]
|
|
node _T_35 = and(_T_34, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 205:127]
|
|
node _T_36 = or(io.dec_tlu_force_halt, _T_35) @[el2_ifu_mem_ctl.scala 205:51]
|
|
node _T_37 = bits(_T_36, 0, 0) @[el2_ifu_mem_ctl.scala 205:152]
|
|
node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:30]
|
|
node _T_39 = and(ic_byp_hit_f, _T_38) @[el2_ifu_mem_ctl.scala 206:27]
|
|
node _T_40 = and(_T_39, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 206:53]
|
|
node _T_41 = bits(_T_40, 0, 0) @[el2_ifu_mem_ctl.scala 206:77]
|
|
node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:16]
|
|
node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:32]
|
|
node _T_44 = and(_T_42, _T_43) @[el2_ifu_mem_ctl.scala 207:30]
|
|
node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 207:72]
|
|
node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 207:52]
|
|
node _T_47 = and(_T_46, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 207:85]
|
|
node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_mem_ctl.scala 207:109]
|
|
node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 208:36]
|
|
node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 208:51]
|
|
node _T_51 = and(_T_49, _T_50) @[el2_ifu_mem_ctl.scala 208:49]
|
|
node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_mem_ctl.scala 208:73]
|
|
node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:35]
|
|
node _T_54 = and(ic_byp_hit_f, _T_53) @[el2_ifu_mem_ctl.scala 209:33]
|
|
node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 209:76]
|
|
node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:57]
|
|
node _T_57 = and(_T_54, _T_56) @[el2_ifu_mem_ctl.scala 209:55]
|
|
node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:91]
|
|
node _T_59 = and(_T_57, _T_58) @[el2_ifu_mem_ctl.scala 209:89]
|
|
node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:115]
|
|
node _T_61 = and(_T_59, _T_60) @[el2_ifu_mem_ctl.scala 209:113]
|
|
node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_mem_ctl.scala 209:137]
|
|
node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:41]
|
|
node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[el2_ifu_mem_ctl.scala 210:39]
|
|
node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 210:82]
|
|
node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:63]
|
|
node _T_67 = and(_T_64, _T_66) @[el2_ifu_mem_ctl.scala 210:61]
|
|
node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:97]
|
|
node _T_69 = and(_T_67, _T_68) @[el2_ifu_mem_ctl.scala 210:95]
|
|
node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:121]
|
|
node _T_71 = and(_T_69, _T_70) @[el2_ifu_mem_ctl.scala 210:119]
|
|
node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_mem_ctl.scala 210:143]
|
|
node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:22]
|
|
node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:40]
|
|
node _T_75 = and(_T_73, _T_74) @[el2_ifu_mem_ctl.scala 211:37]
|
|
node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 211:81]
|
|
node _T_77 = and(_T_75, _T_76) @[el2_ifu_mem_ctl.scala 211:60]
|
|
node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:102]
|
|
node _T_79 = and(_T_77, _T_78) @[el2_ifu_mem_ctl.scala 211:100]
|
|
node _T_80 = bits(_T_79, 0, 0) @[el2_ifu_mem_ctl.scala 211:124]
|
|
node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 212:44]
|
|
node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 212:89]
|
|
node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:70]
|
|
node _T_84 = and(_T_81, _T_83) @[el2_ifu_mem_ctl.scala 212:68]
|
|
node _T_85 = bits(_T_84, 0, 0) @[el2_ifu_mem_ctl.scala 212:103]
|
|
node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 212:22]
|
|
node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[el2_ifu_mem_ctl.scala 211:20]
|
|
node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[el2_ifu_mem_ctl.scala 210:20]
|
|
node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 209:18]
|
|
node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[el2_ifu_mem_ctl.scala 208:16]
|
|
node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[el2_ifu_mem_ctl.scala 207:14]
|
|
node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[el2_ifu_mem_ctl.scala 206:12]
|
|
node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[el2_ifu_mem_ctl.scala 205:27]
|
|
miss_nxtstate <= _T_93 @[el2_ifu_mem_ctl.scala 205:21]
|
|
node _T_94 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 213:46]
|
|
node _T_95 = or(_T_94, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 213:67]
|
|
node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 213:82]
|
|
node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 213:125]
|
|
node _T_98 = or(_T_96, _T_97) @[el2_ifu_mem_ctl.scala 213:105]
|
|
node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 213:160]
|
|
node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[el2_ifu_mem_ctl.scala 213:158]
|
|
node _T_101 = or(_T_98, _T_100) @[el2_ifu_mem_ctl.scala 213:138]
|
|
miss_state_en <= _T_101 @[el2_ifu_mem_ctl.scala 213:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_102 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_102 : @[Conditional.scala 39:67]
|
|
miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 216:21]
|
|
node _T_103 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 217:43]
|
|
node _T_104 = or(_T_103, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 217:59]
|
|
node _T_105 = or(_T_104, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 217:74]
|
|
miss_state_en <= _T_105 @[el2_ifu_mem_ctl.scala 217:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_106 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_106 : @[Conditional.scala 39:67]
|
|
node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 220:49]
|
|
node _T_108 = or(_T_107, stream_eol_f) @[el2_ifu_mem_ctl.scala 220:72]
|
|
node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 220:108]
|
|
node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 220:89]
|
|
node _T_111 = and(_T_108, _T_110) @[el2_ifu_mem_ctl.scala 220:87]
|
|
node _T_112 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 220:124]
|
|
node _T_113 = and(_T_111, _T_112) @[el2_ifu_mem_ctl.scala 220:122]
|
|
node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_mem_ctl.scala 220:148]
|
|
node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 220:27]
|
|
miss_nxtstate <= _T_115 @[el2_ifu_mem_ctl.scala 220:21]
|
|
node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 221:43]
|
|
node _T_117 = or(_T_116, stream_eol_f) @[el2_ifu_mem_ctl.scala 221:67]
|
|
node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 221:105]
|
|
node _T_119 = or(_T_117, _T_118) @[el2_ifu_mem_ctl.scala 221:84]
|
|
node _T_120 = or(_T_119, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 221:118]
|
|
miss_state_en <= _T_120 @[el2_ifu_mem_ctl.scala 221:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_121 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_121 : @[Conditional.scala 39:67]
|
|
node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 224:69]
|
|
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 224:50]
|
|
node _T_124 = and(io.exu_flush_final, _T_123) @[el2_ifu_mem_ctl.scala 224:48]
|
|
node _T_125 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 224:84]
|
|
node _T_126 = and(_T_124, _T_125) @[el2_ifu_mem_ctl.scala 224:82]
|
|
node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_mem_ctl.scala 224:108]
|
|
node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 224:27]
|
|
miss_nxtstate <= _T_128 @[el2_ifu_mem_ctl.scala 224:21]
|
|
node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 225:63]
|
|
node _T_130 = or(io.exu_flush_final, _T_129) @[el2_ifu_mem_ctl.scala 225:43]
|
|
node _T_131 = or(_T_130, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 225:76]
|
|
miss_state_en <= _T_131 @[el2_ifu_mem_ctl.scala 225:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_132 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_132 : @[Conditional.scala 39:67]
|
|
node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 228:71]
|
|
node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 228:52]
|
|
node _T_135 = and(ic_miss_under_miss_f, _T_134) @[el2_ifu_mem_ctl.scala 228:50]
|
|
node _T_136 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 228:86]
|
|
node _T_137 = and(_T_135, _T_136) @[el2_ifu_mem_ctl.scala 228:84]
|
|
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_mem_ctl.scala 228:110]
|
|
node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 229:56]
|
|
node _T_140 = eq(_T_139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 229:37]
|
|
node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[el2_ifu_mem_ctl.scala 229:35]
|
|
node _T_142 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 229:71]
|
|
node _T_143 = and(_T_141, _T_142) @[el2_ifu_mem_ctl.scala 229:69]
|
|
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_mem_ctl.scala 229:95]
|
|
node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 229:12]
|
|
node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[el2_ifu_mem_ctl.scala 228:27]
|
|
miss_nxtstate <= _T_146 @[el2_ifu_mem_ctl.scala 228:21]
|
|
node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 230:42]
|
|
node _T_148 = or(_T_147, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 230:55]
|
|
node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 230:78]
|
|
node _T_150 = or(_T_149, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 230:101]
|
|
miss_state_en <= _T_150 @[el2_ifu_mem_ctl.scala 230:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_151 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_151 : @[Conditional.scala 39:67]
|
|
node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 234:31]
|
|
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_mem_ctl.scala 234:44]
|
|
node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 234:12]
|
|
node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 233:62]
|
|
node _T_156 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[el2_ifu_mem_ctl.scala 233:27]
|
|
miss_nxtstate <= _T_156 @[el2_ifu_mem_ctl.scala 233:21]
|
|
node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 235:42]
|
|
node _T_158 = or(_T_157, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 235:55]
|
|
node _T_159 = or(_T_158, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 235:76]
|
|
miss_state_en <= _T_159 @[el2_ifu_mem_ctl.scala 235:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_160 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_160 : @[Conditional.scala 39:67]
|
|
node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 239:31]
|
|
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_mem_ctl.scala 239:44]
|
|
node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 239:12]
|
|
node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 238:62]
|
|
node _T_165 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[el2_ifu_mem_ctl.scala 238:27]
|
|
miss_nxtstate <= _T_165 @[el2_ifu_mem_ctl.scala 238:21]
|
|
node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 240:42]
|
|
node _T_167 = or(_T_166, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 240:55]
|
|
node _T_168 = or(_T_167, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 240:76]
|
|
miss_state_en <= _T_168 @[el2_ifu_mem_ctl.scala 240:21]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_169 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 243:61]
|
|
reg _T_170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_169 : @[Reg.scala 28:19]
|
|
_T_170 <= miss_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
miss_state <= _T_170 @[el2_ifu_mem_ctl.scala 243:14]
|
|
wire crit_byp_hit_f : UInt<1>
|
|
crit_byp_hit_f <= UInt<1>("h00")
|
|
wire way_status_mb_scnd_ff : UInt<1>
|
|
way_status_mb_scnd_ff <= UInt<1>("h00")
|
|
wire way_status : UInt<1>
|
|
way_status <= UInt<1>("h00")
|
|
wire tagv_mb_scnd_ff : UInt<2>
|
|
tagv_mb_scnd_ff <= UInt<1>("h00")
|
|
wire uncacheable_miss_scnd_ff : UInt<1>
|
|
uncacheable_miss_scnd_ff <= UInt<1>("h00")
|
|
wire imb_scnd_ff : UInt<31>
|
|
imb_scnd_ff <= UInt<1>("h00")
|
|
wire reset_all_tags : UInt<1>
|
|
reset_all_tags <= UInt<1>("h00")
|
|
wire bus_rd_addr_count : UInt<3>
|
|
bus_rd_addr_count <= UInt<1>("h00")
|
|
wire ifu_bus_rid_ff : UInt<3>
|
|
ifu_bus_rid_ff <= UInt<1>("h00")
|
|
node _T_171 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 253:30]
|
|
miss_pending <= _T_171 @[el2_ifu_mem_ctl.scala 253:16]
|
|
node _T_172 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 254:39]
|
|
node _T_173 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 254:73]
|
|
node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:95]
|
|
node _T_175 = and(_T_173, _T_174) @[el2_ifu_mem_ctl.scala 254:93]
|
|
node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[el2_ifu_mem_ctl.scala 254:58]
|
|
node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 255:57]
|
|
node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:38]
|
|
node _T_178 = and(miss_pending, _T_177) @[el2_ifu_mem_ctl.scala 255:36]
|
|
node _T_179 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 255:86]
|
|
node _T_180 = and(_T_179, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 255:106]
|
|
node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:72]
|
|
node _T_182 = and(_T_178, _T_181) @[el2_ifu_mem_ctl.scala 255:70]
|
|
node _T_183 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 256:37]
|
|
node _T_184 = and(_T_183, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 256:57]
|
|
node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:23]
|
|
node _T_186 = and(_T_182, _T_185) @[el2_ifu_mem_ctl.scala 255:128]
|
|
node _T_187 = or(_T_186, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 256:77]
|
|
node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 257:36]
|
|
node _T_189 = and(miss_pending, _T_188) @[el2_ifu_mem_ctl.scala 257:19]
|
|
node sel_hold_imb = or(_T_187, _T_189) @[el2_ifu_mem_ctl.scala 256:93]
|
|
node _T_190 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 259:40]
|
|
node _T_191 = or(_T_190, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 259:57]
|
|
node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 259:83]
|
|
node sel_hold_imb_scnd = and(_T_191, _T_192) @[el2_ifu_mem_ctl.scala 259:81]
|
|
node _T_193 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 260:46]
|
|
node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 260:34]
|
|
node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 262:40]
|
|
node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 262:96]
|
|
node _T_196 = bits(_T_195, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_197 = mux(_T_196, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_198 = and(_T_197, io.ic_tag_valid) @[el2_ifu_mem_ctl.scala 262:113]
|
|
node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 262:28]
|
|
node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 263:56]
|
|
node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 263:37]
|
|
reg _T_200 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 264:67]
|
|
_T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 264:67]
|
|
uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 264:28]
|
|
node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 265:43]
|
|
node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 265:24]
|
|
reg _T_202 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 266:54]
|
|
_T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 266:54]
|
|
imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 266:15]
|
|
reg _T_203 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 267:64]
|
|
_T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 267:64]
|
|
way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 267:25]
|
|
reg _T_204 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 268:58]
|
|
_T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 268:58]
|
|
tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 268:19]
|
|
node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_206 = mux(_T_205, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[el2_ifu_mem_ctl.scala 271:45]
|
|
wire ifc_iccm_access_f : UInt<1>
|
|
ifc_iccm_access_f <= UInt<1>("h00")
|
|
wire ifc_region_acc_fault_final_f : UInt<1>
|
|
ifc_region_acc_fault_final_f <= UInt<1>("h00")
|
|
node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:48]
|
|
node _T_208 = and(ifc_fetch_req_f, _T_207) @[el2_ifu_mem_ctl.scala 274:46]
|
|
node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:69]
|
|
node fetch_req_icache_f = and(_T_208, _T_209) @[el2_ifu_mem_ctl.scala 274:67]
|
|
node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 275:46]
|
|
node _T_210 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 276:45]
|
|
node _T_211 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 276:73]
|
|
node _T_212 = or(_T_210, _T_211) @[el2_ifu_mem_ctl.scala 276:59]
|
|
node _T_213 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 276:105]
|
|
node _T_214 = or(_T_212, _T_213) @[el2_ifu_mem_ctl.scala 276:91]
|
|
node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[el2_ifu_mem_ctl.scala 276:41]
|
|
wire stream_hit_f : UInt<1>
|
|
stream_hit_f <= UInt<1>("h00")
|
|
node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 278:35]
|
|
node _T_216 = and(_T_215, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 278:52]
|
|
node _T_217 = and(_T_216, miss_pending) @[el2_ifu_mem_ctl.scala 278:73]
|
|
ic_byp_hit_f <= _T_217 @[el2_ifu_mem_ctl.scala 278:16]
|
|
wire sel_mb_addr_ff : UInt<1>
|
|
sel_mb_addr_ff <= UInt<1>("h00")
|
|
wire imb_ff : UInt<31>
|
|
imb_ff <= UInt<1>("h00")
|
|
wire ifu_fetch_addr_int_f : UInt<31>
|
|
ifu_fetch_addr_int_f <= UInt<1>("h00")
|
|
node _T_218 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 282:35]
|
|
node _T_219 = and(_T_218, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 282:39]
|
|
node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 282:62]
|
|
node _T_221 = and(_T_219, _T_220) @[el2_ifu_mem_ctl.scala 282:60]
|
|
node _T_222 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 282:81]
|
|
node _T_223 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 282:108]
|
|
node _T_224 = or(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 282:95]
|
|
node _T_225 = and(_T_221, _T_224) @[el2_ifu_mem_ctl.scala 282:78]
|
|
node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 282:128]
|
|
node ic_act_hit_f = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 282:126]
|
|
node _T_227 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 283:37]
|
|
node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:23]
|
|
node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 283:41]
|
|
node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 283:59]
|
|
node _T_231 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:82]
|
|
node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 283:80]
|
|
node _T_233 = or(_T_232, scnd_miss_req) @[el2_ifu_mem_ctl.scala 283:97]
|
|
node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:116]
|
|
node _T_235 = and(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 283:114]
|
|
ic_act_miss_f <= _T_235 @[el2_ifu_mem_ctl.scala 283:17]
|
|
node _T_236 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:28]
|
|
node _T_237 = or(_T_236, reset_all_tags) @[el2_ifu_mem_ctl.scala 284:42]
|
|
node _T_238 = and(_T_237, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 284:60]
|
|
node _T_239 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 284:94]
|
|
node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 284:81]
|
|
node _T_241 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 285:12]
|
|
node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 285:63]
|
|
node _T_243 = neq(_T_241, _T_242) @[el2_ifu_mem_ctl.scala 285:39]
|
|
node _T_244 = and(_T_240, _T_243) @[el2_ifu_mem_ctl.scala 284:111]
|
|
node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:93]
|
|
node _T_246 = and(_T_244, _T_245) @[el2_ifu_mem_ctl.scala 285:91]
|
|
node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:116]
|
|
node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 285:114]
|
|
node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:134]
|
|
node _T_250 = and(_T_248, _T_249) @[el2_ifu_mem_ctl.scala 285:132]
|
|
ic_miss_under_miss_f <= _T_250 @[el2_ifu_mem_ctl.scala 284:24]
|
|
node _T_251 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 286:42]
|
|
node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 286:28]
|
|
node _T_253 = or(_T_252, reset_all_tags) @[el2_ifu_mem_ctl.scala 286:46]
|
|
node _T_254 = and(_T_253, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 286:64]
|
|
node _T_255 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 286:99]
|
|
node _T_256 = and(_T_254, _T_255) @[el2_ifu_mem_ctl.scala 286:85]
|
|
node _T_257 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 287:13]
|
|
node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 287:62]
|
|
node _T_259 = eq(_T_257, _T_258) @[el2_ifu_mem_ctl.scala 287:39]
|
|
node _T_260 = or(_T_259, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 287:91]
|
|
node _T_261 = and(_T_256, _T_260) @[el2_ifu_mem_ctl.scala 286:117]
|
|
ic_ignore_2nd_miss_f <= _T_261 @[el2_ifu_mem_ctl.scala 286:24]
|
|
node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 289:31]
|
|
node _T_263 = or(_T_262, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 289:46]
|
|
node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 289:94]
|
|
node _T_265 = or(_T_263, _T_264) @[el2_ifu_mem_ctl.scala 289:62]
|
|
io.ic_hit_f <= _T_265 @[el2_ifu_mem_ctl.scala 289:15]
|
|
node _T_266 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 290:47]
|
|
node _T_267 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 290:98]
|
|
node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 290:84]
|
|
node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[el2_ifu_mem_ctl.scala 290:32]
|
|
node _T_269 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 291:34]
|
|
node _T_270 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 291:72]
|
|
node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 291:58]
|
|
node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 291:19]
|
|
wire ifu_wr_cumulative_err_data : UInt<1>
|
|
ifu_wr_cumulative_err_data <= UInt<1>("h00")
|
|
node _T_272 = bits(imb_ff, 11, 5) @[el2_ifu_mem_ctl.scala 293:38]
|
|
node _T_273 = bits(imb_scnd_ff, 11, 5) @[el2_ifu_mem_ctl.scala 293:93]
|
|
node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 293:79]
|
|
node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 293:135]
|
|
node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 293:153]
|
|
node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 293:151]
|
|
wire way_status_mb_ff : UInt<1>
|
|
way_status_mb_ff <= UInt<1>("h00")
|
|
wire way_status_rep_new : UInt<1>
|
|
way_status_rep_new <= UInt<1>("h00")
|
|
node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 296:47]
|
|
node _T_278 = and(scnd_miss_req, _T_277) @[el2_ifu_mem_ctl.scala 296:45]
|
|
node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_mem_ctl.scala 296:71]
|
|
node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 297:26]
|
|
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_mem_ctl.scala 297:52]
|
|
node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 298:26]
|
|
node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 298:12]
|
|
node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[el2_ifu_mem_ctl.scala 297:10]
|
|
node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[el2_ifu_mem_ctl.scala 296:29]
|
|
wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 299:32]
|
|
wire tagv_mb_ff : UInt<2>
|
|
tagv_mb_ff <= UInt<1>("h00")
|
|
node _T_285 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 301:38]
|
|
node _T_286 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_287 = mux(_T_286, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_288 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58]
|
|
node _T_289 = and(_T_287, _T_288) @[el2_ifu_mem_ctl.scala 301:110]
|
|
node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[el2_ifu_mem_ctl.scala 301:62]
|
|
node _T_291 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 302:20]
|
|
node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:80]
|
|
node _T_293 = bits(_T_292, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_294 = mux(_T_293, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_295 = and(io.ic_tag_valid, _T_294) @[el2_ifu_mem_ctl.scala 302:56]
|
|
node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[el2_ifu_mem_ctl.scala 302:6]
|
|
node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[el2_ifu_mem_ctl.scala 301:23]
|
|
wire scnd_miss_req_q : UInt<1>
|
|
scnd_miss_req_q <= UInt<1>("h00")
|
|
wire reset_ic_ff : UInt<1>
|
|
reset_ic_ff <= UInt<1>("h00")
|
|
node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 305:36]
|
|
node _T_298 = and(miss_pending, _T_297) @[el2_ifu_mem_ctl.scala 305:34]
|
|
node _T_299 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 305:72]
|
|
node reset_ic_in = and(_T_298, _T_299) @[el2_ifu_mem_ctl.scala 305:53]
|
|
reg _T_300 : UInt, clock @[el2_ifu_mem_ctl.scala 306:25]
|
|
_T_300 <= reset_ic_in @[el2_ifu_mem_ctl.scala 306:25]
|
|
reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 306:15]
|
|
reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 307:37]
|
|
fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 307:37]
|
|
reg _T_301 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 308:63]
|
|
_T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 308:63]
|
|
ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 308:24]
|
|
node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 309:37]
|
|
reg _T_302 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:62]
|
|
_T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 310:62]
|
|
uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 310:23]
|
|
reg _T_303 : UInt, rvclkhdr_2.io.l1clk @[el2_ifu_mem_ctl.scala 311:49]
|
|
_T_303 <= imb_in @[el2_ifu_mem_ctl.scala 311:49]
|
|
imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 311:10]
|
|
wire miss_addr : UInt<26>
|
|
miss_addr <= UInt<1>("h00")
|
|
node _T_304 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 313:26]
|
|
node _T_305 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 313:47]
|
|
node _T_306 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 314:25]
|
|
node _T_307 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 314:44]
|
|
node _T_308 = mux(_T_306, _T_307, miss_addr) @[el2_ifu_mem_ctl.scala 314:8]
|
|
node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 313:25]
|
|
node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 315:57]
|
|
node _T_310 = or(_T_309, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 315:73]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 461:22]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= reset
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 462:17]
|
|
rvclkhdr_3.io.en <= _T_310 @[el2_lib.scala 463:16]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23]
|
|
reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 316:48]
|
|
_T_311 <= miss_addr_in @[el2_ifu_mem_ctl.scala 316:48]
|
|
miss_addr <= _T_311 @[el2_ifu_mem_ctl.scala 316:13]
|
|
reg _T_312 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:59]
|
|
_T_312 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 317:59]
|
|
way_status_mb_ff <= _T_312 @[el2_ifu_mem_ctl.scala 317:20]
|
|
reg _T_313 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:53]
|
|
_T_313 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 318:53]
|
|
tagv_mb_ff <= _T_313 @[el2_ifu_mem_ctl.scala 318:14]
|
|
wire stream_miss_f : UInt<1>
|
|
stream_miss_f <= UInt<1>("h00")
|
|
node _T_314 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 320:68]
|
|
node _T_315 = and(_T_314, flush_final_f) @[el2_ifu_mem_ctl.scala 320:87]
|
|
node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 320:55]
|
|
node _T_317 = and(io.ifc_fetch_req_bf, _T_316) @[el2_ifu_mem_ctl.scala 320:53]
|
|
node _T_318 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 320:106]
|
|
node ifc_fetch_req_qual_bf = and(_T_317, _T_318) @[el2_ifu_mem_ctl.scala 320:104]
|
|
reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 321:36]
|
|
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 321:36]
|
|
node _T_319 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:44]
|
|
node _T_320 = and(ifc_fetch_req_f_raw, _T_319) @[el2_ifu_mem_ctl.scala 322:42]
|
|
ifc_fetch_req_f <= _T_320 @[el2_ifu_mem_ctl.scala 322:19]
|
|
reg _T_321 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 323:60]
|
|
_T_321 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 323:60]
|
|
ifc_iccm_access_f <= _T_321 @[el2_ifu_mem_ctl.scala 323:21]
|
|
wire ifc_region_acc_fault_final_bf : UInt<1>
|
|
ifc_region_acc_fault_final_bf <= UInt<1>("h00")
|
|
reg _T_322 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 325:71]
|
|
_T_322 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 325:71]
|
|
ifc_region_acc_fault_final_f <= _T_322 @[el2_ifu_mem_ctl.scala 325:32]
|
|
reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 326:68]
|
|
ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 326:68]
|
|
node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
|
|
node _T_323 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 328:38]
|
|
node _T_324 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 328:68]
|
|
node _T_325 = or(_T_323, _T_324) @[el2_ifu_mem_ctl.scala 328:55]
|
|
node _T_326 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 328:103]
|
|
node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 328:84]
|
|
node _T_328 = and(_T_325, _T_327) @[el2_ifu_mem_ctl.scala 328:82]
|
|
node _T_329 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 328:119]
|
|
node _T_330 = or(_T_328, _T_329) @[el2_ifu_mem_ctl.scala 328:117]
|
|
io.ifu_ic_mb_empty <= _T_330 @[el2_ifu_mem_ctl.scala 328:22]
|
|
node _T_331 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 329:40]
|
|
io.ifu_miss_state_idle <= _T_331 @[el2_ifu_mem_ctl.scala 329:26]
|
|
wire write_ic_16_bytes : UInt<1>
|
|
write_ic_16_bytes <= UInt<1>("h00")
|
|
wire reset_tag_valid_for_miss : UInt<1>
|
|
reset_tag_valid_for_miss <= UInt<1>("h00")
|
|
node _T_332 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 332:35]
|
|
node _T_333 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:57]
|
|
node _T_334 = and(_T_332, _T_333) @[el2_ifu_mem_ctl.scala 332:55]
|
|
node sel_mb_addr = or(_T_334, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 332:79]
|
|
node _T_335 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 333:63]
|
|
node _T_336 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 333:119]
|
|
node _T_337 = cat(_T_335, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_338 = cat(_T_337, _T_336) @[Cat.scala 29:58]
|
|
node _T_339 = eq(sel_mb_addr, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 334:37]
|
|
node _T_340 = mux(sel_mb_addr, _T_338, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_341 = mux(_T_339, io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_342 = or(_T_340, _T_341) @[Mux.scala 27:72]
|
|
wire ifu_ic_rw_int_addr : UInt<31> @[Mux.scala 27:72]
|
|
ifu_ic_rw_int_addr <= _T_342 @[Mux.scala 27:72]
|
|
wire bus_ifu_wr_en_ff_q : UInt<1>
|
|
bus_ifu_wr_en_ff_q <= UInt<1>("h00")
|
|
node _T_343 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 336:41]
|
|
node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 336:63]
|
|
node _T_345 = and(_T_343, _T_344) @[el2_ifu_mem_ctl.scala 336:61]
|
|
node _T_346 = and(_T_345, last_beat) @[el2_ifu_mem_ctl.scala 336:84]
|
|
node sel_mb_status_addr = and(_T_346, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 336:96]
|
|
node _T_347 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 337:62]
|
|
node _T_348 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 337:116]
|
|
node _T_349 = cat(_T_347, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_350 = cat(_T_349, _T_348) @[Cat.scala 29:58]
|
|
node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_350, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 337:31]
|
|
io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 338:17]
|
|
reg _T_351 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 339:51]
|
|
_T_351 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 339:51]
|
|
sel_mb_addr_ff <= _T_351 @[el2_ifu_mem_ctl.scala 339:18]
|
|
wire ifu_bus_rdata_ff : UInt<64>
|
|
ifu_bus_rdata_ff <= UInt<1>("h00")
|
|
wire ic_miss_buff_half : UInt<64>
|
|
ic_miss_buff_half <= UInt<1>("h00")
|
|
wire _T_352 : UInt<1>[35] @[el2_lib.scala 373:18]
|
|
wire _T_353 : UInt<1>[35] @[el2_lib.scala 374:18]
|
|
wire _T_354 : UInt<1>[35] @[el2_lib.scala 375:18]
|
|
wire _T_355 : UInt<1>[31] @[el2_lib.scala 376:18]
|
|
wire _T_356 : UInt<1>[31] @[el2_lib.scala 377:18]
|
|
wire _T_357 : UInt<1>[31] @[el2_lib.scala 378:18]
|
|
wire _T_358 : UInt<1>[7] @[el2_lib.scala 379:18]
|
|
node _T_359 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 386:36]
|
|
_T_352[0] <= _T_359 @[el2_lib.scala 386:30]
|
|
node _T_360 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 387:36]
|
|
_T_353[0] <= _T_360 @[el2_lib.scala 387:30]
|
|
node _T_361 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 386:36]
|
|
_T_352[1] <= _T_361 @[el2_lib.scala 386:30]
|
|
node _T_362 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 388:36]
|
|
_T_354[0] <= _T_362 @[el2_lib.scala 388:30]
|
|
node _T_363 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 387:36]
|
|
_T_353[1] <= _T_363 @[el2_lib.scala 387:30]
|
|
node _T_364 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 388:36]
|
|
_T_354[1] <= _T_364 @[el2_lib.scala 388:30]
|
|
node _T_365 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 386:36]
|
|
_T_352[2] <= _T_365 @[el2_lib.scala 386:30]
|
|
node _T_366 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 387:36]
|
|
_T_353[2] <= _T_366 @[el2_lib.scala 387:30]
|
|
node _T_367 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 388:36]
|
|
_T_354[2] <= _T_367 @[el2_lib.scala 388:30]
|
|
node _T_368 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 386:36]
|
|
_T_352[3] <= _T_368 @[el2_lib.scala 386:30]
|
|
node _T_369 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 389:36]
|
|
_T_355[0] <= _T_369 @[el2_lib.scala 389:30]
|
|
node _T_370 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 387:36]
|
|
_T_353[3] <= _T_370 @[el2_lib.scala 387:30]
|
|
node _T_371 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 389:36]
|
|
_T_355[1] <= _T_371 @[el2_lib.scala 389:30]
|
|
node _T_372 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 386:36]
|
|
_T_352[4] <= _T_372 @[el2_lib.scala 386:30]
|
|
node _T_373 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 387:36]
|
|
_T_353[4] <= _T_373 @[el2_lib.scala 387:30]
|
|
node _T_374 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 389:36]
|
|
_T_355[2] <= _T_374 @[el2_lib.scala 389:30]
|
|
node _T_375 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 388:36]
|
|
_T_354[3] <= _T_375 @[el2_lib.scala 388:30]
|
|
node _T_376 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 389:36]
|
|
_T_355[3] <= _T_376 @[el2_lib.scala 389:30]
|
|
node _T_377 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 386:36]
|
|
_T_352[5] <= _T_377 @[el2_lib.scala 386:30]
|
|
node _T_378 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 388:36]
|
|
_T_354[4] <= _T_378 @[el2_lib.scala 388:30]
|
|
node _T_379 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 389:36]
|
|
_T_355[4] <= _T_379 @[el2_lib.scala 389:30]
|
|
node _T_380 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 387:36]
|
|
_T_353[5] <= _T_380 @[el2_lib.scala 387:30]
|
|
node _T_381 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 388:36]
|
|
_T_354[5] <= _T_381 @[el2_lib.scala 388:30]
|
|
node _T_382 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 389:36]
|
|
_T_355[5] <= _T_382 @[el2_lib.scala 389:30]
|
|
node _T_383 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 386:36]
|
|
_T_352[6] <= _T_383 @[el2_lib.scala 386:30]
|
|
node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 387:36]
|
|
_T_353[6] <= _T_384 @[el2_lib.scala 387:30]
|
|
node _T_385 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 388:36]
|
|
_T_354[6] <= _T_385 @[el2_lib.scala 388:30]
|
|
node _T_386 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 389:36]
|
|
_T_355[6] <= _T_386 @[el2_lib.scala 389:30]
|
|
node _T_387 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 386:36]
|
|
_T_352[7] <= _T_387 @[el2_lib.scala 386:30]
|
|
node _T_388 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 390:36]
|
|
_T_356[0] <= _T_388 @[el2_lib.scala 390:30]
|
|
node _T_389 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 387:36]
|
|
_T_353[7] <= _T_389 @[el2_lib.scala 387:30]
|
|
node _T_390 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 390:36]
|
|
_T_356[1] <= _T_390 @[el2_lib.scala 390:30]
|
|
node _T_391 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 386:36]
|
|
_T_352[8] <= _T_391 @[el2_lib.scala 386:30]
|
|
node _T_392 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 387:36]
|
|
_T_353[8] <= _T_392 @[el2_lib.scala 387:30]
|
|
node _T_393 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 390:36]
|
|
_T_356[2] <= _T_393 @[el2_lib.scala 390:30]
|
|
node _T_394 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 388:36]
|
|
_T_354[7] <= _T_394 @[el2_lib.scala 388:30]
|
|
node _T_395 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 390:36]
|
|
_T_356[3] <= _T_395 @[el2_lib.scala 390:30]
|
|
node _T_396 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 386:36]
|
|
_T_352[9] <= _T_396 @[el2_lib.scala 386:30]
|
|
node _T_397 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 388:36]
|
|
_T_354[8] <= _T_397 @[el2_lib.scala 388:30]
|
|
node _T_398 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 390:36]
|
|
_T_356[4] <= _T_398 @[el2_lib.scala 390:30]
|
|
node _T_399 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 387:36]
|
|
_T_353[9] <= _T_399 @[el2_lib.scala 387:30]
|
|
node _T_400 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 388:36]
|
|
_T_354[9] <= _T_400 @[el2_lib.scala 388:30]
|
|
node _T_401 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 390:36]
|
|
_T_356[5] <= _T_401 @[el2_lib.scala 390:30]
|
|
node _T_402 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 386:36]
|
|
_T_352[10] <= _T_402 @[el2_lib.scala 386:30]
|
|
node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 387:36]
|
|
_T_353[10] <= _T_403 @[el2_lib.scala 387:30]
|
|
node _T_404 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 388:36]
|
|
_T_354[10] <= _T_404 @[el2_lib.scala 388:30]
|
|
node _T_405 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 390:36]
|
|
_T_356[6] <= _T_405 @[el2_lib.scala 390:30]
|
|
node _T_406 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 389:36]
|
|
_T_355[7] <= _T_406 @[el2_lib.scala 389:30]
|
|
node _T_407 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 390:36]
|
|
_T_356[7] <= _T_407 @[el2_lib.scala 390:30]
|
|
node _T_408 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 386:36]
|
|
_T_352[11] <= _T_408 @[el2_lib.scala 386:30]
|
|
node _T_409 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 389:36]
|
|
_T_355[8] <= _T_409 @[el2_lib.scala 389:30]
|
|
node _T_410 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 390:36]
|
|
_T_356[8] <= _T_410 @[el2_lib.scala 390:30]
|
|
node _T_411 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 387:36]
|
|
_T_353[11] <= _T_411 @[el2_lib.scala 387:30]
|
|
node _T_412 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 389:36]
|
|
_T_355[9] <= _T_412 @[el2_lib.scala 389:30]
|
|
node _T_413 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 390:36]
|
|
_T_356[9] <= _T_413 @[el2_lib.scala 390:30]
|
|
node _T_414 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 386:36]
|
|
_T_352[12] <= _T_414 @[el2_lib.scala 386:30]
|
|
node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 387:36]
|
|
_T_353[12] <= _T_415 @[el2_lib.scala 387:30]
|
|
node _T_416 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 389:36]
|
|
_T_355[10] <= _T_416 @[el2_lib.scala 389:30]
|
|
node _T_417 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 390:36]
|
|
_T_356[10] <= _T_417 @[el2_lib.scala 390:30]
|
|
node _T_418 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 388:36]
|
|
_T_354[11] <= _T_418 @[el2_lib.scala 388:30]
|
|
node _T_419 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 389:36]
|
|
_T_355[11] <= _T_419 @[el2_lib.scala 389:30]
|
|
node _T_420 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 390:36]
|
|
_T_356[11] <= _T_420 @[el2_lib.scala 390:30]
|
|
node _T_421 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 386:36]
|
|
_T_352[13] <= _T_421 @[el2_lib.scala 386:30]
|
|
node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 388:36]
|
|
_T_354[12] <= _T_422 @[el2_lib.scala 388:30]
|
|
node _T_423 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 389:36]
|
|
_T_355[12] <= _T_423 @[el2_lib.scala 389:30]
|
|
node _T_424 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 390:36]
|
|
_T_356[12] <= _T_424 @[el2_lib.scala 390:30]
|
|
node _T_425 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 387:36]
|
|
_T_353[13] <= _T_425 @[el2_lib.scala 387:30]
|
|
node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 388:36]
|
|
_T_354[13] <= _T_426 @[el2_lib.scala 388:30]
|
|
node _T_427 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 389:36]
|
|
_T_355[13] <= _T_427 @[el2_lib.scala 389:30]
|
|
node _T_428 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 390:36]
|
|
_T_356[13] <= _T_428 @[el2_lib.scala 390:30]
|
|
node _T_429 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 386:36]
|
|
_T_352[14] <= _T_429 @[el2_lib.scala 386:30]
|
|
node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 387:36]
|
|
_T_353[14] <= _T_430 @[el2_lib.scala 387:30]
|
|
node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 388:36]
|
|
_T_354[14] <= _T_431 @[el2_lib.scala 388:30]
|
|
node _T_432 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 389:36]
|
|
_T_355[14] <= _T_432 @[el2_lib.scala 389:30]
|
|
node _T_433 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 390:36]
|
|
_T_356[14] <= _T_433 @[el2_lib.scala 390:30]
|
|
node _T_434 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 386:36]
|
|
_T_352[15] <= _T_434 @[el2_lib.scala 386:30]
|
|
node _T_435 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 391:36]
|
|
_T_357[0] <= _T_435 @[el2_lib.scala 391:30]
|
|
node _T_436 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 387:36]
|
|
_T_353[15] <= _T_436 @[el2_lib.scala 387:30]
|
|
node _T_437 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 391:36]
|
|
_T_357[1] <= _T_437 @[el2_lib.scala 391:30]
|
|
node _T_438 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 386:36]
|
|
_T_352[16] <= _T_438 @[el2_lib.scala 386:30]
|
|
node _T_439 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 387:36]
|
|
_T_353[16] <= _T_439 @[el2_lib.scala 387:30]
|
|
node _T_440 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 391:36]
|
|
_T_357[2] <= _T_440 @[el2_lib.scala 391:30]
|
|
node _T_441 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 388:36]
|
|
_T_354[15] <= _T_441 @[el2_lib.scala 388:30]
|
|
node _T_442 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 391:36]
|
|
_T_357[3] <= _T_442 @[el2_lib.scala 391:30]
|
|
node _T_443 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 386:36]
|
|
_T_352[17] <= _T_443 @[el2_lib.scala 386:30]
|
|
node _T_444 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 388:36]
|
|
_T_354[16] <= _T_444 @[el2_lib.scala 388:30]
|
|
node _T_445 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 391:36]
|
|
_T_357[4] <= _T_445 @[el2_lib.scala 391:30]
|
|
node _T_446 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 387:36]
|
|
_T_353[17] <= _T_446 @[el2_lib.scala 387:30]
|
|
node _T_447 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 388:36]
|
|
_T_354[17] <= _T_447 @[el2_lib.scala 388:30]
|
|
node _T_448 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 391:36]
|
|
_T_357[5] <= _T_448 @[el2_lib.scala 391:30]
|
|
node _T_449 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 386:36]
|
|
_T_352[18] <= _T_449 @[el2_lib.scala 386:30]
|
|
node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 387:36]
|
|
_T_353[18] <= _T_450 @[el2_lib.scala 387:30]
|
|
node _T_451 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 388:36]
|
|
_T_354[18] <= _T_451 @[el2_lib.scala 388:30]
|
|
node _T_452 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 391:36]
|
|
_T_357[6] <= _T_452 @[el2_lib.scala 391:30]
|
|
node _T_453 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 389:36]
|
|
_T_355[15] <= _T_453 @[el2_lib.scala 389:30]
|
|
node _T_454 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 391:36]
|
|
_T_357[7] <= _T_454 @[el2_lib.scala 391:30]
|
|
node _T_455 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 386:36]
|
|
_T_352[19] <= _T_455 @[el2_lib.scala 386:30]
|
|
node _T_456 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 389:36]
|
|
_T_355[16] <= _T_456 @[el2_lib.scala 389:30]
|
|
node _T_457 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 391:36]
|
|
_T_357[8] <= _T_457 @[el2_lib.scala 391:30]
|
|
node _T_458 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 387:36]
|
|
_T_353[19] <= _T_458 @[el2_lib.scala 387:30]
|
|
node _T_459 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 389:36]
|
|
_T_355[17] <= _T_459 @[el2_lib.scala 389:30]
|
|
node _T_460 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 391:36]
|
|
_T_357[9] <= _T_460 @[el2_lib.scala 391:30]
|
|
node _T_461 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 386:36]
|
|
_T_352[20] <= _T_461 @[el2_lib.scala 386:30]
|
|
node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 387:36]
|
|
_T_353[20] <= _T_462 @[el2_lib.scala 387:30]
|
|
node _T_463 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 389:36]
|
|
_T_355[18] <= _T_463 @[el2_lib.scala 389:30]
|
|
node _T_464 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 391:36]
|
|
_T_357[10] <= _T_464 @[el2_lib.scala 391:30]
|
|
node _T_465 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 388:36]
|
|
_T_354[19] <= _T_465 @[el2_lib.scala 388:30]
|
|
node _T_466 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 389:36]
|
|
_T_355[19] <= _T_466 @[el2_lib.scala 389:30]
|
|
node _T_467 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 391:36]
|
|
_T_357[11] <= _T_467 @[el2_lib.scala 391:30]
|
|
node _T_468 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 386:36]
|
|
_T_352[21] <= _T_468 @[el2_lib.scala 386:30]
|
|
node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 388:36]
|
|
_T_354[20] <= _T_469 @[el2_lib.scala 388:30]
|
|
node _T_470 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 389:36]
|
|
_T_355[20] <= _T_470 @[el2_lib.scala 389:30]
|
|
node _T_471 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 391:36]
|
|
_T_357[12] <= _T_471 @[el2_lib.scala 391:30]
|
|
node _T_472 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 387:36]
|
|
_T_353[21] <= _T_472 @[el2_lib.scala 387:30]
|
|
node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 388:36]
|
|
_T_354[21] <= _T_473 @[el2_lib.scala 388:30]
|
|
node _T_474 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 389:36]
|
|
_T_355[21] <= _T_474 @[el2_lib.scala 389:30]
|
|
node _T_475 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 391:36]
|
|
_T_357[13] <= _T_475 @[el2_lib.scala 391:30]
|
|
node _T_476 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 386:36]
|
|
_T_352[22] <= _T_476 @[el2_lib.scala 386:30]
|
|
node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 387:36]
|
|
_T_353[22] <= _T_477 @[el2_lib.scala 387:30]
|
|
node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 388:36]
|
|
_T_354[22] <= _T_478 @[el2_lib.scala 388:30]
|
|
node _T_479 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 389:36]
|
|
_T_355[22] <= _T_479 @[el2_lib.scala 389:30]
|
|
node _T_480 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 391:36]
|
|
_T_357[14] <= _T_480 @[el2_lib.scala 391:30]
|
|
node _T_481 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 390:36]
|
|
_T_356[15] <= _T_481 @[el2_lib.scala 390:30]
|
|
node _T_482 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 391:36]
|
|
_T_357[15] <= _T_482 @[el2_lib.scala 391:30]
|
|
node _T_483 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 386:36]
|
|
_T_352[23] <= _T_483 @[el2_lib.scala 386:30]
|
|
node _T_484 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 390:36]
|
|
_T_356[16] <= _T_484 @[el2_lib.scala 390:30]
|
|
node _T_485 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 391:36]
|
|
_T_357[16] <= _T_485 @[el2_lib.scala 391:30]
|
|
node _T_486 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 387:36]
|
|
_T_353[23] <= _T_486 @[el2_lib.scala 387:30]
|
|
node _T_487 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 390:36]
|
|
_T_356[17] <= _T_487 @[el2_lib.scala 390:30]
|
|
node _T_488 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 391:36]
|
|
_T_357[17] <= _T_488 @[el2_lib.scala 391:30]
|
|
node _T_489 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 386:36]
|
|
_T_352[24] <= _T_489 @[el2_lib.scala 386:30]
|
|
node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 387:36]
|
|
_T_353[24] <= _T_490 @[el2_lib.scala 387:30]
|
|
node _T_491 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 390:36]
|
|
_T_356[18] <= _T_491 @[el2_lib.scala 390:30]
|
|
node _T_492 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 391:36]
|
|
_T_357[18] <= _T_492 @[el2_lib.scala 391:30]
|
|
node _T_493 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 388:36]
|
|
_T_354[23] <= _T_493 @[el2_lib.scala 388:30]
|
|
node _T_494 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 390:36]
|
|
_T_356[19] <= _T_494 @[el2_lib.scala 390:30]
|
|
node _T_495 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 391:36]
|
|
_T_357[19] <= _T_495 @[el2_lib.scala 391:30]
|
|
node _T_496 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 386:36]
|
|
_T_352[25] <= _T_496 @[el2_lib.scala 386:30]
|
|
node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 388:36]
|
|
_T_354[24] <= _T_497 @[el2_lib.scala 388:30]
|
|
node _T_498 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 390:36]
|
|
_T_356[20] <= _T_498 @[el2_lib.scala 390:30]
|
|
node _T_499 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 391:36]
|
|
_T_357[20] <= _T_499 @[el2_lib.scala 391:30]
|
|
node _T_500 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 387:36]
|
|
_T_353[25] <= _T_500 @[el2_lib.scala 387:30]
|
|
node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 388:36]
|
|
_T_354[25] <= _T_501 @[el2_lib.scala 388:30]
|
|
node _T_502 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 390:36]
|
|
_T_356[21] <= _T_502 @[el2_lib.scala 390:30]
|
|
node _T_503 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 391:36]
|
|
_T_357[21] <= _T_503 @[el2_lib.scala 391:30]
|
|
node _T_504 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 386:36]
|
|
_T_352[26] <= _T_504 @[el2_lib.scala 386:30]
|
|
node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 387:36]
|
|
_T_353[26] <= _T_505 @[el2_lib.scala 387:30]
|
|
node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 388:36]
|
|
_T_354[26] <= _T_506 @[el2_lib.scala 388:30]
|
|
node _T_507 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 390:36]
|
|
_T_356[22] <= _T_507 @[el2_lib.scala 390:30]
|
|
node _T_508 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 391:36]
|
|
_T_357[22] <= _T_508 @[el2_lib.scala 391:30]
|
|
node _T_509 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 389:36]
|
|
_T_355[23] <= _T_509 @[el2_lib.scala 389:30]
|
|
node _T_510 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 390:36]
|
|
_T_356[23] <= _T_510 @[el2_lib.scala 390:30]
|
|
node _T_511 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 391:36]
|
|
_T_357[23] <= _T_511 @[el2_lib.scala 391:30]
|
|
node _T_512 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 386:36]
|
|
_T_352[27] <= _T_512 @[el2_lib.scala 386:30]
|
|
node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 389:36]
|
|
_T_355[24] <= _T_513 @[el2_lib.scala 389:30]
|
|
node _T_514 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 390:36]
|
|
_T_356[24] <= _T_514 @[el2_lib.scala 390:30]
|
|
node _T_515 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 391:36]
|
|
_T_357[24] <= _T_515 @[el2_lib.scala 391:30]
|
|
node _T_516 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 387:36]
|
|
_T_353[27] <= _T_516 @[el2_lib.scala 387:30]
|
|
node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 389:36]
|
|
_T_355[25] <= _T_517 @[el2_lib.scala 389:30]
|
|
node _T_518 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 390:36]
|
|
_T_356[25] <= _T_518 @[el2_lib.scala 390:30]
|
|
node _T_519 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 391:36]
|
|
_T_357[25] <= _T_519 @[el2_lib.scala 391:30]
|
|
node _T_520 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 386:36]
|
|
_T_352[28] <= _T_520 @[el2_lib.scala 386:30]
|
|
node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 387:36]
|
|
_T_353[28] <= _T_521 @[el2_lib.scala 387:30]
|
|
node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 389:36]
|
|
_T_355[26] <= _T_522 @[el2_lib.scala 389:30]
|
|
node _T_523 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 390:36]
|
|
_T_356[26] <= _T_523 @[el2_lib.scala 390:30]
|
|
node _T_524 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 391:36]
|
|
_T_357[26] <= _T_524 @[el2_lib.scala 391:30]
|
|
node _T_525 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 388:36]
|
|
_T_354[27] <= _T_525 @[el2_lib.scala 388:30]
|
|
node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 389:36]
|
|
_T_355[27] <= _T_526 @[el2_lib.scala 389:30]
|
|
node _T_527 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 390:36]
|
|
_T_356[27] <= _T_527 @[el2_lib.scala 390:30]
|
|
node _T_528 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 391:36]
|
|
_T_357[27] <= _T_528 @[el2_lib.scala 391:30]
|
|
node _T_529 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 386:36]
|
|
_T_352[29] <= _T_529 @[el2_lib.scala 386:30]
|
|
node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 388:36]
|
|
_T_354[28] <= _T_530 @[el2_lib.scala 388:30]
|
|
node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 389:36]
|
|
_T_355[28] <= _T_531 @[el2_lib.scala 389:30]
|
|
node _T_532 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 390:36]
|
|
_T_356[28] <= _T_532 @[el2_lib.scala 390:30]
|
|
node _T_533 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 391:36]
|
|
_T_357[28] <= _T_533 @[el2_lib.scala 391:30]
|
|
node _T_534 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 387:36]
|
|
_T_353[29] <= _T_534 @[el2_lib.scala 387:30]
|
|
node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 388:36]
|
|
_T_354[29] <= _T_535 @[el2_lib.scala 388:30]
|
|
node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 389:36]
|
|
_T_355[29] <= _T_536 @[el2_lib.scala 389:30]
|
|
node _T_537 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 390:36]
|
|
_T_356[29] <= _T_537 @[el2_lib.scala 390:30]
|
|
node _T_538 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 391:36]
|
|
_T_357[29] <= _T_538 @[el2_lib.scala 391:30]
|
|
node _T_539 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 386:36]
|
|
_T_352[30] <= _T_539 @[el2_lib.scala 386:30]
|
|
node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 387:36]
|
|
_T_353[30] <= _T_540 @[el2_lib.scala 387:30]
|
|
node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 388:36]
|
|
_T_354[30] <= _T_541 @[el2_lib.scala 388:30]
|
|
node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 389:36]
|
|
_T_355[30] <= _T_542 @[el2_lib.scala 389:30]
|
|
node _T_543 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 390:36]
|
|
_T_356[30] <= _T_543 @[el2_lib.scala 390:30]
|
|
node _T_544 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 391:36]
|
|
_T_357[30] <= _T_544 @[el2_lib.scala 391:30]
|
|
node _T_545 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 386:36]
|
|
_T_352[31] <= _T_545 @[el2_lib.scala 386:30]
|
|
node _T_546 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 392:36]
|
|
_T_358[0] <= _T_546 @[el2_lib.scala 392:30]
|
|
node _T_547 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 387:36]
|
|
_T_353[31] <= _T_547 @[el2_lib.scala 387:30]
|
|
node _T_548 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 392:36]
|
|
_T_358[1] <= _T_548 @[el2_lib.scala 392:30]
|
|
node _T_549 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 386:36]
|
|
_T_352[32] <= _T_549 @[el2_lib.scala 386:30]
|
|
node _T_550 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 387:36]
|
|
_T_353[32] <= _T_550 @[el2_lib.scala 387:30]
|
|
node _T_551 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 392:36]
|
|
_T_358[2] <= _T_551 @[el2_lib.scala 392:30]
|
|
node _T_552 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 388:36]
|
|
_T_354[31] <= _T_552 @[el2_lib.scala 388:30]
|
|
node _T_553 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 392:36]
|
|
_T_358[3] <= _T_553 @[el2_lib.scala 392:30]
|
|
node _T_554 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 386:36]
|
|
_T_352[33] <= _T_554 @[el2_lib.scala 386:30]
|
|
node _T_555 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 388:36]
|
|
_T_354[32] <= _T_555 @[el2_lib.scala 388:30]
|
|
node _T_556 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 392:36]
|
|
_T_358[4] <= _T_556 @[el2_lib.scala 392:30]
|
|
node _T_557 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 387:36]
|
|
_T_353[33] <= _T_557 @[el2_lib.scala 387:30]
|
|
node _T_558 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 388:36]
|
|
_T_354[33] <= _T_558 @[el2_lib.scala 388:30]
|
|
node _T_559 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 392:36]
|
|
_T_358[5] <= _T_559 @[el2_lib.scala 392:30]
|
|
node _T_560 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 386:36]
|
|
_T_352[34] <= _T_560 @[el2_lib.scala 386:30]
|
|
node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 387:36]
|
|
_T_353[34] <= _T_561 @[el2_lib.scala 387:30]
|
|
node _T_562 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 388:36]
|
|
_T_354[34] <= _T_562 @[el2_lib.scala 388:30]
|
|
node _T_563 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 392:36]
|
|
_T_358[6] <= _T_563 @[el2_lib.scala 392:30]
|
|
node _T_564 = cat(_T_358[2], _T_358[1]) @[el2_lib.scala 394:13]
|
|
node _T_565 = cat(_T_564, _T_358[0]) @[el2_lib.scala 394:13]
|
|
node _T_566 = cat(_T_358[4], _T_358[3]) @[el2_lib.scala 394:13]
|
|
node _T_567 = cat(_T_358[6], _T_358[5]) @[el2_lib.scala 394:13]
|
|
node _T_568 = cat(_T_567, _T_566) @[el2_lib.scala 394:13]
|
|
node _T_569 = cat(_T_568, _T_565) @[el2_lib.scala 394:13]
|
|
node _T_570 = xorr(_T_569) @[el2_lib.scala 394:20]
|
|
node _T_571 = cat(_T_357[2], _T_357[1]) @[el2_lib.scala 394:30]
|
|
node _T_572 = cat(_T_571, _T_357[0]) @[el2_lib.scala 394:30]
|
|
node _T_573 = cat(_T_357[4], _T_357[3]) @[el2_lib.scala 394:30]
|
|
node _T_574 = cat(_T_357[6], _T_357[5]) @[el2_lib.scala 394:30]
|
|
node _T_575 = cat(_T_574, _T_573) @[el2_lib.scala 394:30]
|
|
node _T_576 = cat(_T_575, _T_572) @[el2_lib.scala 394:30]
|
|
node _T_577 = cat(_T_357[8], _T_357[7]) @[el2_lib.scala 394:30]
|
|
node _T_578 = cat(_T_357[10], _T_357[9]) @[el2_lib.scala 394:30]
|
|
node _T_579 = cat(_T_578, _T_577) @[el2_lib.scala 394:30]
|
|
node _T_580 = cat(_T_357[12], _T_357[11]) @[el2_lib.scala 394:30]
|
|
node _T_581 = cat(_T_357[14], _T_357[13]) @[el2_lib.scala 394:30]
|
|
node _T_582 = cat(_T_581, _T_580) @[el2_lib.scala 394:30]
|
|
node _T_583 = cat(_T_582, _T_579) @[el2_lib.scala 394:30]
|
|
node _T_584 = cat(_T_583, _T_576) @[el2_lib.scala 394:30]
|
|
node _T_585 = cat(_T_357[16], _T_357[15]) @[el2_lib.scala 394:30]
|
|
node _T_586 = cat(_T_357[18], _T_357[17]) @[el2_lib.scala 394:30]
|
|
node _T_587 = cat(_T_586, _T_585) @[el2_lib.scala 394:30]
|
|
node _T_588 = cat(_T_357[20], _T_357[19]) @[el2_lib.scala 394:30]
|
|
node _T_589 = cat(_T_357[22], _T_357[21]) @[el2_lib.scala 394:30]
|
|
node _T_590 = cat(_T_589, _T_588) @[el2_lib.scala 394:30]
|
|
node _T_591 = cat(_T_590, _T_587) @[el2_lib.scala 394:30]
|
|
node _T_592 = cat(_T_357[24], _T_357[23]) @[el2_lib.scala 394:30]
|
|
node _T_593 = cat(_T_357[26], _T_357[25]) @[el2_lib.scala 394:30]
|
|
node _T_594 = cat(_T_593, _T_592) @[el2_lib.scala 394:30]
|
|
node _T_595 = cat(_T_357[28], _T_357[27]) @[el2_lib.scala 394:30]
|
|
node _T_596 = cat(_T_357[30], _T_357[29]) @[el2_lib.scala 394:30]
|
|
node _T_597 = cat(_T_596, _T_595) @[el2_lib.scala 394:30]
|
|
node _T_598 = cat(_T_597, _T_594) @[el2_lib.scala 394:30]
|
|
node _T_599 = cat(_T_598, _T_591) @[el2_lib.scala 394:30]
|
|
node _T_600 = cat(_T_599, _T_584) @[el2_lib.scala 394:30]
|
|
node _T_601 = xorr(_T_600) @[el2_lib.scala 394:37]
|
|
node _T_602 = cat(_T_356[2], _T_356[1]) @[el2_lib.scala 394:47]
|
|
node _T_603 = cat(_T_602, _T_356[0]) @[el2_lib.scala 394:47]
|
|
node _T_604 = cat(_T_356[4], _T_356[3]) @[el2_lib.scala 394:47]
|
|
node _T_605 = cat(_T_356[6], _T_356[5]) @[el2_lib.scala 394:47]
|
|
node _T_606 = cat(_T_605, _T_604) @[el2_lib.scala 394:47]
|
|
node _T_607 = cat(_T_606, _T_603) @[el2_lib.scala 394:47]
|
|
node _T_608 = cat(_T_356[8], _T_356[7]) @[el2_lib.scala 394:47]
|
|
node _T_609 = cat(_T_356[10], _T_356[9]) @[el2_lib.scala 394:47]
|
|
node _T_610 = cat(_T_609, _T_608) @[el2_lib.scala 394:47]
|
|
node _T_611 = cat(_T_356[12], _T_356[11]) @[el2_lib.scala 394:47]
|
|
node _T_612 = cat(_T_356[14], _T_356[13]) @[el2_lib.scala 394:47]
|
|
node _T_613 = cat(_T_612, _T_611) @[el2_lib.scala 394:47]
|
|
node _T_614 = cat(_T_613, _T_610) @[el2_lib.scala 394:47]
|
|
node _T_615 = cat(_T_614, _T_607) @[el2_lib.scala 394:47]
|
|
node _T_616 = cat(_T_356[16], _T_356[15]) @[el2_lib.scala 394:47]
|
|
node _T_617 = cat(_T_356[18], _T_356[17]) @[el2_lib.scala 394:47]
|
|
node _T_618 = cat(_T_617, _T_616) @[el2_lib.scala 394:47]
|
|
node _T_619 = cat(_T_356[20], _T_356[19]) @[el2_lib.scala 394:47]
|
|
node _T_620 = cat(_T_356[22], _T_356[21]) @[el2_lib.scala 394:47]
|
|
node _T_621 = cat(_T_620, _T_619) @[el2_lib.scala 394:47]
|
|
node _T_622 = cat(_T_621, _T_618) @[el2_lib.scala 394:47]
|
|
node _T_623 = cat(_T_356[24], _T_356[23]) @[el2_lib.scala 394:47]
|
|
node _T_624 = cat(_T_356[26], _T_356[25]) @[el2_lib.scala 394:47]
|
|
node _T_625 = cat(_T_624, _T_623) @[el2_lib.scala 394:47]
|
|
node _T_626 = cat(_T_356[28], _T_356[27]) @[el2_lib.scala 394:47]
|
|
node _T_627 = cat(_T_356[30], _T_356[29]) @[el2_lib.scala 394:47]
|
|
node _T_628 = cat(_T_627, _T_626) @[el2_lib.scala 394:47]
|
|
node _T_629 = cat(_T_628, _T_625) @[el2_lib.scala 394:47]
|
|
node _T_630 = cat(_T_629, _T_622) @[el2_lib.scala 394:47]
|
|
node _T_631 = cat(_T_630, _T_615) @[el2_lib.scala 394:47]
|
|
node _T_632 = xorr(_T_631) @[el2_lib.scala 394:54]
|
|
node _T_633 = cat(_T_355[2], _T_355[1]) @[el2_lib.scala 394:64]
|
|
node _T_634 = cat(_T_633, _T_355[0]) @[el2_lib.scala 394:64]
|
|
node _T_635 = cat(_T_355[4], _T_355[3]) @[el2_lib.scala 394:64]
|
|
node _T_636 = cat(_T_355[6], _T_355[5]) @[el2_lib.scala 394:64]
|
|
node _T_637 = cat(_T_636, _T_635) @[el2_lib.scala 394:64]
|
|
node _T_638 = cat(_T_637, _T_634) @[el2_lib.scala 394:64]
|
|
node _T_639 = cat(_T_355[8], _T_355[7]) @[el2_lib.scala 394:64]
|
|
node _T_640 = cat(_T_355[10], _T_355[9]) @[el2_lib.scala 394:64]
|
|
node _T_641 = cat(_T_640, _T_639) @[el2_lib.scala 394:64]
|
|
node _T_642 = cat(_T_355[12], _T_355[11]) @[el2_lib.scala 394:64]
|
|
node _T_643 = cat(_T_355[14], _T_355[13]) @[el2_lib.scala 394:64]
|
|
node _T_644 = cat(_T_643, _T_642) @[el2_lib.scala 394:64]
|
|
node _T_645 = cat(_T_644, _T_641) @[el2_lib.scala 394:64]
|
|
node _T_646 = cat(_T_645, _T_638) @[el2_lib.scala 394:64]
|
|
node _T_647 = cat(_T_355[16], _T_355[15]) @[el2_lib.scala 394:64]
|
|
node _T_648 = cat(_T_355[18], _T_355[17]) @[el2_lib.scala 394:64]
|
|
node _T_649 = cat(_T_648, _T_647) @[el2_lib.scala 394:64]
|
|
node _T_650 = cat(_T_355[20], _T_355[19]) @[el2_lib.scala 394:64]
|
|
node _T_651 = cat(_T_355[22], _T_355[21]) @[el2_lib.scala 394:64]
|
|
node _T_652 = cat(_T_651, _T_650) @[el2_lib.scala 394:64]
|
|
node _T_653 = cat(_T_652, _T_649) @[el2_lib.scala 394:64]
|
|
node _T_654 = cat(_T_355[24], _T_355[23]) @[el2_lib.scala 394:64]
|
|
node _T_655 = cat(_T_355[26], _T_355[25]) @[el2_lib.scala 394:64]
|
|
node _T_656 = cat(_T_655, _T_654) @[el2_lib.scala 394:64]
|
|
node _T_657 = cat(_T_355[28], _T_355[27]) @[el2_lib.scala 394:64]
|
|
node _T_658 = cat(_T_355[30], _T_355[29]) @[el2_lib.scala 394:64]
|
|
node _T_659 = cat(_T_658, _T_657) @[el2_lib.scala 394:64]
|
|
node _T_660 = cat(_T_659, _T_656) @[el2_lib.scala 394:64]
|
|
node _T_661 = cat(_T_660, _T_653) @[el2_lib.scala 394:64]
|
|
node _T_662 = cat(_T_661, _T_646) @[el2_lib.scala 394:64]
|
|
node _T_663 = xorr(_T_662) @[el2_lib.scala 394:71]
|
|
node _T_664 = cat(_T_354[1], _T_354[0]) @[el2_lib.scala 394:81]
|
|
node _T_665 = cat(_T_354[3], _T_354[2]) @[el2_lib.scala 394:81]
|
|
node _T_666 = cat(_T_665, _T_664) @[el2_lib.scala 394:81]
|
|
node _T_667 = cat(_T_354[5], _T_354[4]) @[el2_lib.scala 394:81]
|
|
node _T_668 = cat(_T_354[7], _T_354[6]) @[el2_lib.scala 394:81]
|
|
node _T_669 = cat(_T_668, _T_667) @[el2_lib.scala 394:81]
|
|
node _T_670 = cat(_T_669, _T_666) @[el2_lib.scala 394:81]
|
|
node _T_671 = cat(_T_354[9], _T_354[8]) @[el2_lib.scala 394:81]
|
|
node _T_672 = cat(_T_354[11], _T_354[10]) @[el2_lib.scala 394:81]
|
|
node _T_673 = cat(_T_672, _T_671) @[el2_lib.scala 394:81]
|
|
node _T_674 = cat(_T_354[13], _T_354[12]) @[el2_lib.scala 394:81]
|
|
node _T_675 = cat(_T_354[16], _T_354[15]) @[el2_lib.scala 394:81]
|
|
node _T_676 = cat(_T_675, _T_354[14]) @[el2_lib.scala 394:81]
|
|
node _T_677 = cat(_T_676, _T_674) @[el2_lib.scala 394:81]
|
|
node _T_678 = cat(_T_677, _T_673) @[el2_lib.scala 394:81]
|
|
node _T_679 = cat(_T_678, _T_670) @[el2_lib.scala 394:81]
|
|
node _T_680 = cat(_T_354[18], _T_354[17]) @[el2_lib.scala 394:81]
|
|
node _T_681 = cat(_T_354[20], _T_354[19]) @[el2_lib.scala 394:81]
|
|
node _T_682 = cat(_T_681, _T_680) @[el2_lib.scala 394:81]
|
|
node _T_683 = cat(_T_354[22], _T_354[21]) @[el2_lib.scala 394:81]
|
|
node _T_684 = cat(_T_354[25], _T_354[24]) @[el2_lib.scala 394:81]
|
|
node _T_685 = cat(_T_684, _T_354[23]) @[el2_lib.scala 394:81]
|
|
node _T_686 = cat(_T_685, _T_683) @[el2_lib.scala 394:81]
|
|
node _T_687 = cat(_T_686, _T_682) @[el2_lib.scala 394:81]
|
|
node _T_688 = cat(_T_354[27], _T_354[26]) @[el2_lib.scala 394:81]
|
|
node _T_689 = cat(_T_354[29], _T_354[28]) @[el2_lib.scala 394:81]
|
|
node _T_690 = cat(_T_689, _T_688) @[el2_lib.scala 394:81]
|
|
node _T_691 = cat(_T_354[31], _T_354[30]) @[el2_lib.scala 394:81]
|
|
node _T_692 = cat(_T_354[34], _T_354[33]) @[el2_lib.scala 394:81]
|
|
node _T_693 = cat(_T_692, _T_354[32]) @[el2_lib.scala 394:81]
|
|
node _T_694 = cat(_T_693, _T_691) @[el2_lib.scala 394:81]
|
|
node _T_695 = cat(_T_694, _T_690) @[el2_lib.scala 394:81]
|
|
node _T_696 = cat(_T_695, _T_687) @[el2_lib.scala 394:81]
|
|
node _T_697 = cat(_T_696, _T_679) @[el2_lib.scala 394:81]
|
|
node _T_698 = xorr(_T_697) @[el2_lib.scala 394:88]
|
|
node _T_699 = cat(_T_353[1], _T_353[0]) @[el2_lib.scala 394:98]
|
|
node _T_700 = cat(_T_353[3], _T_353[2]) @[el2_lib.scala 394:98]
|
|
node _T_701 = cat(_T_700, _T_699) @[el2_lib.scala 394:98]
|
|
node _T_702 = cat(_T_353[5], _T_353[4]) @[el2_lib.scala 394:98]
|
|
node _T_703 = cat(_T_353[7], _T_353[6]) @[el2_lib.scala 394:98]
|
|
node _T_704 = cat(_T_703, _T_702) @[el2_lib.scala 394:98]
|
|
node _T_705 = cat(_T_704, _T_701) @[el2_lib.scala 394:98]
|
|
node _T_706 = cat(_T_353[9], _T_353[8]) @[el2_lib.scala 394:98]
|
|
node _T_707 = cat(_T_353[11], _T_353[10]) @[el2_lib.scala 394:98]
|
|
node _T_708 = cat(_T_707, _T_706) @[el2_lib.scala 394:98]
|
|
node _T_709 = cat(_T_353[13], _T_353[12]) @[el2_lib.scala 394:98]
|
|
node _T_710 = cat(_T_353[16], _T_353[15]) @[el2_lib.scala 394:98]
|
|
node _T_711 = cat(_T_710, _T_353[14]) @[el2_lib.scala 394:98]
|
|
node _T_712 = cat(_T_711, _T_709) @[el2_lib.scala 394:98]
|
|
node _T_713 = cat(_T_712, _T_708) @[el2_lib.scala 394:98]
|
|
node _T_714 = cat(_T_713, _T_705) @[el2_lib.scala 394:98]
|
|
node _T_715 = cat(_T_353[18], _T_353[17]) @[el2_lib.scala 394:98]
|
|
node _T_716 = cat(_T_353[20], _T_353[19]) @[el2_lib.scala 394:98]
|
|
node _T_717 = cat(_T_716, _T_715) @[el2_lib.scala 394:98]
|
|
node _T_718 = cat(_T_353[22], _T_353[21]) @[el2_lib.scala 394:98]
|
|
node _T_719 = cat(_T_353[25], _T_353[24]) @[el2_lib.scala 394:98]
|
|
node _T_720 = cat(_T_719, _T_353[23]) @[el2_lib.scala 394:98]
|
|
node _T_721 = cat(_T_720, _T_718) @[el2_lib.scala 394:98]
|
|
node _T_722 = cat(_T_721, _T_717) @[el2_lib.scala 394:98]
|
|
node _T_723 = cat(_T_353[27], _T_353[26]) @[el2_lib.scala 394:98]
|
|
node _T_724 = cat(_T_353[29], _T_353[28]) @[el2_lib.scala 394:98]
|
|
node _T_725 = cat(_T_724, _T_723) @[el2_lib.scala 394:98]
|
|
node _T_726 = cat(_T_353[31], _T_353[30]) @[el2_lib.scala 394:98]
|
|
node _T_727 = cat(_T_353[34], _T_353[33]) @[el2_lib.scala 394:98]
|
|
node _T_728 = cat(_T_727, _T_353[32]) @[el2_lib.scala 394:98]
|
|
node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 394:98]
|
|
node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 394:98]
|
|
node _T_731 = cat(_T_730, _T_722) @[el2_lib.scala 394:98]
|
|
node _T_732 = cat(_T_731, _T_714) @[el2_lib.scala 394:98]
|
|
node _T_733 = xorr(_T_732) @[el2_lib.scala 394:105]
|
|
node _T_734 = cat(_T_352[1], _T_352[0]) @[el2_lib.scala 394:115]
|
|
node _T_735 = cat(_T_352[3], _T_352[2]) @[el2_lib.scala 394:115]
|
|
node _T_736 = cat(_T_735, _T_734) @[el2_lib.scala 394:115]
|
|
node _T_737 = cat(_T_352[5], _T_352[4]) @[el2_lib.scala 394:115]
|
|
node _T_738 = cat(_T_352[7], _T_352[6]) @[el2_lib.scala 394:115]
|
|
node _T_739 = cat(_T_738, _T_737) @[el2_lib.scala 394:115]
|
|
node _T_740 = cat(_T_739, _T_736) @[el2_lib.scala 394:115]
|
|
node _T_741 = cat(_T_352[9], _T_352[8]) @[el2_lib.scala 394:115]
|
|
node _T_742 = cat(_T_352[11], _T_352[10]) @[el2_lib.scala 394:115]
|
|
node _T_743 = cat(_T_742, _T_741) @[el2_lib.scala 394:115]
|
|
node _T_744 = cat(_T_352[13], _T_352[12]) @[el2_lib.scala 394:115]
|
|
node _T_745 = cat(_T_352[16], _T_352[15]) @[el2_lib.scala 394:115]
|
|
node _T_746 = cat(_T_745, _T_352[14]) @[el2_lib.scala 394:115]
|
|
node _T_747 = cat(_T_746, _T_744) @[el2_lib.scala 394:115]
|
|
node _T_748 = cat(_T_747, _T_743) @[el2_lib.scala 394:115]
|
|
node _T_749 = cat(_T_748, _T_740) @[el2_lib.scala 394:115]
|
|
node _T_750 = cat(_T_352[18], _T_352[17]) @[el2_lib.scala 394:115]
|
|
node _T_751 = cat(_T_352[20], _T_352[19]) @[el2_lib.scala 394:115]
|
|
node _T_752 = cat(_T_751, _T_750) @[el2_lib.scala 394:115]
|
|
node _T_753 = cat(_T_352[22], _T_352[21]) @[el2_lib.scala 394:115]
|
|
node _T_754 = cat(_T_352[25], _T_352[24]) @[el2_lib.scala 394:115]
|
|
node _T_755 = cat(_T_754, _T_352[23]) @[el2_lib.scala 394:115]
|
|
node _T_756 = cat(_T_755, _T_753) @[el2_lib.scala 394:115]
|
|
node _T_757 = cat(_T_756, _T_752) @[el2_lib.scala 394:115]
|
|
node _T_758 = cat(_T_352[27], _T_352[26]) @[el2_lib.scala 394:115]
|
|
node _T_759 = cat(_T_352[29], _T_352[28]) @[el2_lib.scala 394:115]
|
|
node _T_760 = cat(_T_759, _T_758) @[el2_lib.scala 394:115]
|
|
node _T_761 = cat(_T_352[31], _T_352[30]) @[el2_lib.scala 394:115]
|
|
node _T_762 = cat(_T_352[34], _T_352[33]) @[el2_lib.scala 394:115]
|
|
node _T_763 = cat(_T_762, _T_352[32]) @[el2_lib.scala 394:115]
|
|
node _T_764 = cat(_T_763, _T_761) @[el2_lib.scala 394:115]
|
|
node _T_765 = cat(_T_764, _T_760) @[el2_lib.scala 394:115]
|
|
node _T_766 = cat(_T_765, _T_757) @[el2_lib.scala 394:115]
|
|
node _T_767 = cat(_T_766, _T_749) @[el2_lib.scala 394:115]
|
|
node _T_768 = xorr(_T_767) @[el2_lib.scala 394:122]
|
|
node _T_769 = cat(_T_698, _T_733) @[Cat.scala 29:58]
|
|
node _T_770 = cat(_T_769, _T_768) @[Cat.scala 29:58]
|
|
node _T_771 = cat(_T_632, _T_663) @[Cat.scala 29:58]
|
|
node _T_772 = cat(_T_570, _T_601) @[Cat.scala 29:58]
|
|
node _T_773 = cat(_T_772, _T_771) @[Cat.scala 29:58]
|
|
node ic_wr_ecc = cat(_T_773, _T_770) @[Cat.scala 29:58]
|
|
wire _T_774 : UInt<1>[35] @[el2_lib.scala 373:18]
|
|
wire _T_775 : UInt<1>[35] @[el2_lib.scala 374:18]
|
|
wire _T_776 : UInt<1>[35] @[el2_lib.scala 375:18]
|
|
wire _T_777 : UInt<1>[31] @[el2_lib.scala 376:18]
|
|
wire _T_778 : UInt<1>[31] @[el2_lib.scala 377:18]
|
|
wire _T_779 : UInt<1>[31] @[el2_lib.scala 378:18]
|
|
wire _T_780 : UInt<1>[7] @[el2_lib.scala 379:18]
|
|
node _T_781 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 386:36]
|
|
_T_774[0] <= _T_781 @[el2_lib.scala 386:30]
|
|
node _T_782 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 387:36]
|
|
_T_775[0] <= _T_782 @[el2_lib.scala 387:30]
|
|
node _T_783 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 386:36]
|
|
_T_774[1] <= _T_783 @[el2_lib.scala 386:30]
|
|
node _T_784 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 388:36]
|
|
_T_776[0] <= _T_784 @[el2_lib.scala 388:30]
|
|
node _T_785 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 387:36]
|
|
_T_775[1] <= _T_785 @[el2_lib.scala 387:30]
|
|
node _T_786 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 388:36]
|
|
_T_776[1] <= _T_786 @[el2_lib.scala 388:30]
|
|
node _T_787 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 386:36]
|
|
_T_774[2] <= _T_787 @[el2_lib.scala 386:30]
|
|
node _T_788 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 387:36]
|
|
_T_775[2] <= _T_788 @[el2_lib.scala 387:30]
|
|
node _T_789 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 388:36]
|
|
_T_776[2] <= _T_789 @[el2_lib.scala 388:30]
|
|
node _T_790 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 386:36]
|
|
_T_774[3] <= _T_790 @[el2_lib.scala 386:30]
|
|
node _T_791 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 389:36]
|
|
_T_777[0] <= _T_791 @[el2_lib.scala 389:30]
|
|
node _T_792 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 387:36]
|
|
_T_775[3] <= _T_792 @[el2_lib.scala 387:30]
|
|
node _T_793 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 389:36]
|
|
_T_777[1] <= _T_793 @[el2_lib.scala 389:30]
|
|
node _T_794 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 386:36]
|
|
_T_774[4] <= _T_794 @[el2_lib.scala 386:30]
|
|
node _T_795 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 387:36]
|
|
_T_775[4] <= _T_795 @[el2_lib.scala 387:30]
|
|
node _T_796 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 389:36]
|
|
_T_777[2] <= _T_796 @[el2_lib.scala 389:30]
|
|
node _T_797 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 388:36]
|
|
_T_776[3] <= _T_797 @[el2_lib.scala 388:30]
|
|
node _T_798 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 389:36]
|
|
_T_777[3] <= _T_798 @[el2_lib.scala 389:30]
|
|
node _T_799 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 386:36]
|
|
_T_774[5] <= _T_799 @[el2_lib.scala 386:30]
|
|
node _T_800 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 388:36]
|
|
_T_776[4] <= _T_800 @[el2_lib.scala 388:30]
|
|
node _T_801 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 389:36]
|
|
_T_777[4] <= _T_801 @[el2_lib.scala 389:30]
|
|
node _T_802 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 387:36]
|
|
_T_775[5] <= _T_802 @[el2_lib.scala 387:30]
|
|
node _T_803 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 388:36]
|
|
_T_776[5] <= _T_803 @[el2_lib.scala 388:30]
|
|
node _T_804 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 389:36]
|
|
_T_777[5] <= _T_804 @[el2_lib.scala 389:30]
|
|
node _T_805 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 386:36]
|
|
_T_774[6] <= _T_805 @[el2_lib.scala 386:30]
|
|
node _T_806 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 387:36]
|
|
_T_775[6] <= _T_806 @[el2_lib.scala 387:30]
|
|
node _T_807 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 388:36]
|
|
_T_776[6] <= _T_807 @[el2_lib.scala 388:30]
|
|
node _T_808 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 389:36]
|
|
_T_777[6] <= _T_808 @[el2_lib.scala 389:30]
|
|
node _T_809 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 386:36]
|
|
_T_774[7] <= _T_809 @[el2_lib.scala 386:30]
|
|
node _T_810 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 390:36]
|
|
_T_778[0] <= _T_810 @[el2_lib.scala 390:30]
|
|
node _T_811 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 387:36]
|
|
_T_775[7] <= _T_811 @[el2_lib.scala 387:30]
|
|
node _T_812 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 390:36]
|
|
_T_778[1] <= _T_812 @[el2_lib.scala 390:30]
|
|
node _T_813 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 386:36]
|
|
_T_774[8] <= _T_813 @[el2_lib.scala 386:30]
|
|
node _T_814 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 387:36]
|
|
_T_775[8] <= _T_814 @[el2_lib.scala 387:30]
|
|
node _T_815 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 390:36]
|
|
_T_778[2] <= _T_815 @[el2_lib.scala 390:30]
|
|
node _T_816 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 388:36]
|
|
_T_776[7] <= _T_816 @[el2_lib.scala 388:30]
|
|
node _T_817 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 390:36]
|
|
_T_778[3] <= _T_817 @[el2_lib.scala 390:30]
|
|
node _T_818 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 386:36]
|
|
_T_774[9] <= _T_818 @[el2_lib.scala 386:30]
|
|
node _T_819 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 388:36]
|
|
_T_776[8] <= _T_819 @[el2_lib.scala 388:30]
|
|
node _T_820 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 390:36]
|
|
_T_778[4] <= _T_820 @[el2_lib.scala 390:30]
|
|
node _T_821 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 387:36]
|
|
_T_775[9] <= _T_821 @[el2_lib.scala 387:30]
|
|
node _T_822 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 388:36]
|
|
_T_776[9] <= _T_822 @[el2_lib.scala 388:30]
|
|
node _T_823 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 390:36]
|
|
_T_778[5] <= _T_823 @[el2_lib.scala 390:30]
|
|
node _T_824 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 386:36]
|
|
_T_774[10] <= _T_824 @[el2_lib.scala 386:30]
|
|
node _T_825 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 387:36]
|
|
_T_775[10] <= _T_825 @[el2_lib.scala 387:30]
|
|
node _T_826 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 388:36]
|
|
_T_776[10] <= _T_826 @[el2_lib.scala 388:30]
|
|
node _T_827 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 390:36]
|
|
_T_778[6] <= _T_827 @[el2_lib.scala 390:30]
|
|
node _T_828 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 389:36]
|
|
_T_777[7] <= _T_828 @[el2_lib.scala 389:30]
|
|
node _T_829 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 390:36]
|
|
_T_778[7] <= _T_829 @[el2_lib.scala 390:30]
|
|
node _T_830 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 386:36]
|
|
_T_774[11] <= _T_830 @[el2_lib.scala 386:30]
|
|
node _T_831 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 389:36]
|
|
_T_777[8] <= _T_831 @[el2_lib.scala 389:30]
|
|
node _T_832 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 390:36]
|
|
_T_778[8] <= _T_832 @[el2_lib.scala 390:30]
|
|
node _T_833 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 387:36]
|
|
_T_775[11] <= _T_833 @[el2_lib.scala 387:30]
|
|
node _T_834 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 389:36]
|
|
_T_777[9] <= _T_834 @[el2_lib.scala 389:30]
|
|
node _T_835 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 390:36]
|
|
_T_778[9] <= _T_835 @[el2_lib.scala 390:30]
|
|
node _T_836 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 386:36]
|
|
_T_774[12] <= _T_836 @[el2_lib.scala 386:30]
|
|
node _T_837 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 387:36]
|
|
_T_775[12] <= _T_837 @[el2_lib.scala 387:30]
|
|
node _T_838 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 389:36]
|
|
_T_777[10] <= _T_838 @[el2_lib.scala 389:30]
|
|
node _T_839 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 390:36]
|
|
_T_778[10] <= _T_839 @[el2_lib.scala 390:30]
|
|
node _T_840 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 388:36]
|
|
_T_776[11] <= _T_840 @[el2_lib.scala 388:30]
|
|
node _T_841 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 389:36]
|
|
_T_777[11] <= _T_841 @[el2_lib.scala 389:30]
|
|
node _T_842 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 390:36]
|
|
_T_778[11] <= _T_842 @[el2_lib.scala 390:30]
|
|
node _T_843 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 386:36]
|
|
_T_774[13] <= _T_843 @[el2_lib.scala 386:30]
|
|
node _T_844 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 388:36]
|
|
_T_776[12] <= _T_844 @[el2_lib.scala 388:30]
|
|
node _T_845 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 389:36]
|
|
_T_777[12] <= _T_845 @[el2_lib.scala 389:30]
|
|
node _T_846 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 390:36]
|
|
_T_778[12] <= _T_846 @[el2_lib.scala 390:30]
|
|
node _T_847 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 387:36]
|
|
_T_775[13] <= _T_847 @[el2_lib.scala 387:30]
|
|
node _T_848 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 388:36]
|
|
_T_776[13] <= _T_848 @[el2_lib.scala 388:30]
|
|
node _T_849 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 389:36]
|
|
_T_777[13] <= _T_849 @[el2_lib.scala 389:30]
|
|
node _T_850 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 390:36]
|
|
_T_778[13] <= _T_850 @[el2_lib.scala 390:30]
|
|
node _T_851 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 386:36]
|
|
_T_774[14] <= _T_851 @[el2_lib.scala 386:30]
|
|
node _T_852 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 387:36]
|
|
_T_775[14] <= _T_852 @[el2_lib.scala 387:30]
|
|
node _T_853 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 388:36]
|
|
_T_776[14] <= _T_853 @[el2_lib.scala 388:30]
|
|
node _T_854 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 389:36]
|
|
_T_777[14] <= _T_854 @[el2_lib.scala 389:30]
|
|
node _T_855 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 390:36]
|
|
_T_778[14] <= _T_855 @[el2_lib.scala 390:30]
|
|
node _T_856 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 386:36]
|
|
_T_774[15] <= _T_856 @[el2_lib.scala 386:30]
|
|
node _T_857 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 391:36]
|
|
_T_779[0] <= _T_857 @[el2_lib.scala 391:30]
|
|
node _T_858 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 387:36]
|
|
_T_775[15] <= _T_858 @[el2_lib.scala 387:30]
|
|
node _T_859 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 391:36]
|
|
_T_779[1] <= _T_859 @[el2_lib.scala 391:30]
|
|
node _T_860 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 386:36]
|
|
_T_774[16] <= _T_860 @[el2_lib.scala 386:30]
|
|
node _T_861 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 387:36]
|
|
_T_775[16] <= _T_861 @[el2_lib.scala 387:30]
|
|
node _T_862 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 391:36]
|
|
_T_779[2] <= _T_862 @[el2_lib.scala 391:30]
|
|
node _T_863 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 388:36]
|
|
_T_776[15] <= _T_863 @[el2_lib.scala 388:30]
|
|
node _T_864 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 391:36]
|
|
_T_779[3] <= _T_864 @[el2_lib.scala 391:30]
|
|
node _T_865 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 386:36]
|
|
_T_774[17] <= _T_865 @[el2_lib.scala 386:30]
|
|
node _T_866 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 388:36]
|
|
_T_776[16] <= _T_866 @[el2_lib.scala 388:30]
|
|
node _T_867 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 391:36]
|
|
_T_779[4] <= _T_867 @[el2_lib.scala 391:30]
|
|
node _T_868 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 387:36]
|
|
_T_775[17] <= _T_868 @[el2_lib.scala 387:30]
|
|
node _T_869 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 388:36]
|
|
_T_776[17] <= _T_869 @[el2_lib.scala 388:30]
|
|
node _T_870 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 391:36]
|
|
_T_779[5] <= _T_870 @[el2_lib.scala 391:30]
|
|
node _T_871 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 386:36]
|
|
_T_774[18] <= _T_871 @[el2_lib.scala 386:30]
|
|
node _T_872 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 387:36]
|
|
_T_775[18] <= _T_872 @[el2_lib.scala 387:30]
|
|
node _T_873 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 388:36]
|
|
_T_776[18] <= _T_873 @[el2_lib.scala 388:30]
|
|
node _T_874 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 391:36]
|
|
_T_779[6] <= _T_874 @[el2_lib.scala 391:30]
|
|
node _T_875 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 389:36]
|
|
_T_777[15] <= _T_875 @[el2_lib.scala 389:30]
|
|
node _T_876 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 391:36]
|
|
_T_779[7] <= _T_876 @[el2_lib.scala 391:30]
|
|
node _T_877 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 386:36]
|
|
_T_774[19] <= _T_877 @[el2_lib.scala 386:30]
|
|
node _T_878 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 389:36]
|
|
_T_777[16] <= _T_878 @[el2_lib.scala 389:30]
|
|
node _T_879 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 391:36]
|
|
_T_779[8] <= _T_879 @[el2_lib.scala 391:30]
|
|
node _T_880 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 387:36]
|
|
_T_775[19] <= _T_880 @[el2_lib.scala 387:30]
|
|
node _T_881 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 389:36]
|
|
_T_777[17] <= _T_881 @[el2_lib.scala 389:30]
|
|
node _T_882 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 391:36]
|
|
_T_779[9] <= _T_882 @[el2_lib.scala 391:30]
|
|
node _T_883 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 386:36]
|
|
_T_774[20] <= _T_883 @[el2_lib.scala 386:30]
|
|
node _T_884 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 387:36]
|
|
_T_775[20] <= _T_884 @[el2_lib.scala 387:30]
|
|
node _T_885 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 389:36]
|
|
_T_777[18] <= _T_885 @[el2_lib.scala 389:30]
|
|
node _T_886 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 391:36]
|
|
_T_779[10] <= _T_886 @[el2_lib.scala 391:30]
|
|
node _T_887 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 388:36]
|
|
_T_776[19] <= _T_887 @[el2_lib.scala 388:30]
|
|
node _T_888 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 389:36]
|
|
_T_777[19] <= _T_888 @[el2_lib.scala 389:30]
|
|
node _T_889 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 391:36]
|
|
_T_779[11] <= _T_889 @[el2_lib.scala 391:30]
|
|
node _T_890 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 386:36]
|
|
_T_774[21] <= _T_890 @[el2_lib.scala 386:30]
|
|
node _T_891 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 388:36]
|
|
_T_776[20] <= _T_891 @[el2_lib.scala 388:30]
|
|
node _T_892 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 389:36]
|
|
_T_777[20] <= _T_892 @[el2_lib.scala 389:30]
|
|
node _T_893 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 391:36]
|
|
_T_779[12] <= _T_893 @[el2_lib.scala 391:30]
|
|
node _T_894 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 387:36]
|
|
_T_775[21] <= _T_894 @[el2_lib.scala 387:30]
|
|
node _T_895 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 388:36]
|
|
_T_776[21] <= _T_895 @[el2_lib.scala 388:30]
|
|
node _T_896 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 389:36]
|
|
_T_777[21] <= _T_896 @[el2_lib.scala 389:30]
|
|
node _T_897 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 391:36]
|
|
_T_779[13] <= _T_897 @[el2_lib.scala 391:30]
|
|
node _T_898 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 386:36]
|
|
_T_774[22] <= _T_898 @[el2_lib.scala 386:30]
|
|
node _T_899 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 387:36]
|
|
_T_775[22] <= _T_899 @[el2_lib.scala 387:30]
|
|
node _T_900 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 388:36]
|
|
_T_776[22] <= _T_900 @[el2_lib.scala 388:30]
|
|
node _T_901 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 389:36]
|
|
_T_777[22] <= _T_901 @[el2_lib.scala 389:30]
|
|
node _T_902 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 391:36]
|
|
_T_779[14] <= _T_902 @[el2_lib.scala 391:30]
|
|
node _T_903 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 390:36]
|
|
_T_778[15] <= _T_903 @[el2_lib.scala 390:30]
|
|
node _T_904 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 391:36]
|
|
_T_779[15] <= _T_904 @[el2_lib.scala 391:30]
|
|
node _T_905 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 386:36]
|
|
_T_774[23] <= _T_905 @[el2_lib.scala 386:30]
|
|
node _T_906 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 390:36]
|
|
_T_778[16] <= _T_906 @[el2_lib.scala 390:30]
|
|
node _T_907 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 391:36]
|
|
_T_779[16] <= _T_907 @[el2_lib.scala 391:30]
|
|
node _T_908 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 387:36]
|
|
_T_775[23] <= _T_908 @[el2_lib.scala 387:30]
|
|
node _T_909 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 390:36]
|
|
_T_778[17] <= _T_909 @[el2_lib.scala 390:30]
|
|
node _T_910 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 391:36]
|
|
_T_779[17] <= _T_910 @[el2_lib.scala 391:30]
|
|
node _T_911 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 386:36]
|
|
_T_774[24] <= _T_911 @[el2_lib.scala 386:30]
|
|
node _T_912 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 387:36]
|
|
_T_775[24] <= _T_912 @[el2_lib.scala 387:30]
|
|
node _T_913 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 390:36]
|
|
_T_778[18] <= _T_913 @[el2_lib.scala 390:30]
|
|
node _T_914 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 391:36]
|
|
_T_779[18] <= _T_914 @[el2_lib.scala 391:30]
|
|
node _T_915 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 388:36]
|
|
_T_776[23] <= _T_915 @[el2_lib.scala 388:30]
|
|
node _T_916 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 390:36]
|
|
_T_778[19] <= _T_916 @[el2_lib.scala 390:30]
|
|
node _T_917 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 391:36]
|
|
_T_779[19] <= _T_917 @[el2_lib.scala 391:30]
|
|
node _T_918 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 386:36]
|
|
_T_774[25] <= _T_918 @[el2_lib.scala 386:30]
|
|
node _T_919 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 388:36]
|
|
_T_776[24] <= _T_919 @[el2_lib.scala 388:30]
|
|
node _T_920 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 390:36]
|
|
_T_778[20] <= _T_920 @[el2_lib.scala 390:30]
|
|
node _T_921 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 391:36]
|
|
_T_779[20] <= _T_921 @[el2_lib.scala 391:30]
|
|
node _T_922 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 387:36]
|
|
_T_775[25] <= _T_922 @[el2_lib.scala 387:30]
|
|
node _T_923 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 388:36]
|
|
_T_776[25] <= _T_923 @[el2_lib.scala 388:30]
|
|
node _T_924 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 390:36]
|
|
_T_778[21] <= _T_924 @[el2_lib.scala 390:30]
|
|
node _T_925 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 391:36]
|
|
_T_779[21] <= _T_925 @[el2_lib.scala 391:30]
|
|
node _T_926 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 386:36]
|
|
_T_774[26] <= _T_926 @[el2_lib.scala 386:30]
|
|
node _T_927 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 387:36]
|
|
_T_775[26] <= _T_927 @[el2_lib.scala 387:30]
|
|
node _T_928 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 388:36]
|
|
_T_776[26] <= _T_928 @[el2_lib.scala 388:30]
|
|
node _T_929 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 390:36]
|
|
_T_778[22] <= _T_929 @[el2_lib.scala 390:30]
|
|
node _T_930 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 391:36]
|
|
_T_779[22] <= _T_930 @[el2_lib.scala 391:30]
|
|
node _T_931 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 389:36]
|
|
_T_777[23] <= _T_931 @[el2_lib.scala 389:30]
|
|
node _T_932 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 390:36]
|
|
_T_778[23] <= _T_932 @[el2_lib.scala 390:30]
|
|
node _T_933 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 391:36]
|
|
_T_779[23] <= _T_933 @[el2_lib.scala 391:30]
|
|
node _T_934 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 386:36]
|
|
_T_774[27] <= _T_934 @[el2_lib.scala 386:30]
|
|
node _T_935 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 389:36]
|
|
_T_777[24] <= _T_935 @[el2_lib.scala 389:30]
|
|
node _T_936 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 390:36]
|
|
_T_778[24] <= _T_936 @[el2_lib.scala 390:30]
|
|
node _T_937 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 391:36]
|
|
_T_779[24] <= _T_937 @[el2_lib.scala 391:30]
|
|
node _T_938 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 387:36]
|
|
_T_775[27] <= _T_938 @[el2_lib.scala 387:30]
|
|
node _T_939 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 389:36]
|
|
_T_777[25] <= _T_939 @[el2_lib.scala 389:30]
|
|
node _T_940 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 390:36]
|
|
_T_778[25] <= _T_940 @[el2_lib.scala 390:30]
|
|
node _T_941 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 391:36]
|
|
_T_779[25] <= _T_941 @[el2_lib.scala 391:30]
|
|
node _T_942 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 386:36]
|
|
_T_774[28] <= _T_942 @[el2_lib.scala 386:30]
|
|
node _T_943 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 387:36]
|
|
_T_775[28] <= _T_943 @[el2_lib.scala 387:30]
|
|
node _T_944 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 389:36]
|
|
_T_777[26] <= _T_944 @[el2_lib.scala 389:30]
|
|
node _T_945 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 390:36]
|
|
_T_778[26] <= _T_945 @[el2_lib.scala 390:30]
|
|
node _T_946 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 391:36]
|
|
_T_779[26] <= _T_946 @[el2_lib.scala 391:30]
|
|
node _T_947 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 388:36]
|
|
_T_776[27] <= _T_947 @[el2_lib.scala 388:30]
|
|
node _T_948 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 389:36]
|
|
_T_777[27] <= _T_948 @[el2_lib.scala 389:30]
|
|
node _T_949 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 390:36]
|
|
_T_778[27] <= _T_949 @[el2_lib.scala 390:30]
|
|
node _T_950 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 391:36]
|
|
_T_779[27] <= _T_950 @[el2_lib.scala 391:30]
|
|
node _T_951 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 386:36]
|
|
_T_774[29] <= _T_951 @[el2_lib.scala 386:30]
|
|
node _T_952 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 388:36]
|
|
_T_776[28] <= _T_952 @[el2_lib.scala 388:30]
|
|
node _T_953 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 389:36]
|
|
_T_777[28] <= _T_953 @[el2_lib.scala 389:30]
|
|
node _T_954 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 390:36]
|
|
_T_778[28] <= _T_954 @[el2_lib.scala 390:30]
|
|
node _T_955 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 391:36]
|
|
_T_779[28] <= _T_955 @[el2_lib.scala 391:30]
|
|
node _T_956 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 387:36]
|
|
_T_775[29] <= _T_956 @[el2_lib.scala 387:30]
|
|
node _T_957 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 388:36]
|
|
_T_776[29] <= _T_957 @[el2_lib.scala 388:30]
|
|
node _T_958 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 389:36]
|
|
_T_777[29] <= _T_958 @[el2_lib.scala 389:30]
|
|
node _T_959 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 390:36]
|
|
_T_778[29] <= _T_959 @[el2_lib.scala 390:30]
|
|
node _T_960 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 391:36]
|
|
_T_779[29] <= _T_960 @[el2_lib.scala 391:30]
|
|
node _T_961 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 386:36]
|
|
_T_774[30] <= _T_961 @[el2_lib.scala 386:30]
|
|
node _T_962 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 387:36]
|
|
_T_775[30] <= _T_962 @[el2_lib.scala 387:30]
|
|
node _T_963 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 388:36]
|
|
_T_776[30] <= _T_963 @[el2_lib.scala 388:30]
|
|
node _T_964 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 389:36]
|
|
_T_777[30] <= _T_964 @[el2_lib.scala 389:30]
|
|
node _T_965 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 390:36]
|
|
_T_778[30] <= _T_965 @[el2_lib.scala 390:30]
|
|
node _T_966 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 391:36]
|
|
_T_779[30] <= _T_966 @[el2_lib.scala 391:30]
|
|
node _T_967 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 386:36]
|
|
_T_774[31] <= _T_967 @[el2_lib.scala 386:30]
|
|
node _T_968 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 392:36]
|
|
_T_780[0] <= _T_968 @[el2_lib.scala 392:30]
|
|
node _T_969 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 387:36]
|
|
_T_775[31] <= _T_969 @[el2_lib.scala 387:30]
|
|
node _T_970 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 392:36]
|
|
_T_780[1] <= _T_970 @[el2_lib.scala 392:30]
|
|
node _T_971 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 386:36]
|
|
_T_774[32] <= _T_971 @[el2_lib.scala 386:30]
|
|
node _T_972 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 387:36]
|
|
_T_775[32] <= _T_972 @[el2_lib.scala 387:30]
|
|
node _T_973 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 392:36]
|
|
_T_780[2] <= _T_973 @[el2_lib.scala 392:30]
|
|
node _T_974 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 388:36]
|
|
_T_776[31] <= _T_974 @[el2_lib.scala 388:30]
|
|
node _T_975 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 392:36]
|
|
_T_780[3] <= _T_975 @[el2_lib.scala 392:30]
|
|
node _T_976 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 386:36]
|
|
_T_774[33] <= _T_976 @[el2_lib.scala 386:30]
|
|
node _T_977 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 388:36]
|
|
_T_776[32] <= _T_977 @[el2_lib.scala 388:30]
|
|
node _T_978 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 392:36]
|
|
_T_780[4] <= _T_978 @[el2_lib.scala 392:30]
|
|
node _T_979 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 387:36]
|
|
_T_775[33] <= _T_979 @[el2_lib.scala 387:30]
|
|
node _T_980 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 388:36]
|
|
_T_776[33] <= _T_980 @[el2_lib.scala 388:30]
|
|
node _T_981 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 392:36]
|
|
_T_780[5] <= _T_981 @[el2_lib.scala 392:30]
|
|
node _T_982 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 386:36]
|
|
_T_774[34] <= _T_982 @[el2_lib.scala 386:30]
|
|
node _T_983 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 387:36]
|
|
_T_775[34] <= _T_983 @[el2_lib.scala 387:30]
|
|
node _T_984 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 388:36]
|
|
_T_776[34] <= _T_984 @[el2_lib.scala 388:30]
|
|
node _T_985 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 392:36]
|
|
_T_780[6] <= _T_985 @[el2_lib.scala 392:30]
|
|
node _T_986 = cat(_T_780[2], _T_780[1]) @[el2_lib.scala 394:13]
|
|
node _T_987 = cat(_T_986, _T_780[0]) @[el2_lib.scala 394:13]
|
|
node _T_988 = cat(_T_780[4], _T_780[3]) @[el2_lib.scala 394:13]
|
|
node _T_989 = cat(_T_780[6], _T_780[5]) @[el2_lib.scala 394:13]
|
|
node _T_990 = cat(_T_989, _T_988) @[el2_lib.scala 394:13]
|
|
node _T_991 = cat(_T_990, _T_987) @[el2_lib.scala 394:13]
|
|
node _T_992 = xorr(_T_991) @[el2_lib.scala 394:20]
|
|
node _T_993 = cat(_T_779[2], _T_779[1]) @[el2_lib.scala 394:30]
|
|
node _T_994 = cat(_T_993, _T_779[0]) @[el2_lib.scala 394:30]
|
|
node _T_995 = cat(_T_779[4], _T_779[3]) @[el2_lib.scala 394:30]
|
|
node _T_996 = cat(_T_779[6], _T_779[5]) @[el2_lib.scala 394:30]
|
|
node _T_997 = cat(_T_996, _T_995) @[el2_lib.scala 394:30]
|
|
node _T_998 = cat(_T_997, _T_994) @[el2_lib.scala 394:30]
|
|
node _T_999 = cat(_T_779[8], _T_779[7]) @[el2_lib.scala 394:30]
|
|
node _T_1000 = cat(_T_779[10], _T_779[9]) @[el2_lib.scala 394:30]
|
|
node _T_1001 = cat(_T_1000, _T_999) @[el2_lib.scala 394:30]
|
|
node _T_1002 = cat(_T_779[12], _T_779[11]) @[el2_lib.scala 394:30]
|
|
node _T_1003 = cat(_T_779[14], _T_779[13]) @[el2_lib.scala 394:30]
|
|
node _T_1004 = cat(_T_1003, _T_1002) @[el2_lib.scala 394:30]
|
|
node _T_1005 = cat(_T_1004, _T_1001) @[el2_lib.scala 394:30]
|
|
node _T_1006 = cat(_T_1005, _T_998) @[el2_lib.scala 394:30]
|
|
node _T_1007 = cat(_T_779[16], _T_779[15]) @[el2_lib.scala 394:30]
|
|
node _T_1008 = cat(_T_779[18], _T_779[17]) @[el2_lib.scala 394:30]
|
|
node _T_1009 = cat(_T_1008, _T_1007) @[el2_lib.scala 394:30]
|
|
node _T_1010 = cat(_T_779[20], _T_779[19]) @[el2_lib.scala 394:30]
|
|
node _T_1011 = cat(_T_779[22], _T_779[21]) @[el2_lib.scala 394:30]
|
|
node _T_1012 = cat(_T_1011, _T_1010) @[el2_lib.scala 394:30]
|
|
node _T_1013 = cat(_T_1012, _T_1009) @[el2_lib.scala 394:30]
|
|
node _T_1014 = cat(_T_779[24], _T_779[23]) @[el2_lib.scala 394:30]
|
|
node _T_1015 = cat(_T_779[26], _T_779[25]) @[el2_lib.scala 394:30]
|
|
node _T_1016 = cat(_T_1015, _T_1014) @[el2_lib.scala 394:30]
|
|
node _T_1017 = cat(_T_779[28], _T_779[27]) @[el2_lib.scala 394:30]
|
|
node _T_1018 = cat(_T_779[30], _T_779[29]) @[el2_lib.scala 394:30]
|
|
node _T_1019 = cat(_T_1018, _T_1017) @[el2_lib.scala 394:30]
|
|
node _T_1020 = cat(_T_1019, _T_1016) @[el2_lib.scala 394:30]
|
|
node _T_1021 = cat(_T_1020, _T_1013) @[el2_lib.scala 394:30]
|
|
node _T_1022 = cat(_T_1021, _T_1006) @[el2_lib.scala 394:30]
|
|
node _T_1023 = xorr(_T_1022) @[el2_lib.scala 394:37]
|
|
node _T_1024 = cat(_T_778[2], _T_778[1]) @[el2_lib.scala 394:47]
|
|
node _T_1025 = cat(_T_1024, _T_778[0]) @[el2_lib.scala 394:47]
|
|
node _T_1026 = cat(_T_778[4], _T_778[3]) @[el2_lib.scala 394:47]
|
|
node _T_1027 = cat(_T_778[6], _T_778[5]) @[el2_lib.scala 394:47]
|
|
node _T_1028 = cat(_T_1027, _T_1026) @[el2_lib.scala 394:47]
|
|
node _T_1029 = cat(_T_1028, _T_1025) @[el2_lib.scala 394:47]
|
|
node _T_1030 = cat(_T_778[8], _T_778[7]) @[el2_lib.scala 394:47]
|
|
node _T_1031 = cat(_T_778[10], _T_778[9]) @[el2_lib.scala 394:47]
|
|
node _T_1032 = cat(_T_1031, _T_1030) @[el2_lib.scala 394:47]
|
|
node _T_1033 = cat(_T_778[12], _T_778[11]) @[el2_lib.scala 394:47]
|
|
node _T_1034 = cat(_T_778[14], _T_778[13]) @[el2_lib.scala 394:47]
|
|
node _T_1035 = cat(_T_1034, _T_1033) @[el2_lib.scala 394:47]
|
|
node _T_1036 = cat(_T_1035, _T_1032) @[el2_lib.scala 394:47]
|
|
node _T_1037 = cat(_T_1036, _T_1029) @[el2_lib.scala 394:47]
|
|
node _T_1038 = cat(_T_778[16], _T_778[15]) @[el2_lib.scala 394:47]
|
|
node _T_1039 = cat(_T_778[18], _T_778[17]) @[el2_lib.scala 394:47]
|
|
node _T_1040 = cat(_T_1039, _T_1038) @[el2_lib.scala 394:47]
|
|
node _T_1041 = cat(_T_778[20], _T_778[19]) @[el2_lib.scala 394:47]
|
|
node _T_1042 = cat(_T_778[22], _T_778[21]) @[el2_lib.scala 394:47]
|
|
node _T_1043 = cat(_T_1042, _T_1041) @[el2_lib.scala 394:47]
|
|
node _T_1044 = cat(_T_1043, _T_1040) @[el2_lib.scala 394:47]
|
|
node _T_1045 = cat(_T_778[24], _T_778[23]) @[el2_lib.scala 394:47]
|
|
node _T_1046 = cat(_T_778[26], _T_778[25]) @[el2_lib.scala 394:47]
|
|
node _T_1047 = cat(_T_1046, _T_1045) @[el2_lib.scala 394:47]
|
|
node _T_1048 = cat(_T_778[28], _T_778[27]) @[el2_lib.scala 394:47]
|
|
node _T_1049 = cat(_T_778[30], _T_778[29]) @[el2_lib.scala 394:47]
|
|
node _T_1050 = cat(_T_1049, _T_1048) @[el2_lib.scala 394:47]
|
|
node _T_1051 = cat(_T_1050, _T_1047) @[el2_lib.scala 394:47]
|
|
node _T_1052 = cat(_T_1051, _T_1044) @[el2_lib.scala 394:47]
|
|
node _T_1053 = cat(_T_1052, _T_1037) @[el2_lib.scala 394:47]
|
|
node _T_1054 = xorr(_T_1053) @[el2_lib.scala 394:54]
|
|
node _T_1055 = cat(_T_777[2], _T_777[1]) @[el2_lib.scala 394:64]
|
|
node _T_1056 = cat(_T_1055, _T_777[0]) @[el2_lib.scala 394:64]
|
|
node _T_1057 = cat(_T_777[4], _T_777[3]) @[el2_lib.scala 394:64]
|
|
node _T_1058 = cat(_T_777[6], _T_777[5]) @[el2_lib.scala 394:64]
|
|
node _T_1059 = cat(_T_1058, _T_1057) @[el2_lib.scala 394:64]
|
|
node _T_1060 = cat(_T_1059, _T_1056) @[el2_lib.scala 394:64]
|
|
node _T_1061 = cat(_T_777[8], _T_777[7]) @[el2_lib.scala 394:64]
|
|
node _T_1062 = cat(_T_777[10], _T_777[9]) @[el2_lib.scala 394:64]
|
|
node _T_1063 = cat(_T_1062, _T_1061) @[el2_lib.scala 394:64]
|
|
node _T_1064 = cat(_T_777[12], _T_777[11]) @[el2_lib.scala 394:64]
|
|
node _T_1065 = cat(_T_777[14], _T_777[13]) @[el2_lib.scala 394:64]
|
|
node _T_1066 = cat(_T_1065, _T_1064) @[el2_lib.scala 394:64]
|
|
node _T_1067 = cat(_T_1066, _T_1063) @[el2_lib.scala 394:64]
|
|
node _T_1068 = cat(_T_1067, _T_1060) @[el2_lib.scala 394:64]
|
|
node _T_1069 = cat(_T_777[16], _T_777[15]) @[el2_lib.scala 394:64]
|
|
node _T_1070 = cat(_T_777[18], _T_777[17]) @[el2_lib.scala 394:64]
|
|
node _T_1071 = cat(_T_1070, _T_1069) @[el2_lib.scala 394:64]
|
|
node _T_1072 = cat(_T_777[20], _T_777[19]) @[el2_lib.scala 394:64]
|
|
node _T_1073 = cat(_T_777[22], _T_777[21]) @[el2_lib.scala 394:64]
|
|
node _T_1074 = cat(_T_1073, _T_1072) @[el2_lib.scala 394:64]
|
|
node _T_1075 = cat(_T_1074, _T_1071) @[el2_lib.scala 394:64]
|
|
node _T_1076 = cat(_T_777[24], _T_777[23]) @[el2_lib.scala 394:64]
|
|
node _T_1077 = cat(_T_777[26], _T_777[25]) @[el2_lib.scala 394:64]
|
|
node _T_1078 = cat(_T_1077, _T_1076) @[el2_lib.scala 394:64]
|
|
node _T_1079 = cat(_T_777[28], _T_777[27]) @[el2_lib.scala 394:64]
|
|
node _T_1080 = cat(_T_777[30], _T_777[29]) @[el2_lib.scala 394:64]
|
|
node _T_1081 = cat(_T_1080, _T_1079) @[el2_lib.scala 394:64]
|
|
node _T_1082 = cat(_T_1081, _T_1078) @[el2_lib.scala 394:64]
|
|
node _T_1083 = cat(_T_1082, _T_1075) @[el2_lib.scala 394:64]
|
|
node _T_1084 = cat(_T_1083, _T_1068) @[el2_lib.scala 394:64]
|
|
node _T_1085 = xorr(_T_1084) @[el2_lib.scala 394:71]
|
|
node _T_1086 = cat(_T_776[1], _T_776[0]) @[el2_lib.scala 394:81]
|
|
node _T_1087 = cat(_T_776[3], _T_776[2]) @[el2_lib.scala 394:81]
|
|
node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 394:81]
|
|
node _T_1089 = cat(_T_776[5], _T_776[4]) @[el2_lib.scala 394:81]
|
|
node _T_1090 = cat(_T_776[7], _T_776[6]) @[el2_lib.scala 394:81]
|
|
node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 394:81]
|
|
node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 394:81]
|
|
node _T_1093 = cat(_T_776[9], _T_776[8]) @[el2_lib.scala 394:81]
|
|
node _T_1094 = cat(_T_776[11], _T_776[10]) @[el2_lib.scala 394:81]
|
|
node _T_1095 = cat(_T_1094, _T_1093) @[el2_lib.scala 394:81]
|
|
node _T_1096 = cat(_T_776[13], _T_776[12]) @[el2_lib.scala 394:81]
|
|
node _T_1097 = cat(_T_776[16], _T_776[15]) @[el2_lib.scala 394:81]
|
|
node _T_1098 = cat(_T_1097, _T_776[14]) @[el2_lib.scala 394:81]
|
|
node _T_1099 = cat(_T_1098, _T_1096) @[el2_lib.scala 394:81]
|
|
node _T_1100 = cat(_T_1099, _T_1095) @[el2_lib.scala 394:81]
|
|
node _T_1101 = cat(_T_1100, _T_1092) @[el2_lib.scala 394:81]
|
|
node _T_1102 = cat(_T_776[18], _T_776[17]) @[el2_lib.scala 394:81]
|
|
node _T_1103 = cat(_T_776[20], _T_776[19]) @[el2_lib.scala 394:81]
|
|
node _T_1104 = cat(_T_1103, _T_1102) @[el2_lib.scala 394:81]
|
|
node _T_1105 = cat(_T_776[22], _T_776[21]) @[el2_lib.scala 394:81]
|
|
node _T_1106 = cat(_T_776[25], _T_776[24]) @[el2_lib.scala 394:81]
|
|
node _T_1107 = cat(_T_1106, _T_776[23]) @[el2_lib.scala 394:81]
|
|
node _T_1108 = cat(_T_1107, _T_1105) @[el2_lib.scala 394:81]
|
|
node _T_1109 = cat(_T_1108, _T_1104) @[el2_lib.scala 394:81]
|
|
node _T_1110 = cat(_T_776[27], _T_776[26]) @[el2_lib.scala 394:81]
|
|
node _T_1111 = cat(_T_776[29], _T_776[28]) @[el2_lib.scala 394:81]
|
|
node _T_1112 = cat(_T_1111, _T_1110) @[el2_lib.scala 394:81]
|
|
node _T_1113 = cat(_T_776[31], _T_776[30]) @[el2_lib.scala 394:81]
|
|
node _T_1114 = cat(_T_776[34], _T_776[33]) @[el2_lib.scala 394:81]
|
|
node _T_1115 = cat(_T_1114, _T_776[32]) @[el2_lib.scala 394:81]
|
|
node _T_1116 = cat(_T_1115, _T_1113) @[el2_lib.scala 394:81]
|
|
node _T_1117 = cat(_T_1116, _T_1112) @[el2_lib.scala 394:81]
|
|
node _T_1118 = cat(_T_1117, _T_1109) @[el2_lib.scala 394:81]
|
|
node _T_1119 = cat(_T_1118, _T_1101) @[el2_lib.scala 394:81]
|
|
node _T_1120 = xorr(_T_1119) @[el2_lib.scala 394:88]
|
|
node _T_1121 = cat(_T_775[1], _T_775[0]) @[el2_lib.scala 394:98]
|
|
node _T_1122 = cat(_T_775[3], _T_775[2]) @[el2_lib.scala 394:98]
|
|
node _T_1123 = cat(_T_1122, _T_1121) @[el2_lib.scala 394:98]
|
|
node _T_1124 = cat(_T_775[5], _T_775[4]) @[el2_lib.scala 394:98]
|
|
node _T_1125 = cat(_T_775[7], _T_775[6]) @[el2_lib.scala 394:98]
|
|
node _T_1126 = cat(_T_1125, _T_1124) @[el2_lib.scala 394:98]
|
|
node _T_1127 = cat(_T_1126, _T_1123) @[el2_lib.scala 394:98]
|
|
node _T_1128 = cat(_T_775[9], _T_775[8]) @[el2_lib.scala 394:98]
|
|
node _T_1129 = cat(_T_775[11], _T_775[10]) @[el2_lib.scala 394:98]
|
|
node _T_1130 = cat(_T_1129, _T_1128) @[el2_lib.scala 394:98]
|
|
node _T_1131 = cat(_T_775[13], _T_775[12]) @[el2_lib.scala 394:98]
|
|
node _T_1132 = cat(_T_775[16], _T_775[15]) @[el2_lib.scala 394:98]
|
|
node _T_1133 = cat(_T_1132, _T_775[14]) @[el2_lib.scala 394:98]
|
|
node _T_1134 = cat(_T_1133, _T_1131) @[el2_lib.scala 394:98]
|
|
node _T_1135 = cat(_T_1134, _T_1130) @[el2_lib.scala 394:98]
|
|
node _T_1136 = cat(_T_1135, _T_1127) @[el2_lib.scala 394:98]
|
|
node _T_1137 = cat(_T_775[18], _T_775[17]) @[el2_lib.scala 394:98]
|
|
node _T_1138 = cat(_T_775[20], _T_775[19]) @[el2_lib.scala 394:98]
|
|
node _T_1139 = cat(_T_1138, _T_1137) @[el2_lib.scala 394:98]
|
|
node _T_1140 = cat(_T_775[22], _T_775[21]) @[el2_lib.scala 394:98]
|
|
node _T_1141 = cat(_T_775[25], _T_775[24]) @[el2_lib.scala 394:98]
|
|
node _T_1142 = cat(_T_1141, _T_775[23]) @[el2_lib.scala 394:98]
|
|
node _T_1143 = cat(_T_1142, _T_1140) @[el2_lib.scala 394:98]
|
|
node _T_1144 = cat(_T_1143, _T_1139) @[el2_lib.scala 394:98]
|
|
node _T_1145 = cat(_T_775[27], _T_775[26]) @[el2_lib.scala 394:98]
|
|
node _T_1146 = cat(_T_775[29], _T_775[28]) @[el2_lib.scala 394:98]
|
|
node _T_1147 = cat(_T_1146, _T_1145) @[el2_lib.scala 394:98]
|
|
node _T_1148 = cat(_T_775[31], _T_775[30]) @[el2_lib.scala 394:98]
|
|
node _T_1149 = cat(_T_775[34], _T_775[33]) @[el2_lib.scala 394:98]
|
|
node _T_1150 = cat(_T_1149, _T_775[32]) @[el2_lib.scala 394:98]
|
|
node _T_1151 = cat(_T_1150, _T_1148) @[el2_lib.scala 394:98]
|
|
node _T_1152 = cat(_T_1151, _T_1147) @[el2_lib.scala 394:98]
|
|
node _T_1153 = cat(_T_1152, _T_1144) @[el2_lib.scala 394:98]
|
|
node _T_1154 = cat(_T_1153, _T_1136) @[el2_lib.scala 394:98]
|
|
node _T_1155 = xorr(_T_1154) @[el2_lib.scala 394:105]
|
|
node _T_1156 = cat(_T_774[1], _T_774[0]) @[el2_lib.scala 394:115]
|
|
node _T_1157 = cat(_T_774[3], _T_774[2]) @[el2_lib.scala 394:115]
|
|
node _T_1158 = cat(_T_1157, _T_1156) @[el2_lib.scala 394:115]
|
|
node _T_1159 = cat(_T_774[5], _T_774[4]) @[el2_lib.scala 394:115]
|
|
node _T_1160 = cat(_T_774[7], _T_774[6]) @[el2_lib.scala 394:115]
|
|
node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 394:115]
|
|
node _T_1162 = cat(_T_1161, _T_1158) @[el2_lib.scala 394:115]
|
|
node _T_1163 = cat(_T_774[9], _T_774[8]) @[el2_lib.scala 394:115]
|
|
node _T_1164 = cat(_T_774[11], _T_774[10]) @[el2_lib.scala 394:115]
|
|
node _T_1165 = cat(_T_1164, _T_1163) @[el2_lib.scala 394:115]
|
|
node _T_1166 = cat(_T_774[13], _T_774[12]) @[el2_lib.scala 394:115]
|
|
node _T_1167 = cat(_T_774[16], _T_774[15]) @[el2_lib.scala 394:115]
|
|
node _T_1168 = cat(_T_1167, _T_774[14]) @[el2_lib.scala 394:115]
|
|
node _T_1169 = cat(_T_1168, _T_1166) @[el2_lib.scala 394:115]
|
|
node _T_1170 = cat(_T_1169, _T_1165) @[el2_lib.scala 394:115]
|
|
node _T_1171 = cat(_T_1170, _T_1162) @[el2_lib.scala 394:115]
|
|
node _T_1172 = cat(_T_774[18], _T_774[17]) @[el2_lib.scala 394:115]
|
|
node _T_1173 = cat(_T_774[20], _T_774[19]) @[el2_lib.scala 394:115]
|
|
node _T_1174 = cat(_T_1173, _T_1172) @[el2_lib.scala 394:115]
|
|
node _T_1175 = cat(_T_774[22], _T_774[21]) @[el2_lib.scala 394:115]
|
|
node _T_1176 = cat(_T_774[25], _T_774[24]) @[el2_lib.scala 394:115]
|
|
node _T_1177 = cat(_T_1176, _T_774[23]) @[el2_lib.scala 394:115]
|
|
node _T_1178 = cat(_T_1177, _T_1175) @[el2_lib.scala 394:115]
|
|
node _T_1179 = cat(_T_1178, _T_1174) @[el2_lib.scala 394:115]
|
|
node _T_1180 = cat(_T_774[27], _T_774[26]) @[el2_lib.scala 394:115]
|
|
node _T_1181 = cat(_T_774[29], _T_774[28]) @[el2_lib.scala 394:115]
|
|
node _T_1182 = cat(_T_1181, _T_1180) @[el2_lib.scala 394:115]
|
|
node _T_1183 = cat(_T_774[31], _T_774[30]) @[el2_lib.scala 394:115]
|
|
node _T_1184 = cat(_T_774[34], _T_774[33]) @[el2_lib.scala 394:115]
|
|
node _T_1185 = cat(_T_1184, _T_774[32]) @[el2_lib.scala 394:115]
|
|
node _T_1186 = cat(_T_1185, _T_1183) @[el2_lib.scala 394:115]
|
|
node _T_1187 = cat(_T_1186, _T_1182) @[el2_lib.scala 394:115]
|
|
node _T_1188 = cat(_T_1187, _T_1179) @[el2_lib.scala 394:115]
|
|
node _T_1189 = cat(_T_1188, _T_1171) @[el2_lib.scala 394:115]
|
|
node _T_1190 = xorr(_T_1189) @[el2_lib.scala 394:122]
|
|
node _T_1191 = cat(_T_1120, _T_1155) @[Cat.scala 29:58]
|
|
node _T_1192 = cat(_T_1191, _T_1190) @[Cat.scala 29:58]
|
|
node _T_1193 = cat(_T_1054, _T_1085) @[Cat.scala 29:58]
|
|
node _T_1194 = cat(_T_992, _T_1023) @[Cat.scala 29:58]
|
|
node _T_1195 = cat(_T_1194, _T_1193) @[Cat.scala 29:58]
|
|
node ic_miss_buff_ecc = cat(_T_1195, _T_1192) @[Cat.scala 29:58]
|
|
wire ic_wr_16bytes_data : UInt<142>
|
|
ic_wr_16bytes_data <= UInt<1>("h00")
|
|
node _T_1196 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 345:72]
|
|
node _T_1197 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 345:72]
|
|
io.ic_wr_data[0] <= _T_1196 @[el2_ifu_mem_ctl.scala 345:17]
|
|
io.ic_wr_data[1] <= _T_1197 @[el2_ifu_mem_ctl.scala 345:17]
|
|
io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 346:23]
|
|
wire ic_rd_parity_final_err : UInt<1>
|
|
ic_rd_parity_final_err <= UInt<1>("h00")
|
|
node _T_1198 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 348:56]
|
|
node _T_1199 = and(_T_1198, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 348:83]
|
|
node _T_1200 = or(_T_1199, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 348:99]
|
|
io.ic_error_start <= _T_1200 @[el2_ifu_mem_ctl.scala 348:21]
|
|
wire ic_debug_tag_val_rd_out : UInt<1>
|
|
ic_debug_tag_val_rd_out <= UInt<1>("h00")
|
|
wire ic_debug_ict_array_sel_ff : UInt<1>
|
|
ic_debug_ict_array_sel_ff <= UInt<1>("h00")
|
|
node _T_1201 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 351:63]
|
|
node _T_1202 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 351:121]
|
|
node _T_1203 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 351:161]
|
|
node _T_1204 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
|
|
node _T_1205 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
|
|
node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 29:58]
|
|
node _T_1207 = cat(UInt<32>("h00"), _T_1203) @[Cat.scala 29:58]
|
|
node _T_1208 = cat(UInt<2>("h00"), _T_1202) @[Cat.scala 29:58]
|
|
node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 29:58]
|
|
node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 29:58]
|
|
node ifu_ic_debug_rd_data_in = mux(_T_1201, _T_1210, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 351:36]
|
|
reg _T_1211 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 354:63]
|
|
_T_1211 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 354:63]
|
|
io.ifu_ic_debug_rd_data <= _T_1211 @[el2_ifu_mem_ctl.scala 354:27]
|
|
node _T_1212 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 355:74]
|
|
node _T_1213 = xorr(_T_1212) @[el2_lib.scala 201:13]
|
|
node _T_1214 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 355:74]
|
|
node _T_1215 = xorr(_T_1214) @[el2_lib.scala 201:13]
|
|
node _T_1216 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 355:74]
|
|
node _T_1217 = xorr(_T_1216) @[el2_lib.scala 201:13]
|
|
node _T_1218 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 355:74]
|
|
node _T_1219 = xorr(_T_1218) @[el2_lib.scala 201:13]
|
|
node _T_1220 = cat(_T_1219, _T_1217) @[Cat.scala 29:58]
|
|
node _T_1221 = cat(_T_1220, _T_1215) @[Cat.scala 29:58]
|
|
node ic_wr_parity = cat(_T_1221, _T_1213) @[Cat.scala 29:58]
|
|
node _T_1222 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 356:82]
|
|
node _T_1223 = xorr(_T_1222) @[el2_lib.scala 201:13]
|
|
node _T_1224 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 356:82]
|
|
node _T_1225 = xorr(_T_1224) @[el2_lib.scala 201:13]
|
|
node _T_1226 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 356:82]
|
|
node _T_1227 = xorr(_T_1226) @[el2_lib.scala 201:13]
|
|
node _T_1228 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 356:82]
|
|
node _T_1229 = xorr(_T_1228) @[el2_lib.scala 201:13]
|
|
node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 29:58]
|
|
node _T_1231 = cat(_T_1230, _T_1225) @[Cat.scala 29:58]
|
|
node ic_miss_buff_parity = cat(_T_1231, _T_1223) @[Cat.scala 29:58]
|
|
node _T_1232 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 358:43]
|
|
node _T_1233 = bits(_T_1232, 0, 0) @[el2_ifu_mem_ctl.scala 358:47]
|
|
node _T_1234 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1235 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1236 = cat(_T_1235, _T_1234) @[Cat.scala 29:58]
|
|
node _T_1237 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1238 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1239 = cat(_T_1238, _T_1237) @[Cat.scala 29:58]
|
|
node _T_1240 = mux(_T_1233, _T_1236, _T_1239) @[el2_ifu_mem_ctl.scala 358:28]
|
|
ic_wr_16bytes_data <= _T_1240 @[el2_ifu_mem_ctl.scala 358:22]
|
|
wire bus_ifu_wr_data_error_ff : UInt<1>
|
|
bus_ifu_wr_data_error_ff <= UInt<1>("h00")
|
|
wire ifu_wr_data_comb_err_ff : UInt<1>
|
|
ifu_wr_data_comb_err_ff <= UInt<1>("h00")
|
|
wire reset_beat_cnt : UInt<1>
|
|
reset_beat_cnt <= UInt<1>("h00")
|
|
node _T_1241 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 365:53]
|
|
node _T_1242 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 365:82]
|
|
node ifu_wr_cumulative_err = and(_T_1241, _T_1242) @[el2_ifu_mem_ctl.scala 365:80]
|
|
node _T_1243 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 366:55]
|
|
ifu_wr_cumulative_err_data <= _T_1243 @[el2_ifu_mem_ctl.scala 366:30]
|
|
reg _T_1244 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 367:61]
|
|
_T_1244 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 367:61]
|
|
ifu_wr_data_comb_err_ff <= _T_1244 @[el2_ifu_mem_ctl.scala 367:27]
|
|
wire ic_crit_wd_rdy : UInt<1>
|
|
ic_crit_wd_rdy <= UInt<1>("h00")
|
|
wire ifu_byp_data_err_new : UInt<1>
|
|
ifu_byp_data_err_new <= UInt<1>("h00")
|
|
node _T_1245 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 370:51]
|
|
node _T_1246 = or(ic_crit_wd_rdy, _T_1245) @[el2_ifu_mem_ctl.scala 370:38]
|
|
node _T_1247 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 370:77]
|
|
node _T_1248 = or(_T_1246, _T_1247) @[el2_ifu_mem_ctl.scala 370:64]
|
|
node _T_1249 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 370:98]
|
|
node sel_byp_data = and(_T_1248, _T_1249) @[el2_ifu_mem_ctl.scala 370:96]
|
|
node _T_1250 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 371:51]
|
|
node _T_1251 = or(ic_crit_wd_rdy, _T_1250) @[el2_ifu_mem_ctl.scala 371:38]
|
|
node _T_1252 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 371:77]
|
|
node _T_1253 = or(_T_1251, _T_1252) @[el2_ifu_mem_ctl.scala 371:64]
|
|
node _T_1254 = eq(_T_1253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 371:21]
|
|
node _T_1255 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 371:98]
|
|
node sel_ic_data = and(_T_1254, _T_1255) @[el2_ifu_mem_ctl.scala 371:96]
|
|
wire ic_byp_data_only_new : UInt<80>
|
|
ic_byp_data_only_new <= UInt<1>("h00")
|
|
node _T_1256 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 375:81]
|
|
node _T_1257 = or(sel_byp_data, _T_1256) @[el2_ifu_mem_ctl.scala 375:47]
|
|
node _T_1258 = bits(_T_1257, 0, 0) @[el2_ifu_mem_ctl.scala 375:140]
|
|
node _T_1259 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1260 = mux(_T_1259, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1261 = and(_T_1260, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 377:69]
|
|
node _T_1262 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1263 = mux(_T_1262, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1264 = and(_T_1263, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 377:114]
|
|
node ic_premux_data_temp = or(_T_1261, _T_1264) @[el2_ifu_mem_ctl.scala 377:88]
|
|
node ic_sel_premux_data_temp = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 379:63]
|
|
io.ic_premux_data <= ic_premux_data_temp @[el2_ifu_mem_ctl.scala 380:21]
|
|
io.ic_sel_premux_data <= ic_sel_premux_data_temp @[el2_ifu_mem_ctl.scala 381:25]
|
|
node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 382:42]
|
|
io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 383:16]
|
|
node _T_1265 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 384:40]
|
|
node fetch_req_f_qual = and(io.ic_hit_f, _T_1265) @[el2_ifu_mem_ctl.scala 384:38]
|
|
wire ifc_region_acc_fault_memory_f : UInt<1>
|
|
ifc_region_acc_fault_memory_f <= UInt<1>("h00")
|
|
node _T_1266 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 386:57]
|
|
node _T_1267 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 386:82]
|
|
node _T_1268 = and(_T_1266, _T_1267) @[el2_ifu_mem_ctl.scala 386:80]
|
|
io.ic_access_fault_f <= _T_1268 @[el2_ifu_mem_ctl.scala 386:24]
|
|
node _T_1269 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 387:62]
|
|
node _T_1270 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 388:32]
|
|
node _T_1271 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 389:47]
|
|
node _T_1272 = mux(_T_1271, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 389:10]
|
|
node _T_1273 = mux(_T_1270, UInt<2>("h02"), _T_1272) @[el2_ifu_mem_ctl.scala 388:8]
|
|
node _T_1274 = mux(_T_1269, UInt<1>("h01"), _T_1273) @[el2_ifu_mem_ctl.scala 387:35]
|
|
io.ic_access_fault_type_f <= _T_1274 @[el2_ifu_mem_ctl.scala 387:29]
|
|
node _T_1275 = and(fetch_req_f_qual, io.ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 390:45]
|
|
node _T_1276 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1277 = eq(vaddr_f, _T_1276) @[el2_ifu_mem_ctl.scala 390:80]
|
|
node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 390:71]
|
|
node _T_1279 = and(_T_1275, _T_1278) @[el2_ifu_mem_ctl.scala 390:69]
|
|
node _T_1280 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 390:131]
|
|
node _T_1281 = and(_T_1279, _T_1280) @[el2_ifu_mem_ctl.scala 390:114]
|
|
node _T_1282 = cat(_T_1281, fetch_req_f_qual) @[Cat.scala 29:58]
|
|
io.ic_fetch_val_f <= _T_1282 @[el2_ifu_mem_ctl.scala 390:21]
|
|
node _T_1283 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 391:36]
|
|
node two_byte_instr = neq(_T_1283, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 391:42]
|
|
wire ic_miss_buff_data_in : UInt<64>
|
|
ic_miss_buff_data_in <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_tag : UInt<3>
|
|
ifu_bus_rsp_tag <= UInt<1>("h00")
|
|
wire bus_ifu_wr_en : UInt<1>
|
|
bus_ifu_wr_en <= UInt<1>("h00")
|
|
node _T_1284 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_0 = and(bus_ifu_wr_en, _T_1284) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1285 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_1 = and(bus_ifu_wr_en, _T_1285) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1286 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_2 = and(bus_ifu_wr_en, _T_1286) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1287 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_3 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1288 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_4 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1289 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_5 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1290 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_6 = and(bus_ifu_wr_en, _T_1290) @[el2_ifu_mem_ctl.scala 397:73]
|
|
node _T_1291 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 397:91]
|
|
node write_fill_data_7 = and(bus_ifu_wr_en, _T_1291) @[el2_ifu_mem_ctl.scala 397:73]
|
|
wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 398:31]
|
|
node _T_1292 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1293 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1294 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1293 : @[Reg.scala 28:19]
|
|
_T_1294 <= _T_1292 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[0] <= _T_1294 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1295 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1296 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1296 : @[Reg.scala 28:19]
|
|
_T_1297 <= _T_1295 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[1] <= _T_1297 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1298 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1299 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1299 : @[Reg.scala 28:19]
|
|
_T_1300 <= _T_1298 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[2] <= _T_1300 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1301 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1302 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1302 : @[Reg.scala 28:19]
|
|
_T_1303 <= _T_1301 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[3] <= _T_1303 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1304 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1305 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1305 : @[Reg.scala 28:19]
|
|
_T_1306 <= _T_1304 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[4] <= _T_1306 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1307 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1308 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1308 : @[Reg.scala 28:19]
|
|
_T_1309 <= _T_1307 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[5] <= _T_1309 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1310 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1311 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1311 : @[Reg.scala 28:19]
|
|
_T_1312 <= _T_1310 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[6] <= _T_1312 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1313 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1314 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1315 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1314 : @[Reg.scala 28:19]
|
|
_T_1315 <= _T_1313 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[7] <= _T_1315 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1316 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1317 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1317 : @[Reg.scala 28:19]
|
|
_T_1318 <= _T_1316 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[8] <= _T_1318 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1319 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1320 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1320 : @[Reg.scala 28:19]
|
|
_T_1321 <= _T_1319 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[9] <= _T_1321 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1322 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1323 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1323 : @[Reg.scala 28:19]
|
|
_T_1324 <= _T_1322 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[10] <= _T_1324 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1325 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1326 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1327 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1326 : @[Reg.scala 28:19]
|
|
_T_1327 <= _T_1325 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[11] <= _T_1327 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1328 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1329 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1330 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1329 : @[Reg.scala 28:19]
|
|
_T_1330 <= _T_1328 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[12] <= _T_1330 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1331 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1332 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1332 : @[Reg.scala 28:19]
|
|
_T_1333 <= _T_1331 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[13] <= _T_1333 @[el2_ifu_mem_ctl.scala 401:28]
|
|
node _T_1334 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 400:59]
|
|
node _T_1335 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 400:97]
|
|
reg _T_1336 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1335 : @[Reg.scala 28:19]
|
|
_T_1336 <= _T_1334 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[14] <= _T_1336 @[el2_ifu_mem_ctl.scala 400:26]
|
|
node _T_1337 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 401:61]
|
|
node _T_1338 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 401:100]
|
|
reg _T_1339 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1338 : @[Reg.scala 28:19]
|
|
_T_1339 <= _T_1337 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[15] <= _T_1339 @[el2_ifu_mem_ctl.scala 401:28]
|
|
wire ic_miss_buff_data_valid : UInt<8>
|
|
ic_miss_buff_data_valid <= UInt<1>("h00")
|
|
node _T_1340 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1341 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1342 = and(_T_1340, _T_1341) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1342) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1343 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1344 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1345 = and(_T_1343, _T_1344) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1345) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1346 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1347 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1348 = and(_T_1346, _T_1347) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1348) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1349 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1350 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1351 = and(_T_1349, _T_1350) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1351) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1352 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1353 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1354 = and(_T_1352, _T_1353) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1354) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1355 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1356 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1357 = and(_T_1355, _T_1356) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1357) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1358 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1359 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1360 = and(_T_1358, _T_1359) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1360) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1361 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 403:113]
|
|
node _T_1362 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:118]
|
|
node _T_1363 = and(_T_1361, _T_1362) @[el2_ifu_mem_ctl.scala 403:116]
|
|
node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1363) @[el2_ifu_mem_ctl.scala 403:88]
|
|
node _T_1364 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58]
|
|
node _T_1365 = cat(_T_1364, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58]
|
|
node _T_1366 = cat(_T_1365, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58]
|
|
node _T_1367 = cat(_T_1366, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58]
|
|
node _T_1368 = cat(_T_1367, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58]
|
|
node _T_1369 = cat(_T_1368, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58]
|
|
node _T_1370 = cat(_T_1369, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58]
|
|
reg _T_1371 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 404:60]
|
|
_T_1371 <= _T_1370 @[el2_ifu_mem_ctl.scala 404:60]
|
|
ic_miss_buff_data_valid <= _T_1371 @[el2_ifu_mem_ctl.scala 404:27]
|
|
wire bus_ifu_wr_data_error : UInt<1>
|
|
bus_ifu_wr_data_error <= UInt<1>("h00")
|
|
wire ic_miss_buff_data_error : UInt<8>
|
|
ic_miss_buff_data_error <= UInt<1>("h00")
|
|
node _T_1372 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
|
|
node _T_1373 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 408:28]
|
|
node _T_1374 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
|
|
node _T_1375 = and(_T_1373, _T_1374) @[el2_ifu_mem_ctl.scala 408:32]
|
|
node ic_miss_buff_data_error_in_0 = mux(_T_1372, bus_ifu_wr_data_error, _T_1375) @[el2_ifu_mem_ctl.scala 407:72]
|
|
node _T_1376 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
|
|
node _T_1377 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 408:28]
|
|
node _T_1378 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
|
|
node _T_1379 = and(_T_1377, _T_1378) @[el2_ifu_mem_ctl.scala 408:32]
|
|
node ic_miss_buff_data_error_in_1 = mux(_T_1376, bus_ifu_wr_data_error, _T_1379) @[el2_ifu_mem_ctl.scala 407:72]
|
|
node _T_1380 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1381 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 408:28]
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node _T_1382 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1383 = and(_T_1381, _T_1382) @[el2_ifu_mem_ctl.scala 408:32]
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node ic_miss_buff_data_error_in_2 = mux(_T_1380, bus_ifu_wr_data_error, _T_1383) @[el2_ifu_mem_ctl.scala 407:72]
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node _T_1384 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1385 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 408:28]
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node _T_1386 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1387 = and(_T_1385, _T_1386) @[el2_ifu_mem_ctl.scala 408:32]
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node ic_miss_buff_data_error_in_3 = mux(_T_1384, bus_ifu_wr_data_error, _T_1387) @[el2_ifu_mem_ctl.scala 407:72]
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node _T_1388 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1389 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 408:28]
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node _T_1390 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1391 = and(_T_1389, _T_1390) @[el2_ifu_mem_ctl.scala 408:32]
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node ic_miss_buff_data_error_in_4 = mux(_T_1388, bus_ifu_wr_data_error, _T_1391) @[el2_ifu_mem_ctl.scala 407:72]
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node _T_1392 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1393 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 408:28]
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node _T_1394 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1395 = and(_T_1393, _T_1394) @[el2_ifu_mem_ctl.scala 408:32]
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node ic_miss_buff_data_error_in_5 = mux(_T_1392, bus_ifu_wr_data_error, _T_1395) @[el2_ifu_mem_ctl.scala 407:72]
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node _T_1396 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1397 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 408:28]
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node _T_1398 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1399 = and(_T_1397, _T_1398) @[el2_ifu_mem_ctl.scala 408:32]
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node ic_miss_buff_data_error_in_6 = mux(_T_1396, bus_ifu_wr_data_error, _T_1399) @[el2_ifu_mem_ctl.scala 407:72]
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node _T_1400 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 407:92]
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node _T_1401 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 408:28]
|
|
node _T_1402 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:34]
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node _T_1403 = and(_T_1401, _T_1402) @[el2_ifu_mem_ctl.scala 408:32]
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|
node ic_miss_buff_data_error_in_7 = mux(_T_1400, bus_ifu_wr_data_error, _T_1403) @[el2_ifu_mem_ctl.scala 407:72]
|
|
node _T_1404 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58]
|
|
node _T_1405 = cat(_T_1404, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58]
|
|
node _T_1406 = cat(_T_1405, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58]
|
|
node _T_1407 = cat(_T_1406, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58]
|
|
node _T_1408 = cat(_T_1407, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58]
|
|
node _T_1409 = cat(_T_1408, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58]
|
|
node _T_1410 = cat(_T_1409, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58]
|
|
reg _T_1411 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 409:60]
|
|
_T_1411 <= _T_1410 @[el2_ifu_mem_ctl.scala 409:60]
|
|
ic_miss_buff_data_error <= _T_1411 @[el2_ifu_mem_ctl.scala 409:27]
|
|
node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 412:28]
|
|
node _T_1412 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 413:42]
|
|
node _T_1413 = add(_T_1412, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 413:70]
|
|
node bypass_index_5_3_inc = tail(_T_1413, 1) @[el2_ifu_mem_ctl.scala 413:70]
|
|
node _T_1414 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1416 = bits(_T_1415, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1417 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1418 = eq(_T_1417, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1419 = bits(_T_1418, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1420 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1421 = eq(_T_1420, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1422 = bits(_T_1421, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1423 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1424 = eq(_T_1423, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1425 = bits(_T_1424, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1426 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1427 = eq(_T_1426, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1428 = bits(_T_1427, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1429 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1430 = eq(_T_1429, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1431 = bits(_T_1430, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1432 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1433 = eq(_T_1432, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1434 = bits(_T_1433, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1435 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:87]
|
|
node _T_1436 = eq(_T_1435, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 414:114]
|
|
node _T_1437 = bits(_T_1436, 0, 0) @[el2_ifu_mem_ctl.scala 414:122]
|
|
node _T_1438 = mux(_T_1416, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1439 = mux(_T_1419, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1440 = mux(_T_1422, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1441 = mux(_T_1425, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1442 = mux(_T_1428, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1443 = mux(_T_1431, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1444 = mux(_T_1434, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1445 = mux(_T_1437, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1446 = or(_T_1438, _T_1439) @[Mux.scala 27:72]
|
|
node _T_1447 = or(_T_1446, _T_1440) @[Mux.scala 27:72]
|
|
node _T_1448 = or(_T_1447, _T_1441) @[Mux.scala 27:72]
|
|
node _T_1449 = or(_T_1448, _T_1442) @[Mux.scala 27:72]
|
|
node _T_1450 = or(_T_1449, _T_1443) @[Mux.scala 27:72]
|
|
node _T_1451 = or(_T_1450, _T_1444) @[Mux.scala 27:72]
|
|
node _T_1452 = or(_T_1451, _T_1445) @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72]
|
|
bypass_valid_value_check <= _T_1452 @[Mux.scala 27:72]
|
|
node _T_1453 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 415:71]
|
|
node _T_1454 = eq(_T_1453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 415:58]
|
|
node _T_1455 = and(bypass_valid_value_check, _T_1454) @[el2_ifu_mem_ctl.scala 415:56]
|
|
node _T_1456 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 415:90]
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|
node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 415:77]
|
|
node _T_1458 = and(_T_1455, _T_1457) @[el2_ifu_mem_ctl.scala 415:75]
|
|
node _T_1459 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 416:71]
|
|
node _T_1460 = eq(_T_1459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:58]
|
|
node _T_1461 = and(bypass_valid_value_check, _T_1460) @[el2_ifu_mem_ctl.scala 416:56]
|
|
node _T_1462 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 416:89]
|
|
node _T_1463 = and(_T_1461, _T_1462) @[el2_ifu_mem_ctl.scala 416:75]
|
|
node _T_1464 = or(_T_1458, _T_1463) @[el2_ifu_mem_ctl.scala 415:95]
|
|
node _T_1465 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 417:70]
|
|
node _T_1466 = and(bypass_valid_value_check, _T_1465) @[el2_ifu_mem_ctl.scala 417:56]
|
|
node _T_1467 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 417:89]
|
|
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:76]
|
|
node _T_1469 = and(_T_1466, _T_1468) @[el2_ifu_mem_ctl.scala 417:74]
|
|
node _T_1470 = or(_T_1464, _T_1469) @[el2_ifu_mem_ctl.scala 416:94]
|
|
node _T_1471 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 418:47]
|
|
node _T_1472 = and(bypass_valid_value_check, _T_1471) @[el2_ifu_mem_ctl.scala 418:33]
|
|
node _T_1473 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 418:65]
|
|
node _T_1474 = and(_T_1472, _T_1473) @[el2_ifu_mem_ctl.scala 418:51]
|
|
node _T_1475 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1476 = bits(_T_1475, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1477 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1478 = bits(_T_1477, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1479 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1480 = bits(_T_1479, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1481 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1482 = bits(_T_1481, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1483 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1484 = bits(_T_1483, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1485 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1486 = bits(_T_1485, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1487 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1488 = bits(_T_1487, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1489 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 418:132]
|
|
node _T_1490 = bits(_T_1489, 0, 0) @[el2_ifu_mem_ctl.scala 418:140]
|
|
node _T_1491 = mux(_T_1476, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1492 = mux(_T_1478, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1493 = mux(_T_1480, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1494 = mux(_T_1482, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1495 = mux(_T_1484, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1496 = mux(_T_1486, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1497 = mux(_T_1488, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1498 = mux(_T_1490, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1499 = or(_T_1491, _T_1492) @[Mux.scala 27:72]
|
|
node _T_1500 = or(_T_1499, _T_1493) @[Mux.scala 27:72]
|
|
node _T_1501 = or(_T_1500, _T_1494) @[Mux.scala 27:72]
|
|
node _T_1502 = or(_T_1501, _T_1495) @[Mux.scala 27:72]
|
|
node _T_1503 = or(_T_1502, _T_1496) @[Mux.scala 27:72]
|
|
node _T_1504 = or(_T_1503, _T_1497) @[Mux.scala 27:72]
|
|
node _T_1505 = or(_T_1504, _T_1498) @[Mux.scala 27:72]
|
|
wire _T_1506 : UInt<1> @[Mux.scala 27:72]
|
|
_T_1506 <= _T_1505 @[Mux.scala 27:72]
|
|
node _T_1507 = and(_T_1474, _T_1506) @[el2_ifu_mem_ctl.scala 418:69]
|
|
node _T_1508 = or(_T_1470, _T_1507) @[el2_ifu_mem_ctl.scala 417:94]
|
|
node _T_1509 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 419:70]
|
|
node _T_1510 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1511 = eq(_T_1509, _T_1510) @[el2_ifu_mem_ctl.scala 419:95]
|
|
node _T_1512 = and(bypass_valid_value_check, _T_1511) @[el2_ifu_mem_ctl.scala 419:56]
|
|
node bypass_data_ready_in = or(_T_1508, _T_1512) @[el2_ifu_mem_ctl.scala 418:181]
|
|
wire ic_crit_wd_rdy_new_ff : UInt<1>
|
|
ic_crit_wd_rdy_new_ff <= UInt<1>("h00")
|
|
node _T_1513 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 423:53]
|
|
node _T_1514 = and(_T_1513, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 423:73]
|
|
node _T_1515 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 423:98]
|
|
node _T_1516 = and(_T_1514, _T_1515) @[el2_ifu_mem_ctl.scala 423:96]
|
|
node _T_1517 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 423:120]
|
|
node _T_1518 = and(_T_1516, _T_1517) @[el2_ifu_mem_ctl.scala 423:118]
|
|
node _T_1519 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 424:75]
|
|
node _T_1520 = and(crit_wd_byp_ok_ff, _T_1519) @[el2_ifu_mem_ctl.scala 424:73]
|
|
node _T_1521 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 424:98]
|
|
node _T_1522 = and(_T_1520, _T_1521) @[el2_ifu_mem_ctl.scala 424:96]
|
|
node _T_1523 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 424:120]
|
|
node _T_1524 = and(_T_1522, _T_1523) @[el2_ifu_mem_ctl.scala 424:118]
|
|
node _T_1525 = or(_T_1518, _T_1524) @[el2_ifu_mem_ctl.scala 423:143]
|
|
node _T_1526 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 425:54]
|
|
node _T_1527 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:76]
|
|
node _T_1528 = and(_T_1526, _T_1527) @[el2_ifu_mem_ctl.scala 425:74]
|
|
node _T_1529 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:98]
|
|
node _T_1530 = and(_T_1528, _T_1529) @[el2_ifu_mem_ctl.scala 425:96]
|
|
node ic_crit_wd_rdy_new_in = or(_T_1525, _T_1530) @[el2_ifu_mem_ctl.scala 424:143]
|
|
reg _T_1531 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 426:58]
|
|
_T_1531 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 426:58]
|
|
ic_crit_wd_rdy_new_ff <= _T_1531 @[el2_ifu_mem_ctl.scala 426:25]
|
|
node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 427:45]
|
|
node _T_1532 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 428:51]
|
|
node byp_fetch_index_0 = cat(_T_1532, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_1533 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 429:51]
|
|
node byp_fetch_index_1 = cat(_T_1533, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1534 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 430:49]
|
|
node _T_1535 = add(_T_1534, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 430:75]
|
|
node byp_fetch_index_inc = tail(_T_1535, 1) @[el2_ifu_mem_ctl.scala 430:75]
|
|
node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1536 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1537 = eq(_T_1536, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1538 = bits(_T_1537, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1539 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1540 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1541 = eq(_T_1540, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1542 = bits(_T_1541, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1543 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1544 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1545 = eq(_T_1544, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1546 = bits(_T_1545, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1547 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1548 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1549 = eq(_T_1548, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1550 = bits(_T_1549, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1551 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1552 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1553 = eq(_T_1552, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1554 = bits(_T_1553, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1555 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1556 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1557 = eq(_T_1556, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1558 = bits(_T_1557, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1559 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1560 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1561 = eq(_T_1560, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1562 = bits(_T_1561, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1563 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1564 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 433:93]
|
|
node _T_1565 = eq(_T_1564, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 433:118]
|
|
node _T_1566 = bits(_T_1565, 0, 0) @[el2_ifu_mem_ctl.scala 433:126]
|
|
node _T_1567 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 433:157]
|
|
node _T_1568 = mux(_T_1538, _T_1539, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1569 = mux(_T_1542, _T_1543, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1570 = mux(_T_1546, _T_1547, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1571 = mux(_T_1550, _T_1551, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1572 = mux(_T_1554, _T_1555, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1573 = mux(_T_1558, _T_1559, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1574 = mux(_T_1562, _T_1563, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1575 = mux(_T_1566, _T_1567, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1576 = or(_T_1568, _T_1569) @[Mux.scala 27:72]
|
|
node _T_1577 = or(_T_1576, _T_1570) @[Mux.scala 27:72]
|
|
node _T_1578 = or(_T_1577, _T_1571) @[Mux.scala 27:72]
|
|
node _T_1579 = or(_T_1578, _T_1572) @[Mux.scala 27:72]
|
|
node _T_1580 = or(_T_1579, _T_1573) @[Mux.scala 27:72]
|
|
node _T_1581 = or(_T_1580, _T_1574) @[Mux.scala 27:72]
|
|
node _T_1582 = or(_T_1581, _T_1575) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass <= _T_1582 @[Mux.scala 27:72]
|
|
node _T_1583 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1584 = bits(_T_1583, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1585 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1586 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1587 = bits(_T_1586, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1588 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1589 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1590 = bits(_T_1589, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1591 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1592 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1593 = bits(_T_1592, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1594 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1595 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1596 = bits(_T_1595, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1597 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1598 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1599 = bits(_T_1598, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1600 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1601 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1602 = bits(_T_1601, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1603 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1604 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 434:104]
|
|
node _T_1605 = bits(_T_1604, 0, 0) @[el2_ifu_mem_ctl.scala 434:112]
|
|
node _T_1606 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 434:143]
|
|
node _T_1607 = mux(_T_1584, _T_1585, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1608 = mux(_T_1587, _T_1588, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1609 = mux(_T_1590, _T_1591, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1610 = mux(_T_1593, _T_1594, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1611 = mux(_T_1596, _T_1597, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1612 = mux(_T_1599, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1613 = mux(_T_1602, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1614 = mux(_T_1605, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1615 = or(_T_1607, _T_1608) @[Mux.scala 27:72]
|
|
node _T_1616 = or(_T_1615, _T_1609) @[Mux.scala 27:72]
|
|
node _T_1617 = or(_T_1616, _T_1610) @[Mux.scala 27:72]
|
|
node _T_1618 = or(_T_1617, _T_1611) @[Mux.scala 27:72]
|
|
node _T_1619 = or(_T_1618, _T_1612) @[Mux.scala 27:72]
|
|
node _T_1620 = or(_T_1619, _T_1613) @[Mux.scala 27:72]
|
|
node _T_1621 = or(_T_1620, _T_1614) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass_inc <= _T_1621 @[Mux.scala 27:72]
|
|
node _T_1622 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 437:28]
|
|
node _T_1623 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 437:52]
|
|
node _T_1624 = and(_T_1622, _T_1623) @[el2_ifu_mem_ctl.scala 437:31]
|
|
when _T_1624 : @[el2_ifu_mem_ctl.scala 437:56]
|
|
ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 438:26]
|
|
skip @[el2_ifu_mem_ctl.scala 437:56]
|
|
else : @[el2_ifu_mem_ctl.scala 439:5]
|
|
node _T_1625 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 439:70]
|
|
ifu_byp_data_err_new <= _T_1625 @[el2_ifu_mem_ctl.scala 439:36]
|
|
skip @[el2_ifu_mem_ctl.scala 439:5]
|
|
node _T_1626 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 441:59]
|
|
node _T_1627 = bits(_T_1626, 0, 0) @[el2_ifu_mem_ctl.scala 441:63]
|
|
node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 441:38]
|
|
node _T_1629 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1630 = bits(_T_1629, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1631 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1632 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1633 = bits(_T_1632, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1634 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1635 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1636 = bits(_T_1635, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1637 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1638 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1639 = bits(_T_1638, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1640 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1641 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1642 = bits(_T_1641, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1643 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1644 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1645 = bits(_T_1644, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1646 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1647 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1648 = bits(_T_1647, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1649 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1650 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1651 = bits(_T_1650, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1652 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1653 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1654 = bits(_T_1653, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1655 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1656 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1657 = bits(_T_1656, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1658 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1659 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1660 = bits(_T_1659, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1661 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1662 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1663 = bits(_T_1662, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1664 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1665 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1666 = bits(_T_1665, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1667 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1668 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1669 = bits(_T_1668, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1670 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1671 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1672 = bits(_T_1671, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1673 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1674 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1675 = bits(_T_1674, 0, 0) @[el2_ifu_mem_ctl.scala 442:81]
|
|
node _T_1676 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 442:109]
|
|
node _T_1677 = mux(_T_1630, _T_1631, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1678 = mux(_T_1633, _T_1634, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1679 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1680 = mux(_T_1639, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1681 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1682 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1683 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1684 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1685 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1686 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1687 = mux(_T_1660, _T_1661, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1688 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1689 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1690 = mux(_T_1669, _T_1670, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1691 = mux(_T_1672, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1692 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1693 = or(_T_1677, _T_1678) @[Mux.scala 27:72]
|
|
node _T_1694 = or(_T_1693, _T_1679) @[Mux.scala 27:72]
|
|
node _T_1695 = or(_T_1694, _T_1680) @[Mux.scala 27:72]
|
|
node _T_1696 = or(_T_1695, _T_1681) @[Mux.scala 27:72]
|
|
node _T_1697 = or(_T_1696, _T_1682) @[Mux.scala 27:72]
|
|
node _T_1698 = or(_T_1697, _T_1683) @[Mux.scala 27:72]
|
|
node _T_1699 = or(_T_1698, _T_1684) @[Mux.scala 27:72]
|
|
node _T_1700 = or(_T_1699, _T_1685) @[Mux.scala 27:72]
|
|
node _T_1701 = or(_T_1700, _T_1686) @[Mux.scala 27:72]
|
|
node _T_1702 = or(_T_1701, _T_1687) @[Mux.scala 27:72]
|
|
node _T_1703 = or(_T_1702, _T_1688) @[Mux.scala 27:72]
|
|
node _T_1704 = or(_T_1703, _T_1689) @[Mux.scala 27:72]
|
|
node _T_1705 = or(_T_1704, _T_1690) @[Mux.scala 27:72]
|
|
node _T_1706 = or(_T_1705, _T_1691) @[Mux.scala 27:72]
|
|
node _T_1707 = or(_T_1706, _T_1692) @[Mux.scala 27:72]
|
|
wire _T_1708 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1708 <= _T_1707 @[Mux.scala 27:72]
|
|
node _T_1709 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1710 = bits(_T_1709, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1711 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1712 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1713 = bits(_T_1712, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1714 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1715 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1716 = bits(_T_1715, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1717 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1718 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1719 = bits(_T_1718, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1720 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1721 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1722 = bits(_T_1721, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1723 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1724 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1725 = bits(_T_1724, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1726 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1727 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1728 = bits(_T_1727, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1729 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1730 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1731 = bits(_T_1730, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1732 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1733 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1734 = bits(_T_1733, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1735 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1736 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1737 = bits(_T_1736, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1738 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1739 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1740 = bits(_T_1739, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1741 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1742 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1743 = bits(_T_1742, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1744 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1745 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1746 = bits(_T_1745, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1747 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1748 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1749 = bits(_T_1748, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1750 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1751 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1752 = bits(_T_1751, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1753 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1754 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 442:179]
|
|
node _T_1755 = bits(_T_1754, 0, 0) @[el2_ifu_mem_ctl.scala 442:187]
|
|
node _T_1756 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 442:215]
|
|
node _T_1757 = mux(_T_1710, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1758 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1759 = mux(_T_1716, _T_1717, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1760 = mux(_T_1719, _T_1720, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1761 = mux(_T_1722, _T_1723, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1762 = mux(_T_1725, _T_1726, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1763 = mux(_T_1728, _T_1729, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1764 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1765 = mux(_T_1734, _T_1735, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1766 = mux(_T_1737, _T_1738, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1767 = mux(_T_1740, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1768 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1769 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1770 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1771 = mux(_T_1752, _T_1753, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1772 = mux(_T_1755, _T_1756, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1773 = or(_T_1757, _T_1758) @[Mux.scala 27:72]
|
|
node _T_1774 = or(_T_1773, _T_1759) @[Mux.scala 27:72]
|
|
node _T_1775 = or(_T_1774, _T_1760) @[Mux.scala 27:72]
|
|
node _T_1776 = or(_T_1775, _T_1761) @[Mux.scala 27:72]
|
|
node _T_1777 = or(_T_1776, _T_1762) @[Mux.scala 27:72]
|
|
node _T_1778 = or(_T_1777, _T_1763) @[Mux.scala 27:72]
|
|
node _T_1779 = or(_T_1778, _T_1764) @[Mux.scala 27:72]
|
|
node _T_1780 = or(_T_1779, _T_1765) @[Mux.scala 27:72]
|
|
node _T_1781 = or(_T_1780, _T_1766) @[Mux.scala 27:72]
|
|
node _T_1782 = or(_T_1781, _T_1767) @[Mux.scala 27:72]
|
|
node _T_1783 = or(_T_1782, _T_1768) @[Mux.scala 27:72]
|
|
node _T_1784 = or(_T_1783, _T_1769) @[Mux.scala 27:72]
|
|
node _T_1785 = or(_T_1784, _T_1770) @[Mux.scala 27:72]
|
|
node _T_1786 = or(_T_1785, _T_1771) @[Mux.scala 27:72]
|
|
node _T_1787 = or(_T_1786, _T_1772) @[Mux.scala 27:72]
|
|
wire _T_1788 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1788 <= _T_1787 @[Mux.scala 27:72]
|
|
node _T_1789 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1790 = bits(_T_1789, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1791 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1792 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1793 = bits(_T_1792, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1794 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1795 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1796 = bits(_T_1795, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1797 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1798 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1799 = bits(_T_1798, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1800 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1801 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1802 = bits(_T_1801, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1803 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1804 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1805 = bits(_T_1804, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1806 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1807 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1808 = bits(_T_1807, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1809 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1810 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1811 = bits(_T_1810, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1812 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1813 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1814 = bits(_T_1813, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1815 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1816 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1817 = bits(_T_1816, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1818 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1819 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1820 = bits(_T_1819, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1821 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1822 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1823 = bits(_T_1822, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1824 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1825 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1826 = bits(_T_1825, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1827 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1828 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1829 = bits(_T_1828, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1830 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1831 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1832 = bits(_T_1831, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1833 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1834 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 442:285]
|
|
node _T_1835 = bits(_T_1834, 0, 0) @[el2_ifu_mem_ctl.scala 442:293]
|
|
node _T_1836 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 442:321]
|
|
node _T_1837 = mux(_T_1790, _T_1791, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1838 = mux(_T_1793, _T_1794, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1839 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1840 = mux(_T_1799, _T_1800, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1841 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1842 = mux(_T_1805, _T_1806, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1843 = mux(_T_1808, _T_1809, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1844 = mux(_T_1811, _T_1812, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1845 = mux(_T_1814, _T_1815, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1846 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1847 = mux(_T_1820, _T_1821, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1848 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1849 = mux(_T_1826, _T_1827, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1850 = mux(_T_1829, _T_1830, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1851 = mux(_T_1832, _T_1833, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1852 = mux(_T_1835, _T_1836, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1853 = or(_T_1837, _T_1838) @[Mux.scala 27:72]
|
|
node _T_1854 = or(_T_1853, _T_1839) @[Mux.scala 27:72]
|
|
node _T_1855 = or(_T_1854, _T_1840) @[Mux.scala 27:72]
|
|
node _T_1856 = or(_T_1855, _T_1841) @[Mux.scala 27:72]
|
|
node _T_1857 = or(_T_1856, _T_1842) @[Mux.scala 27:72]
|
|
node _T_1858 = or(_T_1857, _T_1843) @[Mux.scala 27:72]
|
|
node _T_1859 = or(_T_1858, _T_1844) @[Mux.scala 27:72]
|
|
node _T_1860 = or(_T_1859, _T_1845) @[Mux.scala 27:72]
|
|
node _T_1861 = or(_T_1860, _T_1846) @[Mux.scala 27:72]
|
|
node _T_1862 = or(_T_1861, _T_1847) @[Mux.scala 27:72]
|
|
node _T_1863 = or(_T_1862, _T_1848) @[Mux.scala 27:72]
|
|
node _T_1864 = or(_T_1863, _T_1849) @[Mux.scala 27:72]
|
|
node _T_1865 = or(_T_1864, _T_1850) @[Mux.scala 27:72]
|
|
node _T_1866 = or(_T_1865, _T_1851) @[Mux.scala 27:72]
|
|
node _T_1867 = or(_T_1866, _T_1852) @[Mux.scala 27:72]
|
|
wire _T_1868 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1868 <= _T_1867 @[Mux.scala 27:72]
|
|
node _T_1869 = cat(_T_1708, _T_1788) @[Cat.scala 29:58]
|
|
node _T_1870 = cat(_T_1869, _T_1868) @[Cat.scala 29:58]
|
|
node _T_1871 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1872 = bits(_T_1871, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1873 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1874 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1875 = bits(_T_1874, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1876 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1877 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1878 = bits(_T_1877, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1879 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1880 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1881 = bits(_T_1880, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1882 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1883 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1884 = bits(_T_1883, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1885 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1886 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1887 = bits(_T_1886, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1888 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1889 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1890 = bits(_T_1889, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1891 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1892 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1893 = bits(_T_1892, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1894 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1895 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1896 = bits(_T_1895, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1897 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1898 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1899 = bits(_T_1898, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1900 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1901 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1902 = bits(_T_1901, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1903 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1904 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1905 = bits(_T_1904, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1906 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1907 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1908 = bits(_T_1907, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1909 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1910 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1911 = bits(_T_1910, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1912 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1913 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1914 = bits(_T_1913, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1915 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1916 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1917 = bits(_T_1916, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1918 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1919 = mux(_T_1872, _T_1873, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1920 = mux(_T_1875, _T_1876, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1921 = mux(_T_1878, _T_1879, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1922 = mux(_T_1881, _T_1882, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1923 = mux(_T_1884, _T_1885, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1924 = mux(_T_1887, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1925 = mux(_T_1890, _T_1891, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1926 = mux(_T_1893, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1927 = mux(_T_1896, _T_1897, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1928 = mux(_T_1899, _T_1900, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1929 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1930 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1931 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1932 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1933 = mux(_T_1914, _T_1915, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1934 = mux(_T_1917, _T_1918, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1935 = or(_T_1919, _T_1920) @[Mux.scala 27:72]
|
|
node _T_1936 = or(_T_1935, _T_1921) @[Mux.scala 27:72]
|
|
node _T_1937 = or(_T_1936, _T_1922) @[Mux.scala 27:72]
|
|
node _T_1938 = or(_T_1937, _T_1923) @[Mux.scala 27:72]
|
|
node _T_1939 = or(_T_1938, _T_1924) @[Mux.scala 27:72]
|
|
node _T_1940 = or(_T_1939, _T_1925) @[Mux.scala 27:72]
|
|
node _T_1941 = or(_T_1940, _T_1926) @[Mux.scala 27:72]
|
|
node _T_1942 = or(_T_1941, _T_1927) @[Mux.scala 27:72]
|
|
node _T_1943 = or(_T_1942, _T_1928) @[Mux.scala 27:72]
|
|
node _T_1944 = or(_T_1943, _T_1929) @[Mux.scala 27:72]
|
|
node _T_1945 = or(_T_1944, _T_1930) @[Mux.scala 27:72]
|
|
node _T_1946 = or(_T_1945, _T_1931) @[Mux.scala 27:72]
|
|
node _T_1947 = or(_T_1946, _T_1932) @[Mux.scala 27:72]
|
|
node _T_1948 = or(_T_1947, _T_1933) @[Mux.scala 27:72]
|
|
node _T_1949 = or(_T_1948, _T_1934) @[Mux.scala 27:72]
|
|
wire _T_1950 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1950 <= _T_1949 @[Mux.scala 27:72]
|
|
node _T_1951 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1952 = bits(_T_1951, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1953 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1954 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1955 = bits(_T_1954, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1956 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1957 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1958 = bits(_T_1957, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1959 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1960 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1961 = bits(_T_1960, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1962 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1963 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1964 = bits(_T_1963, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1965 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1966 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1967 = bits(_T_1966, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1968 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1969 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1970 = bits(_T_1969, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1971 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1972 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1973 = bits(_T_1972, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1974 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1975 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1976 = bits(_T_1975, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1977 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1978 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1979 = bits(_T_1978, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1980 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1981 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1982 = bits(_T_1981, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1983 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1984 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1985 = bits(_T_1984, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1986 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1987 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1988 = bits(_T_1987, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1989 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1990 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1991 = bits(_T_1990, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1992 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1993 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1994 = bits(_T_1993, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1995 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1996 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:183]
|
|
node _T_1997 = bits(_T_1996, 0, 0) @[el2_ifu_mem_ctl.scala 443:191]
|
|
node _T_1998 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 443:219]
|
|
node _T_1999 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2000 = mux(_T_1955, _T_1956, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2001 = mux(_T_1958, _T_1959, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2002 = mux(_T_1961, _T_1962, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2003 = mux(_T_1964, _T_1965, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2004 = mux(_T_1967, _T_1968, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2005 = mux(_T_1970, _T_1971, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2006 = mux(_T_1973, _T_1974, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2007 = mux(_T_1976, _T_1977, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2008 = mux(_T_1979, _T_1980, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2009 = mux(_T_1982, _T_1983, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2010 = mux(_T_1985, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2011 = mux(_T_1988, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2012 = mux(_T_1991, _T_1992, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2013 = mux(_T_1994, _T_1995, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2014 = mux(_T_1997, _T_1998, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2015 = or(_T_1999, _T_2000) @[Mux.scala 27:72]
|
|
node _T_2016 = or(_T_2015, _T_2001) @[Mux.scala 27:72]
|
|
node _T_2017 = or(_T_2016, _T_2002) @[Mux.scala 27:72]
|
|
node _T_2018 = or(_T_2017, _T_2003) @[Mux.scala 27:72]
|
|
node _T_2019 = or(_T_2018, _T_2004) @[Mux.scala 27:72]
|
|
node _T_2020 = or(_T_2019, _T_2005) @[Mux.scala 27:72]
|
|
node _T_2021 = or(_T_2020, _T_2006) @[Mux.scala 27:72]
|
|
node _T_2022 = or(_T_2021, _T_2007) @[Mux.scala 27:72]
|
|
node _T_2023 = or(_T_2022, _T_2008) @[Mux.scala 27:72]
|
|
node _T_2024 = or(_T_2023, _T_2009) @[Mux.scala 27:72]
|
|
node _T_2025 = or(_T_2024, _T_2010) @[Mux.scala 27:72]
|
|
node _T_2026 = or(_T_2025, _T_2011) @[Mux.scala 27:72]
|
|
node _T_2027 = or(_T_2026, _T_2012) @[Mux.scala 27:72]
|
|
node _T_2028 = or(_T_2027, _T_2013) @[Mux.scala 27:72]
|
|
node _T_2029 = or(_T_2028, _T_2014) @[Mux.scala 27:72]
|
|
wire _T_2030 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2030 <= _T_2029 @[Mux.scala 27:72]
|
|
node _T_2031 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2032 = bits(_T_2031, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2033 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2034 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2035 = bits(_T_2034, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2036 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2037 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2038 = bits(_T_2037, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2039 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2040 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2041 = bits(_T_2040, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2042 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2043 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2044 = bits(_T_2043, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2045 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2046 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2047 = bits(_T_2046, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2048 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2049 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2050 = bits(_T_2049, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2051 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2052 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2053 = bits(_T_2052, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2054 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2055 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2056 = bits(_T_2055, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2057 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2058 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2059 = bits(_T_2058, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2060 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2061 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2062 = bits(_T_2061, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2063 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2064 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2065 = bits(_T_2064, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2066 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2067 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2068 = bits(_T_2067, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2069 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2070 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2071 = bits(_T_2070, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2072 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2073 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2074 = bits(_T_2073, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2075 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2076 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:289]
|
|
node _T_2077 = bits(_T_2076, 0, 0) @[el2_ifu_mem_ctl.scala 443:297]
|
|
node _T_2078 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 443:325]
|
|
node _T_2079 = mux(_T_2032, _T_2033, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2080 = mux(_T_2035, _T_2036, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2081 = mux(_T_2038, _T_2039, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2082 = mux(_T_2041, _T_2042, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2083 = mux(_T_2044, _T_2045, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2084 = mux(_T_2047, _T_2048, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2085 = mux(_T_2050, _T_2051, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2086 = mux(_T_2053, _T_2054, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2087 = mux(_T_2056, _T_2057, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2088 = mux(_T_2059, _T_2060, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2089 = mux(_T_2062, _T_2063, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2090 = mux(_T_2065, _T_2066, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2091 = mux(_T_2068, _T_2069, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2092 = mux(_T_2071, _T_2072, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2093 = mux(_T_2074, _T_2075, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2094 = mux(_T_2077, _T_2078, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2095 = or(_T_2079, _T_2080) @[Mux.scala 27:72]
|
|
node _T_2096 = or(_T_2095, _T_2081) @[Mux.scala 27:72]
|
|
node _T_2097 = or(_T_2096, _T_2082) @[Mux.scala 27:72]
|
|
node _T_2098 = or(_T_2097, _T_2083) @[Mux.scala 27:72]
|
|
node _T_2099 = or(_T_2098, _T_2084) @[Mux.scala 27:72]
|
|
node _T_2100 = or(_T_2099, _T_2085) @[Mux.scala 27:72]
|
|
node _T_2101 = or(_T_2100, _T_2086) @[Mux.scala 27:72]
|
|
node _T_2102 = or(_T_2101, _T_2087) @[Mux.scala 27:72]
|
|
node _T_2103 = or(_T_2102, _T_2088) @[Mux.scala 27:72]
|
|
node _T_2104 = or(_T_2103, _T_2089) @[Mux.scala 27:72]
|
|
node _T_2105 = or(_T_2104, _T_2090) @[Mux.scala 27:72]
|
|
node _T_2106 = or(_T_2105, _T_2091) @[Mux.scala 27:72]
|
|
node _T_2107 = or(_T_2106, _T_2092) @[Mux.scala 27:72]
|
|
node _T_2108 = or(_T_2107, _T_2093) @[Mux.scala 27:72]
|
|
node _T_2109 = or(_T_2108, _T_2094) @[Mux.scala 27:72]
|
|
wire _T_2110 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2110 <= _T_2109 @[Mux.scala 27:72]
|
|
node _T_2111 = cat(_T_1950, _T_2030) @[Cat.scala 29:58]
|
|
node _T_2112 = cat(_T_2111, _T_2110) @[Cat.scala 29:58]
|
|
node ic_byp_data_only_pre_new = mux(_T_1628, _T_1870, _T_2112) @[el2_ifu_mem_ctl.scala 441:37]
|
|
node _T_2113 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 445:52]
|
|
node _T_2114 = bits(_T_2113, 0, 0) @[el2_ifu_mem_ctl.scala 445:62]
|
|
node _T_2115 = eq(_T_2114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:31]
|
|
node _T_2116 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 445:128]
|
|
node _T_2117 = cat(UInt<16>("h00"), _T_2116) @[Cat.scala 29:58]
|
|
node _T_2118 = mux(_T_2115, ic_byp_data_only_pre_new, _T_2117) @[el2_ifu_mem_ctl.scala 445:30]
|
|
ic_byp_data_only_new <= _T_2118 @[el2_ifu_mem_ctl.scala 445:24]
|
|
node _T_2119 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 447:27]
|
|
node _T_2120 = bits(ifu_fetch_addr_int_f, 5, 5) @[el2_ifu_mem_ctl.scala 447:75]
|
|
node miss_wrap_f = neq(_T_2119, _T_2120) @[el2_ifu_mem_ctl.scala 447:51]
|
|
node _T_2121 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2122 = eq(_T_2121, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2123 = bits(_T_2122, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2124 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2125 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2126 = eq(_T_2125, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2127 = bits(_T_2126, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2128 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2129 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2130 = eq(_T_2129, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2131 = bits(_T_2130, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2132 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2133 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2134 = eq(_T_2133, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2135 = bits(_T_2134, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2136 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2137 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2138 = eq(_T_2137, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2139 = bits(_T_2138, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2140 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2141 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2142 = eq(_T_2141, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2143 = bits(_T_2142, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2144 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2145 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2146 = eq(_T_2145, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2147 = bits(_T_2146, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2148 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2149 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:102]
|
|
node _T_2150 = eq(_T_2149, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 448:127]
|
|
node _T_2151 = bits(_T_2150, 0, 0) @[el2_ifu_mem_ctl.scala 448:135]
|
|
node _T_2152 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 448:166]
|
|
node _T_2153 = mux(_T_2123, _T_2124, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2154 = mux(_T_2127, _T_2128, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2155 = mux(_T_2131, _T_2132, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2156 = mux(_T_2135, _T_2136, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2157 = mux(_T_2139, _T_2140, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2158 = mux(_T_2143, _T_2144, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2159 = mux(_T_2147, _T_2148, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2160 = mux(_T_2151, _T_2152, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2161 = or(_T_2153, _T_2154) @[Mux.scala 27:72]
|
|
node _T_2162 = or(_T_2161, _T_2155) @[Mux.scala 27:72]
|
|
node _T_2163 = or(_T_2162, _T_2156) @[Mux.scala 27:72]
|
|
node _T_2164 = or(_T_2163, _T_2157) @[Mux.scala 27:72]
|
|
node _T_2165 = or(_T_2164, _T_2158) @[Mux.scala 27:72]
|
|
node _T_2166 = or(_T_2165, _T_2159) @[Mux.scala 27:72]
|
|
node _T_2167 = or(_T_2166, _T_2160) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_bypass_index <= _T_2167 @[Mux.scala 27:72]
|
|
node _T_2168 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2169 = bits(_T_2168, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2170 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2171 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2172 = bits(_T_2171, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2173 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2174 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2175 = bits(_T_2174, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2176 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2177 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2178 = bits(_T_2177, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2179 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2180 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2181 = bits(_T_2180, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2182 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2183 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2184 = bits(_T_2183, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2185 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2186 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2187 = bits(_T_2186, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2188 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2189 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 449:110]
|
|
node _T_2190 = bits(_T_2189, 0, 0) @[el2_ifu_mem_ctl.scala 449:118]
|
|
node _T_2191 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 449:149]
|
|
node _T_2192 = mux(_T_2169, _T_2170, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2193 = mux(_T_2172, _T_2173, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2194 = mux(_T_2175, _T_2176, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2195 = mux(_T_2178, _T_2179, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2196 = mux(_T_2181, _T_2182, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2197 = mux(_T_2184, _T_2185, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2198 = mux(_T_2187, _T_2188, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2199 = mux(_T_2190, _T_2191, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2200 = or(_T_2192, _T_2193) @[Mux.scala 27:72]
|
|
node _T_2201 = or(_T_2200, _T_2194) @[Mux.scala 27:72]
|
|
node _T_2202 = or(_T_2201, _T_2195) @[Mux.scala 27:72]
|
|
node _T_2203 = or(_T_2202, _T_2196) @[Mux.scala 27:72]
|
|
node _T_2204 = or(_T_2203, _T_2197) @[Mux.scala 27:72]
|
|
node _T_2205 = or(_T_2204, _T_2198) @[Mux.scala 27:72]
|
|
node _T_2206 = or(_T_2205, _T_2199) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_inc_bypass_index <= _T_2206 @[Mux.scala 27:72]
|
|
node _T_2207 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 450:85]
|
|
node _T_2208 = eq(_T_2207, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:69]
|
|
node _T_2209 = and(ic_miss_buff_data_valid_bypass_index, _T_2208) @[el2_ifu_mem_ctl.scala 450:67]
|
|
node _T_2210 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 450:107]
|
|
node _T_2211 = eq(_T_2210, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:91]
|
|
node _T_2212 = and(_T_2209, _T_2211) @[el2_ifu_mem_ctl.scala 450:89]
|
|
node _T_2213 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 451:61]
|
|
node _T_2214 = eq(_T_2213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:45]
|
|
node _T_2215 = and(ic_miss_buff_data_valid_bypass_index, _T_2214) @[el2_ifu_mem_ctl.scala 451:43]
|
|
node _T_2216 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 451:83]
|
|
node _T_2217 = and(_T_2215, _T_2216) @[el2_ifu_mem_ctl.scala 451:65]
|
|
node _T_2218 = or(_T_2212, _T_2217) @[el2_ifu_mem_ctl.scala 450:112]
|
|
node _T_2219 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 452:61]
|
|
node _T_2220 = and(ic_miss_buff_data_valid_bypass_index, _T_2219) @[el2_ifu_mem_ctl.scala 452:43]
|
|
node _T_2221 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 452:83]
|
|
node _T_2222 = eq(_T_2221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:67]
|
|
node _T_2223 = and(_T_2220, _T_2222) @[el2_ifu_mem_ctl.scala 452:65]
|
|
node _T_2224 = or(_T_2218, _T_2223) @[el2_ifu_mem_ctl.scala 451:88]
|
|
node _T_2225 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 453:61]
|
|
node _T_2226 = and(ic_miss_buff_data_valid_bypass_index, _T_2225) @[el2_ifu_mem_ctl.scala 453:43]
|
|
node _T_2227 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 453:83]
|
|
node _T_2228 = and(_T_2226, _T_2227) @[el2_ifu_mem_ctl.scala 453:65]
|
|
node _T_2229 = and(_T_2228, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 453:87]
|
|
node _T_2230 = or(_T_2224, _T_2229) @[el2_ifu_mem_ctl.scala 452:88]
|
|
node _T_2231 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 454:61]
|
|
node _T_2232 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2233 = eq(_T_2231, _T_2232) @[el2_ifu_mem_ctl.scala 454:87]
|
|
node _T_2234 = and(ic_miss_buff_data_valid_bypass_index, _T_2233) @[el2_ifu_mem_ctl.scala 454:43]
|
|
node miss_buff_hit_unq_f = or(_T_2230, _T_2234) @[el2_ifu_mem_ctl.scala 453:131]
|
|
node _T_2235 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 456:30]
|
|
node _T_2236 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 456:68]
|
|
node _T_2237 = and(miss_buff_hit_unq_f, _T_2236) @[el2_ifu_mem_ctl.scala 456:66]
|
|
node _T_2238 = and(_T_2235, _T_2237) @[el2_ifu_mem_ctl.scala 456:43]
|
|
stream_hit_f <= _T_2238 @[el2_ifu_mem_ctl.scala 456:16]
|
|
node _T_2239 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 457:31]
|
|
node _T_2240 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:70]
|
|
node _T_2241 = and(miss_buff_hit_unq_f, _T_2240) @[el2_ifu_mem_ctl.scala 457:68]
|
|
node _T_2242 = eq(_T_2241, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:46]
|
|
node _T_2243 = and(_T_2239, _T_2242) @[el2_ifu_mem_ctl.scala 457:44]
|
|
node _T_2244 = and(_T_2243, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 457:84]
|
|
stream_miss_f <= _T_2244 @[el2_ifu_mem_ctl.scala 457:17]
|
|
node _T_2245 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 458:35]
|
|
node _T_2246 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2247 = eq(_T_2245, _T_2246) @[el2_ifu_mem_ctl.scala 458:60]
|
|
node _T_2248 = and(_T_2247, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 458:94]
|
|
node _T_2249 = and(_T_2248, stream_hit_f) @[el2_ifu_mem_ctl.scala 458:112]
|
|
stream_eol_f <= _T_2249 @[el2_ifu_mem_ctl.scala 458:16]
|
|
node _T_2250 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 459:55]
|
|
node _T_2251 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_2252 = or(_T_2250, _T_2251) @[el2_ifu_mem_ctl.scala 459:74]
|
|
node _T_2253 = and(miss_buff_hit_unq_f, _T_2252) @[el2_ifu_mem_ctl.scala 459:41]
|
|
crit_byp_hit_f <= _T_2253 @[el2_ifu_mem_ctl.scala 459:18]
|
|
node _T_2254 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 462:37]
|
|
node _T_2255 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 462:70]
|
|
node _T_2256 = eq(_T_2255, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 462:55]
|
|
node other_tag = cat(_T_2254, _T_2256) @[Cat.scala 29:58]
|
|
node _T_2257 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2258 = bits(_T_2257, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2259 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2260 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2261 = bits(_T_2260, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2262 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2263 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2264 = bits(_T_2263, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2265 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2266 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2267 = bits(_T_2266, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2268 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2269 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2270 = bits(_T_2269, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2271 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2272 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2273 = bits(_T_2272, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2274 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2275 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2276 = bits(_T_2275, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2277 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2278 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 463:81]
|
|
node _T_2279 = bits(_T_2278, 0, 0) @[el2_ifu_mem_ctl.scala 463:89]
|
|
node _T_2280 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 463:120]
|
|
node _T_2281 = mux(_T_2258, _T_2259, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2282 = mux(_T_2261, _T_2262, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2283 = mux(_T_2264, _T_2265, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2284 = mux(_T_2267, _T_2268, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2285 = mux(_T_2270, _T_2271, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2286 = mux(_T_2273, _T_2274, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2287 = mux(_T_2276, _T_2277, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2288 = mux(_T_2279, _T_2280, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2289 = or(_T_2281, _T_2282) @[Mux.scala 27:72]
|
|
node _T_2290 = or(_T_2289, _T_2283) @[Mux.scala 27:72]
|
|
node _T_2291 = or(_T_2290, _T_2284) @[Mux.scala 27:72]
|
|
node _T_2292 = or(_T_2291, _T_2285) @[Mux.scala 27:72]
|
|
node _T_2293 = or(_T_2292, _T_2286) @[Mux.scala 27:72]
|
|
node _T_2294 = or(_T_2293, _T_2287) @[Mux.scala 27:72]
|
|
node _T_2295 = or(_T_2294, _T_2288) @[Mux.scala 27:72]
|
|
wire second_half_available : UInt<1> @[Mux.scala 27:72]
|
|
second_half_available <= _T_2295 @[Mux.scala 27:72]
|
|
node _T_2296 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 464:46]
|
|
write_ic_16_bytes <= _T_2296 @[el2_ifu_mem_ctl.scala 464:21]
|
|
node _T_2297 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2298 = eq(_T_2297, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2299 = bits(_T_2298, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2300 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2301 = eq(_T_2300, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2302 = bits(_T_2301, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2303 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2304 = eq(_T_2303, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2305 = bits(_T_2304, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2306 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2307 = eq(_T_2306, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2308 = bits(_T_2307, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2309 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2310 = eq(_T_2309, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2311 = bits(_T_2310, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2312 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2313 = eq(_T_2312, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2314 = bits(_T_2313, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2315 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2316 = eq(_T_2315, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2317 = bits(_T_2316, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2318 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2319 = eq(_T_2318, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2320 = bits(_T_2319, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2321 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2322 = eq(_T_2321, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2323 = bits(_T_2322, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2324 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2325 = eq(_T_2324, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2326 = bits(_T_2325, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2327 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2328 = eq(_T_2327, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2329 = bits(_T_2328, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2330 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2331 = eq(_T_2330, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2332 = bits(_T_2331, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2333 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2334 = eq(_T_2333, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2335 = bits(_T_2334, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2336 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2337 = eq(_T_2336, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2338 = bits(_T_2337, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2339 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2340 = eq(_T_2339, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2341 = bits(_T_2340, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2342 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2343 = eq(_T_2342, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 465:89]
|
|
node _T_2344 = bits(_T_2343, 0, 0) @[el2_ifu_mem_ctl.scala 465:97]
|
|
node _T_2345 = mux(_T_2299, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2346 = mux(_T_2302, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2347 = mux(_T_2305, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2348 = mux(_T_2308, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2349 = mux(_T_2311, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2350 = mux(_T_2314, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2351 = mux(_T_2317, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2352 = mux(_T_2320, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2353 = mux(_T_2323, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2354 = mux(_T_2326, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2355 = mux(_T_2329, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2356 = mux(_T_2332, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2357 = mux(_T_2335, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2358 = mux(_T_2338, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2359 = mux(_T_2341, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2360 = mux(_T_2344, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2361 = or(_T_2345, _T_2346) @[Mux.scala 27:72]
|
|
node _T_2362 = or(_T_2361, _T_2347) @[Mux.scala 27:72]
|
|
node _T_2363 = or(_T_2362, _T_2348) @[Mux.scala 27:72]
|
|
node _T_2364 = or(_T_2363, _T_2349) @[Mux.scala 27:72]
|
|
node _T_2365 = or(_T_2364, _T_2350) @[Mux.scala 27:72]
|
|
node _T_2366 = or(_T_2365, _T_2351) @[Mux.scala 27:72]
|
|
node _T_2367 = or(_T_2366, _T_2352) @[Mux.scala 27:72]
|
|
node _T_2368 = or(_T_2367, _T_2353) @[Mux.scala 27:72]
|
|
node _T_2369 = or(_T_2368, _T_2354) @[Mux.scala 27:72]
|
|
node _T_2370 = or(_T_2369, _T_2355) @[Mux.scala 27:72]
|
|
node _T_2371 = or(_T_2370, _T_2356) @[Mux.scala 27:72]
|
|
node _T_2372 = or(_T_2371, _T_2357) @[Mux.scala 27:72]
|
|
node _T_2373 = or(_T_2372, _T_2358) @[Mux.scala 27:72]
|
|
node _T_2374 = or(_T_2373, _T_2359) @[Mux.scala 27:72]
|
|
node _T_2375 = or(_T_2374, _T_2360) @[Mux.scala 27:72]
|
|
wire _T_2376 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2376 <= _T_2375 @[Mux.scala 27:72]
|
|
node _T_2377 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2378 = eq(_T_2377, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2379 = bits(_T_2378, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2380 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2381 = eq(_T_2380, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2382 = bits(_T_2381, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2383 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2384 = eq(_T_2383, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2385 = bits(_T_2384, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2386 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2387 = eq(_T_2386, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2388 = bits(_T_2387, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2389 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2390 = eq(_T_2389, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2391 = bits(_T_2390, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2392 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2393 = eq(_T_2392, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2394 = bits(_T_2393, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2395 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2396 = eq(_T_2395, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2397 = bits(_T_2396, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2398 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2399 = eq(_T_2398, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2400 = bits(_T_2399, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2401 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2402 = eq(_T_2401, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2403 = bits(_T_2402, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2404 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2405 = eq(_T_2404, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2406 = bits(_T_2405, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2407 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2408 = eq(_T_2407, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2409 = bits(_T_2408, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2410 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2411 = eq(_T_2410, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2412 = bits(_T_2411, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2413 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2414 = eq(_T_2413, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2415 = bits(_T_2414, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2416 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2417 = eq(_T_2416, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2418 = bits(_T_2417, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2419 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2420 = eq(_T_2419, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2421 = bits(_T_2420, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2422 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2423 = eq(_T_2422, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 466:66]
|
|
node _T_2424 = bits(_T_2423, 0, 0) @[el2_ifu_mem_ctl.scala 466:74]
|
|
node _T_2425 = mux(_T_2379, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2426 = mux(_T_2382, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2427 = mux(_T_2385, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2428 = mux(_T_2388, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2429 = mux(_T_2391, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2430 = mux(_T_2394, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2431 = mux(_T_2397, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2432 = mux(_T_2400, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2433 = mux(_T_2403, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2434 = mux(_T_2406, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2435 = mux(_T_2409, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2436 = mux(_T_2412, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2437 = mux(_T_2415, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2438 = mux(_T_2418, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2439 = mux(_T_2421, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2440 = mux(_T_2424, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2441 = or(_T_2425, _T_2426) @[Mux.scala 27:72]
|
|
node _T_2442 = or(_T_2441, _T_2427) @[Mux.scala 27:72]
|
|
node _T_2443 = or(_T_2442, _T_2428) @[Mux.scala 27:72]
|
|
node _T_2444 = or(_T_2443, _T_2429) @[Mux.scala 27:72]
|
|
node _T_2445 = or(_T_2444, _T_2430) @[Mux.scala 27:72]
|
|
node _T_2446 = or(_T_2445, _T_2431) @[Mux.scala 27:72]
|
|
node _T_2447 = or(_T_2446, _T_2432) @[Mux.scala 27:72]
|
|
node _T_2448 = or(_T_2447, _T_2433) @[Mux.scala 27:72]
|
|
node _T_2449 = or(_T_2448, _T_2434) @[Mux.scala 27:72]
|
|
node _T_2450 = or(_T_2449, _T_2435) @[Mux.scala 27:72]
|
|
node _T_2451 = or(_T_2450, _T_2436) @[Mux.scala 27:72]
|
|
node _T_2452 = or(_T_2451, _T_2437) @[Mux.scala 27:72]
|
|
node _T_2453 = or(_T_2452, _T_2438) @[Mux.scala 27:72]
|
|
node _T_2454 = or(_T_2453, _T_2439) @[Mux.scala 27:72]
|
|
node _T_2455 = or(_T_2454, _T_2440) @[Mux.scala 27:72]
|
|
wire _T_2456 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2456 <= _T_2455 @[Mux.scala 27:72]
|
|
node _T_2457 = cat(_T_2376, _T_2456) @[Cat.scala 29:58]
|
|
ic_miss_buff_half <= _T_2457 @[el2_ifu_mem_ctl.scala 465:21]
|
|
node _T_2458 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 470:44]
|
|
node _T_2459 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 470:91]
|
|
node _T_2460 = eq(_T_2459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:60]
|
|
node _T_2461 = and(_T_2458, _T_2460) @[el2_ifu_mem_ctl.scala 470:58]
|
|
ic_rd_parity_final_err <= _T_2461 @[el2_ifu_mem_ctl.scala 470:26]
|
|
wire ifu_ic_rw_int_addr_ff : UInt<7>
|
|
ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
|
|
wire perr_sb_write_status : UInt<1>
|
|
perr_sb_write_status <= UInt<1>("h00")
|
|
reg perr_ic_index_ff : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_sb_write_status : @[Reg.scala 28:19]
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
wire perr_sel_invalidate : UInt<1>
|
|
perr_sel_invalidate <= UInt<1>("h00")
|
|
node _T_2462 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15]
|
|
node perr_err_inv_way = mux(_T_2462, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2463 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 477:34]
|
|
iccm_correct_ecc <= _T_2463 @[el2_ifu_mem_ctl.scala 477:20]
|
|
node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 478:37]
|
|
wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 479:33]
|
|
node _T_2464 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 480:49]
|
|
node _T_2465 = and(iccm_correct_ecc, _T_2464) @[el2_ifu_mem_ctl.scala 480:47]
|
|
io.iccm_buf_correct_ecc <= _T_2465 @[el2_ifu_mem_ctl.scala 480:27]
|
|
reg _T_2466 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 481:58]
|
|
_T_2466 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 481:58]
|
|
dma_sb_err_state_ff <= _T_2466 @[el2_ifu_mem_ctl.scala 481:23]
|
|
wire perr_nxtstate : UInt<3>
|
|
perr_nxtstate <= UInt<1>("h00")
|
|
wire perr_state_en : UInt<1>
|
|
perr_state_en <= UInt<1>("h00")
|
|
wire iccm_error_start : UInt<1>
|
|
iccm_error_start <= UInt<1>("h00")
|
|
node _T_2467 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2467 : @[Conditional.scala 40:58]
|
|
node _T_2468 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 489:89]
|
|
node _T_2469 = and(io.ic_error_start, _T_2468) @[el2_ifu_mem_ctl.scala 489:87]
|
|
node _T_2470 = bits(_T_2469, 0, 0) @[el2_ifu_mem_ctl.scala 489:110]
|
|
node _T_2471 = mux(_T_2470, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 489:67]
|
|
node _T_2472 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2471) @[el2_ifu_mem_ctl.scala 489:27]
|
|
perr_nxtstate <= _T_2472 @[el2_ifu_mem_ctl.scala 489:21]
|
|
node _T_2473 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 490:44]
|
|
node _T_2474 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 490:67]
|
|
node _T_2475 = and(_T_2473, _T_2474) @[el2_ifu_mem_ctl.scala 490:65]
|
|
node _T_2476 = or(_T_2475, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 490:88]
|
|
node _T_2477 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 490:114]
|
|
node _T_2478 = and(_T_2476, _T_2477) @[el2_ifu_mem_ctl.scala 490:112]
|
|
perr_state_en <= _T_2478 @[el2_ifu_mem_ctl.scala 490:21]
|
|
perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 491:28]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2479 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2479 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 494:21]
|
|
node _T_2480 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 495:50]
|
|
perr_state_en <= _T_2480 @[el2_ifu_mem_ctl.scala 495:21]
|
|
node _T_2481 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 496:56]
|
|
perr_sel_invalidate <= _T_2481 @[el2_ifu_mem_ctl.scala 496:27]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2482 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2482 : @[Conditional.scala 39:67]
|
|
node _T_2483 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 499:54]
|
|
node _T_2484 = or(_T_2483, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 499:84]
|
|
node _T_2485 = bits(_T_2484, 0, 0) @[el2_ifu_mem_ctl.scala 499:115]
|
|
node _T_2486 = mux(_T_2485, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 499:27]
|
|
perr_nxtstate <= _T_2486 @[el2_ifu_mem_ctl.scala 499:21]
|
|
node _T_2487 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 500:50]
|
|
perr_state_en <= _T_2487 @[el2_ifu_mem_ctl.scala 500:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2488 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2488 : @[Conditional.scala 39:67]
|
|
node _T_2489 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 503:27]
|
|
perr_nxtstate <= _T_2489 @[el2_ifu_mem_ctl.scala 503:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 504:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2490 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2490 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 507:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 508:21]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2491 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_state_en : @[Reg.scala 28:19]
|
|
_T_2491 <= perr_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
perr_state <= _T_2491 @[el2_ifu_mem_ctl.scala 511:14]
|
|
wire err_stop_nxtstate : UInt<2>
|
|
err_stop_nxtstate <= UInt<1>("h00")
|
|
wire err_stop_state_en : UInt<1>
|
|
err_stop_state_en <= UInt<1>("h00")
|
|
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 515:28]
|
|
node _T_2492 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2492 : @[Conditional.scala 40:58]
|
|
err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 519:25]
|
|
node _T_2493 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 520:66]
|
|
node _T_2494 = and(io.dec_tlu_flush_err_wb, _T_2493) @[el2_ifu_mem_ctl.scala 520:52]
|
|
node _T_2495 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 520:83]
|
|
node _T_2496 = and(_T_2494, _T_2495) @[el2_ifu_mem_ctl.scala 520:81]
|
|
err_stop_state_en <= _T_2496 @[el2_ifu_mem_ctl.scala 520:25]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2497 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2497 : @[Conditional.scala 39:67]
|
|
node _T_2498 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 523:59]
|
|
node _T_2499 = or(_T_2498, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 523:86]
|
|
node _T_2500 = bits(_T_2499, 0, 0) @[el2_ifu_mem_ctl.scala 523:117]
|
|
node _T_2501 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 524:31]
|
|
node _T_2502 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 524:56]
|
|
node _T_2503 = and(_T_2502, two_byte_instr) @[el2_ifu_mem_ctl.scala 524:59]
|
|
node _T_2504 = or(_T_2501, _T_2503) @[el2_ifu_mem_ctl.scala 524:38]
|
|
node _T_2505 = bits(_T_2504, 0, 0) @[el2_ifu_mem_ctl.scala 524:83]
|
|
node _T_2506 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 525:31]
|
|
node _T_2507 = bits(_T_2506, 0, 0) @[el2_ifu_mem_ctl.scala 525:41]
|
|
node _T_2508 = mux(_T_2507, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 525:14]
|
|
node _T_2509 = mux(_T_2505, UInt<2>("h03"), _T_2508) @[el2_ifu_mem_ctl.scala 524:12]
|
|
node _T_2510 = mux(_T_2500, UInt<2>("h00"), _T_2509) @[el2_ifu_mem_ctl.scala 523:31]
|
|
err_stop_nxtstate <= _T_2510 @[el2_ifu_mem_ctl.scala 523:25]
|
|
node _T_2511 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 526:54]
|
|
node _T_2512 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:99]
|
|
node _T_2513 = or(_T_2511, _T_2512) @[el2_ifu_mem_ctl.scala 526:81]
|
|
node _T_2514 = or(_T_2513, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 526:103]
|
|
node _T_2515 = or(_T_2514, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 526:126]
|
|
err_stop_state_en <= _T_2515 @[el2_ifu_mem_ctl.scala 526:25]
|
|
node _T_2516 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 527:43]
|
|
node _T_2517 = eq(_T_2516, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 527:48]
|
|
node _T_2518 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 527:75]
|
|
node _T_2519 = and(_T_2518, two_byte_instr) @[el2_ifu_mem_ctl.scala 527:79]
|
|
node _T_2520 = or(_T_2517, _T_2519) @[el2_ifu_mem_ctl.scala 527:56]
|
|
node _T_2521 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 527:122]
|
|
node _T_2522 = eq(_T_2521, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 527:101]
|
|
node _T_2523 = and(_T_2520, _T_2522) @[el2_ifu_mem_ctl.scala 527:99]
|
|
err_stop_fetch <= _T_2523 @[el2_ifu_mem_ctl.scala 527:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 528:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2524 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2524 : @[Conditional.scala 39:67]
|
|
node _T_2525 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 531:59]
|
|
node _T_2526 = or(_T_2525, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 531:86]
|
|
node _T_2527 = bits(_T_2526, 0, 0) @[el2_ifu_mem_ctl.scala 531:111]
|
|
node _T_2528 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 532:46]
|
|
node _T_2529 = bits(_T_2528, 0, 0) @[el2_ifu_mem_ctl.scala 532:50]
|
|
node _T_2530 = mux(_T_2529, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 532:29]
|
|
node _T_2531 = mux(_T_2527, UInt<2>("h00"), _T_2530) @[el2_ifu_mem_ctl.scala 531:31]
|
|
err_stop_nxtstate <= _T_2531 @[el2_ifu_mem_ctl.scala 531:25]
|
|
node _T_2532 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 533:54]
|
|
node _T_2533 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 533:99]
|
|
node _T_2534 = or(_T_2532, _T_2533) @[el2_ifu_mem_ctl.scala 533:81]
|
|
node _T_2535 = or(_T_2534, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 533:103]
|
|
err_stop_state_en <= _T_2535 @[el2_ifu_mem_ctl.scala 533:25]
|
|
node _T_2536 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 534:41]
|
|
node _T_2537 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 534:47]
|
|
node _T_2538 = and(_T_2536, _T_2537) @[el2_ifu_mem_ctl.scala 534:45]
|
|
node _T_2539 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 534:69]
|
|
node _T_2540 = and(_T_2538, _T_2539) @[el2_ifu_mem_ctl.scala 534:67]
|
|
err_stop_fetch <= _T_2540 @[el2_ifu_mem_ctl.scala 534:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 535:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2541 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2541 : @[Conditional.scala 39:67]
|
|
node _T_2542 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 538:62]
|
|
node _T_2543 = and(io.dec_tlu_flush_lower_wb, _T_2542) @[el2_ifu_mem_ctl.scala 538:60]
|
|
node _T_2544 = or(_T_2543, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 538:88]
|
|
node _T_2545 = or(_T_2544, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 538:115]
|
|
node _T_2546 = bits(_T_2545, 0, 0) @[el2_ifu_mem_ctl.scala 538:140]
|
|
node _T_2547 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 539:60]
|
|
node _T_2548 = mux(_T_2547, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 539:29]
|
|
node _T_2549 = mux(_T_2546, UInt<2>("h00"), _T_2548) @[el2_ifu_mem_ctl.scala 538:31]
|
|
err_stop_nxtstate <= _T_2549 @[el2_ifu_mem_ctl.scala 538:25]
|
|
node _T_2550 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 540:54]
|
|
node _T_2551 = or(_T_2550, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 540:81]
|
|
err_stop_state_en <= _T_2551 @[el2_ifu_mem_ctl.scala 540:25]
|
|
err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 541:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 542:32]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2552 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when err_stop_state_en : @[Reg.scala 28:19]
|
|
_T_2552 <= err_stop_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
err_stop_state <= _T_2552 @[el2_ifu_mem_ctl.scala 545:18]
|
|
bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 546:22]
|
|
reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 547:61]
|
|
bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 547:61]
|
|
reg _T_2553 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 548:52]
|
|
_T_2553 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 548:52]
|
|
scnd_miss_req_q <= _T_2553 @[el2_ifu_mem_ctl.scala 548:19]
|
|
reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 549:57]
|
|
scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 549:57]
|
|
node _T_2554 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 550:39]
|
|
node _T_2555 = and(scnd_miss_req_q, _T_2554) @[el2_ifu_mem_ctl.scala 550:36]
|
|
scnd_miss_req <= _T_2555 @[el2_ifu_mem_ctl.scala 550:17]
|
|
wire bus_cmd_req_hold : UInt<1>
|
|
bus_cmd_req_hold <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_valid : UInt<1>
|
|
ifu_bus_cmd_valid <= UInt<1>("h00")
|
|
wire bus_cmd_beat_count : UInt<3>
|
|
bus_cmd_beat_count <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_ready : UInt<1>
|
|
ifu_bus_cmd_ready <= UInt<1>("h00")
|
|
node _T_2556 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 555:45]
|
|
node _T_2557 = or(_T_2556, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 555:64]
|
|
node _T_2558 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 555:87]
|
|
node _T_2559 = and(_T_2557, _T_2558) @[el2_ifu_mem_ctl.scala 555:85]
|
|
node _T_2560 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2561 = eq(bus_cmd_beat_count, _T_2560) @[el2_ifu_mem_ctl.scala 555:133]
|
|
node _T_2562 = and(_T_2561, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 555:164]
|
|
node _T_2563 = and(_T_2562, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 555:184]
|
|
node _T_2564 = and(_T_2563, miss_pending) @[el2_ifu_mem_ctl.scala 555:204]
|
|
node _T_2565 = eq(_T_2564, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 555:112]
|
|
node ifc_bus_ic_req_ff_in = and(_T_2559, _T_2565) @[el2_ifu_mem_ctl.scala 555:110]
|
|
node _T_2566 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 556:80]
|
|
reg _T_2567 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2566 : @[Reg.scala 28:19]
|
|
_T_2567 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_cmd_valid <= _T_2567 @[el2_ifu_mem_ctl.scala 556:21]
|
|
wire bus_cmd_sent : UInt<1>
|
|
bus_cmd_sent <= UInt<1>("h00")
|
|
node _T_2568 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 558:39]
|
|
node _T_2569 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 558:61]
|
|
node _T_2570 = and(_T_2568, _T_2569) @[el2_ifu_mem_ctl.scala 558:59]
|
|
node _T_2571 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 558:77]
|
|
node bus_cmd_req_in = and(_T_2570, _T_2571) @[el2_ifu_mem_ctl.scala 558:75]
|
|
reg _T_2572 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 559:49]
|
|
_T_2572 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 559:49]
|
|
bus_cmd_sent <= _T_2572 @[el2_ifu_mem_ctl.scala 559:16]
|
|
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 561:22]
|
|
node _T_2573 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2574 = mux(_T_2573, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2575 = and(bus_rd_addr_count, _T_2574) @[el2_ifu_mem_ctl.scala 562:40]
|
|
io.ifu_axi_arid <= _T_2575 @[el2_ifu_mem_ctl.scala 562:19]
|
|
node _T_2576 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
node _T_2577 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2578 = mux(_T_2577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2579 = and(_T_2576, _T_2578) @[el2_ifu_mem_ctl.scala 563:57]
|
|
io.ifu_axi_araddr <= _T_2579 @[el2_ifu_mem_ctl.scala 563:21]
|
|
io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 564:21]
|
|
io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 565:22]
|
|
node _T_2580 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 566:43]
|
|
io.ifu_axi_arregion <= _T_2580 @[el2_ifu_mem_ctl.scala 566:23]
|
|
io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 567:22]
|
|
io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 568:21]
|
|
reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rvalid_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_arvalid_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rresp_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rresp_ff <= io.ifu_axi_rresp @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg _T_2581 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2581 <= io.ifu_axi_rdata @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rdata_ff <= _T_2581 @[el2_ifu_mem_ctl.scala 578:20]
|
|
reg _T_2582 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2582 <= io.ifu_axi_rid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rid_ff <= _T_2582 @[el2_ifu_mem_ctl.scala 579:18]
|
|
ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 580:21]
|
|
ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 581:21]
|
|
ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 582:21]
|
|
ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 583:19]
|
|
ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 584:21]
|
|
node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 586:42]
|
|
node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 587:45]
|
|
node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 588:51]
|
|
node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 589:49]
|
|
node _T_2583 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 590:35]
|
|
node _T_2584 = and(_T_2583, miss_pending) @[el2_ifu_mem_ctl.scala 590:53]
|
|
node _T_2585 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 590:70]
|
|
node _T_2586 = and(_T_2584, _T_2585) @[el2_ifu_mem_ctl.scala 590:68]
|
|
bus_cmd_sent <= _T_2586 @[el2_ifu_mem_ctl.scala 590:16]
|
|
wire bus_last_data_beat : UInt<1>
|
|
bus_last_data_beat <= UInt<1>("h00")
|
|
node _T_2587 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 592:50]
|
|
node _T_2588 = and(bus_ifu_wr_en_ff, _T_2587) @[el2_ifu_mem_ctl.scala 592:48]
|
|
node _T_2589 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 592:72]
|
|
node bus_inc_data_beat_cnt = and(_T_2588, _T_2589) @[el2_ifu_mem_ctl.scala 592:70]
|
|
node _T_2590 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 593:68]
|
|
node _T_2591 = or(ic_act_miss_f, _T_2590) @[el2_ifu_mem_ctl.scala 593:48]
|
|
node bus_reset_data_beat_cnt = or(_T_2591, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 593:91]
|
|
node _T_2592 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 594:32]
|
|
node _T_2593 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 594:57]
|
|
node bus_hold_data_beat_cnt = and(_T_2592, _T_2593) @[el2_ifu_mem_ctl.scala 594:55]
|
|
wire bus_data_beat_count : UInt<3>
|
|
bus_data_beat_count <= UInt<1>("h00")
|
|
node _T_2594 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 596:115]
|
|
node _T_2595 = tail(_T_2594, 1) @[el2_ifu_mem_ctl.scala 596:115]
|
|
node _T_2596 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2597 = mux(bus_inc_data_beat_cnt, _T_2595, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2598 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2599 = or(_T_2596, _T_2597) @[Mux.scala 27:72]
|
|
node _T_2600 = or(_T_2599, _T_2598) @[Mux.scala 27:72]
|
|
wire _T_2601 : UInt<3> @[Mux.scala 27:72]
|
|
_T_2601 <= _T_2600 @[Mux.scala 27:72]
|
|
bus_new_data_beat_count <= _T_2601 @[el2_ifu_mem_ctl.scala 596:27]
|
|
reg _T_2602 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 597:56]
|
|
_T_2602 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 597:56]
|
|
bus_data_beat_count <= _T_2602 @[el2_ifu_mem_ctl.scala 597:23]
|
|
node _T_2603 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 598:49]
|
|
node _T_2604 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:73]
|
|
node _T_2605 = and(_T_2603, _T_2604) @[el2_ifu_mem_ctl.scala 598:71]
|
|
node _T_2606 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:116]
|
|
node _T_2607 = and(last_data_recieved_ff, _T_2606) @[el2_ifu_mem_ctl.scala 598:114]
|
|
node last_data_recieved_in = or(_T_2605, _T_2607) @[el2_ifu_mem_ctl.scala 598:89]
|
|
reg _T_2608 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 599:58]
|
|
_T_2608 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 599:58]
|
|
last_data_recieved_ff <= _T_2608 @[el2_ifu_mem_ctl.scala 599:25]
|
|
node _T_2609 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 601:35]
|
|
node _T_2610 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 601:56]
|
|
node _T_2611 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 602:39]
|
|
node _T_2612 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 603:45]
|
|
node _T_2613 = tail(_T_2612, 1) @[el2_ifu_mem_ctl.scala 603:45]
|
|
node _T_2614 = mux(bus_cmd_sent, _T_2613, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 603:12]
|
|
node _T_2615 = mux(scnd_miss_req_q, _T_2611, _T_2614) @[el2_ifu_mem_ctl.scala 602:10]
|
|
node bus_new_rd_addr_count = mux(_T_2609, _T_2610, _T_2615) @[el2_ifu_mem_ctl.scala 601:34]
|
|
reg _T_2616 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 604:55]
|
|
_T_2616 <= bus_new_rd_addr_count @[el2_ifu_mem_ctl.scala 604:55]
|
|
bus_rd_addr_count <= _T_2616 @[el2_ifu_mem_ctl.scala 604:21]
|
|
node _T_2617 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 606:48]
|
|
node _T_2618 = and(_T_2617, miss_pending) @[el2_ifu_mem_ctl.scala 606:68]
|
|
node _T_2619 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 606:85]
|
|
node bus_inc_cmd_beat_cnt = and(_T_2618, _T_2619) @[el2_ifu_mem_ctl.scala 606:83]
|
|
node _T_2620 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 607:51]
|
|
node _T_2621 = and(ic_act_miss_f, _T_2620) @[el2_ifu_mem_ctl.scala 607:49]
|
|
node bus_reset_cmd_beat_cnt_0 = or(_T_2621, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 607:73]
|
|
node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 608:57]
|
|
node _T_2622 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:31]
|
|
node _T_2623 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 609:71]
|
|
node _T_2624 = or(_T_2623, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 609:87]
|
|
node _T_2625 = eq(_T_2624, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:55]
|
|
node bus_hold_cmd_beat_cnt = and(_T_2622, _T_2625) @[el2_ifu_mem_ctl.scala 609:53]
|
|
node _T_2626 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 610:46]
|
|
node bus_cmd_beat_en = or(_T_2626, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 610:62]
|
|
node _T_2627 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 611:107]
|
|
node _T_2628 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 612:46]
|
|
node _T_2629 = tail(_T_2628, 1) @[el2_ifu_mem_ctl.scala 612:46]
|
|
node _T_2630 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2631 = mux(_T_2627, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2632 = mux(bus_inc_cmd_beat_cnt, _T_2629, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2633 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2634 = or(_T_2630, _T_2631) @[Mux.scala 27:72]
|
|
node _T_2635 = or(_T_2634, _T_2632) @[Mux.scala 27:72]
|
|
node _T_2636 = or(_T_2635, _T_2633) @[Mux.scala 27:72]
|
|
wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72]
|
|
bus_new_cmd_beat_count <= _T_2636 @[Mux.scala 27:72]
|
|
reg _T_2637 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_cmd_beat_en : @[Reg.scala 28:19]
|
|
_T_2637 <= bus_new_cmd_beat_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_cmd_beat_count <= _T_2637 @[el2_ifu_mem_ctl.scala 613:22]
|
|
node _T_2638 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 614:69]
|
|
node _T_2639 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 614:101]
|
|
node _T_2640 = mux(uncacheable_miss_ff, _T_2638, _T_2639) @[el2_ifu_mem_ctl.scala 614:28]
|
|
bus_last_data_beat <= _T_2640 @[el2_ifu_mem_ctl.scala 614:22]
|
|
node _T_2641 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 615:35]
|
|
bus_ifu_wr_en <= _T_2641 @[el2_ifu_mem_ctl.scala 615:17]
|
|
node _T_2642 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 616:41]
|
|
bus_ifu_wr_en_ff <= _T_2642 @[el2_ifu_mem_ctl.scala 616:20]
|
|
node _T_2643 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 617:44]
|
|
node _T_2644 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 617:61]
|
|
node _T_2645 = and(_T_2643, _T_2644) @[el2_ifu_mem_ctl.scala 617:59]
|
|
node _T_2646 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 617:103]
|
|
node _T_2647 = eq(_T_2646, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 617:84]
|
|
node _T_2648 = and(_T_2645, _T_2647) @[el2_ifu_mem_ctl.scala 617:82]
|
|
node _T_2649 = and(_T_2648, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 617:108]
|
|
bus_ifu_wr_en_ff_q <= _T_2649 @[el2_ifu_mem_ctl.scala 617:22]
|
|
node _T_2650 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 618:51]
|
|
node _T_2651 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 618:68]
|
|
node bus_ifu_wr_en_ff_wo_err = and(_T_2650, _T_2651) @[el2_ifu_mem_ctl.scala 618:66]
|
|
reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 619:61]
|
|
ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 619:61]
|
|
node _T_2652 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 620:66]
|
|
node _T_2653 = and(ic_act_miss_f_delayed, _T_2652) @[el2_ifu_mem_ctl.scala 620:53]
|
|
node _T_2654 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 620:86]
|
|
node _T_2655 = and(_T_2653, _T_2654) @[el2_ifu_mem_ctl.scala 620:84]
|
|
reset_tag_valid_for_miss <= _T_2655 @[el2_ifu_mem_ctl.scala 620:28]
|
|
node _T_2656 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 621:47]
|
|
node _T_2657 = and(_T_2656, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 621:50]
|
|
node _T_2658 = and(_T_2657, miss_pending) @[el2_ifu_mem_ctl.scala 621:68]
|
|
bus_ifu_wr_data_error <= _T_2658 @[el2_ifu_mem_ctl.scala 621:25]
|
|
node _T_2659 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 622:48]
|
|
node _T_2660 = and(_T_2659, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 622:52]
|
|
node _T_2661 = and(_T_2660, miss_pending) @[el2_ifu_mem_ctl.scala 622:73]
|
|
bus_ifu_wr_data_error_ff <= _T_2661 @[el2_ifu_mem_ctl.scala 622:28]
|
|
wire ifc_dma_access_ok_d : UInt<1>
|
|
ifc_dma_access_ok_d <= UInt<1>("h00")
|
|
reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 624:62]
|
|
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 624:62]
|
|
node _T_2662 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 625:43]
|
|
ic_crit_wd_rdy <= _T_2662 @[el2_ifu_mem_ctl.scala 625:18]
|
|
node _T_2663 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 626:35]
|
|
last_beat <= _T_2663 @[el2_ifu_mem_ctl.scala 626:13]
|
|
reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 627:18]
|
|
node _T_2664 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 629:50]
|
|
node _T_2665 = and(io.ifc_dma_access_ok, _T_2664) @[el2_ifu_mem_ctl.scala 629:47]
|
|
node _T_2666 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 629:70]
|
|
node _T_2667 = and(_T_2665, _T_2666) @[el2_ifu_mem_ctl.scala 629:68]
|
|
ifc_dma_access_ok_d <= _T_2667 @[el2_ifu_mem_ctl.scala 629:23]
|
|
node _T_2668 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:54]
|
|
node _T_2669 = and(io.ifc_dma_access_ok, _T_2668) @[el2_ifu_mem_ctl.scala 630:51]
|
|
node _T_2670 = and(_T_2669, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 630:72]
|
|
node _T_2671 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 630:111]
|
|
node _T_2672 = and(_T_2670, _T_2671) @[el2_ifu_mem_ctl.scala 630:97]
|
|
node _T_2673 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:129]
|
|
node ifc_dma_access_q_ok = and(_T_2672, _T_2673) @[el2_ifu_mem_ctl.scala 630:127]
|
|
io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 631:17]
|
|
reg _T_2674 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 632:51]
|
|
_T_2674 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 632:51]
|
|
dma_iccm_req_f <= _T_2674 @[el2_ifu_mem_ctl.scala 632:18]
|
|
node _T_2675 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 633:40]
|
|
node _T_2676 = and(_T_2675, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 633:58]
|
|
node _T_2677 = or(_T_2676, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 633:79]
|
|
io.iccm_wren <= _T_2677 @[el2_ifu_mem_ctl.scala 633:16]
|
|
node _T_2678 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 634:40]
|
|
node _T_2679 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:60]
|
|
node _T_2680 = and(_T_2678, _T_2679) @[el2_ifu_mem_ctl.scala 634:58]
|
|
node _T_2681 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 634:104]
|
|
node _T_2682 = or(_T_2680, _T_2681) @[el2_ifu_mem_ctl.scala 634:79]
|
|
io.iccm_rden <= _T_2682 @[el2_ifu_mem_ctl.scala 634:16]
|
|
node _T_2683 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 635:43]
|
|
node _T_2684 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 635:63]
|
|
node iccm_dma_rden = and(_T_2683, _T_2684) @[el2_ifu_mem_ctl.scala 635:61]
|
|
node _T_2685 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2686 = mux(_T_2685, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2687 = and(_T_2686, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 636:47]
|
|
io.iccm_wr_size <= _T_2687 @[el2_ifu_mem_ctl.scala 636:19]
|
|
node _T_2688 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 638:54]
|
|
node _T_2689 = bits(_T_2688, 0, 0) @[el2_lib.scala 237:58]
|
|
node _T_2690 = bits(_T_2688, 1, 1) @[el2_lib.scala 237:58]
|
|
node _T_2691 = bits(_T_2688, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2692 = bits(_T_2688, 4, 4) @[el2_lib.scala 237:58]
|
|
node _T_2693 = bits(_T_2688, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2694 = bits(_T_2688, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2695 = bits(_T_2688, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2696 = bits(_T_2688, 11, 11) @[el2_lib.scala 237:58]
|
|
node _T_2697 = bits(_T_2688, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_2698 = bits(_T_2688, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_2699 = bits(_T_2688, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2700 = bits(_T_2688, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_2701 = bits(_T_2688, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2702 = bits(_T_2688, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2703 = bits(_T_2688, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2704 = bits(_T_2688, 26, 26) @[el2_lib.scala 237:58]
|
|
node _T_2705 = bits(_T_2688, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_2706 = bits(_T_2688, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_2707 = xor(_T_2689, _T_2690) @[el2_lib.scala 237:74]
|
|
node _T_2708 = xor(_T_2707, _T_2691) @[el2_lib.scala 237:74]
|
|
node _T_2709 = xor(_T_2708, _T_2692) @[el2_lib.scala 237:74]
|
|
node _T_2710 = xor(_T_2709, _T_2693) @[el2_lib.scala 237:74]
|
|
node _T_2711 = xor(_T_2710, _T_2694) @[el2_lib.scala 237:74]
|
|
node _T_2712 = xor(_T_2711, _T_2695) @[el2_lib.scala 237:74]
|
|
node _T_2713 = xor(_T_2712, _T_2696) @[el2_lib.scala 237:74]
|
|
node _T_2714 = xor(_T_2713, _T_2697) @[el2_lib.scala 237:74]
|
|
node _T_2715 = xor(_T_2714, _T_2698) @[el2_lib.scala 237:74]
|
|
node _T_2716 = xor(_T_2715, _T_2699) @[el2_lib.scala 237:74]
|
|
node _T_2717 = xor(_T_2716, _T_2700) @[el2_lib.scala 237:74]
|
|
node _T_2718 = xor(_T_2717, _T_2701) @[el2_lib.scala 237:74]
|
|
node _T_2719 = xor(_T_2718, _T_2702) @[el2_lib.scala 237:74]
|
|
node _T_2720 = xor(_T_2719, _T_2703) @[el2_lib.scala 237:74]
|
|
node _T_2721 = xor(_T_2720, _T_2704) @[el2_lib.scala 237:74]
|
|
node _T_2722 = xor(_T_2721, _T_2705) @[el2_lib.scala 237:74]
|
|
node _T_2723 = xor(_T_2722, _T_2706) @[el2_lib.scala 237:74]
|
|
node _T_2724 = bits(_T_2688, 0, 0) @[el2_lib.scala 237:58]
|
|
node _T_2725 = bits(_T_2688, 2, 2) @[el2_lib.scala 237:58]
|
|
node _T_2726 = bits(_T_2688, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2727 = bits(_T_2688, 5, 5) @[el2_lib.scala 237:58]
|
|
node _T_2728 = bits(_T_2688, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2729 = bits(_T_2688, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2730 = bits(_T_2688, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2731 = bits(_T_2688, 12, 12) @[el2_lib.scala 237:58]
|
|
node _T_2732 = bits(_T_2688, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_2733 = bits(_T_2688, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_2734 = bits(_T_2688, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2735 = bits(_T_2688, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_2736 = bits(_T_2688, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2737 = bits(_T_2688, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2738 = bits(_T_2688, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2739 = bits(_T_2688, 27, 27) @[el2_lib.scala 237:58]
|
|
node _T_2740 = bits(_T_2688, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_2741 = bits(_T_2688, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_2742 = xor(_T_2724, _T_2725) @[el2_lib.scala 237:74]
|
|
node _T_2743 = xor(_T_2742, _T_2726) @[el2_lib.scala 237:74]
|
|
node _T_2744 = xor(_T_2743, _T_2727) @[el2_lib.scala 237:74]
|
|
node _T_2745 = xor(_T_2744, _T_2728) @[el2_lib.scala 237:74]
|
|
node _T_2746 = xor(_T_2745, _T_2729) @[el2_lib.scala 237:74]
|
|
node _T_2747 = xor(_T_2746, _T_2730) @[el2_lib.scala 237:74]
|
|
node _T_2748 = xor(_T_2747, _T_2731) @[el2_lib.scala 237:74]
|
|
node _T_2749 = xor(_T_2748, _T_2732) @[el2_lib.scala 237:74]
|
|
node _T_2750 = xor(_T_2749, _T_2733) @[el2_lib.scala 237:74]
|
|
node _T_2751 = xor(_T_2750, _T_2734) @[el2_lib.scala 237:74]
|
|
node _T_2752 = xor(_T_2751, _T_2735) @[el2_lib.scala 237:74]
|
|
node _T_2753 = xor(_T_2752, _T_2736) @[el2_lib.scala 237:74]
|
|
node _T_2754 = xor(_T_2753, _T_2737) @[el2_lib.scala 237:74]
|
|
node _T_2755 = xor(_T_2754, _T_2738) @[el2_lib.scala 237:74]
|
|
node _T_2756 = xor(_T_2755, _T_2739) @[el2_lib.scala 237:74]
|
|
node _T_2757 = xor(_T_2756, _T_2740) @[el2_lib.scala 237:74]
|
|
node _T_2758 = xor(_T_2757, _T_2741) @[el2_lib.scala 237:74]
|
|
node _T_2759 = bits(_T_2688, 1, 1) @[el2_lib.scala 237:58]
|
|
node _T_2760 = bits(_T_2688, 2, 2) @[el2_lib.scala 237:58]
|
|
node _T_2761 = bits(_T_2688, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2762 = bits(_T_2688, 7, 7) @[el2_lib.scala 237:58]
|
|
node _T_2763 = bits(_T_2688, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2764 = bits(_T_2688, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2765 = bits(_T_2688, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2766 = bits(_T_2688, 14, 14) @[el2_lib.scala 237:58]
|
|
node _T_2767 = bits(_T_2688, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_2768 = bits(_T_2688, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_2769 = bits(_T_2688, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2770 = bits(_T_2688, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_2771 = bits(_T_2688, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2772 = bits(_T_2688, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2773 = bits(_T_2688, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2774 = bits(_T_2688, 29, 29) @[el2_lib.scala 237:58]
|
|
node _T_2775 = bits(_T_2688, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_2776 = bits(_T_2688, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_2777 = xor(_T_2759, _T_2760) @[el2_lib.scala 237:74]
|
|
node _T_2778 = xor(_T_2777, _T_2761) @[el2_lib.scala 237:74]
|
|
node _T_2779 = xor(_T_2778, _T_2762) @[el2_lib.scala 237:74]
|
|
node _T_2780 = xor(_T_2779, _T_2763) @[el2_lib.scala 237:74]
|
|
node _T_2781 = xor(_T_2780, _T_2764) @[el2_lib.scala 237:74]
|
|
node _T_2782 = xor(_T_2781, _T_2765) @[el2_lib.scala 237:74]
|
|
node _T_2783 = xor(_T_2782, _T_2766) @[el2_lib.scala 237:74]
|
|
node _T_2784 = xor(_T_2783, _T_2767) @[el2_lib.scala 237:74]
|
|
node _T_2785 = xor(_T_2784, _T_2768) @[el2_lib.scala 237:74]
|
|
node _T_2786 = xor(_T_2785, _T_2769) @[el2_lib.scala 237:74]
|
|
node _T_2787 = xor(_T_2786, _T_2770) @[el2_lib.scala 237:74]
|
|
node _T_2788 = xor(_T_2787, _T_2771) @[el2_lib.scala 237:74]
|
|
node _T_2789 = xor(_T_2788, _T_2772) @[el2_lib.scala 237:74]
|
|
node _T_2790 = xor(_T_2789, _T_2773) @[el2_lib.scala 237:74]
|
|
node _T_2791 = xor(_T_2790, _T_2774) @[el2_lib.scala 237:74]
|
|
node _T_2792 = xor(_T_2791, _T_2775) @[el2_lib.scala 237:74]
|
|
node _T_2793 = xor(_T_2792, _T_2776) @[el2_lib.scala 237:74]
|
|
node _T_2794 = bits(_T_2688, 4, 4) @[el2_lib.scala 237:58]
|
|
node _T_2795 = bits(_T_2688, 5, 5) @[el2_lib.scala 237:58]
|
|
node _T_2796 = bits(_T_2688, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2797 = bits(_T_2688, 7, 7) @[el2_lib.scala 237:58]
|
|
node _T_2798 = bits(_T_2688, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2799 = bits(_T_2688, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2800 = bits(_T_2688, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2801 = bits(_T_2688, 18, 18) @[el2_lib.scala 237:58]
|
|
node _T_2802 = bits(_T_2688, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_2803 = bits(_T_2688, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_2804 = bits(_T_2688, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2805 = bits(_T_2688, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_2806 = bits(_T_2688, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2807 = bits(_T_2688, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2808 = bits(_T_2688, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2809 = xor(_T_2794, _T_2795) @[el2_lib.scala 237:74]
|
|
node _T_2810 = xor(_T_2809, _T_2796) @[el2_lib.scala 237:74]
|
|
node _T_2811 = xor(_T_2810, _T_2797) @[el2_lib.scala 237:74]
|
|
node _T_2812 = xor(_T_2811, _T_2798) @[el2_lib.scala 237:74]
|
|
node _T_2813 = xor(_T_2812, _T_2799) @[el2_lib.scala 237:74]
|
|
node _T_2814 = xor(_T_2813, _T_2800) @[el2_lib.scala 237:74]
|
|
node _T_2815 = xor(_T_2814, _T_2801) @[el2_lib.scala 237:74]
|
|
node _T_2816 = xor(_T_2815, _T_2802) @[el2_lib.scala 237:74]
|
|
node _T_2817 = xor(_T_2816, _T_2803) @[el2_lib.scala 237:74]
|
|
node _T_2818 = xor(_T_2817, _T_2804) @[el2_lib.scala 237:74]
|
|
node _T_2819 = xor(_T_2818, _T_2805) @[el2_lib.scala 237:74]
|
|
node _T_2820 = xor(_T_2819, _T_2806) @[el2_lib.scala 237:74]
|
|
node _T_2821 = xor(_T_2820, _T_2807) @[el2_lib.scala 237:74]
|
|
node _T_2822 = xor(_T_2821, _T_2808) @[el2_lib.scala 237:74]
|
|
node _T_2823 = bits(_T_2688, 11, 11) @[el2_lib.scala 237:58]
|
|
node _T_2824 = bits(_T_2688, 12, 12) @[el2_lib.scala 237:58]
|
|
node _T_2825 = bits(_T_2688, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_2826 = bits(_T_2688, 14, 14) @[el2_lib.scala 237:58]
|
|
node _T_2827 = bits(_T_2688, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_2828 = bits(_T_2688, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_2829 = bits(_T_2688, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2830 = bits(_T_2688, 18, 18) @[el2_lib.scala 237:58]
|
|
node _T_2831 = bits(_T_2688, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_2832 = bits(_T_2688, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_2833 = bits(_T_2688, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2834 = bits(_T_2688, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_2835 = bits(_T_2688, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2836 = bits(_T_2688, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2837 = bits(_T_2688, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2838 = xor(_T_2823, _T_2824) @[el2_lib.scala 237:74]
|
|
node _T_2839 = xor(_T_2838, _T_2825) @[el2_lib.scala 237:74]
|
|
node _T_2840 = xor(_T_2839, _T_2826) @[el2_lib.scala 237:74]
|
|
node _T_2841 = xor(_T_2840, _T_2827) @[el2_lib.scala 237:74]
|
|
node _T_2842 = xor(_T_2841, _T_2828) @[el2_lib.scala 237:74]
|
|
node _T_2843 = xor(_T_2842, _T_2829) @[el2_lib.scala 237:74]
|
|
node _T_2844 = xor(_T_2843, _T_2830) @[el2_lib.scala 237:74]
|
|
node _T_2845 = xor(_T_2844, _T_2831) @[el2_lib.scala 237:74]
|
|
node _T_2846 = xor(_T_2845, _T_2832) @[el2_lib.scala 237:74]
|
|
node _T_2847 = xor(_T_2846, _T_2833) @[el2_lib.scala 237:74]
|
|
node _T_2848 = xor(_T_2847, _T_2834) @[el2_lib.scala 237:74]
|
|
node _T_2849 = xor(_T_2848, _T_2835) @[el2_lib.scala 237:74]
|
|
node _T_2850 = xor(_T_2849, _T_2836) @[el2_lib.scala 237:74]
|
|
node _T_2851 = xor(_T_2850, _T_2837) @[el2_lib.scala 237:74]
|
|
node _T_2852 = bits(_T_2688, 26, 26) @[el2_lib.scala 237:58]
|
|
node _T_2853 = bits(_T_2688, 27, 27) @[el2_lib.scala 237:58]
|
|
node _T_2854 = bits(_T_2688, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_2855 = bits(_T_2688, 29, 29) @[el2_lib.scala 237:58]
|
|
node _T_2856 = bits(_T_2688, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_2857 = bits(_T_2688, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_2858 = xor(_T_2852, _T_2853) @[el2_lib.scala 237:74]
|
|
node _T_2859 = xor(_T_2858, _T_2854) @[el2_lib.scala 237:74]
|
|
node _T_2860 = xor(_T_2859, _T_2855) @[el2_lib.scala 237:74]
|
|
node _T_2861 = xor(_T_2860, _T_2856) @[el2_lib.scala 237:74]
|
|
node _T_2862 = xor(_T_2861, _T_2857) @[el2_lib.scala 237:74]
|
|
node _T_2863 = cat(_T_2793, _T_2758) @[Cat.scala 29:58]
|
|
node _T_2864 = cat(_T_2863, _T_2723) @[Cat.scala 29:58]
|
|
node _T_2865 = cat(_T_2862, _T_2851) @[Cat.scala 29:58]
|
|
node _T_2866 = cat(_T_2865, _T_2822) @[Cat.scala 29:58]
|
|
node _T_2867 = cat(_T_2866, _T_2864) @[Cat.scala 29:58]
|
|
node _T_2868 = xorr(_T_2688) @[el2_lib.scala 245:13]
|
|
node _T_2869 = xorr(_T_2867) @[el2_lib.scala 245:23]
|
|
node _T_2870 = xor(_T_2868, _T_2869) @[el2_lib.scala 245:18]
|
|
node _T_2871 = cat(_T_2870, _T_2867) @[Cat.scala 29:58]
|
|
node _T_2872 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 638:93]
|
|
node _T_2873 = bits(_T_2872, 0, 0) @[el2_lib.scala 237:58]
|
|
node _T_2874 = bits(_T_2872, 1, 1) @[el2_lib.scala 237:58]
|
|
node _T_2875 = bits(_T_2872, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2876 = bits(_T_2872, 4, 4) @[el2_lib.scala 237:58]
|
|
node _T_2877 = bits(_T_2872, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2878 = bits(_T_2872, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2879 = bits(_T_2872, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2880 = bits(_T_2872, 11, 11) @[el2_lib.scala 237:58]
|
|
node _T_2881 = bits(_T_2872, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_2882 = bits(_T_2872, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_2883 = bits(_T_2872, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2884 = bits(_T_2872, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_2885 = bits(_T_2872, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2886 = bits(_T_2872, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2887 = bits(_T_2872, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2888 = bits(_T_2872, 26, 26) @[el2_lib.scala 237:58]
|
|
node _T_2889 = bits(_T_2872, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_2890 = bits(_T_2872, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_2891 = xor(_T_2873, _T_2874) @[el2_lib.scala 237:74]
|
|
node _T_2892 = xor(_T_2891, _T_2875) @[el2_lib.scala 237:74]
|
|
node _T_2893 = xor(_T_2892, _T_2876) @[el2_lib.scala 237:74]
|
|
node _T_2894 = xor(_T_2893, _T_2877) @[el2_lib.scala 237:74]
|
|
node _T_2895 = xor(_T_2894, _T_2878) @[el2_lib.scala 237:74]
|
|
node _T_2896 = xor(_T_2895, _T_2879) @[el2_lib.scala 237:74]
|
|
node _T_2897 = xor(_T_2896, _T_2880) @[el2_lib.scala 237:74]
|
|
node _T_2898 = xor(_T_2897, _T_2881) @[el2_lib.scala 237:74]
|
|
node _T_2899 = xor(_T_2898, _T_2882) @[el2_lib.scala 237:74]
|
|
node _T_2900 = xor(_T_2899, _T_2883) @[el2_lib.scala 237:74]
|
|
node _T_2901 = xor(_T_2900, _T_2884) @[el2_lib.scala 237:74]
|
|
node _T_2902 = xor(_T_2901, _T_2885) @[el2_lib.scala 237:74]
|
|
node _T_2903 = xor(_T_2902, _T_2886) @[el2_lib.scala 237:74]
|
|
node _T_2904 = xor(_T_2903, _T_2887) @[el2_lib.scala 237:74]
|
|
node _T_2905 = xor(_T_2904, _T_2888) @[el2_lib.scala 237:74]
|
|
node _T_2906 = xor(_T_2905, _T_2889) @[el2_lib.scala 237:74]
|
|
node _T_2907 = xor(_T_2906, _T_2890) @[el2_lib.scala 237:74]
|
|
node _T_2908 = bits(_T_2872, 0, 0) @[el2_lib.scala 237:58]
|
|
node _T_2909 = bits(_T_2872, 2, 2) @[el2_lib.scala 237:58]
|
|
node _T_2910 = bits(_T_2872, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2911 = bits(_T_2872, 5, 5) @[el2_lib.scala 237:58]
|
|
node _T_2912 = bits(_T_2872, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2913 = bits(_T_2872, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2914 = bits(_T_2872, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2915 = bits(_T_2872, 12, 12) @[el2_lib.scala 237:58]
|
|
node _T_2916 = bits(_T_2872, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_2917 = bits(_T_2872, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_2918 = bits(_T_2872, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2919 = bits(_T_2872, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_2920 = bits(_T_2872, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2921 = bits(_T_2872, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2922 = bits(_T_2872, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2923 = bits(_T_2872, 27, 27) @[el2_lib.scala 237:58]
|
|
node _T_2924 = bits(_T_2872, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_2925 = bits(_T_2872, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_2926 = xor(_T_2908, _T_2909) @[el2_lib.scala 237:74]
|
|
node _T_2927 = xor(_T_2926, _T_2910) @[el2_lib.scala 237:74]
|
|
node _T_2928 = xor(_T_2927, _T_2911) @[el2_lib.scala 237:74]
|
|
node _T_2929 = xor(_T_2928, _T_2912) @[el2_lib.scala 237:74]
|
|
node _T_2930 = xor(_T_2929, _T_2913) @[el2_lib.scala 237:74]
|
|
node _T_2931 = xor(_T_2930, _T_2914) @[el2_lib.scala 237:74]
|
|
node _T_2932 = xor(_T_2931, _T_2915) @[el2_lib.scala 237:74]
|
|
node _T_2933 = xor(_T_2932, _T_2916) @[el2_lib.scala 237:74]
|
|
node _T_2934 = xor(_T_2933, _T_2917) @[el2_lib.scala 237:74]
|
|
node _T_2935 = xor(_T_2934, _T_2918) @[el2_lib.scala 237:74]
|
|
node _T_2936 = xor(_T_2935, _T_2919) @[el2_lib.scala 237:74]
|
|
node _T_2937 = xor(_T_2936, _T_2920) @[el2_lib.scala 237:74]
|
|
node _T_2938 = xor(_T_2937, _T_2921) @[el2_lib.scala 237:74]
|
|
node _T_2939 = xor(_T_2938, _T_2922) @[el2_lib.scala 237:74]
|
|
node _T_2940 = xor(_T_2939, _T_2923) @[el2_lib.scala 237:74]
|
|
node _T_2941 = xor(_T_2940, _T_2924) @[el2_lib.scala 237:74]
|
|
node _T_2942 = xor(_T_2941, _T_2925) @[el2_lib.scala 237:74]
|
|
node _T_2943 = bits(_T_2872, 1, 1) @[el2_lib.scala 237:58]
|
|
node _T_2944 = bits(_T_2872, 2, 2) @[el2_lib.scala 237:58]
|
|
node _T_2945 = bits(_T_2872, 3, 3) @[el2_lib.scala 237:58]
|
|
node _T_2946 = bits(_T_2872, 7, 7) @[el2_lib.scala 237:58]
|
|
node _T_2947 = bits(_T_2872, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2948 = bits(_T_2872, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2949 = bits(_T_2872, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2950 = bits(_T_2872, 14, 14) @[el2_lib.scala 237:58]
|
|
node _T_2951 = bits(_T_2872, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_2952 = bits(_T_2872, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_2953 = bits(_T_2872, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_2954 = bits(_T_2872, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_2955 = bits(_T_2872, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2956 = bits(_T_2872, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2957 = bits(_T_2872, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2958 = bits(_T_2872, 29, 29) @[el2_lib.scala 237:58]
|
|
node _T_2959 = bits(_T_2872, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_2960 = bits(_T_2872, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_2961 = xor(_T_2943, _T_2944) @[el2_lib.scala 237:74]
|
|
node _T_2962 = xor(_T_2961, _T_2945) @[el2_lib.scala 237:74]
|
|
node _T_2963 = xor(_T_2962, _T_2946) @[el2_lib.scala 237:74]
|
|
node _T_2964 = xor(_T_2963, _T_2947) @[el2_lib.scala 237:74]
|
|
node _T_2965 = xor(_T_2964, _T_2948) @[el2_lib.scala 237:74]
|
|
node _T_2966 = xor(_T_2965, _T_2949) @[el2_lib.scala 237:74]
|
|
node _T_2967 = xor(_T_2966, _T_2950) @[el2_lib.scala 237:74]
|
|
node _T_2968 = xor(_T_2967, _T_2951) @[el2_lib.scala 237:74]
|
|
node _T_2969 = xor(_T_2968, _T_2952) @[el2_lib.scala 237:74]
|
|
node _T_2970 = xor(_T_2969, _T_2953) @[el2_lib.scala 237:74]
|
|
node _T_2971 = xor(_T_2970, _T_2954) @[el2_lib.scala 237:74]
|
|
node _T_2972 = xor(_T_2971, _T_2955) @[el2_lib.scala 237:74]
|
|
node _T_2973 = xor(_T_2972, _T_2956) @[el2_lib.scala 237:74]
|
|
node _T_2974 = xor(_T_2973, _T_2957) @[el2_lib.scala 237:74]
|
|
node _T_2975 = xor(_T_2974, _T_2958) @[el2_lib.scala 237:74]
|
|
node _T_2976 = xor(_T_2975, _T_2959) @[el2_lib.scala 237:74]
|
|
node _T_2977 = xor(_T_2976, _T_2960) @[el2_lib.scala 237:74]
|
|
node _T_2978 = bits(_T_2872, 4, 4) @[el2_lib.scala 237:58]
|
|
node _T_2979 = bits(_T_2872, 5, 5) @[el2_lib.scala 237:58]
|
|
node _T_2980 = bits(_T_2872, 6, 6) @[el2_lib.scala 237:58]
|
|
node _T_2981 = bits(_T_2872, 7, 7) @[el2_lib.scala 237:58]
|
|
node _T_2982 = bits(_T_2872, 8, 8) @[el2_lib.scala 237:58]
|
|
node _T_2983 = bits(_T_2872, 9, 9) @[el2_lib.scala 237:58]
|
|
node _T_2984 = bits(_T_2872, 10, 10) @[el2_lib.scala 237:58]
|
|
node _T_2985 = bits(_T_2872, 18, 18) @[el2_lib.scala 237:58]
|
|
node _T_2986 = bits(_T_2872, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_2987 = bits(_T_2872, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_2988 = bits(_T_2872, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_2989 = bits(_T_2872, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_2990 = bits(_T_2872, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_2991 = bits(_T_2872, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_2992 = bits(_T_2872, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_2993 = xor(_T_2978, _T_2979) @[el2_lib.scala 237:74]
|
|
node _T_2994 = xor(_T_2993, _T_2980) @[el2_lib.scala 237:74]
|
|
node _T_2995 = xor(_T_2994, _T_2981) @[el2_lib.scala 237:74]
|
|
node _T_2996 = xor(_T_2995, _T_2982) @[el2_lib.scala 237:74]
|
|
node _T_2997 = xor(_T_2996, _T_2983) @[el2_lib.scala 237:74]
|
|
node _T_2998 = xor(_T_2997, _T_2984) @[el2_lib.scala 237:74]
|
|
node _T_2999 = xor(_T_2998, _T_2985) @[el2_lib.scala 237:74]
|
|
node _T_3000 = xor(_T_2999, _T_2986) @[el2_lib.scala 237:74]
|
|
node _T_3001 = xor(_T_3000, _T_2987) @[el2_lib.scala 237:74]
|
|
node _T_3002 = xor(_T_3001, _T_2988) @[el2_lib.scala 237:74]
|
|
node _T_3003 = xor(_T_3002, _T_2989) @[el2_lib.scala 237:74]
|
|
node _T_3004 = xor(_T_3003, _T_2990) @[el2_lib.scala 237:74]
|
|
node _T_3005 = xor(_T_3004, _T_2991) @[el2_lib.scala 237:74]
|
|
node _T_3006 = xor(_T_3005, _T_2992) @[el2_lib.scala 237:74]
|
|
node _T_3007 = bits(_T_2872, 11, 11) @[el2_lib.scala 237:58]
|
|
node _T_3008 = bits(_T_2872, 12, 12) @[el2_lib.scala 237:58]
|
|
node _T_3009 = bits(_T_2872, 13, 13) @[el2_lib.scala 237:58]
|
|
node _T_3010 = bits(_T_2872, 14, 14) @[el2_lib.scala 237:58]
|
|
node _T_3011 = bits(_T_2872, 15, 15) @[el2_lib.scala 237:58]
|
|
node _T_3012 = bits(_T_2872, 16, 16) @[el2_lib.scala 237:58]
|
|
node _T_3013 = bits(_T_2872, 17, 17) @[el2_lib.scala 237:58]
|
|
node _T_3014 = bits(_T_2872, 18, 18) @[el2_lib.scala 237:58]
|
|
node _T_3015 = bits(_T_2872, 19, 19) @[el2_lib.scala 237:58]
|
|
node _T_3016 = bits(_T_2872, 20, 20) @[el2_lib.scala 237:58]
|
|
node _T_3017 = bits(_T_2872, 21, 21) @[el2_lib.scala 237:58]
|
|
node _T_3018 = bits(_T_2872, 22, 22) @[el2_lib.scala 237:58]
|
|
node _T_3019 = bits(_T_2872, 23, 23) @[el2_lib.scala 237:58]
|
|
node _T_3020 = bits(_T_2872, 24, 24) @[el2_lib.scala 237:58]
|
|
node _T_3021 = bits(_T_2872, 25, 25) @[el2_lib.scala 237:58]
|
|
node _T_3022 = xor(_T_3007, _T_3008) @[el2_lib.scala 237:74]
|
|
node _T_3023 = xor(_T_3022, _T_3009) @[el2_lib.scala 237:74]
|
|
node _T_3024 = xor(_T_3023, _T_3010) @[el2_lib.scala 237:74]
|
|
node _T_3025 = xor(_T_3024, _T_3011) @[el2_lib.scala 237:74]
|
|
node _T_3026 = xor(_T_3025, _T_3012) @[el2_lib.scala 237:74]
|
|
node _T_3027 = xor(_T_3026, _T_3013) @[el2_lib.scala 237:74]
|
|
node _T_3028 = xor(_T_3027, _T_3014) @[el2_lib.scala 237:74]
|
|
node _T_3029 = xor(_T_3028, _T_3015) @[el2_lib.scala 237:74]
|
|
node _T_3030 = xor(_T_3029, _T_3016) @[el2_lib.scala 237:74]
|
|
node _T_3031 = xor(_T_3030, _T_3017) @[el2_lib.scala 237:74]
|
|
node _T_3032 = xor(_T_3031, _T_3018) @[el2_lib.scala 237:74]
|
|
node _T_3033 = xor(_T_3032, _T_3019) @[el2_lib.scala 237:74]
|
|
node _T_3034 = xor(_T_3033, _T_3020) @[el2_lib.scala 237:74]
|
|
node _T_3035 = xor(_T_3034, _T_3021) @[el2_lib.scala 237:74]
|
|
node _T_3036 = bits(_T_2872, 26, 26) @[el2_lib.scala 237:58]
|
|
node _T_3037 = bits(_T_2872, 27, 27) @[el2_lib.scala 237:58]
|
|
node _T_3038 = bits(_T_2872, 28, 28) @[el2_lib.scala 237:58]
|
|
node _T_3039 = bits(_T_2872, 29, 29) @[el2_lib.scala 237:58]
|
|
node _T_3040 = bits(_T_2872, 30, 30) @[el2_lib.scala 237:58]
|
|
node _T_3041 = bits(_T_2872, 31, 31) @[el2_lib.scala 237:58]
|
|
node _T_3042 = xor(_T_3036, _T_3037) @[el2_lib.scala 237:74]
|
|
node _T_3043 = xor(_T_3042, _T_3038) @[el2_lib.scala 237:74]
|
|
node _T_3044 = xor(_T_3043, _T_3039) @[el2_lib.scala 237:74]
|
|
node _T_3045 = xor(_T_3044, _T_3040) @[el2_lib.scala 237:74]
|
|
node _T_3046 = xor(_T_3045, _T_3041) @[el2_lib.scala 237:74]
|
|
node _T_3047 = cat(_T_2977, _T_2942) @[Cat.scala 29:58]
|
|
node _T_3048 = cat(_T_3047, _T_2907) @[Cat.scala 29:58]
|
|
node _T_3049 = cat(_T_3046, _T_3035) @[Cat.scala 29:58]
|
|
node _T_3050 = cat(_T_3049, _T_3006) @[Cat.scala 29:58]
|
|
node _T_3051 = cat(_T_3050, _T_3048) @[Cat.scala 29:58]
|
|
node _T_3052 = xorr(_T_2872) @[el2_lib.scala 245:13]
|
|
node _T_3053 = xorr(_T_3051) @[el2_lib.scala 245:23]
|
|
node _T_3054 = xor(_T_3052, _T_3053) @[el2_lib.scala 245:18]
|
|
node _T_3055 = cat(_T_3054, _T_3051) @[Cat.scala 29:58]
|
|
node dma_mem_ecc = cat(_T_2871, _T_3055) @[Cat.scala 29:58]
|
|
wire iccm_ecc_corr_data_ff : UInt<39>
|
|
iccm_ecc_corr_data_ff <= UInt<1>("h00")
|
|
node _T_3056 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 640:67]
|
|
node _T_3057 = eq(_T_3056, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 640:45]
|
|
node _T_3058 = and(iccm_correct_ecc, _T_3057) @[el2_ifu_mem_ctl.scala 640:43]
|
|
node _T_3059 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58]
|
|
node _T_3060 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 641:20]
|
|
node _T_3061 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 641:43]
|
|
node _T_3062 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 641:63]
|
|
node _T_3063 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 641:86]
|
|
node _T_3064 = cat(_T_3062, _T_3063) @[Cat.scala 29:58]
|
|
node _T_3065 = cat(_T_3060, _T_3061) @[Cat.scala 29:58]
|
|
node _T_3066 = cat(_T_3065, _T_3064) @[Cat.scala 29:58]
|
|
node _T_3067 = mux(_T_3058, _T_3059, _T_3066) @[el2_ifu_mem_ctl.scala 640:25]
|
|
io.iccm_wr_data <= _T_3067 @[el2_ifu_mem_ctl.scala 640:19]
|
|
wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 642:33]
|
|
iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 643:26]
|
|
iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 644:26]
|
|
wire dma_mem_addr_ff : UInt<2>
|
|
dma_mem_addr_ff <= UInt<1>("h00")
|
|
node _T_3068 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 646:51]
|
|
node _T_3069 = bits(_T_3068, 0, 0) @[el2_ifu_mem_ctl.scala 646:55]
|
|
node iccm_dma_rdata_1_muxed = mux(_T_3069, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 646:35]
|
|
wire iccm_double_ecc_error : UInt<2>
|
|
iccm_double_ecc_error <= UInt<1>("h00")
|
|
node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 648:53]
|
|
node _T_3070 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58]
|
|
node _T_3071 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58]
|
|
node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3070, _T_3071) @[el2_ifu_mem_ctl.scala 649:30]
|
|
reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 650:54]
|
|
dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 650:54]
|
|
reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 651:74]
|
|
iccm_dma_rtag_temp <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 651:74]
|
|
io.iccm_dma_rtag <= iccm_dma_rtag_temp @[el2_ifu_mem_ctl.scala 652:20]
|
|
node _T_3072 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 654:69]
|
|
reg _T_3073 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 654:53]
|
|
_T_3073 <= _T_3072 @[el2_ifu_mem_ctl.scala 654:53]
|
|
dma_mem_addr_ff <= _T_3073 @[el2_ifu_mem_ctl.scala 654:19]
|
|
reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 655:59]
|
|
iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 655:59]
|
|
reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 656:76]
|
|
iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 656:76]
|
|
io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[el2_ifu_mem_ctl.scala 657:22]
|
|
reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 658:74]
|
|
iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 658:74]
|
|
io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 659:25]
|
|
reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 660:75]
|
|
iccm_dma_rdata_temp <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 660:75]
|
|
io.iccm_dma_rdata <= iccm_dma_rdata_temp @[el2_ifu_mem_ctl.scala 661:21]
|
|
wire iccm_ecc_corr_index_ff : UInt<14>
|
|
iccm_ecc_corr_index_ff <= UInt<1>("h00")
|
|
node _T_3074 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 663:46]
|
|
node _T_3075 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 663:67]
|
|
node _T_3076 = and(_T_3074, _T_3075) @[el2_ifu_mem_ctl.scala 663:65]
|
|
node _T_3077 = bits(io.dma_mem_addr, 15, 1) @[el2_ifu_mem_ctl.scala 663:101]
|
|
node _T_3078 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 664:31]
|
|
node _T_3079 = eq(_T_3078, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 664:9]
|
|
node _T_3080 = and(_T_3079, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 664:50]
|
|
node _T_3081 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_3082 = bits(io.ifc_fetch_addr_bf, 14, 0) @[el2_ifu_mem_ctl.scala 664:124]
|
|
node _T_3083 = mux(_T_3080, _T_3081, _T_3082) @[el2_ifu_mem_ctl.scala 664:8]
|
|
node _T_3084 = mux(_T_3076, _T_3077, _T_3083) @[el2_ifu_mem_ctl.scala 663:25]
|
|
io.iccm_rw_addr <= _T_3084 @[el2_ifu_mem_ctl.scala 663:19]
|
|
node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58]
|
|
node _T_3085 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 666:76]
|
|
node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3085) @[el2_ifu_mem_ctl.scala 666:53]
|
|
node _T_3086 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 669:75]
|
|
node _T_3087 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:93]
|
|
node _T_3088 = and(_T_3086, _T_3087) @[el2_ifu_mem_ctl.scala 669:91]
|
|
node _T_3089 = and(_T_3088, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 669:113]
|
|
node _T_3090 = or(_T_3089, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 669:130]
|
|
node _T_3091 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:154]
|
|
node _T_3092 = and(_T_3090, _T_3091) @[el2_ifu_mem_ctl.scala 669:152]
|
|
node _T_3093 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 669:75]
|
|
node _T_3094 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:93]
|
|
node _T_3095 = and(_T_3093, _T_3094) @[el2_ifu_mem_ctl.scala 669:91]
|
|
node _T_3096 = and(_T_3095, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 669:113]
|
|
node _T_3097 = or(_T_3096, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 669:130]
|
|
node _T_3098 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:154]
|
|
node _T_3099 = and(_T_3097, _T_3098) @[el2_ifu_mem_ctl.scala 669:152]
|
|
node iccm_ecc_word_enable = cat(_T_3099, _T_3092) @[Cat.scala 29:58]
|
|
node _T_3100 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 670:73]
|
|
node _T_3101 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 670:93]
|
|
node _T_3102 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 670:128]
|
|
wire _T_3103 : UInt<1>[18] @[el2_lib.scala 291:18]
|
|
wire _T_3104 : UInt<1>[18] @[el2_lib.scala 292:18]
|
|
wire _T_3105 : UInt<1>[18] @[el2_lib.scala 293:18]
|
|
wire _T_3106 : UInt<1>[15] @[el2_lib.scala 294:18]
|
|
wire _T_3107 : UInt<1>[15] @[el2_lib.scala 295:18]
|
|
wire _T_3108 : UInt<1>[6] @[el2_lib.scala 296:18]
|
|
node _T_3109 = bits(_T_3101, 0, 0) @[el2_lib.scala 303:36]
|
|
_T_3103[0] <= _T_3109 @[el2_lib.scala 303:30]
|
|
node _T_3110 = bits(_T_3101, 0, 0) @[el2_lib.scala 304:36]
|
|
_T_3104[0] <= _T_3110 @[el2_lib.scala 304:30]
|
|
node _T_3111 = bits(_T_3101, 1, 1) @[el2_lib.scala 303:36]
|
|
_T_3103[1] <= _T_3111 @[el2_lib.scala 303:30]
|
|
node _T_3112 = bits(_T_3101, 1, 1) @[el2_lib.scala 305:36]
|
|
_T_3105[0] <= _T_3112 @[el2_lib.scala 305:30]
|
|
node _T_3113 = bits(_T_3101, 2, 2) @[el2_lib.scala 304:36]
|
|
_T_3104[1] <= _T_3113 @[el2_lib.scala 304:30]
|
|
node _T_3114 = bits(_T_3101, 2, 2) @[el2_lib.scala 305:36]
|
|
_T_3105[1] <= _T_3114 @[el2_lib.scala 305:30]
|
|
node _T_3115 = bits(_T_3101, 3, 3) @[el2_lib.scala 303:36]
|
|
_T_3103[2] <= _T_3115 @[el2_lib.scala 303:30]
|
|
node _T_3116 = bits(_T_3101, 3, 3) @[el2_lib.scala 304:36]
|
|
_T_3104[2] <= _T_3116 @[el2_lib.scala 304:30]
|
|
node _T_3117 = bits(_T_3101, 3, 3) @[el2_lib.scala 305:36]
|
|
_T_3105[2] <= _T_3117 @[el2_lib.scala 305:30]
|
|
node _T_3118 = bits(_T_3101, 4, 4) @[el2_lib.scala 303:36]
|
|
_T_3103[3] <= _T_3118 @[el2_lib.scala 303:30]
|
|
node _T_3119 = bits(_T_3101, 4, 4) @[el2_lib.scala 306:36]
|
|
_T_3106[0] <= _T_3119 @[el2_lib.scala 306:30]
|
|
node _T_3120 = bits(_T_3101, 5, 5) @[el2_lib.scala 304:36]
|
|
_T_3104[3] <= _T_3120 @[el2_lib.scala 304:30]
|
|
node _T_3121 = bits(_T_3101, 5, 5) @[el2_lib.scala 306:36]
|
|
_T_3106[1] <= _T_3121 @[el2_lib.scala 306:30]
|
|
node _T_3122 = bits(_T_3101, 6, 6) @[el2_lib.scala 303:36]
|
|
_T_3103[4] <= _T_3122 @[el2_lib.scala 303:30]
|
|
node _T_3123 = bits(_T_3101, 6, 6) @[el2_lib.scala 304:36]
|
|
_T_3104[4] <= _T_3123 @[el2_lib.scala 304:30]
|
|
node _T_3124 = bits(_T_3101, 6, 6) @[el2_lib.scala 306:36]
|
|
_T_3106[2] <= _T_3124 @[el2_lib.scala 306:30]
|
|
node _T_3125 = bits(_T_3101, 7, 7) @[el2_lib.scala 305:36]
|
|
_T_3105[3] <= _T_3125 @[el2_lib.scala 305:30]
|
|
node _T_3126 = bits(_T_3101, 7, 7) @[el2_lib.scala 306:36]
|
|
_T_3106[3] <= _T_3126 @[el2_lib.scala 306:30]
|
|
node _T_3127 = bits(_T_3101, 8, 8) @[el2_lib.scala 303:36]
|
|
_T_3103[5] <= _T_3127 @[el2_lib.scala 303:30]
|
|
node _T_3128 = bits(_T_3101, 8, 8) @[el2_lib.scala 305:36]
|
|
_T_3105[4] <= _T_3128 @[el2_lib.scala 305:30]
|
|
node _T_3129 = bits(_T_3101, 8, 8) @[el2_lib.scala 306:36]
|
|
_T_3106[4] <= _T_3129 @[el2_lib.scala 306:30]
|
|
node _T_3130 = bits(_T_3101, 9, 9) @[el2_lib.scala 304:36]
|
|
_T_3104[5] <= _T_3130 @[el2_lib.scala 304:30]
|
|
node _T_3131 = bits(_T_3101, 9, 9) @[el2_lib.scala 305:36]
|
|
_T_3105[5] <= _T_3131 @[el2_lib.scala 305:30]
|
|
node _T_3132 = bits(_T_3101, 9, 9) @[el2_lib.scala 306:36]
|
|
_T_3106[5] <= _T_3132 @[el2_lib.scala 306:30]
|
|
node _T_3133 = bits(_T_3101, 10, 10) @[el2_lib.scala 303:36]
|
|
_T_3103[6] <= _T_3133 @[el2_lib.scala 303:30]
|
|
node _T_3134 = bits(_T_3101, 10, 10) @[el2_lib.scala 304:36]
|
|
_T_3104[6] <= _T_3134 @[el2_lib.scala 304:30]
|
|
node _T_3135 = bits(_T_3101, 10, 10) @[el2_lib.scala 305:36]
|
|
_T_3105[6] <= _T_3135 @[el2_lib.scala 305:30]
|
|
node _T_3136 = bits(_T_3101, 10, 10) @[el2_lib.scala 306:36]
|
|
_T_3106[6] <= _T_3136 @[el2_lib.scala 306:30]
|
|
node _T_3137 = bits(_T_3101, 11, 11) @[el2_lib.scala 303:36]
|
|
_T_3103[7] <= _T_3137 @[el2_lib.scala 303:30]
|
|
node _T_3138 = bits(_T_3101, 11, 11) @[el2_lib.scala 307:36]
|
|
_T_3107[0] <= _T_3138 @[el2_lib.scala 307:30]
|
|
node _T_3139 = bits(_T_3101, 12, 12) @[el2_lib.scala 304:36]
|
|
_T_3104[7] <= _T_3139 @[el2_lib.scala 304:30]
|
|
node _T_3140 = bits(_T_3101, 12, 12) @[el2_lib.scala 307:36]
|
|
_T_3107[1] <= _T_3140 @[el2_lib.scala 307:30]
|
|
node _T_3141 = bits(_T_3101, 13, 13) @[el2_lib.scala 303:36]
|
|
_T_3103[8] <= _T_3141 @[el2_lib.scala 303:30]
|
|
node _T_3142 = bits(_T_3101, 13, 13) @[el2_lib.scala 304:36]
|
|
_T_3104[8] <= _T_3142 @[el2_lib.scala 304:30]
|
|
node _T_3143 = bits(_T_3101, 13, 13) @[el2_lib.scala 307:36]
|
|
_T_3107[2] <= _T_3143 @[el2_lib.scala 307:30]
|
|
node _T_3144 = bits(_T_3101, 14, 14) @[el2_lib.scala 305:36]
|
|
_T_3105[7] <= _T_3144 @[el2_lib.scala 305:30]
|
|
node _T_3145 = bits(_T_3101, 14, 14) @[el2_lib.scala 307:36]
|
|
_T_3107[3] <= _T_3145 @[el2_lib.scala 307:30]
|
|
node _T_3146 = bits(_T_3101, 15, 15) @[el2_lib.scala 303:36]
|
|
_T_3103[9] <= _T_3146 @[el2_lib.scala 303:30]
|
|
node _T_3147 = bits(_T_3101, 15, 15) @[el2_lib.scala 305:36]
|
|
_T_3105[8] <= _T_3147 @[el2_lib.scala 305:30]
|
|
node _T_3148 = bits(_T_3101, 15, 15) @[el2_lib.scala 307:36]
|
|
_T_3107[4] <= _T_3148 @[el2_lib.scala 307:30]
|
|
node _T_3149 = bits(_T_3101, 16, 16) @[el2_lib.scala 304:36]
|
|
_T_3104[9] <= _T_3149 @[el2_lib.scala 304:30]
|
|
node _T_3150 = bits(_T_3101, 16, 16) @[el2_lib.scala 305:36]
|
|
_T_3105[9] <= _T_3150 @[el2_lib.scala 305:30]
|
|
node _T_3151 = bits(_T_3101, 16, 16) @[el2_lib.scala 307:36]
|
|
_T_3107[5] <= _T_3151 @[el2_lib.scala 307:30]
|
|
node _T_3152 = bits(_T_3101, 17, 17) @[el2_lib.scala 303:36]
|
|
_T_3103[10] <= _T_3152 @[el2_lib.scala 303:30]
|
|
node _T_3153 = bits(_T_3101, 17, 17) @[el2_lib.scala 304:36]
|
|
_T_3104[10] <= _T_3153 @[el2_lib.scala 304:30]
|
|
node _T_3154 = bits(_T_3101, 17, 17) @[el2_lib.scala 305:36]
|
|
_T_3105[10] <= _T_3154 @[el2_lib.scala 305:30]
|
|
node _T_3155 = bits(_T_3101, 17, 17) @[el2_lib.scala 307:36]
|
|
_T_3107[6] <= _T_3155 @[el2_lib.scala 307:30]
|
|
node _T_3156 = bits(_T_3101, 18, 18) @[el2_lib.scala 306:36]
|
|
_T_3106[7] <= _T_3156 @[el2_lib.scala 306:30]
|
|
node _T_3157 = bits(_T_3101, 18, 18) @[el2_lib.scala 307:36]
|
|
_T_3107[7] <= _T_3157 @[el2_lib.scala 307:30]
|
|
node _T_3158 = bits(_T_3101, 19, 19) @[el2_lib.scala 303:36]
|
|
_T_3103[11] <= _T_3158 @[el2_lib.scala 303:30]
|
|
node _T_3159 = bits(_T_3101, 19, 19) @[el2_lib.scala 306:36]
|
|
_T_3106[8] <= _T_3159 @[el2_lib.scala 306:30]
|
|
node _T_3160 = bits(_T_3101, 19, 19) @[el2_lib.scala 307:36]
|
|
_T_3107[8] <= _T_3160 @[el2_lib.scala 307:30]
|
|
node _T_3161 = bits(_T_3101, 20, 20) @[el2_lib.scala 304:36]
|
|
_T_3104[11] <= _T_3161 @[el2_lib.scala 304:30]
|
|
node _T_3162 = bits(_T_3101, 20, 20) @[el2_lib.scala 306:36]
|
|
_T_3106[9] <= _T_3162 @[el2_lib.scala 306:30]
|
|
node _T_3163 = bits(_T_3101, 20, 20) @[el2_lib.scala 307:36]
|
|
_T_3107[9] <= _T_3163 @[el2_lib.scala 307:30]
|
|
node _T_3164 = bits(_T_3101, 21, 21) @[el2_lib.scala 303:36]
|
|
_T_3103[12] <= _T_3164 @[el2_lib.scala 303:30]
|
|
node _T_3165 = bits(_T_3101, 21, 21) @[el2_lib.scala 304:36]
|
|
_T_3104[12] <= _T_3165 @[el2_lib.scala 304:30]
|
|
node _T_3166 = bits(_T_3101, 21, 21) @[el2_lib.scala 306:36]
|
|
_T_3106[10] <= _T_3166 @[el2_lib.scala 306:30]
|
|
node _T_3167 = bits(_T_3101, 21, 21) @[el2_lib.scala 307:36]
|
|
_T_3107[10] <= _T_3167 @[el2_lib.scala 307:30]
|
|
node _T_3168 = bits(_T_3101, 22, 22) @[el2_lib.scala 305:36]
|
|
_T_3105[11] <= _T_3168 @[el2_lib.scala 305:30]
|
|
node _T_3169 = bits(_T_3101, 22, 22) @[el2_lib.scala 306:36]
|
|
_T_3106[11] <= _T_3169 @[el2_lib.scala 306:30]
|
|
node _T_3170 = bits(_T_3101, 22, 22) @[el2_lib.scala 307:36]
|
|
_T_3107[11] <= _T_3170 @[el2_lib.scala 307:30]
|
|
node _T_3171 = bits(_T_3101, 23, 23) @[el2_lib.scala 303:36]
|
|
_T_3103[13] <= _T_3171 @[el2_lib.scala 303:30]
|
|
node _T_3172 = bits(_T_3101, 23, 23) @[el2_lib.scala 305:36]
|
|
_T_3105[12] <= _T_3172 @[el2_lib.scala 305:30]
|
|
node _T_3173 = bits(_T_3101, 23, 23) @[el2_lib.scala 306:36]
|
|
_T_3106[12] <= _T_3173 @[el2_lib.scala 306:30]
|
|
node _T_3174 = bits(_T_3101, 23, 23) @[el2_lib.scala 307:36]
|
|
_T_3107[12] <= _T_3174 @[el2_lib.scala 307:30]
|
|
node _T_3175 = bits(_T_3101, 24, 24) @[el2_lib.scala 304:36]
|
|
_T_3104[13] <= _T_3175 @[el2_lib.scala 304:30]
|
|
node _T_3176 = bits(_T_3101, 24, 24) @[el2_lib.scala 305:36]
|
|
_T_3105[13] <= _T_3176 @[el2_lib.scala 305:30]
|
|
node _T_3177 = bits(_T_3101, 24, 24) @[el2_lib.scala 306:36]
|
|
_T_3106[13] <= _T_3177 @[el2_lib.scala 306:30]
|
|
node _T_3178 = bits(_T_3101, 24, 24) @[el2_lib.scala 307:36]
|
|
_T_3107[13] <= _T_3178 @[el2_lib.scala 307:30]
|
|
node _T_3179 = bits(_T_3101, 25, 25) @[el2_lib.scala 303:36]
|
|
_T_3103[14] <= _T_3179 @[el2_lib.scala 303:30]
|
|
node _T_3180 = bits(_T_3101, 25, 25) @[el2_lib.scala 304:36]
|
|
_T_3104[14] <= _T_3180 @[el2_lib.scala 304:30]
|
|
node _T_3181 = bits(_T_3101, 25, 25) @[el2_lib.scala 305:36]
|
|
_T_3105[14] <= _T_3181 @[el2_lib.scala 305:30]
|
|
node _T_3182 = bits(_T_3101, 25, 25) @[el2_lib.scala 306:36]
|
|
_T_3106[14] <= _T_3182 @[el2_lib.scala 306:30]
|
|
node _T_3183 = bits(_T_3101, 25, 25) @[el2_lib.scala 307:36]
|
|
_T_3107[14] <= _T_3183 @[el2_lib.scala 307:30]
|
|
node _T_3184 = bits(_T_3101, 26, 26) @[el2_lib.scala 303:36]
|
|
_T_3103[15] <= _T_3184 @[el2_lib.scala 303:30]
|
|
node _T_3185 = bits(_T_3101, 26, 26) @[el2_lib.scala 308:36]
|
|
_T_3108[0] <= _T_3185 @[el2_lib.scala 308:30]
|
|
node _T_3186 = bits(_T_3101, 27, 27) @[el2_lib.scala 304:36]
|
|
_T_3104[15] <= _T_3186 @[el2_lib.scala 304:30]
|
|
node _T_3187 = bits(_T_3101, 27, 27) @[el2_lib.scala 308:36]
|
|
_T_3108[1] <= _T_3187 @[el2_lib.scala 308:30]
|
|
node _T_3188 = bits(_T_3101, 28, 28) @[el2_lib.scala 303:36]
|
|
_T_3103[16] <= _T_3188 @[el2_lib.scala 303:30]
|
|
node _T_3189 = bits(_T_3101, 28, 28) @[el2_lib.scala 304:36]
|
|
_T_3104[16] <= _T_3189 @[el2_lib.scala 304:30]
|
|
node _T_3190 = bits(_T_3101, 28, 28) @[el2_lib.scala 308:36]
|
|
_T_3108[2] <= _T_3190 @[el2_lib.scala 308:30]
|
|
node _T_3191 = bits(_T_3101, 29, 29) @[el2_lib.scala 305:36]
|
|
_T_3105[15] <= _T_3191 @[el2_lib.scala 305:30]
|
|
node _T_3192 = bits(_T_3101, 29, 29) @[el2_lib.scala 308:36]
|
|
_T_3108[3] <= _T_3192 @[el2_lib.scala 308:30]
|
|
node _T_3193 = bits(_T_3101, 30, 30) @[el2_lib.scala 303:36]
|
|
_T_3103[17] <= _T_3193 @[el2_lib.scala 303:30]
|
|
node _T_3194 = bits(_T_3101, 30, 30) @[el2_lib.scala 305:36]
|
|
_T_3105[16] <= _T_3194 @[el2_lib.scala 305:30]
|
|
node _T_3195 = bits(_T_3101, 30, 30) @[el2_lib.scala 308:36]
|
|
_T_3108[4] <= _T_3195 @[el2_lib.scala 308:30]
|
|
node _T_3196 = bits(_T_3101, 31, 31) @[el2_lib.scala 304:36]
|
|
_T_3104[17] <= _T_3196 @[el2_lib.scala 304:30]
|
|
node _T_3197 = bits(_T_3101, 31, 31) @[el2_lib.scala 305:36]
|
|
_T_3105[17] <= _T_3197 @[el2_lib.scala 305:30]
|
|
node _T_3198 = bits(_T_3101, 31, 31) @[el2_lib.scala 308:36]
|
|
_T_3108[5] <= _T_3198 @[el2_lib.scala 308:30]
|
|
node _T_3199 = xorr(_T_3101) @[el2_lib.scala 311:30]
|
|
node _T_3200 = xorr(_T_3102) @[el2_lib.scala 311:44]
|
|
node _T_3201 = xor(_T_3199, _T_3200) @[el2_lib.scala 311:35]
|
|
node _T_3202 = not(UInt<1>("h00")) @[el2_lib.scala 311:52]
|
|
node _T_3203 = and(_T_3201, _T_3202) @[el2_lib.scala 311:50]
|
|
node _T_3204 = bits(_T_3102, 5, 5) @[el2_lib.scala 311:68]
|
|
node _T_3205 = cat(_T_3108[2], _T_3108[1]) @[el2_lib.scala 311:76]
|
|
node _T_3206 = cat(_T_3205, _T_3108[0]) @[el2_lib.scala 311:76]
|
|
node _T_3207 = cat(_T_3108[5], _T_3108[4]) @[el2_lib.scala 311:76]
|
|
node _T_3208 = cat(_T_3207, _T_3108[3]) @[el2_lib.scala 311:76]
|
|
node _T_3209 = cat(_T_3208, _T_3206) @[el2_lib.scala 311:76]
|
|
node _T_3210 = xorr(_T_3209) @[el2_lib.scala 311:83]
|
|
node _T_3211 = xor(_T_3204, _T_3210) @[el2_lib.scala 311:71]
|
|
node _T_3212 = bits(_T_3102, 4, 4) @[el2_lib.scala 311:95]
|
|
node _T_3213 = cat(_T_3107[2], _T_3107[1]) @[el2_lib.scala 311:103]
|
|
node _T_3214 = cat(_T_3213, _T_3107[0]) @[el2_lib.scala 311:103]
|
|
node _T_3215 = cat(_T_3107[4], _T_3107[3]) @[el2_lib.scala 311:103]
|
|
node _T_3216 = cat(_T_3107[6], _T_3107[5]) @[el2_lib.scala 311:103]
|
|
node _T_3217 = cat(_T_3216, _T_3215) @[el2_lib.scala 311:103]
|
|
node _T_3218 = cat(_T_3217, _T_3214) @[el2_lib.scala 311:103]
|
|
node _T_3219 = cat(_T_3107[8], _T_3107[7]) @[el2_lib.scala 311:103]
|
|
node _T_3220 = cat(_T_3107[10], _T_3107[9]) @[el2_lib.scala 311:103]
|
|
node _T_3221 = cat(_T_3220, _T_3219) @[el2_lib.scala 311:103]
|
|
node _T_3222 = cat(_T_3107[12], _T_3107[11]) @[el2_lib.scala 311:103]
|
|
node _T_3223 = cat(_T_3107[14], _T_3107[13]) @[el2_lib.scala 311:103]
|
|
node _T_3224 = cat(_T_3223, _T_3222) @[el2_lib.scala 311:103]
|
|
node _T_3225 = cat(_T_3224, _T_3221) @[el2_lib.scala 311:103]
|
|
node _T_3226 = cat(_T_3225, _T_3218) @[el2_lib.scala 311:103]
|
|
node _T_3227 = xorr(_T_3226) @[el2_lib.scala 311:110]
|
|
node _T_3228 = xor(_T_3212, _T_3227) @[el2_lib.scala 311:98]
|
|
node _T_3229 = bits(_T_3102, 3, 3) @[el2_lib.scala 311:122]
|
|
node _T_3230 = cat(_T_3106[2], _T_3106[1]) @[el2_lib.scala 311:130]
|
|
node _T_3231 = cat(_T_3230, _T_3106[0]) @[el2_lib.scala 311:130]
|
|
node _T_3232 = cat(_T_3106[4], _T_3106[3]) @[el2_lib.scala 311:130]
|
|
node _T_3233 = cat(_T_3106[6], _T_3106[5]) @[el2_lib.scala 311:130]
|
|
node _T_3234 = cat(_T_3233, _T_3232) @[el2_lib.scala 311:130]
|
|
node _T_3235 = cat(_T_3234, _T_3231) @[el2_lib.scala 311:130]
|
|
node _T_3236 = cat(_T_3106[8], _T_3106[7]) @[el2_lib.scala 311:130]
|
|
node _T_3237 = cat(_T_3106[10], _T_3106[9]) @[el2_lib.scala 311:130]
|
|
node _T_3238 = cat(_T_3237, _T_3236) @[el2_lib.scala 311:130]
|
|
node _T_3239 = cat(_T_3106[12], _T_3106[11]) @[el2_lib.scala 311:130]
|
|
node _T_3240 = cat(_T_3106[14], _T_3106[13]) @[el2_lib.scala 311:130]
|
|
node _T_3241 = cat(_T_3240, _T_3239) @[el2_lib.scala 311:130]
|
|
node _T_3242 = cat(_T_3241, _T_3238) @[el2_lib.scala 311:130]
|
|
node _T_3243 = cat(_T_3242, _T_3235) @[el2_lib.scala 311:130]
|
|
node _T_3244 = xorr(_T_3243) @[el2_lib.scala 311:137]
|
|
node _T_3245 = xor(_T_3229, _T_3244) @[el2_lib.scala 311:125]
|
|
node _T_3246 = bits(_T_3102, 2, 2) @[el2_lib.scala 311:149]
|
|
node _T_3247 = cat(_T_3105[1], _T_3105[0]) @[el2_lib.scala 311:157]
|
|
node _T_3248 = cat(_T_3105[3], _T_3105[2]) @[el2_lib.scala 311:157]
|
|
node _T_3249 = cat(_T_3248, _T_3247) @[el2_lib.scala 311:157]
|
|
node _T_3250 = cat(_T_3105[5], _T_3105[4]) @[el2_lib.scala 311:157]
|
|
node _T_3251 = cat(_T_3105[8], _T_3105[7]) @[el2_lib.scala 311:157]
|
|
node _T_3252 = cat(_T_3251, _T_3105[6]) @[el2_lib.scala 311:157]
|
|
node _T_3253 = cat(_T_3252, _T_3250) @[el2_lib.scala 311:157]
|
|
node _T_3254 = cat(_T_3253, _T_3249) @[el2_lib.scala 311:157]
|
|
node _T_3255 = cat(_T_3105[10], _T_3105[9]) @[el2_lib.scala 311:157]
|
|
node _T_3256 = cat(_T_3105[12], _T_3105[11]) @[el2_lib.scala 311:157]
|
|
node _T_3257 = cat(_T_3256, _T_3255) @[el2_lib.scala 311:157]
|
|
node _T_3258 = cat(_T_3105[14], _T_3105[13]) @[el2_lib.scala 311:157]
|
|
node _T_3259 = cat(_T_3105[17], _T_3105[16]) @[el2_lib.scala 311:157]
|
|
node _T_3260 = cat(_T_3259, _T_3105[15]) @[el2_lib.scala 311:157]
|
|
node _T_3261 = cat(_T_3260, _T_3258) @[el2_lib.scala 311:157]
|
|
node _T_3262 = cat(_T_3261, _T_3257) @[el2_lib.scala 311:157]
|
|
node _T_3263 = cat(_T_3262, _T_3254) @[el2_lib.scala 311:157]
|
|
node _T_3264 = xorr(_T_3263) @[el2_lib.scala 311:164]
|
|
node _T_3265 = xor(_T_3246, _T_3264) @[el2_lib.scala 311:152]
|
|
node _T_3266 = bits(_T_3102, 1, 1) @[el2_lib.scala 311:176]
|
|
node _T_3267 = cat(_T_3104[1], _T_3104[0]) @[el2_lib.scala 311:184]
|
|
node _T_3268 = cat(_T_3104[3], _T_3104[2]) @[el2_lib.scala 311:184]
|
|
node _T_3269 = cat(_T_3268, _T_3267) @[el2_lib.scala 311:184]
|
|
node _T_3270 = cat(_T_3104[5], _T_3104[4]) @[el2_lib.scala 311:184]
|
|
node _T_3271 = cat(_T_3104[8], _T_3104[7]) @[el2_lib.scala 311:184]
|
|
node _T_3272 = cat(_T_3271, _T_3104[6]) @[el2_lib.scala 311:184]
|
|
node _T_3273 = cat(_T_3272, _T_3270) @[el2_lib.scala 311:184]
|
|
node _T_3274 = cat(_T_3273, _T_3269) @[el2_lib.scala 311:184]
|
|
node _T_3275 = cat(_T_3104[10], _T_3104[9]) @[el2_lib.scala 311:184]
|
|
node _T_3276 = cat(_T_3104[12], _T_3104[11]) @[el2_lib.scala 311:184]
|
|
node _T_3277 = cat(_T_3276, _T_3275) @[el2_lib.scala 311:184]
|
|
node _T_3278 = cat(_T_3104[14], _T_3104[13]) @[el2_lib.scala 311:184]
|
|
node _T_3279 = cat(_T_3104[17], _T_3104[16]) @[el2_lib.scala 311:184]
|
|
node _T_3280 = cat(_T_3279, _T_3104[15]) @[el2_lib.scala 311:184]
|
|
node _T_3281 = cat(_T_3280, _T_3278) @[el2_lib.scala 311:184]
|
|
node _T_3282 = cat(_T_3281, _T_3277) @[el2_lib.scala 311:184]
|
|
node _T_3283 = cat(_T_3282, _T_3274) @[el2_lib.scala 311:184]
|
|
node _T_3284 = xorr(_T_3283) @[el2_lib.scala 311:191]
|
|
node _T_3285 = xor(_T_3266, _T_3284) @[el2_lib.scala 311:179]
|
|
node _T_3286 = bits(_T_3102, 0, 0) @[el2_lib.scala 311:203]
|
|
node _T_3287 = cat(_T_3103[1], _T_3103[0]) @[el2_lib.scala 311:211]
|
|
node _T_3288 = cat(_T_3103[3], _T_3103[2]) @[el2_lib.scala 311:211]
|
|
node _T_3289 = cat(_T_3288, _T_3287) @[el2_lib.scala 311:211]
|
|
node _T_3290 = cat(_T_3103[5], _T_3103[4]) @[el2_lib.scala 311:211]
|
|
node _T_3291 = cat(_T_3103[8], _T_3103[7]) @[el2_lib.scala 311:211]
|
|
node _T_3292 = cat(_T_3291, _T_3103[6]) @[el2_lib.scala 311:211]
|
|
node _T_3293 = cat(_T_3292, _T_3290) @[el2_lib.scala 311:211]
|
|
node _T_3294 = cat(_T_3293, _T_3289) @[el2_lib.scala 311:211]
|
|
node _T_3295 = cat(_T_3103[10], _T_3103[9]) @[el2_lib.scala 311:211]
|
|
node _T_3296 = cat(_T_3103[12], _T_3103[11]) @[el2_lib.scala 311:211]
|
|
node _T_3297 = cat(_T_3296, _T_3295) @[el2_lib.scala 311:211]
|
|
node _T_3298 = cat(_T_3103[14], _T_3103[13]) @[el2_lib.scala 311:211]
|
|
node _T_3299 = cat(_T_3103[17], _T_3103[16]) @[el2_lib.scala 311:211]
|
|
node _T_3300 = cat(_T_3299, _T_3103[15]) @[el2_lib.scala 311:211]
|
|
node _T_3301 = cat(_T_3300, _T_3298) @[el2_lib.scala 311:211]
|
|
node _T_3302 = cat(_T_3301, _T_3297) @[el2_lib.scala 311:211]
|
|
node _T_3303 = cat(_T_3302, _T_3294) @[el2_lib.scala 311:211]
|
|
node _T_3304 = xorr(_T_3303) @[el2_lib.scala 311:218]
|
|
node _T_3305 = xor(_T_3286, _T_3304) @[el2_lib.scala 311:206]
|
|
node _T_3306 = cat(_T_3265, _T_3285) @[Cat.scala 29:58]
|
|
node _T_3307 = cat(_T_3306, _T_3305) @[Cat.scala 29:58]
|
|
node _T_3308 = cat(_T_3228, _T_3245) @[Cat.scala 29:58]
|
|
node _T_3309 = cat(_T_3203, _T_3211) @[Cat.scala 29:58]
|
|
node _T_3310 = cat(_T_3309, _T_3308) @[Cat.scala 29:58]
|
|
node _T_3311 = cat(_T_3310, _T_3307) @[Cat.scala 29:58]
|
|
node _T_3312 = neq(_T_3311, UInt<1>("h00")) @[el2_lib.scala 312:44]
|
|
node _T_3313 = and(_T_3100, _T_3312) @[el2_lib.scala 312:32]
|
|
node _T_3314 = bits(_T_3311, 6, 6) @[el2_lib.scala 312:64]
|
|
node _T_3315 = and(_T_3313, _T_3314) @[el2_lib.scala 312:53]
|
|
node _T_3316 = neq(_T_3311, UInt<1>("h00")) @[el2_lib.scala 313:44]
|
|
node _T_3317 = and(_T_3100, _T_3316) @[el2_lib.scala 313:32]
|
|
node _T_3318 = bits(_T_3311, 6, 6) @[el2_lib.scala 313:65]
|
|
node _T_3319 = not(_T_3318) @[el2_lib.scala 313:55]
|
|
node _T_3320 = and(_T_3317, _T_3319) @[el2_lib.scala 313:53]
|
|
wire _T_3321 : UInt<1>[39] @[el2_lib.scala 314:26]
|
|
node _T_3322 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3323 = eq(_T_3322, UInt<1>("h01")) @[el2_lib.scala 317:41]
|
|
_T_3321[0] <= _T_3323 @[el2_lib.scala 317:23]
|
|
node _T_3324 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3325 = eq(_T_3324, UInt<2>("h02")) @[el2_lib.scala 317:41]
|
|
_T_3321[1] <= _T_3325 @[el2_lib.scala 317:23]
|
|
node _T_3326 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3327 = eq(_T_3326, UInt<2>("h03")) @[el2_lib.scala 317:41]
|
|
_T_3321[2] <= _T_3327 @[el2_lib.scala 317:23]
|
|
node _T_3328 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3329 = eq(_T_3328, UInt<3>("h04")) @[el2_lib.scala 317:41]
|
|
_T_3321[3] <= _T_3329 @[el2_lib.scala 317:23]
|
|
node _T_3330 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3331 = eq(_T_3330, UInt<3>("h05")) @[el2_lib.scala 317:41]
|
|
_T_3321[4] <= _T_3331 @[el2_lib.scala 317:23]
|
|
node _T_3332 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3333 = eq(_T_3332, UInt<3>("h06")) @[el2_lib.scala 317:41]
|
|
_T_3321[5] <= _T_3333 @[el2_lib.scala 317:23]
|
|
node _T_3334 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3335 = eq(_T_3334, UInt<3>("h07")) @[el2_lib.scala 317:41]
|
|
_T_3321[6] <= _T_3335 @[el2_lib.scala 317:23]
|
|
node _T_3336 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3337 = eq(_T_3336, UInt<4>("h08")) @[el2_lib.scala 317:41]
|
|
_T_3321[7] <= _T_3337 @[el2_lib.scala 317:23]
|
|
node _T_3338 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3339 = eq(_T_3338, UInt<4>("h09")) @[el2_lib.scala 317:41]
|
|
_T_3321[8] <= _T_3339 @[el2_lib.scala 317:23]
|
|
node _T_3340 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3341 = eq(_T_3340, UInt<4>("h0a")) @[el2_lib.scala 317:41]
|
|
_T_3321[9] <= _T_3341 @[el2_lib.scala 317:23]
|
|
node _T_3342 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3343 = eq(_T_3342, UInt<4>("h0b")) @[el2_lib.scala 317:41]
|
|
_T_3321[10] <= _T_3343 @[el2_lib.scala 317:23]
|
|
node _T_3344 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3345 = eq(_T_3344, UInt<4>("h0c")) @[el2_lib.scala 317:41]
|
|
_T_3321[11] <= _T_3345 @[el2_lib.scala 317:23]
|
|
node _T_3346 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3347 = eq(_T_3346, UInt<4>("h0d")) @[el2_lib.scala 317:41]
|
|
_T_3321[12] <= _T_3347 @[el2_lib.scala 317:23]
|
|
node _T_3348 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3349 = eq(_T_3348, UInt<4>("h0e")) @[el2_lib.scala 317:41]
|
|
_T_3321[13] <= _T_3349 @[el2_lib.scala 317:23]
|
|
node _T_3350 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3351 = eq(_T_3350, UInt<4>("h0f")) @[el2_lib.scala 317:41]
|
|
_T_3321[14] <= _T_3351 @[el2_lib.scala 317:23]
|
|
node _T_3352 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3353 = eq(_T_3352, UInt<5>("h010")) @[el2_lib.scala 317:41]
|
|
_T_3321[15] <= _T_3353 @[el2_lib.scala 317:23]
|
|
node _T_3354 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3355 = eq(_T_3354, UInt<5>("h011")) @[el2_lib.scala 317:41]
|
|
_T_3321[16] <= _T_3355 @[el2_lib.scala 317:23]
|
|
node _T_3356 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3357 = eq(_T_3356, UInt<5>("h012")) @[el2_lib.scala 317:41]
|
|
_T_3321[17] <= _T_3357 @[el2_lib.scala 317:23]
|
|
node _T_3358 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3359 = eq(_T_3358, UInt<5>("h013")) @[el2_lib.scala 317:41]
|
|
_T_3321[18] <= _T_3359 @[el2_lib.scala 317:23]
|
|
node _T_3360 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3361 = eq(_T_3360, UInt<5>("h014")) @[el2_lib.scala 317:41]
|
|
_T_3321[19] <= _T_3361 @[el2_lib.scala 317:23]
|
|
node _T_3362 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3363 = eq(_T_3362, UInt<5>("h015")) @[el2_lib.scala 317:41]
|
|
_T_3321[20] <= _T_3363 @[el2_lib.scala 317:23]
|
|
node _T_3364 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3365 = eq(_T_3364, UInt<5>("h016")) @[el2_lib.scala 317:41]
|
|
_T_3321[21] <= _T_3365 @[el2_lib.scala 317:23]
|
|
node _T_3366 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3367 = eq(_T_3366, UInt<5>("h017")) @[el2_lib.scala 317:41]
|
|
_T_3321[22] <= _T_3367 @[el2_lib.scala 317:23]
|
|
node _T_3368 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3369 = eq(_T_3368, UInt<5>("h018")) @[el2_lib.scala 317:41]
|
|
_T_3321[23] <= _T_3369 @[el2_lib.scala 317:23]
|
|
node _T_3370 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3371 = eq(_T_3370, UInt<5>("h019")) @[el2_lib.scala 317:41]
|
|
_T_3321[24] <= _T_3371 @[el2_lib.scala 317:23]
|
|
node _T_3372 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3373 = eq(_T_3372, UInt<5>("h01a")) @[el2_lib.scala 317:41]
|
|
_T_3321[25] <= _T_3373 @[el2_lib.scala 317:23]
|
|
node _T_3374 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3375 = eq(_T_3374, UInt<5>("h01b")) @[el2_lib.scala 317:41]
|
|
_T_3321[26] <= _T_3375 @[el2_lib.scala 317:23]
|
|
node _T_3376 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3377 = eq(_T_3376, UInt<5>("h01c")) @[el2_lib.scala 317:41]
|
|
_T_3321[27] <= _T_3377 @[el2_lib.scala 317:23]
|
|
node _T_3378 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3379 = eq(_T_3378, UInt<5>("h01d")) @[el2_lib.scala 317:41]
|
|
_T_3321[28] <= _T_3379 @[el2_lib.scala 317:23]
|
|
node _T_3380 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3381 = eq(_T_3380, UInt<5>("h01e")) @[el2_lib.scala 317:41]
|
|
_T_3321[29] <= _T_3381 @[el2_lib.scala 317:23]
|
|
node _T_3382 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3383 = eq(_T_3382, UInt<5>("h01f")) @[el2_lib.scala 317:41]
|
|
_T_3321[30] <= _T_3383 @[el2_lib.scala 317:23]
|
|
node _T_3384 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3385 = eq(_T_3384, UInt<6>("h020")) @[el2_lib.scala 317:41]
|
|
_T_3321[31] <= _T_3385 @[el2_lib.scala 317:23]
|
|
node _T_3386 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3387 = eq(_T_3386, UInt<6>("h021")) @[el2_lib.scala 317:41]
|
|
_T_3321[32] <= _T_3387 @[el2_lib.scala 317:23]
|
|
node _T_3388 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3389 = eq(_T_3388, UInt<6>("h022")) @[el2_lib.scala 317:41]
|
|
_T_3321[33] <= _T_3389 @[el2_lib.scala 317:23]
|
|
node _T_3390 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3391 = eq(_T_3390, UInt<6>("h023")) @[el2_lib.scala 317:41]
|
|
_T_3321[34] <= _T_3391 @[el2_lib.scala 317:23]
|
|
node _T_3392 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3393 = eq(_T_3392, UInt<6>("h024")) @[el2_lib.scala 317:41]
|
|
_T_3321[35] <= _T_3393 @[el2_lib.scala 317:23]
|
|
node _T_3394 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3395 = eq(_T_3394, UInt<6>("h025")) @[el2_lib.scala 317:41]
|
|
_T_3321[36] <= _T_3395 @[el2_lib.scala 317:23]
|
|
node _T_3396 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3397 = eq(_T_3396, UInt<6>("h026")) @[el2_lib.scala 317:41]
|
|
_T_3321[37] <= _T_3397 @[el2_lib.scala 317:23]
|
|
node _T_3398 = bits(_T_3311, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3399 = eq(_T_3398, UInt<6>("h027")) @[el2_lib.scala 317:41]
|
|
_T_3321[38] <= _T_3399 @[el2_lib.scala 317:23]
|
|
node _T_3400 = bits(_T_3102, 6, 6) @[el2_lib.scala 319:37]
|
|
node _T_3401 = bits(_T_3101, 31, 26) @[el2_lib.scala 319:45]
|
|
node _T_3402 = bits(_T_3102, 5, 5) @[el2_lib.scala 319:60]
|
|
node _T_3403 = bits(_T_3101, 25, 11) @[el2_lib.scala 319:68]
|
|
node _T_3404 = bits(_T_3102, 4, 4) @[el2_lib.scala 319:83]
|
|
node _T_3405 = bits(_T_3101, 10, 4) @[el2_lib.scala 319:91]
|
|
node _T_3406 = bits(_T_3102, 3, 3) @[el2_lib.scala 319:105]
|
|
node _T_3407 = bits(_T_3101, 3, 1) @[el2_lib.scala 319:113]
|
|
node _T_3408 = bits(_T_3102, 2, 2) @[el2_lib.scala 319:126]
|
|
node _T_3409 = bits(_T_3101, 0, 0) @[el2_lib.scala 319:134]
|
|
node _T_3410 = bits(_T_3102, 1, 0) @[el2_lib.scala 319:145]
|
|
node _T_3411 = cat(_T_3409, _T_3410) @[Cat.scala 29:58]
|
|
node _T_3412 = cat(_T_3406, _T_3407) @[Cat.scala 29:58]
|
|
node _T_3413 = cat(_T_3412, _T_3408) @[Cat.scala 29:58]
|
|
node _T_3414 = cat(_T_3413, _T_3411) @[Cat.scala 29:58]
|
|
node _T_3415 = cat(_T_3403, _T_3404) @[Cat.scala 29:58]
|
|
node _T_3416 = cat(_T_3415, _T_3405) @[Cat.scala 29:58]
|
|
node _T_3417 = cat(_T_3400, _T_3401) @[Cat.scala 29:58]
|
|
node _T_3418 = cat(_T_3417, _T_3402) @[Cat.scala 29:58]
|
|
node _T_3419 = cat(_T_3418, _T_3416) @[Cat.scala 29:58]
|
|
node _T_3420 = cat(_T_3419, _T_3414) @[Cat.scala 29:58]
|
|
node _T_3421 = bits(_T_3315, 0, 0) @[el2_lib.scala 320:49]
|
|
node _T_3422 = cat(_T_3321[1], _T_3321[0]) @[el2_lib.scala 320:69]
|
|
node _T_3423 = cat(_T_3321[3], _T_3321[2]) @[el2_lib.scala 320:69]
|
|
node _T_3424 = cat(_T_3423, _T_3422) @[el2_lib.scala 320:69]
|
|
node _T_3425 = cat(_T_3321[5], _T_3321[4]) @[el2_lib.scala 320:69]
|
|
node _T_3426 = cat(_T_3321[8], _T_3321[7]) @[el2_lib.scala 320:69]
|
|
node _T_3427 = cat(_T_3426, _T_3321[6]) @[el2_lib.scala 320:69]
|
|
node _T_3428 = cat(_T_3427, _T_3425) @[el2_lib.scala 320:69]
|
|
node _T_3429 = cat(_T_3428, _T_3424) @[el2_lib.scala 320:69]
|
|
node _T_3430 = cat(_T_3321[10], _T_3321[9]) @[el2_lib.scala 320:69]
|
|
node _T_3431 = cat(_T_3321[13], _T_3321[12]) @[el2_lib.scala 320:69]
|
|
node _T_3432 = cat(_T_3431, _T_3321[11]) @[el2_lib.scala 320:69]
|
|
node _T_3433 = cat(_T_3432, _T_3430) @[el2_lib.scala 320:69]
|
|
node _T_3434 = cat(_T_3321[15], _T_3321[14]) @[el2_lib.scala 320:69]
|
|
node _T_3435 = cat(_T_3321[18], _T_3321[17]) @[el2_lib.scala 320:69]
|
|
node _T_3436 = cat(_T_3435, _T_3321[16]) @[el2_lib.scala 320:69]
|
|
node _T_3437 = cat(_T_3436, _T_3434) @[el2_lib.scala 320:69]
|
|
node _T_3438 = cat(_T_3437, _T_3433) @[el2_lib.scala 320:69]
|
|
node _T_3439 = cat(_T_3438, _T_3429) @[el2_lib.scala 320:69]
|
|
node _T_3440 = cat(_T_3321[20], _T_3321[19]) @[el2_lib.scala 320:69]
|
|
node _T_3441 = cat(_T_3321[23], _T_3321[22]) @[el2_lib.scala 320:69]
|
|
node _T_3442 = cat(_T_3441, _T_3321[21]) @[el2_lib.scala 320:69]
|
|
node _T_3443 = cat(_T_3442, _T_3440) @[el2_lib.scala 320:69]
|
|
node _T_3444 = cat(_T_3321[25], _T_3321[24]) @[el2_lib.scala 320:69]
|
|
node _T_3445 = cat(_T_3321[28], _T_3321[27]) @[el2_lib.scala 320:69]
|
|
node _T_3446 = cat(_T_3445, _T_3321[26]) @[el2_lib.scala 320:69]
|
|
node _T_3447 = cat(_T_3446, _T_3444) @[el2_lib.scala 320:69]
|
|
node _T_3448 = cat(_T_3447, _T_3443) @[el2_lib.scala 320:69]
|
|
node _T_3449 = cat(_T_3321[30], _T_3321[29]) @[el2_lib.scala 320:69]
|
|
node _T_3450 = cat(_T_3321[33], _T_3321[32]) @[el2_lib.scala 320:69]
|
|
node _T_3451 = cat(_T_3450, _T_3321[31]) @[el2_lib.scala 320:69]
|
|
node _T_3452 = cat(_T_3451, _T_3449) @[el2_lib.scala 320:69]
|
|
node _T_3453 = cat(_T_3321[35], _T_3321[34]) @[el2_lib.scala 320:69]
|
|
node _T_3454 = cat(_T_3321[38], _T_3321[37]) @[el2_lib.scala 320:69]
|
|
node _T_3455 = cat(_T_3454, _T_3321[36]) @[el2_lib.scala 320:69]
|
|
node _T_3456 = cat(_T_3455, _T_3453) @[el2_lib.scala 320:69]
|
|
node _T_3457 = cat(_T_3456, _T_3452) @[el2_lib.scala 320:69]
|
|
node _T_3458 = cat(_T_3457, _T_3448) @[el2_lib.scala 320:69]
|
|
node _T_3459 = cat(_T_3458, _T_3439) @[el2_lib.scala 320:69]
|
|
node _T_3460 = xor(_T_3459, _T_3420) @[el2_lib.scala 320:76]
|
|
node _T_3461 = mux(_T_3421, _T_3460, _T_3420) @[el2_lib.scala 320:31]
|
|
node _T_3462 = bits(_T_3461, 37, 32) @[el2_lib.scala 322:37]
|
|
node _T_3463 = bits(_T_3461, 30, 16) @[el2_lib.scala 322:61]
|
|
node _T_3464 = bits(_T_3461, 14, 8) @[el2_lib.scala 322:86]
|
|
node _T_3465 = bits(_T_3461, 6, 4) @[el2_lib.scala 322:110]
|
|
node _T_3466 = bits(_T_3461, 2, 2) @[el2_lib.scala 322:133]
|
|
node _T_3467 = cat(_T_3465, _T_3466) @[Cat.scala 29:58]
|
|
node _T_3468 = cat(_T_3462, _T_3463) @[Cat.scala 29:58]
|
|
node _T_3469 = cat(_T_3468, _T_3464) @[Cat.scala 29:58]
|
|
node _T_3470 = cat(_T_3469, _T_3467) @[Cat.scala 29:58]
|
|
node _T_3471 = bits(_T_3461, 38, 38) @[el2_lib.scala 323:39]
|
|
node _T_3472 = bits(_T_3311, 6, 0) @[el2_lib.scala 323:56]
|
|
node _T_3473 = eq(_T_3472, UInt<7>("h040")) @[el2_lib.scala 323:62]
|
|
node _T_3474 = xor(_T_3471, _T_3473) @[el2_lib.scala 323:44]
|
|
node _T_3475 = bits(_T_3461, 31, 31) @[el2_lib.scala 323:102]
|
|
node _T_3476 = bits(_T_3461, 15, 15) @[el2_lib.scala 323:124]
|
|
node _T_3477 = bits(_T_3461, 7, 7) @[el2_lib.scala 323:146]
|
|
node _T_3478 = bits(_T_3461, 3, 3) @[el2_lib.scala 323:167]
|
|
node _T_3479 = bits(_T_3461, 1, 0) @[el2_lib.scala 323:188]
|
|
node _T_3480 = cat(_T_3477, _T_3478) @[Cat.scala 29:58]
|
|
node _T_3481 = cat(_T_3480, _T_3479) @[Cat.scala 29:58]
|
|
node _T_3482 = cat(_T_3474, _T_3475) @[Cat.scala 29:58]
|
|
node _T_3483 = cat(_T_3482, _T_3476) @[Cat.scala 29:58]
|
|
node _T_3484 = cat(_T_3483, _T_3481) @[Cat.scala 29:58]
|
|
node _T_3485 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 670:73]
|
|
node _T_3486 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 670:93]
|
|
node _T_3487 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 670:128]
|
|
wire _T_3488 : UInt<1>[18] @[el2_lib.scala 291:18]
|
|
wire _T_3489 : UInt<1>[18] @[el2_lib.scala 292:18]
|
|
wire _T_3490 : UInt<1>[18] @[el2_lib.scala 293:18]
|
|
wire _T_3491 : UInt<1>[15] @[el2_lib.scala 294:18]
|
|
wire _T_3492 : UInt<1>[15] @[el2_lib.scala 295:18]
|
|
wire _T_3493 : UInt<1>[6] @[el2_lib.scala 296:18]
|
|
node _T_3494 = bits(_T_3486, 0, 0) @[el2_lib.scala 303:36]
|
|
_T_3488[0] <= _T_3494 @[el2_lib.scala 303:30]
|
|
node _T_3495 = bits(_T_3486, 0, 0) @[el2_lib.scala 304:36]
|
|
_T_3489[0] <= _T_3495 @[el2_lib.scala 304:30]
|
|
node _T_3496 = bits(_T_3486, 1, 1) @[el2_lib.scala 303:36]
|
|
_T_3488[1] <= _T_3496 @[el2_lib.scala 303:30]
|
|
node _T_3497 = bits(_T_3486, 1, 1) @[el2_lib.scala 305:36]
|
|
_T_3490[0] <= _T_3497 @[el2_lib.scala 305:30]
|
|
node _T_3498 = bits(_T_3486, 2, 2) @[el2_lib.scala 304:36]
|
|
_T_3489[1] <= _T_3498 @[el2_lib.scala 304:30]
|
|
node _T_3499 = bits(_T_3486, 2, 2) @[el2_lib.scala 305:36]
|
|
_T_3490[1] <= _T_3499 @[el2_lib.scala 305:30]
|
|
node _T_3500 = bits(_T_3486, 3, 3) @[el2_lib.scala 303:36]
|
|
_T_3488[2] <= _T_3500 @[el2_lib.scala 303:30]
|
|
node _T_3501 = bits(_T_3486, 3, 3) @[el2_lib.scala 304:36]
|
|
_T_3489[2] <= _T_3501 @[el2_lib.scala 304:30]
|
|
node _T_3502 = bits(_T_3486, 3, 3) @[el2_lib.scala 305:36]
|
|
_T_3490[2] <= _T_3502 @[el2_lib.scala 305:30]
|
|
node _T_3503 = bits(_T_3486, 4, 4) @[el2_lib.scala 303:36]
|
|
_T_3488[3] <= _T_3503 @[el2_lib.scala 303:30]
|
|
node _T_3504 = bits(_T_3486, 4, 4) @[el2_lib.scala 306:36]
|
|
_T_3491[0] <= _T_3504 @[el2_lib.scala 306:30]
|
|
node _T_3505 = bits(_T_3486, 5, 5) @[el2_lib.scala 304:36]
|
|
_T_3489[3] <= _T_3505 @[el2_lib.scala 304:30]
|
|
node _T_3506 = bits(_T_3486, 5, 5) @[el2_lib.scala 306:36]
|
|
_T_3491[1] <= _T_3506 @[el2_lib.scala 306:30]
|
|
node _T_3507 = bits(_T_3486, 6, 6) @[el2_lib.scala 303:36]
|
|
_T_3488[4] <= _T_3507 @[el2_lib.scala 303:30]
|
|
node _T_3508 = bits(_T_3486, 6, 6) @[el2_lib.scala 304:36]
|
|
_T_3489[4] <= _T_3508 @[el2_lib.scala 304:30]
|
|
node _T_3509 = bits(_T_3486, 6, 6) @[el2_lib.scala 306:36]
|
|
_T_3491[2] <= _T_3509 @[el2_lib.scala 306:30]
|
|
node _T_3510 = bits(_T_3486, 7, 7) @[el2_lib.scala 305:36]
|
|
_T_3490[3] <= _T_3510 @[el2_lib.scala 305:30]
|
|
node _T_3511 = bits(_T_3486, 7, 7) @[el2_lib.scala 306:36]
|
|
_T_3491[3] <= _T_3511 @[el2_lib.scala 306:30]
|
|
node _T_3512 = bits(_T_3486, 8, 8) @[el2_lib.scala 303:36]
|
|
_T_3488[5] <= _T_3512 @[el2_lib.scala 303:30]
|
|
node _T_3513 = bits(_T_3486, 8, 8) @[el2_lib.scala 305:36]
|
|
_T_3490[4] <= _T_3513 @[el2_lib.scala 305:30]
|
|
node _T_3514 = bits(_T_3486, 8, 8) @[el2_lib.scala 306:36]
|
|
_T_3491[4] <= _T_3514 @[el2_lib.scala 306:30]
|
|
node _T_3515 = bits(_T_3486, 9, 9) @[el2_lib.scala 304:36]
|
|
_T_3489[5] <= _T_3515 @[el2_lib.scala 304:30]
|
|
node _T_3516 = bits(_T_3486, 9, 9) @[el2_lib.scala 305:36]
|
|
_T_3490[5] <= _T_3516 @[el2_lib.scala 305:30]
|
|
node _T_3517 = bits(_T_3486, 9, 9) @[el2_lib.scala 306:36]
|
|
_T_3491[5] <= _T_3517 @[el2_lib.scala 306:30]
|
|
node _T_3518 = bits(_T_3486, 10, 10) @[el2_lib.scala 303:36]
|
|
_T_3488[6] <= _T_3518 @[el2_lib.scala 303:30]
|
|
node _T_3519 = bits(_T_3486, 10, 10) @[el2_lib.scala 304:36]
|
|
_T_3489[6] <= _T_3519 @[el2_lib.scala 304:30]
|
|
node _T_3520 = bits(_T_3486, 10, 10) @[el2_lib.scala 305:36]
|
|
_T_3490[6] <= _T_3520 @[el2_lib.scala 305:30]
|
|
node _T_3521 = bits(_T_3486, 10, 10) @[el2_lib.scala 306:36]
|
|
_T_3491[6] <= _T_3521 @[el2_lib.scala 306:30]
|
|
node _T_3522 = bits(_T_3486, 11, 11) @[el2_lib.scala 303:36]
|
|
_T_3488[7] <= _T_3522 @[el2_lib.scala 303:30]
|
|
node _T_3523 = bits(_T_3486, 11, 11) @[el2_lib.scala 307:36]
|
|
_T_3492[0] <= _T_3523 @[el2_lib.scala 307:30]
|
|
node _T_3524 = bits(_T_3486, 12, 12) @[el2_lib.scala 304:36]
|
|
_T_3489[7] <= _T_3524 @[el2_lib.scala 304:30]
|
|
node _T_3525 = bits(_T_3486, 12, 12) @[el2_lib.scala 307:36]
|
|
_T_3492[1] <= _T_3525 @[el2_lib.scala 307:30]
|
|
node _T_3526 = bits(_T_3486, 13, 13) @[el2_lib.scala 303:36]
|
|
_T_3488[8] <= _T_3526 @[el2_lib.scala 303:30]
|
|
node _T_3527 = bits(_T_3486, 13, 13) @[el2_lib.scala 304:36]
|
|
_T_3489[8] <= _T_3527 @[el2_lib.scala 304:30]
|
|
node _T_3528 = bits(_T_3486, 13, 13) @[el2_lib.scala 307:36]
|
|
_T_3492[2] <= _T_3528 @[el2_lib.scala 307:30]
|
|
node _T_3529 = bits(_T_3486, 14, 14) @[el2_lib.scala 305:36]
|
|
_T_3490[7] <= _T_3529 @[el2_lib.scala 305:30]
|
|
node _T_3530 = bits(_T_3486, 14, 14) @[el2_lib.scala 307:36]
|
|
_T_3492[3] <= _T_3530 @[el2_lib.scala 307:30]
|
|
node _T_3531 = bits(_T_3486, 15, 15) @[el2_lib.scala 303:36]
|
|
_T_3488[9] <= _T_3531 @[el2_lib.scala 303:30]
|
|
node _T_3532 = bits(_T_3486, 15, 15) @[el2_lib.scala 305:36]
|
|
_T_3490[8] <= _T_3532 @[el2_lib.scala 305:30]
|
|
node _T_3533 = bits(_T_3486, 15, 15) @[el2_lib.scala 307:36]
|
|
_T_3492[4] <= _T_3533 @[el2_lib.scala 307:30]
|
|
node _T_3534 = bits(_T_3486, 16, 16) @[el2_lib.scala 304:36]
|
|
_T_3489[9] <= _T_3534 @[el2_lib.scala 304:30]
|
|
node _T_3535 = bits(_T_3486, 16, 16) @[el2_lib.scala 305:36]
|
|
_T_3490[9] <= _T_3535 @[el2_lib.scala 305:30]
|
|
node _T_3536 = bits(_T_3486, 16, 16) @[el2_lib.scala 307:36]
|
|
_T_3492[5] <= _T_3536 @[el2_lib.scala 307:30]
|
|
node _T_3537 = bits(_T_3486, 17, 17) @[el2_lib.scala 303:36]
|
|
_T_3488[10] <= _T_3537 @[el2_lib.scala 303:30]
|
|
node _T_3538 = bits(_T_3486, 17, 17) @[el2_lib.scala 304:36]
|
|
_T_3489[10] <= _T_3538 @[el2_lib.scala 304:30]
|
|
node _T_3539 = bits(_T_3486, 17, 17) @[el2_lib.scala 305:36]
|
|
_T_3490[10] <= _T_3539 @[el2_lib.scala 305:30]
|
|
node _T_3540 = bits(_T_3486, 17, 17) @[el2_lib.scala 307:36]
|
|
_T_3492[6] <= _T_3540 @[el2_lib.scala 307:30]
|
|
node _T_3541 = bits(_T_3486, 18, 18) @[el2_lib.scala 306:36]
|
|
_T_3491[7] <= _T_3541 @[el2_lib.scala 306:30]
|
|
node _T_3542 = bits(_T_3486, 18, 18) @[el2_lib.scala 307:36]
|
|
_T_3492[7] <= _T_3542 @[el2_lib.scala 307:30]
|
|
node _T_3543 = bits(_T_3486, 19, 19) @[el2_lib.scala 303:36]
|
|
_T_3488[11] <= _T_3543 @[el2_lib.scala 303:30]
|
|
node _T_3544 = bits(_T_3486, 19, 19) @[el2_lib.scala 306:36]
|
|
_T_3491[8] <= _T_3544 @[el2_lib.scala 306:30]
|
|
node _T_3545 = bits(_T_3486, 19, 19) @[el2_lib.scala 307:36]
|
|
_T_3492[8] <= _T_3545 @[el2_lib.scala 307:30]
|
|
node _T_3546 = bits(_T_3486, 20, 20) @[el2_lib.scala 304:36]
|
|
_T_3489[11] <= _T_3546 @[el2_lib.scala 304:30]
|
|
node _T_3547 = bits(_T_3486, 20, 20) @[el2_lib.scala 306:36]
|
|
_T_3491[9] <= _T_3547 @[el2_lib.scala 306:30]
|
|
node _T_3548 = bits(_T_3486, 20, 20) @[el2_lib.scala 307:36]
|
|
_T_3492[9] <= _T_3548 @[el2_lib.scala 307:30]
|
|
node _T_3549 = bits(_T_3486, 21, 21) @[el2_lib.scala 303:36]
|
|
_T_3488[12] <= _T_3549 @[el2_lib.scala 303:30]
|
|
node _T_3550 = bits(_T_3486, 21, 21) @[el2_lib.scala 304:36]
|
|
_T_3489[12] <= _T_3550 @[el2_lib.scala 304:30]
|
|
node _T_3551 = bits(_T_3486, 21, 21) @[el2_lib.scala 306:36]
|
|
_T_3491[10] <= _T_3551 @[el2_lib.scala 306:30]
|
|
node _T_3552 = bits(_T_3486, 21, 21) @[el2_lib.scala 307:36]
|
|
_T_3492[10] <= _T_3552 @[el2_lib.scala 307:30]
|
|
node _T_3553 = bits(_T_3486, 22, 22) @[el2_lib.scala 305:36]
|
|
_T_3490[11] <= _T_3553 @[el2_lib.scala 305:30]
|
|
node _T_3554 = bits(_T_3486, 22, 22) @[el2_lib.scala 306:36]
|
|
_T_3491[11] <= _T_3554 @[el2_lib.scala 306:30]
|
|
node _T_3555 = bits(_T_3486, 22, 22) @[el2_lib.scala 307:36]
|
|
_T_3492[11] <= _T_3555 @[el2_lib.scala 307:30]
|
|
node _T_3556 = bits(_T_3486, 23, 23) @[el2_lib.scala 303:36]
|
|
_T_3488[13] <= _T_3556 @[el2_lib.scala 303:30]
|
|
node _T_3557 = bits(_T_3486, 23, 23) @[el2_lib.scala 305:36]
|
|
_T_3490[12] <= _T_3557 @[el2_lib.scala 305:30]
|
|
node _T_3558 = bits(_T_3486, 23, 23) @[el2_lib.scala 306:36]
|
|
_T_3491[12] <= _T_3558 @[el2_lib.scala 306:30]
|
|
node _T_3559 = bits(_T_3486, 23, 23) @[el2_lib.scala 307:36]
|
|
_T_3492[12] <= _T_3559 @[el2_lib.scala 307:30]
|
|
node _T_3560 = bits(_T_3486, 24, 24) @[el2_lib.scala 304:36]
|
|
_T_3489[13] <= _T_3560 @[el2_lib.scala 304:30]
|
|
node _T_3561 = bits(_T_3486, 24, 24) @[el2_lib.scala 305:36]
|
|
_T_3490[13] <= _T_3561 @[el2_lib.scala 305:30]
|
|
node _T_3562 = bits(_T_3486, 24, 24) @[el2_lib.scala 306:36]
|
|
_T_3491[13] <= _T_3562 @[el2_lib.scala 306:30]
|
|
node _T_3563 = bits(_T_3486, 24, 24) @[el2_lib.scala 307:36]
|
|
_T_3492[13] <= _T_3563 @[el2_lib.scala 307:30]
|
|
node _T_3564 = bits(_T_3486, 25, 25) @[el2_lib.scala 303:36]
|
|
_T_3488[14] <= _T_3564 @[el2_lib.scala 303:30]
|
|
node _T_3565 = bits(_T_3486, 25, 25) @[el2_lib.scala 304:36]
|
|
_T_3489[14] <= _T_3565 @[el2_lib.scala 304:30]
|
|
node _T_3566 = bits(_T_3486, 25, 25) @[el2_lib.scala 305:36]
|
|
_T_3490[14] <= _T_3566 @[el2_lib.scala 305:30]
|
|
node _T_3567 = bits(_T_3486, 25, 25) @[el2_lib.scala 306:36]
|
|
_T_3491[14] <= _T_3567 @[el2_lib.scala 306:30]
|
|
node _T_3568 = bits(_T_3486, 25, 25) @[el2_lib.scala 307:36]
|
|
_T_3492[14] <= _T_3568 @[el2_lib.scala 307:30]
|
|
node _T_3569 = bits(_T_3486, 26, 26) @[el2_lib.scala 303:36]
|
|
_T_3488[15] <= _T_3569 @[el2_lib.scala 303:30]
|
|
node _T_3570 = bits(_T_3486, 26, 26) @[el2_lib.scala 308:36]
|
|
_T_3493[0] <= _T_3570 @[el2_lib.scala 308:30]
|
|
node _T_3571 = bits(_T_3486, 27, 27) @[el2_lib.scala 304:36]
|
|
_T_3489[15] <= _T_3571 @[el2_lib.scala 304:30]
|
|
node _T_3572 = bits(_T_3486, 27, 27) @[el2_lib.scala 308:36]
|
|
_T_3493[1] <= _T_3572 @[el2_lib.scala 308:30]
|
|
node _T_3573 = bits(_T_3486, 28, 28) @[el2_lib.scala 303:36]
|
|
_T_3488[16] <= _T_3573 @[el2_lib.scala 303:30]
|
|
node _T_3574 = bits(_T_3486, 28, 28) @[el2_lib.scala 304:36]
|
|
_T_3489[16] <= _T_3574 @[el2_lib.scala 304:30]
|
|
node _T_3575 = bits(_T_3486, 28, 28) @[el2_lib.scala 308:36]
|
|
_T_3493[2] <= _T_3575 @[el2_lib.scala 308:30]
|
|
node _T_3576 = bits(_T_3486, 29, 29) @[el2_lib.scala 305:36]
|
|
_T_3490[15] <= _T_3576 @[el2_lib.scala 305:30]
|
|
node _T_3577 = bits(_T_3486, 29, 29) @[el2_lib.scala 308:36]
|
|
_T_3493[3] <= _T_3577 @[el2_lib.scala 308:30]
|
|
node _T_3578 = bits(_T_3486, 30, 30) @[el2_lib.scala 303:36]
|
|
_T_3488[17] <= _T_3578 @[el2_lib.scala 303:30]
|
|
node _T_3579 = bits(_T_3486, 30, 30) @[el2_lib.scala 305:36]
|
|
_T_3490[16] <= _T_3579 @[el2_lib.scala 305:30]
|
|
node _T_3580 = bits(_T_3486, 30, 30) @[el2_lib.scala 308:36]
|
|
_T_3493[4] <= _T_3580 @[el2_lib.scala 308:30]
|
|
node _T_3581 = bits(_T_3486, 31, 31) @[el2_lib.scala 304:36]
|
|
_T_3489[17] <= _T_3581 @[el2_lib.scala 304:30]
|
|
node _T_3582 = bits(_T_3486, 31, 31) @[el2_lib.scala 305:36]
|
|
_T_3490[17] <= _T_3582 @[el2_lib.scala 305:30]
|
|
node _T_3583 = bits(_T_3486, 31, 31) @[el2_lib.scala 308:36]
|
|
_T_3493[5] <= _T_3583 @[el2_lib.scala 308:30]
|
|
node _T_3584 = xorr(_T_3486) @[el2_lib.scala 311:30]
|
|
node _T_3585 = xorr(_T_3487) @[el2_lib.scala 311:44]
|
|
node _T_3586 = xor(_T_3584, _T_3585) @[el2_lib.scala 311:35]
|
|
node _T_3587 = not(UInt<1>("h00")) @[el2_lib.scala 311:52]
|
|
node _T_3588 = and(_T_3586, _T_3587) @[el2_lib.scala 311:50]
|
|
node _T_3589 = bits(_T_3487, 5, 5) @[el2_lib.scala 311:68]
|
|
node _T_3590 = cat(_T_3493[2], _T_3493[1]) @[el2_lib.scala 311:76]
|
|
node _T_3591 = cat(_T_3590, _T_3493[0]) @[el2_lib.scala 311:76]
|
|
node _T_3592 = cat(_T_3493[5], _T_3493[4]) @[el2_lib.scala 311:76]
|
|
node _T_3593 = cat(_T_3592, _T_3493[3]) @[el2_lib.scala 311:76]
|
|
node _T_3594 = cat(_T_3593, _T_3591) @[el2_lib.scala 311:76]
|
|
node _T_3595 = xorr(_T_3594) @[el2_lib.scala 311:83]
|
|
node _T_3596 = xor(_T_3589, _T_3595) @[el2_lib.scala 311:71]
|
|
node _T_3597 = bits(_T_3487, 4, 4) @[el2_lib.scala 311:95]
|
|
node _T_3598 = cat(_T_3492[2], _T_3492[1]) @[el2_lib.scala 311:103]
|
|
node _T_3599 = cat(_T_3598, _T_3492[0]) @[el2_lib.scala 311:103]
|
|
node _T_3600 = cat(_T_3492[4], _T_3492[3]) @[el2_lib.scala 311:103]
|
|
node _T_3601 = cat(_T_3492[6], _T_3492[5]) @[el2_lib.scala 311:103]
|
|
node _T_3602 = cat(_T_3601, _T_3600) @[el2_lib.scala 311:103]
|
|
node _T_3603 = cat(_T_3602, _T_3599) @[el2_lib.scala 311:103]
|
|
node _T_3604 = cat(_T_3492[8], _T_3492[7]) @[el2_lib.scala 311:103]
|
|
node _T_3605 = cat(_T_3492[10], _T_3492[9]) @[el2_lib.scala 311:103]
|
|
node _T_3606 = cat(_T_3605, _T_3604) @[el2_lib.scala 311:103]
|
|
node _T_3607 = cat(_T_3492[12], _T_3492[11]) @[el2_lib.scala 311:103]
|
|
node _T_3608 = cat(_T_3492[14], _T_3492[13]) @[el2_lib.scala 311:103]
|
|
node _T_3609 = cat(_T_3608, _T_3607) @[el2_lib.scala 311:103]
|
|
node _T_3610 = cat(_T_3609, _T_3606) @[el2_lib.scala 311:103]
|
|
node _T_3611 = cat(_T_3610, _T_3603) @[el2_lib.scala 311:103]
|
|
node _T_3612 = xorr(_T_3611) @[el2_lib.scala 311:110]
|
|
node _T_3613 = xor(_T_3597, _T_3612) @[el2_lib.scala 311:98]
|
|
node _T_3614 = bits(_T_3487, 3, 3) @[el2_lib.scala 311:122]
|
|
node _T_3615 = cat(_T_3491[2], _T_3491[1]) @[el2_lib.scala 311:130]
|
|
node _T_3616 = cat(_T_3615, _T_3491[0]) @[el2_lib.scala 311:130]
|
|
node _T_3617 = cat(_T_3491[4], _T_3491[3]) @[el2_lib.scala 311:130]
|
|
node _T_3618 = cat(_T_3491[6], _T_3491[5]) @[el2_lib.scala 311:130]
|
|
node _T_3619 = cat(_T_3618, _T_3617) @[el2_lib.scala 311:130]
|
|
node _T_3620 = cat(_T_3619, _T_3616) @[el2_lib.scala 311:130]
|
|
node _T_3621 = cat(_T_3491[8], _T_3491[7]) @[el2_lib.scala 311:130]
|
|
node _T_3622 = cat(_T_3491[10], _T_3491[9]) @[el2_lib.scala 311:130]
|
|
node _T_3623 = cat(_T_3622, _T_3621) @[el2_lib.scala 311:130]
|
|
node _T_3624 = cat(_T_3491[12], _T_3491[11]) @[el2_lib.scala 311:130]
|
|
node _T_3625 = cat(_T_3491[14], _T_3491[13]) @[el2_lib.scala 311:130]
|
|
node _T_3626 = cat(_T_3625, _T_3624) @[el2_lib.scala 311:130]
|
|
node _T_3627 = cat(_T_3626, _T_3623) @[el2_lib.scala 311:130]
|
|
node _T_3628 = cat(_T_3627, _T_3620) @[el2_lib.scala 311:130]
|
|
node _T_3629 = xorr(_T_3628) @[el2_lib.scala 311:137]
|
|
node _T_3630 = xor(_T_3614, _T_3629) @[el2_lib.scala 311:125]
|
|
node _T_3631 = bits(_T_3487, 2, 2) @[el2_lib.scala 311:149]
|
|
node _T_3632 = cat(_T_3490[1], _T_3490[0]) @[el2_lib.scala 311:157]
|
|
node _T_3633 = cat(_T_3490[3], _T_3490[2]) @[el2_lib.scala 311:157]
|
|
node _T_3634 = cat(_T_3633, _T_3632) @[el2_lib.scala 311:157]
|
|
node _T_3635 = cat(_T_3490[5], _T_3490[4]) @[el2_lib.scala 311:157]
|
|
node _T_3636 = cat(_T_3490[8], _T_3490[7]) @[el2_lib.scala 311:157]
|
|
node _T_3637 = cat(_T_3636, _T_3490[6]) @[el2_lib.scala 311:157]
|
|
node _T_3638 = cat(_T_3637, _T_3635) @[el2_lib.scala 311:157]
|
|
node _T_3639 = cat(_T_3638, _T_3634) @[el2_lib.scala 311:157]
|
|
node _T_3640 = cat(_T_3490[10], _T_3490[9]) @[el2_lib.scala 311:157]
|
|
node _T_3641 = cat(_T_3490[12], _T_3490[11]) @[el2_lib.scala 311:157]
|
|
node _T_3642 = cat(_T_3641, _T_3640) @[el2_lib.scala 311:157]
|
|
node _T_3643 = cat(_T_3490[14], _T_3490[13]) @[el2_lib.scala 311:157]
|
|
node _T_3644 = cat(_T_3490[17], _T_3490[16]) @[el2_lib.scala 311:157]
|
|
node _T_3645 = cat(_T_3644, _T_3490[15]) @[el2_lib.scala 311:157]
|
|
node _T_3646 = cat(_T_3645, _T_3643) @[el2_lib.scala 311:157]
|
|
node _T_3647 = cat(_T_3646, _T_3642) @[el2_lib.scala 311:157]
|
|
node _T_3648 = cat(_T_3647, _T_3639) @[el2_lib.scala 311:157]
|
|
node _T_3649 = xorr(_T_3648) @[el2_lib.scala 311:164]
|
|
node _T_3650 = xor(_T_3631, _T_3649) @[el2_lib.scala 311:152]
|
|
node _T_3651 = bits(_T_3487, 1, 1) @[el2_lib.scala 311:176]
|
|
node _T_3652 = cat(_T_3489[1], _T_3489[0]) @[el2_lib.scala 311:184]
|
|
node _T_3653 = cat(_T_3489[3], _T_3489[2]) @[el2_lib.scala 311:184]
|
|
node _T_3654 = cat(_T_3653, _T_3652) @[el2_lib.scala 311:184]
|
|
node _T_3655 = cat(_T_3489[5], _T_3489[4]) @[el2_lib.scala 311:184]
|
|
node _T_3656 = cat(_T_3489[8], _T_3489[7]) @[el2_lib.scala 311:184]
|
|
node _T_3657 = cat(_T_3656, _T_3489[6]) @[el2_lib.scala 311:184]
|
|
node _T_3658 = cat(_T_3657, _T_3655) @[el2_lib.scala 311:184]
|
|
node _T_3659 = cat(_T_3658, _T_3654) @[el2_lib.scala 311:184]
|
|
node _T_3660 = cat(_T_3489[10], _T_3489[9]) @[el2_lib.scala 311:184]
|
|
node _T_3661 = cat(_T_3489[12], _T_3489[11]) @[el2_lib.scala 311:184]
|
|
node _T_3662 = cat(_T_3661, _T_3660) @[el2_lib.scala 311:184]
|
|
node _T_3663 = cat(_T_3489[14], _T_3489[13]) @[el2_lib.scala 311:184]
|
|
node _T_3664 = cat(_T_3489[17], _T_3489[16]) @[el2_lib.scala 311:184]
|
|
node _T_3665 = cat(_T_3664, _T_3489[15]) @[el2_lib.scala 311:184]
|
|
node _T_3666 = cat(_T_3665, _T_3663) @[el2_lib.scala 311:184]
|
|
node _T_3667 = cat(_T_3666, _T_3662) @[el2_lib.scala 311:184]
|
|
node _T_3668 = cat(_T_3667, _T_3659) @[el2_lib.scala 311:184]
|
|
node _T_3669 = xorr(_T_3668) @[el2_lib.scala 311:191]
|
|
node _T_3670 = xor(_T_3651, _T_3669) @[el2_lib.scala 311:179]
|
|
node _T_3671 = bits(_T_3487, 0, 0) @[el2_lib.scala 311:203]
|
|
node _T_3672 = cat(_T_3488[1], _T_3488[0]) @[el2_lib.scala 311:211]
|
|
node _T_3673 = cat(_T_3488[3], _T_3488[2]) @[el2_lib.scala 311:211]
|
|
node _T_3674 = cat(_T_3673, _T_3672) @[el2_lib.scala 311:211]
|
|
node _T_3675 = cat(_T_3488[5], _T_3488[4]) @[el2_lib.scala 311:211]
|
|
node _T_3676 = cat(_T_3488[8], _T_3488[7]) @[el2_lib.scala 311:211]
|
|
node _T_3677 = cat(_T_3676, _T_3488[6]) @[el2_lib.scala 311:211]
|
|
node _T_3678 = cat(_T_3677, _T_3675) @[el2_lib.scala 311:211]
|
|
node _T_3679 = cat(_T_3678, _T_3674) @[el2_lib.scala 311:211]
|
|
node _T_3680 = cat(_T_3488[10], _T_3488[9]) @[el2_lib.scala 311:211]
|
|
node _T_3681 = cat(_T_3488[12], _T_3488[11]) @[el2_lib.scala 311:211]
|
|
node _T_3682 = cat(_T_3681, _T_3680) @[el2_lib.scala 311:211]
|
|
node _T_3683 = cat(_T_3488[14], _T_3488[13]) @[el2_lib.scala 311:211]
|
|
node _T_3684 = cat(_T_3488[17], _T_3488[16]) @[el2_lib.scala 311:211]
|
|
node _T_3685 = cat(_T_3684, _T_3488[15]) @[el2_lib.scala 311:211]
|
|
node _T_3686 = cat(_T_3685, _T_3683) @[el2_lib.scala 311:211]
|
|
node _T_3687 = cat(_T_3686, _T_3682) @[el2_lib.scala 311:211]
|
|
node _T_3688 = cat(_T_3687, _T_3679) @[el2_lib.scala 311:211]
|
|
node _T_3689 = xorr(_T_3688) @[el2_lib.scala 311:218]
|
|
node _T_3690 = xor(_T_3671, _T_3689) @[el2_lib.scala 311:206]
|
|
node _T_3691 = cat(_T_3650, _T_3670) @[Cat.scala 29:58]
|
|
node _T_3692 = cat(_T_3691, _T_3690) @[Cat.scala 29:58]
|
|
node _T_3693 = cat(_T_3613, _T_3630) @[Cat.scala 29:58]
|
|
node _T_3694 = cat(_T_3588, _T_3596) @[Cat.scala 29:58]
|
|
node _T_3695 = cat(_T_3694, _T_3693) @[Cat.scala 29:58]
|
|
node _T_3696 = cat(_T_3695, _T_3692) @[Cat.scala 29:58]
|
|
node _T_3697 = neq(_T_3696, UInt<1>("h00")) @[el2_lib.scala 312:44]
|
|
node _T_3698 = and(_T_3485, _T_3697) @[el2_lib.scala 312:32]
|
|
node _T_3699 = bits(_T_3696, 6, 6) @[el2_lib.scala 312:64]
|
|
node _T_3700 = and(_T_3698, _T_3699) @[el2_lib.scala 312:53]
|
|
node _T_3701 = neq(_T_3696, UInt<1>("h00")) @[el2_lib.scala 313:44]
|
|
node _T_3702 = and(_T_3485, _T_3701) @[el2_lib.scala 313:32]
|
|
node _T_3703 = bits(_T_3696, 6, 6) @[el2_lib.scala 313:65]
|
|
node _T_3704 = not(_T_3703) @[el2_lib.scala 313:55]
|
|
node _T_3705 = and(_T_3702, _T_3704) @[el2_lib.scala 313:53]
|
|
wire _T_3706 : UInt<1>[39] @[el2_lib.scala 314:26]
|
|
node _T_3707 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3708 = eq(_T_3707, UInt<1>("h01")) @[el2_lib.scala 317:41]
|
|
_T_3706[0] <= _T_3708 @[el2_lib.scala 317:23]
|
|
node _T_3709 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3710 = eq(_T_3709, UInt<2>("h02")) @[el2_lib.scala 317:41]
|
|
_T_3706[1] <= _T_3710 @[el2_lib.scala 317:23]
|
|
node _T_3711 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3712 = eq(_T_3711, UInt<2>("h03")) @[el2_lib.scala 317:41]
|
|
_T_3706[2] <= _T_3712 @[el2_lib.scala 317:23]
|
|
node _T_3713 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3714 = eq(_T_3713, UInt<3>("h04")) @[el2_lib.scala 317:41]
|
|
_T_3706[3] <= _T_3714 @[el2_lib.scala 317:23]
|
|
node _T_3715 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3716 = eq(_T_3715, UInt<3>("h05")) @[el2_lib.scala 317:41]
|
|
_T_3706[4] <= _T_3716 @[el2_lib.scala 317:23]
|
|
node _T_3717 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3718 = eq(_T_3717, UInt<3>("h06")) @[el2_lib.scala 317:41]
|
|
_T_3706[5] <= _T_3718 @[el2_lib.scala 317:23]
|
|
node _T_3719 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3720 = eq(_T_3719, UInt<3>("h07")) @[el2_lib.scala 317:41]
|
|
_T_3706[6] <= _T_3720 @[el2_lib.scala 317:23]
|
|
node _T_3721 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3722 = eq(_T_3721, UInt<4>("h08")) @[el2_lib.scala 317:41]
|
|
_T_3706[7] <= _T_3722 @[el2_lib.scala 317:23]
|
|
node _T_3723 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3724 = eq(_T_3723, UInt<4>("h09")) @[el2_lib.scala 317:41]
|
|
_T_3706[8] <= _T_3724 @[el2_lib.scala 317:23]
|
|
node _T_3725 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3726 = eq(_T_3725, UInt<4>("h0a")) @[el2_lib.scala 317:41]
|
|
_T_3706[9] <= _T_3726 @[el2_lib.scala 317:23]
|
|
node _T_3727 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3728 = eq(_T_3727, UInt<4>("h0b")) @[el2_lib.scala 317:41]
|
|
_T_3706[10] <= _T_3728 @[el2_lib.scala 317:23]
|
|
node _T_3729 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3730 = eq(_T_3729, UInt<4>("h0c")) @[el2_lib.scala 317:41]
|
|
_T_3706[11] <= _T_3730 @[el2_lib.scala 317:23]
|
|
node _T_3731 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3732 = eq(_T_3731, UInt<4>("h0d")) @[el2_lib.scala 317:41]
|
|
_T_3706[12] <= _T_3732 @[el2_lib.scala 317:23]
|
|
node _T_3733 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3734 = eq(_T_3733, UInt<4>("h0e")) @[el2_lib.scala 317:41]
|
|
_T_3706[13] <= _T_3734 @[el2_lib.scala 317:23]
|
|
node _T_3735 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3736 = eq(_T_3735, UInt<4>("h0f")) @[el2_lib.scala 317:41]
|
|
_T_3706[14] <= _T_3736 @[el2_lib.scala 317:23]
|
|
node _T_3737 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3738 = eq(_T_3737, UInt<5>("h010")) @[el2_lib.scala 317:41]
|
|
_T_3706[15] <= _T_3738 @[el2_lib.scala 317:23]
|
|
node _T_3739 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3740 = eq(_T_3739, UInt<5>("h011")) @[el2_lib.scala 317:41]
|
|
_T_3706[16] <= _T_3740 @[el2_lib.scala 317:23]
|
|
node _T_3741 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3742 = eq(_T_3741, UInt<5>("h012")) @[el2_lib.scala 317:41]
|
|
_T_3706[17] <= _T_3742 @[el2_lib.scala 317:23]
|
|
node _T_3743 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3744 = eq(_T_3743, UInt<5>("h013")) @[el2_lib.scala 317:41]
|
|
_T_3706[18] <= _T_3744 @[el2_lib.scala 317:23]
|
|
node _T_3745 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3746 = eq(_T_3745, UInt<5>("h014")) @[el2_lib.scala 317:41]
|
|
_T_3706[19] <= _T_3746 @[el2_lib.scala 317:23]
|
|
node _T_3747 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3748 = eq(_T_3747, UInt<5>("h015")) @[el2_lib.scala 317:41]
|
|
_T_3706[20] <= _T_3748 @[el2_lib.scala 317:23]
|
|
node _T_3749 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3750 = eq(_T_3749, UInt<5>("h016")) @[el2_lib.scala 317:41]
|
|
_T_3706[21] <= _T_3750 @[el2_lib.scala 317:23]
|
|
node _T_3751 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3752 = eq(_T_3751, UInt<5>("h017")) @[el2_lib.scala 317:41]
|
|
_T_3706[22] <= _T_3752 @[el2_lib.scala 317:23]
|
|
node _T_3753 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3754 = eq(_T_3753, UInt<5>("h018")) @[el2_lib.scala 317:41]
|
|
_T_3706[23] <= _T_3754 @[el2_lib.scala 317:23]
|
|
node _T_3755 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3756 = eq(_T_3755, UInt<5>("h019")) @[el2_lib.scala 317:41]
|
|
_T_3706[24] <= _T_3756 @[el2_lib.scala 317:23]
|
|
node _T_3757 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3758 = eq(_T_3757, UInt<5>("h01a")) @[el2_lib.scala 317:41]
|
|
_T_3706[25] <= _T_3758 @[el2_lib.scala 317:23]
|
|
node _T_3759 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3760 = eq(_T_3759, UInt<5>("h01b")) @[el2_lib.scala 317:41]
|
|
_T_3706[26] <= _T_3760 @[el2_lib.scala 317:23]
|
|
node _T_3761 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3762 = eq(_T_3761, UInt<5>("h01c")) @[el2_lib.scala 317:41]
|
|
_T_3706[27] <= _T_3762 @[el2_lib.scala 317:23]
|
|
node _T_3763 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3764 = eq(_T_3763, UInt<5>("h01d")) @[el2_lib.scala 317:41]
|
|
_T_3706[28] <= _T_3764 @[el2_lib.scala 317:23]
|
|
node _T_3765 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3766 = eq(_T_3765, UInt<5>("h01e")) @[el2_lib.scala 317:41]
|
|
_T_3706[29] <= _T_3766 @[el2_lib.scala 317:23]
|
|
node _T_3767 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3768 = eq(_T_3767, UInt<5>("h01f")) @[el2_lib.scala 317:41]
|
|
_T_3706[30] <= _T_3768 @[el2_lib.scala 317:23]
|
|
node _T_3769 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3770 = eq(_T_3769, UInt<6>("h020")) @[el2_lib.scala 317:41]
|
|
_T_3706[31] <= _T_3770 @[el2_lib.scala 317:23]
|
|
node _T_3771 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3772 = eq(_T_3771, UInt<6>("h021")) @[el2_lib.scala 317:41]
|
|
_T_3706[32] <= _T_3772 @[el2_lib.scala 317:23]
|
|
node _T_3773 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3774 = eq(_T_3773, UInt<6>("h022")) @[el2_lib.scala 317:41]
|
|
_T_3706[33] <= _T_3774 @[el2_lib.scala 317:23]
|
|
node _T_3775 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3776 = eq(_T_3775, UInt<6>("h023")) @[el2_lib.scala 317:41]
|
|
_T_3706[34] <= _T_3776 @[el2_lib.scala 317:23]
|
|
node _T_3777 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3778 = eq(_T_3777, UInt<6>("h024")) @[el2_lib.scala 317:41]
|
|
_T_3706[35] <= _T_3778 @[el2_lib.scala 317:23]
|
|
node _T_3779 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3780 = eq(_T_3779, UInt<6>("h025")) @[el2_lib.scala 317:41]
|
|
_T_3706[36] <= _T_3780 @[el2_lib.scala 317:23]
|
|
node _T_3781 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3782 = eq(_T_3781, UInt<6>("h026")) @[el2_lib.scala 317:41]
|
|
_T_3706[37] <= _T_3782 @[el2_lib.scala 317:23]
|
|
node _T_3783 = bits(_T_3696, 5, 0) @[el2_lib.scala 317:35]
|
|
node _T_3784 = eq(_T_3783, UInt<6>("h027")) @[el2_lib.scala 317:41]
|
|
_T_3706[38] <= _T_3784 @[el2_lib.scala 317:23]
|
|
node _T_3785 = bits(_T_3487, 6, 6) @[el2_lib.scala 319:37]
|
|
node _T_3786 = bits(_T_3486, 31, 26) @[el2_lib.scala 319:45]
|
|
node _T_3787 = bits(_T_3487, 5, 5) @[el2_lib.scala 319:60]
|
|
node _T_3788 = bits(_T_3486, 25, 11) @[el2_lib.scala 319:68]
|
|
node _T_3789 = bits(_T_3487, 4, 4) @[el2_lib.scala 319:83]
|
|
node _T_3790 = bits(_T_3486, 10, 4) @[el2_lib.scala 319:91]
|
|
node _T_3791 = bits(_T_3487, 3, 3) @[el2_lib.scala 319:105]
|
|
node _T_3792 = bits(_T_3486, 3, 1) @[el2_lib.scala 319:113]
|
|
node _T_3793 = bits(_T_3487, 2, 2) @[el2_lib.scala 319:126]
|
|
node _T_3794 = bits(_T_3486, 0, 0) @[el2_lib.scala 319:134]
|
|
node _T_3795 = bits(_T_3487, 1, 0) @[el2_lib.scala 319:145]
|
|
node _T_3796 = cat(_T_3794, _T_3795) @[Cat.scala 29:58]
|
|
node _T_3797 = cat(_T_3791, _T_3792) @[Cat.scala 29:58]
|
|
node _T_3798 = cat(_T_3797, _T_3793) @[Cat.scala 29:58]
|
|
node _T_3799 = cat(_T_3798, _T_3796) @[Cat.scala 29:58]
|
|
node _T_3800 = cat(_T_3788, _T_3789) @[Cat.scala 29:58]
|
|
node _T_3801 = cat(_T_3800, _T_3790) @[Cat.scala 29:58]
|
|
node _T_3802 = cat(_T_3785, _T_3786) @[Cat.scala 29:58]
|
|
node _T_3803 = cat(_T_3802, _T_3787) @[Cat.scala 29:58]
|
|
node _T_3804 = cat(_T_3803, _T_3801) @[Cat.scala 29:58]
|
|
node _T_3805 = cat(_T_3804, _T_3799) @[Cat.scala 29:58]
|
|
node _T_3806 = bits(_T_3700, 0, 0) @[el2_lib.scala 320:49]
|
|
node _T_3807 = cat(_T_3706[1], _T_3706[0]) @[el2_lib.scala 320:69]
|
|
node _T_3808 = cat(_T_3706[3], _T_3706[2]) @[el2_lib.scala 320:69]
|
|
node _T_3809 = cat(_T_3808, _T_3807) @[el2_lib.scala 320:69]
|
|
node _T_3810 = cat(_T_3706[5], _T_3706[4]) @[el2_lib.scala 320:69]
|
|
node _T_3811 = cat(_T_3706[8], _T_3706[7]) @[el2_lib.scala 320:69]
|
|
node _T_3812 = cat(_T_3811, _T_3706[6]) @[el2_lib.scala 320:69]
|
|
node _T_3813 = cat(_T_3812, _T_3810) @[el2_lib.scala 320:69]
|
|
node _T_3814 = cat(_T_3813, _T_3809) @[el2_lib.scala 320:69]
|
|
node _T_3815 = cat(_T_3706[10], _T_3706[9]) @[el2_lib.scala 320:69]
|
|
node _T_3816 = cat(_T_3706[13], _T_3706[12]) @[el2_lib.scala 320:69]
|
|
node _T_3817 = cat(_T_3816, _T_3706[11]) @[el2_lib.scala 320:69]
|
|
node _T_3818 = cat(_T_3817, _T_3815) @[el2_lib.scala 320:69]
|
|
node _T_3819 = cat(_T_3706[15], _T_3706[14]) @[el2_lib.scala 320:69]
|
|
node _T_3820 = cat(_T_3706[18], _T_3706[17]) @[el2_lib.scala 320:69]
|
|
node _T_3821 = cat(_T_3820, _T_3706[16]) @[el2_lib.scala 320:69]
|
|
node _T_3822 = cat(_T_3821, _T_3819) @[el2_lib.scala 320:69]
|
|
node _T_3823 = cat(_T_3822, _T_3818) @[el2_lib.scala 320:69]
|
|
node _T_3824 = cat(_T_3823, _T_3814) @[el2_lib.scala 320:69]
|
|
node _T_3825 = cat(_T_3706[20], _T_3706[19]) @[el2_lib.scala 320:69]
|
|
node _T_3826 = cat(_T_3706[23], _T_3706[22]) @[el2_lib.scala 320:69]
|
|
node _T_3827 = cat(_T_3826, _T_3706[21]) @[el2_lib.scala 320:69]
|
|
node _T_3828 = cat(_T_3827, _T_3825) @[el2_lib.scala 320:69]
|
|
node _T_3829 = cat(_T_3706[25], _T_3706[24]) @[el2_lib.scala 320:69]
|
|
node _T_3830 = cat(_T_3706[28], _T_3706[27]) @[el2_lib.scala 320:69]
|
|
node _T_3831 = cat(_T_3830, _T_3706[26]) @[el2_lib.scala 320:69]
|
|
node _T_3832 = cat(_T_3831, _T_3829) @[el2_lib.scala 320:69]
|
|
node _T_3833 = cat(_T_3832, _T_3828) @[el2_lib.scala 320:69]
|
|
node _T_3834 = cat(_T_3706[30], _T_3706[29]) @[el2_lib.scala 320:69]
|
|
node _T_3835 = cat(_T_3706[33], _T_3706[32]) @[el2_lib.scala 320:69]
|
|
node _T_3836 = cat(_T_3835, _T_3706[31]) @[el2_lib.scala 320:69]
|
|
node _T_3837 = cat(_T_3836, _T_3834) @[el2_lib.scala 320:69]
|
|
node _T_3838 = cat(_T_3706[35], _T_3706[34]) @[el2_lib.scala 320:69]
|
|
node _T_3839 = cat(_T_3706[38], _T_3706[37]) @[el2_lib.scala 320:69]
|
|
node _T_3840 = cat(_T_3839, _T_3706[36]) @[el2_lib.scala 320:69]
|
|
node _T_3841 = cat(_T_3840, _T_3838) @[el2_lib.scala 320:69]
|
|
node _T_3842 = cat(_T_3841, _T_3837) @[el2_lib.scala 320:69]
|
|
node _T_3843 = cat(_T_3842, _T_3833) @[el2_lib.scala 320:69]
|
|
node _T_3844 = cat(_T_3843, _T_3824) @[el2_lib.scala 320:69]
|
|
node _T_3845 = xor(_T_3844, _T_3805) @[el2_lib.scala 320:76]
|
|
node _T_3846 = mux(_T_3806, _T_3845, _T_3805) @[el2_lib.scala 320:31]
|
|
node _T_3847 = bits(_T_3846, 37, 32) @[el2_lib.scala 322:37]
|
|
node _T_3848 = bits(_T_3846, 30, 16) @[el2_lib.scala 322:61]
|
|
node _T_3849 = bits(_T_3846, 14, 8) @[el2_lib.scala 322:86]
|
|
node _T_3850 = bits(_T_3846, 6, 4) @[el2_lib.scala 322:110]
|
|
node _T_3851 = bits(_T_3846, 2, 2) @[el2_lib.scala 322:133]
|
|
node _T_3852 = cat(_T_3850, _T_3851) @[Cat.scala 29:58]
|
|
node _T_3853 = cat(_T_3847, _T_3848) @[Cat.scala 29:58]
|
|
node _T_3854 = cat(_T_3853, _T_3849) @[Cat.scala 29:58]
|
|
node _T_3855 = cat(_T_3854, _T_3852) @[Cat.scala 29:58]
|
|
node _T_3856 = bits(_T_3846, 38, 38) @[el2_lib.scala 323:39]
|
|
node _T_3857 = bits(_T_3696, 6, 0) @[el2_lib.scala 323:56]
|
|
node _T_3858 = eq(_T_3857, UInt<7>("h040")) @[el2_lib.scala 323:62]
|
|
node _T_3859 = xor(_T_3856, _T_3858) @[el2_lib.scala 323:44]
|
|
node _T_3860 = bits(_T_3846, 31, 31) @[el2_lib.scala 323:102]
|
|
node _T_3861 = bits(_T_3846, 15, 15) @[el2_lib.scala 323:124]
|
|
node _T_3862 = bits(_T_3846, 7, 7) @[el2_lib.scala 323:146]
|
|
node _T_3863 = bits(_T_3846, 3, 3) @[el2_lib.scala 323:167]
|
|
node _T_3864 = bits(_T_3846, 1, 0) @[el2_lib.scala 323:188]
|
|
node _T_3865 = cat(_T_3862, _T_3863) @[Cat.scala 29:58]
|
|
node _T_3866 = cat(_T_3865, _T_3864) @[Cat.scala 29:58]
|
|
node _T_3867 = cat(_T_3859, _T_3860) @[Cat.scala 29:58]
|
|
node _T_3868 = cat(_T_3867, _T_3861) @[Cat.scala 29:58]
|
|
node _T_3869 = cat(_T_3868, _T_3866) @[Cat.scala 29:58]
|
|
wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 671:32]
|
|
wire _T_3870 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 672:32]
|
|
_T_3870[0] <= _T_3484 @[el2_ifu_mem_ctl.scala 672:32]
|
|
_T_3870[1] <= _T_3869 @[el2_ifu_mem_ctl.scala 672:32]
|
|
iccm_corrected_ecc[0] <= _T_3870[0] @[el2_ifu_mem_ctl.scala 672:22]
|
|
iccm_corrected_ecc[1] <= _T_3870[1] @[el2_ifu_mem_ctl.scala 672:22]
|
|
wire _T_3871 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 673:33]
|
|
_T_3871[0] <= _T_3470 @[el2_ifu_mem_ctl.scala 673:33]
|
|
_T_3871[1] <= _T_3855 @[el2_ifu_mem_ctl.scala 673:33]
|
|
iccm_corrected_data[0] <= _T_3871[0] @[el2_ifu_mem_ctl.scala 673:23]
|
|
iccm_corrected_data[1] <= _T_3871[1] @[el2_ifu_mem_ctl.scala 673:23]
|
|
node _T_3872 = cat(_T_3315, _T_3700) @[Cat.scala 29:58]
|
|
iccm_single_ecc_error <= _T_3872 @[el2_ifu_mem_ctl.scala 674:25]
|
|
node _T_3873 = cat(_T_3320, _T_3705) @[Cat.scala 29:58]
|
|
iccm_double_ecc_error <= _T_3873 @[el2_ifu_mem_ctl.scala 675:25]
|
|
node _T_3874 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 676:54]
|
|
node _T_3875 = and(_T_3874, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 676:58]
|
|
node _T_3876 = and(_T_3875, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 676:78]
|
|
io.iccm_rd_ecc_single_err <= _T_3876 @[el2_ifu_mem_ctl.scala 676:29]
|
|
node _T_3877 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 677:54]
|
|
node _T_3878 = and(_T_3877, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 677:58]
|
|
io.iccm_rd_ecc_double_err <= _T_3878 @[el2_ifu_mem_ctl.scala 677:29]
|
|
node _T_3879 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 678:60]
|
|
node _T_3880 = bits(_T_3879, 0, 0) @[el2_ifu_mem_ctl.scala 678:64]
|
|
node iccm_corrected_data_f_mux = mux(_T_3880, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 678:38]
|
|
node _T_3881 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 679:59]
|
|
node _T_3882 = bits(_T_3881, 0, 0) @[el2_ifu_mem_ctl.scala 679:63]
|
|
node iccm_corrected_ecc_f_mux = mux(_T_3882, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 679:37]
|
|
wire iccm_rd_ecc_single_err_ff : UInt<1>
|
|
iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
|
|
node _T_3883 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:76]
|
|
node _T_3884 = and(io.iccm_rd_ecc_single_err, _T_3883) @[el2_ifu_mem_ctl.scala 681:74]
|
|
node _T_3885 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:106]
|
|
node _T_3886 = and(_T_3884, _T_3885) @[el2_ifu_mem_ctl.scala 681:104]
|
|
node iccm_ecc_write_status = or(_T_3886, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 681:127]
|
|
node _T_3887 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 682:67]
|
|
node _T_3888 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:98]
|
|
node iccm_rd_ecc_single_err_hold_in = and(_T_3887, _T_3888) @[el2_ifu_mem_ctl.scala 682:96]
|
|
iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 683:20]
|
|
wire iccm_rw_addr_f : UInt<14>
|
|
iccm_rw_addr_f <= UInt<1>("h00")
|
|
node _T_3889 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 685:57]
|
|
node _T_3890 = bits(_T_3889, 0, 0) @[el2_ifu_mem_ctl.scala 685:67]
|
|
node _T_3891 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 685:102]
|
|
node _T_3892 = tail(_T_3891, 1) @[el2_ifu_mem_ctl.scala 685:102]
|
|
node iccm_ecc_corr_index_in = mux(_T_3890, iccm_rw_addr_f, _T_3892) @[el2_ifu_mem_ctl.scala 685:35]
|
|
node _T_3893 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 686:67]
|
|
reg _T_3894 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 686:51]
|
|
_T_3894 <= _T_3893 @[el2_ifu_mem_ctl.scala 686:51]
|
|
iccm_rw_addr_f <= _T_3894 @[el2_ifu_mem_ctl.scala 686:18]
|
|
reg _T_3895 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 687:62]
|
|
_T_3895 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 687:62]
|
|
iccm_rd_ecc_single_err_ff <= _T_3895 @[el2_ifu_mem_ctl.scala 687:29]
|
|
node _T_3896 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
|
|
node _T_3897 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 688:152]
|
|
reg _T_3898 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3897 : @[Reg.scala 28:19]
|
|
_T_3898 <= _T_3896 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_data_ff <= _T_3898 @[el2_ifu_mem_ctl.scala 688:25]
|
|
node _T_3899 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 689:119]
|
|
reg _T_3900 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3899 : @[Reg.scala 28:19]
|
|
_T_3900 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_index_ff <= _T_3900 @[el2_ifu_mem_ctl.scala 689:26]
|
|
node _T_3901 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 690:41]
|
|
node _T_3902 = and(io.ifc_fetch_req_bf, _T_3901) @[el2_ifu_mem_ctl.scala 690:39]
|
|
node _T_3903 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 690:72]
|
|
node _T_3904 = and(_T_3902, _T_3903) @[el2_ifu_mem_ctl.scala 690:70]
|
|
node _T_3905 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 691:19]
|
|
node _T_3906 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:34]
|
|
node _T_3907 = and(_T_3905, _T_3906) @[el2_ifu_mem_ctl.scala 691:32]
|
|
node _T_3908 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 692:19]
|
|
node _T_3909 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:39]
|
|
node _T_3910 = and(_T_3908, _T_3909) @[el2_ifu_mem_ctl.scala 692:37]
|
|
node _T_3911 = or(_T_3907, _T_3910) @[el2_ifu_mem_ctl.scala 691:88]
|
|
node _T_3912 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 693:19]
|
|
node _T_3913 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 693:43]
|
|
node _T_3914 = and(_T_3912, _T_3913) @[el2_ifu_mem_ctl.scala 693:41]
|
|
node _T_3915 = or(_T_3911, _T_3914) @[el2_ifu_mem_ctl.scala 692:88]
|
|
node _T_3916 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 694:19]
|
|
node _T_3917 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:37]
|
|
node _T_3918 = and(_T_3916, _T_3917) @[el2_ifu_mem_ctl.scala 694:35]
|
|
node _T_3919 = or(_T_3915, _T_3918) @[el2_ifu_mem_ctl.scala 693:88]
|
|
node _T_3920 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 695:19]
|
|
node _T_3921 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:40]
|
|
node _T_3922 = and(_T_3920, _T_3921) @[el2_ifu_mem_ctl.scala 695:38]
|
|
node _T_3923 = or(_T_3919, _T_3922) @[el2_ifu_mem_ctl.scala 694:88]
|
|
node _T_3924 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 696:19]
|
|
node _T_3925 = and(_T_3924, miss_state_en) @[el2_ifu_mem_ctl.scala 696:37]
|
|
node _T_3926 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 696:71]
|
|
node _T_3927 = and(_T_3925, _T_3926) @[el2_ifu_mem_ctl.scala 696:54]
|
|
node _T_3928 = or(_T_3923, _T_3927) @[el2_ifu_mem_ctl.scala 695:57]
|
|
node _T_3929 = eq(_T_3928, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:5]
|
|
node _T_3930 = and(_T_3904, _T_3929) @[el2_ifu_mem_ctl.scala 690:96]
|
|
node _T_3931 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 697:28]
|
|
node _T_3932 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 697:52]
|
|
node _T_3933 = and(_T_3931, _T_3932) @[el2_ifu_mem_ctl.scala 697:50]
|
|
node _T_3934 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 697:83]
|
|
node _T_3935 = and(_T_3933, _T_3934) @[el2_ifu_mem_ctl.scala 697:81]
|
|
node _T_3936 = or(_T_3930, _T_3935) @[el2_ifu_mem_ctl.scala 696:93]
|
|
io.ic_rd_en <= _T_3936 @[el2_ifu_mem_ctl.scala 690:15]
|
|
wire bus_ic_wr_en : UInt<2>
|
|
bus_ic_wr_en <= UInt<1>("h00")
|
|
node _T_3937 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_3938 = mux(_T_3937, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_3939 = and(bus_ic_wr_en, _T_3938) @[el2_ifu_mem_ctl.scala 699:31]
|
|
io.ic_wr_en <= _T_3939 @[el2_ifu_mem_ctl.scala 699:15]
|
|
node _T_3940 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 700:59]
|
|
node _T_3941 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 700:91]
|
|
node _T_3942 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 700:127]
|
|
node _T_3943 = or(_T_3942, stream_eol_f) @[el2_ifu_mem_ctl.scala 700:151]
|
|
node _T_3944 = eq(_T_3943, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:106]
|
|
node _T_3945 = and(_T_3941, _T_3944) @[el2_ifu_mem_ctl.scala 700:104]
|
|
node _T_3946 = or(_T_3940, _T_3945) @[el2_ifu_mem_ctl.scala 700:77]
|
|
node _T_3947 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 700:191]
|
|
node _T_3948 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:205]
|
|
node _T_3949 = and(_T_3947, _T_3948) @[el2_ifu_mem_ctl.scala 700:203]
|
|
node _T_3950 = eq(_T_3949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:172]
|
|
node _T_3951 = and(_T_3946, _T_3950) @[el2_ifu_mem_ctl.scala 700:170]
|
|
node _T_3952 = eq(_T_3951, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:44]
|
|
node _T_3953 = and(write_ic_16_bytes, _T_3952) @[el2_ifu_mem_ctl.scala 700:42]
|
|
io.ic_write_stall <= _T_3953 @[el2_ifu_mem_ctl.scala 700:21]
|
|
reg _T_3954 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 701:53]
|
|
_T_3954 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 701:53]
|
|
reset_all_tags <= _T_3954 @[el2_ifu_mem_ctl.scala 701:18]
|
|
node _T_3955 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:20]
|
|
node _T_3956 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 703:64]
|
|
node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:50]
|
|
node _T_3958 = and(_T_3955, _T_3957) @[el2_ifu_mem_ctl.scala 703:48]
|
|
node _T_3959 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:81]
|
|
node ic_valid = and(_T_3958, _T_3959) @[el2_ifu_mem_ctl.scala 703:79]
|
|
node _T_3960 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 704:61]
|
|
node _T_3961 = and(_T_3960, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 704:82]
|
|
node _T_3962 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 704:123]
|
|
node _T_3963 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 705:25]
|
|
node ifu_status_wr_addr_w_debug = mux(_T_3961, _T_3962, _T_3963) @[el2_ifu_mem_ctl.scala 704:41]
|
|
reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 707:14]
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 707:14]
|
|
wire way_status_wr_en : UInt<1>
|
|
way_status_wr_en <= UInt<1>("h00")
|
|
node _T_3964 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 710:74]
|
|
node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3964) @[el2_ifu_mem_ctl.scala 710:53]
|
|
reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 712:14]
|
|
way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 712:14]
|
|
wire way_status_new : UInt<1>
|
|
way_status_new <= UInt<1>("h00")
|
|
node _T_3965 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 715:56]
|
|
node _T_3966 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 716:55]
|
|
node way_status_new_w_debug = mux(_T_3965, _T_3966, way_status_new) @[el2_ifu_mem_ctl.scala 715:37]
|
|
reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 718:14]
|
|
way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 718:14]
|
|
node _T_3967 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_0 = eq(_T_3967, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3968 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_1 = eq(_T_3968, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3969 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_2 = eq(_T_3969, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3970 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_3 = eq(_T_3970, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3971 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_4 = eq(_T_3971, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3972 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_5 = eq(_T_3972, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3973 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_6 = eq(_T_3973, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3974 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_7 = eq(_T_3974, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3975 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_8 = eq(_T_3975, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3976 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_9 = eq(_T_3976, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3977 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_10 = eq(_T_3977, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3978 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_11 = eq(_T_3978, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3979 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_12 = eq(_T_3979, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3980 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_13 = eq(_T_3980, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3981 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_14 = eq(_T_3981, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
node _T_3982 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 720:89]
|
|
node way_status_clken_15 = eq(_T_3982, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 720:132]
|
|
wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 722:30]
|
|
node _T_3983 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_3984 = eq(_T_3983, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_3985 = and(_T_3984, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_3986 = and(_T_3985, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_3987 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3986 : @[Reg.scala 28:19]
|
|
_T_3987 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[0] <= _T_3987 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_3988 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_3989 = eq(_T_3988, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_3990 = and(_T_3989, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_3991 = and(_T_3990, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_3992 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3991 : @[Reg.scala 28:19]
|
|
_T_3992 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[1] <= _T_3992 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_3993 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_3994 = eq(_T_3993, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_3995 = and(_T_3994, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_3996 = and(_T_3995, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_3997 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3996 : @[Reg.scala 28:19]
|
|
_T_3997 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[2] <= _T_3997 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_3998 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_3999 = eq(_T_3998, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4000 = and(_T_3999, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4001 = and(_T_4000, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4002 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4001 : @[Reg.scala 28:19]
|
|
_T_4002 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[3] <= _T_4002 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4003 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4004 = eq(_T_4003, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4005 = and(_T_4004, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4006 = and(_T_4005, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4007 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4006 : @[Reg.scala 28:19]
|
|
_T_4007 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[4] <= _T_4007 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4008 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4009 = eq(_T_4008, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4010 = and(_T_4009, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4011 = and(_T_4010, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4011 : @[Reg.scala 28:19]
|
|
_T_4012 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[5] <= _T_4012 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4013 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4014 = eq(_T_4013, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4015 = and(_T_4014, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4016 = and(_T_4015, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4017 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4016 : @[Reg.scala 28:19]
|
|
_T_4017 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[6] <= _T_4017 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4018 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4019 = eq(_T_4018, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4020 = and(_T_4019, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4021 = and(_T_4020, way_status_clken_0) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4022 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4021 : @[Reg.scala 28:19]
|
|
_T_4022 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[7] <= _T_4022 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4023 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4024 = eq(_T_4023, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4026 = and(_T_4025, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4027 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4026 : @[Reg.scala 28:19]
|
|
_T_4027 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[8] <= _T_4027 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4028 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4029 = eq(_T_4028, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4030 = and(_T_4029, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4031 = and(_T_4030, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4032 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4031 : @[Reg.scala 28:19]
|
|
_T_4032 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[9] <= _T_4032 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4033 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4034 = eq(_T_4033, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4035 = and(_T_4034, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4036 = and(_T_4035, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4037 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4036 : @[Reg.scala 28:19]
|
|
_T_4037 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[10] <= _T_4037 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4038 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4039 = eq(_T_4038, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4040 = and(_T_4039, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4041 = and(_T_4040, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4042 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4041 : @[Reg.scala 28:19]
|
|
_T_4042 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[11] <= _T_4042 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4043 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4044 = eq(_T_4043, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4046 = and(_T_4045, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4047 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4046 : @[Reg.scala 28:19]
|
|
_T_4047 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[12] <= _T_4047 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4048 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4049 = eq(_T_4048, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4050 = and(_T_4049, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4051 = and(_T_4050, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4052 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4051 : @[Reg.scala 28:19]
|
|
_T_4052 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[13] <= _T_4052 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4053 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4054 = eq(_T_4053, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4055 = and(_T_4054, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4056 = and(_T_4055, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4057 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4056 : @[Reg.scala 28:19]
|
|
_T_4057 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[14] <= _T_4057 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4058 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4059 = eq(_T_4058, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4060 = and(_T_4059, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4061 = and(_T_4060, way_status_clken_1) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4062 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4061 : @[Reg.scala 28:19]
|
|
_T_4062 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[15] <= _T_4062 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4063 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4064 = eq(_T_4063, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4065 = and(_T_4064, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4066 = and(_T_4065, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4067 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4066 : @[Reg.scala 28:19]
|
|
_T_4067 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[16] <= _T_4067 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4068 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4069 = eq(_T_4068, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4070 = and(_T_4069, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4071 = and(_T_4070, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4072 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4071 : @[Reg.scala 28:19]
|
|
_T_4072 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[17] <= _T_4072 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4073 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4074 = eq(_T_4073, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4075 = and(_T_4074, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4076 = and(_T_4075, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4077 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4076 : @[Reg.scala 28:19]
|
|
_T_4077 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[18] <= _T_4077 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4078 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4079 = eq(_T_4078, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4080 = and(_T_4079, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4081 = and(_T_4080, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4082 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4081 : @[Reg.scala 28:19]
|
|
_T_4082 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[19] <= _T_4082 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4083 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4084 = eq(_T_4083, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4086 = and(_T_4085, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4087 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4086 : @[Reg.scala 28:19]
|
|
_T_4087 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[20] <= _T_4087 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4088 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4089 = eq(_T_4088, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4090 = and(_T_4089, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4091 = and(_T_4090, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4092 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4091 : @[Reg.scala 28:19]
|
|
_T_4092 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[21] <= _T_4092 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4093 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4094 = eq(_T_4093, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4095 = and(_T_4094, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4096 = and(_T_4095, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4097 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4096 : @[Reg.scala 28:19]
|
|
_T_4097 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[22] <= _T_4097 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4098 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4099 = eq(_T_4098, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4100 = and(_T_4099, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4101 = and(_T_4100, way_status_clken_2) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4102 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4101 : @[Reg.scala 28:19]
|
|
_T_4102 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[23] <= _T_4102 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4103 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4104 = eq(_T_4103, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4106 = and(_T_4105, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4107 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4106 : @[Reg.scala 28:19]
|
|
_T_4107 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[24] <= _T_4107 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4108 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4109 = eq(_T_4108, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4110 = and(_T_4109, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4111 = and(_T_4110, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4111 : @[Reg.scala 28:19]
|
|
_T_4112 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[25] <= _T_4112 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4113 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4114 = eq(_T_4113, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4115 = and(_T_4114, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4116 = and(_T_4115, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4117 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4116 : @[Reg.scala 28:19]
|
|
_T_4117 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[26] <= _T_4117 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4118 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4119 = eq(_T_4118, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4120 = and(_T_4119, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4121 = and(_T_4120, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4122 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4121 : @[Reg.scala 28:19]
|
|
_T_4122 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[27] <= _T_4122 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4123 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4124 = eq(_T_4123, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4125 = and(_T_4124, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4126 = and(_T_4125, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4127 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4126 : @[Reg.scala 28:19]
|
|
_T_4127 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[28] <= _T_4127 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4128 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4129 = eq(_T_4128, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4130 = and(_T_4129, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4131 = and(_T_4130, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4131 : @[Reg.scala 28:19]
|
|
_T_4132 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[29] <= _T_4132 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4133 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4134 = eq(_T_4133, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4135 = and(_T_4134, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4136 = and(_T_4135, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4136 : @[Reg.scala 28:19]
|
|
_T_4137 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[30] <= _T_4137 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4138 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4139 = eq(_T_4138, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4140 = and(_T_4139, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4141 = and(_T_4140, way_status_clken_3) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4142 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4141 : @[Reg.scala 28:19]
|
|
_T_4142 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[31] <= _T_4142 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4143 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4144 = eq(_T_4143, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4146 = and(_T_4145, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4147 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4146 : @[Reg.scala 28:19]
|
|
_T_4147 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[32] <= _T_4147 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4148 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4149 = eq(_T_4148, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4150 = and(_T_4149, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4151 = and(_T_4150, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4152 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4151 : @[Reg.scala 28:19]
|
|
_T_4152 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[33] <= _T_4152 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4153 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4154 = eq(_T_4153, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4155 = and(_T_4154, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4156 = and(_T_4155, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4157 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4156 : @[Reg.scala 28:19]
|
|
_T_4157 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[34] <= _T_4157 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4158 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4159 = eq(_T_4158, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4160 = and(_T_4159, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4161 = and(_T_4160, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4161 : @[Reg.scala 28:19]
|
|
_T_4162 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[35] <= _T_4162 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4163 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4164 = eq(_T_4163, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4166 = and(_T_4165, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4166 : @[Reg.scala 28:19]
|
|
_T_4167 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[36] <= _T_4167 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4168 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4169 = eq(_T_4168, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4170 = and(_T_4169, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4171 = and(_T_4170, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4171 : @[Reg.scala 28:19]
|
|
_T_4172 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[37] <= _T_4172 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4173 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4174 = eq(_T_4173, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4175 = and(_T_4174, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4176 = and(_T_4175, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4176 : @[Reg.scala 28:19]
|
|
_T_4177 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[38] <= _T_4177 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4178 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4179 = eq(_T_4178, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4180 = and(_T_4179, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4181 = and(_T_4180, way_status_clken_4) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4181 : @[Reg.scala 28:19]
|
|
_T_4182 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[39] <= _T_4182 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4183 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4184 = eq(_T_4183, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4185 = and(_T_4184, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4186 = and(_T_4185, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4187 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4186 : @[Reg.scala 28:19]
|
|
_T_4187 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[40] <= _T_4187 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4188 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4189 = eq(_T_4188, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4190 = and(_T_4189, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4191 = and(_T_4190, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4192 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4191 : @[Reg.scala 28:19]
|
|
_T_4192 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[41] <= _T_4192 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4193 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4194 = eq(_T_4193, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4195 = and(_T_4194, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4196 = and(_T_4195, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4197 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4196 : @[Reg.scala 28:19]
|
|
_T_4197 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[42] <= _T_4197 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4198 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4199 = eq(_T_4198, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4200 = and(_T_4199, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4201 = and(_T_4200, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4201 : @[Reg.scala 28:19]
|
|
_T_4202 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[43] <= _T_4202 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4203 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4204 = eq(_T_4203, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4206 = and(_T_4205, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4207 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4206 : @[Reg.scala 28:19]
|
|
_T_4207 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[44] <= _T_4207 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4208 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4209 = eq(_T_4208, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4210 = and(_T_4209, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4211 = and(_T_4210, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4212 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4211 : @[Reg.scala 28:19]
|
|
_T_4212 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[45] <= _T_4212 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4213 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4214 = eq(_T_4213, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4215 = and(_T_4214, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4216 = and(_T_4215, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4217 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4216 : @[Reg.scala 28:19]
|
|
_T_4217 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[46] <= _T_4217 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4218 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4219 = eq(_T_4218, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4220 = and(_T_4219, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4221 = and(_T_4220, way_status_clken_5) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4222 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4221 : @[Reg.scala 28:19]
|
|
_T_4222 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[47] <= _T_4222 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4223 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4224 = eq(_T_4223, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4226 = and(_T_4225, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4227 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4226 : @[Reg.scala 28:19]
|
|
_T_4227 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[48] <= _T_4227 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4228 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4229 = eq(_T_4228, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4230 = and(_T_4229, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4231 = and(_T_4230, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4232 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4231 : @[Reg.scala 28:19]
|
|
_T_4232 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[49] <= _T_4232 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4233 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4234 = eq(_T_4233, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4235 = and(_T_4234, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4236 = and(_T_4235, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4237 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4236 : @[Reg.scala 28:19]
|
|
_T_4237 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[50] <= _T_4237 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4238 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4239 = eq(_T_4238, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4240 = and(_T_4239, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4241 = and(_T_4240, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4242 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4241 : @[Reg.scala 28:19]
|
|
_T_4242 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[51] <= _T_4242 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4243 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4244 = eq(_T_4243, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4245 = and(_T_4244, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4246 = and(_T_4245, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4247 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4246 : @[Reg.scala 28:19]
|
|
_T_4247 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[52] <= _T_4247 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4248 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4249 = eq(_T_4248, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4250 = and(_T_4249, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4251 = and(_T_4250, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4252 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4251 : @[Reg.scala 28:19]
|
|
_T_4252 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[53] <= _T_4252 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4253 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4254 = eq(_T_4253, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4255 = and(_T_4254, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4256 = and(_T_4255, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4257 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4256 : @[Reg.scala 28:19]
|
|
_T_4257 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[54] <= _T_4257 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4258 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4259 = eq(_T_4258, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4260 = and(_T_4259, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4261 = and(_T_4260, way_status_clken_6) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4262 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4261 : @[Reg.scala 28:19]
|
|
_T_4262 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[55] <= _T_4262 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4263 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4264 = eq(_T_4263, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4266 = and(_T_4265, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4267 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4266 : @[Reg.scala 28:19]
|
|
_T_4267 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[56] <= _T_4267 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4268 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4269 = eq(_T_4268, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4270 = and(_T_4269, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4271 = and(_T_4270, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4272 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4271 : @[Reg.scala 28:19]
|
|
_T_4272 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[57] <= _T_4272 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4273 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4274 = eq(_T_4273, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4275 = and(_T_4274, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4276 = and(_T_4275, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4277 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4276 : @[Reg.scala 28:19]
|
|
_T_4277 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[58] <= _T_4277 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4278 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4279 = eq(_T_4278, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4280 = and(_T_4279, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4281 = and(_T_4280, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4282 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4281 : @[Reg.scala 28:19]
|
|
_T_4282 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[59] <= _T_4282 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4283 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4284 = eq(_T_4283, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4286 = and(_T_4285, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4287 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4286 : @[Reg.scala 28:19]
|
|
_T_4287 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[60] <= _T_4287 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4288 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4289 = eq(_T_4288, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4290 = and(_T_4289, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4291 = and(_T_4290, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4291 : @[Reg.scala 28:19]
|
|
_T_4292 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[61] <= _T_4292 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4293 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4294 = eq(_T_4293, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4295 = and(_T_4294, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4296 = and(_T_4295, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4296 : @[Reg.scala 28:19]
|
|
_T_4297 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[62] <= _T_4297 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4298 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4299 = eq(_T_4298, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4300 = and(_T_4299, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4301 = and(_T_4300, way_status_clken_7) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4301 : @[Reg.scala 28:19]
|
|
_T_4302 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[63] <= _T_4302 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4303 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4304 = eq(_T_4303, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4305 = and(_T_4304, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4306 = and(_T_4305, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4307 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4306 : @[Reg.scala 28:19]
|
|
_T_4307 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[64] <= _T_4307 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4308 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4309 = eq(_T_4308, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4310 = and(_T_4309, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4311 = and(_T_4310, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4312 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4311 : @[Reg.scala 28:19]
|
|
_T_4312 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[65] <= _T_4312 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4313 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4314 = eq(_T_4313, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4315 = and(_T_4314, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4316 = and(_T_4315, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4317 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4316 : @[Reg.scala 28:19]
|
|
_T_4317 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[66] <= _T_4317 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4318 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4319 = eq(_T_4318, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4320 = and(_T_4319, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4321 = and(_T_4320, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4321 : @[Reg.scala 28:19]
|
|
_T_4322 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[67] <= _T_4322 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4323 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4324 = eq(_T_4323, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4326 = and(_T_4325, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4327 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4326 : @[Reg.scala 28:19]
|
|
_T_4327 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[68] <= _T_4327 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4328 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4329 = eq(_T_4328, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4330 = and(_T_4329, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4331 = and(_T_4330, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4331 : @[Reg.scala 28:19]
|
|
_T_4332 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[69] <= _T_4332 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4333 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4334 = eq(_T_4333, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4335 = and(_T_4334, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4336 = and(_T_4335, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4337 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4336 : @[Reg.scala 28:19]
|
|
_T_4337 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[70] <= _T_4337 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4338 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4339 = eq(_T_4338, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4340 = and(_T_4339, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4341 = and(_T_4340, way_status_clken_8) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4342 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4341 : @[Reg.scala 28:19]
|
|
_T_4342 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[71] <= _T_4342 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4343 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4344 = eq(_T_4343, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4345 = and(_T_4344, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4346 = and(_T_4345, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4347 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4346 : @[Reg.scala 28:19]
|
|
_T_4347 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[72] <= _T_4347 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4348 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4349 = eq(_T_4348, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4350 = and(_T_4349, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4351 = and(_T_4350, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4352 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4351 : @[Reg.scala 28:19]
|
|
_T_4352 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[73] <= _T_4352 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4353 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4354 = eq(_T_4353, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4355 = and(_T_4354, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4356 = and(_T_4355, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4357 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4356 : @[Reg.scala 28:19]
|
|
_T_4357 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[74] <= _T_4357 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4358 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4359 = eq(_T_4358, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4360 = and(_T_4359, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4361 = and(_T_4360, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4362 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4361 : @[Reg.scala 28:19]
|
|
_T_4362 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[75] <= _T_4362 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4363 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4364 = eq(_T_4363, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4365 = and(_T_4364, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4366 = and(_T_4365, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4367 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4366 : @[Reg.scala 28:19]
|
|
_T_4367 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[76] <= _T_4367 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4368 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4369 = eq(_T_4368, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4370 = and(_T_4369, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4371 = and(_T_4370, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4371 : @[Reg.scala 28:19]
|
|
_T_4372 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[77] <= _T_4372 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4373 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4374 = eq(_T_4373, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4375 = and(_T_4374, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4376 = and(_T_4375, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4377 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4376 : @[Reg.scala 28:19]
|
|
_T_4377 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[78] <= _T_4377 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4378 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4379 = eq(_T_4378, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4380 = and(_T_4379, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4381 = and(_T_4380, way_status_clken_9) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4382 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4381 : @[Reg.scala 28:19]
|
|
_T_4382 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[79] <= _T_4382 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4383 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4384 = eq(_T_4383, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4385 = and(_T_4384, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4386 = and(_T_4385, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4387 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4386 : @[Reg.scala 28:19]
|
|
_T_4387 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[80] <= _T_4387 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4388 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4389 = eq(_T_4388, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4390 = and(_T_4389, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4391 = and(_T_4390, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4392 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4391 : @[Reg.scala 28:19]
|
|
_T_4392 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[81] <= _T_4392 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4393 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4394 = eq(_T_4393, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4395 = and(_T_4394, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4396 = and(_T_4395, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4397 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4396 : @[Reg.scala 28:19]
|
|
_T_4397 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[82] <= _T_4397 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4398 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4399 = eq(_T_4398, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4400 = and(_T_4399, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4401 = and(_T_4400, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4402 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4401 : @[Reg.scala 28:19]
|
|
_T_4402 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[83] <= _T_4402 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4403 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4404 = eq(_T_4403, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4405 = and(_T_4404, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4406 = and(_T_4405, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4407 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4406 : @[Reg.scala 28:19]
|
|
_T_4407 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[84] <= _T_4407 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4408 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4409 = eq(_T_4408, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4410 = and(_T_4409, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4411 = and(_T_4410, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4412 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4411 : @[Reg.scala 28:19]
|
|
_T_4412 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[85] <= _T_4412 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4413 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4414 = eq(_T_4413, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4415 = and(_T_4414, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4416 = and(_T_4415, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4416 : @[Reg.scala 28:19]
|
|
_T_4417 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[86] <= _T_4417 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4418 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4419 = eq(_T_4418, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4420 = and(_T_4419, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4421 = and(_T_4420, way_status_clken_10) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4422 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4421 : @[Reg.scala 28:19]
|
|
_T_4422 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[87] <= _T_4422 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4423 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4424 = eq(_T_4423, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4425 = and(_T_4424, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4426 = and(_T_4425, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4427 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4426 : @[Reg.scala 28:19]
|
|
_T_4427 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[88] <= _T_4427 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4428 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4429 = eq(_T_4428, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4430 = and(_T_4429, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4431 = and(_T_4430, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4432 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4431 : @[Reg.scala 28:19]
|
|
_T_4432 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[89] <= _T_4432 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4433 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4434 = eq(_T_4433, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4435 = and(_T_4434, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4436 = and(_T_4435, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4437 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4436 : @[Reg.scala 28:19]
|
|
_T_4437 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[90] <= _T_4437 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4438 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4439 = eq(_T_4438, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4440 = and(_T_4439, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4441 = and(_T_4440, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4442 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4441 : @[Reg.scala 28:19]
|
|
_T_4442 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[91] <= _T_4442 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4443 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4444 = eq(_T_4443, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4445 = and(_T_4444, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4446 = and(_T_4445, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4447 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4446 : @[Reg.scala 28:19]
|
|
_T_4447 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[92] <= _T_4447 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4448 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4449 = eq(_T_4448, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4450 = and(_T_4449, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4451 = and(_T_4450, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4452 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4451 : @[Reg.scala 28:19]
|
|
_T_4452 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[93] <= _T_4452 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4453 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4454 = eq(_T_4453, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4455 = and(_T_4454, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4456 = and(_T_4455, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4457 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4456 : @[Reg.scala 28:19]
|
|
_T_4457 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[94] <= _T_4457 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4458 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4459 = eq(_T_4458, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4460 = and(_T_4459, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4461 = and(_T_4460, way_status_clken_11) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4462 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4461 : @[Reg.scala 28:19]
|
|
_T_4462 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[95] <= _T_4462 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4463 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4464 = eq(_T_4463, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4465 = and(_T_4464, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4466 = and(_T_4465, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4467 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4466 : @[Reg.scala 28:19]
|
|
_T_4467 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[96] <= _T_4467 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4468 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4469 = eq(_T_4468, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4470 = and(_T_4469, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4471 = and(_T_4470, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4472 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4471 : @[Reg.scala 28:19]
|
|
_T_4472 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[97] <= _T_4472 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4473 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4474 = eq(_T_4473, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4475 = and(_T_4474, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4476 = and(_T_4475, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4477 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4476 : @[Reg.scala 28:19]
|
|
_T_4477 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[98] <= _T_4477 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4478 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4479 = eq(_T_4478, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4480 = and(_T_4479, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4481 = and(_T_4480, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4482 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4481 : @[Reg.scala 28:19]
|
|
_T_4482 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[99] <= _T_4482 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4483 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4484 = eq(_T_4483, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4485 = and(_T_4484, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4486 = and(_T_4485, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4487 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4486 : @[Reg.scala 28:19]
|
|
_T_4487 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[100] <= _T_4487 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4488 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4489 = eq(_T_4488, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4490 = and(_T_4489, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4491 = and(_T_4490, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4492 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4491 : @[Reg.scala 28:19]
|
|
_T_4492 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[101] <= _T_4492 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4493 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4494 = eq(_T_4493, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4495 = and(_T_4494, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4496 = and(_T_4495, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4497 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4496 : @[Reg.scala 28:19]
|
|
_T_4497 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[102] <= _T_4497 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4498 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4499 = eq(_T_4498, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4500 = and(_T_4499, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4501 = and(_T_4500, way_status_clken_12) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4502 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4501 : @[Reg.scala 28:19]
|
|
_T_4502 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[103] <= _T_4502 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4503 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4505 = and(_T_4504, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4506 = and(_T_4505, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4507 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4506 : @[Reg.scala 28:19]
|
|
_T_4507 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[104] <= _T_4507 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4508 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4509 = eq(_T_4508, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4510 = and(_T_4509, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4511 = and(_T_4510, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4512 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4511 : @[Reg.scala 28:19]
|
|
_T_4512 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[105] <= _T_4512 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4513 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4514 = eq(_T_4513, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4515 = and(_T_4514, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4516 = and(_T_4515, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4517 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4516 : @[Reg.scala 28:19]
|
|
_T_4517 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[106] <= _T_4517 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4518 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4519 = eq(_T_4518, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4520 = and(_T_4519, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4521 = and(_T_4520, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4522 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4521 : @[Reg.scala 28:19]
|
|
_T_4522 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[107] <= _T_4522 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4523 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4524 = eq(_T_4523, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4525 = and(_T_4524, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4526 = and(_T_4525, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4527 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4526 : @[Reg.scala 28:19]
|
|
_T_4527 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[108] <= _T_4527 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4528 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4529 = eq(_T_4528, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4530 = and(_T_4529, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4531 = and(_T_4530, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4532 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4531 : @[Reg.scala 28:19]
|
|
_T_4532 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[109] <= _T_4532 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4533 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4534 = eq(_T_4533, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4535 = and(_T_4534, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4536 = and(_T_4535, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4537 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4536 : @[Reg.scala 28:19]
|
|
_T_4537 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[110] <= _T_4537 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4538 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4539 = eq(_T_4538, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4540 = and(_T_4539, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4541 = and(_T_4540, way_status_clken_13) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4542 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4541 : @[Reg.scala 28:19]
|
|
_T_4542 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[111] <= _T_4542 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4543 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4545 = and(_T_4544, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4546 = and(_T_4545, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4547 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4546 : @[Reg.scala 28:19]
|
|
_T_4547 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[112] <= _T_4547 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4548 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4549 = eq(_T_4548, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4550 = and(_T_4549, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4551 = and(_T_4550, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4552 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4551 : @[Reg.scala 28:19]
|
|
_T_4552 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[113] <= _T_4552 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4553 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4554 = eq(_T_4553, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4555 = and(_T_4554, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4556 = and(_T_4555, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4557 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4556 : @[Reg.scala 28:19]
|
|
_T_4557 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[114] <= _T_4557 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4558 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4559 = eq(_T_4558, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4560 = and(_T_4559, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4561 = and(_T_4560, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4562 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4561 : @[Reg.scala 28:19]
|
|
_T_4562 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[115] <= _T_4562 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4563 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4564 = eq(_T_4563, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4565 = and(_T_4564, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4566 = and(_T_4565, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4567 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4566 : @[Reg.scala 28:19]
|
|
_T_4567 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[116] <= _T_4567 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4568 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4569 = eq(_T_4568, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4570 = and(_T_4569, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4571 = and(_T_4570, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4572 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4571 : @[Reg.scala 28:19]
|
|
_T_4572 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[117] <= _T_4572 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4573 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4574 = eq(_T_4573, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4575 = and(_T_4574, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4576 = and(_T_4575, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4577 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4576 : @[Reg.scala 28:19]
|
|
_T_4577 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[118] <= _T_4577 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4578 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4579 = eq(_T_4578, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4580 = and(_T_4579, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4581 = and(_T_4580, way_status_clken_14) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4582 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4581 : @[Reg.scala 28:19]
|
|
_T_4582 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[119] <= _T_4582 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4583 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4584 = eq(_T_4583, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4585 = and(_T_4584, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4586 = and(_T_4585, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4587 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4586 : @[Reg.scala 28:19]
|
|
_T_4587 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[120] <= _T_4587 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4588 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4589 = eq(_T_4588, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4590 = and(_T_4589, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4591 = and(_T_4590, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4592 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4591 : @[Reg.scala 28:19]
|
|
_T_4592 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[121] <= _T_4592 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4593 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4594 = eq(_T_4593, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4595 = and(_T_4594, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4596 = and(_T_4595, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4597 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4596 : @[Reg.scala 28:19]
|
|
_T_4597 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[122] <= _T_4597 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4598 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4599 = eq(_T_4598, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4600 = and(_T_4599, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4601 = and(_T_4600, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4602 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4601 : @[Reg.scala 28:19]
|
|
_T_4602 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[123] <= _T_4602 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4603 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4604 = eq(_T_4603, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4605 = and(_T_4604, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4606 = and(_T_4605, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4607 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4606 : @[Reg.scala 28:19]
|
|
_T_4607 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[124] <= _T_4607 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4608 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4609 = eq(_T_4608, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4610 = and(_T_4609, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4611 = and(_T_4610, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4612 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4611 : @[Reg.scala 28:19]
|
|
_T_4612 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[125] <= _T_4612 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4613 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4614 = eq(_T_4613, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4615 = and(_T_4614, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4616 = and(_T_4615, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4617 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4616 : @[Reg.scala 28:19]
|
|
_T_4617 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[126] <= _T_4617 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4618 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 724:95]
|
|
node _T_4619 = eq(_T_4618, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:100]
|
|
node _T_4620 = and(_T_4619, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 724:108]
|
|
node _T_4621 = and(_T_4620, way_status_clken_15) @[el2_ifu_mem_ctl.scala 724:131]
|
|
reg _T_4622 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4621 : @[Reg.scala 28:19]
|
|
_T_4622 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[127] <= _T_4622 @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_4623 = cat(way_status_out[127], way_status_out[126]) @[Cat.scala 29:58]
|
|
node _T_4624 = cat(_T_4623, way_status_out[125]) @[Cat.scala 29:58]
|
|
node _T_4625 = cat(_T_4624, way_status_out[124]) @[Cat.scala 29:58]
|
|
node _T_4626 = cat(_T_4625, way_status_out[123]) @[Cat.scala 29:58]
|
|
node _T_4627 = cat(_T_4626, way_status_out[122]) @[Cat.scala 29:58]
|
|
node _T_4628 = cat(_T_4627, way_status_out[121]) @[Cat.scala 29:58]
|
|
node _T_4629 = cat(_T_4628, way_status_out[120]) @[Cat.scala 29:58]
|
|
node _T_4630 = cat(_T_4629, way_status_out[119]) @[Cat.scala 29:58]
|
|
node _T_4631 = cat(_T_4630, way_status_out[118]) @[Cat.scala 29:58]
|
|
node _T_4632 = cat(_T_4631, way_status_out[117]) @[Cat.scala 29:58]
|
|
node _T_4633 = cat(_T_4632, way_status_out[116]) @[Cat.scala 29:58]
|
|
node _T_4634 = cat(_T_4633, way_status_out[115]) @[Cat.scala 29:58]
|
|
node _T_4635 = cat(_T_4634, way_status_out[114]) @[Cat.scala 29:58]
|
|
node _T_4636 = cat(_T_4635, way_status_out[113]) @[Cat.scala 29:58]
|
|
node _T_4637 = cat(_T_4636, way_status_out[112]) @[Cat.scala 29:58]
|
|
node _T_4638 = cat(_T_4637, way_status_out[111]) @[Cat.scala 29:58]
|
|
node _T_4639 = cat(_T_4638, way_status_out[110]) @[Cat.scala 29:58]
|
|
node _T_4640 = cat(_T_4639, way_status_out[109]) @[Cat.scala 29:58]
|
|
node _T_4641 = cat(_T_4640, way_status_out[108]) @[Cat.scala 29:58]
|
|
node _T_4642 = cat(_T_4641, way_status_out[107]) @[Cat.scala 29:58]
|
|
node _T_4643 = cat(_T_4642, way_status_out[106]) @[Cat.scala 29:58]
|
|
node _T_4644 = cat(_T_4643, way_status_out[105]) @[Cat.scala 29:58]
|
|
node _T_4645 = cat(_T_4644, way_status_out[104]) @[Cat.scala 29:58]
|
|
node _T_4646 = cat(_T_4645, way_status_out[103]) @[Cat.scala 29:58]
|
|
node _T_4647 = cat(_T_4646, way_status_out[102]) @[Cat.scala 29:58]
|
|
node _T_4648 = cat(_T_4647, way_status_out[101]) @[Cat.scala 29:58]
|
|
node _T_4649 = cat(_T_4648, way_status_out[100]) @[Cat.scala 29:58]
|
|
node _T_4650 = cat(_T_4649, way_status_out[99]) @[Cat.scala 29:58]
|
|
node _T_4651 = cat(_T_4650, way_status_out[98]) @[Cat.scala 29:58]
|
|
node _T_4652 = cat(_T_4651, way_status_out[97]) @[Cat.scala 29:58]
|
|
node _T_4653 = cat(_T_4652, way_status_out[96]) @[Cat.scala 29:58]
|
|
node _T_4654 = cat(_T_4653, way_status_out[95]) @[Cat.scala 29:58]
|
|
node _T_4655 = cat(_T_4654, way_status_out[94]) @[Cat.scala 29:58]
|
|
node _T_4656 = cat(_T_4655, way_status_out[93]) @[Cat.scala 29:58]
|
|
node _T_4657 = cat(_T_4656, way_status_out[92]) @[Cat.scala 29:58]
|
|
node _T_4658 = cat(_T_4657, way_status_out[91]) @[Cat.scala 29:58]
|
|
node _T_4659 = cat(_T_4658, way_status_out[90]) @[Cat.scala 29:58]
|
|
node _T_4660 = cat(_T_4659, way_status_out[89]) @[Cat.scala 29:58]
|
|
node _T_4661 = cat(_T_4660, way_status_out[88]) @[Cat.scala 29:58]
|
|
node _T_4662 = cat(_T_4661, way_status_out[87]) @[Cat.scala 29:58]
|
|
node _T_4663 = cat(_T_4662, way_status_out[86]) @[Cat.scala 29:58]
|
|
node _T_4664 = cat(_T_4663, way_status_out[85]) @[Cat.scala 29:58]
|
|
node _T_4665 = cat(_T_4664, way_status_out[84]) @[Cat.scala 29:58]
|
|
node _T_4666 = cat(_T_4665, way_status_out[83]) @[Cat.scala 29:58]
|
|
node _T_4667 = cat(_T_4666, way_status_out[82]) @[Cat.scala 29:58]
|
|
node _T_4668 = cat(_T_4667, way_status_out[81]) @[Cat.scala 29:58]
|
|
node _T_4669 = cat(_T_4668, way_status_out[80]) @[Cat.scala 29:58]
|
|
node _T_4670 = cat(_T_4669, way_status_out[79]) @[Cat.scala 29:58]
|
|
node _T_4671 = cat(_T_4670, way_status_out[78]) @[Cat.scala 29:58]
|
|
node _T_4672 = cat(_T_4671, way_status_out[77]) @[Cat.scala 29:58]
|
|
node _T_4673 = cat(_T_4672, way_status_out[76]) @[Cat.scala 29:58]
|
|
node _T_4674 = cat(_T_4673, way_status_out[75]) @[Cat.scala 29:58]
|
|
node _T_4675 = cat(_T_4674, way_status_out[74]) @[Cat.scala 29:58]
|
|
node _T_4676 = cat(_T_4675, way_status_out[73]) @[Cat.scala 29:58]
|
|
node _T_4677 = cat(_T_4676, way_status_out[72]) @[Cat.scala 29:58]
|
|
node _T_4678 = cat(_T_4677, way_status_out[71]) @[Cat.scala 29:58]
|
|
node _T_4679 = cat(_T_4678, way_status_out[70]) @[Cat.scala 29:58]
|
|
node _T_4680 = cat(_T_4679, way_status_out[69]) @[Cat.scala 29:58]
|
|
node _T_4681 = cat(_T_4680, way_status_out[68]) @[Cat.scala 29:58]
|
|
node _T_4682 = cat(_T_4681, way_status_out[67]) @[Cat.scala 29:58]
|
|
node _T_4683 = cat(_T_4682, way_status_out[66]) @[Cat.scala 29:58]
|
|
node _T_4684 = cat(_T_4683, way_status_out[65]) @[Cat.scala 29:58]
|
|
node _T_4685 = cat(_T_4684, way_status_out[64]) @[Cat.scala 29:58]
|
|
node _T_4686 = cat(_T_4685, way_status_out[63]) @[Cat.scala 29:58]
|
|
node _T_4687 = cat(_T_4686, way_status_out[62]) @[Cat.scala 29:58]
|
|
node _T_4688 = cat(_T_4687, way_status_out[61]) @[Cat.scala 29:58]
|
|
node _T_4689 = cat(_T_4688, way_status_out[60]) @[Cat.scala 29:58]
|
|
node _T_4690 = cat(_T_4689, way_status_out[59]) @[Cat.scala 29:58]
|
|
node _T_4691 = cat(_T_4690, way_status_out[58]) @[Cat.scala 29:58]
|
|
node _T_4692 = cat(_T_4691, way_status_out[57]) @[Cat.scala 29:58]
|
|
node _T_4693 = cat(_T_4692, way_status_out[56]) @[Cat.scala 29:58]
|
|
node _T_4694 = cat(_T_4693, way_status_out[55]) @[Cat.scala 29:58]
|
|
node _T_4695 = cat(_T_4694, way_status_out[54]) @[Cat.scala 29:58]
|
|
node _T_4696 = cat(_T_4695, way_status_out[53]) @[Cat.scala 29:58]
|
|
node _T_4697 = cat(_T_4696, way_status_out[52]) @[Cat.scala 29:58]
|
|
node _T_4698 = cat(_T_4697, way_status_out[51]) @[Cat.scala 29:58]
|
|
node _T_4699 = cat(_T_4698, way_status_out[50]) @[Cat.scala 29:58]
|
|
node _T_4700 = cat(_T_4699, way_status_out[49]) @[Cat.scala 29:58]
|
|
node _T_4701 = cat(_T_4700, way_status_out[48]) @[Cat.scala 29:58]
|
|
node _T_4702 = cat(_T_4701, way_status_out[47]) @[Cat.scala 29:58]
|
|
node _T_4703 = cat(_T_4702, way_status_out[46]) @[Cat.scala 29:58]
|
|
node _T_4704 = cat(_T_4703, way_status_out[45]) @[Cat.scala 29:58]
|
|
node _T_4705 = cat(_T_4704, way_status_out[44]) @[Cat.scala 29:58]
|
|
node _T_4706 = cat(_T_4705, way_status_out[43]) @[Cat.scala 29:58]
|
|
node _T_4707 = cat(_T_4706, way_status_out[42]) @[Cat.scala 29:58]
|
|
node _T_4708 = cat(_T_4707, way_status_out[41]) @[Cat.scala 29:58]
|
|
node _T_4709 = cat(_T_4708, way_status_out[40]) @[Cat.scala 29:58]
|
|
node _T_4710 = cat(_T_4709, way_status_out[39]) @[Cat.scala 29:58]
|
|
node _T_4711 = cat(_T_4710, way_status_out[38]) @[Cat.scala 29:58]
|
|
node _T_4712 = cat(_T_4711, way_status_out[37]) @[Cat.scala 29:58]
|
|
node _T_4713 = cat(_T_4712, way_status_out[36]) @[Cat.scala 29:58]
|
|
node _T_4714 = cat(_T_4713, way_status_out[35]) @[Cat.scala 29:58]
|
|
node _T_4715 = cat(_T_4714, way_status_out[34]) @[Cat.scala 29:58]
|
|
node _T_4716 = cat(_T_4715, way_status_out[33]) @[Cat.scala 29:58]
|
|
node _T_4717 = cat(_T_4716, way_status_out[32]) @[Cat.scala 29:58]
|
|
node _T_4718 = cat(_T_4717, way_status_out[31]) @[Cat.scala 29:58]
|
|
node _T_4719 = cat(_T_4718, way_status_out[30]) @[Cat.scala 29:58]
|
|
node _T_4720 = cat(_T_4719, way_status_out[29]) @[Cat.scala 29:58]
|
|
node _T_4721 = cat(_T_4720, way_status_out[28]) @[Cat.scala 29:58]
|
|
node _T_4722 = cat(_T_4721, way_status_out[27]) @[Cat.scala 29:58]
|
|
node _T_4723 = cat(_T_4722, way_status_out[26]) @[Cat.scala 29:58]
|
|
node _T_4724 = cat(_T_4723, way_status_out[25]) @[Cat.scala 29:58]
|
|
node _T_4725 = cat(_T_4724, way_status_out[24]) @[Cat.scala 29:58]
|
|
node _T_4726 = cat(_T_4725, way_status_out[23]) @[Cat.scala 29:58]
|
|
node _T_4727 = cat(_T_4726, way_status_out[22]) @[Cat.scala 29:58]
|
|
node _T_4728 = cat(_T_4727, way_status_out[21]) @[Cat.scala 29:58]
|
|
node _T_4729 = cat(_T_4728, way_status_out[20]) @[Cat.scala 29:58]
|
|
node _T_4730 = cat(_T_4729, way_status_out[19]) @[Cat.scala 29:58]
|
|
node _T_4731 = cat(_T_4730, way_status_out[18]) @[Cat.scala 29:58]
|
|
node _T_4732 = cat(_T_4731, way_status_out[17]) @[Cat.scala 29:58]
|
|
node _T_4733 = cat(_T_4732, way_status_out[16]) @[Cat.scala 29:58]
|
|
node _T_4734 = cat(_T_4733, way_status_out[15]) @[Cat.scala 29:58]
|
|
node _T_4735 = cat(_T_4734, way_status_out[14]) @[Cat.scala 29:58]
|
|
node _T_4736 = cat(_T_4735, way_status_out[13]) @[Cat.scala 29:58]
|
|
node _T_4737 = cat(_T_4736, way_status_out[12]) @[Cat.scala 29:58]
|
|
node _T_4738 = cat(_T_4737, way_status_out[11]) @[Cat.scala 29:58]
|
|
node _T_4739 = cat(_T_4738, way_status_out[10]) @[Cat.scala 29:58]
|
|
node _T_4740 = cat(_T_4739, way_status_out[9]) @[Cat.scala 29:58]
|
|
node _T_4741 = cat(_T_4740, way_status_out[8]) @[Cat.scala 29:58]
|
|
node _T_4742 = cat(_T_4741, way_status_out[7]) @[Cat.scala 29:58]
|
|
node _T_4743 = cat(_T_4742, way_status_out[6]) @[Cat.scala 29:58]
|
|
node _T_4744 = cat(_T_4743, way_status_out[5]) @[Cat.scala 29:58]
|
|
node _T_4745 = cat(_T_4744, way_status_out[4]) @[Cat.scala 29:58]
|
|
node _T_4746 = cat(_T_4745, way_status_out[3]) @[Cat.scala 29:58]
|
|
node _T_4747 = cat(_T_4746, way_status_out[2]) @[Cat.scala 29:58]
|
|
node _T_4748 = cat(_T_4747, way_status_out[1]) @[Cat.scala 29:58]
|
|
node test_way_status_out = cat(_T_4748, way_status_out[0]) @[Cat.scala 29:58]
|
|
node _T_4749 = cat(way_status_clken_15, way_status_clken_14) @[Cat.scala 29:58]
|
|
node _T_4750 = cat(_T_4749, way_status_clken_13) @[Cat.scala 29:58]
|
|
node _T_4751 = cat(_T_4750, way_status_clken_12) @[Cat.scala 29:58]
|
|
node _T_4752 = cat(_T_4751, way_status_clken_11) @[Cat.scala 29:58]
|
|
node _T_4753 = cat(_T_4752, way_status_clken_10) @[Cat.scala 29:58]
|
|
node _T_4754 = cat(_T_4753, way_status_clken_9) @[Cat.scala 29:58]
|
|
node _T_4755 = cat(_T_4754, way_status_clken_8) @[Cat.scala 29:58]
|
|
node _T_4756 = cat(_T_4755, way_status_clken_7) @[Cat.scala 29:58]
|
|
node _T_4757 = cat(_T_4756, way_status_clken_6) @[Cat.scala 29:58]
|
|
node _T_4758 = cat(_T_4757, way_status_clken_5) @[Cat.scala 29:58]
|
|
node _T_4759 = cat(_T_4758, way_status_clken_4) @[Cat.scala 29:58]
|
|
node _T_4760 = cat(_T_4759, way_status_clken_3) @[Cat.scala 29:58]
|
|
node _T_4761 = cat(_T_4760, way_status_clken_2) @[Cat.scala 29:58]
|
|
node _T_4762 = cat(_T_4761, way_status_clken_1) @[Cat.scala 29:58]
|
|
node test_way_status_clken = cat(_T_4762, way_status_clken_0) @[Cat.scala 29:58]
|
|
node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4766 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4770 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4774 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4778 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4782 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4786 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4790 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4794 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4798 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4799 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4800 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4801 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4803 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4804 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4806 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4807 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4808 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4809 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4810 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4811 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4812 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4813 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4814 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4815 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4816 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4817 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4818 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4819 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4821 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4822 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4823 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4824 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4825 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4826 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4827 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4829 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4831 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4833 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4835 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4837 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4838 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4839 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4841 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4843 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4844 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4846 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4847 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4849 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4851 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4852 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4853 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4854 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4856 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4857 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4859 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4861 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4862 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4863 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4865 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4867 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4868 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4869 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4871 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4873 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4876 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4877 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4878 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4880 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4881 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4883 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4884 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4886 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4887 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4888 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4889 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 729:80]
|
|
node _T_4891 = mux(_T_4763, way_status_out[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4892 = mux(_T_4764, way_status_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4893 = mux(_T_4765, way_status_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4894 = mux(_T_4766, way_status_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4895 = mux(_T_4767, way_status_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4896 = mux(_T_4768, way_status_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4897 = mux(_T_4769, way_status_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4898 = mux(_T_4770, way_status_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4899 = mux(_T_4771, way_status_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4900 = mux(_T_4772, way_status_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4901 = mux(_T_4773, way_status_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4902 = mux(_T_4774, way_status_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4903 = mux(_T_4775, way_status_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4904 = mux(_T_4776, way_status_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4905 = mux(_T_4777, way_status_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4906 = mux(_T_4778, way_status_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4907 = mux(_T_4779, way_status_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4908 = mux(_T_4780, way_status_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4909 = mux(_T_4781, way_status_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4910 = mux(_T_4782, way_status_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4911 = mux(_T_4783, way_status_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4912 = mux(_T_4784, way_status_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4913 = mux(_T_4785, way_status_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4914 = mux(_T_4786, way_status_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4915 = mux(_T_4787, way_status_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4916 = mux(_T_4788, way_status_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4917 = mux(_T_4789, way_status_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4918 = mux(_T_4790, way_status_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4919 = mux(_T_4791, way_status_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4920 = mux(_T_4792, way_status_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4921 = mux(_T_4793, way_status_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4922 = mux(_T_4794, way_status_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4923 = mux(_T_4795, way_status_out[32], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4924 = mux(_T_4796, way_status_out[33], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4925 = mux(_T_4797, way_status_out[34], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4926 = mux(_T_4798, way_status_out[35], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4927 = mux(_T_4799, way_status_out[36], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4928 = mux(_T_4800, way_status_out[37], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4929 = mux(_T_4801, way_status_out[38], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4930 = mux(_T_4802, way_status_out[39], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4931 = mux(_T_4803, way_status_out[40], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4932 = mux(_T_4804, way_status_out[41], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4933 = mux(_T_4805, way_status_out[42], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4934 = mux(_T_4806, way_status_out[43], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4935 = mux(_T_4807, way_status_out[44], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4936 = mux(_T_4808, way_status_out[45], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4937 = mux(_T_4809, way_status_out[46], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4938 = mux(_T_4810, way_status_out[47], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4939 = mux(_T_4811, way_status_out[48], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4940 = mux(_T_4812, way_status_out[49], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4941 = mux(_T_4813, way_status_out[50], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4942 = mux(_T_4814, way_status_out[51], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4943 = mux(_T_4815, way_status_out[52], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4944 = mux(_T_4816, way_status_out[53], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4945 = mux(_T_4817, way_status_out[54], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4946 = mux(_T_4818, way_status_out[55], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4947 = mux(_T_4819, way_status_out[56], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4948 = mux(_T_4820, way_status_out[57], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4949 = mux(_T_4821, way_status_out[58], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4950 = mux(_T_4822, way_status_out[59], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4951 = mux(_T_4823, way_status_out[60], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4952 = mux(_T_4824, way_status_out[61], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4953 = mux(_T_4825, way_status_out[62], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4954 = mux(_T_4826, way_status_out[63], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4955 = mux(_T_4827, way_status_out[64], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4956 = mux(_T_4828, way_status_out[65], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4957 = mux(_T_4829, way_status_out[66], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4958 = mux(_T_4830, way_status_out[67], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4959 = mux(_T_4831, way_status_out[68], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4960 = mux(_T_4832, way_status_out[69], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4961 = mux(_T_4833, way_status_out[70], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4962 = mux(_T_4834, way_status_out[71], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4963 = mux(_T_4835, way_status_out[72], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4964 = mux(_T_4836, way_status_out[73], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4965 = mux(_T_4837, way_status_out[74], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4966 = mux(_T_4838, way_status_out[75], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4967 = mux(_T_4839, way_status_out[76], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4968 = mux(_T_4840, way_status_out[77], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4969 = mux(_T_4841, way_status_out[78], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4970 = mux(_T_4842, way_status_out[79], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4971 = mux(_T_4843, way_status_out[80], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4972 = mux(_T_4844, way_status_out[81], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4973 = mux(_T_4845, way_status_out[82], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4974 = mux(_T_4846, way_status_out[83], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4975 = mux(_T_4847, way_status_out[84], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4976 = mux(_T_4848, way_status_out[85], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4977 = mux(_T_4849, way_status_out[86], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4978 = mux(_T_4850, way_status_out[87], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4979 = mux(_T_4851, way_status_out[88], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4980 = mux(_T_4852, way_status_out[89], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4981 = mux(_T_4853, way_status_out[90], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4982 = mux(_T_4854, way_status_out[91], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4983 = mux(_T_4855, way_status_out[92], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4984 = mux(_T_4856, way_status_out[93], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4985 = mux(_T_4857, way_status_out[94], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4986 = mux(_T_4858, way_status_out[95], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4987 = mux(_T_4859, way_status_out[96], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4988 = mux(_T_4860, way_status_out[97], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4989 = mux(_T_4861, way_status_out[98], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4990 = mux(_T_4862, way_status_out[99], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4991 = mux(_T_4863, way_status_out[100], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4992 = mux(_T_4864, way_status_out[101], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4993 = mux(_T_4865, way_status_out[102], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4994 = mux(_T_4866, way_status_out[103], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4995 = mux(_T_4867, way_status_out[104], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4996 = mux(_T_4868, way_status_out[105], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4997 = mux(_T_4869, way_status_out[106], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4998 = mux(_T_4870, way_status_out[107], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_4999 = mux(_T_4871, way_status_out[108], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5000 = mux(_T_4872, way_status_out[109], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5001 = mux(_T_4873, way_status_out[110], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5002 = mux(_T_4874, way_status_out[111], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5003 = mux(_T_4875, way_status_out[112], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5004 = mux(_T_4876, way_status_out[113], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5005 = mux(_T_4877, way_status_out[114], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5006 = mux(_T_4878, way_status_out[115], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5007 = mux(_T_4879, way_status_out[116], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5008 = mux(_T_4880, way_status_out[117], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5009 = mux(_T_4881, way_status_out[118], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5010 = mux(_T_4882, way_status_out[119], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5011 = mux(_T_4883, way_status_out[120], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5012 = mux(_T_4884, way_status_out[121], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5013 = mux(_T_4885, way_status_out[122], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5014 = mux(_T_4886, way_status_out[123], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5015 = mux(_T_4887, way_status_out[124], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5016 = mux(_T_4888, way_status_out[125], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5017 = mux(_T_4889, way_status_out[126], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5018 = mux(_T_4890, way_status_out[127], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_5019 = or(_T_4891, _T_4892) @[Mux.scala 27:72]
|
|
node _T_5020 = or(_T_5019, _T_4893) @[Mux.scala 27:72]
|
|
node _T_5021 = or(_T_5020, _T_4894) @[Mux.scala 27:72]
|
|
node _T_5022 = or(_T_5021, _T_4895) @[Mux.scala 27:72]
|
|
node _T_5023 = or(_T_5022, _T_4896) @[Mux.scala 27:72]
|
|
node _T_5024 = or(_T_5023, _T_4897) @[Mux.scala 27:72]
|
|
node _T_5025 = or(_T_5024, _T_4898) @[Mux.scala 27:72]
|
|
node _T_5026 = or(_T_5025, _T_4899) @[Mux.scala 27:72]
|
|
node _T_5027 = or(_T_5026, _T_4900) @[Mux.scala 27:72]
|
|
node _T_5028 = or(_T_5027, _T_4901) @[Mux.scala 27:72]
|
|
node _T_5029 = or(_T_5028, _T_4902) @[Mux.scala 27:72]
|
|
node _T_5030 = or(_T_5029, _T_4903) @[Mux.scala 27:72]
|
|
node _T_5031 = or(_T_5030, _T_4904) @[Mux.scala 27:72]
|
|
node _T_5032 = or(_T_5031, _T_4905) @[Mux.scala 27:72]
|
|
node _T_5033 = or(_T_5032, _T_4906) @[Mux.scala 27:72]
|
|
node _T_5034 = or(_T_5033, _T_4907) @[Mux.scala 27:72]
|
|
node _T_5035 = or(_T_5034, _T_4908) @[Mux.scala 27:72]
|
|
node _T_5036 = or(_T_5035, _T_4909) @[Mux.scala 27:72]
|
|
node _T_5037 = or(_T_5036, _T_4910) @[Mux.scala 27:72]
|
|
node _T_5038 = or(_T_5037, _T_4911) @[Mux.scala 27:72]
|
|
node _T_5039 = or(_T_5038, _T_4912) @[Mux.scala 27:72]
|
|
node _T_5040 = or(_T_5039, _T_4913) @[Mux.scala 27:72]
|
|
node _T_5041 = or(_T_5040, _T_4914) @[Mux.scala 27:72]
|
|
node _T_5042 = or(_T_5041, _T_4915) @[Mux.scala 27:72]
|
|
node _T_5043 = or(_T_5042, _T_4916) @[Mux.scala 27:72]
|
|
node _T_5044 = or(_T_5043, _T_4917) @[Mux.scala 27:72]
|
|
node _T_5045 = or(_T_5044, _T_4918) @[Mux.scala 27:72]
|
|
node _T_5046 = or(_T_5045, _T_4919) @[Mux.scala 27:72]
|
|
node _T_5047 = or(_T_5046, _T_4920) @[Mux.scala 27:72]
|
|
node _T_5048 = or(_T_5047, _T_4921) @[Mux.scala 27:72]
|
|
node _T_5049 = or(_T_5048, _T_4922) @[Mux.scala 27:72]
|
|
node _T_5050 = or(_T_5049, _T_4923) @[Mux.scala 27:72]
|
|
node _T_5051 = or(_T_5050, _T_4924) @[Mux.scala 27:72]
|
|
node _T_5052 = or(_T_5051, _T_4925) @[Mux.scala 27:72]
|
|
node _T_5053 = or(_T_5052, _T_4926) @[Mux.scala 27:72]
|
|
node _T_5054 = or(_T_5053, _T_4927) @[Mux.scala 27:72]
|
|
node _T_5055 = or(_T_5054, _T_4928) @[Mux.scala 27:72]
|
|
node _T_5056 = or(_T_5055, _T_4929) @[Mux.scala 27:72]
|
|
node _T_5057 = or(_T_5056, _T_4930) @[Mux.scala 27:72]
|
|
node _T_5058 = or(_T_5057, _T_4931) @[Mux.scala 27:72]
|
|
node _T_5059 = or(_T_5058, _T_4932) @[Mux.scala 27:72]
|
|
node _T_5060 = or(_T_5059, _T_4933) @[Mux.scala 27:72]
|
|
node _T_5061 = or(_T_5060, _T_4934) @[Mux.scala 27:72]
|
|
node _T_5062 = or(_T_5061, _T_4935) @[Mux.scala 27:72]
|
|
node _T_5063 = or(_T_5062, _T_4936) @[Mux.scala 27:72]
|
|
node _T_5064 = or(_T_5063, _T_4937) @[Mux.scala 27:72]
|
|
node _T_5065 = or(_T_5064, _T_4938) @[Mux.scala 27:72]
|
|
node _T_5066 = or(_T_5065, _T_4939) @[Mux.scala 27:72]
|
|
node _T_5067 = or(_T_5066, _T_4940) @[Mux.scala 27:72]
|
|
node _T_5068 = or(_T_5067, _T_4941) @[Mux.scala 27:72]
|
|
node _T_5069 = or(_T_5068, _T_4942) @[Mux.scala 27:72]
|
|
node _T_5070 = or(_T_5069, _T_4943) @[Mux.scala 27:72]
|
|
node _T_5071 = or(_T_5070, _T_4944) @[Mux.scala 27:72]
|
|
node _T_5072 = or(_T_5071, _T_4945) @[Mux.scala 27:72]
|
|
node _T_5073 = or(_T_5072, _T_4946) @[Mux.scala 27:72]
|
|
node _T_5074 = or(_T_5073, _T_4947) @[Mux.scala 27:72]
|
|
node _T_5075 = or(_T_5074, _T_4948) @[Mux.scala 27:72]
|
|
node _T_5076 = or(_T_5075, _T_4949) @[Mux.scala 27:72]
|
|
node _T_5077 = or(_T_5076, _T_4950) @[Mux.scala 27:72]
|
|
node _T_5078 = or(_T_5077, _T_4951) @[Mux.scala 27:72]
|
|
node _T_5079 = or(_T_5078, _T_4952) @[Mux.scala 27:72]
|
|
node _T_5080 = or(_T_5079, _T_4953) @[Mux.scala 27:72]
|
|
node _T_5081 = or(_T_5080, _T_4954) @[Mux.scala 27:72]
|
|
node _T_5082 = or(_T_5081, _T_4955) @[Mux.scala 27:72]
|
|
node _T_5083 = or(_T_5082, _T_4956) @[Mux.scala 27:72]
|
|
node _T_5084 = or(_T_5083, _T_4957) @[Mux.scala 27:72]
|
|
node _T_5085 = or(_T_5084, _T_4958) @[Mux.scala 27:72]
|
|
node _T_5086 = or(_T_5085, _T_4959) @[Mux.scala 27:72]
|
|
node _T_5087 = or(_T_5086, _T_4960) @[Mux.scala 27:72]
|
|
node _T_5088 = or(_T_5087, _T_4961) @[Mux.scala 27:72]
|
|
node _T_5089 = or(_T_5088, _T_4962) @[Mux.scala 27:72]
|
|
node _T_5090 = or(_T_5089, _T_4963) @[Mux.scala 27:72]
|
|
node _T_5091 = or(_T_5090, _T_4964) @[Mux.scala 27:72]
|
|
node _T_5092 = or(_T_5091, _T_4965) @[Mux.scala 27:72]
|
|
node _T_5093 = or(_T_5092, _T_4966) @[Mux.scala 27:72]
|
|
node _T_5094 = or(_T_5093, _T_4967) @[Mux.scala 27:72]
|
|
node _T_5095 = or(_T_5094, _T_4968) @[Mux.scala 27:72]
|
|
node _T_5096 = or(_T_5095, _T_4969) @[Mux.scala 27:72]
|
|
node _T_5097 = or(_T_5096, _T_4970) @[Mux.scala 27:72]
|
|
node _T_5098 = or(_T_5097, _T_4971) @[Mux.scala 27:72]
|
|
node _T_5099 = or(_T_5098, _T_4972) @[Mux.scala 27:72]
|
|
node _T_5100 = or(_T_5099, _T_4973) @[Mux.scala 27:72]
|
|
node _T_5101 = or(_T_5100, _T_4974) @[Mux.scala 27:72]
|
|
node _T_5102 = or(_T_5101, _T_4975) @[Mux.scala 27:72]
|
|
node _T_5103 = or(_T_5102, _T_4976) @[Mux.scala 27:72]
|
|
node _T_5104 = or(_T_5103, _T_4977) @[Mux.scala 27:72]
|
|
node _T_5105 = or(_T_5104, _T_4978) @[Mux.scala 27:72]
|
|
node _T_5106 = or(_T_5105, _T_4979) @[Mux.scala 27:72]
|
|
node _T_5107 = or(_T_5106, _T_4980) @[Mux.scala 27:72]
|
|
node _T_5108 = or(_T_5107, _T_4981) @[Mux.scala 27:72]
|
|
node _T_5109 = or(_T_5108, _T_4982) @[Mux.scala 27:72]
|
|
node _T_5110 = or(_T_5109, _T_4983) @[Mux.scala 27:72]
|
|
node _T_5111 = or(_T_5110, _T_4984) @[Mux.scala 27:72]
|
|
node _T_5112 = or(_T_5111, _T_4985) @[Mux.scala 27:72]
|
|
node _T_5113 = or(_T_5112, _T_4986) @[Mux.scala 27:72]
|
|
node _T_5114 = or(_T_5113, _T_4987) @[Mux.scala 27:72]
|
|
node _T_5115 = or(_T_5114, _T_4988) @[Mux.scala 27:72]
|
|
node _T_5116 = or(_T_5115, _T_4989) @[Mux.scala 27:72]
|
|
node _T_5117 = or(_T_5116, _T_4990) @[Mux.scala 27:72]
|
|
node _T_5118 = or(_T_5117, _T_4991) @[Mux.scala 27:72]
|
|
node _T_5119 = or(_T_5118, _T_4992) @[Mux.scala 27:72]
|
|
node _T_5120 = or(_T_5119, _T_4993) @[Mux.scala 27:72]
|
|
node _T_5121 = or(_T_5120, _T_4994) @[Mux.scala 27:72]
|
|
node _T_5122 = or(_T_5121, _T_4995) @[Mux.scala 27:72]
|
|
node _T_5123 = or(_T_5122, _T_4996) @[Mux.scala 27:72]
|
|
node _T_5124 = or(_T_5123, _T_4997) @[Mux.scala 27:72]
|
|
node _T_5125 = or(_T_5124, _T_4998) @[Mux.scala 27:72]
|
|
node _T_5126 = or(_T_5125, _T_4999) @[Mux.scala 27:72]
|
|
node _T_5127 = or(_T_5126, _T_5000) @[Mux.scala 27:72]
|
|
node _T_5128 = or(_T_5127, _T_5001) @[Mux.scala 27:72]
|
|
node _T_5129 = or(_T_5128, _T_5002) @[Mux.scala 27:72]
|
|
node _T_5130 = or(_T_5129, _T_5003) @[Mux.scala 27:72]
|
|
node _T_5131 = or(_T_5130, _T_5004) @[Mux.scala 27:72]
|
|
node _T_5132 = or(_T_5131, _T_5005) @[Mux.scala 27:72]
|
|
node _T_5133 = or(_T_5132, _T_5006) @[Mux.scala 27:72]
|
|
node _T_5134 = or(_T_5133, _T_5007) @[Mux.scala 27:72]
|
|
node _T_5135 = or(_T_5134, _T_5008) @[Mux.scala 27:72]
|
|
node _T_5136 = or(_T_5135, _T_5009) @[Mux.scala 27:72]
|
|
node _T_5137 = or(_T_5136, _T_5010) @[Mux.scala 27:72]
|
|
node _T_5138 = or(_T_5137, _T_5011) @[Mux.scala 27:72]
|
|
node _T_5139 = or(_T_5138, _T_5012) @[Mux.scala 27:72]
|
|
node _T_5140 = or(_T_5139, _T_5013) @[Mux.scala 27:72]
|
|
node _T_5141 = or(_T_5140, _T_5014) @[Mux.scala 27:72]
|
|
node _T_5142 = or(_T_5141, _T_5015) @[Mux.scala 27:72]
|
|
node _T_5143 = or(_T_5142, _T_5016) @[Mux.scala 27:72]
|
|
node _T_5144 = or(_T_5143, _T_5017) @[Mux.scala 27:72]
|
|
node _T_5145 = or(_T_5144, _T_5018) @[Mux.scala 27:72]
|
|
wire _T_5146 : UInt<1> @[Mux.scala 27:72]
|
|
_T_5146 <= _T_5145 @[Mux.scala 27:72]
|
|
way_status <= _T_5146 @[el2_ifu_mem_ctl.scala 729:14]
|
|
node _T_5147 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 730:61]
|
|
node _T_5148 = and(_T_5147, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 730:82]
|
|
node _T_5149 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 731:23]
|
|
node _T_5150 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 731:89]
|
|
node ifu_ic_rw_int_addr_w_debug = mux(_T_5148, _T_5149, _T_5150) @[el2_ifu_mem_ctl.scala 730:41]
|
|
reg _T_5151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 733:14]
|
|
_T_5151 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 733:14]
|
|
ifu_ic_rw_int_addr_ff <= _T_5151 @[el2_ifu_mem_ctl.scala 732:27]
|
|
wire ifu_tag_wren : UInt<2>
|
|
ifu_tag_wren <= UInt<1>("h00")
|
|
wire ic_debug_tag_wr_en : UInt<2>
|
|
ic_debug_tag_wr_en <= UInt<1>("h00")
|
|
node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 737:45]
|
|
reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 739:14]
|
|
ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 739:14]
|
|
node _T_5152 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 741:50]
|
|
node _T_5153 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 741:94]
|
|
node ic_valid_w_debug = mux(_T_5152, _T_5153, ic_valid) @[el2_ifu_mem_ctl.scala 741:31]
|
|
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 743:14]
|
|
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 743:14]
|
|
node _T_5154 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5155 = eq(_T_5154, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5156 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5157 = and(_T_5155, _T_5156) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5158 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5159 = eq(_T_5158, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5160 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5161 = and(_T_5159, _T_5160) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5162 = or(_T_5157, _T_5161) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5163 = or(_T_5162, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node _T_5164 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5165 = eq(_T_5164, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5166 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5167 = and(_T_5165, _T_5166) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5168 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5169 = eq(_T_5168, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5170 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5171 = and(_T_5169, _T_5170) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5172 = or(_T_5167, _T_5171) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5173 = or(_T_5172, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node tag_valid_clken_0 = cat(_T_5173, _T_5163) @[Cat.scala 29:58]
|
|
node _T_5174 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5175 = eq(_T_5174, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5176 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5177 = and(_T_5175, _T_5176) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5178 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5179 = eq(_T_5178, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5180 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5181 = and(_T_5179, _T_5180) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5182 = or(_T_5177, _T_5181) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5183 = or(_T_5182, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node _T_5184 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5185 = eq(_T_5184, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5186 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5187 = and(_T_5185, _T_5186) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5188 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5189 = eq(_T_5188, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5190 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5191 = and(_T_5189, _T_5190) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5192 = or(_T_5187, _T_5191) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5193 = or(_T_5192, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node tag_valid_clken_1 = cat(_T_5193, _T_5183) @[Cat.scala 29:58]
|
|
node _T_5194 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5195 = eq(_T_5194, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5196 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5197 = and(_T_5195, _T_5196) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5198 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5199 = eq(_T_5198, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5200 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5201 = and(_T_5199, _T_5200) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5202 = or(_T_5197, _T_5201) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5203 = or(_T_5202, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node _T_5204 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5205 = eq(_T_5204, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5206 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5207 = and(_T_5205, _T_5206) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5208 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5209 = eq(_T_5208, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5210 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5211 = and(_T_5209, _T_5210) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5212 = or(_T_5207, _T_5211) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5213 = or(_T_5212, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node tag_valid_clken_2 = cat(_T_5213, _T_5203) @[Cat.scala 29:58]
|
|
node _T_5214 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5215 = eq(_T_5214, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5217 = and(_T_5215, _T_5216) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5218 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5219 = eq(_T_5218, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5220 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5221 = and(_T_5219, _T_5220) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5222 = or(_T_5217, _T_5221) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5223 = or(_T_5222, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node _T_5224 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 747:35]
|
|
node _T_5225 = eq(_T_5224, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 747:78]
|
|
node _T_5226 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 747:104]
|
|
node _T_5227 = and(_T_5225, _T_5226) @[el2_ifu_mem_ctl.scala 747:87]
|
|
node _T_5228 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 748:27]
|
|
node _T_5229 = eq(_T_5228, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 748:70]
|
|
node _T_5230 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 748:97]
|
|
node _T_5231 = and(_T_5229, _T_5230) @[el2_ifu_mem_ctl.scala 748:79]
|
|
node _T_5232 = or(_T_5227, _T_5231) @[el2_ifu_mem_ctl.scala 747:109]
|
|
node _T_5233 = or(_T_5232, reset_all_tags) @[el2_ifu_mem_ctl.scala 748:102]
|
|
node tag_valid_clken_3 = cat(_T_5233, _T_5223) @[Cat.scala 29:58]
|
|
wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 751:32]
|
|
node _T_5234 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5235 = eq(_T_5234, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5236 = and(ic_valid_ff, _T_5235) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5237 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5238 = and(_T_5236, _T_5237) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5239 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5240 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5241 = and(_T_5239, _T_5240) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5242 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5243 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5244 = and(_T_5242, _T_5243) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5245 = or(_T_5241, _T_5244) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5246 = or(_T_5245, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5247 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5248 = and(_T_5246, _T_5247) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5249 = bits(_T_5248, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5250 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5249 : @[Reg.scala 28:19]
|
|
_T_5250 <= _T_5238 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][0] <= _T_5250 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5252 = eq(_T_5251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5253 = and(ic_valid_ff, _T_5252) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5255 = and(_T_5253, _T_5254) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5256 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5257 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5258 = and(_T_5256, _T_5257) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5259 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5260 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5261 = and(_T_5259, _T_5260) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5262 = or(_T_5258, _T_5261) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5263 = or(_T_5262, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5264 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5265 = and(_T_5263, _T_5264) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5266 = bits(_T_5265, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5267 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5266 : @[Reg.scala 28:19]
|
|
_T_5267 <= _T_5255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][1] <= _T_5267 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5268 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5269 = eq(_T_5268, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5270 = and(ic_valid_ff, _T_5269) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5271 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5272 = and(_T_5270, _T_5271) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5273 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5274 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5275 = and(_T_5273, _T_5274) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5276 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5277 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5278 = and(_T_5276, _T_5277) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5279 = or(_T_5275, _T_5278) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5280 = or(_T_5279, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5281 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5282 = and(_T_5280, _T_5281) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5283 = bits(_T_5282, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5284 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5283 : @[Reg.scala 28:19]
|
|
_T_5284 <= _T_5272 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][2] <= _T_5284 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5286 = eq(_T_5285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5287 = and(ic_valid_ff, _T_5286) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5289 = and(_T_5287, _T_5288) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5290 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5292 = and(_T_5290, _T_5291) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5293 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5294 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5295 = and(_T_5293, _T_5294) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5296 = or(_T_5292, _T_5295) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5297 = or(_T_5296, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5298 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5299 = and(_T_5297, _T_5298) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5300 = bits(_T_5299, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5301 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5300 : @[Reg.scala 28:19]
|
|
_T_5301 <= _T_5289 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][3] <= _T_5301 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5302 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5303 = eq(_T_5302, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5304 = and(ic_valid_ff, _T_5303) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5305 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5306 = and(_T_5304, _T_5305) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5307 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5308 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5309 = and(_T_5307, _T_5308) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5310 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5311 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5312 = and(_T_5310, _T_5311) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5313 = or(_T_5309, _T_5312) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5314 = or(_T_5313, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5315 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5316 = and(_T_5314, _T_5315) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5317 = bits(_T_5316, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5318 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5317 : @[Reg.scala 28:19]
|
|
_T_5318 <= _T_5306 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][4] <= _T_5318 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5319 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5320 = eq(_T_5319, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5321 = and(ic_valid_ff, _T_5320) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5322 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5323 = and(_T_5321, _T_5322) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5324 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5325 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5326 = and(_T_5324, _T_5325) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5327 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5328 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5329 = and(_T_5327, _T_5328) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5330 = or(_T_5326, _T_5329) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5331 = or(_T_5330, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5332 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5333 = and(_T_5331, _T_5332) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5334 = bits(_T_5333, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5335 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5334 : @[Reg.scala 28:19]
|
|
_T_5335 <= _T_5323 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][5] <= _T_5335 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5336 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5337 = eq(_T_5336, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5338 = and(ic_valid_ff, _T_5337) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5339 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5340 = and(_T_5338, _T_5339) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5341 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5343 = and(_T_5341, _T_5342) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5344 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5345 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5346 = and(_T_5344, _T_5345) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5347 = or(_T_5343, _T_5346) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5348 = or(_T_5347, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5349 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5350 = and(_T_5348, _T_5349) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5351 = bits(_T_5350, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5352 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5351 : @[Reg.scala 28:19]
|
|
_T_5352 <= _T_5340 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][6] <= _T_5352 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5353 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5354 = eq(_T_5353, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5355 = and(ic_valid_ff, _T_5354) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5356 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5357 = and(_T_5355, _T_5356) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5358 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5359 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5360 = and(_T_5358, _T_5359) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5361 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5362 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5363 = and(_T_5361, _T_5362) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5364 = or(_T_5360, _T_5363) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5365 = or(_T_5364, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5366 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5367 = and(_T_5365, _T_5366) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5368 = bits(_T_5367, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5369 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5368 : @[Reg.scala 28:19]
|
|
_T_5369 <= _T_5357 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][7] <= _T_5369 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5370 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5371 = eq(_T_5370, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5372 = and(ic_valid_ff, _T_5371) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5374 = and(_T_5372, _T_5373) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5375 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5376 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5377 = and(_T_5375, _T_5376) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5378 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5379 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5380 = and(_T_5378, _T_5379) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5381 = or(_T_5377, _T_5380) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5382 = or(_T_5381, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5383 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5384 = and(_T_5382, _T_5383) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5385 = bits(_T_5384, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5386 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5385 : @[Reg.scala 28:19]
|
|
_T_5386 <= _T_5374 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][8] <= _T_5386 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5387 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5388 = eq(_T_5387, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5389 = and(ic_valid_ff, _T_5388) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5390 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5391 = and(_T_5389, _T_5390) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5392 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5393 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5394 = and(_T_5392, _T_5393) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5395 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5396 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5397 = and(_T_5395, _T_5396) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5398 = or(_T_5394, _T_5397) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5399 = or(_T_5398, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5400 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5401 = and(_T_5399, _T_5400) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5402 = bits(_T_5401, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5403 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5402 : @[Reg.scala 28:19]
|
|
_T_5403 <= _T_5391 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][9] <= _T_5403 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5404 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5405 = eq(_T_5404, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5406 = and(ic_valid_ff, _T_5405) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5407 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5408 = and(_T_5406, _T_5407) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5409 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5410 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5411 = and(_T_5409, _T_5410) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5412 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5413 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5414 = and(_T_5412, _T_5413) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5415 = or(_T_5411, _T_5414) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5416 = or(_T_5415, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5417 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5418 = and(_T_5416, _T_5417) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5419 = bits(_T_5418, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5420 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5419 : @[Reg.scala 28:19]
|
|
_T_5420 <= _T_5408 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][10] <= _T_5420 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5422 = eq(_T_5421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5423 = and(ic_valid_ff, _T_5422) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5425 = and(_T_5423, _T_5424) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5426 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5428 = and(_T_5426, _T_5427) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5429 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5430 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5431 = and(_T_5429, _T_5430) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5432 = or(_T_5428, _T_5431) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5433 = or(_T_5432, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5434 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5435 = and(_T_5433, _T_5434) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5436 = bits(_T_5435, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5437 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5436 : @[Reg.scala 28:19]
|
|
_T_5437 <= _T_5425 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][11] <= _T_5437 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5438 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5439 = eq(_T_5438, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5440 = and(ic_valid_ff, _T_5439) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5441 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5442 = and(_T_5440, _T_5441) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5443 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5444 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5445 = and(_T_5443, _T_5444) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5446 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5447 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5448 = and(_T_5446, _T_5447) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5449 = or(_T_5445, _T_5448) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5450 = or(_T_5449, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5451 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5452 = and(_T_5450, _T_5451) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5453 = bits(_T_5452, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5454 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5453 : @[Reg.scala 28:19]
|
|
_T_5454 <= _T_5442 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][12] <= _T_5454 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5455 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5456 = eq(_T_5455, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5457 = and(ic_valid_ff, _T_5456) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5459 = and(_T_5457, _T_5458) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5460 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5461 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5462 = and(_T_5460, _T_5461) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5463 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5464 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5465 = and(_T_5463, _T_5464) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5466 = or(_T_5462, _T_5465) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5467 = or(_T_5466, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5468 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5469 = and(_T_5467, _T_5468) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5470 = bits(_T_5469, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5471 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5470 : @[Reg.scala 28:19]
|
|
_T_5471 <= _T_5459 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][13] <= _T_5471 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5472 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5473 = eq(_T_5472, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5474 = and(ic_valid_ff, _T_5473) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5475 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5476 = and(_T_5474, _T_5475) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5477 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5478 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5479 = and(_T_5477, _T_5478) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5480 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5481 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5482 = and(_T_5480, _T_5481) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5483 = or(_T_5479, _T_5482) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5484 = or(_T_5483, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5485 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5486 = and(_T_5484, _T_5485) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5487 = bits(_T_5486, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5488 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5487 : @[Reg.scala 28:19]
|
|
_T_5488 <= _T_5476 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][14] <= _T_5488 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5489 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5490 = eq(_T_5489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5491 = and(ic_valid_ff, _T_5490) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5492 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5493 = and(_T_5491, _T_5492) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5494 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5495 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5496 = and(_T_5494, _T_5495) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5497 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5498 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5499 = and(_T_5497, _T_5498) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5500 = or(_T_5496, _T_5499) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5501 = or(_T_5500, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5502 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5503 = and(_T_5501, _T_5502) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5504 = bits(_T_5503, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5505 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5504 : @[Reg.scala 28:19]
|
|
_T_5505 <= _T_5493 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][15] <= _T_5505 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5506 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5507 = eq(_T_5506, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5508 = and(ic_valid_ff, _T_5507) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5509 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5510 = and(_T_5508, _T_5509) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5511 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5512 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5513 = and(_T_5511, _T_5512) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5514 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5515 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5516 = and(_T_5514, _T_5515) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5517 = or(_T_5513, _T_5516) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5518 = or(_T_5517, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5519 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5520 = and(_T_5518, _T_5519) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5521 = bits(_T_5520, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5522 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5521 : @[Reg.scala 28:19]
|
|
_T_5522 <= _T_5510 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][16] <= _T_5522 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5523 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5524 = eq(_T_5523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5525 = and(ic_valid_ff, _T_5524) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5526 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5527 = and(_T_5525, _T_5526) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5528 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5529 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5530 = and(_T_5528, _T_5529) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5531 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5532 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5533 = and(_T_5531, _T_5532) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5534 = or(_T_5530, _T_5533) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5535 = or(_T_5534, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5536 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5537 = and(_T_5535, _T_5536) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5538 = bits(_T_5537, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5539 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5538 : @[Reg.scala 28:19]
|
|
_T_5539 <= _T_5527 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][17] <= _T_5539 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5540 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5541 = eq(_T_5540, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5542 = and(ic_valid_ff, _T_5541) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5544 = and(_T_5542, _T_5543) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5546 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5547 = and(_T_5545, _T_5546) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5548 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5549 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5550 = and(_T_5548, _T_5549) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5551 = or(_T_5547, _T_5550) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5552 = or(_T_5551, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5553 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5554 = and(_T_5552, _T_5553) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5555 = bits(_T_5554, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5556 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5555 : @[Reg.scala 28:19]
|
|
_T_5556 <= _T_5544 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][18] <= _T_5556 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5558 = eq(_T_5557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5559 = and(ic_valid_ff, _T_5558) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5561 = and(_T_5559, _T_5560) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5562 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5563 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5564 = and(_T_5562, _T_5563) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5565 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5566 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5567 = and(_T_5565, _T_5566) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5568 = or(_T_5564, _T_5567) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5569 = or(_T_5568, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5570 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5571 = and(_T_5569, _T_5570) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5572 = bits(_T_5571, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5573 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5572 : @[Reg.scala 28:19]
|
|
_T_5573 <= _T_5561 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][19] <= _T_5573 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5574 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5575 = eq(_T_5574, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5576 = and(ic_valid_ff, _T_5575) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5577 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5578 = and(_T_5576, _T_5577) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5579 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5580 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5581 = and(_T_5579, _T_5580) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5582 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5583 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5584 = and(_T_5582, _T_5583) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5585 = or(_T_5581, _T_5584) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5586 = or(_T_5585, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5587 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5588 = and(_T_5586, _T_5587) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5589 = bits(_T_5588, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5590 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5589 : @[Reg.scala 28:19]
|
|
_T_5590 <= _T_5578 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][20] <= _T_5590 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5591 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5592 = eq(_T_5591, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5593 = and(ic_valid_ff, _T_5592) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5594 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5595 = and(_T_5593, _T_5594) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5596 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5597 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5598 = and(_T_5596, _T_5597) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5599 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5600 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5601 = and(_T_5599, _T_5600) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5602 = or(_T_5598, _T_5601) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5603 = or(_T_5602, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5604 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5605 = and(_T_5603, _T_5604) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5606 = bits(_T_5605, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5607 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5606 : @[Reg.scala 28:19]
|
|
_T_5607 <= _T_5595 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][21] <= _T_5607 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5608 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5609 = eq(_T_5608, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5610 = and(ic_valid_ff, _T_5609) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5611 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5612 = and(_T_5610, _T_5611) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5613 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5614 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5615 = and(_T_5613, _T_5614) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5616 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5617 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5618 = and(_T_5616, _T_5617) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5619 = or(_T_5615, _T_5618) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5620 = or(_T_5619, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5621 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5622 = and(_T_5620, _T_5621) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5623 = bits(_T_5622, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5624 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5623 : @[Reg.scala 28:19]
|
|
_T_5624 <= _T_5612 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][22] <= _T_5624 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5625 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5626 = eq(_T_5625, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5627 = and(ic_valid_ff, _T_5626) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5629 = and(_T_5627, _T_5628) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5630 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5631 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5632 = and(_T_5630, _T_5631) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5633 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5634 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5635 = and(_T_5633, _T_5634) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5636 = or(_T_5632, _T_5635) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5637 = or(_T_5636, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5638 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5639 = and(_T_5637, _T_5638) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5640 = bits(_T_5639, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5641 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5640 : @[Reg.scala 28:19]
|
|
_T_5641 <= _T_5629 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][23] <= _T_5641 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5642 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5643 = eq(_T_5642, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5644 = and(ic_valid_ff, _T_5643) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5645 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5646 = and(_T_5644, _T_5645) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5647 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5648 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5649 = and(_T_5647, _T_5648) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5650 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5651 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5652 = and(_T_5650, _T_5651) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5653 = or(_T_5649, _T_5652) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5654 = or(_T_5653, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5655 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5656 = and(_T_5654, _T_5655) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5657 = bits(_T_5656, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5658 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5657 : @[Reg.scala 28:19]
|
|
_T_5658 <= _T_5646 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][24] <= _T_5658 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5659 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5660 = eq(_T_5659, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5661 = and(ic_valid_ff, _T_5660) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5662 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5663 = and(_T_5661, _T_5662) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5664 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5665 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5666 = and(_T_5664, _T_5665) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5667 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5668 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5669 = and(_T_5667, _T_5668) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5670 = or(_T_5666, _T_5669) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5671 = or(_T_5670, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5672 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5673 = and(_T_5671, _T_5672) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5674 = bits(_T_5673, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5675 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5674 : @[Reg.scala 28:19]
|
|
_T_5675 <= _T_5663 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][25] <= _T_5675 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5676 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5677 = eq(_T_5676, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5678 = and(ic_valid_ff, _T_5677) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5679 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5680 = and(_T_5678, _T_5679) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5681 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5682 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5683 = and(_T_5681, _T_5682) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5684 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5685 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5686 = and(_T_5684, _T_5685) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5687 = or(_T_5683, _T_5686) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5688 = or(_T_5687, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5689 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5690 = and(_T_5688, _T_5689) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5691 = bits(_T_5690, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5692 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5691 : @[Reg.scala 28:19]
|
|
_T_5692 <= _T_5680 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][26] <= _T_5692 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5694 = eq(_T_5693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5695 = and(ic_valid_ff, _T_5694) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5697 = and(_T_5695, _T_5696) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5699 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5700 = and(_T_5698, _T_5699) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5701 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5702 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5703 = and(_T_5701, _T_5702) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5704 = or(_T_5700, _T_5703) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5705 = or(_T_5704, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5706 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5707 = and(_T_5705, _T_5706) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5708 = bits(_T_5707, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5709 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5708 : @[Reg.scala 28:19]
|
|
_T_5709 <= _T_5697 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][27] <= _T_5709 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5710 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5711 = eq(_T_5710, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5712 = and(ic_valid_ff, _T_5711) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5714 = and(_T_5712, _T_5713) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5715 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5716 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5717 = and(_T_5715, _T_5716) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5718 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5719 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5720 = and(_T_5718, _T_5719) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5721 = or(_T_5717, _T_5720) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5722 = or(_T_5721, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5723 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5724 = and(_T_5722, _T_5723) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5725 = bits(_T_5724, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5726 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5725 : @[Reg.scala 28:19]
|
|
_T_5726 <= _T_5714 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][28] <= _T_5726 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5727 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5728 = eq(_T_5727, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5729 = and(ic_valid_ff, _T_5728) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5730 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5731 = and(_T_5729, _T_5730) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5732 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5733 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5734 = and(_T_5732, _T_5733) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5735 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5736 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5737 = and(_T_5735, _T_5736) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5738 = or(_T_5734, _T_5737) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5739 = or(_T_5738, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5740 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5741 = and(_T_5739, _T_5740) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5742 = bits(_T_5741, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5743 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5742 : @[Reg.scala 28:19]
|
|
_T_5743 <= _T_5731 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][29] <= _T_5743 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5744 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5745 = eq(_T_5744, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5746 = and(ic_valid_ff, _T_5745) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5747 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5748 = and(_T_5746, _T_5747) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5749 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5750 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5751 = and(_T_5749, _T_5750) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5752 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5753 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5754 = and(_T_5752, _T_5753) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5755 = or(_T_5751, _T_5754) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5756 = or(_T_5755, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5757 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5758 = and(_T_5756, _T_5757) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5759 = bits(_T_5758, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5760 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5759 : @[Reg.scala 28:19]
|
|
_T_5760 <= _T_5748 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][30] <= _T_5760 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5761 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5762 = eq(_T_5761, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5763 = and(ic_valid_ff, _T_5762) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5764 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5765 = and(_T_5763, _T_5764) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5766 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5767 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5768 = and(_T_5766, _T_5767) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5769 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5770 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5771 = and(_T_5769, _T_5770) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5772 = or(_T_5768, _T_5771) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5773 = or(_T_5772, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5774 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5775 = and(_T_5773, _T_5774) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5776 = bits(_T_5775, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5777 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5776 : @[Reg.scala 28:19]
|
|
_T_5777 <= _T_5765 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][31] <= _T_5777 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5778 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5779 = eq(_T_5778, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5780 = and(ic_valid_ff, _T_5779) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5781 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5782 = and(_T_5780, _T_5781) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5783 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5784 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5785 = and(_T_5783, _T_5784) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5786 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5787 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5788 = and(_T_5786, _T_5787) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5789 = or(_T_5785, _T_5788) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5790 = or(_T_5789, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5791 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5792 = and(_T_5790, _T_5791) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5793 = bits(_T_5792, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5794 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5793 : @[Reg.scala 28:19]
|
|
_T_5794 <= _T_5782 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][0] <= _T_5794 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5795 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5797 = and(ic_valid_ff, _T_5796) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5802 = and(_T_5800, _T_5801) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5803 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5804 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5805 = and(_T_5803, _T_5804) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5806 = or(_T_5802, _T_5805) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5807 = or(_T_5806, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5808 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5809 = and(_T_5807, _T_5808) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5810 = bits(_T_5809, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5811 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5810 : @[Reg.scala 28:19]
|
|
_T_5811 <= _T_5799 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][1] <= _T_5811 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5812 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5813 = eq(_T_5812, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5814 = and(ic_valid_ff, _T_5813) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5815 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5816 = and(_T_5814, _T_5815) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5817 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5818 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5819 = and(_T_5817, _T_5818) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5820 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5821 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5822 = and(_T_5820, _T_5821) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5823 = or(_T_5819, _T_5822) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5824 = or(_T_5823, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5825 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5826 = and(_T_5824, _T_5825) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5827 = bits(_T_5826, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5828 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5827 : @[Reg.scala 28:19]
|
|
_T_5828 <= _T_5816 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][2] <= _T_5828 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5830 = eq(_T_5829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5831 = and(ic_valid_ff, _T_5830) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5833 = and(_T_5831, _T_5832) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5834 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5836 = and(_T_5834, _T_5835) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5837 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5838 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5839 = and(_T_5837, _T_5838) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5840 = or(_T_5836, _T_5839) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5841 = or(_T_5840, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5842 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5843 = and(_T_5841, _T_5842) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5844 = bits(_T_5843, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5845 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5844 : @[Reg.scala 28:19]
|
|
_T_5845 <= _T_5833 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][3] <= _T_5845 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5846 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5847 = eq(_T_5846, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5848 = and(ic_valid_ff, _T_5847) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5849 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5850 = and(_T_5848, _T_5849) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5851 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5852 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5853 = and(_T_5851, _T_5852) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5854 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5855 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5856 = and(_T_5854, _T_5855) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5857 = or(_T_5853, _T_5856) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5858 = or(_T_5857, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5859 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5860 = and(_T_5858, _T_5859) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5861 = bits(_T_5860, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5862 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5861 : @[Reg.scala 28:19]
|
|
_T_5862 <= _T_5850 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][4] <= _T_5862 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5863 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5864 = eq(_T_5863, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5865 = and(ic_valid_ff, _T_5864) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5866 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5867 = and(_T_5865, _T_5866) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5868 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5869 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5870 = and(_T_5868, _T_5869) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5871 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5872 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5873 = and(_T_5871, _T_5872) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5874 = or(_T_5870, _T_5873) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5875 = or(_T_5874, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5876 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5877 = and(_T_5875, _T_5876) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5878 = bits(_T_5877, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5879 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5878 : @[Reg.scala 28:19]
|
|
_T_5879 <= _T_5867 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][5] <= _T_5879 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5880 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5881 = eq(_T_5880, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5882 = and(ic_valid_ff, _T_5881) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5884 = and(_T_5882, _T_5883) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5885 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5887 = and(_T_5885, _T_5886) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5888 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5889 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5890 = and(_T_5888, _T_5889) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5891 = or(_T_5887, _T_5890) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5892 = or(_T_5891, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5893 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5894 = and(_T_5892, _T_5893) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5895 = bits(_T_5894, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5896 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5895 : @[Reg.scala 28:19]
|
|
_T_5896 <= _T_5884 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][6] <= _T_5896 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5897 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5898 = eq(_T_5897, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5899 = and(ic_valid_ff, _T_5898) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5900 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5901 = and(_T_5899, _T_5900) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5902 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5903 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5904 = and(_T_5902, _T_5903) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5905 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5906 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5907 = and(_T_5905, _T_5906) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5908 = or(_T_5904, _T_5907) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5909 = or(_T_5908, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5910 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5911 = and(_T_5909, _T_5910) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5912 = bits(_T_5911, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5913 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5912 : @[Reg.scala 28:19]
|
|
_T_5913 <= _T_5901 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][7] <= _T_5913 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5914 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5915 = eq(_T_5914, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5916 = and(ic_valid_ff, _T_5915) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5917 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5918 = and(_T_5916, _T_5917) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5919 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5920 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5921 = and(_T_5919, _T_5920) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5922 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5923 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5924 = and(_T_5922, _T_5923) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5925 = or(_T_5921, _T_5924) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5926 = or(_T_5925, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5927 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5928 = and(_T_5926, _T_5927) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5929 = bits(_T_5928, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5930 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5929 : @[Reg.scala 28:19]
|
|
_T_5930 <= _T_5918 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][8] <= _T_5930 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5931 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5932 = eq(_T_5931, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5933 = and(ic_valid_ff, _T_5932) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5934 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5935 = and(_T_5933, _T_5934) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5936 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5937 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5938 = and(_T_5936, _T_5937) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5939 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5940 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5941 = and(_T_5939, _T_5940) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5942 = or(_T_5938, _T_5941) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5943 = or(_T_5942, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5944 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5945 = and(_T_5943, _T_5944) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5946 = bits(_T_5945, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5947 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5946 : @[Reg.scala 28:19]
|
|
_T_5947 <= _T_5935 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][9] <= _T_5947 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5948 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5949 = eq(_T_5948, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5950 = and(ic_valid_ff, _T_5949) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5951 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5952 = and(_T_5950, _T_5951) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5953 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5954 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5955 = and(_T_5953, _T_5954) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5956 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5957 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5958 = and(_T_5956, _T_5957) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5959 = or(_T_5955, _T_5958) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5960 = or(_T_5959, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5961 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5962 = and(_T_5960, _T_5961) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5963 = bits(_T_5962, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5964 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5963 : @[Reg.scala 28:19]
|
|
_T_5964 <= _T_5952 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][10] <= _T_5964 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5966 = eq(_T_5965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5967 = and(ic_valid_ff, _T_5966) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5969 = and(_T_5967, _T_5968) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5970 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5972 = and(_T_5970, _T_5971) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5973 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5974 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5975 = and(_T_5973, _T_5974) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5976 = or(_T_5972, _T_5975) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5977 = or(_T_5976, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5978 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5979 = and(_T_5977, _T_5978) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5980 = bits(_T_5979, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5981 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5980 : @[Reg.scala 28:19]
|
|
_T_5981 <= _T_5969 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][11] <= _T_5981 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5982 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_5983 = eq(_T_5982, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_5984 = and(ic_valid_ff, _T_5983) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_5985 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_5986 = and(_T_5984, _T_5985) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_5987 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_5988 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_5989 = and(_T_5987, _T_5988) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_5990 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_5991 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_5992 = and(_T_5990, _T_5991) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_5993 = or(_T_5989, _T_5992) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_5994 = or(_T_5993, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_5995 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_5996 = and(_T_5994, _T_5995) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_5997 = bits(_T_5996, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_5998 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5997 : @[Reg.scala 28:19]
|
|
_T_5998 <= _T_5986 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][12] <= _T_5998 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_5999 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6000 = eq(_T_5999, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6001 = and(ic_valid_ff, _T_6000) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6002 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6003 = and(_T_6001, _T_6002) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6004 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6005 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6006 = and(_T_6004, _T_6005) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6007 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6008 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6009 = and(_T_6007, _T_6008) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6010 = or(_T_6006, _T_6009) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6011 = or(_T_6010, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6012 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6013 = and(_T_6011, _T_6012) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6014 = bits(_T_6013, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6015 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6014 : @[Reg.scala 28:19]
|
|
_T_6015 <= _T_6003 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][13] <= _T_6015 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6016 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6017 = eq(_T_6016, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6018 = and(ic_valid_ff, _T_6017) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6019 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6020 = and(_T_6018, _T_6019) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6021 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6022 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6023 = and(_T_6021, _T_6022) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6024 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6025 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6026 = and(_T_6024, _T_6025) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6027 = or(_T_6023, _T_6026) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6028 = or(_T_6027, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6029 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6030 = and(_T_6028, _T_6029) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6031 = bits(_T_6030, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6032 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6031 : @[Reg.scala 28:19]
|
|
_T_6032 <= _T_6020 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][14] <= _T_6032 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6033 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6034 = eq(_T_6033, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6035 = and(ic_valid_ff, _T_6034) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6036 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6037 = and(_T_6035, _T_6036) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6038 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6039 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6040 = and(_T_6038, _T_6039) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6041 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6042 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6043 = and(_T_6041, _T_6042) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6044 = or(_T_6040, _T_6043) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6045 = or(_T_6044, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6046 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6047 = and(_T_6045, _T_6046) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6048 = bits(_T_6047, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6049 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6048 : @[Reg.scala 28:19]
|
|
_T_6049 <= _T_6037 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][15] <= _T_6049 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6050 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6051 = eq(_T_6050, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6052 = and(ic_valid_ff, _T_6051) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6053 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6054 = and(_T_6052, _T_6053) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6055 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6056 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6057 = and(_T_6055, _T_6056) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6058 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6059 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6060 = and(_T_6058, _T_6059) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6061 = or(_T_6057, _T_6060) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6062 = or(_T_6061, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6063 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6064 = and(_T_6062, _T_6063) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6065 = bits(_T_6064, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6066 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6065 : @[Reg.scala 28:19]
|
|
_T_6066 <= _T_6054 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][16] <= _T_6066 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6067 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6068 = eq(_T_6067, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6069 = and(ic_valid_ff, _T_6068) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6070 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6071 = and(_T_6069, _T_6070) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6072 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6073 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6074 = and(_T_6072, _T_6073) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6075 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6076 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6077 = and(_T_6075, _T_6076) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6078 = or(_T_6074, _T_6077) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6079 = or(_T_6078, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6080 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6081 = and(_T_6079, _T_6080) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6082 = bits(_T_6081, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6083 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6082 : @[Reg.scala 28:19]
|
|
_T_6083 <= _T_6071 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][17] <= _T_6083 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6084 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6085 = eq(_T_6084, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6086 = and(ic_valid_ff, _T_6085) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6087 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6088 = and(_T_6086, _T_6087) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6089 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6090 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6091 = and(_T_6089, _T_6090) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6092 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6093 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6094 = and(_T_6092, _T_6093) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6095 = or(_T_6091, _T_6094) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6096 = or(_T_6095, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6097 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6098 = and(_T_6096, _T_6097) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6099 = bits(_T_6098, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6100 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6099 : @[Reg.scala 28:19]
|
|
_T_6100 <= _T_6088 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][18] <= _T_6100 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6101 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6102 = eq(_T_6101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6103 = and(ic_valid_ff, _T_6102) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6104 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6105 = and(_T_6103, _T_6104) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6106 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6107 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6108 = and(_T_6106, _T_6107) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6109 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6110 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6111 = and(_T_6109, _T_6110) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6112 = or(_T_6108, _T_6111) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6113 = or(_T_6112, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6114 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6115 = and(_T_6113, _T_6114) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6116 = bits(_T_6115, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6117 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6116 : @[Reg.scala 28:19]
|
|
_T_6117 <= _T_6105 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][19] <= _T_6117 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6118 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6119 = eq(_T_6118, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6120 = and(ic_valid_ff, _T_6119) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6121 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6122 = and(_T_6120, _T_6121) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6123 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6124 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6125 = and(_T_6123, _T_6124) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6126 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6127 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6128 = and(_T_6126, _T_6127) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6129 = or(_T_6125, _T_6128) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6130 = or(_T_6129, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6131 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6132 = and(_T_6130, _T_6131) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6133 = bits(_T_6132, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6134 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6133 : @[Reg.scala 28:19]
|
|
_T_6134 <= _T_6122 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][20] <= _T_6134 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6135 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6136 = eq(_T_6135, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6137 = and(ic_valid_ff, _T_6136) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6138 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6139 = and(_T_6137, _T_6138) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6140 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6141 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6142 = and(_T_6140, _T_6141) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6143 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6144 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6145 = and(_T_6143, _T_6144) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6146 = or(_T_6142, _T_6145) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6147 = or(_T_6146, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6148 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6149 = and(_T_6147, _T_6148) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6150 = bits(_T_6149, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6151 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6150 : @[Reg.scala 28:19]
|
|
_T_6151 <= _T_6139 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][21] <= _T_6151 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6152 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6153 = eq(_T_6152, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6154 = and(ic_valid_ff, _T_6153) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6155 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6156 = and(_T_6154, _T_6155) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6157 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6158 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6159 = and(_T_6157, _T_6158) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6160 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6161 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6162 = and(_T_6160, _T_6161) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6163 = or(_T_6159, _T_6162) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6164 = or(_T_6163, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6165 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6166 = and(_T_6164, _T_6165) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6167 = bits(_T_6166, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6168 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6167 : @[Reg.scala 28:19]
|
|
_T_6168 <= _T_6156 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][22] <= _T_6168 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6169 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6170 = eq(_T_6169, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6171 = and(ic_valid_ff, _T_6170) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6172 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6173 = and(_T_6171, _T_6172) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6174 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6175 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6176 = and(_T_6174, _T_6175) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6177 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6178 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6179 = and(_T_6177, _T_6178) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6180 = or(_T_6176, _T_6179) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6181 = or(_T_6180, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6182 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6184 = bits(_T_6183, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6185 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6184 : @[Reg.scala 28:19]
|
|
_T_6185 <= _T_6173 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][23] <= _T_6185 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6186 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6187 = eq(_T_6186, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6188 = and(ic_valid_ff, _T_6187) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6189 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6190 = and(_T_6188, _T_6189) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6191 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6192 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6193 = and(_T_6191, _T_6192) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6194 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6195 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6196 = and(_T_6194, _T_6195) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6197 = or(_T_6193, _T_6196) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6198 = or(_T_6197, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6199 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6200 = and(_T_6198, _T_6199) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6201 = bits(_T_6200, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6202 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6201 : @[Reg.scala 28:19]
|
|
_T_6202 <= _T_6190 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][24] <= _T_6202 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6203 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6204 = eq(_T_6203, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6205 = and(ic_valid_ff, _T_6204) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6206 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6207 = and(_T_6205, _T_6206) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6208 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6209 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6210 = and(_T_6208, _T_6209) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6211 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6212 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6213 = and(_T_6211, _T_6212) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6214 = or(_T_6210, _T_6213) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6215 = or(_T_6214, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6216 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6217 = and(_T_6215, _T_6216) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6218 = bits(_T_6217, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6219 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6218 : @[Reg.scala 28:19]
|
|
_T_6219 <= _T_6207 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][25] <= _T_6219 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6220 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6221 = eq(_T_6220, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6222 = and(ic_valid_ff, _T_6221) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6223 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6224 = and(_T_6222, _T_6223) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6225 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6226 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6227 = and(_T_6225, _T_6226) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6228 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6229 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6230 = and(_T_6228, _T_6229) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6231 = or(_T_6227, _T_6230) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6232 = or(_T_6231, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6233 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6234 = and(_T_6232, _T_6233) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6235 = bits(_T_6234, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6236 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6235 : @[Reg.scala 28:19]
|
|
_T_6236 <= _T_6224 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][26] <= _T_6236 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6238 = eq(_T_6237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6239 = and(ic_valid_ff, _T_6238) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6241 = and(_T_6239, _T_6240) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6242 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6243 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6244 = and(_T_6242, _T_6243) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6245 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6246 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6247 = and(_T_6245, _T_6246) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6248 = or(_T_6244, _T_6247) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6249 = or(_T_6248, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6250 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6251 = and(_T_6249, _T_6250) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6252 = bits(_T_6251, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6253 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6252 : @[Reg.scala 28:19]
|
|
_T_6253 <= _T_6241 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][27] <= _T_6253 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6254 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6255 = eq(_T_6254, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6256 = and(ic_valid_ff, _T_6255) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6257 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6258 = and(_T_6256, _T_6257) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6259 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6260 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6261 = and(_T_6259, _T_6260) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6262 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6263 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6264 = and(_T_6262, _T_6263) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6265 = or(_T_6261, _T_6264) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6266 = or(_T_6265, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6267 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6268 = and(_T_6266, _T_6267) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6269 = bits(_T_6268, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6270 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6269 : @[Reg.scala 28:19]
|
|
_T_6270 <= _T_6258 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][28] <= _T_6270 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6271 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6272 = eq(_T_6271, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6273 = and(ic_valid_ff, _T_6272) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6274 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6275 = and(_T_6273, _T_6274) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6276 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6277 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6278 = and(_T_6276, _T_6277) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6279 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6280 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6281 = and(_T_6279, _T_6280) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6282 = or(_T_6278, _T_6281) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6283 = or(_T_6282, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6284 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6285 = and(_T_6283, _T_6284) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6286 = bits(_T_6285, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6287 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6286 : @[Reg.scala 28:19]
|
|
_T_6287 <= _T_6275 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][29] <= _T_6287 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6288 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6289 = eq(_T_6288, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6290 = and(ic_valid_ff, _T_6289) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6291 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6292 = and(_T_6290, _T_6291) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6293 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6294 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6295 = and(_T_6293, _T_6294) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6296 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6297 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6298 = and(_T_6296, _T_6297) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6299 = or(_T_6295, _T_6298) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6300 = or(_T_6299, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6301 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6302 = and(_T_6300, _T_6301) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6303 = bits(_T_6302, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6304 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6303 : @[Reg.scala 28:19]
|
|
_T_6304 <= _T_6292 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][30] <= _T_6304 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6305 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6306 = eq(_T_6305, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6307 = and(ic_valid_ff, _T_6306) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6309 = and(_T_6307, _T_6308) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6310 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6311 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6312 = and(_T_6310, _T_6311) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6313 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6314 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6315 = and(_T_6313, _T_6314) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6316 = or(_T_6312, _T_6315) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6317 = or(_T_6316, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6318 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6319 = and(_T_6317, _T_6318) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6320 = bits(_T_6319, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6321 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6320 : @[Reg.scala 28:19]
|
|
_T_6321 <= _T_6309 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][31] <= _T_6321 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6322 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6323 = eq(_T_6322, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6324 = and(ic_valid_ff, _T_6323) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6325 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6326 = and(_T_6324, _T_6325) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6327 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6328 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6329 = and(_T_6327, _T_6328) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6330 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6331 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6332 = and(_T_6330, _T_6331) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6333 = or(_T_6329, _T_6332) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6334 = or(_T_6333, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6335 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6336 = and(_T_6334, _T_6335) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6337 = bits(_T_6336, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6338 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6337 : @[Reg.scala 28:19]
|
|
_T_6338 <= _T_6326 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][32] <= _T_6338 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6339 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6340 = eq(_T_6339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6341 = and(ic_valid_ff, _T_6340) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6342 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6343 = and(_T_6341, _T_6342) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6344 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6345 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6346 = and(_T_6344, _T_6345) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6347 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6348 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6349 = and(_T_6347, _T_6348) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6350 = or(_T_6346, _T_6349) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6351 = or(_T_6350, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6352 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6353 = and(_T_6351, _T_6352) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6354 = bits(_T_6353, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6355 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6354 : @[Reg.scala 28:19]
|
|
_T_6355 <= _T_6343 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][33] <= _T_6355 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6356 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6357 = eq(_T_6356, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6358 = and(ic_valid_ff, _T_6357) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6359 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6360 = and(_T_6358, _T_6359) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6361 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6362 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6363 = and(_T_6361, _T_6362) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6364 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6365 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6366 = and(_T_6364, _T_6365) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6367 = or(_T_6363, _T_6366) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6368 = or(_T_6367, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6369 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6370 = and(_T_6368, _T_6369) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6371 = bits(_T_6370, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6372 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6371 : @[Reg.scala 28:19]
|
|
_T_6372 <= _T_6360 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][34] <= _T_6372 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6373 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6374 = eq(_T_6373, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6375 = and(ic_valid_ff, _T_6374) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6376 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6377 = and(_T_6375, _T_6376) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6378 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6379 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6380 = and(_T_6378, _T_6379) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6381 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6382 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6383 = and(_T_6381, _T_6382) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6384 = or(_T_6380, _T_6383) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6385 = or(_T_6384, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6386 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6387 = and(_T_6385, _T_6386) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6388 = bits(_T_6387, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6389 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6388 : @[Reg.scala 28:19]
|
|
_T_6389 <= _T_6377 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][35] <= _T_6389 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6390 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6391 = eq(_T_6390, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6392 = and(ic_valid_ff, _T_6391) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6394 = and(_T_6392, _T_6393) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6395 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6396 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6397 = and(_T_6395, _T_6396) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6398 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6399 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6400 = and(_T_6398, _T_6399) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6401 = or(_T_6397, _T_6400) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6402 = or(_T_6401, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6403 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6404 = and(_T_6402, _T_6403) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6405 = bits(_T_6404, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6406 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6405 : @[Reg.scala 28:19]
|
|
_T_6406 <= _T_6394 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][36] <= _T_6406 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6407 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6408 = eq(_T_6407, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6409 = and(ic_valid_ff, _T_6408) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6410 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6411 = and(_T_6409, _T_6410) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6412 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6413 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6414 = and(_T_6412, _T_6413) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6415 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6416 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6417 = and(_T_6415, _T_6416) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6418 = or(_T_6414, _T_6417) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6419 = or(_T_6418, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6420 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6421 = and(_T_6419, _T_6420) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6422 = bits(_T_6421, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6423 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6422 : @[Reg.scala 28:19]
|
|
_T_6423 <= _T_6411 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][37] <= _T_6423 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6424 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6425 = eq(_T_6424, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6426 = and(ic_valid_ff, _T_6425) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6427 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6428 = and(_T_6426, _T_6427) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6429 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6431 = and(_T_6429, _T_6430) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6432 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6433 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6434 = and(_T_6432, _T_6433) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6435 = or(_T_6431, _T_6434) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6436 = or(_T_6435, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6437 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6438 = and(_T_6436, _T_6437) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6439 = bits(_T_6438, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6440 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6439 : @[Reg.scala 28:19]
|
|
_T_6440 <= _T_6428 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][38] <= _T_6440 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6441 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6442 = eq(_T_6441, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6443 = and(ic_valid_ff, _T_6442) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6444 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6445 = and(_T_6443, _T_6444) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6446 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6447 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6448 = and(_T_6446, _T_6447) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6449 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6450 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6451 = and(_T_6449, _T_6450) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6452 = or(_T_6448, _T_6451) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6453 = or(_T_6452, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6454 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6455 = and(_T_6453, _T_6454) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6456 = bits(_T_6455, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6457 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6456 : @[Reg.scala 28:19]
|
|
_T_6457 <= _T_6445 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][39] <= _T_6457 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6458 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6459 = eq(_T_6458, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6460 = and(ic_valid_ff, _T_6459) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6461 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6462 = and(_T_6460, _T_6461) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6464 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6465 = and(_T_6463, _T_6464) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6466 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6467 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6468 = and(_T_6466, _T_6467) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6469 = or(_T_6465, _T_6468) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6470 = or(_T_6469, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6471 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6472 = and(_T_6470, _T_6471) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6473 = bits(_T_6472, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6474 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6473 : @[Reg.scala 28:19]
|
|
_T_6474 <= _T_6462 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][40] <= _T_6474 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6475 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6476 = eq(_T_6475, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6477 = and(ic_valid_ff, _T_6476) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6479 = and(_T_6477, _T_6478) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6480 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6481 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6482 = and(_T_6480, _T_6481) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6483 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6484 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6485 = and(_T_6483, _T_6484) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6486 = or(_T_6482, _T_6485) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6487 = or(_T_6486, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6488 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6489 = and(_T_6487, _T_6488) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6490 = bits(_T_6489, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6491 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6490 : @[Reg.scala 28:19]
|
|
_T_6491 <= _T_6479 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][41] <= _T_6491 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6492 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6493 = eq(_T_6492, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6494 = and(ic_valid_ff, _T_6493) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6495 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6496 = and(_T_6494, _T_6495) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6498 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6499 = and(_T_6497, _T_6498) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6500 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6501 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6502 = and(_T_6500, _T_6501) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6503 = or(_T_6499, _T_6502) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6504 = or(_T_6503, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6505 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6506 = and(_T_6504, _T_6505) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6507 = bits(_T_6506, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6508 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6507 : @[Reg.scala 28:19]
|
|
_T_6508 <= _T_6496 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][42] <= _T_6508 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6510 = eq(_T_6509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6511 = and(ic_valid_ff, _T_6510) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6513 = and(_T_6511, _T_6512) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6514 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6516 = and(_T_6514, _T_6515) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6517 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6518 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6520 = or(_T_6516, _T_6519) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6521 = or(_T_6520, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6522 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6523 = and(_T_6521, _T_6522) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6524 = bits(_T_6523, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6525 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6524 : @[Reg.scala 28:19]
|
|
_T_6525 <= _T_6513 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][43] <= _T_6525 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6526 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6527 = eq(_T_6526, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6528 = and(ic_valid_ff, _T_6527) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6529 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6530 = and(_T_6528, _T_6529) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6531 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6532 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6533 = and(_T_6531, _T_6532) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6534 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6535 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6536 = and(_T_6534, _T_6535) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6537 = or(_T_6533, _T_6536) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6538 = or(_T_6537, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6539 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6540 = and(_T_6538, _T_6539) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6541 = bits(_T_6540, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6542 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6541 : @[Reg.scala 28:19]
|
|
_T_6542 <= _T_6530 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][44] <= _T_6542 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6543 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6544 = eq(_T_6543, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6545 = and(ic_valid_ff, _T_6544) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6546 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6547 = and(_T_6545, _T_6546) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6548 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6549 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6550 = and(_T_6548, _T_6549) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6551 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6552 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6553 = and(_T_6551, _T_6552) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6554 = or(_T_6550, _T_6553) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6555 = or(_T_6554, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6556 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6557 = and(_T_6555, _T_6556) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6558 = bits(_T_6557, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6559 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6558 : @[Reg.scala 28:19]
|
|
_T_6559 <= _T_6547 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][45] <= _T_6559 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6560 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6561 = eq(_T_6560, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6562 = and(ic_valid_ff, _T_6561) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6563 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6564 = and(_T_6562, _T_6563) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6567 = and(_T_6565, _T_6566) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6568 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6569 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6570 = and(_T_6568, _T_6569) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6571 = or(_T_6567, _T_6570) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6572 = or(_T_6571, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6573 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6574 = and(_T_6572, _T_6573) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6575 = bits(_T_6574, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6576 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6575 : @[Reg.scala 28:19]
|
|
_T_6576 <= _T_6564 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][46] <= _T_6576 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6577 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6578 = eq(_T_6577, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6579 = and(ic_valid_ff, _T_6578) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6580 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6581 = and(_T_6579, _T_6580) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6582 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6583 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6584 = and(_T_6582, _T_6583) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6585 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6586 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6587 = and(_T_6585, _T_6586) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6588 = or(_T_6584, _T_6587) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6589 = or(_T_6588, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6590 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6591 = and(_T_6589, _T_6590) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6592 = bits(_T_6591, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6593 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6592 : @[Reg.scala 28:19]
|
|
_T_6593 <= _T_6581 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][47] <= _T_6593 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6594 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6595 = eq(_T_6594, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6596 = and(ic_valid_ff, _T_6595) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6597 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6598 = and(_T_6596, _T_6597) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6599 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6600 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6601 = and(_T_6599, _T_6600) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6602 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6603 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6604 = and(_T_6602, _T_6603) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6605 = or(_T_6601, _T_6604) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6606 = or(_T_6605, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6607 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6608 = and(_T_6606, _T_6607) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6609 = bits(_T_6608, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6610 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6609 : @[Reg.scala 28:19]
|
|
_T_6610 <= _T_6598 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][48] <= _T_6610 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6611 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6612 = eq(_T_6611, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6613 = and(ic_valid_ff, _T_6612) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6614 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6615 = and(_T_6613, _T_6614) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6616 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6617 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6618 = and(_T_6616, _T_6617) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6619 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6620 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6621 = and(_T_6619, _T_6620) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6622 = or(_T_6618, _T_6621) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6623 = or(_T_6622, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6624 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6625 = and(_T_6623, _T_6624) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6626 = bits(_T_6625, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6627 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6626 : @[Reg.scala 28:19]
|
|
_T_6627 <= _T_6615 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][49] <= _T_6627 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6628 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6629 = eq(_T_6628, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6630 = and(ic_valid_ff, _T_6629) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6631 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6632 = and(_T_6630, _T_6631) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6633 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6634 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6635 = and(_T_6633, _T_6634) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6636 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6637 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6638 = and(_T_6636, _T_6637) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6639 = or(_T_6635, _T_6638) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6640 = or(_T_6639, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6641 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6642 = and(_T_6640, _T_6641) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6643 = bits(_T_6642, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6644 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6643 : @[Reg.scala 28:19]
|
|
_T_6644 <= _T_6632 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][50] <= _T_6644 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6645 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6646 = eq(_T_6645, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6647 = and(ic_valid_ff, _T_6646) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6649 = and(_T_6647, _T_6648) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6650 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6651 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6652 = and(_T_6650, _T_6651) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6653 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6654 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6655 = and(_T_6653, _T_6654) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6656 = or(_T_6652, _T_6655) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6657 = or(_T_6656, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6658 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6659 = and(_T_6657, _T_6658) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6660 = bits(_T_6659, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6661 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6660 : @[Reg.scala 28:19]
|
|
_T_6661 <= _T_6649 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][51] <= _T_6661 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6662 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6663 = eq(_T_6662, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6664 = and(ic_valid_ff, _T_6663) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6665 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6666 = and(_T_6664, _T_6665) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6667 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6668 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6669 = and(_T_6667, _T_6668) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6670 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6671 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6672 = and(_T_6670, _T_6671) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6673 = or(_T_6669, _T_6672) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6674 = or(_T_6673, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6675 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6676 = and(_T_6674, _T_6675) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6677 = bits(_T_6676, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6678 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6677 : @[Reg.scala 28:19]
|
|
_T_6678 <= _T_6666 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][52] <= _T_6678 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6679 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6680 = eq(_T_6679, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6681 = and(ic_valid_ff, _T_6680) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6682 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6683 = and(_T_6681, _T_6682) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6684 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6685 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6686 = and(_T_6684, _T_6685) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6687 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6688 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6689 = and(_T_6687, _T_6688) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6690 = or(_T_6686, _T_6689) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6691 = or(_T_6690, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6692 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6693 = and(_T_6691, _T_6692) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6694 = bits(_T_6693, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6695 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6694 : @[Reg.scala 28:19]
|
|
_T_6695 <= _T_6683 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][53] <= _T_6695 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6696 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6697 = eq(_T_6696, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6698 = and(ic_valid_ff, _T_6697) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6699 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6700 = and(_T_6698, _T_6699) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6701 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6702 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6703 = and(_T_6701, _T_6702) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6704 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6705 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6706 = and(_T_6704, _T_6705) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6707 = or(_T_6703, _T_6706) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6708 = or(_T_6707, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6709 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6710 = and(_T_6708, _T_6709) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6712 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6711 : @[Reg.scala 28:19]
|
|
_T_6712 <= _T_6700 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][54] <= _T_6712 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6713 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6714 = eq(_T_6713, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6715 = and(ic_valid_ff, _T_6714) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6716 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6717 = and(_T_6715, _T_6716) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6718 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6719 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6720 = and(_T_6718, _T_6719) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6721 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6722 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6723 = and(_T_6721, _T_6722) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6724 = or(_T_6720, _T_6723) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6725 = or(_T_6724, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6726 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6727 = and(_T_6725, _T_6726) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6728 = bits(_T_6727, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6729 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6728 : @[Reg.scala 28:19]
|
|
_T_6729 <= _T_6717 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][55] <= _T_6729 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6730 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6731 = eq(_T_6730, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6732 = and(ic_valid_ff, _T_6731) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6733 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6734 = and(_T_6732, _T_6733) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6735 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6736 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6737 = and(_T_6735, _T_6736) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6738 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6739 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6740 = and(_T_6738, _T_6739) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6741 = or(_T_6737, _T_6740) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6742 = or(_T_6741, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6743 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6744 = and(_T_6742, _T_6743) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6745 = bits(_T_6744, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6746 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6745 : @[Reg.scala 28:19]
|
|
_T_6746 <= _T_6734 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][56] <= _T_6746 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6747 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6748 = eq(_T_6747, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6749 = and(ic_valid_ff, _T_6748) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6750 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6751 = and(_T_6749, _T_6750) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6752 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6753 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6754 = and(_T_6752, _T_6753) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6755 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6756 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6757 = and(_T_6755, _T_6756) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6758 = or(_T_6754, _T_6757) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6759 = or(_T_6758, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6760 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6761 = and(_T_6759, _T_6760) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6762 = bits(_T_6761, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6763 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6762 : @[Reg.scala 28:19]
|
|
_T_6763 <= _T_6751 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][57] <= _T_6763 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6764 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6765 = eq(_T_6764, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6766 = and(ic_valid_ff, _T_6765) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6767 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6768 = and(_T_6766, _T_6767) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6769 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6770 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6771 = and(_T_6769, _T_6770) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6772 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6773 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6774 = and(_T_6772, _T_6773) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6775 = or(_T_6771, _T_6774) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6776 = or(_T_6775, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6777 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6778 = and(_T_6776, _T_6777) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6779 = bits(_T_6778, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6780 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6779 : @[Reg.scala 28:19]
|
|
_T_6780 <= _T_6768 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][58] <= _T_6780 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6782 = eq(_T_6781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6783 = and(ic_valid_ff, _T_6782) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6785 = and(_T_6783, _T_6784) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6787 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6788 = and(_T_6786, _T_6787) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6789 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6790 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6791 = and(_T_6789, _T_6790) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6792 = or(_T_6788, _T_6791) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6793 = or(_T_6792, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6794 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6795 = and(_T_6793, _T_6794) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6796 = bits(_T_6795, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6797 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6796 : @[Reg.scala 28:19]
|
|
_T_6797 <= _T_6785 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][59] <= _T_6797 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6798 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6799 = eq(_T_6798, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6800 = and(ic_valid_ff, _T_6799) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6801 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6802 = and(_T_6800, _T_6801) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6803 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6804 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6805 = and(_T_6803, _T_6804) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6806 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6807 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6808 = and(_T_6806, _T_6807) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6809 = or(_T_6805, _T_6808) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6810 = or(_T_6809, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6811 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6812 = and(_T_6810, _T_6811) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6813 = bits(_T_6812, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6814 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6813 : @[Reg.scala 28:19]
|
|
_T_6814 <= _T_6802 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][60] <= _T_6814 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6815 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6816 = eq(_T_6815, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6817 = and(ic_valid_ff, _T_6816) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6818 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6819 = and(_T_6817, _T_6818) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6821 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6822 = and(_T_6820, _T_6821) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6823 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6824 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6825 = and(_T_6823, _T_6824) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6826 = or(_T_6822, _T_6825) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6827 = or(_T_6826, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6828 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6829 = and(_T_6827, _T_6828) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6830 = bits(_T_6829, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6831 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6830 : @[Reg.scala 28:19]
|
|
_T_6831 <= _T_6819 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][61] <= _T_6831 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6832 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6833 = eq(_T_6832, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6834 = and(ic_valid_ff, _T_6833) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6835 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6836 = and(_T_6834, _T_6835) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6837 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6838 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6839 = and(_T_6837, _T_6838) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6840 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6841 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6842 = and(_T_6840, _T_6841) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6843 = or(_T_6839, _T_6842) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6844 = or(_T_6843, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6845 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6846 = and(_T_6844, _T_6845) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6847 = bits(_T_6846, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6848 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6847 : @[Reg.scala 28:19]
|
|
_T_6848 <= _T_6836 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][62] <= _T_6848 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6849 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6850 = eq(_T_6849, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6851 = and(ic_valid_ff, _T_6850) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6852 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6853 = and(_T_6851, _T_6852) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6854 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6855 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6856 = and(_T_6854, _T_6855) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6857 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6858 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6859 = and(_T_6857, _T_6858) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6860 = or(_T_6856, _T_6859) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6861 = or(_T_6860, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6862 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6863 = and(_T_6861, _T_6862) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6865 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6864 : @[Reg.scala 28:19]
|
|
_T_6865 <= _T_6853 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][63] <= _T_6865 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6866 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6867 = eq(_T_6866, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6868 = and(ic_valid_ff, _T_6867) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6869 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6870 = and(_T_6868, _T_6869) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6871 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6872 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6873 = and(_T_6871, _T_6872) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6874 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6875 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6876 = and(_T_6874, _T_6875) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6877 = or(_T_6873, _T_6876) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6878 = or(_T_6877, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6879 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6880 = and(_T_6878, _T_6879) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6881 = bits(_T_6880, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6882 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6881 : @[Reg.scala 28:19]
|
|
_T_6882 <= _T_6870 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][32] <= _T_6882 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6883 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6884 = eq(_T_6883, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6885 = and(ic_valid_ff, _T_6884) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6886 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6887 = and(_T_6885, _T_6886) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6888 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6889 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6890 = and(_T_6888, _T_6889) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6891 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6892 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6893 = and(_T_6891, _T_6892) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6894 = or(_T_6890, _T_6893) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6895 = or(_T_6894, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6896 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6897 = and(_T_6895, _T_6896) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6898 = bits(_T_6897, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6899 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6898 : @[Reg.scala 28:19]
|
|
_T_6899 <= _T_6887 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][33] <= _T_6899 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6900 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6901 = eq(_T_6900, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6902 = and(ic_valid_ff, _T_6901) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6904 = and(_T_6902, _T_6903) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6905 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6906 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6907 = and(_T_6905, _T_6906) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6908 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6909 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6910 = and(_T_6908, _T_6909) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6911 = or(_T_6907, _T_6910) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6912 = or(_T_6911, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6913 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6914 = and(_T_6912, _T_6913) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6915 = bits(_T_6914, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6916 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6915 : @[Reg.scala 28:19]
|
|
_T_6916 <= _T_6904 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][34] <= _T_6916 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6917 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6918 = eq(_T_6917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6919 = and(ic_valid_ff, _T_6918) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6920 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6921 = and(_T_6919, _T_6920) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6922 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6923 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6924 = and(_T_6922, _T_6923) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6925 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6926 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6927 = and(_T_6925, _T_6926) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6928 = or(_T_6924, _T_6927) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6929 = or(_T_6928, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6930 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6931 = and(_T_6929, _T_6930) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6932 = bits(_T_6931, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6933 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6932 : @[Reg.scala 28:19]
|
|
_T_6933 <= _T_6921 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][35] <= _T_6933 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6934 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6935 = eq(_T_6934, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6936 = and(ic_valid_ff, _T_6935) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6937 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6938 = and(_T_6936, _T_6937) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6939 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6940 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6941 = and(_T_6939, _T_6940) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6942 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6943 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6944 = and(_T_6942, _T_6943) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6945 = or(_T_6941, _T_6944) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6946 = or(_T_6945, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6947 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6948 = and(_T_6946, _T_6947) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6949 = bits(_T_6948, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6950 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6949 : @[Reg.scala 28:19]
|
|
_T_6950 <= _T_6938 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][36] <= _T_6950 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6951 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6952 = eq(_T_6951, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6953 = and(ic_valid_ff, _T_6952) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6954 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6955 = and(_T_6953, _T_6954) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6956 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6957 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6958 = and(_T_6956, _T_6957) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6959 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6960 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6961 = and(_T_6959, _T_6960) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6962 = or(_T_6958, _T_6961) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6963 = or(_T_6962, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6964 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6965 = and(_T_6963, _T_6964) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6966 = bits(_T_6965, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6967 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6966 : @[Reg.scala 28:19]
|
|
_T_6967 <= _T_6955 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][37] <= _T_6967 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6968 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6969 = eq(_T_6968, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6970 = and(ic_valid_ff, _T_6969) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6971 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6972 = and(_T_6970, _T_6971) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6973 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6974 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6975 = and(_T_6973, _T_6974) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6976 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6977 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6978 = and(_T_6976, _T_6977) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6979 = or(_T_6975, _T_6978) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6980 = or(_T_6979, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6981 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6982 = and(_T_6980, _T_6981) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_6983 = bits(_T_6982, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_6984 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6983 : @[Reg.scala 28:19]
|
|
_T_6984 <= _T_6972 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][38] <= _T_6984 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_6985 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_6986 = eq(_T_6985, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_6987 = and(ic_valid_ff, _T_6986) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_6988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_6989 = and(_T_6987, _T_6988) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_6990 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_6991 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_6992 = and(_T_6990, _T_6991) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_6993 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_6994 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_6995 = and(_T_6993, _T_6994) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_6996 = or(_T_6992, _T_6995) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_6997 = or(_T_6996, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_6998 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_6999 = and(_T_6997, _T_6998) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7000 = bits(_T_6999, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7001 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7000 : @[Reg.scala 28:19]
|
|
_T_7001 <= _T_6989 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][39] <= _T_7001 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7002 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7003 = eq(_T_7002, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7004 = and(ic_valid_ff, _T_7003) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7005 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7006 = and(_T_7004, _T_7005) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7007 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7008 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7009 = and(_T_7007, _T_7008) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7010 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7011 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7012 = and(_T_7010, _T_7011) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7013 = or(_T_7009, _T_7012) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7014 = or(_T_7013, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7015 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7016 = and(_T_7014, _T_7015) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7018 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7017 : @[Reg.scala 28:19]
|
|
_T_7018 <= _T_7006 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][40] <= _T_7018 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7019 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7020 = eq(_T_7019, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7021 = and(ic_valid_ff, _T_7020) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7022 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7023 = and(_T_7021, _T_7022) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7024 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7025 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7026 = and(_T_7024, _T_7025) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7027 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7028 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7029 = and(_T_7027, _T_7028) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7030 = or(_T_7026, _T_7029) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7031 = or(_T_7030, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7032 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7033 = and(_T_7031, _T_7032) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7034 = bits(_T_7033, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7035 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7034 : @[Reg.scala 28:19]
|
|
_T_7035 <= _T_7023 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][41] <= _T_7035 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7036 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7037 = eq(_T_7036, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7038 = and(ic_valid_ff, _T_7037) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7039 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7040 = and(_T_7038, _T_7039) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7041 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7042 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7043 = and(_T_7041, _T_7042) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7044 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7045 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7046 = and(_T_7044, _T_7045) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7047 = or(_T_7043, _T_7046) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7048 = or(_T_7047, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7049 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7050 = and(_T_7048, _T_7049) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7051 = bits(_T_7050, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7052 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7051 : @[Reg.scala 28:19]
|
|
_T_7052 <= _T_7040 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][42] <= _T_7052 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7053 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7054 = eq(_T_7053, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7055 = and(ic_valid_ff, _T_7054) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7056 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7057 = and(_T_7055, _T_7056) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7059 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7060 = and(_T_7058, _T_7059) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7061 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7062 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7063 = and(_T_7061, _T_7062) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7064 = or(_T_7060, _T_7063) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7065 = or(_T_7064, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7066 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7067 = and(_T_7065, _T_7066) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7068 = bits(_T_7067, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7069 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7068 : @[Reg.scala 28:19]
|
|
_T_7069 <= _T_7057 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][43] <= _T_7069 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7070 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7071 = eq(_T_7070, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7072 = and(ic_valid_ff, _T_7071) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7073 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7074 = and(_T_7072, _T_7073) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7075 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7076 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7077 = and(_T_7075, _T_7076) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7078 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7079 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7080 = and(_T_7078, _T_7079) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7081 = or(_T_7077, _T_7080) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7082 = or(_T_7081, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7083 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7084 = and(_T_7082, _T_7083) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7085 = bits(_T_7084, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7086 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7085 : @[Reg.scala 28:19]
|
|
_T_7086 <= _T_7074 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][44] <= _T_7086 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7087 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7088 = eq(_T_7087, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7089 = and(ic_valid_ff, _T_7088) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7090 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7091 = and(_T_7089, _T_7090) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7093 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7094 = and(_T_7092, _T_7093) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7095 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7096 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7097 = and(_T_7095, _T_7096) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7098 = or(_T_7094, _T_7097) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7099 = or(_T_7098, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7100 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7101 = and(_T_7099, _T_7100) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7102 = bits(_T_7101, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7103 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7102 : @[Reg.scala 28:19]
|
|
_T_7103 <= _T_7091 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][45] <= _T_7103 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7104 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7105 = eq(_T_7104, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7106 = and(ic_valid_ff, _T_7105) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7107 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7108 = and(_T_7106, _T_7107) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7109 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7110 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7111 = and(_T_7109, _T_7110) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7112 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7113 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7114 = and(_T_7112, _T_7113) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7115 = or(_T_7111, _T_7114) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7116 = or(_T_7115, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7117 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7118 = and(_T_7116, _T_7117) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7119 = bits(_T_7118, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7120 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7119 : @[Reg.scala 28:19]
|
|
_T_7120 <= _T_7108 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][46] <= _T_7120 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7121 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7122 = eq(_T_7121, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7123 = and(ic_valid_ff, _T_7122) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7124 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7125 = and(_T_7123, _T_7124) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7126 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7127 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7128 = and(_T_7126, _T_7127) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7129 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7130 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7131 = and(_T_7129, _T_7130) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7132 = or(_T_7128, _T_7131) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7133 = or(_T_7132, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7134 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7135 = and(_T_7133, _T_7134) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7136 = bits(_T_7135, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7137 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7136 : @[Reg.scala 28:19]
|
|
_T_7137 <= _T_7125 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][47] <= _T_7137 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7138 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7139 = eq(_T_7138, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7140 = and(ic_valid_ff, _T_7139) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7141 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7142 = and(_T_7140, _T_7141) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7143 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7144 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7145 = and(_T_7143, _T_7144) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7146 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7147 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7148 = and(_T_7146, _T_7147) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7149 = or(_T_7145, _T_7148) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7150 = or(_T_7149, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7151 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7152 = and(_T_7150, _T_7151) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7153 = bits(_T_7152, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7154 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7153 : @[Reg.scala 28:19]
|
|
_T_7154 <= _T_7142 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][48] <= _T_7154 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7155 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7156 = eq(_T_7155, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7157 = and(ic_valid_ff, _T_7156) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7159 = and(_T_7157, _T_7158) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7161 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7162 = and(_T_7160, _T_7161) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7163 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7164 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7165 = and(_T_7163, _T_7164) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7166 = or(_T_7162, _T_7165) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7167 = or(_T_7166, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7168 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7169 = and(_T_7167, _T_7168) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7171 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7170 : @[Reg.scala 28:19]
|
|
_T_7171 <= _T_7159 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][49] <= _T_7171 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7172 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7173 = eq(_T_7172, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7174 = and(ic_valid_ff, _T_7173) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7175 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7176 = and(_T_7174, _T_7175) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7177 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7178 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7179 = and(_T_7177, _T_7178) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7180 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7181 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7182 = and(_T_7180, _T_7181) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7183 = or(_T_7179, _T_7182) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7184 = or(_T_7183, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7185 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7186 = and(_T_7184, _T_7185) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7187 = bits(_T_7186, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7188 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7187 : @[Reg.scala 28:19]
|
|
_T_7188 <= _T_7176 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][50] <= _T_7188 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7190 = eq(_T_7189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7191 = and(ic_valid_ff, _T_7190) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7193 = and(_T_7191, _T_7192) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7194 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7196 = and(_T_7194, _T_7195) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7197 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7198 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7199 = and(_T_7197, _T_7198) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7200 = or(_T_7196, _T_7199) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7201 = or(_T_7200, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7202 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7203 = and(_T_7201, _T_7202) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7204 = bits(_T_7203, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7205 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7204 : @[Reg.scala 28:19]
|
|
_T_7205 <= _T_7193 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][51] <= _T_7205 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7206 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7207 = eq(_T_7206, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7208 = and(ic_valid_ff, _T_7207) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7209 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7210 = and(_T_7208, _T_7209) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7211 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7212 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7213 = and(_T_7211, _T_7212) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7214 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7215 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7216 = and(_T_7214, _T_7215) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7217 = or(_T_7213, _T_7216) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7218 = or(_T_7217, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7219 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7220 = and(_T_7218, _T_7219) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7221 = bits(_T_7220, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7222 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7221 : @[Reg.scala 28:19]
|
|
_T_7222 <= _T_7210 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][52] <= _T_7222 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7223 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7224 = eq(_T_7223, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7225 = and(ic_valid_ff, _T_7224) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7226 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7227 = and(_T_7225, _T_7226) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7228 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7229 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7230 = and(_T_7228, _T_7229) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7231 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7232 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7233 = and(_T_7231, _T_7232) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7234 = or(_T_7230, _T_7233) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7235 = or(_T_7234, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7236 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7237 = and(_T_7235, _T_7236) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7238 = bits(_T_7237, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7239 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7238 : @[Reg.scala 28:19]
|
|
_T_7239 <= _T_7227 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][53] <= _T_7239 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7240 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7241 = eq(_T_7240, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7242 = and(ic_valid_ff, _T_7241) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7244 = and(_T_7242, _T_7243) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7245 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7246 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7247 = and(_T_7245, _T_7246) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7248 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7249 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7250 = and(_T_7248, _T_7249) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7251 = or(_T_7247, _T_7250) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7252 = or(_T_7251, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7253 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7254 = and(_T_7252, _T_7253) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7255 = bits(_T_7254, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7256 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7255 : @[Reg.scala 28:19]
|
|
_T_7256 <= _T_7244 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][54] <= _T_7256 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7257 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7258 = eq(_T_7257, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7259 = and(ic_valid_ff, _T_7258) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7260 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7261 = and(_T_7259, _T_7260) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7262 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7263 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7264 = and(_T_7262, _T_7263) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7265 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7266 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7267 = and(_T_7265, _T_7266) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7268 = or(_T_7264, _T_7267) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7269 = or(_T_7268, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7270 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7271 = and(_T_7269, _T_7270) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7272 = bits(_T_7271, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7273 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7272 : @[Reg.scala 28:19]
|
|
_T_7273 <= _T_7261 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][55] <= _T_7273 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7274 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7275 = eq(_T_7274, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7276 = and(ic_valid_ff, _T_7275) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7277 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7278 = and(_T_7276, _T_7277) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7279 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7280 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7281 = and(_T_7279, _T_7280) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7282 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7283 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7284 = and(_T_7282, _T_7283) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7285 = or(_T_7281, _T_7284) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7286 = or(_T_7285, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7287 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7288 = and(_T_7286, _T_7287) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7289 = bits(_T_7288, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7290 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7289 : @[Reg.scala 28:19]
|
|
_T_7290 <= _T_7278 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][56] <= _T_7290 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7291 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7292 = eq(_T_7291, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7293 = and(ic_valid_ff, _T_7292) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7294 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7295 = and(_T_7293, _T_7294) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7296 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7297 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7298 = and(_T_7296, _T_7297) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7299 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7300 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7301 = and(_T_7299, _T_7300) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7302 = or(_T_7298, _T_7301) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7303 = or(_T_7302, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7304 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7305 = and(_T_7303, _T_7304) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7306 = bits(_T_7305, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7307 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7306 : @[Reg.scala 28:19]
|
|
_T_7307 <= _T_7295 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][57] <= _T_7307 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7308 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7309 = eq(_T_7308, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7310 = and(ic_valid_ff, _T_7309) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7311 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7312 = and(_T_7310, _T_7311) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7313 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7314 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7315 = and(_T_7313, _T_7314) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7316 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7317 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7318 = and(_T_7316, _T_7317) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7319 = or(_T_7315, _T_7318) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7320 = or(_T_7319, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7321 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7322 = and(_T_7320, _T_7321) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7324 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7323 : @[Reg.scala 28:19]
|
|
_T_7324 <= _T_7312 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][58] <= _T_7324 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7325 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7327 = and(ic_valid_ff, _T_7326) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7329 = and(_T_7327, _T_7328) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7331 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7332 = and(_T_7330, _T_7331) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7333 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7334 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7335 = and(_T_7333, _T_7334) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7336 = or(_T_7332, _T_7335) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7337 = or(_T_7336, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7338 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7339 = and(_T_7337, _T_7338) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7340 = bits(_T_7339, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7341 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7340 : @[Reg.scala 28:19]
|
|
_T_7341 <= _T_7329 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][59] <= _T_7341 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7342 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7343 = eq(_T_7342, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7344 = and(ic_valid_ff, _T_7343) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7345 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7346 = and(_T_7344, _T_7345) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7347 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7348 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7349 = and(_T_7347, _T_7348) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7350 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7351 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7352 = and(_T_7350, _T_7351) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7353 = or(_T_7349, _T_7352) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7354 = or(_T_7353, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7355 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7356 = and(_T_7354, _T_7355) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7357 = bits(_T_7356, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7358 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7357 : @[Reg.scala 28:19]
|
|
_T_7358 <= _T_7346 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][60] <= _T_7358 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7359 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7360 = eq(_T_7359, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7361 = and(ic_valid_ff, _T_7360) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7362 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7363 = and(_T_7361, _T_7362) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7364 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7365 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7366 = and(_T_7364, _T_7365) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7367 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7368 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7369 = and(_T_7367, _T_7368) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7370 = or(_T_7366, _T_7369) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7371 = or(_T_7370, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7372 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7373 = and(_T_7371, _T_7372) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7374 = bits(_T_7373, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7375 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7374 : @[Reg.scala 28:19]
|
|
_T_7375 <= _T_7363 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][61] <= _T_7375 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7376 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7377 = eq(_T_7376, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7378 = and(ic_valid_ff, _T_7377) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7379 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7380 = and(_T_7378, _T_7379) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7381 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7382 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7383 = and(_T_7381, _T_7382) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7384 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7385 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7386 = and(_T_7384, _T_7385) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7387 = or(_T_7383, _T_7386) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7388 = or(_T_7387, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7389 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7390 = and(_T_7388, _T_7389) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7391 = bits(_T_7390, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7392 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7391 : @[Reg.scala 28:19]
|
|
_T_7392 <= _T_7380 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][62] <= _T_7392 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7393 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7394 = eq(_T_7393, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7395 = and(ic_valid_ff, _T_7394) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7396 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7397 = and(_T_7395, _T_7396) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7398 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7399 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7400 = and(_T_7398, _T_7399) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7401 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7402 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7403 = and(_T_7401, _T_7402) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7404 = or(_T_7400, _T_7403) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7405 = or(_T_7404, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7406 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7407 = and(_T_7405, _T_7406) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7408 = bits(_T_7407, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7409 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7408 : @[Reg.scala 28:19]
|
|
_T_7409 <= _T_7397 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][63] <= _T_7409 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7410 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7411 = eq(_T_7410, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7412 = and(ic_valid_ff, _T_7411) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7413 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7414 = and(_T_7412, _T_7413) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7415 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7416 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7417 = and(_T_7415, _T_7416) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7418 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7419 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7420 = and(_T_7418, _T_7419) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7421 = or(_T_7417, _T_7420) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7422 = or(_T_7421, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7423 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7424 = and(_T_7422, _T_7423) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7425 = bits(_T_7424, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7426 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7425 : @[Reg.scala 28:19]
|
|
_T_7426 <= _T_7414 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][64] <= _T_7426 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7427 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7428 = eq(_T_7427, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7429 = and(ic_valid_ff, _T_7428) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7430 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7431 = and(_T_7429, _T_7430) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7432 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7433 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7434 = and(_T_7432, _T_7433) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7435 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7436 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7437 = and(_T_7435, _T_7436) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7438 = or(_T_7434, _T_7437) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7439 = or(_T_7438, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7440 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7441 = and(_T_7439, _T_7440) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7442 = bits(_T_7441, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7443 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7442 : @[Reg.scala 28:19]
|
|
_T_7443 <= _T_7431 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][65] <= _T_7443 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7444 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7445 = eq(_T_7444, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7446 = and(ic_valid_ff, _T_7445) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7447 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7448 = and(_T_7446, _T_7447) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7449 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7450 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7451 = and(_T_7449, _T_7450) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7452 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7453 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7454 = and(_T_7452, _T_7453) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7455 = or(_T_7451, _T_7454) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7456 = or(_T_7455, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7457 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7458 = and(_T_7456, _T_7457) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7459 = bits(_T_7458, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7460 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7459 : @[Reg.scala 28:19]
|
|
_T_7460 <= _T_7448 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][66] <= _T_7460 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7462 = eq(_T_7461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7463 = and(ic_valid_ff, _T_7462) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7465 = and(_T_7463, _T_7464) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7466 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7467 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7468 = and(_T_7466, _T_7467) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7469 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7470 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7471 = and(_T_7469, _T_7470) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7472 = or(_T_7468, _T_7471) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7473 = or(_T_7472, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7474 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7475 = and(_T_7473, _T_7474) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7477 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7476 : @[Reg.scala 28:19]
|
|
_T_7477 <= _T_7465 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][67] <= _T_7477 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7478 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7479 = eq(_T_7478, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7480 = and(ic_valid_ff, _T_7479) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7481 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7482 = and(_T_7480, _T_7481) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7483 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7484 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7485 = and(_T_7483, _T_7484) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7486 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7487 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7488 = and(_T_7486, _T_7487) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7489 = or(_T_7485, _T_7488) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7490 = or(_T_7489, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7491 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7492 = and(_T_7490, _T_7491) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7493 = bits(_T_7492, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7494 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7493 : @[Reg.scala 28:19]
|
|
_T_7494 <= _T_7482 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][68] <= _T_7494 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7495 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7496 = eq(_T_7495, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7497 = and(ic_valid_ff, _T_7496) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7499 = and(_T_7497, _T_7498) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7501 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7502 = and(_T_7500, _T_7501) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7503 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7504 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7505 = and(_T_7503, _T_7504) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7506 = or(_T_7502, _T_7505) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7507 = or(_T_7506, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7508 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7509 = and(_T_7507, _T_7508) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7510 = bits(_T_7509, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7511 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7510 : @[Reg.scala 28:19]
|
|
_T_7511 <= _T_7499 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][69] <= _T_7511 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7512 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7513 = eq(_T_7512, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7514 = and(ic_valid_ff, _T_7513) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7515 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7516 = and(_T_7514, _T_7515) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7518 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7519 = and(_T_7517, _T_7518) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7520 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7521 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7522 = and(_T_7520, _T_7521) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7523 = or(_T_7519, _T_7522) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7524 = or(_T_7523, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7525 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7526 = and(_T_7524, _T_7525) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7527 = bits(_T_7526, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7528 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7527 : @[Reg.scala 28:19]
|
|
_T_7528 <= _T_7516 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][70] <= _T_7528 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7529 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7530 = eq(_T_7529, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7531 = and(ic_valid_ff, _T_7530) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7532 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7533 = and(_T_7531, _T_7532) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7534 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7535 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7536 = and(_T_7534, _T_7535) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7537 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7538 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7539 = and(_T_7537, _T_7538) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7540 = or(_T_7536, _T_7539) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7541 = or(_T_7540, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7542 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7543 = and(_T_7541, _T_7542) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7544 = bits(_T_7543, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7545 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7544 : @[Reg.scala 28:19]
|
|
_T_7545 <= _T_7533 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][71] <= _T_7545 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7546 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7547 = eq(_T_7546, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7548 = and(ic_valid_ff, _T_7547) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7549 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7550 = and(_T_7548, _T_7549) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7552 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7553 = and(_T_7551, _T_7552) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7554 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7555 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7556 = and(_T_7554, _T_7555) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7557 = or(_T_7553, _T_7556) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7558 = or(_T_7557, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7559 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7560 = and(_T_7558, _T_7559) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7561 = bits(_T_7560, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7562 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7561 : @[Reg.scala 28:19]
|
|
_T_7562 <= _T_7550 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][72] <= _T_7562 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7563 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7564 = eq(_T_7563, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7565 = and(ic_valid_ff, _T_7564) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7566 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7567 = and(_T_7565, _T_7566) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7568 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7569 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7570 = and(_T_7568, _T_7569) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7571 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7572 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7573 = and(_T_7571, _T_7572) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7574 = or(_T_7570, _T_7573) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7575 = or(_T_7574, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7576 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7577 = and(_T_7575, _T_7576) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7578 = bits(_T_7577, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7579 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7578 : @[Reg.scala 28:19]
|
|
_T_7579 <= _T_7567 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][73] <= _T_7579 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7580 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7581 = eq(_T_7580, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7582 = and(ic_valid_ff, _T_7581) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7583 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7584 = and(_T_7582, _T_7583) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7586 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7587 = and(_T_7585, _T_7586) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7588 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7589 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7590 = and(_T_7588, _T_7589) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7591 = or(_T_7587, _T_7590) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7592 = or(_T_7591, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7593 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7594 = and(_T_7592, _T_7593) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7595 = bits(_T_7594, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7596 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7595 : @[Reg.scala 28:19]
|
|
_T_7596 <= _T_7584 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][74] <= _T_7596 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7597 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7598 = eq(_T_7597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7599 = and(ic_valid_ff, _T_7598) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7600 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7601 = and(_T_7599, _T_7600) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7602 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7603 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7604 = and(_T_7602, _T_7603) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7605 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7606 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7607 = and(_T_7605, _T_7606) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7608 = or(_T_7604, _T_7607) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7609 = or(_T_7608, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7610 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7611 = and(_T_7609, _T_7610) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7612 = bits(_T_7611, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7613 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7612 : @[Reg.scala 28:19]
|
|
_T_7613 <= _T_7601 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][75] <= _T_7613 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7614 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7615 = eq(_T_7614, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7616 = and(ic_valid_ff, _T_7615) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7617 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7618 = and(_T_7616, _T_7617) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7620 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7621 = and(_T_7619, _T_7620) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7622 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7623 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7624 = and(_T_7622, _T_7623) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7625 = or(_T_7621, _T_7624) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7626 = or(_T_7625, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7627 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7628 = and(_T_7626, _T_7627) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7630 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7629 : @[Reg.scala 28:19]
|
|
_T_7630 <= _T_7618 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][76] <= _T_7630 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7631 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7632 = eq(_T_7631, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7633 = and(ic_valid_ff, _T_7632) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7634 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7635 = and(_T_7633, _T_7634) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7636 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7637 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7638 = and(_T_7636, _T_7637) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7639 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7640 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7641 = and(_T_7639, _T_7640) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7642 = or(_T_7638, _T_7641) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7643 = or(_T_7642, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7644 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7645 = and(_T_7643, _T_7644) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7646 = bits(_T_7645, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7647 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7646 : @[Reg.scala 28:19]
|
|
_T_7647 <= _T_7635 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][77] <= _T_7647 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7648 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7649 = eq(_T_7648, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7650 = and(ic_valid_ff, _T_7649) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7651 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7652 = and(_T_7650, _T_7651) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7653 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7654 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7655 = and(_T_7653, _T_7654) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7656 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7657 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7658 = and(_T_7656, _T_7657) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7659 = or(_T_7655, _T_7658) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7660 = or(_T_7659, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7661 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7662 = and(_T_7660, _T_7661) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7663 = bits(_T_7662, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7664 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7663 : @[Reg.scala 28:19]
|
|
_T_7664 <= _T_7652 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][78] <= _T_7664 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7665 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7666 = eq(_T_7665, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7667 = and(ic_valid_ff, _T_7666) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7668 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7669 = and(_T_7667, _T_7668) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7670 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7671 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7672 = and(_T_7670, _T_7671) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7673 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7674 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7675 = and(_T_7673, _T_7674) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7676 = or(_T_7672, _T_7675) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7677 = or(_T_7676, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7678 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7679 = and(_T_7677, _T_7678) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7680 = bits(_T_7679, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7681 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7680 : @[Reg.scala 28:19]
|
|
_T_7681 <= _T_7669 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][79] <= _T_7681 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7682 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7683 = eq(_T_7682, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7684 = and(ic_valid_ff, _T_7683) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7685 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7686 = and(_T_7684, _T_7685) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7687 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7688 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7689 = and(_T_7687, _T_7688) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7690 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7691 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7692 = and(_T_7690, _T_7691) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7693 = or(_T_7689, _T_7692) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7694 = or(_T_7693, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7695 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7696 = and(_T_7694, _T_7695) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7697 = bits(_T_7696, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7698 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7697 : @[Reg.scala 28:19]
|
|
_T_7698 <= _T_7686 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][80] <= _T_7698 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7700 = eq(_T_7699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7701 = and(ic_valid_ff, _T_7700) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7703 = and(_T_7701, _T_7702) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7705 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7706 = and(_T_7704, _T_7705) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7707 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7708 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7709 = and(_T_7707, _T_7708) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7710 = or(_T_7706, _T_7709) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7711 = or(_T_7710, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7712 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7713 = and(_T_7711, _T_7712) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7714 = bits(_T_7713, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7715 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7714 : @[Reg.scala 28:19]
|
|
_T_7715 <= _T_7703 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][81] <= _T_7715 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7716 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7717 = eq(_T_7716, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7718 = and(ic_valid_ff, _T_7717) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7719 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7720 = and(_T_7718, _T_7719) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7721 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7722 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7723 = and(_T_7721, _T_7722) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7724 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7725 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7726 = and(_T_7724, _T_7725) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7727 = or(_T_7723, _T_7726) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7728 = or(_T_7727, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7729 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7730 = and(_T_7728, _T_7729) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7731 = bits(_T_7730, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7732 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7731 : @[Reg.scala 28:19]
|
|
_T_7732 <= _T_7720 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][82] <= _T_7732 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7734 = eq(_T_7733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7735 = and(ic_valid_ff, _T_7734) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7737 = and(_T_7735, _T_7736) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7739 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7740 = and(_T_7738, _T_7739) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7741 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7742 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7743 = and(_T_7741, _T_7742) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7744 = or(_T_7740, _T_7743) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7745 = or(_T_7744, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7746 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7747 = and(_T_7745, _T_7746) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7748 = bits(_T_7747, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7749 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7748 : @[Reg.scala 28:19]
|
|
_T_7749 <= _T_7737 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][83] <= _T_7749 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7750 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7751 = eq(_T_7750, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7752 = and(ic_valid_ff, _T_7751) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7754 = and(_T_7752, _T_7753) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7756 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7757 = and(_T_7755, _T_7756) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7758 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7759 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7760 = and(_T_7758, _T_7759) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7761 = or(_T_7757, _T_7760) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7762 = or(_T_7761, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7763 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7764 = and(_T_7762, _T_7763) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7765 = bits(_T_7764, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7766 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7765 : @[Reg.scala 28:19]
|
|
_T_7766 <= _T_7754 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][84] <= _T_7766 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7767 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7768 = eq(_T_7767, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7769 = and(ic_valid_ff, _T_7768) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7770 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7771 = and(_T_7769, _T_7770) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7773 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7774 = and(_T_7772, _T_7773) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7775 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7776 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7777 = and(_T_7775, _T_7776) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7778 = or(_T_7774, _T_7777) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7779 = or(_T_7778, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7780 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7781 = and(_T_7779, _T_7780) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7783 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7782 : @[Reg.scala 28:19]
|
|
_T_7783 <= _T_7771 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][85] <= _T_7783 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7784 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7785 = eq(_T_7784, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7786 = and(ic_valid_ff, _T_7785) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7787 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7788 = and(_T_7786, _T_7787) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7790 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7791 = and(_T_7789, _T_7790) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7792 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7793 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7794 = and(_T_7792, _T_7793) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7795 = or(_T_7791, _T_7794) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7796 = or(_T_7795, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7797 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7798 = and(_T_7796, _T_7797) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7799 = bits(_T_7798, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7800 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7799 : @[Reg.scala 28:19]
|
|
_T_7800 <= _T_7788 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][86] <= _T_7800 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7801 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7802 = eq(_T_7801, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7803 = and(ic_valid_ff, _T_7802) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7804 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7805 = and(_T_7803, _T_7804) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7806 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7807 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7808 = and(_T_7806, _T_7807) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7809 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7810 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7811 = and(_T_7809, _T_7810) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7812 = or(_T_7808, _T_7811) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7813 = or(_T_7812, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7814 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7815 = and(_T_7813, _T_7814) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7816 = bits(_T_7815, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7817 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7816 : @[Reg.scala 28:19]
|
|
_T_7817 <= _T_7805 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][87] <= _T_7817 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7818 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7819 = eq(_T_7818, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7820 = and(ic_valid_ff, _T_7819) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7821 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7822 = and(_T_7820, _T_7821) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7823 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7824 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7825 = and(_T_7823, _T_7824) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7826 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7827 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7828 = and(_T_7826, _T_7827) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7829 = or(_T_7825, _T_7828) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7830 = or(_T_7829, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7831 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7832 = and(_T_7830, _T_7831) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7833 = bits(_T_7832, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7834 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7833 : @[Reg.scala 28:19]
|
|
_T_7834 <= _T_7822 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][88] <= _T_7834 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7835 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7836 = eq(_T_7835, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7837 = and(ic_valid_ff, _T_7836) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7839 = and(_T_7837, _T_7838) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7841 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7842 = and(_T_7840, _T_7841) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7843 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7844 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7845 = and(_T_7843, _T_7844) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7846 = or(_T_7842, _T_7845) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7847 = or(_T_7846, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7848 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7849 = and(_T_7847, _T_7848) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7850 = bits(_T_7849, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7851 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7850 : @[Reg.scala 28:19]
|
|
_T_7851 <= _T_7839 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][89] <= _T_7851 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7852 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7853 = eq(_T_7852, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7854 = and(ic_valid_ff, _T_7853) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7855 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7856 = and(_T_7854, _T_7855) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7857 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7858 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7859 = and(_T_7857, _T_7858) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7860 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7861 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7862 = and(_T_7860, _T_7861) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7863 = or(_T_7859, _T_7862) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7864 = or(_T_7863, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7865 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7866 = and(_T_7864, _T_7865) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7867 = bits(_T_7866, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7868 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7867 : @[Reg.scala 28:19]
|
|
_T_7868 <= _T_7856 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][90] <= _T_7868 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7870 = eq(_T_7869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7871 = and(ic_valid_ff, _T_7870) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7873 = and(_T_7871, _T_7872) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7875 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7876 = and(_T_7874, _T_7875) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7877 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7878 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7879 = and(_T_7877, _T_7878) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7880 = or(_T_7876, _T_7879) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7881 = or(_T_7880, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7882 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7883 = and(_T_7881, _T_7882) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7884 = bits(_T_7883, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7885 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7884 : @[Reg.scala 28:19]
|
|
_T_7885 <= _T_7873 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][91] <= _T_7885 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7886 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7887 = eq(_T_7886, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7888 = and(ic_valid_ff, _T_7887) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7889 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7890 = and(_T_7888, _T_7889) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7891 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7892 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7893 = and(_T_7891, _T_7892) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7894 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7895 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7896 = and(_T_7894, _T_7895) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7897 = or(_T_7893, _T_7896) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7898 = or(_T_7897, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7899 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7900 = and(_T_7898, _T_7899) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7901 = bits(_T_7900, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7902 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7901 : @[Reg.scala 28:19]
|
|
_T_7902 <= _T_7890 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][92] <= _T_7902 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7903 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7904 = eq(_T_7903, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7905 = and(ic_valid_ff, _T_7904) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7906 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7907 = and(_T_7905, _T_7906) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7908 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7909 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7910 = and(_T_7908, _T_7909) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7911 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7912 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7913 = and(_T_7911, _T_7912) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7914 = or(_T_7910, _T_7913) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7915 = or(_T_7914, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7916 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7917 = and(_T_7915, _T_7916) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7918 = bits(_T_7917, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7919 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7918 : @[Reg.scala 28:19]
|
|
_T_7919 <= _T_7907 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][93] <= _T_7919 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7920 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7921 = eq(_T_7920, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7922 = and(ic_valid_ff, _T_7921) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7923 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7924 = and(_T_7922, _T_7923) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7925 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7926 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7927 = and(_T_7925, _T_7926) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7928 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7929 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7930 = and(_T_7928, _T_7929) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7931 = or(_T_7927, _T_7930) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7932 = or(_T_7931, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7933 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7934 = and(_T_7932, _T_7933) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7936 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7935 : @[Reg.scala 28:19]
|
|
_T_7936 <= _T_7924 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][94] <= _T_7936 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7937 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7938 = eq(_T_7937, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7939 = and(ic_valid_ff, _T_7938) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7940 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7941 = and(_T_7939, _T_7940) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7942 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7943 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7944 = and(_T_7942, _T_7943) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7945 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7946 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7947 = and(_T_7945, _T_7946) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7948 = or(_T_7944, _T_7947) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7949 = or(_T_7948, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7950 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7951 = and(_T_7949, _T_7950) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7952 = bits(_T_7951, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7953 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7952 : @[Reg.scala 28:19]
|
|
_T_7953 <= _T_7941 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][95] <= _T_7953 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7954 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7955 = eq(_T_7954, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7956 = and(ic_valid_ff, _T_7955) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7957 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7958 = and(_T_7956, _T_7957) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7959 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7960 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7961 = and(_T_7959, _T_7960) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7962 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7963 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7964 = and(_T_7962, _T_7963) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7965 = or(_T_7961, _T_7964) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7966 = or(_T_7965, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7967 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7968 = and(_T_7966, _T_7967) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7969 = bits(_T_7968, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7970 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7969 : @[Reg.scala 28:19]
|
|
_T_7970 <= _T_7958 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][64] <= _T_7970 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7971 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7972 = eq(_T_7971, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7973 = and(ic_valid_ff, _T_7972) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7974 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7975 = and(_T_7973, _T_7974) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7976 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7977 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7978 = and(_T_7976, _T_7977) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7979 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7980 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7981 = and(_T_7979, _T_7980) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7982 = or(_T_7978, _T_7981) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_7983 = or(_T_7982, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_7984 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_7985 = and(_T_7983, _T_7984) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_7986 = bits(_T_7985, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_7987 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7986 : @[Reg.scala 28:19]
|
|
_T_7987 <= _T_7975 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][65] <= _T_7987 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_7988 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_7989 = eq(_T_7988, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_7990 = and(ic_valid_ff, _T_7989) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_7991 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_7992 = and(_T_7990, _T_7991) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_7993 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_7994 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_7995 = and(_T_7993, _T_7994) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_7996 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_7997 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_7998 = and(_T_7996, _T_7997) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_7999 = or(_T_7995, _T_7998) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8000 = or(_T_7999, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8001 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8002 = and(_T_8000, _T_8001) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8003 = bits(_T_8002, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8004 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8003 : @[Reg.scala 28:19]
|
|
_T_8004 <= _T_7992 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][66] <= _T_8004 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8006 = eq(_T_8005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8007 = and(ic_valid_ff, _T_8006) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8009 = and(_T_8007, _T_8008) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8010 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8012 = and(_T_8010, _T_8011) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8013 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8014 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8015 = and(_T_8013, _T_8014) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8016 = or(_T_8012, _T_8015) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8017 = or(_T_8016, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8018 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8019 = and(_T_8017, _T_8018) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8020 = bits(_T_8019, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8021 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8020 : @[Reg.scala 28:19]
|
|
_T_8021 <= _T_8009 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][67] <= _T_8021 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8022 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8023 = eq(_T_8022, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8024 = and(ic_valid_ff, _T_8023) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8025 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8026 = and(_T_8024, _T_8025) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8027 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8028 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8029 = and(_T_8027, _T_8028) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8030 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8031 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8032 = and(_T_8030, _T_8031) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8033 = or(_T_8029, _T_8032) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8034 = or(_T_8033, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8035 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8036 = and(_T_8034, _T_8035) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8037 = bits(_T_8036, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8038 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8037 : @[Reg.scala 28:19]
|
|
_T_8038 <= _T_8026 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][68] <= _T_8038 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8039 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8040 = eq(_T_8039, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8041 = and(ic_valid_ff, _T_8040) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8042 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8043 = and(_T_8041, _T_8042) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8044 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8045 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8046 = and(_T_8044, _T_8045) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8047 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8048 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8049 = and(_T_8047, _T_8048) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8050 = or(_T_8046, _T_8049) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8051 = or(_T_8050, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8052 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8053 = and(_T_8051, _T_8052) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8054 = bits(_T_8053, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8055 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8054 : @[Reg.scala 28:19]
|
|
_T_8055 <= _T_8043 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][69] <= _T_8055 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8056 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8057 = eq(_T_8056, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8058 = and(ic_valid_ff, _T_8057) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8059 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8060 = and(_T_8058, _T_8059) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8061 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8062 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8063 = and(_T_8061, _T_8062) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8064 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8065 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8066 = and(_T_8064, _T_8065) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8067 = or(_T_8063, _T_8066) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8068 = or(_T_8067, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8069 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8070 = and(_T_8068, _T_8069) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8071 = bits(_T_8070, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8072 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8071 : @[Reg.scala 28:19]
|
|
_T_8072 <= _T_8060 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][70] <= _T_8072 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8073 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8074 = eq(_T_8073, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8075 = and(ic_valid_ff, _T_8074) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8076 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8077 = and(_T_8075, _T_8076) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8078 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8079 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8080 = and(_T_8078, _T_8079) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8081 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8082 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8083 = and(_T_8081, _T_8082) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8084 = or(_T_8080, _T_8083) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8085 = or(_T_8084, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8086 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8087 = and(_T_8085, _T_8086) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8089 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8088 : @[Reg.scala 28:19]
|
|
_T_8089 <= _T_8077 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][71] <= _T_8089 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8090 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8091 = eq(_T_8090, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8092 = and(ic_valid_ff, _T_8091) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8093 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8094 = and(_T_8092, _T_8093) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8096 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8097 = and(_T_8095, _T_8096) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8098 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8099 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8100 = and(_T_8098, _T_8099) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8101 = or(_T_8097, _T_8100) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8102 = or(_T_8101, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8103 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8104 = and(_T_8102, _T_8103) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8105 = bits(_T_8104, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8106 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8105 : @[Reg.scala 28:19]
|
|
_T_8106 <= _T_8094 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][72] <= _T_8106 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8107 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8108 = eq(_T_8107, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8109 = and(ic_valid_ff, _T_8108) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8110 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8111 = and(_T_8109, _T_8110) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8112 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8113 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8114 = and(_T_8112, _T_8113) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8115 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8116 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8117 = and(_T_8115, _T_8116) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8118 = or(_T_8114, _T_8117) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8119 = or(_T_8118, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8120 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8121 = and(_T_8119, _T_8120) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8122 = bits(_T_8121, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8123 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8122 : @[Reg.scala 28:19]
|
|
_T_8123 <= _T_8111 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][73] <= _T_8123 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8124 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8125 = eq(_T_8124, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8126 = and(ic_valid_ff, _T_8125) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8127 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8128 = and(_T_8126, _T_8127) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8129 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8130 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8131 = and(_T_8129, _T_8130) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8132 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8133 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8134 = and(_T_8132, _T_8133) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8135 = or(_T_8131, _T_8134) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8136 = or(_T_8135, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8137 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8138 = and(_T_8136, _T_8137) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8139 = bits(_T_8138, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8140 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8139 : @[Reg.scala 28:19]
|
|
_T_8140 <= _T_8128 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][74] <= _T_8140 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8141 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8142 = eq(_T_8141, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8143 = and(ic_valid_ff, _T_8142) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8144 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8145 = and(_T_8143, _T_8144) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8147 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8148 = and(_T_8146, _T_8147) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8149 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8150 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8152 = or(_T_8148, _T_8151) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8153 = or(_T_8152, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8154 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8155 = and(_T_8153, _T_8154) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8156 = bits(_T_8155, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8157 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8156 : @[Reg.scala 28:19]
|
|
_T_8157 <= _T_8145 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][75] <= _T_8157 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8158 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8159 = eq(_T_8158, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8160 = and(ic_valid_ff, _T_8159) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8161 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8162 = and(_T_8160, _T_8161) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8163 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8164 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8165 = and(_T_8163, _T_8164) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8166 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8167 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8168 = and(_T_8166, _T_8167) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8169 = or(_T_8165, _T_8168) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8170 = or(_T_8169, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8171 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8172 = and(_T_8170, _T_8171) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8173 = bits(_T_8172, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8174 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8173 : @[Reg.scala 28:19]
|
|
_T_8174 <= _T_8162 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][76] <= _T_8174 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8175 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8176 = eq(_T_8175, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8177 = and(ic_valid_ff, _T_8176) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8179 = and(_T_8177, _T_8178) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8181 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8182 = and(_T_8180, _T_8181) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8183 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8184 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8185 = and(_T_8183, _T_8184) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8186 = or(_T_8182, _T_8185) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8187 = or(_T_8186, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8188 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8189 = and(_T_8187, _T_8188) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8190 = bits(_T_8189, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8191 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8190 : @[Reg.scala 28:19]
|
|
_T_8191 <= _T_8179 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][77] <= _T_8191 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8192 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8193 = eq(_T_8192, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8194 = and(ic_valid_ff, _T_8193) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8195 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8196 = and(_T_8194, _T_8195) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8197 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8198 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8200 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8201 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8202 = and(_T_8200, _T_8201) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8203 = or(_T_8199, _T_8202) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8204 = or(_T_8203, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8205 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8206 = and(_T_8204, _T_8205) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8207 = bits(_T_8206, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8208 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8207 : @[Reg.scala 28:19]
|
|
_T_8208 <= _T_8196 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][78] <= _T_8208 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8209 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8210 = eq(_T_8209, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8211 = and(ic_valid_ff, _T_8210) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8212 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8213 = and(_T_8211, _T_8212) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8215 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8216 = and(_T_8214, _T_8215) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8217 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8218 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8219 = and(_T_8217, _T_8218) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8220 = or(_T_8216, _T_8219) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8221 = or(_T_8220, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8222 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8223 = and(_T_8221, _T_8222) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8224 = bits(_T_8223, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8225 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8224 : @[Reg.scala 28:19]
|
|
_T_8225 <= _T_8213 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][79] <= _T_8225 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8226 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8227 = eq(_T_8226, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8228 = and(ic_valid_ff, _T_8227) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8229 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8230 = and(_T_8228, _T_8229) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8231 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8232 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8233 = and(_T_8231, _T_8232) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8234 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8235 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8236 = and(_T_8234, _T_8235) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8237 = or(_T_8233, _T_8236) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8238 = or(_T_8237, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8239 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8240 = and(_T_8238, _T_8239) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8242 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8241 : @[Reg.scala 28:19]
|
|
_T_8242 <= _T_8230 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][80] <= _T_8242 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8243 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8244 = eq(_T_8243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8245 = and(ic_valid_ff, _T_8244) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8246 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8247 = and(_T_8245, _T_8246) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8248 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8249 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8250 = and(_T_8248, _T_8249) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8251 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8252 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8253 = and(_T_8251, _T_8252) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8254 = or(_T_8250, _T_8253) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8255 = or(_T_8254, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8256 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8257 = and(_T_8255, _T_8256) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8258 = bits(_T_8257, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8259 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8258 : @[Reg.scala 28:19]
|
|
_T_8259 <= _T_8247 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][81] <= _T_8259 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8260 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8261 = eq(_T_8260, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8262 = and(ic_valid_ff, _T_8261) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8263 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8264 = and(_T_8262, _T_8263) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8265 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8266 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8267 = and(_T_8265, _T_8266) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8268 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8269 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8270 = and(_T_8268, _T_8269) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8271 = or(_T_8267, _T_8270) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8272 = or(_T_8271, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8273 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8274 = and(_T_8272, _T_8273) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8275 = bits(_T_8274, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8276 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8275 : @[Reg.scala 28:19]
|
|
_T_8276 <= _T_8264 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][82] <= _T_8276 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8278 = eq(_T_8277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8279 = and(ic_valid_ff, _T_8278) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8281 = and(_T_8279, _T_8280) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8283 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8284 = and(_T_8282, _T_8283) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8285 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8286 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8287 = and(_T_8285, _T_8286) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8288 = or(_T_8284, _T_8287) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8289 = or(_T_8288, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8290 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8291 = and(_T_8289, _T_8290) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8292 = bits(_T_8291, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8293 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8292 : @[Reg.scala 28:19]
|
|
_T_8293 <= _T_8281 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][83] <= _T_8293 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8294 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8295 = eq(_T_8294, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8296 = and(ic_valid_ff, _T_8295) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8297 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8298 = and(_T_8296, _T_8297) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8299 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8300 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8301 = and(_T_8299, _T_8300) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8302 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8303 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8304 = and(_T_8302, _T_8303) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8305 = or(_T_8301, _T_8304) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8306 = or(_T_8305, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8307 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8308 = and(_T_8306, _T_8307) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8309 = bits(_T_8308, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8310 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8309 : @[Reg.scala 28:19]
|
|
_T_8310 <= _T_8298 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][84] <= _T_8310 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8311 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8312 = eq(_T_8311, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8313 = and(ic_valid_ff, _T_8312) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8314 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8315 = and(_T_8313, _T_8314) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8316 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8317 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8318 = and(_T_8316, _T_8317) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8319 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8320 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8321 = and(_T_8319, _T_8320) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8322 = or(_T_8318, _T_8321) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8323 = or(_T_8322, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8324 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8325 = and(_T_8323, _T_8324) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8326 = bits(_T_8325, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8327 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8326 : @[Reg.scala 28:19]
|
|
_T_8327 <= _T_8315 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][85] <= _T_8327 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8328 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8329 = eq(_T_8328, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8330 = and(ic_valid_ff, _T_8329) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8331 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8332 = and(_T_8330, _T_8331) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8333 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8334 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8335 = and(_T_8333, _T_8334) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8336 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8337 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8338 = and(_T_8336, _T_8337) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8339 = or(_T_8335, _T_8338) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8340 = or(_T_8339, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8341 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8342 = and(_T_8340, _T_8341) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8343 = bits(_T_8342, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8344 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8343 : @[Reg.scala 28:19]
|
|
_T_8344 <= _T_8332 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][86] <= _T_8344 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8345 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8346 = eq(_T_8345, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8347 = and(ic_valid_ff, _T_8346) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8349 = and(_T_8347, _T_8348) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8350 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8351 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8352 = and(_T_8350, _T_8351) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8353 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8354 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8355 = and(_T_8353, _T_8354) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8356 = or(_T_8352, _T_8355) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8357 = or(_T_8356, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8358 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8359 = and(_T_8357, _T_8358) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8360 = bits(_T_8359, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8361 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8360 : @[Reg.scala 28:19]
|
|
_T_8361 <= _T_8349 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][87] <= _T_8361 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8362 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8363 = eq(_T_8362, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8364 = and(ic_valid_ff, _T_8363) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8365 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8366 = and(_T_8364, _T_8365) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8367 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8368 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8369 = and(_T_8367, _T_8368) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8370 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8371 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8372 = and(_T_8370, _T_8371) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8373 = or(_T_8369, _T_8372) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8374 = or(_T_8373, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8375 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8376 = and(_T_8374, _T_8375) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8377 = bits(_T_8376, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8378 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8377 : @[Reg.scala 28:19]
|
|
_T_8378 <= _T_8366 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][88] <= _T_8378 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8379 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8380 = eq(_T_8379, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8381 = and(ic_valid_ff, _T_8380) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8382 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8383 = and(_T_8381, _T_8382) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8384 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8385 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8386 = and(_T_8384, _T_8385) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8387 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8388 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8389 = and(_T_8387, _T_8388) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8390 = or(_T_8386, _T_8389) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8391 = or(_T_8390, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8392 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8393 = and(_T_8391, _T_8392) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8395 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8394 : @[Reg.scala 28:19]
|
|
_T_8395 <= _T_8383 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][89] <= _T_8395 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8396 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8397 = eq(_T_8396, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8398 = and(ic_valid_ff, _T_8397) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8399 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8400 = and(_T_8398, _T_8399) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8401 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8402 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8403 = and(_T_8401, _T_8402) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8404 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8405 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8406 = and(_T_8404, _T_8405) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8407 = or(_T_8403, _T_8406) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8408 = or(_T_8407, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8409 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8410 = and(_T_8408, _T_8409) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8411 = bits(_T_8410, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8412 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8411 : @[Reg.scala 28:19]
|
|
_T_8412 <= _T_8400 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][90] <= _T_8412 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8414 = eq(_T_8413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8415 = and(ic_valid_ff, _T_8414) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8417 = and(_T_8415, _T_8416) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8418 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8419 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8420 = and(_T_8418, _T_8419) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8421 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8422 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8423 = and(_T_8421, _T_8422) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8424 = or(_T_8420, _T_8423) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8425 = or(_T_8424, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8426 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8427 = and(_T_8425, _T_8426) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8428 = bits(_T_8427, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8429 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8428 : @[Reg.scala 28:19]
|
|
_T_8429 <= _T_8417 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][91] <= _T_8429 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8430 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8431 = eq(_T_8430, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8432 = and(ic_valid_ff, _T_8431) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8433 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8434 = and(_T_8432, _T_8433) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8436 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8437 = and(_T_8435, _T_8436) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8438 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8439 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8440 = and(_T_8438, _T_8439) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8441 = or(_T_8437, _T_8440) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8442 = or(_T_8441, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8443 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8444 = and(_T_8442, _T_8443) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8445 = bits(_T_8444, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8446 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8445 : @[Reg.scala 28:19]
|
|
_T_8446 <= _T_8434 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][92] <= _T_8446 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8447 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8448 = eq(_T_8447, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8449 = and(ic_valid_ff, _T_8448) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8450 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8451 = and(_T_8449, _T_8450) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8452 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8453 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8454 = and(_T_8452, _T_8453) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8455 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8456 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8457 = and(_T_8455, _T_8456) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8458 = or(_T_8454, _T_8457) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8459 = or(_T_8458, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8460 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8461 = and(_T_8459, _T_8460) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8462 = bits(_T_8461, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8463 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8462 : @[Reg.scala 28:19]
|
|
_T_8463 <= _T_8451 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][93] <= _T_8463 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8464 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8465 = eq(_T_8464, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8466 = and(ic_valid_ff, _T_8465) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8467 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8468 = and(_T_8466, _T_8467) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8469 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8470 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8471 = and(_T_8469, _T_8470) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8472 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8473 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8474 = and(_T_8472, _T_8473) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8475 = or(_T_8471, _T_8474) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8476 = or(_T_8475, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8477 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8478 = and(_T_8476, _T_8477) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8479 = bits(_T_8478, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8480 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8479 : @[Reg.scala 28:19]
|
|
_T_8480 <= _T_8468 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][94] <= _T_8480 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8481 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8482 = eq(_T_8481, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8483 = and(ic_valid_ff, _T_8482) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8484 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8485 = and(_T_8483, _T_8484) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8486 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8487 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8488 = and(_T_8486, _T_8487) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8489 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8490 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8491 = and(_T_8489, _T_8490) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8492 = or(_T_8488, _T_8491) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8493 = or(_T_8492, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8494 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8495 = and(_T_8493, _T_8494) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8496 = bits(_T_8495, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8497 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8496 : @[Reg.scala 28:19]
|
|
_T_8497 <= _T_8485 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][95] <= _T_8497 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8498 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8499 = eq(_T_8498, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8500 = and(ic_valid_ff, _T_8499) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8501 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8502 = and(_T_8500, _T_8501) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8504 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8505 = and(_T_8503, _T_8504) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8506 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8507 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8508 = and(_T_8506, _T_8507) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8509 = or(_T_8505, _T_8508) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8510 = or(_T_8509, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8511 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8512 = and(_T_8510, _T_8511) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8513 = bits(_T_8512, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8514 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8513 : @[Reg.scala 28:19]
|
|
_T_8514 <= _T_8502 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][96] <= _T_8514 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8515 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8516 = eq(_T_8515, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8517 = and(ic_valid_ff, _T_8516) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8519 = and(_T_8517, _T_8518) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8520 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8521 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8522 = and(_T_8520, _T_8521) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8523 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8524 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8525 = and(_T_8523, _T_8524) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8526 = or(_T_8522, _T_8525) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8527 = or(_T_8526, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8528 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8529 = and(_T_8527, _T_8528) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8530 = bits(_T_8529, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8531 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8530 : @[Reg.scala 28:19]
|
|
_T_8531 <= _T_8519 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][97] <= _T_8531 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8532 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8533 = eq(_T_8532, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8534 = and(ic_valid_ff, _T_8533) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8535 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8536 = and(_T_8534, _T_8535) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8538 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8539 = and(_T_8537, _T_8538) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8540 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8541 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8542 = and(_T_8540, _T_8541) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8543 = or(_T_8539, _T_8542) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8544 = or(_T_8543, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8545 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8546 = and(_T_8544, _T_8545) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8548 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8547 : @[Reg.scala 28:19]
|
|
_T_8548 <= _T_8536 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][98] <= _T_8548 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8550 = eq(_T_8549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8551 = and(ic_valid_ff, _T_8550) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8553 = and(_T_8551, _T_8552) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8554 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8556 = and(_T_8554, _T_8555) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8557 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8558 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8559 = and(_T_8557, _T_8558) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8560 = or(_T_8556, _T_8559) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8561 = or(_T_8560, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8562 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8563 = and(_T_8561, _T_8562) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8564 = bits(_T_8563, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8565 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8564 : @[Reg.scala 28:19]
|
|
_T_8565 <= _T_8553 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][99] <= _T_8565 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8566 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8567 = eq(_T_8566, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8568 = and(ic_valid_ff, _T_8567) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8569 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8570 = and(_T_8568, _T_8569) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8572 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8573 = and(_T_8571, _T_8572) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8574 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8575 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8576 = and(_T_8574, _T_8575) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8577 = or(_T_8573, _T_8576) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8578 = or(_T_8577, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8579 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8580 = and(_T_8578, _T_8579) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8581 = bits(_T_8580, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8582 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8581 : @[Reg.scala 28:19]
|
|
_T_8582 <= _T_8570 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][100] <= _T_8582 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8583 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8584 = eq(_T_8583, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8585 = and(ic_valid_ff, _T_8584) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8586 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8587 = and(_T_8585, _T_8586) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8588 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8589 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8590 = and(_T_8588, _T_8589) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8591 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8592 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8593 = and(_T_8591, _T_8592) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8594 = or(_T_8590, _T_8593) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8595 = or(_T_8594, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8596 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8597 = and(_T_8595, _T_8596) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8598 = bits(_T_8597, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8599 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8598 : @[Reg.scala 28:19]
|
|
_T_8599 <= _T_8587 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][101] <= _T_8599 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8600 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8601 = eq(_T_8600, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8602 = and(ic_valid_ff, _T_8601) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8604 = and(_T_8602, _T_8603) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8606 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8607 = and(_T_8605, _T_8606) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8608 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8609 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8610 = and(_T_8608, _T_8609) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8611 = or(_T_8607, _T_8610) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8612 = or(_T_8611, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8613 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8614 = and(_T_8612, _T_8613) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8615 = bits(_T_8614, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8616 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8615 : @[Reg.scala 28:19]
|
|
_T_8616 <= _T_8604 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][102] <= _T_8616 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8617 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8618 = eq(_T_8617, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8619 = and(ic_valid_ff, _T_8618) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8620 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8621 = and(_T_8619, _T_8620) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8622 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8623 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8624 = and(_T_8622, _T_8623) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8625 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8626 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8627 = and(_T_8625, _T_8626) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8628 = or(_T_8624, _T_8627) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8629 = or(_T_8628, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8630 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8631 = and(_T_8629, _T_8630) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8632 = bits(_T_8631, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8633 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8632 : @[Reg.scala 28:19]
|
|
_T_8633 <= _T_8621 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][103] <= _T_8633 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8634 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8635 = eq(_T_8634, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8636 = and(ic_valid_ff, _T_8635) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8637 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8638 = and(_T_8636, _T_8637) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8639 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8640 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8641 = and(_T_8639, _T_8640) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8642 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8643 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8644 = and(_T_8642, _T_8643) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8645 = or(_T_8641, _T_8644) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8646 = or(_T_8645, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8647 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8648 = and(_T_8646, _T_8647) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8649 = bits(_T_8648, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8650 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8649 : @[Reg.scala 28:19]
|
|
_T_8650 <= _T_8638 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][104] <= _T_8650 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8651 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8652 = eq(_T_8651, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8653 = and(ic_valid_ff, _T_8652) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8654 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8655 = and(_T_8653, _T_8654) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8656 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8657 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8658 = and(_T_8656, _T_8657) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8659 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8660 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8661 = and(_T_8659, _T_8660) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8662 = or(_T_8658, _T_8661) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8663 = or(_T_8662, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8664 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8665 = and(_T_8663, _T_8664) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8666 = bits(_T_8665, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8667 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8666 : @[Reg.scala 28:19]
|
|
_T_8667 <= _T_8655 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][105] <= _T_8667 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8668 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8669 = eq(_T_8668, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8670 = and(ic_valid_ff, _T_8669) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8671 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8672 = and(_T_8670, _T_8671) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8673 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8674 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8675 = and(_T_8673, _T_8674) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8676 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8677 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8678 = and(_T_8676, _T_8677) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8679 = or(_T_8675, _T_8678) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8680 = or(_T_8679, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8681 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8682 = and(_T_8680, _T_8681) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8683 = bits(_T_8682, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8684 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8683 : @[Reg.scala 28:19]
|
|
_T_8684 <= _T_8672 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][106] <= _T_8684 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8686 = eq(_T_8685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8687 = and(ic_valid_ff, _T_8686) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8689 = and(_T_8687, _T_8688) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8691 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8692 = and(_T_8690, _T_8691) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8693 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8694 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8695 = and(_T_8693, _T_8694) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8696 = or(_T_8692, _T_8695) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8697 = or(_T_8696, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8698 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8699 = and(_T_8697, _T_8698) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8701 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8700 : @[Reg.scala 28:19]
|
|
_T_8701 <= _T_8689 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][107] <= _T_8701 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8702 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8703 = eq(_T_8702, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8704 = and(ic_valid_ff, _T_8703) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8705 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8706 = and(_T_8704, _T_8705) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8707 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8708 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8709 = and(_T_8707, _T_8708) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8710 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8711 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8712 = and(_T_8710, _T_8711) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8713 = or(_T_8709, _T_8712) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8714 = or(_T_8713, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8715 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8716 = and(_T_8714, _T_8715) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8717 = bits(_T_8716, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8718 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8717 : @[Reg.scala 28:19]
|
|
_T_8718 <= _T_8706 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][108] <= _T_8718 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8719 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8720 = eq(_T_8719, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8721 = and(ic_valid_ff, _T_8720) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8722 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8723 = and(_T_8721, _T_8722) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8724 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8725 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8726 = and(_T_8724, _T_8725) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8727 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8728 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8729 = and(_T_8727, _T_8728) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8730 = or(_T_8726, _T_8729) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8731 = or(_T_8730, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8732 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8733 = and(_T_8731, _T_8732) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8734 = bits(_T_8733, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8735 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8734 : @[Reg.scala 28:19]
|
|
_T_8735 <= _T_8723 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][109] <= _T_8735 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8736 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8737 = eq(_T_8736, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8738 = and(ic_valid_ff, _T_8737) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8739 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8740 = and(_T_8738, _T_8739) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8742 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8743 = and(_T_8741, _T_8742) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8744 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8745 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8746 = and(_T_8744, _T_8745) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8747 = or(_T_8743, _T_8746) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8748 = or(_T_8747, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8749 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8750 = and(_T_8748, _T_8749) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8751 = bits(_T_8750, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8752 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8751 : @[Reg.scala 28:19]
|
|
_T_8752 <= _T_8740 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][110] <= _T_8752 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8753 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8754 = eq(_T_8753, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8755 = and(ic_valid_ff, _T_8754) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8756 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8757 = and(_T_8755, _T_8756) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8759 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8760 = and(_T_8758, _T_8759) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8761 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8762 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8763 = and(_T_8761, _T_8762) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8764 = or(_T_8760, _T_8763) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8765 = or(_T_8764, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8766 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8767 = and(_T_8765, _T_8766) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8768 = bits(_T_8767, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8769 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8768 : @[Reg.scala 28:19]
|
|
_T_8769 <= _T_8757 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][111] <= _T_8769 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8770 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8771 = eq(_T_8770, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8772 = and(ic_valid_ff, _T_8771) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8773 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8774 = and(_T_8772, _T_8773) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8776 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8777 = and(_T_8775, _T_8776) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8778 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8779 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8780 = and(_T_8778, _T_8779) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8781 = or(_T_8777, _T_8780) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8782 = or(_T_8781, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8783 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8784 = and(_T_8782, _T_8783) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8785 = bits(_T_8784, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8786 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8785 : @[Reg.scala 28:19]
|
|
_T_8786 <= _T_8774 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][112] <= _T_8786 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8787 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8788 = eq(_T_8787, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8789 = and(ic_valid_ff, _T_8788) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8790 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8791 = and(_T_8789, _T_8790) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8793 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8794 = and(_T_8792, _T_8793) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8795 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8796 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8797 = and(_T_8795, _T_8796) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8798 = or(_T_8794, _T_8797) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8799 = or(_T_8798, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8800 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8801 = and(_T_8799, _T_8800) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8802 = bits(_T_8801, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8803 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8802 : @[Reg.scala 28:19]
|
|
_T_8803 <= _T_8791 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][113] <= _T_8803 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8804 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8805 = eq(_T_8804, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8806 = and(ic_valid_ff, _T_8805) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8807 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8808 = and(_T_8806, _T_8807) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8809 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8810 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8811 = and(_T_8809, _T_8810) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8812 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8813 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8814 = and(_T_8812, _T_8813) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8815 = or(_T_8811, _T_8814) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8816 = or(_T_8815, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8817 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8818 = and(_T_8816, _T_8817) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8819 = bits(_T_8818, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8820 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8819 : @[Reg.scala 28:19]
|
|
_T_8820 <= _T_8808 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][114] <= _T_8820 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8821 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8822 = eq(_T_8821, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8823 = and(ic_valid_ff, _T_8822) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8824 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8825 = and(_T_8823, _T_8824) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8827 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8828 = and(_T_8826, _T_8827) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8829 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8830 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8831 = and(_T_8829, _T_8830) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8832 = or(_T_8828, _T_8831) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8833 = or(_T_8832, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8834 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8835 = and(_T_8833, _T_8834) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8836 = bits(_T_8835, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8837 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8836 : @[Reg.scala 28:19]
|
|
_T_8837 <= _T_8825 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][115] <= _T_8837 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8838 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8839 = eq(_T_8838, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8840 = and(ic_valid_ff, _T_8839) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8841 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8842 = and(_T_8840, _T_8841) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8843 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8844 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8845 = and(_T_8843, _T_8844) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8846 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8847 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8848 = and(_T_8846, _T_8847) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8849 = or(_T_8845, _T_8848) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8850 = or(_T_8849, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8851 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8852 = and(_T_8850, _T_8851) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8854 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8853 : @[Reg.scala 28:19]
|
|
_T_8854 <= _T_8842 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][116] <= _T_8854 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8855 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8856 = eq(_T_8855, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8857 = and(ic_valid_ff, _T_8856) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8859 = and(_T_8857, _T_8858) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8861 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8862 = and(_T_8860, _T_8861) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8863 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8864 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8865 = and(_T_8863, _T_8864) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8866 = or(_T_8862, _T_8865) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8867 = or(_T_8866, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8868 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8869 = and(_T_8867, _T_8868) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8870 = bits(_T_8869, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8871 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8870 : @[Reg.scala 28:19]
|
|
_T_8871 <= _T_8859 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][117] <= _T_8871 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8872 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8873 = eq(_T_8872, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8874 = and(ic_valid_ff, _T_8873) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8875 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8876 = and(_T_8874, _T_8875) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8877 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8878 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8879 = and(_T_8877, _T_8878) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8880 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8881 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8882 = and(_T_8880, _T_8881) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8883 = or(_T_8879, _T_8882) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8884 = or(_T_8883, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8885 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8886 = and(_T_8884, _T_8885) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8887 = bits(_T_8886, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8888 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8887 : @[Reg.scala 28:19]
|
|
_T_8888 <= _T_8876 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][118] <= _T_8888 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8889 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8890 = eq(_T_8889, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8891 = and(ic_valid_ff, _T_8890) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8892 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8893 = and(_T_8891, _T_8892) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8894 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8895 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8896 = and(_T_8894, _T_8895) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8897 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8898 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8899 = and(_T_8897, _T_8898) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8900 = or(_T_8896, _T_8899) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8901 = or(_T_8900, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8902 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8903 = and(_T_8901, _T_8902) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8904 = bits(_T_8903, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8905 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8904 : @[Reg.scala 28:19]
|
|
_T_8905 <= _T_8893 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][119] <= _T_8905 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8906 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8907 = eq(_T_8906, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8908 = and(ic_valid_ff, _T_8907) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8909 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8910 = and(_T_8908, _T_8909) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8911 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8912 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8913 = and(_T_8911, _T_8912) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8914 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8915 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8916 = and(_T_8914, _T_8915) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8917 = or(_T_8913, _T_8916) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8918 = or(_T_8917, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8919 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8920 = and(_T_8918, _T_8919) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8921 = bits(_T_8920, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8922 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8921 : @[Reg.scala 28:19]
|
|
_T_8922 <= _T_8910 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][120] <= _T_8922 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8923 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8924 = eq(_T_8923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8925 = and(ic_valid_ff, _T_8924) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8926 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8927 = and(_T_8925, _T_8926) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8929 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8930 = and(_T_8928, _T_8929) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8931 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8932 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8933 = and(_T_8931, _T_8932) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8934 = or(_T_8930, _T_8933) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8935 = or(_T_8934, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8936 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8937 = and(_T_8935, _T_8936) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8938 = bits(_T_8937, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8939 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8938 : @[Reg.scala 28:19]
|
|
_T_8939 <= _T_8927 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][121] <= _T_8939 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8940 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8941 = eq(_T_8940, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8942 = and(ic_valid_ff, _T_8941) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8943 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8944 = and(_T_8942, _T_8943) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8946 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8947 = and(_T_8945, _T_8946) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8948 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8949 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8950 = and(_T_8948, _T_8949) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8951 = or(_T_8947, _T_8950) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8952 = or(_T_8951, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8953 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8954 = and(_T_8952, _T_8953) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8955 = bits(_T_8954, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8956 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8955 : @[Reg.scala 28:19]
|
|
_T_8956 <= _T_8944 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][122] <= _T_8956 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8958 = eq(_T_8957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8959 = and(ic_valid_ff, _T_8958) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8961 = and(_T_8959, _T_8960) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8962 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8963 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8964 = and(_T_8962, _T_8963) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8965 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8966 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8967 = and(_T_8965, _T_8966) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8968 = or(_T_8964, _T_8967) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8969 = or(_T_8968, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8970 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8971 = and(_T_8969, _T_8970) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8972 = bits(_T_8971, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8973 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8972 : @[Reg.scala 28:19]
|
|
_T_8973 <= _T_8961 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][123] <= _T_8973 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8974 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8975 = eq(_T_8974, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8976 = and(ic_valid_ff, _T_8975) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8977 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8978 = and(_T_8976, _T_8977) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8979 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8980 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8981 = and(_T_8979, _T_8980) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8982 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_8983 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_8984 = and(_T_8982, _T_8983) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_8985 = or(_T_8981, _T_8984) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_8986 = or(_T_8985, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_8987 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_8988 = and(_T_8986, _T_8987) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_8989 = bits(_T_8988, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_8990 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8989 : @[Reg.scala 28:19]
|
|
_T_8990 <= _T_8978 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][124] <= _T_8990 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_8991 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_8992 = eq(_T_8991, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_8993 = and(ic_valid_ff, _T_8992) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_8994 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_8995 = and(_T_8993, _T_8994) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_8996 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_8997 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_8998 = and(_T_8996, _T_8997) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_8999 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9000 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9001 = and(_T_8999, _T_9000) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9002 = or(_T_8998, _T_9001) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9003 = or(_T_9002, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9004 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9005 = and(_T_9003, _T_9004) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9007 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9006 : @[Reg.scala 28:19]
|
|
_T_9007 <= _T_8995 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][125] <= _T_9007 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9008 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9010 = and(ic_valid_ff, _T_9009) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9011 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9012 = and(_T_9010, _T_9011) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9013 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9014 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9015 = and(_T_9013, _T_9014) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9016 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9017 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9018 = and(_T_9016, _T_9017) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9019 = or(_T_9015, _T_9018) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9020 = or(_T_9019, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9021 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9022 = and(_T_9020, _T_9021) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9023 = bits(_T_9022, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9024 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9023 : @[Reg.scala 28:19]
|
|
_T_9024 <= _T_9012 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][126] <= _T_9024 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9025 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9026 = eq(_T_9025, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9027 = and(ic_valid_ff, _T_9026) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9028 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9029 = and(_T_9027, _T_9028) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9030 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9031 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9032 = and(_T_9030, _T_9031) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9033 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9034 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9035 = and(_T_9033, _T_9034) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9036 = or(_T_9032, _T_9035) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9037 = or(_T_9036, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9038 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9039 = and(_T_9037, _T_9038) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9040 = bits(_T_9039, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9041 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9040 : @[Reg.scala 28:19]
|
|
_T_9041 <= _T_9029 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][127] <= _T_9041 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9042 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9043 = eq(_T_9042, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9044 = and(ic_valid_ff, _T_9043) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9045 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9046 = and(_T_9044, _T_9045) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9047 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9048 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9049 = and(_T_9047, _T_9048) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9050 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9051 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9052 = and(_T_9050, _T_9051) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9053 = or(_T_9049, _T_9052) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9054 = or(_T_9053, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9055 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9056 = and(_T_9054, _T_9055) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9057 = bits(_T_9056, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9058 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9057 : @[Reg.scala 28:19]
|
|
_T_9058 <= _T_9046 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][96] <= _T_9058 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9059 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9060 = eq(_T_9059, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9061 = and(ic_valid_ff, _T_9060) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9062 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9063 = and(_T_9061, _T_9062) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9065 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9066 = and(_T_9064, _T_9065) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9067 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9068 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9069 = and(_T_9067, _T_9068) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9070 = or(_T_9066, _T_9069) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9071 = or(_T_9070, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9072 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9073 = and(_T_9071, _T_9072) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9074 = bits(_T_9073, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9075 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9074 : @[Reg.scala 28:19]
|
|
_T_9075 <= _T_9063 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][97] <= _T_9075 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9076 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9077 = eq(_T_9076, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9078 = and(ic_valid_ff, _T_9077) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9079 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9080 = and(_T_9078, _T_9079) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9081 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9082 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9083 = and(_T_9081, _T_9082) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9084 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9085 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9086 = and(_T_9084, _T_9085) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9087 = or(_T_9083, _T_9086) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9088 = or(_T_9087, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9089 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9090 = and(_T_9088, _T_9089) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9091 = bits(_T_9090, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9092 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9091 : @[Reg.scala 28:19]
|
|
_T_9092 <= _T_9080 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][98] <= _T_9092 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9093 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9094 = eq(_T_9093, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9095 = and(ic_valid_ff, _T_9094) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9096 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9097 = and(_T_9095, _T_9096) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9099 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9100 = and(_T_9098, _T_9099) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9101 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9102 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9103 = and(_T_9101, _T_9102) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9104 = or(_T_9100, _T_9103) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9105 = or(_T_9104, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9106 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9107 = and(_T_9105, _T_9106) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9108 = bits(_T_9107, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9109 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9108 : @[Reg.scala 28:19]
|
|
_T_9109 <= _T_9097 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][99] <= _T_9109 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9110 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9111 = eq(_T_9110, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9112 = and(ic_valid_ff, _T_9111) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9113 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9114 = and(_T_9112, _T_9113) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9115 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9116 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9117 = and(_T_9115, _T_9116) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9118 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9119 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9120 = and(_T_9118, _T_9119) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9121 = or(_T_9117, _T_9120) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9122 = or(_T_9121, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9123 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9124 = and(_T_9122, _T_9123) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9125 = bits(_T_9124, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9126 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9125 : @[Reg.scala 28:19]
|
|
_T_9126 <= _T_9114 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][100] <= _T_9126 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9127 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9128 = eq(_T_9127, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9129 = and(ic_valid_ff, _T_9128) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9130 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9131 = and(_T_9129, _T_9130) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9133 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9134 = and(_T_9132, _T_9133) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9135 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9136 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9137 = and(_T_9135, _T_9136) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9138 = or(_T_9134, _T_9137) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9139 = or(_T_9138, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9140 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9141 = and(_T_9139, _T_9140) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9142 = bits(_T_9141, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9143 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9142 : @[Reg.scala 28:19]
|
|
_T_9143 <= _T_9131 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][101] <= _T_9143 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9144 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9145 = eq(_T_9144, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9146 = and(ic_valid_ff, _T_9145) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9147 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9148 = and(_T_9146, _T_9147) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9149 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9150 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9151 = and(_T_9149, _T_9150) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9152 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9153 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9154 = and(_T_9152, _T_9153) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9155 = or(_T_9151, _T_9154) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9156 = or(_T_9155, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9157 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9158 = and(_T_9156, _T_9157) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9160 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9159 : @[Reg.scala 28:19]
|
|
_T_9160 <= _T_9148 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][102] <= _T_9160 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9161 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9162 = eq(_T_9161, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9163 = and(ic_valid_ff, _T_9162) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9164 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9165 = and(_T_9163, _T_9164) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9167 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9168 = and(_T_9166, _T_9167) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9169 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9170 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9171 = and(_T_9169, _T_9170) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9172 = or(_T_9168, _T_9171) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9173 = or(_T_9172, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9174 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9175 = and(_T_9173, _T_9174) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9176 = bits(_T_9175, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9177 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9176 : @[Reg.scala 28:19]
|
|
_T_9177 <= _T_9165 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][103] <= _T_9177 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9178 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9179 = eq(_T_9178, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9180 = and(ic_valid_ff, _T_9179) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9181 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9182 = and(_T_9180, _T_9181) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9183 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9184 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9185 = and(_T_9183, _T_9184) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9186 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9187 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9188 = and(_T_9186, _T_9187) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9189 = or(_T_9185, _T_9188) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9190 = or(_T_9189, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9191 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9192 = and(_T_9190, _T_9191) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9193 = bits(_T_9192, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9194 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9193 : @[Reg.scala 28:19]
|
|
_T_9194 <= _T_9182 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][104] <= _T_9194 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9195 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9196 = eq(_T_9195, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9197 = and(ic_valid_ff, _T_9196) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9199 = and(_T_9197, _T_9198) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9201 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9202 = and(_T_9200, _T_9201) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9203 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9204 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9205 = and(_T_9203, _T_9204) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9206 = or(_T_9202, _T_9205) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9207 = or(_T_9206, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9208 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9209 = and(_T_9207, _T_9208) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9210 = bits(_T_9209, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9211 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9210 : @[Reg.scala 28:19]
|
|
_T_9211 <= _T_9199 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][105] <= _T_9211 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9212 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9213 = eq(_T_9212, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9214 = and(ic_valid_ff, _T_9213) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9215 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9216 = and(_T_9214, _T_9215) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9217 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9218 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9219 = and(_T_9217, _T_9218) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9220 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9221 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9222 = and(_T_9220, _T_9221) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9223 = or(_T_9219, _T_9222) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9224 = or(_T_9223, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9225 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9226 = and(_T_9224, _T_9225) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9227 = bits(_T_9226, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9228 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9227 : @[Reg.scala 28:19]
|
|
_T_9228 <= _T_9216 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][106] <= _T_9228 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9230 = eq(_T_9229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9231 = and(ic_valid_ff, _T_9230) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9233 = and(_T_9231, _T_9232) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9235 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9236 = and(_T_9234, _T_9235) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9237 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9238 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9239 = and(_T_9237, _T_9238) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9240 = or(_T_9236, _T_9239) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9241 = or(_T_9240, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9242 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9243 = and(_T_9241, _T_9242) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9244 = bits(_T_9243, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9245 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9244 : @[Reg.scala 28:19]
|
|
_T_9245 <= _T_9233 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][107] <= _T_9245 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9246 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9247 = eq(_T_9246, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9248 = and(ic_valid_ff, _T_9247) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9249 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9250 = and(_T_9248, _T_9249) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9251 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9252 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9253 = and(_T_9251, _T_9252) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9254 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9255 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9256 = and(_T_9254, _T_9255) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9257 = or(_T_9253, _T_9256) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9258 = or(_T_9257, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9259 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9260 = and(_T_9258, _T_9259) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9261 = bits(_T_9260, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9262 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9261 : @[Reg.scala 28:19]
|
|
_T_9262 <= _T_9250 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][108] <= _T_9262 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9263 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9264 = eq(_T_9263, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9265 = and(ic_valid_ff, _T_9264) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9266 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9267 = and(_T_9265, _T_9266) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9268 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9269 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9270 = and(_T_9268, _T_9269) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9271 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9272 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9273 = and(_T_9271, _T_9272) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9274 = or(_T_9270, _T_9273) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9275 = or(_T_9274, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9276 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9277 = and(_T_9275, _T_9276) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9278 = bits(_T_9277, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9279 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9278 : @[Reg.scala 28:19]
|
|
_T_9279 <= _T_9267 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][109] <= _T_9279 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9280 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9281 = eq(_T_9280, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9282 = and(ic_valid_ff, _T_9281) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9283 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9284 = and(_T_9282, _T_9283) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9285 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9286 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9287 = and(_T_9285, _T_9286) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9288 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9289 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9290 = and(_T_9288, _T_9289) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9291 = or(_T_9287, _T_9290) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9292 = or(_T_9291, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9293 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9294 = and(_T_9292, _T_9293) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9295 = bits(_T_9294, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9296 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9295 : @[Reg.scala 28:19]
|
|
_T_9296 <= _T_9284 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][110] <= _T_9296 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9297 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9298 = eq(_T_9297, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9299 = and(ic_valid_ff, _T_9298) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9300 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9301 = and(_T_9299, _T_9300) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9302 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9303 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9304 = and(_T_9302, _T_9303) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9305 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9306 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9307 = and(_T_9305, _T_9306) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9308 = or(_T_9304, _T_9307) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9309 = or(_T_9308, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9310 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9311 = and(_T_9309, _T_9310) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9313 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9312 : @[Reg.scala 28:19]
|
|
_T_9313 <= _T_9301 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][111] <= _T_9313 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9314 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9315 = eq(_T_9314, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9316 = and(ic_valid_ff, _T_9315) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9317 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9318 = and(_T_9316, _T_9317) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9319 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9320 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9321 = and(_T_9319, _T_9320) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9322 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9323 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9324 = and(_T_9322, _T_9323) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9325 = or(_T_9321, _T_9324) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9326 = or(_T_9325, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9327 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9328 = and(_T_9326, _T_9327) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9329 = bits(_T_9328, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9330 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9329 : @[Reg.scala 28:19]
|
|
_T_9330 <= _T_9318 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][112] <= _T_9330 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9331 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9332 = eq(_T_9331, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9333 = and(ic_valid_ff, _T_9332) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9334 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9335 = and(_T_9333, _T_9334) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9336 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9337 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9338 = and(_T_9336, _T_9337) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9339 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9340 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9341 = and(_T_9339, _T_9340) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9342 = or(_T_9338, _T_9341) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9343 = or(_T_9342, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9344 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9345 = and(_T_9343, _T_9344) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9346 = bits(_T_9345, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9347 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9346 : @[Reg.scala 28:19]
|
|
_T_9347 <= _T_9335 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][113] <= _T_9347 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9348 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9349 = eq(_T_9348, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9350 = and(ic_valid_ff, _T_9349) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9351 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9352 = and(_T_9350, _T_9351) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9353 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9354 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9355 = and(_T_9353, _T_9354) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9356 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9357 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9358 = and(_T_9356, _T_9357) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9359 = or(_T_9355, _T_9358) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9360 = or(_T_9359, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9361 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9362 = and(_T_9360, _T_9361) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9363 = bits(_T_9362, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9364 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9363 : @[Reg.scala 28:19]
|
|
_T_9364 <= _T_9352 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][114] <= _T_9364 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9365 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9366 = eq(_T_9365, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9367 = and(ic_valid_ff, _T_9366) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9369 = and(_T_9367, _T_9368) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9370 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9371 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9372 = and(_T_9370, _T_9371) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9373 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9374 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9375 = and(_T_9373, _T_9374) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9376 = or(_T_9372, _T_9375) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9377 = or(_T_9376, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9378 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9379 = and(_T_9377, _T_9378) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9380 = bits(_T_9379, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9381 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9380 : @[Reg.scala 28:19]
|
|
_T_9381 <= _T_9369 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][115] <= _T_9381 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9382 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9383 = eq(_T_9382, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9384 = and(ic_valid_ff, _T_9383) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9385 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9386 = and(_T_9384, _T_9385) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9388 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9389 = and(_T_9387, _T_9388) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9390 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9391 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9392 = and(_T_9390, _T_9391) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9393 = or(_T_9389, _T_9392) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9394 = or(_T_9393, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9395 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9396 = and(_T_9394, _T_9395) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9397 = bits(_T_9396, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9398 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9397 : @[Reg.scala 28:19]
|
|
_T_9398 <= _T_9386 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][116] <= _T_9398 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9399 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9400 = eq(_T_9399, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9401 = and(ic_valid_ff, _T_9400) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9402 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9403 = and(_T_9401, _T_9402) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9404 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9405 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9406 = and(_T_9404, _T_9405) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9407 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9408 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9409 = and(_T_9407, _T_9408) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9410 = or(_T_9406, _T_9409) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9411 = or(_T_9410, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9412 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9413 = and(_T_9411, _T_9412) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9414 = bits(_T_9413, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9415 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9414 : @[Reg.scala 28:19]
|
|
_T_9415 <= _T_9403 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][117] <= _T_9415 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9416 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9417 = eq(_T_9416, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9418 = and(ic_valid_ff, _T_9417) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9419 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9420 = and(_T_9418, _T_9419) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9422 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9423 = and(_T_9421, _T_9422) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9424 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9425 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9426 = and(_T_9424, _T_9425) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9427 = or(_T_9423, _T_9426) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9428 = or(_T_9427, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9429 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9430 = and(_T_9428, _T_9429) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9431 = bits(_T_9430, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9432 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9431 : @[Reg.scala 28:19]
|
|
_T_9432 <= _T_9420 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][118] <= _T_9432 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9433 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9434 = eq(_T_9433, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9435 = and(ic_valid_ff, _T_9434) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9436 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9437 = and(_T_9435, _T_9436) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9438 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9439 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9440 = and(_T_9438, _T_9439) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9441 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9442 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9443 = and(_T_9441, _T_9442) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9444 = or(_T_9440, _T_9443) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9445 = or(_T_9444, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9446 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9447 = and(_T_9445, _T_9446) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9448 = bits(_T_9447, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9449 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9448 : @[Reg.scala 28:19]
|
|
_T_9449 <= _T_9437 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][119] <= _T_9449 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9450 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9451 = eq(_T_9450, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9452 = and(ic_valid_ff, _T_9451) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9454 = and(_T_9452, _T_9453) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9456 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9457 = and(_T_9455, _T_9456) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9458 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9459 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9460 = and(_T_9458, _T_9459) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9461 = or(_T_9457, _T_9460) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9462 = or(_T_9461, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9463 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9464 = and(_T_9462, _T_9463) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9466 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9465 : @[Reg.scala 28:19]
|
|
_T_9466 <= _T_9454 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][120] <= _T_9466 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9467 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9468 = eq(_T_9467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9469 = and(ic_valid_ff, _T_9468) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9470 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9471 = and(_T_9469, _T_9470) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9472 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9473 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9474 = and(_T_9472, _T_9473) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9475 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9476 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9477 = and(_T_9475, _T_9476) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9478 = or(_T_9474, _T_9477) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9479 = or(_T_9478, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9480 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9481 = and(_T_9479, _T_9480) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9482 = bits(_T_9481, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9483 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9482 : @[Reg.scala 28:19]
|
|
_T_9483 <= _T_9471 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][121] <= _T_9483 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9484 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9485 = eq(_T_9484, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9486 = and(ic_valid_ff, _T_9485) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9487 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9488 = and(_T_9486, _T_9487) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9490 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9491 = and(_T_9489, _T_9490) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9492 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9493 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9494 = and(_T_9492, _T_9493) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9495 = or(_T_9491, _T_9494) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9496 = or(_T_9495, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9497 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9498 = and(_T_9496, _T_9497) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9499 = bits(_T_9498, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9500 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9499 : @[Reg.scala 28:19]
|
|
_T_9500 <= _T_9488 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][122] <= _T_9500 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9502 = eq(_T_9501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9503 = and(ic_valid_ff, _T_9502) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9505 = and(_T_9503, _T_9504) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9506 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9507 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9508 = and(_T_9506, _T_9507) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9509 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9510 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9511 = and(_T_9509, _T_9510) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9512 = or(_T_9508, _T_9511) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9513 = or(_T_9512, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9514 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9515 = and(_T_9513, _T_9514) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9516 = bits(_T_9515, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9517 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9516 : @[Reg.scala 28:19]
|
|
_T_9517 <= _T_9505 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][123] <= _T_9517 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9518 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9519 = eq(_T_9518, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9520 = and(ic_valid_ff, _T_9519) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9521 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9522 = and(_T_9520, _T_9521) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9524 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9525 = and(_T_9523, _T_9524) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9526 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9527 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9528 = and(_T_9526, _T_9527) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9529 = or(_T_9525, _T_9528) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9530 = or(_T_9529, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9531 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9532 = and(_T_9530, _T_9531) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9533 = bits(_T_9532, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9534 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9533 : @[Reg.scala 28:19]
|
|
_T_9534 <= _T_9522 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][124] <= _T_9534 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9535 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9536 = eq(_T_9535, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9537 = and(ic_valid_ff, _T_9536) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9538 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9539 = and(_T_9537, _T_9538) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9541 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9542 = and(_T_9540, _T_9541) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9543 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9544 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9545 = and(_T_9543, _T_9544) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9546 = or(_T_9542, _T_9545) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9547 = or(_T_9546, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9548 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9549 = and(_T_9547, _T_9548) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9550 = bits(_T_9549, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9551 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9550 : @[Reg.scala 28:19]
|
|
_T_9551 <= _T_9539 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][125] <= _T_9551 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9552 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9553 = eq(_T_9552, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9554 = and(ic_valid_ff, _T_9553) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9555 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9556 = and(_T_9554, _T_9555) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9558 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9559 = and(_T_9557, _T_9558) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9560 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9561 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9562 = and(_T_9560, _T_9561) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9563 = or(_T_9559, _T_9562) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9564 = or(_T_9563, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9565 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9566 = and(_T_9564, _T_9565) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9567 = bits(_T_9566, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9568 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9567 : @[Reg.scala 28:19]
|
|
_T_9568 <= _T_9556 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][126] <= _T_9568 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9569 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 756:84]
|
|
node _T_9570 = eq(_T_9569, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:68]
|
|
node _T_9571 = and(ic_valid_ff, _T_9570) @[el2_ifu_mem_ctl.scala 756:66]
|
|
node _T_9572 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:93]
|
|
node _T_9573 = and(_T_9571, _T_9572) @[el2_ifu_mem_ctl.scala 756:91]
|
|
node _T_9574 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:37]
|
|
node _T_9575 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 757:76]
|
|
node _T_9576 = and(_T_9574, _T_9575) @[el2_ifu_mem_ctl.scala 757:59]
|
|
node _T_9577 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:102]
|
|
node _T_9578 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 757:142]
|
|
node _T_9579 = and(_T_9577, _T_9578) @[el2_ifu_mem_ctl.scala 757:124]
|
|
node _T_9580 = or(_T_9576, _T_9579) @[el2_ifu_mem_ctl.scala 757:81]
|
|
node _T_9581 = or(_T_9580, reset_all_tags) @[el2_ifu_mem_ctl.scala 757:147]
|
|
node _T_9582 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 757:185]
|
|
node _T_9583 = and(_T_9581, _T_9582) @[el2_ifu_mem_ctl.scala 757:165]
|
|
node _T_9584 = bits(_T_9583, 0, 0) @[el2_ifu_mem_ctl.scala 757:190]
|
|
reg _T_9585 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9584 : @[Reg.scala 28:19]
|
|
_T_9585 <= _T_9573 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][127] <= _T_9585 @[el2_ifu_mem_ctl.scala 756:41]
|
|
node _T_9586 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9587 = mux(_T_9586, ic_tag_valid_out[0][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9588 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9589 = mux(_T_9588, ic_tag_valid_out[0][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9590 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9591 = mux(_T_9590, ic_tag_valid_out[0][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9592 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9593 = mux(_T_9592, ic_tag_valid_out[0][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9594 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9595 = mux(_T_9594, ic_tag_valid_out[0][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9596 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9597 = mux(_T_9596, ic_tag_valid_out[0][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9598 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9599 = mux(_T_9598, ic_tag_valid_out[0][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9600 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9601 = mux(_T_9600, ic_tag_valid_out[0][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9602 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9603 = mux(_T_9602, ic_tag_valid_out[0][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9604 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9605 = mux(_T_9604, ic_tag_valid_out[0][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9606 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9607 = mux(_T_9606, ic_tag_valid_out[0][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9608 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9609 = mux(_T_9608, ic_tag_valid_out[0][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9610 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9611 = mux(_T_9610, ic_tag_valid_out[0][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9612 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9613 = mux(_T_9612, ic_tag_valid_out[0][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9614 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9615 = mux(_T_9614, ic_tag_valid_out[0][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9616 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9617 = mux(_T_9616, ic_tag_valid_out[0][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9618 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9619 = mux(_T_9618, ic_tag_valid_out[0][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9620 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9621 = mux(_T_9620, ic_tag_valid_out[0][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9622 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9623 = mux(_T_9622, ic_tag_valid_out[0][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9624 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9625 = mux(_T_9624, ic_tag_valid_out[0][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9626 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9627 = mux(_T_9626, ic_tag_valid_out[0][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9628 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9629 = mux(_T_9628, ic_tag_valid_out[0][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9630 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9631 = mux(_T_9630, ic_tag_valid_out[0][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9632 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9633 = mux(_T_9632, ic_tag_valid_out[0][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9634 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9635 = mux(_T_9634, ic_tag_valid_out[0][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9636 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9637 = mux(_T_9636, ic_tag_valid_out[0][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9638 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9639 = mux(_T_9638, ic_tag_valid_out[0][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9640 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9641 = mux(_T_9640, ic_tag_valid_out[0][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9642 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9643 = mux(_T_9642, ic_tag_valid_out[0][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9644 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9645 = mux(_T_9644, ic_tag_valid_out[0][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9646 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9647 = mux(_T_9646, ic_tag_valid_out[0][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9648 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9649 = mux(_T_9648, ic_tag_valid_out[0][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9650 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9651 = mux(_T_9650, ic_tag_valid_out[0][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9652 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9653 = mux(_T_9652, ic_tag_valid_out[0][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9654 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9655 = mux(_T_9654, ic_tag_valid_out[0][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9656 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9657 = mux(_T_9656, ic_tag_valid_out[0][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9658 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9659 = mux(_T_9658, ic_tag_valid_out[0][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9660 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9661 = mux(_T_9660, ic_tag_valid_out[0][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9662 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9663 = mux(_T_9662, ic_tag_valid_out[0][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9664 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9665 = mux(_T_9664, ic_tag_valid_out[0][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9666 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9667 = mux(_T_9666, ic_tag_valid_out[0][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9668 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9669 = mux(_T_9668, ic_tag_valid_out[0][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9671 = mux(_T_9670, ic_tag_valid_out[0][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9672 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9673 = mux(_T_9672, ic_tag_valid_out[0][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9674 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9675 = mux(_T_9674, ic_tag_valid_out[0][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9676 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9677 = mux(_T_9676, ic_tag_valid_out[0][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9678 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9679 = mux(_T_9678, ic_tag_valid_out[0][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9680 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9681 = mux(_T_9680, ic_tag_valid_out[0][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9682 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9683 = mux(_T_9682, ic_tag_valid_out[0][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9684 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9685 = mux(_T_9684, ic_tag_valid_out[0][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9686 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9687 = mux(_T_9686, ic_tag_valid_out[0][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9688 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9689 = mux(_T_9688, ic_tag_valid_out[0][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9690 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9691 = mux(_T_9690, ic_tag_valid_out[0][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9692 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9693 = mux(_T_9692, ic_tag_valid_out[0][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9694 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9695 = mux(_T_9694, ic_tag_valid_out[0][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9696 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9697 = mux(_T_9696, ic_tag_valid_out[0][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9698 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9699 = mux(_T_9698, ic_tag_valid_out[0][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9700 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9701 = mux(_T_9700, ic_tag_valid_out[0][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9702 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9703 = mux(_T_9702, ic_tag_valid_out[0][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9704 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9705 = mux(_T_9704, ic_tag_valid_out[0][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9707 = mux(_T_9706, ic_tag_valid_out[0][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9708 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9709 = mux(_T_9708, ic_tag_valid_out[0][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9711 = mux(_T_9710, ic_tag_valid_out[0][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9713 = mux(_T_9712, ic_tag_valid_out[0][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9714 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9715 = mux(_T_9714, ic_tag_valid_out[0][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9716 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9717 = mux(_T_9716, ic_tag_valid_out[0][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9718 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9719 = mux(_T_9718, ic_tag_valid_out[0][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9721 = mux(_T_9720, ic_tag_valid_out[0][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9722 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9723 = mux(_T_9722, ic_tag_valid_out[0][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9724 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9725 = mux(_T_9724, ic_tag_valid_out[0][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9726 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9727 = mux(_T_9726, ic_tag_valid_out[0][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9728 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9729 = mux(_T_9728, ic_tag_valid_out[0][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9730 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9731 = mux(_T_9730, ic_tag_valid_out[0][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9733 = mux(_T_9732, ic_tag_valid_out[0][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9734 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9735 = mux(_T_9734, ic_tag_valid_out[0][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9737 = mux(_T_9736, ic_tag_valid_out[0][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9739 = mux(_T_9738, ic_tag_valid_out[0][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9741 = mux(_T_9740, ic_tag_valid_out[0][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9743 = mux(_T_9742, ic_tag_valid_out[0][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9745 = mux(_T_9744, ic_tag_valid_out[0][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9747 = mux(_T_9746, ic_tag_valid_out[0][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9749 = mux(_T_9748, ic_tag_valid_out[0][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9751 = mux(_T_9750, ic_tag_valid_out[0][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9753 = mux(_T_9752, ic_tag_valid_out[0][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9755 = mux(_T_9754, ic_tag_valid_out[0][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9757 = mux(_T_9756, ic_tag_valid_out[0][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9759 = mux(_T_9758, ic_tag_valid_out[0][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9761 = mux(_T_9760, ic_tag_valid_out[0][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9763 = mux(_T_9762, ic_tag_valid_out[0][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9765 = mux(_T_9764, ic_tag_valid_out[0][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9767 = mux(_T_9766, ic_tag_valid_out[0][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9769 = mux(_T_9768, ic_tag_valid_out[0][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9771 = mux(_T_9770, ic_tag_valid_out[0][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9773 = mux(_T_9772, ic_tag_valid_out[0][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9775 = mux(_T_9774, ic_tag_valid_out[0][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9777 = mux(_T_9776, ic_tag_valid_out[0][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9779 = mux(_T_9778, ic_tag_valid_out[0][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9781 = mux(_T_9780, ic_tag_valid_out[0][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9782 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9783 = mux(_T_9782, ic_tag_valid_out[0][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9785 = mux(_T_9784, ic_tag_valid_out[0][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9787 = mux(_T_9786, ic_tag_valid_out[0][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9789 = mux(_T_9788, ic_tag_valid_out[0][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9790 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9791 = mux(_T_9790, ic_tag_valid_out[0][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9793 = mux(_T_9792, ic_tag_valid_out[0][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9795 = mux(_T_9794, ic_tag_valid_out[0][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9797 = mux(_T_9796, ic_tag_valid_out[0][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9798 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9799 = mux(_T_9798, ic_tag_valid_out[0][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9801 = mux(_T_9800, ic_tag_valid_out[0][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9802 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9803 = mux(_T_9802, ic_tag_valid_out[0][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9805 = mux(_T_9804, ic_tag_valid_out[0][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9806 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9807 = mux(_T_9806, ic_tag_valid_out[0][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9809 = mux(_T_9808, ic_tag_valid_out[0][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9811 = mux(_T_9810, ic_tag_valid_out[0][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9813 = mux(_T_9812, ic_tag_valid_out[0][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9814 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9815 = mux(_T_9814, ic_tag_valid_out[0][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9817 = mux(_T_9816, ic_tag_valid_out[0][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9819 = mux(_T_9818, ic_tag_valid_out[0][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9821 = mux(_T_9820, ic_tag_valid_out[0][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9822 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9823 = mux(_T_9822, ic_tag_valid_out[0][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9825 = mux(_T_9824, ic_tag_valid_out[0][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9827 = mux(_T_9826, ic_tag_valid_out[0][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9829 = mux(_T_9828, ic_tag_valid_out[0][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9831 = mux(_T_9830, ic_tag_valid_out[0][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9833 = mux(_T_9832, ic_tag_valid_out[0][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9835 = mux(_T_9834, ic_tag_valid_out[0][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9837 = mux(_T_9836, ic_tag_valid_out[0][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9838 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9839 = mux(_T_9838, ic_tag_valid_out[0][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9841 = mux(_T_9840, ic_tag_valid_out[0][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9842 = or(_T_9587, _T_9589) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9843 = or(_T_9842, _T_9591) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9844 = or(_T_9843, _T_9593) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9845 = or(_T_9844, _T_9595) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9846 = or(_T_9845, _T_9597) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9847 = or(_T_9846, _T_9599) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9848 = or(_T_9847, _T_9601) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9849 = or(_T_9848, _T_9603) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9850 = or(_T_9849, _T_9605) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9851 = or(_T_9850, _T_9607) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9852 = or(_T_9851, _T_9609) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9853 = or(_T_9852, _T_9611) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9854 = or(_T_9853, _T_9613) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9855 = or(_T_9854, _T_9615) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9856 = or(_T_9855, _T_9617) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9857 = or(_T_9856, _T_9619) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9858 = or(_T_9857, _T_9621) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9859 = or(_T_9858, _T_9623) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9860 = or(_T_9859, _T_9625) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9861 = or(_T_9860, _T_9627) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9862 = or(_T_9861, _T_9629) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9863 = or(_T_9862, _T_9631) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9864 = or(_T_9863, _T_9633) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9865 = or(_T_9864, _T_9635) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9866 = or(_T_9865, _T_9637) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9867 = or(_T_9866, _T_9639) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9868 = or(_T_9867, _T_9641) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9869 = or(_T_9868, _T_9643) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9870 = or(_T_9869, _T_9645) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9871 = or(_T_9870, _T_9647) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9872 = or(_T_9871, _T_9649) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9873 = or(_T_9872, _T_9651) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9874 = or(_T_9873, _T_9653) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9875 = or(_T_9874, _T_9655) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9876 = or(_T_9875, _T_9657) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9877 = or(_T_9876, _T_9659) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9878 = or(_T_9877, _T_9661) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9879 = or(_T_9878, _T_9663) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9880 = or(_T_9879, _T_9665) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9881 = or(_T_9880, _T_9667) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9882 = or(_T_9881, _T_9669) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9883 = or(_T_9882, _T_9671) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9884 = or(_T_9883, _T_9673) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9885 = or(_T_9884, _T_9675) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9886 = or(_T_9885, _T_9677) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9887 = or(_T_9886, _T_9679) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9888 = or(_T_9887, _T_9681) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9889 = or(_T_9888, _T_9683) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9890 = or(_T_9889, _T_9685) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9891 = or(_T_9890, _T_9687) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9892 = or(_T_9891, _T_9689) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9893 = or(_T_9892, _T_9691) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9894 = or(_T_9893, _T_9693) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9895 = or(_T_9894, _T_9695) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9896 = or(_T_9895, _T_9697) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9897 = or(_T_9896, _T_9699) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9898 = or(_T_9897, _T_9701) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9899 = or(_T_9898, _T_9703) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9900 = or(_T_9899, _T_9705) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9901 = or(_T_9900, _T_9707) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9902 = or(_T_9901, _T_9709) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9903 = or(_T_9902, _T_9711) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9904 = or(_T_9903, _T_9713) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9905 = or(_T_9904, _T_9715) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9906 = or(_T_9905, _T_9717) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9907 = or(_T_9906, _T_9719) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9908 = or(_T_9907, _T_9721) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9909 = or(_T_9908, _T_9723) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9910 = or(_T_9909, _T_9725) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9911 = or(_T_9910, _T_9727) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9912 = or(_T_9911, _T_9729) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9913 = or(_T_9912, _T_9731) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9914 = or(_T_9913, _T_9733) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9915 = or(_T_9914, _T_9735) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9916 = or(_T_9915, _T_9737) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9917 = or(_T_9916, _T_9739) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9918 = or(_T_9917, _T_9741) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9919 = or(_T_9918, _T_9743) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9920 = or(_T_9919, _T_9745) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9921 = or(_T_9920, _T_9747) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9922 = or(_T_9921, _T_9749) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9923 = or(_T_9922, _T_9751) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9924 = or(_T_9923, _T_9753) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9925 = or(_T_9924, _T_9755) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9926 = or(_T_9925, _T_9757) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9927 = or(_T_9926, _T_9759) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9928 = or(_T_9927, _T_9761) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9929 = or(_T_9928, _T_9763) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9930 = or(_T_9929, _T_9765) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9931 = or(_T_9930, _T_9767) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9932 = or(_T_9931, _T_9769) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9933 = or(_T_9932, _T_9771) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9934 = or(_T_9933, _T_9773) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9935 = or(_T_9934, _T_9775) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9936 = or(_T_9935, _T_9777) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9937 = or(_T_9936, _T_9779) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9938 = or(_T_9937, _T_9781) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9939 = or(_T_9938, _T_9783) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9940 = or(_T_9939, _T_9785) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9941 = or(_T_9940, _T_9787) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9942 = or(_T_9941, _T_9789) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9943 = or(_T_9942, _T_9791) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9944 = or(_T_9943, _T_9793) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9945 = or(_T_9944, _T_9795) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9946 = or(_T_9945, _T_9797) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9947 = or(_T_9946, _T_9799) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9948 = or(_T_9947, _T_9801) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9949 = or(_T_9948, _T_9803) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9950 = or(_T_9949, _T_9805) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9951 = or(_T_9950, _T_9807) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9952 = or(_T_9951, _T_9809) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9953 = or(_T_9952, _T_9811) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9954 = or(_T_9953, _T_9813) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9955 = or(_T_9954, _T_9815) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9956 = or(_T_9955, _T_9817) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9957 = or(_T_9956, _T_9819) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9958 = or(_T_9957, _T_9821) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9959 = or(_T_9958, _T_9823) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9960 = or(_T_9959, _T_9825) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9961 = or(_T_9960, _T_9827) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9962 = or(_T_9961, _T_9829) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9963 = or(_T_9962, _T_9831) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9964 = or(_T_9963, _T_9833) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9965 = or(_T_9964, _T_9835) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9966 = or(_T_9965, _T_9837) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9967 = or(_T_9966, _T_9839) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9968 = or(_T_9967, _T_9841) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_9969 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9970 = mux(_T_9969, ic_tag_valid_out[1][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9971 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9972 = mux(_T_9971, ic_tag_valid_out[1][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9973 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9974 = mux(_T_9973, ic_tag_valid_out[1][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9975 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9976 = mux(_T_9975, ic_tag_valid_out[1][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9977 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9978 = mux(_T_9977, ic_tag_valid_out[1][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9979 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9980 = mux(_T_9979, ic_tag_valid_out[1][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9981 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9982 = mux(_T_9981, ic_tag_valid_out[1][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9983 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9984 = mux(_T_9983, ic_tag_valid_out[1][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9985 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9986 = mux(_T_9985, ic_tag_valid_out[1][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9987 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9988 = mux(_T_9987, ic_tag_valid_out[1][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9989 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9990 = mux(_T_9989, ic_tag_valid_out[1][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9991 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9992 = mux(_T_9991, ic_tag_valid_out[1][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9993 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9994 = mux(_T_9993, ic_tag_valid_out[1][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9995 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9996 = mux(_T_9995, ic_tag_valid_out[1][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9997 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_9998 = mux(_T_9997, ic_tag_valid_out[1][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_9999 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10000 = mux(_T_9999, ic_tag_valid_out[1][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10001 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10002 = mux(_T_10001, ic_tag_valid_out[1][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10003 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10004 = mux(_T_10003, ic_tag_valid_out[1][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10005 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10006 = mux(_T_10005, ic_tag_valid_out[1][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10007 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10008 = mux(_T_10007, ic_tag_valid_out[1][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10009 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10010 = mux(_T_10009, ic_tag_valid_out[1][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10011 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10012 = mux(_T_10011, ic_tag_valid_out[1][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
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node _T_10013 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10014 = mux(_T_10013, ic_tag_valid_out[1][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10015 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10016 = mux(_T_10015, ic_tag_valid_out[1][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10017 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10018 = mux(_T_10017, ic_tag_valid_out[1][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10019 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10020 = mux(_T_10019, ic_tag_valid_out[1][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10021 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10022 = mux(_T_10021, ic_tag_valid_out[1][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10023 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10024 = mux(_T_10023, ic_tag_valid_out[1][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10025 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10026 = mux(_T_10025, ic_tag_valid_out[1][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10027 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10028 = mux(_T_10027, ic_tag_valid_out[1][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10029 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10030 = mux(_T_10029, ic_tag_valid_out[1][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10031 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10032 = mux(_T_10031, ic_tag_valid_out[1][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10033 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10034 = mux(_T_10033, ic_tag_valid_out[1][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10035 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10036 = mux(_T_10035, ic_tag_valid_out[1][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10037 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10038 = mux(_T_10037, ic_tag_valid_out[1][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10039 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10040 = mux(_T_10039, ic_tag_valid_out[1][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10041 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10042 = mux(_T_10041, ic_tag_valid_out[1][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10043 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10044 = mux(_T_10043, ic_tag_valid_out[1][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10046 = mux(_T_10045, ic_tag_valid_out[1][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10047 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10048 = mux(_T_10047, ic_tag_valid_out[1][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10049 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10050 = mux(_T_10049, ic_tag_valid_out[1][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10051 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10052 = mux(_T_10051, ic_tag_valid_out[1][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10053 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10054 = mux(_T_10053, ic_tag_valid_out[1][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10055 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10056 = mux(_T_10055, ic_tag_valid_out[1][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10057 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10058 = mux(_T_10057, ic_tag_valid_out[1][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10059 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10060 = mux(_T_10059, ic_tag_valid_out[1][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10061 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10062 = mux(_T_10061, ic_tag_valid_out[1][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10063 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10064 = mux(_T_10063, ic_tag_valid_out[1][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10065 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10066 = mux(_T_10065, ic_tag_valid_out[1][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10067 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10068 = mux(_T_10067, ic_tag_valid_out[1][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10069 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10070 = mux(_T_10069, ic_tag_valid_out[1][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10071 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10072 = mux(_T_10071, ic_tag_valid_out[1][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10073 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10074 = mux(_T_10073, ic_tag_valid_out[1][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10075 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10076 = mux(_T_10075, ic_tag_valid_out[1][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10077 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10078 = mux(_T_10077, ic_tag_valid_out[1][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10079 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10080 = mux(_T_10079, ic_tag_valid_out[1][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10081 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10082 = mux(_T_10081, ic_tag_valid_out[1][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10083 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10084 = mux(_T_10083, ic_tag_valid_out[1][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10085 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10086 = mux(_T_10085, ic_tag_valid_out[1][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10087 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10088 = mux(_T_10087, ic_tag_valid_out[1][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10089 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10090 = mux(_T_10089, ic_tag_valid_out[1][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10091 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10092 = mux(_T_10091, ic_tag_valid_out[1][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10093 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10094 = mux(_T_10093, ic_tag_valid_out[1][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10095 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10096 = mux(_T_10095, ic_tag_valid_out[1][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10097 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10098 = mux(_T_10097, ic_tag_valid_out[1][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10099 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10100 = mux(_T_10099, ic_tag_valid_out[1][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10101 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10102 = mux(_T_10101, ic_tag_valid_out[1][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10103 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10104 = mux(_T_10103, ic_tag_valid_out[1][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10106 = mux(_T_10105, ic_tag_valid_out[1][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10107 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10108 = mux(_T_10107, ic_tag_valid_out[1][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10109 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10110 = mux(_T_10109, ic_tag_valid_out[1][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10111 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10112 = mux(_T_10111, ic_tag_valid_out[1][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10113 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10114 = mux(_T_10113, ic_tag_valid_out[1][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10115 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10116 = mux(_T_10115, ic_tag_valid_out[1][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10117 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10118 = mux(_T_10117, ic_tag_valid_out[1][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10119 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10120 = mux(_T_10119, ic_tag_valid_out[1][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10121 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10122 = mux(_T_10121, ic_tag_valid_out[1][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10123 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10124 = mux(_T_10123, ic_tag_valid_out[1][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10126 = mux(_T_10125, ic_tag_valid_out[1][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10127 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10128 = mux(_T_10127, ic_tag_valid_out[1][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10129 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10130 = mux(_T_10129, ic_tag_valid_out[1][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10131 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10132 = mux(_T_10131, ic_tag_valid_out[1][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10133 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10134 = mux(_T_10133, ic_tag_valid_out[1][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10136 = mux(_T_10135, ic_tag_valid_out[1][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10137 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10138 = mux(_T_10137, ic_tag_valid_out[1][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10139 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10140 = mux(_T_10139, ic_tag_valid_out[1][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10141 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10142 = mux(_T_10141, ic_tag_valid_out[1][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10143 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10144 = mux(_T_10143, ic_tag_valid_out[1][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10145 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10146 = mux(_T_10145, ic_tag_valid_out[1][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
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node _T_10147 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 760:33]
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node _T_10148 = mux(_T_10147, ic_tag_valid_out[1][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10149 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10150 = mux(_T_10149, ic_tag_valid_out[1][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10151 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10152 = mux(_T_10151, ic_tag_valid_out[1][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10153 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10154 = mux(_T_10153, ic_tag_valid_out[1][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10156 = mux(_T_10155, ic_tag_valid_out[1][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10157 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10158 = mux(_T_10157, ic_tag_valid_out[1][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10159 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10160 = mux(_T_10159, ic_tag_valid_out[1][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10161 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10162 = mux(_T_10161, ic_tag_valid_out[1][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10163 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10164 = mux(_T_10163, ic_tag_valid_out[1][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10166 = mux(_T_10165, ic_tag_valid_out[1][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10167 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10168 = mux(_T_10167, ic_tag_valid_out[1][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10169 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10170 = mux(_T_10169, ic_tag_valid_out[1][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10171 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10172 = mux(_T_10171, ic_tag_valid_out[1][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10173 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10174 = mux(_T_10173, ic_tag_valid_out[1][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10175 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10176 = mux(_T_10175, ic_tag_valid_out[1][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10177 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10178 = mux(_T_10177, ic_tag_valid_out[1][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10179 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10180 = mux(_T_10179, ic_tag_valid_out[1][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10181 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10182 = mux(_T_10181, ic_tag_valid_out[1][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10183 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10184 = mux(_T_10183, ic_tag_valid_out[1][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10186 = mux(_T_10185, ic_tag_valid_out[1][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10187 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10188 = mux(_T_10187, ic_tag_valid_out[1][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10189 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10190 = mux(_T_10189, ic_tag_valid_out[1][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10191 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10192 = mux(_T_10191, ic_tag_valid_out[1][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10193 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10194 = mux(_T_10193, ic_tag_valid_out[1][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10195 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10196 = mux(_T_10195, ic_tag_valid_out[1][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10197 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10198 = mux(_T_10197, ic_tag_valid_out[1][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10199 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10200 = mux(_T_10199, ic_tag_valid_out[1][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10201 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10202 = mux(_T_10201, ic_tag_valid_out[1][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10203 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10204 = mux(_T_10203, ic_tag_valid_out[1][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10205 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10206 = mux(_T_10205, ic_tag_valid_out[1][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10207 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10208 = mux(_T_10207, ic_tag_valid_out[1][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10209 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10210 = mux(_T_10209, ic_tag_valid_out[1][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10211 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10212 = mux(_T_10211, ic_tag_valid_out[1][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10213 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10214 = mux(_T_10213, ic_tag_valid_out[1][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10215 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10216 = mux(_T_10215, ic_tag_valid_out[1][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10217 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10218 = mux(_T_10217, ic_tag_valid_out[1][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10219 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10220 = mux(_T_10219, ic_tag_valid_out[1][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10221 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10222 = mux(_T_10221, ic_tag_valid_out[1][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10223 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 760:33]
|
|
node _T_10224 = mux(_T_10223, ic_tag_valid_out[1][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:10]
|
|
node _T_10225 = or(_T_9970, _T_9972) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10226 = or(_T_10225, _T_9974) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10227 = or(_T_10226, _T_9976) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10228 = or(_T_10227, _T_9978) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10229 = or(_T_10228, _T_9980) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10230 = or(_T_10229, _T_9982) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10231 = or(_T_10230, _T_9984) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10232 = or(_T_10231, _T_9986) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10233 = or(_T_10232, _T_9988) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10234 = or(_T_10233, _T_9990) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10235 = or(_T_10234, _T_9992) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10236 = or(_T_10235, _T_9994) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10237 = or(_T_10236, _T_9996) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10238 = or(_T_10237, _T_9998) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10239 = or(_T_10238, _T_10000) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10240 = or(_T_10239, _T_10002) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10241 = or(_T_10240, _T_10004) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10242 = or(_T_10241, _T_10006) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10243 = or(_T_10242, _T_10008) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10244 = or(_T_10243, _T_10010) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10245 = or(_T_10244, _T_10012) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10246 = or(_T_10245, _T_10014) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10247 = or(_T_10246, _T_10016) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10248 = or(_T_10247, _T_10018) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10249 = or(_T_10248, _T_10020) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10250 = or(_T_10249, _T_10022) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10251 = or(_T_10250, _T_10024) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10252 = or(_T_10251, _T_10026) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10253 = or(_T_10252, _T_10028) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10254 = or(_T_10253, _T_10030) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10255 = or(_T_10254, _T_10032) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10256 = or(_T_10255, _T_10034) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10257 = or(_T_10256, _T_10036) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10258 = or(_T_10257, _T_10038) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10259 = or(_T_10258, _T_10040) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10260 = or(_T_10259, _T_10042) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10261 = or(_T_10260, _T_10044) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10262 = or(_T_10261, _T_10046) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10263 = or(_T_10262, _T_10048) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10264 = or(_T_10263, _T_10050) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10265 = or(_T_10264, _T_10052) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10266 = or(_T_10265, _T_10054) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10267 = or(_T_10266, _T_10056) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10268 = or(_T_10267, _T_10058) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10269 = or(_T_10268, _T_10060) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10270 = or(_T_10269, _T_10062) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10271 = or(_T_10270, _T_10064) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10272 = or(_T_10271, _T_10066) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10273 = or(_T_10272, _T_10068) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10274 = or(_T_10273, _T_10070) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10275 = or(_T_10274, _T_10072) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10276 = or(_T_10275, _T_10074) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10277 = or(_T_10276, _T_10076) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10278 = or(_T_10277, _T_10078) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10279 = or(_T_10278, _T_10080) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10280 = or(_T_10279, _T_10082) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10281 = or(_T_10280, _T_10084) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10282 = or(_T_10281, _T_10086) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10283 = or(_T_10282, _T_10088) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10284 = or(_T_10283, _T_10090) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10285 = or(_T_10284, _T_10092) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10286 = or(_T_10285, _T_10094) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10287 = or(_T_10286, _T_10096) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10288 = or(_T_10287, _T_10098) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10289 = or(_T_10288, _T_10100) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10290 = or(_T_10289, _T_10102) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10291 = or(_T_10290, _T_10104) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10292 = or(_T_10291, _T_10106) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10293 = or(_T_10292, _T_10108) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10294 = or(_T_10293, _T_10110) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10295 = or(_T_10294, _T_10112) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10296 = or(_T_10295, _T_10114) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10297 = or(_T_10296, _T_10116) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10298 = or(_T_10297, _T_10118) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10299 = or(_T_10298, _T_10120) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10300 = or(_T_10299, _T_10122) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10301 = or(_T_10300, _T_10124) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10302 = or(_T_10301, _T_10126) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10303 = or(_T_10302, _T_10128) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10304 = or(_T_10303, _T_10130) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10305 = or(_T_10304, _T_10132) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10306 = or(_T_10305, _T_10134) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10307 = or(_T_10306, _T_10136) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10308 = or(_T_10307, _T_10138) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10309 = or(_T_10308, _T_10140) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10310 = or(_T_10309, _T_10142) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10311 = or(_T_10310, _T_10144) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10312 = or(_T_10311, _T_10146) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10313 = or(_T_10312, _T_10148) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10314 = or(_T_10313, _T_10150) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10315 = or(_T_10314, _T_10152) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10316 = or(_T_10315, _T_10154) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10317 = or(_T_10316, _T_10156) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10318 = or(_T_10317, _T_10158) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10319 = or(_T_10318, _T_10160) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10320 = or(_T_10319, _T_10162) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10321 = or(_T_10320, _T_10164) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10322 = or(_T_10321, _T_10166) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10323 = or(_T_10322, _T_10168) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10324 = or(_T_10323, _T_10170) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10325 = or(_T_10324, _T_10172) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10326 = or(_T_10325, _T_10174) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10327 = or(_T_10326, _T_10176) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10328 = or(_T_10327, _T_10178) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10329 = or(_T_10328, _T_10180) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10330 = or(_T_10329, _T_10182) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10331 = or(_T_10330, _T_10184) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10332 = or(_T_10331, _T_10186) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10333 = or(_T_10332, _T_10188) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10334 = or(_T_10333, _T_10190) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10335 = or(_T_10334, _T_10192) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10336 = or(_T_10335, _T_10194) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10337 = or(_T_10336, _T_10196) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10338 = or(_T_10337, _T_10198) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10339 = or(_T_10338, _T_10200) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10340 = or(_T_10339, _T_10202) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10341 = or(_T_10340, _T_10204) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10342 = or(_T_10341, _T_10206) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10343 = or(_T_10342, _T_10208) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10344 = or(_T_10343, _T_10210) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10345 = or(_T_10344, _T_10212) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10346 = or(_T_10345, _T_10214) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10347 = or(_T_10346, _T_10216) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10348 = or(_T_10347, _T_10218) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10349 = or(_T_10348, _T_10220) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10350 = or(_T_10349, _T_10222) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node _T_10351 = or(_T_10350, _T_10224) @[el2_ifu_mem_ctl.scala 760:91]
|
|
node ic_tag_valid_unq = cat(_T_10351, _T_9968) @[Cat.scala 29:58]
|
|
wire way_status_hit_new : UInt<1>
|
|
way_status_hit_new <= UInt<1>("h00")
|
|
node _T_10352 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 785:33]
|
|
node _T_10353 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 785:63]
|
|
node _T_10354 = and(_T_10352, _T_10353) @[el2_ifu_mem_ctl.scala 785:51]
|
|
node _T_10355 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 785:79]
|
|
node _T_10356 = and(_T_10354, _T_10355) @[el2_ifu_mem_ctl.scala 785:67]
|
|
node _T_10357 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 785:97]
|
|
node _T_10358 = eq(_T_10357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 785:86]
|
|
node _T_10359 = or(_T_10356, _T_10358) @[el2_ifu_mem_ctl.scala 785:84]
|
|
replace_way_mb_any[0] <= _T_10359 @[el2_ifu_mem_ctl.scala 785:29]
|
|
node _T_10360 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 786:62]
|
|
node _T_10361 = and(way_status_mb_ff, _T_10360) @[el2_ifu_mem_ctl.scala 786:50]
|
|
node _T_10362 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 786:78]
|
|
node _T_10363 = and(_T_10361, _T_10362) @[el2_ifu_mem_ctl.scala 786:66]
|
|
node _T_10364 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 786:96]
|
|
node _T_10365 = eq(_T_10364, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 786:85]
|
|
node _T_10366 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 786:112]
|
|
node _T_10367 = and(_T_10365, _T_10366) @[el2_ifu_mem_ctl.scala 786:100]
|
|
node _T_10368 = or(_T_10363, _T_10367) @[el2_ifu_mem_ctl.scala 786:83]
|
|
replace_way_mb_any[1] <= _T_10368 @[el2_ifu_mem_ctl.scala 786:29]
|
|
node _T_10369 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 787:41]
|
|
way_status_hit_new <= _T_10369 @[el2_ifu_mem_ctl.scala 787:26]
|
|
way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 788:26]
|
|
node _T_10370 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 790:47]
|
|
node _T_10371 = bits(_T_10370, 0, 0) @[el2_ifu_mem_ctl.scala 790:60]
|
|
node _T_10372 = mux(_T_10371, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 790:26]
|
|
way_status_new <= _T_10372 @[el2_ifu_mem_ctl.scala 790:20]
|
|
node _T_10373 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 791:45]
|
|
node _T_10374 = or(_T_10373, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 791:58]
|
|
way_status_wr_en <= _T_10374 @[el2_ifu_mem_ctl.scala 791:22]
|
|
node _T_10375 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 792:74]
|
|
node bus_wren_0 = and(_T_10375, miss_pending) @[el2_ifu_mem_ctl.scala 792:98]
|
|
node _T_10376 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 792:74]
|
|
node bus_wren_1 = and(_T_10376, miss_pending) @[el2_ifu_mem_ctl.scala 792:98]
|
|
node _T_10377 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 794:84]
|
|
node _T_10378 = and(_T_10377, miss_pending) @[el2_ifu_mem_ctl.scala 794:108]
|
|
node bus_wren_last_0 = and(_T_10378, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 794:123]
|
|
node _T_10379 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 794:84]
|
|
node _T_10380 = and(_T_10379, miss_pending) @[el2_ifu_mem_ctl.scala 794:108]
|
|
node bus_wren_last_1 = and(_T_10380, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 794:123]
|
|
node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 795:84]
|
|
node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 795:84]
|
|
node _T_10381 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 796:73]
|
|
node _T_10382 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 796:73]
|
|
node _T_10383 = cat(_T_10382, _T_10381) @[Cat.scala 29:58]
|
|
ifu_tag_wren <= _T_10383 @[el2_ifu_mem_ctl.scala 796:18]
|
|
node _T_10384 = cat(bus_wren_1, bus_wren_0) @[Cat.scala 29:58]
|
|
bus_ic_wr_en <= _T_10384 @[el2_ifu_mem_ctl.scala 798:16]
|
|
node _T_10385 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 812:63]
|
|
node _T_10386 = and(_T_10385, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 812:85]
|
|
node _T_10387 = bits(_T_10386, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10388 = mux(_T_10387, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10389 = and(ic_tag_valid_unq, _T_10388) @[el2_ifu_mem_ctl.scala 812:39]
|
|
io.ic_tag_valid <= _T_10389 @[el2_ifu_mem_ctl.scala 812:19]
|
|
wire ic_debug_way_ff : UInt<2>
|
|
ic_debug_way_ff <= UInt<1>("h00")
|
|
node _T_10390 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10391 = mux(_T_10390, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10392 = and(ic_debug_way_ff, _T_10391) @[el2_ifu_mem_ctl.scala 815:67]
|
|
node _T_10393 = and(ic_tag_valid_unq, _T_10392) @[el2_ifu_mem_ctl.scala 815:48]
|
|
node _T_10394 = orr(_T_10393) @[el2_ifu_mem_ctl.scala 815:115]
|
|
ic_debug_tag_val_rd_out <= _T_10394 @[el2_ifu_mem_ctl.scala 815:27]
|
|
reg _T_10395 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:57]
|
|
_T_10395 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 817:57]
|
|
io.ifu_pmu_ic_miss <= _T_10395 @[el2_ifu_mem_ctl.scala 817:22]
|
|
reg _T_10396 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 818:56]
|
|
_T_10396 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 818:56]
|
|
io.ifu_pmu_ic_hit <= _T_10396 @[el2_ifu_mem_ctl.scala 818:21]
|
|
reg _T_10397 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 819:59]
|
|
_T_10397 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 819:59]
|
|
io.ifu_pmu_bus_error <= _T_10397 @[el2_ifu_mem_ctl.scala 819:24]
|
|
node _T_10398 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 820:80]
|
|
node _T_10399 = and(ifu_bus_arvalid_ff, _T_10398) @[el2_ifu_mem_ctl.scala 820:78]
|
|
node _T_10400 = and(_T_10399, miss_pending) @[el2_ifu_mem_ctl.scala 820:100]
|
|
reg _T_10401 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 820:58]
|
|
_T_10401 <= _T_10400 @[el2_ifu_mem_ctl.scala 820:58]
|
|
io.ifu_pmu_bus_busy <= _T_10401 @[el2_ifu_mem_ctl.scala 820:23]
|
|
reg _T_10402 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 821:58]
|
|
_T_10402 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 821:58]
|
|
io.ifu_pmu_bus_trxn <= _T_10402 @[el2_ifu_mem_ctl.scala 821:23]
|
|
io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 824:20]
|
|
node _T_10403 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 825:66]
|
|
io.ic_debug_tag_array <= _T_10403 @[el2_ifu_mem_ctl.scala 825:25]
|
|
io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 826:21]
|
|
io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 827:21]
|
|
node _T_10404 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 828:64]
|
|
node _T_10405 = eq(_T_10404, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 828:71]
|
|
node _T_10406 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 828:117]
|
|
node _T_10407 = eq(_T_10406, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 828:124]
|
|
node _T_10408 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 829:43]
|
|
node _T_10409 = eq(_T_10408, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 829:50]
|
|
node _T_10410 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 829:96]
|
|
node _T_10411 = eq(_T_10410, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 829:103]
|
|
node _T_10412 = cat(_T_10409, _T_10411) @[Cat.scala 29:58]
|
|
node _T_10413 = cat(_T_10405, _T_10407) @[Cat.scala 29:58]
|
|
node _T_10414 = cat(_T_10413, _T_10412) @[Cat.scala 29:58]
|
|
io.ic_debug_way <= _T_10414 @[el2_ifu_mem_ctl.scala 828:19]
|
|
node _T_10415 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 830:65]
|
|
node _T_10416 = bits(_T_10415, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10417 = mux(_T_10416, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10418 = and(_T_10417, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 830:90]
|
|
ic_debug_tag_wr_en <= _T_10418 @[el2_ifu_mem_ctl.scala 830:22]
|
|
node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 831:53]
|
|
reg _T_10419 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 832:53]
|
|
_T_10419 <= io.ic_debug_way @[el2_ifu_mem_ctl.scala 832:53]
|
|
ic_debug_way_ff <= _T_10419 @[el2_ifu_mem_ctl.scala 832:19]
|
|
reg _T_10420 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 833:63]
|
|
_T_10420 <= ic_debug_ict_array_sel_in @[el2_ifu_mem_ctl.scala 833:63]
|
|
ic_debug_ict_array_sel_ff <= _T_10420 @[el2_ifu_mem_ctl.scala 833:29]
|
|
reg _T_10421 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 834:54]
|
|
_T_10421 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 834:54]
|
|
ic_debug_rd_en_ff <= _T_10421 @[el2_ifu_mem_ctl.scala 834:21]
|
|
node _T_10422 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 835:111]
|
|
reg _T_10423 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10422 : @[Reg.scala 28:19]
|
|
_T_10423 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.ifu_ic_debug_rd_data_valid <= _T_10423 @[el2_ifu_mem_ctl.scala 835:33]
|
|
node _T_10424 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10425 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10426 = cat(_T_10425, _T_10424) @[Cat.scala 29:58]
|
|
node _T_10427 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10428 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10429 = cat(_T_10428, _T_10427) @[Cat.scala 29:58]
|
|
node _T_10430 = cat(_T_10429, _T_10426) @[Cat.scala 29:58]
|
|
node _T_10431 = orr(_T_10430) @[el2_ifu_mem_ctl.scala 836:213]
|
|
node _T_10432 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10433 = or(_T_10432, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 837:62]
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node _T_10434 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 837:110]
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node _T_10435 = eq(_T_10433, _T_10434) @[el2_ifu_mem_ctl.scala 837:85]
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node _T_10436 = and(UInt<1>("h01"), _T_10435) @[el2_ifu_mem_ctl.scala 837:27]
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node _T_10437 = or(_T_10431, _T_10436) @[el2_ifu_mem_ctl.scala 836:216]
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node _T_10438 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10439 = or(_T_10438, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 838:62]
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node _T_10440 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 838:110]
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node _T_10441 = eq(_T_10439, _T_10440) @[el2_ifu_mem_ctl.scala 838:85]
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node _T_10442 = and(UInt<1>("h01"), _T_10441) @[el2_ifu_mem_ctl.scala 838:27]
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node _T_10443 = or(_T_10437, _T_10442) @[el2_ifu_mem_ctl.scala 837:134]
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node _T_10444 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10445 = or(_T_10444, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 839:62]
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node _T_10446 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 839:110]
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node _T_10447 = eq(_T_10445, _T_10446) @[el2_ifu_mem_ctl.scala 839:85]
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node _T_10448 = and(UInt<1>("h01"), _T_10447) @[el2_ifu_mem_ctl.scala 839:27]
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node _T_10449 = or(_T_10443, _T_10448) @[el2_ifu_mem_ctl.scala 838:134]
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node _T_10450 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10451 = or(_T_10450, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 840:62]
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node _T_10452 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 840:110]
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node _T_10453 = eq(_T_10451, _T_10452) @[el2_ifu_mem_ctl.scala 840:85]
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node _T_10454 = and(UInt<1>("h01"), _T_10453) @[el2_ifu_mem_ctl.scala 840:27]
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node _T_10455 = or(_T_10449, _T_10454) @[el2_ifu_mem_ctl.scala 839:134]
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node _T_10456 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10457 = or(_T_10456, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:62]
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node _T_10458 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:110]
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node _T_10459 = eq(_T_10457, _T_10458) @[el2_ifu_mem_ctl.scala 841:85]
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node _T_10460 = and(UInt<1>("h00"), _T_10459) @[el2_ifu_mem_ctl.scala 841:27]
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node _T_10461 = or(_T_10455, _T_10460) @[el2_ifu_mem_ctl.scala 840:134]
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node _T_10462 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10463 = or(_T_10462, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:62]
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node _T_10464 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:110]
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node _T_10465 = eq(_T_10463, _T_10464) @[el2_ifu_mem_ctl.scala 842:85]
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node _T_10466 = and(UInt<1>("h00"), _T_10465) @[el2_ifu_mem_ctl.scala 842:27]
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node _T_10467 = or(_T_10461, _T_10466) @[el2_ifu_mem_ctl.scala 841:134]
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node _T_10468 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10469 = or(_T_10468, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:62]
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node _T_10470 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:110]
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node _T_10471 = eq(_T_10469, _T_10470) @[el2_ifu_mem_ctl.scala 843:85]
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node _T_10472 = and(UInt<1>("h00"), _T_10471) @[el2_ifu_mem_ctl.scala 843:27]
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node _T_10473 = or(_T_10467, _T_10472) @[el2_ifu_mem_ctl.scala 842:134]
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node _T_10474 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_10475 = or(_T_10474, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 844:62]
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node _T_10476 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 844:110]
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node _T_10477 = eq(_T_10475, _T_10476) @[el2_ifu_mem_ctl.scala 844:85]
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node _T_10478 = and(UInt<1>("h00"), _T_10477) @[el2_ifu_mem_ctl.scala 844:27]
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node ifc_region_acc_okay = or(_T_10473, _T_10478) @[el2_ifu_mem_ctl.scala 843:134]
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node _T_10479 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 845:40]
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node _T_10480 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 845:65]
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node _T_10481 = and(_T_10479, _T_10480) @[el2_ifu_mem_ctl.scala 845:63]
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node ifc_region_acc_fault_memory_bf = and(_T_10481, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 845:86]
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node _T_10482 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 846:63]
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ifc_region_acc_fault_final_bf <= _T_10482 @[el2_ifu_mem_ctl.scala 846:33]
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reg _T_10483 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 847:66]
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_T_10483 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 847:66]
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ifc_region_acc_fault_memory_f <= _T_10483 @[el2_ifu_mem_ctl.scala 847:33]
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