336 lines
18 KiB
Scala
336 lines
18 KiB
Scala
package lib
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import chisel3._
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import chisel3.util._
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import include._
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class axi4_to_ahb_IO(val TAG : Int) extends Bundle {
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val free_clk = Input(Clock())
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val scan_mode = Input(Bool())
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val bus_clk_en = Input(Bool())
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val clk_override = Input(Bool())
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val dec_tlu_force_halt = Input(Bool())
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// AXI-4 signals
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val axi = Flipped(new axi_channels(TAG))
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// AHB-Lite signals
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val ahb = new ahb_channel()
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}
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class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncReset {
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val io = IO(new axi4_to_ahb_IO(TAG))
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// Create bus synchronized version of force halt
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val dec_tlu_force_halt_bus_q = WireInit(Bool(), init = false.B)
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val dec_tlu_force_halt_bus = io.dec_tlu_force_halt | dec_tlu_force_halt_bus_q
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val dec_tlu_force_halt_bus_ns = !io.bus_clk_en & dec_tlu_force_halt_bus
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dec_tlu_force_halt_bus_q := withClock(io.free_clk) {RegNext(dec_tlu_force_halt_bus_ns, 0.U)}
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val buf_rst = WireInit(0.U(1.W))
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buf_rst := dec_tlu_force_halt_bus
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io.ahb.out.htrans := 0.U
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val buf_state_en = WireInit(Bool(), init = false.B)
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val bus_clk = Wire(Clock())
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val ahbm_data_clk = Wire(Clock())
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val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
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val buf_state = WireInit(0.U(3.W))
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val buf_nxtstate = WireInit(0.U(3.W))
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buf_state := rvdffsc_fpga(buf_nxtstate, buf_state_en.asBool(), buf_rst, bus_clk, io.bus_clk_en, clock)
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//logic signals
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val slave_valid = WireInit(Bool(), init = false.B)
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val slave_ready = WireInit(Bool(), init = false.B)
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val slave_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val slave_rdata = WireInit(0.U(64.W)) // [63:0]
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val slave_opc = WireInit(0.U(4.W)) // [3:0]
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val wrbuf_en = WireInit(Bool(), init = false.B)
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val wrbuf_data_en = WireInit(Bool(), init = false.B)
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val wrbuf_cmd_sent = WireInit(Bool(), init = false.B)
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val wrbuf_rst = WireInit(Bool(), init = false.B)
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val wrbuf_vld = WireInit(Bool(), init = false.B)
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val wrbuf_data_vld = WireInit(Bool(), init = false.B)
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val wrbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val wrbuf_size = WireInit(0.U(3.W)) // [2:0]
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val wrbuf_addr = WireInit(0.U(32.W)) // [31:0]
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val wrbuf_data = WireInit(0.U(64.W)) // [63:0]
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val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0]
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val master_valid = WireInit(Bool(), init = false.B)
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val master_ready = WireInit(0.U(1.W))
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val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val master_addr = WireInit(0.U(32.W)) // [31:0]
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val master_wdata = WireInit(0.U(64.W)) // [63:0]
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val master_size = WireInit(0.U(3.W)) // [2:0]
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val master_opc = WireInit(0.U(3.W)) // [2:0]
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val master_byteen = WireInit(0.U(8.W)) // [7:0]
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// Buffer signals (one entry buffer)
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val buf_addr = WireInit(0.U(32.W)) // [31:0]
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val buf_size = WireInit(0.U(2.W)) // [1:0]
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val buf_write = WireInit(Bool(), init = false.B)
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val buf_byteen = WireInit(0.U(8.W)) // [7:0]
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val buf_aligned = WireInit(Bool(), init = false.B)
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val buf_data = WireInit(0.U(64.W)) // [63:0]
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val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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//Miscellaneous signals
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// val buf_rst = WireInit(Bool(), init = false.B)
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val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
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val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
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val buf_data_in = WireInit(0.U(64.W)) // [63:0]
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val buf_write_in = WireInit(Bool(), init = false.B)
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val buf_aligned_in = WireInit(Bool(), init = false.B)
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val buf_size_in = WireInit(0.U(3.W)) // [2:0]
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// val buf_state_en = WireInit(Bool(), init = false.B)
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val buf_wr_en = WireInit(Bool(), init = false.B)
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val buf_data_wr_en = WireInit(Bool(), init = false.B)
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val slvbuf_error_en = WireInit(Bool(), init = false.B)
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val wr_cmd_vld = WireInit(Bool(), init = false.B)
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val cmd_done_rst = WireInit(Bool(), init = false.B)
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val cmd_done = WireInit(Bool(), init = false.B)
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val cmd_doneQ = WireInit(Bool(), init = false.B)
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val trxn_done = WireInit(Bool(), init = false.B)
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val buf_cmd_byte_ptr = WireInit(0.U(3.W)) // [2:0]
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val buf_cmd_byte_ptrQ = WireInit(0.U(3.W)) // [2:0]
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val buf_cmd_nxtbyte_ptr = WireInit(0.U(3.W)) // [2:0]
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val buf_cmd_byte_ptr_en = WireInit(Bool(), init = false.B)
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val found = WireInit(Bool(), init = false.B)
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val slave_valid_pre = WireInit(Bool(), init = false.B)
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val ahb_hready_q = WireInit(Bool(), init = false.B)
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val ahb_hresp_q = WireInit(Bool(), init = false.B)
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val ahb_htrans_q = WireInit(0.U(2.W)) // [1:0]
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val ahb_hwrite_q = WireInit(Bool(), init = false.B)
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val ahb_hrdata_q = WireInit(0.U(64.W)) // [63:0]
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val slvbuf_write = WireInit(Bool(), init = false.B)
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val slvbuf_error = WireInit(Bool(), init = false.B)
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val slvbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val slvbuf_error_in = WireInit(Bool(), init = false.B)
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val slvbuf_wr_en = WireInit(Bool(), init = false.B)
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val bypass_en = WireInit(Bool(), init = false.B)
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val rd_bypass_idle = WireInit(Bool(), init = false.B)
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val last_addr_en = WireInit(Bool(), init = false.B)
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val last_bus_addr = WireInit(0.U(32.W)) // [31:0]
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// Clocks
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val buf_clken = WireInit(Bool(), init = false.B)
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val ahbm_data_clken = WireInit(Bool(), init = false.B)
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val buf_clk = Wire(Clock())
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def get_write_size(byteen: UInt) = {
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val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) |
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("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U(8.W)))))) |
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("b01".U(2.W) & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U(8.W)) | (byteen(7, 0) === "h03".U(8.W))))))
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size
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}
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def get_write_addr(byteen_e: UInt) = {
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val addr = ("h0".U(3.W) & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U(8.W)) | (byteen_e(7, 0) === "h03".U(8.W)))))) |
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("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U(8.W))))) |
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("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U(8.W)))))) |
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("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))
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("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))
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addr
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}
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def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
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val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
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val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
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MuxCase(7.U, temp)
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}
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wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
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master_valid := wr_cmd_vld | io.axi.ar.valid
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master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi.ar.bits.id(TAG - 1, 0))
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master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U)
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master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi.ar.bits.addr(31, 0))
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master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi.ar.bits.size(2, 0))
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master_byteen := wrbuf_byteen(7, 0)
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master_wdata := wrbuf_data(63, 0)
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// AXI response channel signals
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io.axi.b.valid := slave_valid & slave_ready & slave_opc(3)
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io.axi.b.bits.resp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
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io.axi.b.bits.id := slave_tag(TAG - 1, 0)
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io.axi.r.valid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U)
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io.axi.r.bits.resp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
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io.axi.r.bits.id := slave_tag(TAG - 1, 0)
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io.axi.r.bits.data := slave_rdata(63, 0)
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slave_ready := io.axi.b.ready & io.axi.r.ready
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switch(buf_state) {
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is(idle) {
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master_ready := 1.U
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buf_write_in := (master_opc(2, 1) === "b01".U)
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buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
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buf_state_en := master_valid & 1.U
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buf_wr_en := buf_state_en
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buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
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buf_cmd_byte_ptr_en := buf_state_en
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buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B)), master_addr(2, 0))
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bypass_en := buf_state_en
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rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
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io.ahb.out.htrans := (Fill(2, bypass_en)) & "b10".U
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}
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is(cmd_rd) {
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buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
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buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
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cmd_done := buf_state_en & !master_valid
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slvbuf_wr_en := buf_state_en
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master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) === stream_rd) ////////////TBD////////
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buf_wr_en := master_ready
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bypass_en := master_ready & master_valid
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buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
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io.ahb.out.htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
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}
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is(stream_rd) {
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master_ready := (ahb_hready_q & !ahb_hresp_q) & ~(master_valid & master_opc(2, 1) === "b01".U)
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buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
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buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
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buf_state_en := (ahb_hready_q | ahb_hresp_q)
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buf_data_wr_en := buf_state_en
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slvbuf_error_in := ahb_hresp_q
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slvbuf_error_en := buf_state_en
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slave_valid_pre := buf_state_en & !ahb_hresp_q // send a response right away if we are not going through an error response.
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cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans
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bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
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buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
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io.ahb.out.htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
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slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
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}
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is(stream_err_rd) {
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buf_nxtstate := data_rd
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buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
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slave_valid_pre := buf_state_en
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slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer
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buf_cmd_byte_ptr := buf_addr(2, 0)
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io.ahb.out.htrans := "b10".U(2.W) & Fill(2, !buf_state_en)
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}
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is(data_rd) {
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buf_nxtstate := done
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buf_state_en := (ahb_hready_q | ahb_hresp_q)
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buf_data_wr_en := buf_state_en
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slvbuf_error_in := ahb_hresp_q
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slvbuf_error_en := buf_state_en
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slvbuf_wr_en := buf_state_en
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}
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is(cmd_wr) {
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buf_nxtstate := data_wr
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trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
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buf_state_en := trxn_done
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buf_cmd_byte_ptr_en := buf_state_en
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slvbuf_wr_en := buf_state_en
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buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)), buf_cmd_byte_ptrQ)
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cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))
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io.ahb.out.htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U
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}
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is(data_wr) {
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buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
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master_ready := buf_state_en & !ahb_hresp_q & slave_ready
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buf_nxtstate := Mux((ahb_hresp_q | !slave_ready), done, Mux((master_valid & master_valid), Mux((master_opc(2, 1) === 1.U).asBool(), cmd_wr, cmd_rd), idle))
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slvbuf_error_in := ahb_hresp_q
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slvbuf_error_en := buf_state_en
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buf_write_in := master_opc(2, 1) === 1.U
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buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
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buf_data_wr_en := buf_wr_en
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cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= 0.U) &
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((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === 0.U))))
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bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr)
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io.ahb.out.htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U
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slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
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trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= 0.U)
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buf_cmd_byte_ptr_en := trxn_done | bypass_en
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buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
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}
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is(done) {
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buf_nxtstate := idle
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buf_state_en := slave_ready
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slvbuf_error_en := true.B
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slave_valid_pre := true.B
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}
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}
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// buf_rst := 0.U
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cmd_done_rst := slave_valid_pre
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buf_addr_in := Cat(master_addr(31, 3), Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
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buf_tag_in := master_tag(TAG - 1, 0)
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buf_byteen_in := wrbuf_byteen(7, 0)
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buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0))
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buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0))
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buf_aligned_in := (master_opc(2, 0) === 0.U) | // reads are always aligned since they are either DW or sideeffects
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(master_size(1, 0) === 0.U) | (master_size(1, 0) === "b01".U(2.W)) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
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((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) |
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(master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
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// Generate the ahb signals
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io.ahb.out.haddr := Cat(Mux(bypass_en.asBool(), master_addr(31, 3), buf_addr(31, 3)), Fill(3, io.ahb.out.htrans === 2.U) & buf_cmd_byte_ptr)
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io.ahb.out.hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0))))
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io.ahb.out.hburst := "b0".U
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io.ahb.out.hmastlock := "b0".U
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io.ahb.out.hprot := Cat("b001".U, !io.axi.ar.bits.prot(2))
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io.ahb.out.hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write)
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io.ahb.out.hwdata := buf_data(63, 0)
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slave_valid := slave_valid_pre
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slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U)
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slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0)))
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slave_tag := slvbuf_tag(TAG - 1, 0)
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last_addr_en := (io.ahb.out.htrans(1, 0) =/= "b0".U) & io.ahb.in.hready & io.ahb.out.hwrite
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// Write buffer
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wrbuf_en := io.axi.aw.valid & io.axi.aw.ready & master_ready
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wrbuf_data_en := io.axi.w.valid & io.axi.w.ready & master_ready
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wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
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wrbuf_rst := (wrbuf_cmd_sent & !wrbuf_en) | dec_tlu_force_halt_bus
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io.axi.aw.ready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
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io.axi.w.ready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
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io.axi.ar.ready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
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io.axi.r.bits.last := true.B
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wrbuf_vld := rvdffsc_fpga(1.U, wrbuf_en.asBool(), wrbuf_rst, bus_clk, io.bus_clk_en, clock)
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wrbuf_data_vld := rvdffsc_fpga(1.U, wrbuf_data_en.asBool(), wrbuf_rst, bus_clk, io.bus_clk_en, clock)
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wrbuf_tag := rvdffs_fpga(io.axi.aw.bits.id(TAG - 1, 0), wrbuf_en.asBool(), bus_clk, io.bus_clk_en, clock)
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wrbuf_size := rvdffs_fpga(io.axi.aw.bits.size(2, 0), wrbuf_en.asBool(), bus_clk, io.bus_clk_en, clock)
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wrbuf_addr := rvdffe(io.axi.aw.bits.addr, wrbuf_en.asBool & io.bus_clk_en, clock, io.scan_mode)
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wrbuf_data := rvdffe(io.axi.w.bits.data, wrbuf_data_en.asBool & io.bus_clk_en, clock, io.scan_mode)
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wrbuf_byteen := rvdffs_fpga(io.axi.w.bits.strb(7, 0), wrbuf_data_en.asBool(), bus_clk, io.bus_clk_en, clock)
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last_bus_addr := rvdffs_fpga(io.ahb.out.haddr(31, 0), last_addr_en.asBool(), bus_clk, io.bus_clk_en, clock)
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buf_write := rvdffs_fpga(buf_write_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock)
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buf_tag := rvdffs_fpga(buf_tag_in(TAG - 1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
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buf_addr := rvdffe(buf_addr_in(31, 0), (buf_wr_en & io.bus_clk_en).asBool, clock, io.scan_mode)
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buf_size := rvdffs_fpga(buf_size_in(1,0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
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buf_aligned := rvdffs_fpga(buf_aligned_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock)
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buf_byteen := rvdffs_fpga(buf_byteen_in(7, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
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buf_data := rvdffe(buf_data_in(63, 0), (buf_data_wr_en & io.bus_clk_en).asBool(), clock, io.scan_mode)
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slvbuf_write := rvdffs_fpga(buf_write, slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock)
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slvbuf_tag := rvdffs_fpga(buf_tag(TAG - 1, 0), slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock)
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slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), bus_clk, io.bus_clk_en, clock)
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cmd_doneQ := rvdffsc_fpga(1.U, cmd_done.asBool(), cmd_done_rst, bus_clk, io.bus_clk_en, clock)
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buf_cmd_byte_ptrQ := rvdffs_fpga(buf_cmd_byte_ptr(2, 0), buf_cmd_byte_ptr_en.asBool(), bus_clk, io.bus_clk_en, clock)
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ahb_hready_q := rvdff_fpga(io.ahb.in.hready, bus_clk, io.bus_clk_en, clock)
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ahb_htrans_q := rvdff_fpga(io.ahb.out.htrans(1, 0), bus_clk,io.bus_clk_en, clock)
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ahb_hwrite_q := rvdff_fpga(io.ahb.out.hwrite,bus_clk, io.bus_clk_en, clock)
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ahb_hresp_q := rvdff_fpga(io.ahb.in.hresp,bus_clk, io.bus_clk_en, clock)
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ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock)
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buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
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ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
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if (RV_FPGA_OPTIMIZE) {
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bus_clk := 0.B.asClock()
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buf_clk := 0.B.asClock()
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ahbm_data_clk := 0.B.asClock()
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}
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else {
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buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode)
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bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
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ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
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}
|
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}
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|
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object axi4_to_ahb extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(1)))
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} |