colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
quasar/el2_ifu_ifc_ctrl.fir

254 lines
17 KiB
Plaintext
Raw Blame History

;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl :
input clock : Clock
input reset : UInt<1>
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, mb_empty_mod : UInt<1>}
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:30]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:24]
wire fetch_addr_bf : UInt<32>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 66:36]
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 67:34]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 67:34]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 67:24]
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 69:20]
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 69:20]
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 69:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 71:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 71:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 72:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 72:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 72:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 72:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 73:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctrl.scala 73:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 73:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 76:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 77:46]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 78:45]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 79:46]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<32> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctrl.scala 76:24]
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 83:13]
node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:47]
node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:75]
node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctrl.scala 84:30]
node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 85:45]
node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 85:51]
node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctrl.scala 85:51]
node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58]
fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctrl.scala 85:19]
node _T_31 = not(idle) @[el2_ifu_ifc_ctrl.scala 88:30]
io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctrl.scala 88:27]
node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 90:91]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:70]
node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctrl.scala 90:68]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:53]
node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctrl.scala 90:51]
node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:5]
node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctrl.scala 90:114]
node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:18]
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctrl.scala 91:16]
node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:39]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 91:37]
io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctrl.scala 90:23]
node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 93:37]
fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctrl.scala 93:15]
node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:34]
node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctrl.scala 95:32]
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:49]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 95:47]
miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 95:10]
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 97:39]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:63]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 97:61]
node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:76]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 97:74]
node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:86]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 97:84]
mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctrl.scala 97:16]
io.mb_empty_mod <= mb_empty_mod @[el2_ifu_ifc_ctrl.scala 98:19]
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 99:35]
goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 99:13]
node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 101:38]
node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctrl.scala 101:36]
node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctrl.scala 101:67]
leave_idle <= _T_58 @[el2_ifu_ifc_ctrl.scala 101:14]
node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 103:29]
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:23]
node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 103:40]
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 103:33]
node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctrl.scala 103:44]
node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:55]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctrl.scala 103:53]
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 104:11]
node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:17]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctrl.scala 104:15]
node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:33]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctrl.scala 104:31]
node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctrl.scala 103:67]
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:23]
node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctrl.scala 106:34]
node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 106:56]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:62]
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 106:60]
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 106:48]
node _T_76 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 108:19]
_T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 108:19]
state <= _T_77 @[el2_ifu_ifc_ctrl.scala 108:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 110:12]
node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:38]
node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctrl.scala 112:36]
node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:61]
node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctrl.scala 112:81]
node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctrl.scala 112:58]
node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 113:25]
node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctrl.scala 112:92]
fb_right <= _T_84 @[el2_ifu_ifc_ctrl.scala 112:12]
node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 115:39]
node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctrl.scala 115:59]
node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctrl.scala 115:36]
fb_right2 <= _T_87 @[el2_ifu_ifc_ctrl.scala 115:13]
node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 116:56]
node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:35]
node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctrl.scala 116:33]
node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:80]
node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctrl.scala 116:78]
fb_left <= _T_92 @[el2_ifu_ifc_ctrl.scala 116:11]
node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 118:37]
node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 119:6]
node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctrl.scala 119:16]
node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctrl.scala 119:28]
node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 119:62]
node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 120:6]
node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctrl.scala 120:16]
node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctrl.scala 120:29]
node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 120:63]
node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 121:6]
node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctrl.scala 121:16]
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctrl.scala 121:27]
node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 121:51]
node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:6]
node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:18]
node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctrl.scala 122:16]
node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:30]
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctrl.scala 122:28]
node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:43]
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 122:41]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctrl.scala 122:53]
node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 122:73]
node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
wire _T_127 : UInt<4> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
fb_write_ns <= _T_127 @[el2_ifu_ifc_ctrl.scala 118:15]
node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 125:38]
reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:26]
_T_129 <= _T_128 @[el2_ifu_ifc_ctrl.scala 125:26]
fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctrl.scala 125:16]
node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 127:17]
idle <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:8]
node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 128:16]
wfm <= _T_131 @[el2_ifu_ifc_ctrl.scala 128:7]
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 130:30]
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctrl.scala 130:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 131:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 131:26]
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 132:24]
_T_133 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 132:24]
fb_write_f <= _T_133 @[el2_ifu_ifc_ctrl.scala 132:14]
node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 135:40]
node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 135:61]
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 135:19]
node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctrl.scala 135:17]
node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctrl.scala 135:84]
node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctrl.scala 134:60]
node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctrl.scala 134:33]
io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctrl.scala 134:26]
node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 214:25]
node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 214:47]
node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 217:14]
node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 141:25]
node _T_144 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 142:78]
node _T_145 = cat(_T_144, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_146 = dshr(io.dec_tlu_mrac_ff, _T_145) @[el2_ifu_ifc_ctrl.scala 142:53]
node _T_147 = bits(_T_146, 0, 0) @[el2_ifu_ifc_ctrl.scala 142:53]
node _T_148 = not(_T_147) @[el2_ifu_ifc_ctrl.scala 142:34]
io.ifc_fetch_uncacheable_bf <= _T_148 @[el2_ifu_ifc_ctrl.scala 142:31]
reg _T_149 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 144:32]
_T_149 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 144:32]
io.ifc_fetch_req_f <= _T_149 @[el2_ifu_ifc_ctrl.scala 144:22]
node _T_150 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 146:88]
reg _T_151 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_150 : @[Reg.scala 28:19]
_T_151 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_151 @[el2_ifu_ifc_ctrl.scala 146:23]
Reference in New Issue View Git Blame Copy Permalink