174 lines
5.8 KiB
Systemverilog
174 lines
5.8 KiB
Systemverilog
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module mem #(
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parameter ICACHE_BEAT_BITS,
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parameter ICCM_BITS,
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parameter ICACHE_NUM_WAYS,
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parameter DCCM_BYTE_WIDTH,
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parameter ICCM_BANK_INDEX_LO,
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parameter ICACHE_BANK_BITS,
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parameter DCCM_BITS,
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parameter ICACHE_BEAT_ADDR_HI,
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parameter ICCM_INDEX_BITS,
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parameter ICCM_BANK_HI,
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parameter ICACHE_BANKS_WAY,
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parameter ICACHE_INDEX_HI,
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parameter DCCM_NUM_BANKS,
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parameter ICACHE_BANK_HI,
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parameter ICACHE_BANK_LO,
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parameter DCCM_ENABLE= 'b1,
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parameter ICACHE_TAG_LO,
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parameter ICACHE_DATA_INDEX_LO,
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parameter ICCM_NUM_BANKS,
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parameter ICACHE_ECC,
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parameter ICACHE_ENABLE= 'b1,
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parameter DCCM_BANK_BITS,
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parameter ICCM_ENABLE= 'b1,
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parameter ICCM_BANK_BITS,
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parameter ICACHE_TAG_DEPTH,
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parameter ICACHE_WAYPACK,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH,
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parameter ICACHE_TAG_INDEX_LO,
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parameter ICACHE_DATA_DEPTH)
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(
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input logic clk,
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input logic rst_l,
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input logic dccm_clk_override,
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input logic icm_clk_override,
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input logic dec_tlu_core_ecc_disable,
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//DCCM ports
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input logic dccm_wren,
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input logic dccm_rden,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
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//`ifdef DCCM_ENABLE
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//`endif
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//ICCM ports
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input logic [ICCM_BITS-1:1] iccm_rw_addr,
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input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
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input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [63:0] iccm_rd_data,
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output logic [77:0] iccm_rd_data_ecc,
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// Icache and Itag Ports
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input logic [31:1] ic_rw_addr,
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input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
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input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
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input logic ic_rd_en,
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input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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input logic ic_sel_premux_data, // Premux data sel
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input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
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input logic [70:0] ic_wr_data_1,
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input logic [70:0] ic_debug_wr_data, // Debug wr cache.
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output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
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input logic ic_debug_rd_en, // Icache debug rd
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input logic ic_debug_wr_en, // Icache debug wr
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input logic ic_debug_tag_array, // Debug tag array
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input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
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output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
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output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
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output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
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output logic ic_tag_perr, // Icache Tag parity error
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input logic scan_mode
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);
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logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
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assign ic_wr_data [0] = ic_wr_data_0;
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assign ic_wr_data [1] = ic_wr_data_1;
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// DCCM Instantiation
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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lsu_dccm_mem #(
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.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
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.DCCM_BITS(DCCM_BITS),
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.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
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.DCCM_BANK_BITS(DCCM_BANK_BITS),
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.DCCM_SIZE(DCCM_SIZE),
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.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
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.clk_override(dccm_clk_override),
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.*
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);
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end else begin: Gen_dccm_disable
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assign dccm_rd_data_lo = '0;
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assign dccm_rd_data_hi = '0;
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end
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if ( ICACHE_ENABLE ) begin: icache
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ifu_ic_mem #(
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.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
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.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
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.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
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.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
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.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
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.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
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.ICACHE_BANK_HI(ICACHE_BANK_HI),
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.ICACHE_BANK_LO(ICACHE_BANK_LO),
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.ICACHE_TAG_LO(ICACHE_TAG_LO),
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.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
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.ICACHE_ECC(ICACHE_ECC),
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.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
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.ICACHE_WAYPACK(ICACHE_WAYPACK),
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.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
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.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
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.clk_override(icm_clk_override),
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.*
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);
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end
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else begin
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assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
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assign ic_tag_perr = '0 ;
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assign ic_rd_data = '0 ;
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assign ic_tag_debug_rd_data = '0 ;
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end // else: !if( ICACHE_ENABLE )
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if (ICCM_ENABLE) begin : iccm
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ifu_iccm_mem #(
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.ICCM_BITS(ICCM_BITS),
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.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
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.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
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.ICCM_BANK_HI(ICCM_BANK_HI),
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.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
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.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
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.clk_override(icm_clk_override),
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.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
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.iccm_rd_data(iccm_rd_data[63:0])
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);
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end
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else begin
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assign iccm_rd_data = '0 ;
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assign iccm_rd_data_ecc = '0 ;
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end
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endmodule
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