702 lines
26 KiB
Plaintext
702 lines
26 KiB
Plaintext
hsDirType 1
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fHsimDesignHasDebugNodes 13
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fNSParam 1024
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fLargeSizeSdfTest 0
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fHsimDelayGateMbme 0
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fNoMergeDelays 0
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fHsimAllMtmPat 0
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fHsimCertRaptMode 0
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fSharedMasterElab 0
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hsimLevelizeDone 1
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fHsimCompressDiag 1
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fHsimPowerOpt 0
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fLoopReportElab 0
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fHsimRtl 0
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fHsimCbkOptVec 1
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fHsimDynamicCcnHeur 1
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fHsimPvcs 0
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fHsimPvcsCcn 0
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fHsimOldLdr 0
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fHsimSingleDB 1
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uVfsGcLimit 50
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fHsimCompatSched 0
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fHsimCompatOrder 0
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fHsimTransUsingdoMpd32 0
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fHsimDynamicElabForGates 1
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fHsimDynamicElabForVectors 0
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fHsimDynamicElabForVectorsAlways 0
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fHsimDynamicElabForVectorsMinputs 0
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fHsimCompressMdbForDynamicElab 0
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fHsimCompressMdbDiag 0
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fHsimDeferForceSelTillReElab 0
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fHsimModByModElab 1
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fSvNettRealResType 0
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fHsimExprID 1
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fHsimSequdpon 0
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fHsimDatapinOpt 0
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fHsimExprPrune 0
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fHsimMimoGate 0
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fHsimNewChangeCheckFrankch 1
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fHsimNoSched0Front 0
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fHsimNoSched0FrontForMd 1
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fHsimScalReg 0
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fHsimNtbVl 0
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fHsimICTimeStamp 0
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fHsimICDiag 0
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fHsimNewCSDF 1
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vcselabIncrMode 2
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fHsimMPPackDelay 0
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fHsimMultDriver 0
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fHsimPart 0
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fHsimPrlComp 0
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fHsimPartTest 0
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fHsimTestChangeCheck 0
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fHsimTestFlatNodeOrder 0
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fHsimTestNState 0
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fHsimPartDebug 0
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fHsimPartFlags 0
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fHsimOdeSched0 0
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fHsimNewRootSig 1
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fHsimDisableRootSigModeOpt 0
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fHsimTestRootSigModeOpt 0
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fHsimIncrWriteOnce 0
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fHsimUnifInterfaceFlow 1
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fHsimUnifInterfaceFlowDiag 0
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fHsimUnifInterfaceFlowXmrDiag 0
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fHsimUnifInterfaceMultiDrvChk 1
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fHsimXVirForGenerateScope 0
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fHsimCongruencyIntTestI 0
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fHsimCongruencySVA 0
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fHsimCongruencySVADbg 0
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fHsimCongruencyLatchEdgeFix 0
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fHsimCongruencyFlopEdgeFix 0
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fHsimCongruencyXprop 0
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fHsimCongruencyXpropFix 0
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fHsimCongruencyXpropDbsEdge 0
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fHsimCongruencyResetRecoveryDbs 0
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fHsimCongruencyClockControlDiag 0
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fHsimCongruencySampleUpdate 0
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fHsimCongruencyFFDbsFix 0
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fHsimCongruency 0
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fHsimCongruencySlave 0
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fHsimCongruencyCombinedLoads 0
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fHsimCongruencyFGP 0
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fHsimDeraceClockDataUdp 0
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fHsimDeraceClockDataLERUpdate 0
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fHsimCongruencyPC 0
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fHsimCongruencyPCInl 0
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fHsimCongruencyPCDbg 0
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fHsimCongruencyPCNoReuse 0
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fHsimCongruencyDumpHier 0
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fHsimCongruencyResolution 0
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fHsimCongruencyEveBus 0
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fHsimHcExpr 0
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fHsCgOptModOpt 0
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fHsCgOptSlowProp 0
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fHsimCcnOpt 1
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fHsimCcnOpt2 1
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fHsimCcnOpt3 0
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fHsimSmdMap 0
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fHsimSmdDiag 0
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fHsimSmdSimProf 0
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fHsimSgdDiag 0
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fHsimRtDiagLite 0
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fHsimRtDiagLiteCevent 100
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fHsimRtDiag 0
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fHsimSkRtDiag 0
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fHsimDDBSRtdiag 0
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fHsimDbg 0
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fHsimCompWithGates 0
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fHsimMdbDebugOpt 0
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fHsimMdbDebugOptP1 0
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fHsimMdbDebugOptP2 0
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fHsimMdbPruneOpt 1
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fHsimMdbMemOpt 0
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hsimRandValue 0
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fHsimSimMemProfile 0
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fHsimSimTimeProfile 0
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fHsimElabMemProfile 0
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fHsimElabTimeProfile 0
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fHsimElabMemNodesProfile 0
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fHsimElabMemAllNodesProfile 0
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fHsimDisableVpdGatesProfile 0
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fHsimFileProfile 0
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fHsimCountProfile 0
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fHsimXmrDefault 1
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fHsimFuseWireAndReg 0
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fHsimFuseSelfDrvLogic 0
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fHsimFuseProcess 0
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fHsimNoStitchDump 0
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fHsimAllExtXmrs 0
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fHsimAllExtXmrsDiag 0
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fHsimAllExtXmrsAllowClkFusing 0
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fHsimAllXmrs 1
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fHsimMvsimDb 0
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fHsimTaskFuncXmrs 0
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fHsimTaskFuncXmrsDbg 0
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fHsimAllTaskFuncXmrs 0
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fHsimPageArray 16383
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fHsimPageControls 16383
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hsDfsNodePageElems 0
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hsNodePageElems 0
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hsFlatNodePageElems 0
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hsGateMapPageElems 0
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hsGateOffsetPageElems 0
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hsGateInputOffsetPageElems 0
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hsDbsOffsetPageElems 0
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hsMinPulseWidthPageElems 0
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hsNodeUpPatternPageElems 0
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hsNodeDownPatternPageElems 0
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hsNodeUpOffsetPageElems 0
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hsNodeEblkOffsetPageElems 0
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hsNodeDownOffsetPageElems 0
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hsNodeUpdateOffsetPageElems 0
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hsSdfOffsetPageElems 0
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fHsimPageAllLevelData 0
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fHsimAggrCg 0
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fHsimViWire 1
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fHsimPcCbOpt 1
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fHsimAmsTunneling 0
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fHsimAmsTunnelingDiag 0
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fHsimScUpwardXmrNoSplit 1
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fHsimOrigNdbViewOnly 0
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fHsimVcsInterface 1
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fHsimVcsInterfaceAlias 1
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fHsimSVTypesIntf 1
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fUnifiedAssertCtrlDiag 0
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fHsimEnable2StateScal 0
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fHsimDisable2StateScalIbn 0
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fHsimVcsInterfaceAliasDbg 0
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fHsimVcsInterfaceDbg 0
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fHsimVcsVirtIntfDbg 0
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fHsimVcsAllIntfVarMem 0
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fHsimCheckVIDynLoadOffsets 0
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fHsimModInline 1
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fHsimModInlineDbg 0
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fHsimPCDrvLoadDbg 0
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fHsimDrvChk 1
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fHsimRtlProcessingNeeded 1
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fHsimGrpByGrpElab 0
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fHsimGrpByGrpElabMaster 0
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fHsimNoParentSplitPC 0
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fHsimNusymMode 0
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fHsimOneIntfPart 0
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fHsimCompressInSingleDb 2
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fHsimCompressFlatDb 0
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fHsimNoTime0Sched 1
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fHsimMdbVectorizeInstances 0
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fHsimMdbSplitGates 0
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fHsimDeleteInstances 0
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fHsimUserDeleteInstances 0
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fHsimDeleteGdb 0
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fHsimDeleteInstancesMdb 0
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fHsimShortInstMap 0
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fHsimMdbVectorizationDump 0
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fHsimScanVectorize 0
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fHsimParallelScanVectorize 0
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noInstsInVectorization 0
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cHsimNonReplicatedInstances 0
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fHsimScanRaptor 0
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fHsimConfigFileCount 0
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fHsimVectorConstProp 0
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fHsimPromoteParam 0
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fHsimNoVecInRaptor 0
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fRaptorDumpVal 0
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fRaptorVecNodes 0
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fRaptorVecNodes2 0
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fRaptorNonVecNodes 0
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fRaptorBdrNodes 0
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fRaptorVecGates 0
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fRaptorNonVecGates 0
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fRaptorTotalNodesBeforeVect 0
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fRaptorTotalGatesBeforeVect 0
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fHsimCountRaptorBits 0
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fHsimNewEvcd 1
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fHsimNewEvcdMX 0
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fHsimNewEvcdVecRoot 1
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fHsimNewEvcdForce 1
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fHsimNewEvcdTest 0
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fHsimNewEvcdObnDrv 1
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fHsimNewEvcdW 1
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fHsimNewEvcdWTest 0
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fHsimEvcdDbgFlags 0
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fHsimNewEvcdMultiDrvFmt 1
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fHsimDumpOffsetData 1
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fFlopGlitchDetect 0
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fHsimClkGlitch 0
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fHsimGlitchDumpOnce 0
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fHsimDynamicElab 1
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fHsimCgVectors2Debug 0
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fHsimOdeDynElab 0
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fHsimOdeDynElabDiag 0
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fHsimOdeSeqUdp 0
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fHsimOdeSeqUdpXEdge 0
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fHsimOdeSeqUdpDbg 0
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fHsimOdeRmvSched0 0
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fHsimAllLevelSame 0
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fHsimRtlDbsList 0
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fHsimPePort 0
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fHsimPeXmr 0
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fHsimPePortDiag 0
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fHsimUdpDbs 0
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fHsimRemoveDbgCaps 0
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fFsdbGateOnepassTraverse 0
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fHsimAllowVecGateInVpd 1
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fHsimAllowAllVecGateInVpd 0
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fHsimAllowUdpInVpd 1
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fHsimAllowAlwaysCombInVpd 1
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fHsimAllowAlwaysCombCmpDvcSimv 0
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fHsimAllowAlwaysCombDbg 0
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fHsimMakeAllP2SPrimary 0
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fHsimMakeAllSeqPrimary 0
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fHsimNoCcnDump 0
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fHsimFsdbProfDiag 0
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fVpdSeqGate 0
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fVpdUseMaxBCode 0
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fVpdHsIntVecGate 0
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fVpdHsCmplxVecGate 0
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fVpdHsVecGateDiags 0
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fSeqGateCodePatch 0
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fVpdLongFaninOpt 0
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fVpdSeqLongFaninOpt 0
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fVpdNoLoopDetect 0
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fVpdNoSeqLoopDetect 0
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fVpdOptAllowConstDriver 0
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fVpdAllowCellReconstruction 0
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fVpdRtlForSharedLib 0
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fHsimVpdOptGate 1
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fHsimVpdOptDelay 0
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fHsimVpdOptMPDelay 0
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fHsimCbkOptDiag 0
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fHsimSK 0
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fHsimSharedKernel 1
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fHsimOnepass 0
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fHsimStitchNew 0
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fHsimParallelLevelize 0
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fHsimParallelLevelizeDbg 0
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fHsimSeqUdpDbsByteArray 0
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fHsimCoLocate 0
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fHsimSeqUdpEblkOpt 0
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fHsimSeqUdpEblkOptDiag 0
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fHsimGateInputAndDbsOffsetsOpt 1
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fHsimGDBLargeModule 1
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fHsimUdpDynElab 0
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fHsimCompressData 4
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fHsimIgnoreZForDfuse 1
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fHsimIgnoreDifferentCaps 0
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fHandleGlitchQC 1
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fGlitchDetectForAllRtlLoads 0
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fHsimFuseConstDriversOpt 1
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fHsimMdSchedTr 0
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fHsimIgnoreReElab 0
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fHsimFuseMultiDrivers 0
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fHsimNoSched0Reg 0
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fHsimAmsFusionEnabled 0
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fHsimRtlDbs 1
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fHsimWakeupId 0
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fHsimPassiveIbn 0
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fHsimBcOpt 1
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fHsimCertitude 0
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fHsimCertRapAutoTest 0
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fHsimRaceDetect 0
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fCheckTcCond 0
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fHsimScanOptRelaxDbg 0
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fHsimScanOptRelaxDbgDynamic 0
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fHsimScanOptRelaxDbgDynamicPli 0
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fHsimScanOptRelaxDbgDiag 0
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fHsimScanOptRelaxDbgDiagHi 0
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fHsimScanOptNoErrorOnPliAccess 0
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fHsimScanOptTiming 0
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fRelaxIbnSchedCheck 0
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fHsimScanOptNoDumpCombo 0
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fHsimScanOptPrintSwitchState 0
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fHsimScanOptSelectiveSwitchOn 0
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fHsimScanOptSingleSEPliOpt 1
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fHsimScanOptDesignHasDebugAccessOnly 0
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fHsimScanOptPrintPcode 0
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fHsimScanDbgPerf 0
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fHsimNoStitchMap 0
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fHsimUnifiedModName 0
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fHsimCbkMemOptDebug 0
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fHsimMasterModuleOnly 0
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fHsimUpHierIC 0
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fHsimMdbOptimizeSelects 0
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fHsimMdbScalarizePorts 0
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fHsimMdbOptimizeSelectsHeuristic 1
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fHsimMdb1006Partition 0
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fHsimVectorPgate 0
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fHsimNoHs 0
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fHsimXmrPartition 0
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fHsimNewPartition 0
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fHsimElabPart 0
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fHsimElabPartThreshHoldDesign 1
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fHsimPMdb 0
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fHsimParitionCellInstNum 1000
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fHsimParitionCellNodeNum 1000
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fHsimParitionCellXMRNum 1000
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fHsimNewPartCutSingleInstLimit 268435455
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fHsimElabModDistNum 0
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fHsimElabPartThreshHoldModule 3000000
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fHsimPCPortPartition 0
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fHsimPortPartition 0
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fHsimDumpMdb 0
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fHsimElabDiag 0
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fHsimSimpCollect 0
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fHsimPcodeDiag 0
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fHsimFastelab 0
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fHsimMacroOpt 0
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fHsimSkipOpt 0
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fHsimSkipOptFanoutlimit 0
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fHsimSkipOptRootlimit 0
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fHsimFuseDelayChains 0
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fFusempchainsFanoutlimit 0
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fFusempchainsDiagCount 0
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fHsimCgVectorGates 0
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fHsimCgVectorGates1 0
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fHsimCgVectorGates2 0
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fHsimCgVectorGatesNoReElab 0
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fHsimCgScalarGates 0
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fHsimCgScalarGatesExpr 0
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fHsimCgScalarGatesLut 0
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fHsimCgRtl 100000
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fHsimCgRtlFilter 0
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fHsimCgRtlDebug 0
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fHsimCgRtlSize 15
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fHsimNewCgRt 0
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fHsimNewCgMPRt 0
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fHsimNewCgMPRetain 0
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fHsimCgRtlInfra 1
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fHsimGlueOpt 0
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fHsimPGatePatchOpt 0
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fHsimCgNoPic 0
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fHsimElabModCg 0
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fPossibleNullChecks 0
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fHsimProcessNoSplit 1
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fHsimMdbOptInSchedDelta 0
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fScaleTimeValue 0
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fDebugTimeScale 0
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fPartCompSDF 0
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fHsimNbaGate 1
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fDumpDtviInfoInSC 0
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fDumpSDFBasedMod 1
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fHsimSdfIC 0
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fOptimisticNtcSolver 0
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fHsimAllMtm 0
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fHsimAllMtmPat 0
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fHsimSdgOptEnable 0
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fHsimSVTypesRefPorts 0
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fHsimGrpByGrpElabIncr 0
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fHsimMarkRefereeInVcsElab 0
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fHsimStreamOpFix 1
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fHsimInterface 0
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fHsimMxWrapOpt 0
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fHsimMxTopBdryOpt 0
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fHsimClasses 0
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fHsimAggressiveDce 0
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fHsimDceDebug 1
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fHsimDceDebugUseHeuristics 1
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fHsimMdbNewDebugOpt 0
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fHsimMdbNewDebugOptExitOnError 1
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fHsimNewDebugOptMemDiag 0
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hsGlobalVerboseLevel 0
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fHsimMdbVectorConstProp 1
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fHsimEnableSeqUdpWrite 0
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fHsimDumpMDBOnlyForSeqUdp 0
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fHsimInitRegRandom 0
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fHsimInitRegRandomVcs 1
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fEnableNewFinalStrHash 0
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fEnableNewAssert 1
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fRunDbgDmma 0
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fAssrtCtrlSigChk 1
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fCheckSigValidity 0
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fUniqPriToAstRewrite 0
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fUniqPriToAstCtrl 0
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fAssertcontrolUniqPriNewImpl 0
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fRTLoopDectEna 0
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fCmplLoopDectEna 0
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fHsimMopFlow 1
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fUCaseLabelCtrl 0
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fUniSolRtSvaEna 1
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fUniSolSvaEna 1
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fXpropRtCtrlCallerOnly 0
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fHsimRaptorPart 0
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fHsimEnableDbsMemOpt 1
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fHsimDebugDbsMemOpt 0
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fHsimRenPart 0
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fHsimShortElabInsts 0
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fHsimXmrAllWires 0
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fHsimXmrDiag 0
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fHsimXmrPort 0
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fHsimFalcon 1
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fHsimGenForProfile 0
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fCompressSDF 0
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fDlpSvtbExclElab 0
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fHsimGates1209 0
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fHsimCgRtlNoShareSmd 0
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fHsimGenForErSum 0
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fVpdOpt 1
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fHsimMdbCell 0
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fHsimCellDebug 0
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fHsimNoPeekInMdbCell 0
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igetOpcodeSmdPtrLayoutId -1
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igetFieldSmdPtr -1
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fDebugDump 1
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fHsimOrigNodeNames 0
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fHsimCgVectors2VOnly 0
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fHsimMdbDeltaGate 0
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fHsimMdbDeltaGateAggr 0
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fHsimMdbVecDeltaGate 1
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fHsimVpdOptVfsDB 1
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fHsimMdbPruneVpdGates 1
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fHsimPcPe 0
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fHsimVpdGateOnlyFlag 1
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fHsimMxConnFrc 0
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fHsimNewForceCbkVec 0
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fHsimNewForceCbkVecDiag 0
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fHsimMdbReplaceVpdHighConn 1
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fHsimVpdOptSVTypes 1
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fHsHasPeUpXmr 0
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fHsimCompactVpdFn 1
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fHsimPIP 0
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fHsimRTLoopDectOrgName 0
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fHsimVpdOptPC 0
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fHsimFusePeXmrFo 0
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fHsimXmrSched 0
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fHsimNoMdg 0
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fHsimVectorGates 0
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fHsimRtlLite 0
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fHsimMdbcgLut 0
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fHsimMdbcgSelective 0
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fHsimVcselabGates 0
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fHsimMdbcgLevelize 0
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fHsimParGateEvalMode 0
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fHsimDFuseVectors 0
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fHsimDFuseZero 0
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fHsimDFuseOpt 1
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fHsimPruneOpt 0
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fHsimSeqUdpPruneWithConstInputs 0
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fHsimSafeDFuse 0
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fHsimVpdOptExpVec 0
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fHsimVpdOptSelGate 1
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fHsimVpdOptSkipFuncPorts 0
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fHsimVpdOptAlways 1
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fHsimVpdOptMdbCell 0
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fHsimVpdOptPartialMdb 1
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fHsimVpdOptPartitionGate 1
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fHsimVpdOptXmr 1
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fHsimVpdOptMoreLevels 1
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fHsimVpdHilRtl 0
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fHsimSWave 0
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fHsimNoSched0InCell 1
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fHsimPartialMdb 0
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hsimPdbLargeOffsetThreshold 1048576
|
|
fHsimFlatCell 0
|
|
fHsimFlatCellLimit 0
|
|
fHsimRegBank 0
|
|
fHsimHmetisMaxPartSize 0
|
|
fHsimHmetisGateWt 0
|
|
fHsimHmetisUbFactor 0
|
|
fHsimHmetis 0
|
|
fHsimHmetisDiag 0
|
|
fHsimRenumGatesForMdbCell 0
|
|
fHsimHmetisMinPart 0
|
|
fHsim2stCell 0
|
|
fHsim2stCellMinSize 0
|
|
fHsimMdbcgDebug 0
|
|
fHsimMdbcgDebugLite 0
|
|
fHsimMdbcgDistrib 0
|
|
fHsimMdbcgSepmem 1
|
|
fHsimMdbcgObjDiag 0
|
|
fHsimMdbcg2stDiag 0
|
|
fHsimMdbcgRttrace 0
|
|
fHsimMdbVectorGateGroup 1
|
|
fHsimMdbProcDfuse 1
|
|
fHsimMdbHilPrune 0
|
|
fHsCgOpt 1
|
|
fHsCgOptUdp 1
|
|
fHsCgOptRtl 1
|
|
fHsCgOptDiag 0
|
|
fHsCgOptAggr 0
|
|
fHsCgOptNoZCheck 0
|
|
fHsCgOptEnableZSupport 0
|
|
fHsCgOpt4StateInfra 0
|
|
fHsCgOptDce 0
|
|
fHsCgOptUdpChkDataForWakeup 1
|
|
fHsCgOptXprop 0
|
|
fHsimMdbcgDiag 0
|
|
fHsCgMaxInputs 6
|
|
fHsCgOptFwdPass 1
|
|
fHsimHpnodes 0
|
|
fLightDump 0
|
|
fHDLCosim 0
|
|
fHDLCosimDebug 0
|
|
fHDLCosimTimeCoupled 0
|
|
fHDLCosimTimeCoupledPorts 0
|
|
HDLCosimMaxDataPerDpi 1
|
|
HDLCosimMaxCallsPerDpi 2147483647
|
|
fHDLCosimCompileDUT 0
|
|
fHDLCosimCustomCompile 0
|
|
fHDLCosimBoundaryAnalysis 0
|
|
fVpdBeforeScan 1
|
|
fHsCgOptMiSched0 0
|
|
fgcAddSched0 0
|
|
fParamClassOptRtDiag 0
|
|
fHsRegress 0
|
|
fHsBenchmark 0
|
|
fHsimCgScalarVerilogForce 1
|
|
fVcsElabToRoot 1
|
|
fHilIbnObnCallByName 0
|
|
fHsimMdbcgCellPartition 0
|
|
fHsimCompressVpdSig 0
|
|
fHsimLowPowerOpt 0
|
|
fHsimUdpOpt 1
|
|
fHsVecOneld 0
|
|
fNativeVpdDebug 0
|
|
fNewDtviFuse 0
|
|
fHsimVcsGenTLS 1
|
|
fAssertSuccDebugLevelDump 0
|
|
fHsimMinputsChangeCheck 0
|
|
fHsimClkLayout 0
|
|
fHsimSortLayout 0
|
|
fHsimIslandLayout 0
|
|
fHsimConfigSched0 0
|
|
fHsimSelectFuseAfterDfuse 0
|
|
fHsimFoldedCell 0
|
|
fHsimSWaveEmul 0
|
|
fHsimSWaveDumpMDB 0
|
|
fHsimSWaveDumpFlatData 0
|
|
fHsimRenumberAlias 0
|
|
fHsimAliasRenumbered 0
|
|
fHilCgMode 115
|
|
fHsimUnionOpt 0
|
|
fHsimFuseSGDBoundaryNodes 0
|
|
fHsimRemoveCapsVec 0
|
|
fHsimCertRaptScal 0
|
|
fHsimCertRaptMdbClock 0
|
|
fHsCgOptMux 0
|
|
fHsCgOptFrc 0
|
|
fHsCgOpt30 0
|
|
fHsLpNoCapsOpt 0
|
|
fHsCgOpt4State 1
|
|
fSkipStrChangeOnDelay 1
|
|
fHsimTcheckOpt 0
|
|
fHsCgOptMuxMClk 0
|
|
fHsCgOptMuxFrc 0
|
|
fHsCgOptNoPcb 0
|
|
fHsCgOptMin1 0
|
|
fHsCgOptUdpChk 0
|
|
fHsChkXForSlowSigProp 1
|
|
fHsimVcsParallelDbg 0
|
|
fHsimVcsParallelStrategy 0
|
|
fHsimVcsParallelOpt 0
|
|
fHsimVcsParallelSubLevel 4
|
|
fHsimParallelEblk 0
|
|
fHsimByteCodeParts 1
|
|
fFgpNovlInComp 0
|
|
fFutEventPRL 0
|
|
fFgpNbaDelay 0
|
|
fHsimDbsFlagsByteArray 0
|
|
fHsimDbsFlagsByteArrayTC 0
|
|
fHsimDbsFlagsThreadArray 0
|
|
fHsimGateEdgeEventSched 0
|
|
fHsimEgschedDynelab 0
|
|
fHsimUdpClkDynelab 0
|
|
fUdpLayoutOnClk 0
|
|
fHsimDiagClk 1
|
|
fDbsPreCheck 0
|
|
fHsimSched0Analysis 0
|
|
fHsimMultiDriverSched0 0
|
|
fHsimLargeIbnSched 0
|
|
fFgpHierarchical 0
|
|
fFgpHierAllElabModAsRoot 0
|
|
fFgpHierPCElabModAsRoot 0
|
|
fFgpAdjustDataLevelOfLatch 1
|
|
fHsimUdpXedgeEval 0
|
|
fFgpRaceCheck 0
|
|
fFgpUnifyClk 0
|
|
fFgpSmallClkTree 0
|
|
fFgpSmallRtlClkTree 4
|
|
fFgpNoRtlUnlink 0
|
|
fFgpNoRtlAuxLevel 0
|
|
fFgpNumPartitions 8
|
|
fFgpMultiSocketCompile 0
|
|
fFgpDataDepOn 0
|
|
fFgpDDIgnore 0
|
|
fFgpTbCbOn 0
|
|
fFgpTbEvOn 1
|
|
fFgpTbNoVSA 0
|
|
fFgpTbEvXmr 0
|
|
fFgpTbEvCgCall 1
|
|
fFgpDisabledLevel 512
|
|
fFgpSched0User 0
|
|
fFgpNoSdDelayedNbas 1
|
|
fFgpNoEvNbas 1
|
|
fFgpTimingFlags 0
|
|
fFgpSched0Level 0
|
|
fHsimFgpMultiClock 0
|
|
fFgpScanOptFix 0
|
|
fFgpSched0UdpData 0
|
|
fFgpLoadBalance0CompileTime 1
|
|
fFgpDepositDiag 0
|
|
fFgpEvtDiag.diagOn 0
|
|
fFgpEvtDiag.printAllNodes 0
|
|
fFgpMangleDiagLog 0
|
|
fFgpMultiExclDiag 0
|
|
fFgpSingleExclReason 0
|
|
fHsDoFaninFanoutSanity 0
|
|
fHsFgpNonDbsOva 1
|
|
fFgpParallelTask 1
|
|
fFgpIbnSched 0
|
|
fFgpIbnSchedOpt 0
|
|
fFgpIbnSchedThreshold 0
|
|
fFgpIbnSchedDyn 0
|
|
fFgpMpStateByte 0
|
|
fFgpTcStateByte 0
|
|
fHsimVirtIntfDynLoadSched 0
|
|
fFgpNoRtimeFgp 0
|
|
fHsFgpGlSched0 0
|
|
fFgpExclReason 0
|
|
fHsimIslandByIslandElab 0
|
|
fHsimIslandByIslandFlat 151652416
|
|
fHsimIslandByIslandFlat1 4
|
|
fHsimVpdIBIF 0
|
|
fHsimXmrIBIF 0
|
|
fHsimReportTime 0
|
|
fHsimElabJ 0
|
|
hf_fHsimElabJ 0
|
|
fHsimElabJOpt 0
|
|
fHsimSchedMinput 0
|
|
fHsimSchedSeqPrim 0
|
|
fHsimSchedSelectFanout 0
|
|
fHsimSchedSelectFanoutDebug 0
|
|
fSpecifyInDesign 0
|
|
fFgpDynamicReadOn 0
|
|
fHsCgOptAllUc 0
|
|
fHsimXmrRepl 0
|
|
fZoix 0
|
|
fHsimDfuseNewOpt 0
|
|
fHsimBfuseNewOpt 0
|
|
fFgpXmrSched 0
|
|
fHsimClearClkCaps 0
|
|
fHsimDiagClkConfig 0
|
|
fHsimDiagClkConfigDebug 0
|
|
fHsimDiagClkConfigDumpAll 0
|
|
fHsDiagClkConfigPara 0
|
|
fHsimDiagClkConfigAn 0
|
|
fHsimCanDumpClkConfig 0
|
|
fFgpInitRout 0
|
|
fFgpIgnoreExclSD 0
|
|
fHsCgOptNoClockFusing 0
|
|
fHsClkWheelLimit 50000
|
|
fHsimPCSharedLibSpecified 0
|
|
fHsFgpSchedCgUcLoads 1
|
|
fHsCgOptNewSelCheck 1
|
|
fFgpReportUnsafeFuncs 0
|
|
fHsCgOptUncPrlThreshold 4
|
|
fHsSVNettypePerfOpt 0
|
|
fHsimLowPowerRetAnalysisInChild 0
|
|
fRetainWithDelayedSig 0
|
|
fHsimChargeDecay 0
|
|
fFgpUseAltEgLayout 0
|
|
fFgpTbReactiveLite 0
|