quasar/verif/sim/simv.daidir/vcselab_master_hsim_elabout.db

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26 KiB
Plaintext

hsDirType 1
fHsimDesignHasDebugNodes 13
fNSParam 1024
fLargeSizeSdfTest 0
fHsimDelayGateMbme 0
fNoMergeDelays 0
fHsimAllMtmPat 0
fHsimCertRaptMode 0
fSharedMasterElab 0
hsimLevelizeDone 1
fHsimCompressDiag 1
fHsimPowerOpt 0
fLoopReportElab 0
fHsimRtl 0
fHsimCbkOptVec 1
fHsimDynamicCcnHeur 1
fHsimPvcs 0
fHsimPvcsCcn 0
fHsimOldLdr 0
fHsimSingleDB 1
uVfsGcLimit 50
fHsimCompatSched 0
fHsimCompatOrder 0
fHsimTransUsingdoMpd32 0
fHsimDynamicElabForGates 1
fHsimDynamicElabForVectors 0
fHsimDynamicElabForVectorsAlways 0
fHsimDynamicElabForVectorsMinputs 0
fHsimCompressMdbForDynamicElab 0
fHsimCompressMdbDiag 0
fHsimDeferForceSelTillReElab 0
fHsimModByModElab 1
fSvNettRealResType 0
fHsimExprID 1
fHsimSequdpon 0
fHsimDatapinOpt 0
fHsimExprPrune 0
fHsimMimoGate 0
fHsimNewChangeCheckFrankch 1
fHsimNoSched0Front 0
fHsimNoSched0FrontForMd 1
fHsimScalReg 0
fHsimNtbVl 0
fHsimICTimeStamp 0
fHsimICDiag 0
fHsimNewCSDF 1
vcselabIncrMode 2
fHsimMPPackDelay 0
fHsimMultDriver 0
fHsimPart 0
fHsimPrlComp 0
fHsimPartTest 0
fHsimTestChangeCheck 0
fHsimTestFlatNodeOrder 0
fHsimTestNState 0
fHsimPartDebug 0
fHsimPartFlags 0
fHsimOdeSched0 0
fHsimNewRootSig 1
fHsimDisableRootSigModeOpt 0
fHsimTestRootSigModeOpt 0
fHsimIncrWriteOnce 0
fHsimUnifInterfaceFlow 1
fHsimUnifInterfaceFlowDiag 0
fHsimUnifInterfaceFlowXmrDiag 0
fHsimUnifInterfaceMultiDrvChk 1
fHsimXVirForGenerateScope 0
fHsimCongruencyIntTestI 0
fHsimCongruencySVA 0
fHsimCongruencySVADbg 0
fHsimCongruencyLatchEdgeFix 0
fHsimCongruencyFlopEdgeFix 0
fHsimCongruencyXprop 0
fHsimCongruencyXpropFix 0
fHsimCongruencyXpropDbsEdge 0
fHsimCongruencyResetRecoveryDbs 0
fHsimCongruencyClockControlDiag 0
fHsimCongruencySampleUpdate 0
fHsimCongruencyFFDbsFix 0
fHsimCongruency 0
fHsimCongruencySlave 0
fHsimCongruencyCombinedLoads 0
fHsimCongruencyFGP 0
fHsimDeraceClockDataUdp 0
fHsimDeraceClockDataLERUpdate 0
fHsimCongruencyPC 0
fHsimCongruencyPCInl 0
fHsimCongruencyPCDbg 0
fHsimCongruencyPCNoReuse 0
fHsimCongruencyDumpHier 0
fHsimCongruencyResolution 0
fHsimCongruencyEveBus 0
fHsimHcExpr 0
fHsCgOptModOpt 0
fHsCgOptSlowProp 0
fHsimCcnOpt 1
fHsimCcnOpt2 1
fHsimCcnOpt3 0
fHsimSmdMap 0
fHsimSmdDiag 0
fHsimSmdSimProf 0
fHsimSgdDiag 0
fHsimRtDiagLite 0
fHsimRtDiagLiteCevent 100
fHsimRtDiag 0
fHsimSkRtDiag 0
fHsimDDBSRtdiag 0
fHsimDbg 0
fHsimCompWithGates 0
fHsimMdbDebugOpt 0
fHsimMdbDebugOptP1 0
fHsimMdbDebugOptP2 0
fHsimMdbPruneOpt 1
fHsimMdbMemOpt 0
hsimRandValue 0
fHsimSimMemProfile 0
fHsimSimTimeProfile 0
fHsimElabMemProfile 0
fHsimElabTimeProfile 0
fHsimElabMemNodesProfile 0
fHsimElabMemAllNodesProfile 0
fHsimDisableVpdGatesProfile 0
fHsimFileProfile 0
fHsimCountProfile 0
fHsimXmrDefault 1
fHsimFuseWireAndReg 0
fHsimFuseSelfDrvLogic 0
fHsimFuseProcess 0
fHsimNoStitchDump 0
fHsimAllExtXmrs 0
fHsimAllExtXmrsDiag 0
fHsimAllExtXmrsAllowClkFusing 0
fHsimAllXmrs 1
fHsimMvsimDb 0
fHsimTaskFuncXmrs 0
fHsimTaskFuncXmrsDbg 0
fHsimAllTaskFuncXmrs 0
fHsimPageArray 16383
fHsimPageControls 16383
hsDfsNodePageElems 0
hsNodePageElems 0
hsFlatNodePageElems 0
hsGateMapPageElems 0
hsGateOffsetPageElems 0
hsGateInputOffsetPageElems 0
hsDbsOffsetPageElems 0
hsMinPulseWidthPageElems 0
hsNodeUpPatternPageElems 0
hsNodeDownPatternPageElems 0
hsNodeUpOffsetPageElems 0
hsNodeEblkOffsetPageElems 0
hsNodeDownOffsetPageElems 0
hsNodeUpdateOffsetPageElems 0
hsSdfOffsetPageElems 0
fHsimPageAllLevelData 0
fHsimAggrCg 0
fHsimViWire 1
fHsimPcCbOpt 1
fHsimAmsTunneling 0
fHsimAmsTunnelingDiag 0
fHsimScUpwardXmrNoSplit 1
fHsimOrigNdbViewOnly 0
fHsimVcsInterface 1
fHsimVcsInterfaceAlias 1
fHsimSVTypesIntf 1
fUnifiedAssertCtrlDiag 0
fHsimEnable2StateScal 0
fHsimDisable2StateScalIbn 0
fHsimVcsInterfaceAliasDbg 0
fHsimVcsInterfaceDbg 0
fHsimVcsVirtIntfDbg 0
fHsimVcsAllIntfVarMem 0
fHsimCheckVIDynLoadOffsets 0
fHsimModInline 1
fHsimModInlineDbg 0
fHsimPCDrvLoadDbg 0
fHsimDrvChk 1
fHsimRtlProcessingNeeded 1
fHsimGrpByGrpElab 0
fHsimGrpByGrpElabMaster 0
fHsimNoParentSplitPC 0
fHsimNusymMode 0
fHsimOneIntfPart 0
fHsimCompressInSingleDb 2
fHsimCompressFlatDb 0
fHsimNoTime0Sched 1
fHsimMdbVectorizeInstances 0
fHsimMdbSplitGates 0
fHsimDeleteInstances 0
fHsimUserDeleteInstances 0
fHsimDeleteGdb 0
fHsimDeleteInstancesMdb 0
fHsimShortInstMap 0
fHsimMdbVectorizationDump 0
fHsimScanVectorize 0
fHsimParallelScanVectorize 0
noInstsInVectorization 0
cHsimNonReplicatedInstances 0
fHsimScanRaptor 0
fHsimConfigFileCount 0
fHsimVectorConstProp 0
fHsimPromoteParam 0
fHsimNoVecInRaptor 0
fRaptorDumpVal 0
fRaptorVecNodes 0
fRaptorVecNodes2 0
fRaptorNonVecNodes 0
fRaptorBdrNodes 0
fRaptorVecGates 0
fRaptorNonVecGates 0
fRaptorTotalNodesBeforeVect 0
fRaptorTotalGatesBeforeVect 0
fHsimCountRaptorBits 0
fHsimNewEvcd 1
fHsimNewEvcdMX 0
fHsimNewEvcdVecRoot 1
fHsimNewEvcdForce 1
fHsimNewEvcdTest 0
fHsimNewEvcdObnDrv 1
fHsimNewEvcdW 1
fHsimNewEvcdWTest 0
fHsimEvcdDbgFlags 0
fHsimNewEvcdMultiDrvFmt 1
fHsimDumpOffsetData 1
fFlopGlitchDetect 0
fHsimClkGlitch 0
fHsimGlitchDumpOnce 0
fHsimDynamicElab 1
fHsimCgVectors2Debug 0
fHsimOdeDynElab 0
fHsimOdeDynElabDiag 0
fHsimOdeSeqUdp 0
fHsimOdeSeqUdpXEdge 0
fHsimOdeSeqUdpDbg 0
fHsimOdeRmvSched0 0
fHsimAllLevelSame 0
fHsimRtlDbsList 0
fHsimPePort 0
fHsimPeXmr 0
fHsimPePortDiag 0
fHsimUdpDbs 0
fHsimRemoveDbgCaps 0
fFsdbGateOnepassTraverse 0
fHsimAllowVecGateInVpd 1
fHsimAllowAllVecGateInVpd 0
fHsimAllowUdpInVpd 1
fHsimAllowAlwaysCombInVpd 1
fHsimAllowAlwaysCombCmpDvcSimv 0
fHsimAllowAlwaysCombDbg 0
fHsimMakeAllP2SPrimary 0
fHsimMakeAllSeqPrimary 0
fHsimNoCcnDump 0
fHsimFsdbProfDiag 0
fVpdSeqGate 0
fVpdUseMaxBCode 0
fVpdHsIntVecGate 0
fVpdHsCmplxVecGate 0
fVpdHsVecGateDiags 0
fSeqGateCodePatch 0
fVpdLongFaninOpt 0
fVpdSeqLongFaninOpt 0
fVpdNoLoopDetect 0
fVpdNoSeqLoopDetect 0
fVpdOptAllowConstDriver 0
fVpdAllowCellReconstruction 0
fVpdRtlForSharedLib 0
fHsimVpdOptGate 1
fHsimVpdOptDelay 0
fHsimVpdOptMPDelay 0
fHsimCbkOptDiag 0
fHsimSK 0
fHsimSharedKernel 1
fHsimOnepass 0
fHsimStitchNew 0
fHsimParallelLevelize 0
fHsimParallelLevelizeDbg 0
fHsimSeqUdpDbsByteArray 0
fHsimCoLocate 0
fHsimSeqUdpEblkOpt 0
fHsimSeqUdpEblkOptDiag 0
fHsimGateInputAndDbsOffsetsOpt 1
fHsimGDBLargeModule 1
fHsimUdpDynElab 0
fHsimCompressData 4
fHsimIgnoreZForDfuse 1
fHsimIgnoreDifferentCaps 0
fHandleGlitchQC 1
fGlitchDetectForAllRtlLoads 0
fHsimFuseConstDriversOpt 1
fHsimMdSchedTr 0
fHsimIgnoreReElab 0
fHsimFuseMultiDrivers 0
fHsimNoSched0Reg 0
fHsimAmsFusionEnabled 0
fHsimRtlDbs 1
fHsimWakeupId 0
fHsimPassiveIbn 0
fHsimBcOpt 1
fHsimCertitude 0
fHsimCertRapAutoTest 0
fHsimRaceDetect 0
fCheckTcCond 0
fHsimScanOptRelaxDbg 0
fHsimScanOptRelaxDbgDynamic 0
fHsimScanOptRelaxDbgDynamicPli 0
fHsimScanOptRelaxDbgDiag 0
fHsimScanOptRelaxDbgDiagHi 0
fHsimScanOptNoErrorOnPliAccess 0
fHsimScanOptTiming 0
fRelaxIbnSchedCheck 0
fHsimScanOptNoDumpCombo 0
fHsimScanOptPrintSwitchState 0
fHsimScanOptSelectiveSwitchOn 0
fHsimScanOptSingleSEPliOpt 1
fHsimScanOptDesignHasDebugAccessOnly 0
fHsimScanOptPrintPcode 0
fHsimScanDbgPerf 0
fHsimNoStitchMap 0
fHsimUnifiedModName 0
fHsimCbkMemOptDebug 0
fHsimMasterModuleOnly 0
fHsimUpHierIC 0
fHsimMdbOptimizeSelects 0
fHsimMdbScalarizePorts 0
fHsimMdbOptimizeSelectsHeuristic 1
fHsimMdb1006Partition 0
fHsimVectorPgate 0
fHsimNoHs 0
fHsimXmrPartition 0
fHsimNewPartition 0
fHsimElabPart 0
fHsimElabPartThreshHoldDesign 1
fHsimPMdb 0
fHsimParitionCellInstNum 1000
fHsimParitionCellNodeNum 1000
fHsimParitionCellXMRNum 1000
fHsimNewPartCutSingleInstLimit 268435455
fHsimElabModDistNum 0
fHsimElabPartThreshHoldModule 3000000
fHsimPCPortPartition 0
fHsimPortPartition 0
fHsimDumpMdb 0
fHsimElabDiag 0
fHsimSimpCollect 0
fHsimPcodeDiag 0
fHsimFastelab 0
fHsimMacroOpt 0
fHsimSkipOpt 0
fHsimSkipOptFanoutlimit 0
fHsimSkipOptRootlimit 0
fHsimFuseDelayChains 0
fFusempchainsFanoutlimit 0
fFusempchainsDiagCount 0
fHsimCgVectorGates 0
fHsimCgVectorGates1 0
fHsimCgVectorGates2 0
fHsimCgVectorGatesNoReElab 0
fHsimCgScalarGates 0
fHsimCgScalarGatesExpr 0
fHsimCgScalarGatesLut 0
fHsimCgRtl 100000
fHsimCgRtlFilter 0
fHsimCgRtlDebug 0
fHsimCgRtlSize 15
fHsimNewCgRt 0
fHsimNewCgMPRt 0
fHsimNewCgMPRetain 0
fHsimCgRtlInfra 1
fHsimGlueOpt 0
fHsimPGatePatchOpt 0
fHsimCgNoPic 0
fHsimElabModCg 0
fPossibleNullChecks 0
fHsimProcessNoSplit 1
fHsimMdbOptInSchedDelta 0
fScaleTimeValue 0
fDebugTimeScale 0
fPartCompSDF 0
fHsimNbaGate 1
fDumpDtviInfoInSC 0
fDumpSDFBasedMod 1
fHsimSdfIC 0
fOptimisticNtcSolver 0
fHsimAllMtm 0
fHsimAllMtmPat 0
fHsimSdgOptEnable 0
fHsimSVTypesRefPorts 0
fHsimGrpByGrpElabIncr 0
fHsimMarkRefereeInVcsElab 0
fHsimStreamOpFix 1
fHsimInterface 0
fHsimMxWrapOpt 0
fHsimMxTopBdryOpt 0
fHsimClasses 0
fHsimAggressiveDce 0
fHsimDceDebug 1
fHsimDceDebugUseHeuristics 1
fHsimMdbNewDebugOpt 0
fHsimMdbNewDebugOptExitOnError 1
fHsimNewDebugOptMemDiag 0
hsGlobalVerboseLevel 0
fHsimMdbVectorConstProp 1
fHsimEnableSeqUdpWrite 0
fHsimDumpMDBOnlyForSeqUdp 0
fHsimInitRegRandom 0
fHsimInitRegRandomVcs 1
fEnableNewFinalStrHash 0
fEnableNewAssert 1
fRunDbgDmma 0
fAssrtCtrlSigChk 1
fCheckSigValidity 0
fUniqPriToAstRewrite 0
fUniqPriToAstCtrl 0
fAssertcontrolUniqPriNewImpl 0
fRTLoopDectEna 0
fCmplLoopDectEna 0
fHsimMopFlow 1
fUCaseLabelCtrl 0
fUniSolRtSvaEna 1
fUniSolSvaEna 1
fXpropRtCtrlCallerOnly 0
fHsimRaptorPart 0
fHsimEnableDbsMemOpt 1
fHsimDebugDbsMemOpt 0
fHsimRenPart 0
fHsimShortElabInsts 0
fHsimXmrAllWires 0
fHsimXmrDiag 0
fHsimXmrPort 0
fHsimFalcon 1
fHsimGenForProfile 0
fCompressSDF 0
fDlpSvtbExclElab 0
fHsimGates1209 0
fHsimCgRtlNoShareSmd 0
fHsimGenForErSum 0
fVpdOpt 1
fHsimMdbCell 0
fHsimCellDebug 0
fHsimNoPeekInMdbCell 0
igetOpcodeSmdPtrLayoutId -1
igetFieldSmdPtr -1
fDebugDump 1
fHsimOrigNodeNames 0
fHsimCgVectors2VOnly 0
fHsimMdbDeltaGate 0
fHsimMdbDeltaGateAggr 0
fHsimMdbVecDeltaGate 1
fHsimVpdOptVfsDB 1
fHsimMdbPruneVpdGates 1
fHsimPcPe 0
fHsimVpdGateOnlyFlag 1
fHsimMxConnFrc 0
fHsimNewForceCbkVec 0
fHsimNewForceCbkVecDiag 0
fHsimMdbReplaceVpdHighConn 1
fHsimVpdOptSVTypes 1
fHsHasPeUpXmr 0
fHsimCompactVpdFn 1
fHsimPIP 0
fHsimRTLoopDectOrgName 0
fHsimVpdOptPC 0
fHsimFusePeXmrFo 0
fHsimXmrSched 0
fHsimNoMdg 0
fHsimVectorGates 0
fHsimRtlLite 0
fHsimMdbcgLut 0
fHsimMdbcgSelective 0
fHsimVcselabGates 0
fHsimMdbcgLevelize 0
fHsimParGateEvalMode 0
fHsimDFuseVectors 0
fHsimDFuseZero 0
fHsimDFuseOpt 1
fHsimPruneOpt 0
fHsimSeqUdpPruneWithConstInputs 0
fHsimSafeDFuse 0
fHsimVpdOptExpVec 0
fHsimVpdOptSelGate 1
fHsimVpdOptSkipFuncPorts 0
fHsimVpdOptAlways 1
fHsimVpdOptMdbCell 0
fHsimVpdOptPartialMdb 1
fHsimVpdOptPartitionGate 1
fHsimVpdOptXmr 1
fHsimVpdOptMoreLevels 1
fHsimVpdHilRtl 0
fHsimSWave 0
fHsimNoSched0InCell 1
fHsimPartialMdb 0
hsimPdbLargeOffsetThreshold 1048576
fHsimFlatCell 0
fHsimFlatCellLimit 0
fHsimRegBank 0
fHsimHmetisMaxPartSize 0
fHsimHmetisGateWt 0
fHsimHmetisUbFactor 0
fHsimHmetis 0
fHsimHmetisDiag 0
fHsimRenumGatesForMdbCell 0
fHsimHmetisMinPart 0
fHsim2stCell 0
fHsim2stCellMinSize 0
fHsimMdbcgDebug 0
fHsimMdbcgDebugLite 0
fHsimMdbcgDistrib 0
fHsimMdbcgSepmem 1
fHsimMdbcgObjDiag 0
fHsimMdbcg2stDiag 0
fHsimMdbcgRttrace 0
fHsimMdbVectorGateGroup 1
fHsimMdbProcDfuse 1
fHsimMdbHilPrune 0
fHsCgOpt 1
fHsCgOptUdp 1
fHsCgOptRtl 1
fHsCgOptDiag 0
fHsCgOptAggr 0
fHsCgOptNoZCheck 0
fHsCgOptEnableZSupport 0
fHsCgOpt4StateInfra 0
fHsCgOptDce 0
fHsCgOptUdpChkDataForWakeup 1
fHsCgOptXprop 0
fHsimMdbcgDiag 0
fHsCgMaxInputs 6
fHsCgOptFwdPass 1
fHsimHpnodes 0
fLightDump 0
fHDLCosim 0
fHDLCosimDebug 0
fHDLCosimTimeCoupled 0
fHDLCosimTimeCoupledPorts 0
HDLCosimMaxDataPerDpi 1
HDLCosimMaxCallsPerDpi 2147483647
fHDLCosimCompileDUT 0
fHDLCosimCustomCompile 0
fHDLCosimBoundaryAnalysis 0
fVpdBeforeScan 1
fHsCgOptMiSched0 0
fgcAddSched0 0
fParamClassOptRtDiag 0
fHsRegress 0
fHsBenchmark 0
fHsimCgScalarVerilogForce 1
fVcsElabToRoot 1
fHilIbnObnCallByName 0
fHsimMdbcgCellPartition 0
fHsimCompressVpdSig 0
fHsimLowPowerOpt 0
fHsimUdpOpt 1
fHsVecOneld 0
fNativeVpdDebug 0
fNewDtviFuse 0
fHsimVcsGenTLS 1
fAssertSuccDebugLevelDump 0
fHsimMinputsChangeCheck 0
fHsimClkLayout 0
fHsimSortLayout 0
fHsimIslandLayout 0
fHsimConfigSched0 0
fHsimSelectFuseAfterDfuse 0
fHsimFoldedCell 0
fHsimSWaveEmul 0
fHsimSWaveDumpMDB 0
fHsimSWaveDumpFlatData 0
fHsimRenumberAlias 0
fHsimAliasRenumbered 0
fHilCgMode 115
fHsimUnionOpt 0
fHsimFuseSGDBoundaryNodes 0
fHsimRemoveCapsVec 0
fHsimCertRaptScal 0
fHsimCertRaptMdbClock 0
fHsCgOptMux 0
fHsCgOptFrc 0
fHsCgOpt30 0
fHsLpNoCapsOpt 0
fHsCgOpt4State 1
fSkipStrChangeOnDelay 1
fHsimTcheckOpt 0
fHsCgOptMuxMClk 0
fHsCgOptMuxFrc 0
fHsCgOptNoPcb 0
fHsCgOptMin1 0
fHsCgOptUdpChk 0
fHsChkXForSlowSigProp 1
fHsimVcsParallelDbg 0
fHsimVcsParallelStrategy 0
fHsimVcsParallelOpt 0
fHsimVcsParallelSubLevel 4
fHsimParallelEblk 0
fHsimByteCodeParts 1
fFgpNovlInComp 0
fFutEventPRL 0
fFgpNbaDelay 0
fHsimDbsFlagsByteArray 0
fHsimDbsFlagsByteArrayTC 0
fHsimDbsFlagsThreadArray 0
fHsimGateEdgeEventSched 0
fHsimEgschedDynelab 0
fHsimUdpClkDynelab 0
fUdpLayoutOnClk 0
fHsimDiagClk 1
fDbsPreCheck 0
fHsimSched0Analysis 0
fHsimMultiDriverSched0 0
fHsimLargeIbnSched 0
fFgpHierarchical 0
fFgpHierAllElabModAsRoot 0
fFgpHierPCElabModAsRoot 0
fFgpAdjustDataLevelOfLatch 1
fHsimUdpXedgeEval 0
fFgpRaceCheck 0
fFgpUnifyClk 0
fFgpSmallClkTree 0
fFgpSmallRtlClkTree 4
fFgpNoRtlUnlink 0
fFgpNoRtlAuxLevel 0
fFgpNumPartitions 8
fFgpMultiSocketCompile 0
fFgpDataDepOn 0
fFgpDDIgnore 0
fFgpTbCbOn 0
fFgpTbEvOn 1
fFgpTbNoVSA 0
fFgpTbEvXmr 0
fFgpTbEvCgCall 1
fFgpDisabledLevel 512
fFgpSched0User 0
fFgpNoSdDelayedNbas 1
fFgpNoEvNbas 1
fFgpTimingFlags 0
fFgpSched0Level 0
fHsimFgpMultiClock 0
fFgpScanOptFix 0
fFgpSched0UdpData 0
fFgpLoadBalance0CompileTime 1
fFgpDepositDiag 0
fFgpEvtDiag.diagOn 0
fFgpEvtDiag.printAllNodes 0
fFgpMangleDiagLog 0
fFgpMultiExclDiag 0
fFgpSingleExclReason 0
fHsDoFaninFanoutSanity 0
fHsFgpNonDbsOva 1
fFgpParallelTask 1
fFgpIbnSched 0
fFgpIbnSchedOpt 0
fFgpIbnSchedThreshold 0
fFgpIbnSchedDyn 0
fFgpMpStateByte 0
fFgpTcStateByte 0
fHsimVirtIntfDynLoadSched 0
fFgpNoRtimeFgp 0
fHsFgpGlSched0 0
fFgpExclReason 0
fHsimIslandByIslandElab 0
fHsimIslandByIslandFlat 151652416
fHsimIslandByIslandFlat1 4
fHsimVpdIBIF 0
fHsimXmrIBIF 0
fHsimReportTime 0
fHsimElabJ 0
hf_fHsimElabJ 0
fHsimElabJOpt 0
fHsimSchedMinput 0
fHsimSchedSeqPrim 0
fHsimSchedSelectFanout 0
fHsimSchedSelectFanoutDebug 0
fSpecifyInDesign 0
fFgpDynamicReadOn 0
fHsCgOptAllUc 0
fHsimXmrRepl 0
fZoix 0
fHsimDfuseNewOpt 0
fHsimBfuseNewOpt 0
fFgpXmrSched 0
fHsimClearClkCaps 0
fHsimDiagClkConfig 0
fHsimDiagClkConfigDebug 0
fHsimDiagClkConfigDumpAll 0
fHsDiagClkConfigPara 0
fHsimDiagClkConfigAn 0
fHsimCanDumpClkConfig 0
fFgpInitRout 0
fFgpIgnoreExclSD 0
fHsCgOptNoClockFusing 0
fHsClkWheelLimit 50000
fHsimPCSharedLibSpecified 0
fHsFgpSchedCgUcLoads 1
fHsCgOptNewSelCheck 1
fFgpReportUnsafeFuncs 0
fHsCgOptUncPrlThreshold 4
fHsSVNettypePerfOpt 0
fHsimLowPowerRetAnalysisInChild 0
fRetainWithDelayedSig 0
fHsimChargeDecay 0
fFgpUseAltEgLayout 0
fFgpTbReactiveLite 0