48 lines
3.1 KiB
Plaintext
48 lines
3.1 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit EL2_IC_TAG :
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module EL2_IC_TAG :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<32>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>, test : UInt}
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node _T = bits(io.ic_rw_addr, 5, 4) @[el2_ifu_ic_mem.scala 68:70]
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wire _T_1 : UInt<1>[1] @[el2_lib.scala 40:24]
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_T_1[0] <= UInt<1>("h01") @[el2_lib.scala 40:24]
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node _T_2 = eq(_T, _T_1[0]) @[el2_ifu_ic_mem.scala 68:93]
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wire _T_3 : UInt<1>[2] @[el2_lib.scala 40:24]
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_T_3[0] <= _T_2 @[el2_lib.scala 40:24]
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_T_3[1] <= _T_2 @[el2_lib.scala 40:24]
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node _T_4 = cat(_T_3[0], _T_3[1]) @[Cat.scala 29:58]
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node ic_tag_wren = and(io.ic_wr_en, _T_4) @[el2_ifu_ic_mem.scala 68:33]
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node _T_5 = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 70:68]
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wire _T_6 : UInt<1>[2] @[el2_lib.scala 40:24]
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_T_6[0] <= _T_5 @[el2_lib.scala 40:24]
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_T_6[1] <= _T_5 @[el2_lib.scala 40:24]
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node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58]
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node ic_debug_rd_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 70:93]
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node _T_8 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 71:68]
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wire _T_9 : UInt<1>[2] @[el2_lib.scala 40:24]
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_T_9[0] <= _T_8 @[el2_lib.scala 40:24]
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_T_9[1] <= _T_8 @[el2_lib.scala 40:24]
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node _T_10 = cat(_T_9[0], _T_9[1]) @[Cat.scala 29:58]
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node ic_debug_wr_way_en = and(_T_10, io.ic_debug_way) @[el2_ifu_ic_mem.scala 71:93]
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node _T_11 = or(io.ic_rd_en, io.clk_override) @[el2_ifu_ic_mem.scala 72:55]
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wire _T_12 : UInt<1>[2] @[el2_lib.scala 40:24]
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_T_12[0] <= _T_11 @[el2_lib.scala 40:24]
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_T_12[1] <= _T_11 @[el2_lib.scala 40:24]
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node _T_13 = cat(_T_12[0], _T_12[1]) @[Cat.scala 29:58]
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node _T_14 = or(_T_13, io.ic_wr_en) @[el2_ifu_ic_mem.scala 72:74]
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node _T_15 = or(_T_14, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 72:88]
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node ic_tag_clken = or(_T_15, ic_debug_rd_way_en) @[el2_ifu_ic_mem.scala 72:109]
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reg ic_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 74:28]
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ic_rd_en_ff <= io.ic_rd_en @[el2_ifu_ic_mem.scala 74:28]
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node _T_16 = bits(io.ic_rw_addr, 31, 13) @[el2_ifu_ic_mem.scala 75:44]
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reg ic_rw_addr_ff : UInt, clock @[el2_ifu_ic_mem.scala 75:30]
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ic_rw_addr_ff <= _T_16 @[el2_ifu_ic_mem.scala 75:30]
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node ic_tag_wren_q = or(ic_tag_wren, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 77:35]
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io.test <= ic_tag_wren @[el2_ifu_ic_mem.scala 80:10]
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io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 81:18]
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io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 82:16]
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io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 83:26]
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