88 lines
3.2 KiB
Scala
88 lines
3.2 KiB
Scala
package ifu
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import lib._
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import chisel3._
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import chisel3.util._
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class el2_ifu_ic_mem extends Module with param{
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val io = IO(new Bundle{
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val clk = Input(Bool())
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val rst_l = Input(Bool())
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val clk_override = Input(Bool())
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val dec_tlu_core_ecc_disable = Input(Bool())
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val ic_rw_addr = Input(UInt(31.W))
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val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_rd_en = Input(Bool())
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val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
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val ic_debug_rd_en = Input(Bool())
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val ic_debug_wr_en = Input(Bool())
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val ic_debug_tag_array = Input(Bool())
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val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_premux_data = Input(UInt(64.W))
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val ic_sel_premux_data = Input(Bool())
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val ic_wr_data = Vec(ICACHE_BANK_WAY, Input(UInt(71.W)))
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val ic_rd_data = Output(UInt(64.W))
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val ic_debug_rd_data = Output(UInt(71.W))
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val ictag_debug_rd_data = Output(UInt(26.W))
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val ic_debug_wr_data = Input(UInt(71.W))
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val ic_eccerr = Output(UInt(ICACHE_BANK_WAY.W))
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val ic_parerr = Output(UInt(ICACHE_BANK_WAY.W))
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val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
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val ic_tag_perr = Output(Bool())
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val scan_mode = Input(Bool())
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})
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io.ic_tag_perr := 0.U
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io.ic_rd_hit := 0.U
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io.ic_parerr := 0.U
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io.ic_eccerr := 0.U
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io.ictag_debug_rd_data := 0.U
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io.ic_debug_rd_data := 0.U
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io.ic_rd_data := 0.U
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//val icache_tag = Module(new kncpa)
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}
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class EL2_IC_TAG extends Module with el2_lib with param {
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val io = IO(new Bundle{
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val clk = Input(Bool())
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val rst_l = Input(Bool())
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val clk_override = Input(Bool())
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val dec_tlu_core_ecc_disable = Input(Bool())
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val ic_rw_addr = Input(UInt(32.W)) // TODO : In SV we have 31:3 what should we do here
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val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_rd_en = Input(Bool())
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val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
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val ic_debug_rd_en = Input(Bool())
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val ic_debug_wr_en = Input(Bool())
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val ic_debug_tag_array = Input(Bool())
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val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
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val ictag_debug_rd_data = Output(UInt(26.W))
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val ic_debug_wr_data = Input(UInt(71.W))
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val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
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val ic_tag_perr = Output(Bool())
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val scan_mode = Input(Bool())
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val test = Output(UInt())
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})
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val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
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repl(ICACHE_NUM_WAYS-1, 1.U))
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val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
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val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
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val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en |
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ic_debug_rd_way_en
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val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U)
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val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31,ICACHE_TAG_LO))
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val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
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val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
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io.test:= ic_tag_wren
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io.ic_tag_perr := 0.U
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io.ic_rd_hit := 0.U
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io.ictag_debug_rd_data := 0.U
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}
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object ifu_ic extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG()))
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} |