76 lines
2.8 KiB
Scala
76 lines
2.8 KiB
Scala
package lib
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import chisel3._
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import chisel3.util._
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trait param {
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val BTB_ADDR_HI = 9
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val BTB_ADDR_LO = 2
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val BTB_BTAG_SIZE = 5
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val BTB_FOLD2_INDEX_HASH = false
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val BTB_INDEX1_HI = 9
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val BTB_INDEX1_LO = 2
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val BTB_INDEX2_HI = 17
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val BTB_INDEX2_LO = 10
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val BTB_INDEX3_HI = 25
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val BTB_INDEX3_LO = 18
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val BHT_GHR_HASH_1 = true
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val BHT_GHR_SIZE = 8
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val ICACHE_NUM_WAYS = 2
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val ICACHE_INDEX_HI = 12
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val ICACHE_BANK_WAY = 2
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val ICACHE_BEAT_ADDR_HI = 5
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val ICACHE_TAG_LO = 13
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}
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trait el2_lib extends param{
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def el2_btb_tag_hash(pc : UInt) =
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(VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1))).reduce(_^_)
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def el2_btb_tag_hash_fold(pc : UInt) =
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pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
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def el2_btb_addr_hash(pc : UInt) =
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if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
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else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
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def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
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if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
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else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
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def repl(b:Int, a:UInt) : UInt =
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VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
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// Move rvecc_encode to a proper trait
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def rvecc_encode(din:UInt) = { //Done for verification and testing
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val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
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val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
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val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
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val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
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val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
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val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
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val w0 = Wire(Vec(18,UInt(1.W)))
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val w1 = Wire(Vec(18,UInt(1.W)))
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val w2 = Wire(Vec(18,UInt(1.W)))
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val w3 = Wire(Vec(15,UInt(1.W)))
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val w4 = Wire(Vec(15,UInt(1.W)))
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val w5 = Wire(Vec(6, UInt(1.W)))
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var j = 0;var k = 0;var m = 0;
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var x = 0;var y = 0;var z = 0
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for(i <- 0 to 31)
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{
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if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
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if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
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if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
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if(mask3(i)==1) {w3(x) := din(i); x = x +1 }
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if(mask4(i)==1) {w4(y) := din(i); y = y +1 }
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if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
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}
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val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
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Cat(din.xorR ^ w6.xorR, w6)
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}
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}
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