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quasar/el2_ifu_ifc_ctrl.fir

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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl :
input clock : Clock
input reset : UInt<1>
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, sel_last_addr_bf : UInt<1>, sel_btb_addr_bf : UInt<1>, sel_next_addr_bf : UInt<1>}
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:30]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 43:24]
wire fetch_addr_bf : UInt<32>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 71:36]
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 72:34]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 72:34]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 72:24]
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 74:20]
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 74:20]
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 74:10]
node _T_2 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 76:26]
node _T_3 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 76:49]
node _T_4 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 76:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 76:69]
node _T_6 = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 76:46]
io.sel_last_addr_bf <= _T_6 @[el2_ifu_ifc_ctrl.scala 76:23]
node _T_7 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 77:26]
node _T_8 = and(_T_7, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 77:46]
node _T_9 = and(_T_8, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 77:67]
node _T_10 = and(_T_9, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 77:91]
io.sel_btb_addr_bf <= _T_10 @[el2_ifu_ifc_ctrl.scala 77:23]
node _T_11 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 78:26]
node _T_12 = and(_T_11, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 78:46]
node _T_13 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 78:69]
node _T_14 = and(_T_12, _T_13) @[el2_ifu_ifc_ctrl.scala 78:67]
node _T_15 = and(_T_14, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 78:92]
io.sel_next_addr_bf <= _T_15 @[el2_ifu_ifc_ctrl.scala 78:23]
node _T_16 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 81:56]
node _T_17 = bits(io.sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 82:49]
node _T_18 = bits(io.sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 83:48]
node _T_19 = bits(io.sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:49]
node _T_20 = mux(_T_16, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = mux(_T_17, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_22 = mux(_T_18, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_23 = mux(_T_19, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_24 = or(_T_20, _T_21) @[Mux.scala 27:72]
node _T_25 = or(_T_24, _T_22) @[Mux.scala 27:72]
node _T_26 = or(_T_25, _T_23) @[Mux.scala 27:72]
wire _T_27 : UInt<32> @[Mux.scala 27:72]
_T_27 <= _T_26 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 81:24]
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 88:13]
node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 90:45]
node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 90:51]
node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 90:51]
node _T_31 = cat(_T_30, UInt<1>("h00")) @[Cat.scala 29:58]
fetch_addr_next <= _T_31 @[el2_ifu_ifc_ctrl.scala 90:19]
node _T_32 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
io.ifc_fetch_req_bf_raw <= _T_32 @[el2_ifu_ifc_ctrl.scala 93:27]
node _T_33 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
node _T_34 = not(_T_33) @[el2_ifu_ifc_ctrl.scala 95:70]
node _T_35 = and(fb_full_f_ns, _T_34) @[el2_ifu_ifc_ctrl.scala 95:68]
node _T_36 = not(_T_35) @[el2_ifu_ifc_ctrl.scala 95:53]
node _T_37 = and(io.ifc_fetch_req_bf_raw, _T_36) @[el2_ifu_ifc_ctrl.scala 95:51]
node _T_38 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 96:5]
node _T_39 = and(_T_37, _T_38) @[el2_ifu_ifc_ctrl.scala 95:114]
node _T_40 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 96:18]
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctrl.scala 96:16]
node _T_42 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 96:39]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctrl.scala 96:37]
io.ifc_fetch_req_bf <= _T_43 @[el2_ifu_ifc_ctrl.scala 95:23]
node _T_44 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 98:37]
fetch_bf_en <= _T_44 @[el2_ifu_ifc_ctrl.scala 98:15]
node _T_45 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 100:34]
node _T_46 = and(io.ifc_fetch_req_f, _T_45) @[el2_ifu_ifc_ctrl.scala 100:32]
node _T_47 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 100:49]
node _T_48 = and(_T_46, _T_47) @[el2_ifu_ifc_ctrl.scala 100:47]
miss_f <= _T_48 @[el2_ifu_ifc_ctrl.scala 100:10]
node _T_49 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 102:39]
node _T_50 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:63]
node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 102:61]
node _T_52 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 102:76]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctrl.scala 102:74]
node _T_54 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 102:86]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctrl.scala 102:84]
mb_empty_mod <= _T_55 @[el2_ifu_ifc_ctrl.scala 102:16]
node _T_56 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 104:35]
goto_idle <= _T_56 @[el2_ifu_ifc_ctrl.scala 104:13]
node _T_57 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:38]
node _T_58 = and(io.exu_flush_final, _T_57) @[el2_ifu_ifc_ctrl.scala 106:36]
node _T_59 = and(_T_58, idle) @[el2_ifu_ifc_ctrl.scala 106:67]
leave_idle <= _T_59 @[el2_ifu_ifc_ctrl.scala 106:14]
node _T_60 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 108:29]
node _T_61 = not(_T_60) @[el2_ifu_ifc_ctrl.scala 108:23]
node _T_62 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 108:40]
node _T_63 = and(_T_61, _T_62) @[el2_ifu_ifc_ctrl.scala 108:33]
node _T_64 = and(_T_63, miss_f) @[el2_ifu_ifc_ctrl.scala 108:44]
node _T_65 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 108:55]
node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 108:53]
node _T_67 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 109:11]
node _T_68 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 109:17]
node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 109:15]
node _T_70 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 109:33]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctrl.scala 109:31]
node next_state_1 = or(_T_66, _T_71) @[el2_ifu_ifc_ctrl.scala 108:67]
node _T_72 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:23]
node _T_73 = and(_T_72, leave_idle) @[el2_ifu_ifc_ctrl.scala 111:34]
node _T_74 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 111:56]
node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:62]
node _T_76 = and(_T_74, _T_75) @[el2_ifu_ifc_ctrl.scala 111:60]
node next_state_0 = or(_T_73, _T_76) @[el2_ifu_ifc_ctrl.scala 111:48]
node _T_77 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
reg _T_78 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
_T_78 <= _T_77 @[el2_ifu_ifc_ctrl.scala 113:19]
state <= _T_78 @[el2_ifu_ifc_ctrl.scala 113:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 118:12]
node _T_79 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 120:38]
node _T_80 = and(io.ifu_fb_consume1, _T_79) @[el2_ifu_ifc_ctrl.scala 120:36]
node _T_81 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 120:61]
node _T_82 = or(_T_81, miss_f) @[el2_ifu_ifc_ctrl.scala 120:81]
node _T_83 = and(_T_80, _T_82) @[el2_ifu_ifc_ctrl.scala 120:58]
node _T_84 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:25]
node _T_85 = or(_T_83, _T_84) @[el2_ifu_ifc_ctrl.scala 120:92]
fb_right <= _T_85 @[el2_ifu_ifc_ctrl.scala 120:12]
node _T_86 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 123:39]
node _T_87 = or(_T_86, miss_f) @[el2_ifu_ifc_ctrl.scala 123:59]
node _T_88 = and(io.ifu_fb_consume2, _T_87) @[el2_ifu_ifc_ctrl.scala 123:36]
fb_right2 <= _T_88 @[el2_ifu_ifc_ctrl.scala 123:13]
node _T_89 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 124:56]
node _T_90 = not(_T_89) @[el2_ifu_ifc_ctrl.scala 124:35]
node _T_91 = and(io.ifc_fetch_req_f, _T_90) @[el2_ifu_ifc_ctrl.scala 124:33]
node _T_92 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 124:80]
node _T_93 = and(_T_91, _T_92) @[el2_ifu_ifc_ctrl.scala 124:78]
fb_left <= _T_93 @[el2_ifu_ifc_ctrl.scala 124:11]
node _T_94 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 126:37]
node _T_95 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 127:6]
node _T_96 = and(_T_95, fb_right) @[el2_ifu_ifc_ctrl.scala 127:16]
node _T_97 = bits(_T_96, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:28]
node _T_98 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 127:62]
node _T_99 = cat(UInt<1>("h00"), _T_98) @[Cat.scala 29:58]
node _T_100 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
node _T_101 = and(_T_100, fb_right2) @[el2_ifu_ifc_ctrl.scala 128:16]
node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:29]
node _T_103 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 128:63]
node _T_104 = cat(UInt<2>("h00"), _T_103) @[Cat.scala 29:58]
node _T_105 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
node _T_106 = and(_T_105, fb_left) @[el2_ifu_ifc_ctrl.scala 129:16]
node _T_107 = bits(_T_106, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:27]
node _T_108 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 129:51]
node _T_109 = cat(_T_108, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_110 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
node _T_111 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 130:18]
node _T_112 = and(_T_110, _T_111) @[el2_ifu_ifc_ctrl.scala 130:16]
node _T_113 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 130:30]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctrl.scala 130:28]
node _T_115 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 130:43]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctrl.scala 130:41]
node _T_117 = bits(_T_116, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:53]
node _T_118 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 130:73]
node _T_119 = mux(_T_94, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_97, _T_99, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = mux(_T_102, _T_104, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_107, _T_109, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_117, _T_118, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = or(_T_119, _T_120) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
wire _T_128 : UInt<4> @[Mux.scala 27:72]
_T_128 <= _T_127 @[Mux.scala 27:72]
fb_write_ns <= _T_128 @[el2_ifu_ifc_ctrl.scala 126:15]
node _T_129 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 133:38]
reg _T_130 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 133:26]
_T_130 <= _T_129 @[el2_ifu_ifc_ctrl.scala 133:26]
fb_full_f_ns <= _T_130 @[el2_ifu_ifc_ctrl.scala 133:16]
node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 135:17]
idle <= _T_131 @[el2_ifu_ifc_ctrl.scala 135:8]
node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 136:16]
wfm <= _T_132 @[el2_ifu_ifc_ctrl.scala 136:7]
node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 138:30]
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 138:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 139:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 139:26]
reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:24]
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 140:24]
fb_write_f <= _T_134 @[el2_ifu_ifc_ctrl.scala 140:14]
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
node _T_137 = not(_T_136) @[el2_ifu_ifc_ctrl.scala 143:5]
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctrl.scala 142:75]
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctrl.scala 142:60]
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctrl.scala 142:33]
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctrl.scala 142:26]
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 214:25]
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 214:47]
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 217:14]
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
node _T_145 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = dshr(io.dec_tlu_mrac_ff, _T_146) @[el2_ifu_ifc_ctrl.scala 150:53]
node _T_148 = bits(_T_147, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
node _T_149 = not(_T_148) @[el2_ifu_ifc_ctrl.scala 150:34]
io.ifc_fetch_uncacheable_bf <= _T_149 @[el2_ifu_ifc_ctrl.scala 150:31]
reg _T_150 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 154:32]
_T_150 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 154:32]
io.ifc_fetch_req_f <= _T_150 @[el2_ifu_ifc_ctrl.scala 154:22]
node _T_151 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 157:88]
reg _T_152 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_151 : @[Reg.scala 28:19]
_T_152 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_152 @[el2_ifu_ifc_ctrl.scala 157:23]
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