18 lines
556 B
Verilog
18 lines
556 B
Verilog
module test(
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input clock,
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input reset,
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input [3:0] io_in1,
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input [4:0] io_in2_waleed,
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input [4:0] io_in2_laraib,
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input [4:0] io_in2_hameed,
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output [4:0] io_out2_waleed,
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output [4:0] io_out2_laraib,
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output [4:0] io_out2_hameed,
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output io_out1
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);
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assign io_out2_waleed = 5'h0; // @[el2_ifu_bp_ctl.scala 228:20]
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assign io_out2_laraib = 5'h0; // @[el2_ifu_bp_ctl.scala 229:20]
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assign io_out2_hameed = 5'h0; // @[el2_ifu_bp_ctl.scala 230:20]
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assign io_out1 = 1'h0; // @[el2_ifu_bp_ctl.scala 231:13]
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endmodule
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