quasar/ifu_aln_ctl.anno.json

53 lines
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_ifu_pmu_instr_aligned",
"sources":[
"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_bits_br_error",
"sources":[
"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume1",
"sources":[
"~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume2",
"sources":[
"~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ifu_aln_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ifu_aln_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]