234 lines
11 KiB
Verilog
234 lines
11 KiB
Verilog
module el2_ifu_ifc_ctrl(
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input clock,
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input reset,
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input io_free_clk,
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input io_active_clk,
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input io_rst_l,
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input io_scan_mode,
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input io_ic_hit_f,
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input io_ifu_ic_mb_empty,
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input io_ifu_fb_consume1,
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input io_ifu_fb_consume2,
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input io_dec_tlu_flush_noredir_wb,
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input io_exu_flush_final,
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input [30:0] io_exu_flush_path_final,
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input io_ifu_bp_hit_taken_f,
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input [30:0] io_ifu_bp_btb_target_f,
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input io_ic_dma_active,
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input io_ic_write_stall,
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input io_dma_iccm_stall_any,
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input [31:0] io_dec_tlu_mrac_ff,
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output [30:0] io_ifc_fetch_addr_f,
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output [30:0] io_ifc_fetch_addr_bf,
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output io_ifc_fetch_req_f,
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output io_ifu_pmu_fetch_stall,
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output io_ifc_fetch_uncacheable_bf,
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output io_ifc_fetch_req_bf,
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output io_ifc_fetch_req_bf_raw,
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output io_ifc_iccm_access_bf,
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output io_ifc_region_acc_fault_bf,
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output io_ifc_dma_access_ok,
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output io_sel_last_addr_bf,
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output io_sel_btb_addr_bf,
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output io_sel_next_addr_bf
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_2;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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reg [31:0] _RAND_5;
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`endif // RANDOMIZE_REG_INIT
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reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 72:34]
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wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 71:36]
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wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 76:26]
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wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 76:49]
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wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 76:71]
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wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 76:69]
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wire _T_8 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 77:46]
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wire _T_9 = _T_8 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 77:67]
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wire _T_13 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 78:69]
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wire _T_14 = _T_8 & _T_13; // @[el2_ifu_ifc_ctrl.scala 78:67]
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wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_21 = io_sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_22 = io_sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
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wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 90:51]
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wire [30:0] _T_31 = {_T_30,1'h0}; // @[Cat.scala 29:58]
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wire [31:0] fetch_addr_next = {{1'd0}, _T_31}; // @[el2_ifu_ifc_ctrl.scala 90:19]
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wire [31:0] _T_23 = io_sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
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wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
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wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
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wire [31:0] _GEN_1 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
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wire [31:0] _T_26 = _GEN_1 | _T_23; // @[Mux.scala 27:72]
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reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
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wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 135:17]
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wire _T_33 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
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wire _T_34 = ~_T_33; // @[el2_ifu_ifc_ctrl.scala 95:70]
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wire [3:0] _T_119 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
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wire _T_79 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 120:38]
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wire _T_80 = io_ifu_fb_consume1 & _T_79; // @[el2_ifu_ifc_ctrl.scala 120:36]
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wire _T_46 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
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wire miss_f = _T_46 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
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wire _T_82 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 120:81]
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wire _T_83 = _T_80 & _T_82; // @[el2_ifu_ifc_ctrl.scala 120:58]
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wire _T_84 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 121:25]
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wire fb_right = _T_83 | _T_84; // @[el2_ifu_ifc_ctrl.scala 120:92]
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wire _T_96 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 127:16]
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reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 140:24]
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wire [3:0] _T_99 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
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wire [3:0] _T_120 = _T_96 ? _T_99 : 4'h0; // @[Mux.scala 27:72]
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wire [3:0] _T_124 = _T_119 | _T_120; // @[Mux.scala 27:72]
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wire fb_right2 = io_ifu_fb_consume2 & _T_82; // @[el2_ifu_ifc_ctrl.scala 123:36]
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wire _T_101 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 128:16]
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wire [3:0] _T_104 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
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wire [3:0] _T_121 = _T_101 ? _T_104 : 4'h0; // @[Mux.scala 27:72]
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wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
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wire _T_89 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 124:56]
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wire _T_90 = ~_T_89; // @[el2_ifu_ifc_ctrl.scala 124:35]
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wire _T_91 = io_ifc_fetch_req_f & _T_90; // @[el2_ifu_ifc_ctrl.scala 124:33]
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wire _T_92 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 124:80]
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wire fb_left = _T_91 & _T_92; // @[el2_ifu_ifc_ctrl.scala 124:78]
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wire _T_106 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 129:16]
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wire [3:0] _T_109 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
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wire [3:0] _T_122 = _T_106 ? _T_109 : 4'h0; // @[Mux.scala 27:72]
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wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
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wire _T_111 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 130:18]
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wire _T_112 = _T_2 & _T_111; // @[el2_ifu_ifc_ctrl.scala 130:16]
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wire _T_113 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 130:30]
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wire _T_114 = _T_112 & _T_113; // @[el2_ifu_ifc_ctrl.scala 130:28]
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wire _T_115 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 130:43]
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wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctrl.scala 130:41]
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wire [3:0] _T_123 = _T_116 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
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wire [3:0] fb_write_ns = _T_126 | _T_123; // @[Mux.scala 27:72]
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wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 138:30]
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wire _T_35 = fb_full_f_ns & _T_34; // @[el2_ifu_ifc_ctrl.scala 95:68]
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wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctrl.scala 95:53]
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wire _T_37 = io_ifc_fetch_req_bf_raw & _T_36; // @[el2_ifu_ifc_ctrl.scala 95:51]
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wire _T_38 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 96:5]
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wire _T_39 = _T_37 & _T_38; // @[el2_ifu_ifc_ctrl.scala 95:114]
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wire _T_40 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 96:18]
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wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctrl.scala 96:16]
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wire _T_42 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 96:39]
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wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 98:37]
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wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 104:35]
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wire _T_58 = io_exu_flush_final & _T_42; // @[el2_ifu_ifc_ctrl.scala 106:36]
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wire leave_idle = _T_58 & idle; // @[el2_ifu_ifc_ctrl.scala 106:67]
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wire _T_65 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 108:55]
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wire _T_73 = _T_65 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 111:34]
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wire _T_76 = state[0] & _T_65; // @[el2_ifu_ifc_ctrl.scala 111:60]
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wire next_state_0 = _T_73 | _T_76; // @[el2_ifu_ifc_ctrl.scala 111:48]
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wire [1:0] _T_77 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
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wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 136:16]
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reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 139:26]
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wire _T_136 = _T_33 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
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wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 143:5]
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wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 142:75]
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wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
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wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 142:60]
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wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
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wire [4:0] _T_146 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
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wire [31:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 150:53]
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reg _T_150; // @[el2_ifu_ifc_ctrl.scala 154:32]
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reg [30:0] _T_152; // @[Reg.scala 27:20]
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assign io_ifc_fetch_addr_f = _T_152; // @[el2_ifu_ifc_ctrl.scala 157:23]
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assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 81:24]
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assign io_ifc_fetch_req_f = _T_150; // @[el2_ifu_ifc_ctrl.scala 154:22]
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assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 142:26]
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assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 150:31]
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assign io_ifc_fetch_req_bf = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 95:23]
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assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
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assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 149:25]
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assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:30]
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assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:24]
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assign io_sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 76:23]
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assign io_sel_btb_addr_bf = _T_9 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 77:23]
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assign io_sel_next_addr_bf = _T_14 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 78:23]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {1{`RANDOM}};
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dma_iccm_stall_any_f = _RAND_0[0:0];
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_RAND_1 = {1{`RANDOM}};
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state = _RAND_1[1:0];
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_RAND_2 = {1{`RANDOM}};
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fb_write_f = _RAND_2[3:0];
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_RAND_3 = {1{`RANDOM}};
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fb_full_f = _RAND_3[0:0];
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_RAND_4 = {1{`RANDOM}};
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_T_150 = _RAND_4[0:0];
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_RAND_5 = {1{`RANDOM}};
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_T_152 = _RAND_5[30:0];
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`endif // RANDOMIZE_REG_INIT
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge clock) begin
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if (reset) begin
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dma_iccm_stall_any_f <= 1'h0;
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end else begin
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dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
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end
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if (reset) begin
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state <= 2'h0;
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end else begin
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state <= _T_77;
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end
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if (reset) begin
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fb_write_f <= 4'h0;
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end else begin
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fb_write_f <= fb_write_ns;
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end
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if (reset) begin
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fb_full_f <= 1'h0;
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end else begin
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fb_full_f <= fb_full_f_ns;
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end
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if (reset) begin
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_T_150 <= 1'h0;
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end else begin
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_T_150 <= io_ifc_fetch_req_bf;
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end
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if (reset) begin
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_T_152 <= 31'h0;
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end else if (fetch_bf_en) begin
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_T_152 <= io_ifc_fetch_addr_bf;
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end
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end
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endmodule
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