35 lines
1.4 KiB
Verilog
35 lines
1.4 KiB
Verilog
module EL2_IC_DATA(
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input clock,
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input reset,
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input io_clk_override,
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input [11:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input io_ic_rd_en,
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input [70:0] io_ic_wr_data_0,
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input [70:0] io_ic_wr_data_1,
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output [63:0] io_ic_rd_data,
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input [70:0] io_ic_debug_wr_data,
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output [70:0] io_ic_debug_rd_data,
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output [1:0] io_ic_parerr,
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output [1:0] io_ic_eccerr,
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input [8:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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input [1:0] io_ic_debug_way,
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input [63:0] io_ic_premux_data,
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input io_ic_sel_premux_data,
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input [1:0] io_ic_rd_hit,
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input io_scan_mode,
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output [8:0] io_test
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);
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wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 206:45]
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wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58]
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wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 206:25]
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
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assign io_test = ic_rw_addr_q[11:3]; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 209:11 el2_ifu_ic_mem.scala 241:11]
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endmodule
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