27 lines
879 B
Plaintext
27 lines
879 B
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit top :
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module reg1 :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip in : UInt<1>, out : UInt<1>}
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reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[GCD.scala 32:20]
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_T <= io.in @[GCD.scala 32:20]
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io.out <= _T @[GCD.scala 32:10]
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module top :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip in : UInt<1>, out : UInt<1>}
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node _T = asUInt(reset) @[GCD.scala 40:26]
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node _T_1 = not(_T) @[GCD.scala 40:19]
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node negReset = asAsyncReset(_T_1) @[GCD.scala 40:34]
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inst r0 of reg1 @[GCD.scala 41:18]
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r0.clock <= clock
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r0.reset <= reset
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io.out <= r0.io.out @[GCD.scala 42:8]
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r0.io.in <= io.in @[GCD.scala 42:8]
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r0.reset <= negReset @[GCD.scala 43:12]
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