1235 lines
76 KiB
Plaintext
1235 lines
76 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_dbg :
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extmodule TEC_RV_ICG :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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extmodule TEC_RV_ICG_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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extmodule TEC_RV_ICG_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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extmodule TEC_RV_ICG_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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extmodule TEC_RV_ICG_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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extmodule TEC_RV_ICG_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 459:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
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clkhdr.EN <= io.en @[el2_lib.scala 462:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
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module el2_dbg :
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input clock : Clock
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input reset : AsyncReset
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output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
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wire dbg_state : UInt<3>
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dbg_state <= UInt<3>("h00")
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wire dbg_state_en : UInt<1>
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dbg_state_en <= UInt<1>("h00")
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wire sb_state : UInt<4>
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sb_state <= UInt<4>("h00")
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wire sb_state_en : UInt<1>
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sb_state_en <= UInt<1>("h00")
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wire dmcontrol_reg : UInt<32>
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dmcontrol_reg <= UInt<32>("h00")
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wire sbaddress0_reg : UInt<32>
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sbaddress0_reg <= UInt<32>("h00")
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wire sbcs_sbbusy_wren : UInt<1>
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sbcs_sbbusy_wren <= UInt<1>("h00")
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wire sbcs_sberror_wren : UInt<1>
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sbcs_sberror_wren <= UInt<1>("h00")
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wire sb_bus_rdata : UInt<64>
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sb_bus_rdata <= UInt<64>("h00")
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wire sbaddress0_reg_wren1 : UInt<1>
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sbaddress0_reg_wren1 <= UInt<1>("h00")
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wire dmstatus_reg : UInt<32>
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dmstatus_reg <= UInt<32>("h00")
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wire dmstatus_havereset : UInt<1>
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dmstatus_havereset <= UInt<1>("h00")
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wire dmstatus_resumeack : UInt<1>
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dmstatus_resumeack <= UInt<1>("h00")
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wire dmstatus_unavail : UInt<1>
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dmstatus_unavail <= UInt<1>("h00")
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wire dmstatus_running : UInt<1>
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dmstatus_running <= UInt<1>("h00")
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wire dmstatus_halted : UInt<1>
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dmstatus_halted <= UInt<1>("h00")
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wire abstractcs_busy_wren : UInt<1>
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abstractcs_busy_wren <= UInt<1>("h00")
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wire abstractcs_busy_din : UInt<1>
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abstractcs_busy_din <= UInt<1>("h00")
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wire sb_bus_cmd_read : UInt<1>
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sb_bus_cmd_read <= UInt<1>("h00")
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wire sb_bus_cmd_write_addr : UInt<1>
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sb_bus_cmd_write_addr <= UInt<1>("h00")
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wire sb_bus_cmd_write_data : UInt<1>
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sb_bus_cmd_write_data <= UInt<1>("h00")
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wire sb_bus_rsp_read : UInt<1>
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sb_bus_rsp_read <= UInt<1>("h00")
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wire sb_bus_rsp_error : UInt<1>
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sb_bus_rsp_error <= UInt<1>("h00")
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wire sb_bus_rsp_write : UInt<1>
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sb_bus_rsp_write <= UInt<1>("h00")
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wire sbcs_sbbusy_din : UInt<1>
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sbcs_sbbusy_din <= UInt<1>("h00")
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wire sbcs_sberror_din : UInt<3>
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sbcs_sberror_din <= UInt<3>("h00")
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wire data1_reg : UInt<32>
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data1_reg <= UInt<32>("h00")
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wire sbcs_reg : UInt<32>
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sbcs_reg <= UInt<32>("h00")
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node _T = neq(dbg_state, UInt<3>("h00")) @[el2_dbg.scala 126:51]
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node _T_1 = or(io.dmi_reg_en, _T) @[el2_dbg.scala 126:38]
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node _T_2 = or(_T_1, dbg_state_en) @[el2_dbg.scala 126:69]
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node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[el2_dbg.scala 126:84]
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node dbg_free_clken = or(_T_3, io.clk_override) @[el2_dbg.scala 126:108]
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node _T_4 = or(io.dmi_reg_en, sb_state_en) @[el2_dbg.scala 127:37]
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node _T_5 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 127:63]
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node _T_6 = or(_T_4, _T_5) @[el2_dbg.scala 127:51]
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node sb_free_clken = or(_T_6, io.clk_override) @[el2_dbg.scala 127:86]
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inst rvclkhdr of rvclkhdr @[el2_lib.scala 468:22]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[el2_lib.scala 469:17]
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rvclkhdr.io.en <= dbg_free_clken @[el2_lib.scala 470:16]
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rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 471:23]
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inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 468:22]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[el2_lib.scala 469:17]
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rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 470:16]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 471:23]
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node _T_7 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:51]
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node _T_8 = or(_T_7, io.scan_mode) @[el2_dbg.scala 130:55]
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node dbg_dm_rst_l = and(io.dbg_rst_l, _T_8) @[el2_dbg.scala 130:35]
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node _T_9 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 131:39]
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node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_dbg.scala 131:25]
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node _T_11 = bits(_T_10, 0, 0) @[el2_dbg.scala 131:50]
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io.dbg_core_rst_l <= _T_11 @[el2_dbg.scala 131:21]
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node _T_12 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 132:36]
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node _T_13 = and(_T_12, io.dmi_reg_en) @[el2_dbg.scala 132:49]
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node _T_14 = and(_T_13, io.dmi_reg_wr_en) @[el2_dbg.scala 132:65]
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node _T_15 = eq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 132:96]
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node sbcs_wren = and(_T_14, _T_15) @[el2_dbg.scala 132:84]
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node _T_16 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 133:60]
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node _T_17 = and(sbcs_wren, _T_16) @[el2_dbg.scala 133:42]
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node _T_18 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 133:79]
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node _T_19 = and(_T_18, io.dmi_reg_en) @[el2_dbg.scala 133:102]
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node _T_20 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 134:23]
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node _T_21 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 134:55]
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node _T_22 = or(_T_20, _T_21) @[el2_dbg.scala 134:36]
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node _T_23 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 134:87]
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node _T_24 = or(_T_22, _T_23) @[el2_dbg.scala 134:68]
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node _T_25 = and(_T_19, _T_24) @[el2_dbg.scala 133:118]
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node sbcs_sbbusyerror_wren = or(_T_17, _T_25) @[el2_dbg.scala 133:66]
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node _T_26 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 136:61]
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node _T_27 = and(sbcs_wren, _T_26) @[el2_dbg.scala 136:43]
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node sbcs_sbbusyerror_din = not(_T_27) @[el2_dbg.scala 136:31]
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node _T_28 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 137:53]
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reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_28, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
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temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_29 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 141:53]
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reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_29, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusy_wren : @[Reg.scala 28:19]
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temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_30 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 145:53]
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node _T_31 = bits(io.dmi_reg_wdata, 20, 20) @[el2_dbg.scala 146:31]
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reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_20 <= _T_31 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_32 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 149:56]
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node _T_33 = bits(io.dmi_reg_wdata, 19, 15) @[el2_dbg.scala 150:31]
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reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_19_15 <= _T_33 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_34 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 153:56]
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node _T_35 = bits(sbcs_sberror_din, 2, 0) @[el2_dbg.scala 154:31]
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reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_34, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sberror_wren : @[Reg.scala 28:19]
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temp_sbcs_14_12 <= _T_35 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_36 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58]
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node _T_37 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58]
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node _T_38 = cat(_T_37, _T_36) @[Cat.scala 29:58]
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node _T_39 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58]
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node _T_40 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58]
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node _T_41 = cat(_T_40, temp_sbcs_22) @[Cat.scala 29:58]
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node _T_42 = cat(_T_41, _T_39) @[Cat.scala 29:58]
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node _T_43 = cat(_T_42, _T_38) @[Cat.scala 29:58]
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sbcs_reg <= _T_43 @[el2_dbg.scala 156:12]
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node _T_44 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 158:33]
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node _T_45 = eq(_T_44, UInt<1>("h01")) @[el2_dbg.scala 158:42]
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node _T_46 = bits(sbaddress0_reg, 0, 0) @[el2_dbg.scala 158:72]
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node _T_47 = and(_T_45, _T_46) @[el2_dbg.scala 158:56]
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node _T_48 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 159:14]
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node _T_49 = eq(_T_48, UInt<2>("h02")) @[el2_dbg.scala 159:23]
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node _T_50 = bits(sbaddress0_reg, 1, 0) @[el2_dbg.scala 159:53]
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node _T_51 = orr(_T_50) @[el2_dbg.scala 159:60]
|
|
node _T_52 = and(_T_49, _T_51) @[el2_dbg.scala 159:37]
|
|
node _T_53 = or(_T_47, _T_52) @[el2_dbg.scala 158:76]
|
|
node _T_54 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 160:14]
|
|
node _T_55 = eq(_T_54, UInt<2>("h03")) @[el2_dbg.scala 160:23]
|
|
node _T_56 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 160:53]
|
|
node _T_57 = orr(_T_56) @[el2_dbg.scala 160:60]
|
|
node _T_58 = and(_T_55, _T_57) @[el2_dbg.scala 160:37]
|
|
node sbcs_unaligned = or(_T_53, _T_58) @[el2_dbg.scala 159:64]
|
|
node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[el2_dbg.scala 162:35]
|
|
node _T_59 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:42]
|
|
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dbg.scala 163:51]
|
|
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_62 = mux(_T_61, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_63 = and(_T_62, UInt<1>("h01")) @[el2_dbg.scala 163:64]
|
|
node _T_64 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:95]
|
|
node _T_65 = eq(_T_64, UInt<1>("h01")) @[el2_dbg.scala 163:104]
|
|
node _T_66 = bits(_T_65, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_67 = mux(_T_66, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_68 = and(_T_67, UInt<2>("h02")) @[el2_dbg.scala 163:117]
|
|
node _T_69 = or(_T_63, _T_68) @[el2_dbg.scala 163:76]
|
|
node _T_70 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:22]
|
|
node _T_71 = eq(_T_70, UInt<2>("h02")) @[el2_dbg.scala 164:31]
|
|
node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_74 = and(_T_73, UInt<3>("h04")) @[el2_dbg.scala 164:44]
|
|
node _T_75 = or(_T_69, _T_74) @[el2_dbg.scala 163:129]
|
|
node _T_76 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:75]
|
|
node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_dbg.scala 164:84]
|
|
node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_80 = and(_T_79, UInt<4>("h08")) @[el2_dbg.scala 164:97]
|
|
node sbaddress0_incr = or(_T_75, _T_80) @[el2_dbg.scala 164:56]
|
|
node _T_81 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 166:41]
|
|
node _T_82 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 166:79]
|
|
node sbdata0_reg_wren0 = and(_T_81, _T_82) @[el2_dbg.scala 166:60]
|
|
node _T_83 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 167:37]
|
|
node _T_84 = and(_T_83, sb_state_en) @[el2_dbg.scala 167:60]
|
|
node _T_85 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 167:76]
|
|
node sbdata0_reg_wren1 = and(_T_84, _T_85) @[el2_dbg.scala 167:74]
|
|
node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[el2_dbg.scala 168:44]
|
|
node _T_86 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 169:41]
|
|
node _T_87 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 169:79]
|
|
node sbdata1_reg_wren0 = and(_T_86, _T_87) @[el2_dbg.scala 169:60]
|
|
node _T_88 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 170:37]
|
|
node _T_89 = and(_T_88, sb_state_en) @[el2_dbg.scala 170:60]
|
|
node _T_90 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 170:76]
|
|
node sbdata1_reg_wren1 = and(_T_89, _T_90) @[el2_dbg.scala 170:74]
|
|
node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[el2_dbg.scala 171:44]
|
|
node _T_91 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_93 = and(_T_92, io.dmi_reg_wdata) @[el2_dbg.scala 172:49]
|
|
node _T_94 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_96 = bits(sb_bus_rdata, 31, 0) @[el2_dbg.scala 173:47]
|
|
node _T_97 = and(_T_95, _T_96) @[el2_dbg.scala 173:33]
|
|
node sbdata0_din = or(_T_93, _T_97) @[el2_dbg.scala 172:68]
|
|
node _T_98 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_100 = and(_T_99, io.dmi_reg_wdata) @[el2_dbg.scala 175:49]
|
|
node _T_101 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_103 = bits(sb_bus_rdata, 63, 32) @[el2_dbg.scala 176:47]
|
|
node _T_104 = and(_T_102, _T_103) @[el2_dbg.scala 176:33]
|
|
node sbdata1_din = or(_T_100, _T_104) @[el2_dbg.scala 175:68]
|
|
node _T_105 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 178:31]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 493:23]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= _T_105
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 495:18]
|
|
rvclkhdr_2.io.en <= sbdata0_reg_wren @[el2_lib.scala 496:17]
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
|
|
reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_105, UInt<1>("h00"))) @[el2_lib.scala 499:16]
|
|
sbdata0_reg <= sbdata0_din @[el2_lib.scala 499:16]
|
|
node _T_106 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 182:31]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 493:23]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= _T_106
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 495:18]
|
|
rvclkhdr_3.io.en <= sbdata1_reg_wren @[el2_lib.scala 496:17]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
|
|
reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_106, UInt<1>("h00"))) @[el2_lib.scala 499:16]
|
|
sbdata1_reg <= sbdata1_din @[el2_lib.scala 499:16]
|
|
node _T_107 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 186:44]
|
|
node _T_108 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 186:82]
|
|
node sbaddress0_reg_wren0 = and(_T_107, _T_108) @[el2_dbg.scala 186:63]
|
|
node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[el2_dbg.scala 187:50]
|
|
node _T_109 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_111 = and(_T_110, io.dmi_reg_wdata) @[el2_dbg.scala 188:59]
|
|
node _T_112 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_114 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
|
|
node _T_115 = add(sbaddress0_reg, _T_114) @[el2_dbg.scala 189:54]
|
|
node _T_116 = tail(_T_115, 1) @[el2_dbg.scala 189:54]
|
|
node _T_117 = and(_T_113, _T_116) @[el2_dbg.scala 189:36]
|
|
node sbaddress0_reg_din = or(_T_111, _T_117) @[el2_dbg.scala 188:78]
|
|
node _T_118 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 190:31]
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 493:23]
|
|
rvclkhdr_4.clock <= clock
|
|
rvclkhdr_4.reset <= _T_118
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 495:18]
|
|
rvclkhdr_4.io.en <= sbaddress0_reg_wren @[el2_lib.scala 496:17]
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
|
|
reg _T_119 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_118, UInt<1>("h00"))) @[el2_lib.scala 499:16]
|
|
_T_119 <= sbaddress0_reg_din @[el2_lib.scala 499:16]
|
|
sbaddress0_reg <= _T_119 @[el2_dbg.scala 190:18]
|
|
node _T_120 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 194:43]
|
|
node _T_121 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 194:81]
|
|
node _T_122 = and(_T_120, _T_121) @[el2_dbg.scala 194:62]
|
|
node _T_123 = bits(sbcs_reg, 20, 20) @[el2_dbg.scala 194:104]
|
|
node sbreadonaddr_access = and(_T_122, _T_123) @[el2_dbg.scala 194:94]
|
|
node _T_124 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[el2_dbg.scala 195:45]
|
|
node _T_125 = and(io.dmi_reg_en, _T_124) @[el2_dbg.scala 195:43]
|
|
node _T_126 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 195:82]
|
|
node _T_127 = and(_T_125, _T_126) @[el2_dbg.scala 195:63]
|
|
node _T_128 = bits(sbcs_reg, 15, 15) @[el2_dbg.scala 195:105]
|
|
node sbreadondata_access = and(_T_127, _T_128) @[el2_dbg.scala 195:95]
|
|
node _T_129 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 196:40]
|
|
node _T_130 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 196:78]
|
|
node sbdata0wr_access = and(_T_129, _T_130) @[el2_dbg.scala 196:59]
|
|
node _T_131 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 197:41]
|
|
node _T_132 = and(_T_131, io.dmi_reg_en) @[el2_dbg.scala 197:54]
|
|
node dmcontrol_wren = and(_T_132, io.dmi_reg_wr_en) @[el2_dbg.scala 197:70]
|
|
node _T_133 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 198:49]
|
|
node _T_134 = bits(io.dmi_reg_wdata, 31, 30) @[el2_dbg.scala 200:27]
|
|
node _T_135 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 200:53]
|
|
node _T_136 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 200:75]
|
|
node _T_137 = cat(_T_134, _T_135) @[Cat.scala 29:58]
|
|
node _T_138 = cat(_T_137, _T_136) @[Cat.scala 29:58]
|
|
reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_133, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp <= _T_138 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_139 = bits(io.dmi_reg_wdata, 0, 0) @[el2_dbg.scala 205:31]
|
|
reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp_0 <= _T_139 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_140 = bits(dm_temp, 3, 2) @[el2_dbg.scala 208:25]
|
|
node _T_141 = bits(dm_temp, 1, 1) @[el2_dbg.scala 208:45]
|
|
node _T_142 = bits(dm_temp, 0, 0) @[el2_dbg.scala 208:68]
|
|
node _T_143 = cat(UInt<26>("h00"), _T_142) @[Cat.scala 29:58]
|
|
node _T_144 = cat(_T_143, dm_temp_0) @[Cat.scala 29:58]
|
|
node _T_145 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_146 = cat(_T_145, _T_141) @[Cat.scala 29:58]
|
|
node temp = cat(_T_146, _T_144) @[Cat.scala 29:58]
|
|
dmcontrol_reg <= temp @[el2_dbg.scala 209:17]
|
|
node _T_147 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 211:58]
|
|
reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_147, UInt<1>("h00"))) @[el2_dbg.scala 212:12]
|
|
dmcontrol_wren_Q <= dmcontrol_wren @[el2_dbg.scala 212:12]
|
|
node _T_148 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_149 = mux(_T_148, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_150 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_151 = mux(_T_150, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_152 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_153 = mux(_T_152, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_154 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_155 = mux(_T_154, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_156 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_157 = mux(_T_156, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_158 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
|
|
node _T_159 = cat(_T_155, _T_157) @[Cat.scala 29:58]
|
|
node _T_160 = cat(_T_159, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_161 = cat(_T_160, _T_158) @[Cat.scala 29:58]
|
|
node _T_162 = cat(UInt<2>("h00"), _T_153) @[Cat.scala 29:58]
|
|
node _T_163 = cat(UInt<12>("h00"), _T_149) @[Cat.scala 29:58]
|
|
node _T_164 = cat(_T_163, _T_151) @[Cat.scala 29:58]
|
|
node _T_165 = cat(_T_164, _T_162) @[Cat.scala 29:58]
|
|
node _T_166 = cat(_T_165, _T_161) @[Cat.scala 29:58]
|
|
dmstatus_reg <= _T_166 @[el2_dbg.scala 215:16]
|
|
node _T_167 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 217:44]
|
|
node _T_168 = and(_T_167, io.dec_tlu_resume_ack) @[el2_dbg.scala 217:66]
|
|
node _T_169 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 217:127]
|
|
node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dbg.scala 217:113]
|
|
node _T_171 = and(dmstatus_resumeack, _T_170) @[el2_dbg.scala 217:111]
|
|
node dmstatus_resumeack_wren = or(_T_168, _T_171) @[el2_dbg.scala 217:90]
|
|
node _T_172 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 218:43]
|
|
node dmstatus_resumeack_din = and(_T_172, io.dec_tlu_resume_ack) @[el2_dbg.scala 218:65]
|
|
node _T_173 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 219:50]
|
|
node _T_174 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 219:81]
|
|
node _T_175 = and(_T_173, _T_174) @[el2_dbg.scala 219:63]
|
|
node _T_176 = and(_T_175, io.dmi_reg_en) @[el2_dbg.scala 219:85]
|
|
node dmstatus_havereset_wren = and(_T_176, io.dmi_reg_wr_en) @[el2_dbg.scala 219:101]
|
|
node _T_177 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 220:49]
|
|
node _T_178 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 220:80]
|
|
node _T_179 = and(_T_177, _T_178) @[el2_dbg.scala 220:62]
|
|
node _T_180 = and(_T_179, io.dmi_reg_en) @[el2_dbg.scala 220:85]
|
|
node dmstatus_havereset_rst = and(_T_180, io.dmi_reg_wr_en) @[el2_dbg.scala 220:101]
|
|
node temp_rst = asUInt(reset) @[el2_dbg.scala 221:30]
|
|
node _T_181 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 222:37]
|
|
node _T_182 = eq(temp_rst, UInt<1>("h00")) @[el2_dbg.scala 222:43]
|
|
node _T_183 = or(_T_181, _T_182) @[el2_dbg.scala 222:41]
|
|
node _T_184 = bits(_T_183, 0, 0) @[el2_dbg.scala 222:62]
|
|
dmstatus_unavail <= _T_184 @[el2_dbg.scala 222:20]
|
|
node _T_185 = or(dmstatus_unavail, dmstatus_halted) @[el2_dbg.scala 223:42]
|
|
node _T_186 = not(_T_185) @[el2_dbg.scala 223:23]
|
|
dmstatus_running <= _T_186 @[el2_dbg.scala 223:20]
|
|
node _T_187 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 224:57]
|
|
reg _T_188 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_187, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmstatus_resumeack_wren : @[Reg.scala 28:19]
|
|
_T_188 <= dmstatus_resumeack_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dmstatus_resumeack <= _T_188 @[el2_dbg.scala 224:22]
|
|
node _T_189 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 228:54]
|
|
node _T_190 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[el2_dbg.scala 229:37]
|
|
node _T_191 = and(io.dec_tlu_dbg_halted, _T_190) @[el2_dbg.scala 229:35]
|
|
reg _T_192 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_189, UInt<1>("h00"))) @[el2_dbg.scala 229:12]
|
|
_T_192 <= _T_191 @[el2_dbg.scala 229:12]
|
|
dmstatus_halted <= _T_192 @[el2_dbg.scala 228:19]
|
|
node _T_193 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 232:57]
|
|
node _T_194 = not(dmstatus_havereset_rst) @[el2_dbg.scala 233:15]
|
|
reg _T_195 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_193, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmstatus_havereset_wren : @[Reg.scala 28:19]
|
|
_T_195 <= _T_194 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dmstatus_havereset <= _T_195 @[el2_dbg.scala 232:22]
|
|
node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
|
|
wire abstractcs_reg : UInt<32>
|
|
abstractcs_reg <= UInt<32>("h02")
|
|
node _T_196 = bits(abstractcs_reg, 12, 12) @[el2_dbg.scala 239:45]
|
|
node _T_197 = and(_T_196, io.dmi_reg_en) @[el2_dbg.scala 239:50]
|
|
node _T_198 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 239:106]
|
|
node _T_199 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 239:138]
|
|
node _T_200 = or(_T_198, _T_199) @[el2_dbg.scala 239:119]
|
|
node _T_201 = and(io.dmi_reg_wr_en, _T_200) @[el2_dbg.scala 239:86]
|
|
node _T_202 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 239:171]
|
|
node _T_203 = or(_T_201, _T_202) @[el2_dbg.scala 239:152]
|
|
node abstractcs_error_sel0 = and(_T_197, _T_203) @[el2_dbg.scala 239:66]
|
|
node _T_204 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 240:45]
|
|
node _T_205 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 240:83]
|
|
node _T_206 = and(_T_204, _T_205) @[el2_dbg.scala 240:64]
|
|
node _T_207 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:117]
|
|
node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dbg.scala 240:126]
|
|
node _T_209 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:154]
|
|
node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_dbg.scala 240:163]
|
|
node _T_211 = or(_T_208, _T_210) @[el2_dbg.scala 240:135]
|
|
node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dbg.scala 240:98]
|
|
node abstractcs_error_sel1 = and(_T_206, _T_212) @[el2_dbg.scala 240:96]
|
|
node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[el2_dbg.scala 241:52]
|
|
node _T_213 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 242:45]
|
|
node _T_214 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 242:83]
|
|
node _T_215 = and(_T_213, _T_214) @[el2_dbg.scala 242:64]
|
|
node _T_216 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 242:111]
|
|
node _T_217 = eq(_T_216, UInt<1>("h00")) @[el2_dbg.scala 242:98]
|
|
node abstractcs_error_sel3 = and(_T_215, _T_217) @[el2_dbg.scala 242:96]
|
|
node _T_218 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 243:48]
|
|
node _T_219 = and(_T_218, io.dmi_reg_en) @[el2_dbg.scala 243:61]
|
|
node _T_220 = and(_T_219, io.dmi_reg_wr_en) @[el2_dbg.scala 243:77]
|
|
node _T_221 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 244:23]
|
|
node _T_222 = neq(_T_221, UInt<2>("h02")) @[el2_dbg.scala 244:32]
|
|
node _T_223 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 244:66]
|
|
node _T_224 = eq(_T_223, UInt<2>("h02")) @[el2_dbg.scala 244:75]
|
|
node _T_225 = bits(data1_reg, 1, 0) @[el2_dbg.scala 244:99]
|
|
node _T_226 = orr(_T_225) @[el2_dbg.scala 244:106]
|
|
node _T_227 = and(_T_224, _T_226) @[el2_dbg.scala 244:87]
|
|
node _T_228 = or(_T_222, _T_227) @[el2_dbg.scala 244:46]
|
|
node abstractcs_error_sel4 = and(_T_220, _T_228) @[el2_dbg.scala 243:96]
|
|
node _T_229 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 246:48]
|
|
node _T_230 = and(_T_229, io.dmi_reg_en) @[el2_dbg.scala 246:61]
|
|
node abstractcs_error_sel5 = and(_T_230, io.dmi_reg_wr_en) @[el2_dbg.scala 246:77]
|
|
node _T_231 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[el2_dbg.scala 247:54]
|
|
node _T_232 = or(_T_231, abstractcs_error_sel2) @[el2_dbg.scala 247:78]
|
|
node _T_233 = or(_T_232, abstractcs_error_sel3) @[el2_dbg.scala 247:102]
|
|
node _T_234 = or(_T_233, abstractcs_error_sel4) @[el2_dbg.scala 247:126]
|
|
node abstractcs_error_selor = or(_T_234, abstractcs_error_sel5) @[el2_dbg.scala 247:150]
|
|
node _T_235 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_236 = mux(_T_235, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_237 = and(_T_236, UInt<1>("h01")) @[el2_dbg.scala 248:62]
|
|
node _T_238 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_239 = mux(_T_238, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_240 = and(_T_239, UInt<2>("h02")) @[el2_dbg.scala 249:37]
|
|
node _T_241 = or(_T_237, _T_240) @[el2_dbg.scala 248:74]
|
|
node _T_242 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_243 = mux(_T_242, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_244 = and(_T_243, UInt<2>("h03")) @[el2_dbg.scala 250:37]
|
|
node _T_245 = or(_T_241, _T_244) @[el2_dbg.scala 249:49]
|
|
node _T_246 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_247 = mux(_T_246, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_248 = and(_T_247, UInt<3>("h04")) @[el2_dbg.scala 251:37]
|
|
node _T_249 = or(_T_245, _T_248) @[el2_dbg.scala 250:49]
|
|
node _T_250 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_251 = mux(_T_250, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_252 = and(_T_251, UInt<3>("h07")) @[el2_dbg.scala 252:37]
|
|
node _T_253 = or(_T_249, _T_252) @[el2_dbg.scala 251:49]
|
|
node _T_254 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_255 = mux(_T_254, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_256 = bits(io.dmi_reg_wdata, 10, 8) @[el2_dbg.scala 253:57]
|
|
node _T_257 = not(_T_256) @[el2_dbg.scala 253:40]
|
|
node _T_258 = and(_T_255, _T_257) @[el2_dbg.scala 253:37]
|
|
node _T_259 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 253:91]
|
|
node _T_260 = and(_T_258, _T_259) @[el2_dbg.scala 253:75]
|
|
node _T_261 = or(_T_253, _T_260) @[el2_dbg.scala 252:49]
|
|
node _T_262 = not(abstractcs_error_selor) @[el2_dbg.scala 254:15]
|
|
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_264 = mux(_T_263, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_265 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 254:66]
|
|
node _T_266 = and(_T_264, _T_265) @[el2_dbg.scala 254:50]
|
|
node abstractcs_error_din = or(_T_261, _T_266) @[el2_dbg.scala 253:100]
|
|
node _T_267 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 256:53]
|
|
reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_267, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when abstractcs_busy_wren : @[Reg.scala 28:19]
|
|
abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_268 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 260:55]
|
|
node _T_269 = bits(abstractcs_error_din, 2, 0) @[el2_dbg.scala 261:33]
|
|
reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_268, UInt<1>("h00"))) @[el2_dbg.scala 261:12]
|
|
abs_temp_10_8 <= _T_269 @[el2_dbg.scala 261:12]
|
|
node _T_270 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
|
|
node _T_271 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
|
|
node _T_272 = cat(_T_271, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_273 = cat(_T_272, _T_270) @[Cat.scala 29:58]
|
|
abstractcs_reg <= _T_273 @[el2_dbg.scala 264:18]
|
|
node _T_274 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 266:39]
|
|
node _T_275 = and(_T_274, io.dmi_reg_en) @[el2_dbg.scala 266:52]
|
|
node _T_276 = and(_T_275, io.dmi_reg_wr_en) @[el2_dbg.scala 266:68]
|
|
node _T_277 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 266:100]
|
|
node command_wren = and(_T_276, _T_277) @[el2_dbg.scala 266:87]
|
|
node _T_278 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 267:41]
|
|
node _T_279 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 267:77]
|
|
node _T_280 = bits(io.dmi_reg_wdata, 16, 0) @[el2_dbg.scala 267:113]
|
|
node _T_281 = cat(UInt<3>("h00"), _T_280) @[Cat.scala 29:58]
|
|
node _T_282 = cat(_T_278, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_283 = cat(_T_282, _T_279) @[Cat.scala 29:58]
|
|
node command_din = cat(_T_283, _T_281) @[Cat.scala 29:58]
|
|
node _T_284 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 268:31]
|
|
reg command_reg : UInt, clock with : (reset => (_T_284, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when command_wren : @[Reg.scala 28:19]
|
|
command_reg <= command_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_285 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 272:39]
|
|
node _T_286 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 272:77]
|
|
node _T_287 = and(_T_285, _T_286) @[el2_dbg.scala 272:58]
|
|
node _T_288 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 272:102]
|
|
node data0_reg_wren0 = and(_T_287, _T_288) @[el2_dbg.scala 272:89]
|
|
node _T_289 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 273:59]
|
|
node _T_290 = and(io.core_dbg_cmd_done, _T_289) @[el2_dbg.scala 273:46]
|
|
node _T_291 = bits(command_reg, 16, 16) @[el2_dbg.scala 273:95]
|
|
node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_dbg.scala 273:83]
|
|
node data0_reg_wren1 = and(_T_290, _T_292) @[el2_dbg.scala 273:81]
|
|
node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[el2_dbg.scala 275:40]
|
|
node _T_293 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_294 = mux(_T_293, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_295 = and(_T_294, io.dmi_reg_wdata) @[el2_dbg.scala 276:45]
|
|
node _T_296 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_297 = mux(_T_296, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_298 = and(_T_297, io.core_dbg_rddata) @[el2_dbg.scala 276:92]
|
|
node data0_din = or(_T_295, _T_298) @[el2_dbg.scala 276:64]
|
|
node _T_299 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 277:29]
|
|
reg data0_reg : UInt, clock with : (reset => (_T_299, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when data0_reg_wren : @[Reg.scala 28:19]
|
|
data0_reg <= data0_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_300 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 281:39]
|
|
node _T_301 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 281:77]
|
|
node _T_302 = and(_T_300, _T_301) @[el2_dbg.scala 281:58]
|
|
node _T_303 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 281:102]
|
|
node data1_reg_wren = and(_T_302, _T_303) @[el2_dbg.scala 281:89]
|
|
node _T_304 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_305 = mux(_T_304, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node data1_din = and(_T_305, io.dmi_reg_wdata) @[el2_dbg.scala 282:44]
|
|
node _T_306 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 283:26]
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 493:23]
|
|
rvclkhdr_5.clock <= clock
|
|
rvclkhdr_5.reset <= _T_306
|
|
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 495:18]
|
|
rvclkhdr_5.io.en <= data1_reg_wren @[el2_lib.scala 496:17]
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
|
|
reg _T_307 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_306, UInt<1>("h00"))) @[el2_lib.scala 499:16]
|
|
_T_307 <= data1_din @[el2_lib.scala 499:16]
|
|
data1_reg <= _T_307 @[el2_dbg.scala 283:13]
|
|
wire dbg_nxtstate : UInt<3>
|
|
dbg_nxtstate <= UInt<3>("h00")
|
|
dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 288:16]
|
|
dbg_state_en <= UInt<1>("h00") @[el2_dbg.scala 289:16]
|
|
abstractcs_busy_wren <= UInt<1>("h00") @[el2_dbg.scala 290:24]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 291:23]
|
|
io.dbg_halt_req <= UInt<1>("h00") @[el2_dbg.scala 292:19]
|
|
io.dbg_resume_req <= UInt<1>("h00") @[el2_dbg.scala 293:21]
|
|
node _T_308 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_308 : @[Conditional.scala 40:58]
|
|
node _T_309 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 296:39]
|
|
node _T_310 = or(_T_309, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 296:43]
|
|
node _T_311 = mux(_T_310, UInt<3>("h02"), UInt<3>("h01")) @[el2_dbg.scala 296:26]
|
|
dbg_nxtstate <= _T_311 @[el2_dbg.scala 296:20]
|
|
node _T_312 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 297:38]
|
|
node _T_313 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[el2_dbg.scala 297:45]
|
|
node _T_314 = and(_T_312, _T_313) @[el2_dbg.scala 297:43]
|
|
node _T_315 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 297:83]
|
|
node _T_316 = or(_T_314, _T_315) @[el2_dbg.scala 297:69]
|
|
node _T_317 = or(_T_316, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 297:87]
|
|
node _T_318 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 297:133]
|
|
node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_dbg.scala 297:119]
|
|
node _T_320 = and(_T_317, _T_319) @[el2_dbg.scala 297:117]
|
|
dbg_state_en <= _T_320 @[el2_dbg.scala 297:20]
|
|
node _T_321 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 298:40]
|
|
node _T_322 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 298:61]
|
|
node _T_323 = eq(_T_322, UInt<1>("h00")) @[el2_dbg.scala 298:47]
|
|
node _T_324 = and(_T_321, _T_323) @[el2_dbg.scala 298:45]
|
|
node _T_325 = bits(_T_324, 0, 0) @[el2_dbg.scala 298:72]
|
|
io.dbg_halt_req <= _T_325 @[el2_dbg.scala 298:23]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_326 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_326 : @[Conditional.scala 39:67]
|
|
node _T_327 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 301:40]
|
|
node _T_328 = mux(_T_327, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 301:26]
|
|
dbg_nxtstate <= _T_328 @[el2_dbg.scala 301:20]
|
|
node _T_329 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 302:35]
|
|
node _T_330 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 302:54]
|
|
node _T_331 = or(_T_329, _T_330) @[el2_dbg.scala 302:39]
|
|
dbg_state_en <= _T_331 @[el2_dbg.scala 302:20]
|
|
node _T_332 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 303:59]
|
|
node _T_333 = and(dmcontrol_wren_Q, _T_332) @[el2_dbg.scala 303:44]
|
|
node _T_334 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 303:81]
|
|
node _T_335 = not(_T_334) @[el2_dbg.scala 303:67]
|
|
node _T_336 = and(_T_333, _T_335) @[el2_dbg.scala 303:64]
|
|
node _T_337 = bits(_T_336, 0, 0) @[el2_dbg.scala 303:102]
|
|
io.dbg_halt_req <= _T_337 @[el2_dbg.scala 303:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_338 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_338 : @[Conditional.scala 39:67]
|
|
node _T_339 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 306:39]
|
|
node _T_340 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 306:59]
|
|
node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_dbg.scala 306:45]
|
|
node _T_342 = and(_T_339, _T_341) @[el2_dbg.scala 306:43]
|
|
node _T_343 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 307:26]
|
|
node _T_344 = bits(dmcontrol_reg, 3, 3) @[el2_dbg.scala 307:47]
|
|
node _T_345 = eq(_T_344, UInt<1>("h00")) @[el2_dbg.scala 307:33]
|
|
node _T_346 = and(_T_343, _T_345) @[el2_dbg.scala 307:31]
|
|
node _T_347 = mux(_T_346, UInt<3>("h06"), UInt<3>("h03")) @[el2_dbg.scala 307:12]
|
|
node _T_348 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 308:26]
|
|
node _T_349 = mux(_T_348, UInt<3>("h01"), UInt<3>("h00")) @[el2_dbg.scala 308:12]
|
|
node _T_350 = mux(_T_342, _T_347, _T_349) @[el2_dbg.scala 306:26]
|
|
dbg_nxtstate <= _T_350 @[el2_dbg.scala 306:20]
|
|
node _T_351 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 309:35]
|
|
node _T_352 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 309:54]
|
|
node _T_353 = and(_T_351, _T_352) @[el2_dbg.scala 309:39]
|
|
node _T_354 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 309:75]
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dbg.scala 309:61]
|
|
node _T_356 = and(_T_353, _T_355) @[el2_dbg.scala 309:59]
|
|
node _T_357 = and(_T_356, dmcontrol_wren_Q) @[el2_dbg.scala 309:80]
|
|
node _T_358 = or(_T_357, command_wren) @[el2_dbg.scala 309:99]
|
|
node _T_359 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 310:22]
|
|
node _T_360 = or(_T_358, _T_359) @[el2_dbg.scala 309:114]
|
|
node _T_361 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 310:42]
|
|
node _T_362 = or(_T_361, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 310:46]
|
|
node _T_363 = eq(_T_362, UInt<1>("h00")) @[el2_dbg.scala 310:28]
|
|
node _T_364 = or(_T_360, _T_363) @[el2_dbg.scala 310:26]
|
|
dbg_state_en <= _T_364 @[el2_dbg.scala 309:20]
|
|
node _T_365 = eq(dbg_nxtstate, UInt<3>("h03")) @[el2_dbg.scala 311:60]
|
|
node _T_366 = and(dbg_state_en, _T_365) @[el2_dbg.scala 311:44]
|
|
abstractcs_busy_wren <= _T_366 @[el2_dbg.scala 311:28]
|
|
abstractcs_busy_din <= UInt<1>("h01") @[el2_dbg.scala 312:27]
|
|
node _T_367 = eq(dbg_nxtstate, UInt<3>("h06")) @[el2_dbg.scala 313:58]
|
|
node _T_368 = and(dbg_state_en, _T_367) @[el2_dbg.scala 313:42]
|
|
node _T_369 = bits(_T_368, 0, 0) @[el2_dbg.scala 313:87]
|
|
io.dbg_resume_req <= _T_369 @[el2_dbg.scala 313:25]
|
|
node _T_370 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 314:59]
|
|
node _T_371 = and(dmcontrol_wren_Q, _T_370) @[el2_dbg.scala 314:44]
|
|
node _T_372 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 314:81]
|
|
node _T_373 = not(_T_372) @[el2_dbg.scala 314:67]
|
|
node _T_374 = and(_T_371, _T_373) @[el2_dbg.scala 314:64]
|
|
node _T_375 = bits(_T_374, 0, 0) @[el2_dbg.scala 314:102]
|
|
io.dbg_halt_req <= _T_375 @[el2_dbg.scala 314:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_376 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_376 : @[Conditional.scala 39:67]
|
|
node _T_377 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 317:40]
|
|
node _T_378 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 317:77]
|
|
node _T_379 = orr(_T_378) @[el2_dbg.scala 317:85]
|
|
node _T_380 = mux(_T_379, UInt<3>("h05"), UInt<3>("h04")) @[el2_dbg.scala 317:62]
|
|
node _T_381 = mux(_T_377, UInt<3>("h00"), _T_380) @[el2_dbg.scala 317:26]
|
|
dbg_nxtstate <= _T_381 @[el2_dbg.scala 317:20]
|
|
node _T_382 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 318:56]
|
|
node _T_383 = orr(_T_382) @[el2_dbg.scala 318:64]
|
|
node _T_384 = or(io.dbg_cmd_valid, _T_383) @[el2_dbg.scala 318:40]
|
|
node _T_385 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 318:83]
|
|
node _T_386 = or(_T_384, _T_385) @[el2_dbg.scala 318:68]
|
|
dbg_state_en <= _T_386 @[el2_dbg.scala 318:20]
|
|
node _T_387 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 319:59]
|
|
node _T_388 = and(dmcontrol_wren_Q, _T_387) @[el2_dbg.scala 319:44]
|
|
node _T_389 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 319:81]
|
|
node _T_390 = not(_T_389) @[el2_dbg.scala 319:67]
|
|
node _T_391 = and(_T_388, _T_390) @[el2_dbg.scala 319:64]
|
|
node _T_392 = bits(_T_391, 0, 0) @[el2_dbg.scala 319:102]
|
|
io.dbg_halt_req <= _T_392 @[el2_dbg.scala 319:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_393 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_393 : @[Conditional.scala 39:67]
|
|
node _T_394 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 322:40]
|
|
node _T_395 = mux(_T_394, UInt<3>("h00"), UInt<3>("h05")) @[el2_dbg.scala 322:26]
|
|
dbg_nxtstate <= _T_395 @[el2_dbg.scala 322:20]
|
|
node _T_396 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 323:59]
|
|
node _T_397 = or(io.core_dbg_cmd_done, _T_396) @[el2_dbg.scala 323:44]
|
|
dbg_state_en <= _T_397 @[el2_dbg.scala 323:20]
|
|
node _T_398 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 324:59]
|
|
node _T_399 = and(dmcontrol_wren_Q, _T_398) @[el2_dbg.scala 324:44]
|
|
node _T_400 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 324:81]
|
|
node _T_401 = not(_T_400) @[el2_dbg.scala 324:67]
|
|
node _T_402 = and(_T_399, _T_401) @[el2_dbg.scala 324:64]
|
|
node _T_403 = bits(_T_402, 0, 0) @[el2_dbg.scala 324:102]
|
|
io.dbg_halt_req <= _T_403 @[el2_dbg.scala 324:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_404 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_404 : @[Conditional.scala 39:67]
|
|
node _T_405 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 327:40]
|
|
node _T_406 = mux(_T_405, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 327:26]
|
|
dbg_nxtstate <= _T_406 @[el2_dbg.scala 327:20]
|
|
dbg_state_en <= UInt<1>("h01") @[el2_dbg.scala 328:20]
|
|
abstractcs_busy_wren <= dbg_state_en @[el2_dbg.scala 329:28]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 330:27]
|
|
node _T_407 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 331:59]
|
|
node _T_408 = and(dmcontrol_wren_Q, _T_407) @[el2_dbg.scala 331:44]
|
|
node _T_409 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 331:81]
|
|
node _T_410 = not(_T_409) @[el2_dbg.scala 331:67]
|
|
node _T_411 = and(_T_408, _T_410) @[el2_dbg.scala 331:64]
|
|
node _T_412 = bits(_T_411, 0, 0) @[el2_dbg.scala 331:102]
|
|
io.dbg_halt_req <= _T_412 @[el2_dbg.scala 331:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_413 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_413 : @[Conditional.scala 39:67]
|
|
dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 334:20]
|
|
node _T_414 = bits(dmstatus_reg, 17, 17) @[el2_dbg.scala 335:35]
|
|
node _T_415 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 335:55]
|
|
node _T_416 = or(_T_414, _T_415) @[el2_dbg.scala 335:40]
|
|
dbg_state_en <= _T_416 @[el2_dbg.scala 335:20]
|
|
node _T_417 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 336:59]
|
|
node _T_418 = and(dmcontrol_wren_Q, _T_417) @[el2_dbg.scala 336:44]
|
|
node _T_419 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 336:81]
|
|
node _T_420 = not(_T_419) @[el2_dbg.scala 336:67]
|
|
node _T_421 = and(_T_418, _T_420) @[el2_dbg.scala 336:64]
|
|
node _T_422 = bits(_T_421, 0, 0) @[el2_dbg.scala 336:102]
|
|
io.dbg_halt_req <= _T_422 @[el2_dbg.scala 336:23]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_423 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 339:52]
|
|
node _T_424 = bits(_T_423, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_426 = and(_T_425, data0_reg) @[el2_dbg.scala 339:71]
|
|
node _T_427 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 339:110]
|
|
node _T_428 = bits(_T_427, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_429 = mux(_T_428, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_430 = and(_T_429, data1_reg) @[el2_dbg.scala 339:122]
|
|
node _T_431 = or(_T_426, _T_430) @[el2_dbg.scala 339:83]
|
|
node _T_432 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 340:30]
|
|
node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_435 = and(_T_434, dmcontrol_reg) @[el2_dbg.scala 340:43]
|
|
node _T_436 = or(_T_431, _T_435) @[el2_dbg.scala 339:134]
|
|
node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[el2_dbg.scala 340:86]
|
|
node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_440 = and(_T_439, dmstatus_reg) @[el2_dbg.scala 340:99]
|
|
node _T_441 = or(_T_436, _T_440) @[el2_dbg.scala 340:59]
|
|
node _T_442 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 341:30]
|
|
node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_445 = and(_T_444, abstractcs_reg) @[el2_dbg.scala 341:43]
|
|
node _T_446 = or(_T_441, _T_445) @[el2_dbg.scala 340:114]
|
|
node _T_447 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 341:87]
|
|
node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_450 = and(_T_449, command_reg) @[el2_dbg.scala 341:100]
|
|
node _T_451 = or(_T_446, _T_450) @[el2_dbg.scala 341:60]
|
|
node _T_452 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[el2_dbg.scala 342:30]
|
|
node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_455 = and(_T_454, haltsum0_reg) @[el2_dbg.scala 342:43]
|
|
node _T_456 = or(_T_451, _T_455) @[el2_dbg.scala 341:114]
|
|
node _T_457 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 342:85]
|
|
node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_460 = and(_T_459, sbcs_reg) @[el2_dbg.scala 342:98]
|
|
node _T_461 = or(_T_456, _T_460) @[el2_dbg.scala 342:58]
|
|
node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 343:30]
|
|
node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_465 = and(_T_464, sbaddress0_reg) @[el2_dbg.scala 343:43]
|
|
node _T_466 = or(_T_461, _T_465) @[el2_dbg.scala 342:109]
|
|
node _T_467 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 343:87]
|
|
node _T_468 = bits(_T_467, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_470 = and(_T_469, sbdata0_reg) @[el2_dbg.scala 343:100]
|
|
node _T_471 = or(_T_466, _T_470) @[el2_dbg.scala 343:60]
|
|
node _T_472 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 344:30]
|
|
node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_474 = mux(_T_473, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_475 = and(_T_474, sbdata1_reg) @[el2_dbg.scala 344:43]
|
|
node dmi_reg_rdata_din = or(_T_471, _T_475) @[el2_dbg.scala 343:114]
|
|
node _T_476 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 346:48]
|
|
node _T_477 = and(_T_476, temp_rst) @[el2_dbg.scala 346:62]
|
|
reg _T_478 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_477, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dbg_state_en : @[Reg.scala 28:19]
|
|
_T_478 <= dbg_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dbg_state <= _T_478 @[el2_dbg.scala 346:13]
|
|
node _T_479 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 351:55]
|
|
reg _T_480 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_479, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when io.dmi_reg_en : @[Reg.scala 28:19]
|
|
_T_480 <= dmi_reg_rdata_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.dmi_reg_rdata <= _T_480 @[el2_dbg.scala 351:20]
|
|
node _T_481 = bits(command_reg, 31, 24) @[el2_dbg.scala 355:38]
|
|
node _T_482 = eq(_T_481, UInt<2>("h02")) @[el2_dbg.scala 355:47]
|
|
node _T_483 = bits(data1_reg, 31, 2) @[el2_dbg.scala 355:73]
|
|
node _T_484 = cat(_T_483, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_485 = bits(command_reg, 11, 0) @[el2_dbg.scala 355:118]
|
|
node _T_486 = cat(UInt<20>("h00"), _T_485) @[Cat.scala 29:58]
|
|
node _T_487 = mux(_T_482, _T_484, _T_486) @[el2_dbg.scala 355:25]
|
|
io.dbg_cmd_addr <= _T_487 @[el2_dbg.scala 355:19]
|
|
node _T_488 = bits(data0_reg, 31, 0) @[el2_dbg.scala 356:33]
|
|
io.dbg_cmd_wrdata <= _T_488 @[el2_dbg.scala 356:21]
|
|
node _T_489 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 357:35]
|
|
node _T_490 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 357:76]
|
|
node _T_491 = orr(_T_490) @[el2_dbg.scala 357:84]
|
|
node _T_492 = eq(_T_491, UInt<1>("h00")) @[el2_dbg.scala 357:60]
|
|
node _T_493 = and(_T_489, _T_492) @[el2_dbg.scala 357:58]
|
|
node _T_494 = and(_T_493, io.dma_dbg_ready) @[el2_dbg.scala 357:89]
|
|
node _T_495 = bits(_T_494, 0, 0) @[el2_dbg.scala 357:115]
|
|
io.dbg_cmd_valid <= _T_495 @[el2_dbg.scala 357:20]
|
|
node _T_496 = bits(command_reg, 16, 16) @[el2_dbg.scala 358:34]
|
|
node _T_497 = bits(_T_496, 0, 0) @[el2_dbg.scala 358:45]
|
|
io.dbg_cmd_write <= _T_497 @[el2_dbg.scala 358:20]
|
|
node _T_498 = bits(command_reg, 31, 24) @[el2_dbg.scala 359:38]
|
|
node _T_499 = eq(_T_498, UInt<2>("h02")) @[el2_dbg.scala 359:47]
|
|
node _T_500 = bits(command_reg, 15, 12) @[el2_dbg.scala 359:93]
|
|
node _T_501 = eq(_T_500, UInt<1>("h00")) @[el2_dbg.scala 359:102]
|
|
node _T_502 = cat(UInt<1>("h00"), _T_501) @[Cat.scala 29:58]
|
|
node _T_503 = mux(_T_499, UInt<2>("h02"), _T_502) @[el2_dbg.scala 359:25]
|
|
io.dbg_cmd_type <= _T_503 @[el2_dbg.scala 359:19]
|
|
node _T_504 = bits(command_reg, 21, 20) @[el2_dbg.scala 360:33]
|
|
io.dbg_cmd_size <= _T_504 @[el2_dbg.scala 360:19]
|
|
node _T_505 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 361:36]
|
|
node _T_506 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 361:77]
|
|
node _T_507 = orr(_T_506) @[el2_dbg.scala 361:85]
|
|
node _T_508 = eq(_T_507, UInt<1>("h00")) @[el2_dbg.scala 361:61]
|
|
node _T_509 = and(_T_505, _T_508) @[el2_dbg.scala 361:59]
|
|
node _T_510 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 361:103]
|
|
node _T_511 = or(_T_509, _T_510) @[el2_dbg.scala 361:90]
|
|
node _T_512 = bits(_T_511, 0, 0) @[el2_dbg.scala 361:132]
|
|
io.dbg_dma_bubble <= _T_512 @[el2_dbg.scala 361:21]
|
|
wire sb_nxtstate : UInt<4>
|
|
sb_nxtstate <= UInt<4>("h00")
|
|
sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 364:15]
|
|
sbcs_sbbusy_wren <= UInt<1>("h00") @[el2_dbg.scala 366:20]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 367:19]
|
|
sbcs_sberror_wren <= UInt<1>("h00") @[el2_dbg.scala 368:21]
|
|
sbcs_sberror_din <= UInt<3>("h00") @[el2_dbg.scala 369:20]
|
|
sbaddress0_reg_wren1 <= UInt<1>("h00") @[el2_dbg.scala 370:24]
|
|
node _T_513 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_513 : @[Conditional.scala 40:58]
|
|
node _T_514 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[el2_dbg.scala 373:25]
|
|
sb_nxtstate <= _T_514 @[el2_dbg.scala 373:19]
|
|
node _T_515 = or(sbdata0wr_access, sbreadondata_access) @[el2_dbg.scala 374:39]
|
|
node _T_516 = or(_T_515, sbreadonaddr_access) @[el2_dbg.scala 374:61]
|
|
sb_state_en <= _T_516 @[el2_dbg.scala 374:19]
|
|
sbcs_sbbusy_wren <= sb_state_en @[el2_dbg.scala 375:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h01") @[el2_dbg.scala 376:23]
|
|
node _T_517 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 377:56]
|
|
node _T_518 = orr(_T_517) @[el2_dbg.scala 377:65]
|
|
node _T_519 = and(sbcs_wren, _T_518) @[el2_dbg.scala 377:38]
|
|
sbcs_sberror_wren <= _T_519 @[el2_dbg.scala 377:25]
|
|
node _T_520 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 378:44]
|
|
node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_dbg.scala 378:27]
|
|
node _T_522 = bits(sbcs_reg, 14, 12) @[el2_dbg.scala 378:63]
|
|
node _T_523 = and(_T_521, _T_522) @[el2_dbg.scala 378:53]
|
|
sbcs_sberror_din <= _T_523 @[el2_dbg.scala 378:24]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_524 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_524 : @[Conditional.scala 39:67]
|
|
node _T_525 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 381:41]
|
|
node _T_526 = mux(_T_525, UInt<4>("h09"), UInt<4>("h03")) @[el2_dbg.scala 381:25]
|
|
sb_nxtstate <= _T_526 @[el2_dbg.scala 381:19]
|
|
node _T_527 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 382:40]
|
|
node _T_528 = or(_T_527, sbcs_illegal_size) @[el2_dbg.scala 382:57]
|
|
sb_state_en <= _T_528 @[el2_dbg.scala 382:19]
|
|
node _T_529 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 383:43]
|
|
sbcs_sberror_wren <= _T_529 @[el2_dbg.scala 383:25]
|
|
node _T_530 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 384:30]
|
|
sbcs_sberror_din <= _T_530 @[el2_dbg.scala 384:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_531 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_531 : @[Conditional.scala 39:67]
|
|
node _T_532 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 387:41]
|
|
node _T_533 = mux(_T_532, UInt<4>("h09"), UInt<4>("h04")) @[el2_dbg.scala 387:25]
|
|
sb_nxtstate <= _T_533 @[el2_dbg.scala 387:19]
|
|
node _T_534 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 388:40]
|
|
node _T_535 = or(_T_534, sbcs_illegal_size) @[el2_dbg.scala 388:57]
|
|
sb_state_en <= _T_535 @[el2_dbg.scala 388:19]
|
|
node _T_536 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 389:43]
|
|
sbcs_sberror_wren <= _T_536 @[el2_dbg.scala 389:25]
|
|
node _T_537 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 390:30]
|
|
sbcs_sberror_din <= _T_537 @[el2_dbg.scala 390:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_538 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_538 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h07") @[el2_dbg.scala 393:19]
|
|
node _T_539 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[el2_dbg.scala 394:38]
|
|
sb_state_en <= _T_539 @[el2_dbg.scala 394:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_540 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_540 : @[Conditional.scala 39:67]
|
|
node _T_541 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 397:48]
|
|
node _T_542 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[el2_dbg.scala 397:95]
|
|
node _T_543 = mux(_T_541, UInt<4>("h08"), _T_542) @[el2_dbg.scala 397:25]
|
|
sb_nxtstate <= _T_543 @[el2_dbg.scala 397:19]
|
|
node _T_544 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 398:45]
|
|
node _T_545 = and(_T_544, io.dbg_bus_clk_en) @[el2_dbg.scala 398:70]
|
|
sb_state_en <= _T_545 @[el2_dbg.scala 398:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_546 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_546 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 401:19]
|
|
node _T_547 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[el2_dbg.scala 402:44]
|
|
sb_state_en <= _T_547 @[el2_dbg.scala 402:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_548 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_548 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 405:19]
|
|
node _T_549 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[el2_dbg.scala 406:44]
|
|
sb_state_en <= _T_549 @[el2_dbg.scala 406:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_550 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_550 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 409:19]
|
|
node _T_551 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[el2_dbg.scala 410:38]
|
|
sb_state_en <= _T_551 @[el2_dbg.scala 410:19]
|
|
node _T_552 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 411:40]
|
|
sbcs_sberror_wren <= _T_552 @[el2_dbg.scala 411:25]
|
|
sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 412:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_553 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_553 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 415:19]
|
|
node _T_554 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[el2_dbg.scala 416:39]
|
|
sb_state_en <= _T_554 @[el2_dbg.scala 416:19]
|
|
node _T_555 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 417:40]
|
|
sbcs_sberror_wren <= _T_555 @[el2_dbg.scala 417:25]
|
|
sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 418:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_556 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_556 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 421:19]
|
|
sb_state_en <= UInt<1>("h01") @[el2_dbg.scala 422:19]
|
|
sbcs_sbbusy_wren <= UInt<1>("h01") @[el2_dbg.scala 423:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 424:23]
|
|
node _T_557 = bits(sbcs_reg, 16, 16) @[el2_dbg.scala 425:39]
|
|
sbaddress0_reg_wren1 <= _T_557 @[el2_dbg.scala 425:28]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_558 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[el2_dbg.scala 428:46]
|
|
reg _T_559 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_558, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when sb_state_en : @[Reg.scala 28:19]
|
|
_T_559 <= sb_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
sb_state <= _T_559 @[el2_dbg.scala 428:12]
|
|
node _T_560 = and(io.sb_axi_arvalid, io.sb_axi_arready) @[el2_dbg.scala 432:40]
|
|
sb_bus_cmd_read <= _T_560 @[el2_dbg.scala 432:19]
|
|
node _T_561 = and(io.sb_axi_awvalid, io.sb_axi_awready) @[el2_dbg.scala 433:46]
|
|
sb_bus_cmd_write_addr <= _T_561 @[el2_dbg.scala 433:25]
|
|
node _T_562 = and(io.sb_axi_wvalid, io.sb_axi_wready) @[el2_dbg.scala 434:45]
|
|
sb_bus_cmd_write_data <= _T_562 @[el2_dbg.scala 434:25]
|
|
node _T_563 = and(io.sb_axi_rvalid, io.sb_axi_rready) @[el2_dbg.scala 435:39]
|
|
sb_bus_rsp_read <= _T_563 @[el2_dbg.scala 435:19]
|
|
node _T_564 = and(io.sb_axi_bvalid, io.sb_axi_bready) @[el2_dbg.scala 436:40]
|
|
sb_bus_rsp_write <= _T_564 @[el2_dbg.scala 436:20]
|
|
node _T_565 = bits(io.sb_axi_rresp, 1, 0) @[el2_dbg.scala 437:56]
|
|
node _T_566 = orr(_T_565) @[el2_dbg.scala 437:63]
|
|
node _T_567 = and(sb_bus_rsp_read, _T_566) @[el2_dbg.scala 437:39]
|
|
node _T_568 = bits(io.sb_axi_bresp, 1, 0) @[el2_dbg.scala 437:103]
|
|
node _T_569 = orr(_T_568) @[el2_dbg.scala 437:110]
|
|
node _T_570 = and(sb_bus_rsp_write, _T_569) @[el2_dbg.scala 437:86]
|
|
node _T_571 = or(_T_567, _T_570) @[el2_dbg.scala 437:67]
|
|
sb_bus_rsp_error <= _T_571 @[el2_dbg.scala 437:20]
|
|
node _T_572 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 438:35]
|
|
node _T_573 = eq(sb_state, UInt<4>("h05")) @[el2_dbg.scala 438:70]
|
|
node _T_574 = or(_T_572, _T_573) @[el2_dbg.scala 438:58]
|
|
node _T_575 = bits(_T_574, 0, 0) @[el2_dbg.scala 438:105]
|
|
io.sb_axi_awvalid <= _T_575 @[el2_dbg.scala 438:21]
|
|
io.sb_axi_awaddr <= sbaddress0_reg @[el2_dbg.scala 439:20]
|
|
io.sb_axi_awid <= UInt<1>("h00") @[el2_dbg.scala 440:18]
|
|
node _T_576 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 441:31]
|
|
io.sb_axi_awsize <= _T_576 @[el2_dbg.scala 441:20]
|
|
io.sb_axi_awprot <= UInt<1>("h00") @[el2_dbg.scala 442:20]
|
|
io.sb_axi_awcache <= UInt<4>("h0f") @[el2_dbg.scala 443:21]
|
|
node _T_577 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 444:39]
|
|
io.sb_axi_awregion <= _T_577 @[el2_dbg.scala 444:22]
|
|
io.sb_axi_awlen <= UInt<1>("h00") @[el2_dbg.scala 445:19]
|
|
io.sb_axi_awburst <= UInt<1>("h01") @[el2_dbg.scala 446:21]
|
|
io.sb_axi_awqos <= UInt<1>("h00") @[el2_dbg.scala 447:19]
|
|
io.sb_axi_awlock <= UInt<1>("h00") @[el2_dbg.scala 448:20]
|
|
node _T_578 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 449:34]
|
|
node _T_579 = eq(sb_state, UInt<4>("h06")) @[el2_dbg.scala 449:69]
|
|
node _T_580 = or(_T_578, _T_579) @[el2_dbg.scala 449:57]
|
|
node _T_581 = bits(_T_580, 0, 0) @[el2_dbg.scala 449:104]
|
|
io.sb_axi_wvalid <= _T_581 @[el2_dbg.scala 449:20]
|
|
node _T_582 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:40]
|
|
node _T_583 = eq(_T_582, UInt<1>("h00")) @[el2_dbg.scala 450:49]
|
|
node _T_584 = bits(_T_583, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_585 = mux(_T_584, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_586 = bits(sbdata0_reg, 7, 0) @[el2_dbg.scala 450:81]
|
|
node _T_587 = cat(_T_586, _T_586) @[Cat.scala 29:58]
|
|
node _T_588 = cat(_T_587, _T_587) @[Cat.scala 29:58]
|
|
node _T_589 = cat(_T_588, _T_588) @[Cat.scala 29:58]
|
|
node _T_590 = and(_T_585, _T_589) @[el2_dbg.scala 450:59]
|
|
node _T_591 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:110]
|
|
node _T_592 = eq(_T_591, UInt<1>("h01")) @[el2_dbg.scala 450:119]
|
|
node _T_593 = bits(_T_592, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_594 = mux(_T_593, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_595 = bits(sbdata0_reg, 15, 0) @[el2_dbg.scala 450:153]
|
|
node _T_596 = cat(_T_595, _T_595) @[Cat.scala 29:58]
|
|
node _T_597 = cat(_T_596, _T_596) @[Cat.scala 29:58]
|
|
node _T_598 = and(_T_594, _T_597) @[el2_dbg.scala 450:132]
|
|
node _T_599 = or(_T_590, _T_598) @[el2_dbg.scala 450:90]
|
|
node _T_600 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:23]
|
|
node _T_601 = eq(_T_600, UInt<2>("h02")) @[el2_dbg.scala 451:32]
|
|
node _T_602 = bits(_T_601, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_603 = mux(_T_602, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_604 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:67]
|
|
node _T_605 = cat(_T_604, _T_604) @[Cat.scala 29:58]
|
|
node _T_606 = and(_T_603, _T_605) @[el2_dbg.scala 451:45]
|
|
node _T_607 = or(_T_599, _T_606) @[el2_dbg.scala 450:162]
|
|
node _T_608 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:97]
|
|
node _T_609 = eq(_T_608, UInt<2>("h03")) @[el2_dbg.scala 451:106]
|
|
node _T_610 = bits(_T_609, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_611 = mux(_T_610, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_612 = bits(sbdata1_reg, 31, 0) @[el2_dbg.scala 451:136]
|
|
node _T_613 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:156]
|
|
node _T_614 = cat(_T_612, _T_613) @[Cat.scala 29:58]
|
|
node _T_615 = and(_T_611, _T_614) @[el2_dbg.scala 451:119]
|
|
node _T_616 = or(_T_607, _T_615) @[el2_dbg.scala 451:77]
|
|
io.sb_axi_wdata <= _T_616 @[el2_dbg.scala 450:19]
|
|
node _T_617 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 453:39]
|
|
node _T_618 = eq(_T_617, UInt<1>("h00")) @[el2_dbg.scala 453:48]
|
|
node _T_619 = bits(_T_618, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_620 = mux(_T_619, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_621 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 453:93]
|
|
node _T_622 = dshl(UInt<8>("h01"), _T_621) @[el2_dbg.scala 453:76]
|
|
node _T_623 = and(_T_620, _T_622) @[el2_dbg.scala 453:61]
|
|
node _T_624 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 454:22]
|
|
node _T_625 = eq(_T_624, UInt<1>("h01")) @[el2_dbg.scala 454:31]
|
|
node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_628 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 454:80]
|
|
node _T_629 = cat(_T_628, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_630 = dshl(UInt<8>("h03"), _T_629) @[el2_dbg.scala 454:59]
|
|
node _T_631 = and(_T_627, _T_630) @[el2_dbg.scala 454:44]
|
|
node _T_632 = or(_T_623, _T_631) @[el2_dbg.scala 453:101]
|
|
node _T_633 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 455:22]
|
|
node _T_634 = eq(_T_633, UInt<2>("h02")) @[el2_dbg.scala 455:31]
|
|
node _T_635 = bits(_T_634, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_636 = mux(_T_635, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_637 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 455:80]
|
|
node _T_638 = cat(_T_637, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_639 = dshl(UInt<8>("h0f"), _T_638) @[el2_dbg.scala 455:59]
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node _T_640 = and(_T_636, _T_639) @[el2_dbg.scala 455:44]
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node _T_641 = or(_T_632, _T_640) @[el2_dbg.scala 454:97]
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node _T_642 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 456:22]
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node _T_643 = eq(_T_642, UInt<2>("h03")) @[el2_dbg.scala 456:31]
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node _T_644 = bits(_T_643, 0, 0) @[Bitwise.scala 72:15]
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node _T_645 = mux(_T_644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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node _T_646 = and(_T_645, UInt<8>("h0ff")) @[el2_dbg.scala 456:44]
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node _T_647 = or(_T_641, _T_646) @[el2_dbg.scala 455:95]
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io.sb_axi_wstrb <= _T_647 @[el2_dbg.scala 453:19]
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io.sb_axi_wlast <= UInt<1>("h01") @[el2_dbg.scala 458:19]
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node _T_648 = eq(sb_state, UInt<4>("h03")) @[el2_dbg.scala 459:34]
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node _T_649 = bits(_T_648, 0, 0) @[el2_dbg.scala 459:63]
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io.sb_axi_arvalid <= _T_649 @[el2_dbg.scala 459:21]
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io.sb_axi_araddr <= sbaddress0_reg @[el2_dbg.scala 460:20]
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io.sb_axi_arid <= UInt<1>("h00") @[el2_dbg.scala 461:18]
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node _T_650 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 462:31]
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io.sb_axi_arsize <= _T_650 @[el2_dbg.scala 462:20]
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io.sb_axi_arprot <= UInt<1>("h00") @[el2_dbg.scala 463:20]
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io.sb_axi_arcache <= UInt<1>("h00") @[el2_dbg.scala 464:21]
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node _T_651 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 465:39]
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io.sb_axi_arregion <= _T_651 @[el2_dbg.scala 465:22]
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io.sb_axi_arlen <= UInt<1>("h00") @[el2_dbg.scala 466:19]
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io.sb_axi_arburst <= UInt<1>("h01") @[el2_dbg.scala 467:21]
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io.sb_axi_arqos <= UInt<1>("h00") @[el2_dbg.scala 468:19]
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io.sb_axi_arlock <= UInt<1>("h00") @[el2_dbg.scala 469:20]
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io.sb_axi_bready <= UInt<1>("h01") @[el2_dbg.scala 470:20]
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io.sb_axi_rready <= UInt<1>("h01") @[el2_dbg.scala 471:20]
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node _T_652 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 472:37]
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node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dbg.scala 472:46]
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node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15]
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node _T_655 = mux(_T_654, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_656 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 472:78]
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node _T_657 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 472:109]
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node _T_658 = mul(UInt<4>("h08"), _T_657) @[el2_dbg.scala 472:93]
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node _T_659 = dshr(_T_656, _T_658) @[el2_dbg.scala 472:86]
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node _T_660 = and(_T_659, UInt<64>("h0ff")) @[el2_dbg.scala 472:117]
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node _T_661 = and(_T_655, _T_660) @[el2_dbg.scala 472:59]
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node _T_662 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 473:23]
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node _T_663 = eq(_T_662, UInt<1>("h01")) @[el2_dbg.scala 473:32]
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node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15]
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node _T_665 = mux(_T_664, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_666 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 473:64]
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node _T_667 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 473:96]
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node _T_668 = mul(UInt<5>("h010"), _T_667) @[el2_dbg.scala 473:80]
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node _T_669 = dshr(_T_666, _T_668) @[el2_dbg.scala 473:72]
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node _T_670 = and(_T_669, UInt<64>("h0ffff")) @[el2_dbg.scala 473:104]
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node _T_671 = and(_T_665, _T_670) @[el2_dbg.scala 473:45]
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node _T_672 = or(_T_661, _T_671) @[el2_dbg.scala 472:134]
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node _T_673 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 474:23]
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node _T_674 = eq(_T_673, UInt<2>("h02")) @[el2_dbg.scala 474:32]
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node _T_675 = bits(_T_674, 0, 0) @[Bitwise.scala 72:15]
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node _T_676 = mux(_T_675, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_677 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 474:64]
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node _T_678 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 474:96]
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node _T_679 = mul(UInt<6>("h020"), _T_678) @[el2_dbg.scala 474:80]
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node _T_680 = dshr(_T_677, _T_679) @[el2_dbg.scala 474:72]
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node _T_681 = and(_T_680, UInt<64>("h0ffffffff")) @[el2_dbg.scala 474:101]
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node _T_682 = and(_T_676, _T_681) @[el2_dbg.scala 474:45]
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node _T_683 = or(_T_672, _T_682) @[el2_dbg.scala 473:123]
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node _T_684 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 475:23]
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node _T_685 = eq(_T_684, UInt<2>("h03")) @[el2_dbg.scala 475:32]
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node _T_686 = bits(_T_685, 0, 0) @[Bitwise.scala 72:15]
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node _T_687 = mux(_T_686, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_688 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 475:62]
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node _T_689 = and(_T_687, _T_688) @[el2_dbg.scala 475:45]
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node _T_690 = or(_T_683, _T_689) @[el2_dbg.scala 474:125]
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sb_bus_rdata <= _T_690 @[el2_dbg.scala 472:16]
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