13 lines
433 B
Verilog
13 lines
433 B
Verilog
module encoder_generator(
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input clock,
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input reset,
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input [3:0] io_in,
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output [1:0] io_out
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);
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wire [1:0] _T_6 = io_in[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_7 = io_in[3] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _GEN_0 = {{1'd0}, io_in[1]}; // @[Mux.scala 27:72]
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wire [1:0] _T_9 = _GEN_0 | _T_6; // @[Mux.scala 27:72]
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assign io_out = _T_9 | _T_7; // @[GCD.scala 74:10]
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endmodule
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