598 lines
40 KiB
Plaintext
598 lines
40 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_iccm_mem :
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module el2_ifu_iccm_mem :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>}
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io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
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io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
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node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38]
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node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43]
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node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51]
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node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21]
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node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38]
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node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54]
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node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54]
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wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35]
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node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_11 = and(io.iccm_wren, _T_10) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_12 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_0 = or(_T_11, _T_13) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_16 = and(io.iccm_wren, _T_15) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_17 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_18 = eq(_T_17, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_1 = or(_T_16, _T_18) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_21 = and(io.iccm_wren, _T_20) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_22 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_23 = eq(_T_22, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_2 = or(_T_21, _T_23) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_26 = and(io.iccm_wren, _T_25) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_27 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_28 = eq(_T_27, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_3 = or(_T_26, _T_28) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
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node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
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node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
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node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 38:41]
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node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
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node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
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node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 38:8]
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node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 37:55]
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node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
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node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
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node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
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node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 38:41]
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node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
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node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
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node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 38:8]
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node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 37:55]
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node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
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node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
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node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
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node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 38:41]
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node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
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node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
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node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 38:8]
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node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 37:55]
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node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
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node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
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node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
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node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 38:41]
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node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
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node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
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node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 38:8]
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node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 37:55]
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cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 40:21]
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node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 42:68]
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node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 42:68]
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node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 42:68]
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node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 42:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 42:51]
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write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 42:51]
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write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 42:51]
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write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 42:51]
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write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 42:51]
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node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
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node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 43:70]
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node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
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node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 43:70]
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node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
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node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 43:70]
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node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
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node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 43:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:53]
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read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 43:53]
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read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 43:53]
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read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 43:53]
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read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 43:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 45:28]
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write mport _T_93 = iccm_mem[addr_bank_0], clock
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when write_vec[0] :
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_T_93[0] <= iccm_bank_wr_data[0]
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skip
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when write_vec[1] :
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_T_93[1] <= iccm_bank_wr_data[1]
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skip
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when write_vec[2] :
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_T_93[2] <= iccm_bank_wr_data[2]
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skip
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when write_vec[3] :
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_T_93[3] <= iccm_bank_wr_data[3]
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skip
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write mport _T_94 = iccm_mem[addr_bank_1], clock
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when write_vec[0] :
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_T_94[0] <= iccm_bank_wr_data[0]
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skip
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when write_vec[1] :
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_T_94[1] <= iccm_bank_wr_data[1]
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skip
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when write_vec[2] :
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_T_94[2] <= iccm_bank_wr_data[2]
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skip
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when write_vec[3] :
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_T_94[3] <= iccm_bank_wr_data[3]
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skip
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write mport _T_95 = iccm_mem[addr_bank_2], clock
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when write_vec[0] :
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_T_95[0] <= iccm_bank_wr_data[0]
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skip
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when write_vec[1] :
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_T_95[1] <= iccm_bank_wr_data[1]
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skip
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when write_vec[2] :
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_T_95[2] <= iccm_bank_wr_data[2]
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skip
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when write_vec[3] :
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_T_95[3] <= iccm_bank_wr_data[3]
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skip
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write mport _T_96 = iccm_mem[addr_bank_3], clock
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when write_vec[0] :
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_T_96[0] <= iccm_bank_wr_data[0]
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skip
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when write_vec[1] :
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_T_96[1] <= iccm_bank_wr_data[1]
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skip
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when write_vec[2] :
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_T_96[2] <= iccm_bank_wr_data[2]
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skip
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when write_vec[3] :
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_T_96[3] <= iccm_bank_wr_data[3]
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skip
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read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 47:34]
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iccm_bank_dout[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 47:18]
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iccm_bank_dout[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 47:18]
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iccm_bank_dout[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 47:18]
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iccm_bank_dout[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 47:18]
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wire redundant_valid : UInt<2>
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redundant_valid <= UInt<1>("h00")
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 50:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21]
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node _T_98 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
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node _T_99 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
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node _T_100 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
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node _T_101 = eq(_T_99, _T_100) @[el2_ifu_iccm_mem.scala 53:105]
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node _T_102 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
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node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 53:169]
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node _T_104 = and(_T_101, _T_103) @[el2_ifu_iccm_mem.scala 53:145]
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node _T_105 = and(_T_98, _T_104) @[el2_ifu_iccm_mem.scala 53:71]
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node _T_106 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
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node _T_107 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
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node _T_108 = eq(_T_106, _T_107) @[el2_ifu_iccm_mem.scala 54:37]
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node _T_109 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
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node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 54:99]
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node _T_111 = and(_T_108, _T_110) @[el2_ifu_iccm_mem.scala 54:77]
|
|
node _T_112 = or(_T_105, _T_111) @[el2_ifu_iccm_mem.scala 53:179]
|
|
node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
|
|
node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
|
|
node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
|
|
node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 53:105]
|
|
node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
|
|
node _T_118 = eq(_T_117, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 53:169]
|
|
node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 53:145]
|
|
node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 53:71]
|
|
node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
|
|
node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
|
|
node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 54:37]
|
|
node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
|
|
node _T_125 = eq(_T_124, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 54:99]
|
|
node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 54:77]
|
|
node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 53:179]
|
|
node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
|
|
node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
|
|
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
|
|
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 53:105]
|
|
node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
|
|
node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 53:169]
|
|
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 53:145]
|
|
node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 53:71]
|
|
node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
|
|
node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
|
|
node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 54:37]
|
|
node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
|
|
node _T_140 = eq(_T_139, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 54:99]
|
|
node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 54:77]
|
|
node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 53:179]
|
|
node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
|
|
node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
|
|
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
|
|
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 53:105]
|
|
node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
|
|
node _T_148 = eq(_T_147, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 53:169]
|
|
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 53:145]
|
|
node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 53:71]
|
|
node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
|
|
node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
|
|
node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 54:37]
|
|
node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
|
|
node _T_155 = eq(_T_154, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 54:99]
|
|
node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 54:77]
|
|
node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 53:179]
|
|
node _T_158 = cat(_T_157, _T_142) @[Cat.scala 29:58]
|
|
node _T_159 = cat(_T_158, _T_127) @[Cat.scala 29:58]
|
|
node sel_red1 = cat(_T_159, _T_112) @[Cat.scala 29:58]
|
|
node _T_160 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
|
|
node _T_161 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
|
|
node _T_162 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
|
|
node _T_163 = eq(_T_161, _T_162) @[el2_ifu_iccm_mem.scala 55:105]
|
|
node _T_164 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
|
|
node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 55:169]
|
|
node _T_166 = and(_T_163, _T_165) @[el2_ifu_iccm_mem.scala 55:145]
|
|
node _T_167 = and(_T_160, _T_166) @[el2_ifu_iccm_mem.scala 55:71]
|
|
node _T_168 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
|
|
node _T_169 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
|
|
node _T_170 = eq(_T_168, _T_169) @[el2_ifu_iccm_mem.scala 56:37]
|
|
node _T_171 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
|
|
node _T_172 = eq(_T_171, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:99]
|
|
node _T_173 = and(_T_170, _T_172) @[el2_ifu_iccm_mem.scala 56:77]
|
|
node _T_174 = or(_T_167, _T_173) @[el2_ifu_iccm_mem.scala 55:179]
|
|
node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
|
|
node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
|
|
node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
|
|
node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 55:105]
|
|
node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
|
|
node _T_180 = eq(_T_179, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 55:169]
|
|
node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 55:145]
|
|
node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 55:71]
|
|
node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
|
|
node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
|
|
node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 56:37]
|
|
node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
|
|
node _T_187 = eq(_T_186, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:99]
|
|
node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 56:77]
|
|
node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 55:179]
|
|
node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
|
|
node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
|
|
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
|
|
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 55:105]
|
|
node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
|
|
node _T_195 = eq(_T_194, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 55:169]
|
|
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 55:145]
|
|
node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 55:71]
|
|
node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
|
|
node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
|
|
node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 56:37]
|
|
node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
|
|
node _T_202 = eq(_T_201, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:99]
|
|
node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 56:77]
|
|
node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 55:179]
|
|
node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
|
|
node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
|
|
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
|
|
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 55:105]
|
|
node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
|
|
node _T_210 = eq(_T_209, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 55:169]
|
|
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 55:145]
|
|
node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 55:71]
|
|
node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
|
|
node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
|
|
node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 56:37]
|
|
node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
|
|
node _T_217 = eq(_T_216, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:99]
|
|
node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 56:77]
|
|
node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 55:179]
|
|
node _T_220 = cat(_T_219, _T_204) @[Cat.scala 29:58]
|
|
node _T_221 = cat(_T_220, _T_189) @[Cat.scala 29:58]
|
|
node sel_red0 = cat(_T_221, _T_174) @[Cat.scala 29:58]
|
|
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 58:27]
|
|
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 58:27]
|
|
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 59:27]
|
|
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 59:27]
|
|
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 60:28]
|
|
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18]
|
|
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18]
|
|
node _T_222 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 63:47]
|
|
node _T_223 = bits(_T_222, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
|
|
node _T_224 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 64:47]
|
|
node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
|
|
node _T_226 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:47]
|
|
node _T_227 = not(_T_226) @[el2_ifu_iccm_mem.scala 65:36]
|
|
node _T_228 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:64]
|
|
node _T_229 = not(_T_228) @[el2_ifu_iccm_mem.scala 65:53]
|
|
node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 65:51]
|
|
node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
|
|
node _T_232 = mux(_T_223, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_233 = mux(_T_225, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_234 = mux(_T_231, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_235 = or(_T_232, _T_233) @[Mux.scala 27:72]
|
|
node _T_236 = or(_T_235, _T_234) @[Mux.scala 27:72]
|
|
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
|
iccm_bank_dout_fn_0 <= _T_236 @[Mux.scala 27:72]
|
|
node _T_237 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 63:47]
|
|
node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
|
|
node _T_239 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 64:47]
|
|
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
|
|
node _T_241 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:47]
|
|
node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 65:36]
|
|
node _T_243 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:64]
|
|
node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 65:53]
|
|
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 65:51]
|
|
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
|
|
node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_249 = mux(_T_246, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
|
|
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
|
|
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
|
iccm_bank_dout_fn_1 <= _T_251 @[Mux.scala 27:72]
|
|
node _T_252 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 63:47]
|
|
node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
|
|
node _T_254 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 64:47]
|
|
node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
|
|
node _T_256 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:47]
|
|
node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 65:36]
|
|
node _T_258 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:64]
|
|
node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 65:53]
|
|
node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 65:51]
|
|
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
|
|
node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_264 = mux(_T_261, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72]
|
|
node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
|
|
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
|
iccm_bank_dout_fn_2 <= _T_266 @[Mux.scala 27:72]
|
|
node _T_267 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 63:47]
|
|
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
|
|
node _T_269 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 64:47]
|
|
node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
|
|
node _T_271 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:47]
|
|
node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 65:36]
|
|
node _T_273 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:64]
|
|
node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 65:53]
|
|
node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 65:51]
|
|
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
|
|
node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_279 = mux(_T_276, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72]
|
|
node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
|
|
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
|
iccm_bank_dout_fn_3 <= _T_281 @[Mux.scala 27:72]
|
|
wire redundant_lru : UInt<1>
|
|
redundant_lru <= UInt<1>("h00")
|
|
node _T_282 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:20]
|
|
node r0_addr_en = and(_T_282, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 67:35]
|
|
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 68:35]
|
|
node _T_283 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 69:63]
|
|
node _T_284 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 69:78]
|
|
node _T_285 = or(_T_283, _T_284) @[el2_ifu_iccm_mem.scala 69:67]
|
|
node _T_286 = and(_T_285, io.iccm_rden) @[el2_ifu_iccm_mem.scala 69:83]
|
|
node _T_287 = and(_T_286, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 69:98]
|
|
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_287) @[el2_ifu_iccm_mem.scala 69:50]
|
|
node _T_288 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:55]
|
|
node _T_289 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 70:84]
|
|
node _T_290 = mux(_T_289, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:74]
|
|
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_288, _T_290) @[el2_ifu_iccm_mem.scala 70:29]
|
|
reg _T_291 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when redundant_lru_en : @[Reg.scala 28:19]
|
|
_T_291 <= redundant_lru_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
redundant_lru <= _T_291 @[el2_ifu_iccm_mem.scala 71:17]
|
|
node _T_292 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:52]
|
|
reg _T_293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
|
_T_293 <= _T_292 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
redundant_address[0] <= _T_293 @[el2_ifu_iccm_mem.scala 72:24]
|
|
node _T_294 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 73:52]
|
|
node _T_295 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 73:85]
|
|
reg _T_296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_295 : @[Reg.scala 28:19]
|
|
_T_296 <= _T_294 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
redundant_address[1] <= _T_296 @[el2_ifu_iccm_mem.scala 73:24]
|
|
node _T_297 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 74:57]
|
|
reg _T_298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_297 : @[Reg.scala 28:19]
|
|
_T_298 <= UInt<1>("h01") @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg _T_299 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
|
_T_299 <= UInt<1>("h01") @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_300 = cat(_T_298, _T_299) @[Cat.scala 29:58]
|
|
redundant_valid <= _T_300 @[el2_ifu_iccm_mem.scala 74:19]
|
|
node _T_301 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 76:45]
|
|
node _T_302 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 76:85]
|
|
node _T_303 = eq(_T_301, _T_302) @[el2_ifu_iccm_mem.scala 76:61]
|
|
node _T_304 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 77:22]
|
|
node _T_305 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 77:48]
|
|
node _T_306 = and(_T_304, _T_305) @[el2_ifu_iccm_mem.scala 77:26]
|
|
node _T_307 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 77:70]
|
|
node _T_308 = eq(_T_307, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 77:75]
|
|
node _T_309 = or(_T_306, _T_308) @[el2_ifu_iccm_mem.scala 77:52]
|
|
node _T_310 = and(_T_303, _T_309) @[el2_ifu_iccm_mem.scala 76:102]
|
|
node _T_311 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 77:101]
|
|
node _T_312 = and(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 77:84]
|
|
node _T_313 = and(_T_312, io.iccm_wren) @[el2_ifu_iccm_mem.scala 77:105]
|
|
node _T_314 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:6]
|
|
node _T_315 = and(_T_314, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:21]
|
|
node redundant_data0_en = or(_T_313, _T_315) @[el2_ifu_iccm_mem.scala 77:121]
|
|
node _T_316 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 79:49]
|
|
node _T_317 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:73]
|
|
node _T_318 = and(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 79:52]
|
|
node _T_319 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:100]
|
|
node _T_320 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 79:122]
|
|
node _T_321 = eq(_T_320, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 79:127]
|
|
node _T_322 = and(_T_319, _T_321) @[el2_ifu_iccm_mem.scala 79:104]
|
|
node _T_323 = or(_T_318, _T_322) @[el2_ifu_iccm_mem.scala 79:78]
|
|
node _T_324 = bits(_T_323, 0, 0) @[el2_ifu_iccm_mem.scala 79:137]
|
|
node _T_325 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 80:20]
|
|
node _T_326 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 80:44]
|
|
node redundant_data0_in = mux(_T_324, _T_325, _T_326) @[el2_ifu_iccm_mem.scala 79:31]
|
|
node _T_327 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 81:78]
|
|
reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_327 : @[Reg.scala 28:19]
|
|
_T_328 <= redundant_data0_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
redundant_data[0] <= _T_328 @[el2_ifu_iccm_mem.scala 81:21]
|
|
node _T_329 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 83:45]
|
|
node _T_330 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 83:85]
|
|
node _T_331 = eq(_T_329, _T_330) @[el2_ifu_iccm_mem.scala 83:61]
|
|
node _T_332 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 84:22]
|
|
node _T_333 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 84:48]
|
|
node _T_334 = and(_T_332, _T_333) @[el2_ifu_iccm_mem.scala 84:26]
|
|
node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 84:70]
|
|
node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 84:75]
|
|
node _T_337 = or(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 84:52]
|
|
node _T_338 = and(_T_331, _T_337) @[el2_ifu_iccm_mem.scala 83:102]
|
|
node _T_339 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 84:101]
|
|
node _T_340 = and(_T_338, _T_339) @[el2_ifu_iccm_mem.scala 84:84]
|
|
node _T_341 = and(_T_340, io.iccm_wren) @[el2_ifu_iccm_mem.scala 84:105]
|
|
node _T_342 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 85:6]
|
|
node _T_343 = and(_T_342, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:21]
|
|
node redundant_data1_en = or(_T_341, _T_343) @[el2_ifu_iccm_mem.scala 84:121]
|
|
node _T_344 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 86:49]
|
|
node _T_345 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:73]
|
|
node _T_346 = and(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 86:52]
|
|
node _T_347 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:100]
|
|
node _T_348 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 86:122]
|
|
node _T_349 = eq(_T_348, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 86:127]
|
|
node _T_350 = and(_T_347, _T_349) @[el2_ifu_iccm_mem.scala 86:104]
|
|
node _T_351 = or(_T_346, _T_350) @[el2_ifu_iccm_mem.scala 86:78]
|
|
node _T_352 = bits(_T_351, 0, 0) @[el2_ifu_iccm_mem.scala 86:137]
|
|
node _T_353 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 87:20]
|
|
node _T_354 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 87:44]
|
|
node redundant_data1_in = mux(_T_352, _T_353, _T_354) @[el2_ifu_iccm_mem.scala 86:31]
|
|
node _T_355 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 88:78]
|
|
reg _T_356 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_355 : @[Reg.scala 28:19]
|
|
_T_356 <= redundant_data1_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
redundant_data[1] <= _T_356 @[el2_ifu_iccm_mem.scala 88:21]
|
|
node _T_357 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 90:50]
|
|
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 90:34]
|
|
iccm_rd_addr_lo_q <= _T_357 @[el2_ifu_iccm_mem.scala 90:34]
|
|
node _T_358 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 91:48]
|
|
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 91:34]
|
|
iccm_rd_addr_hi_q <= _T_358 @[el2_ifu_iccm_mem.scala 91:34]
|
|
node _T_359 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 93:86]
|
|
node _T_360 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
|
|
node _T_361 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 93:86]
|
|
node _T_362 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
|
|
node _T_363 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 93:86]
|
|
node _T_364 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
|
|
node _T_365 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 93:86]
|
|
node _T_366 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
|
|
node _T_367 = mux(_T_359, _T_360, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_368 = mux(_T_361, _T_362, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_369 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_370 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_371 = or(_T_367, _T_368) @[Mux.scala 27:72]
|
|
node _T_372 = or(_T_371, _T_369) @[Mux.scala 27:72]
|
|
node _T_373 = or(_T_372, _T_370) @[Mux.scala 27:72]
|
|
wire _T_374 : UInt<32> @[Mux.scala 27:72]
|
|
_T_374 <= _T_373 @[Mux.scala 27:72]
|
|
node _T_375 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
|
|
node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 94:77]
|
|
node _T_377 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
|
|
node _T_378 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
|
|
node _T_379 = eq(_T_378, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 94:77]
|
|
node _T_380 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
|
|
node _T_381 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
|
|
node _T_382 = eq(_T_381, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 94:77]
|
|
node _T_383 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
|
|
node _T_384 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
|
|
node _T_385 = eq(_T_384, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:77]
|
|
node _T_386 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
|
|
node _T_387 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_388 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_389 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_390 = mux(_T_385, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_391 = or(_T_387, _T_388) @[Mux.scala 27:72]
|
|
node _T_392 = or(_T_391, _T_389) @[Mux.scala 27:72]
|
|
node _T_393 = or(_T_392, _T_390) @[Mux.scala 27:72]
|
|
wire _T_394 : UInt<32> @[Mux.scala 27:72]
|
|
_T_394 <= _T_393 @[Mux.scala 27:72]
|
|
node iccm_rd_data_pre = cat(_T_374, _T_394) @[Cat.scala 29:58]
|
|
node _T_395 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 95:43]
|
|
node _T_396 = bits(_T_395, 0, 0) @[el2_ifu_iccm_mem.scala 95:53]
|
|
node _T_397 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_398 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 95:89]
|
|
node _T_399 = cat(_T_397, _T_398) @[Cat.scala 29:58]
|
|
node _T_400 = mux(_T_396, _T_399, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 95:25]
|
|
io.iccm_rd_data <= _T_400 @[el2_ifu_iccm_mem.scala 95:19]
|
|
node _T_401 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:85]
|
|
node _T_402 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:85]
|
|
node _T_403 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:85]
|
|
node _T_404 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:85]
|
|
node _T_405 = mux(_T_401, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_406 = mux(_T_402, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_407 = mux(_T_403, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_408 = mux(_T_404, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_409 = or(_T_405, _T_406) @[Mux.scala 27:72]
|
|
node _T_410 = or(_T_409, _T_407) @[Mux.scala 27:72]
|
|
node _T_411 = or(_T_410, _T_408) @[Mux.scala 27:72]
|
|
wire _T_412 : UInt<39> @[Mux.scala 27:72]
|
|
_T_412 <= _T_411 @[Mux.scala 27:72]
|
|
node _T_413 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
|
|
node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:79]
|
|
node _T_415 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
|
|
node _T_416 = eq(_T_415, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:79]
|
|
node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
|
|
node _T_418 = eq(_T_417, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:79]
|
|
node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
|
|
node _T_420 = eq(_T_419, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:79]
|
|
node _T_421 = mux(_T_414, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_422 = mux(_T_416, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_423 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_424 = mux(_T_420, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_425 = or(_T_421, _T_422) @[Mux.scala 27:72]
|
|
node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
|
|
node _T_427 = or(_T_426, _T_424) @[Mux.scala 27:72]
|
|
wire _T_428 : UInt<39> @[Mux.scala 27:72]
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|
_T_428 <= _T_427 @[Mux.scala 27:72]
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node _T_429 = cat(_T_412, _T_428) @[Cat.scala 29:58]
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io.iccm_rd_data_ecc <= _T_429 @[el2_ifu_iccm_mem.scala 96:23]
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