155 lines
7.3 KiB
Scala
155 lines
7.3 KiB
Scala
package ifu
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import chisel3._
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import chisel3.internal.naming.chiselName
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import chisel3.util._
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import exu._
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import lib._
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import include._
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@chiselName
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class ifu extends Module with lib with RequireAsyncReset {
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val io = IO(new Bundle{
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val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
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val dec_i0_decode_d = Input(Bool()) // Dec
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val dec_fa_error_index = Input(UInt(log2Ceil(BTB_SIZE).W))// Fully associative btb error index
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val exu_flush_final = Input(Bool())
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val exu_flush_path_final = Input(UInt(31.W))
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val free_l2clk = Input(Clock())
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val active_clk = Input(Clock())
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val ifu_dec = new ifu_dec() // IFU and DEC interconnects
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val exu_ifu = new exu_ifu() // IFU and EXU interconnects
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val iccm = new iccm_mem() // ICCM memory signals
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val ic = new ic_mem() // I$ memory signals
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val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
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val ifu_bus_clk_en = Input(Bool())
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val ifu_dma = new ifu_dma() // DMA signals
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// ICCM DMA signals
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val iccm_dma_ecc_error = Output(Bool())
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val iccm_dma_rvalid = Output(Bool())
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val iccm_dma_rdata = Output(UInt(64.W))
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val iccm_dma_rtag = Output(UInt(3.W))
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val iccm_ready = Output(Bool())
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// Performance counter
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val iccm_dma_sb_error = Output(Bool())
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val dec_tlu_flush_lower_wb = Input(Bool())
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val scan_mode = Input(Bool())
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})
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val mem_ctl = Module(new ifu_mem_ctl)
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val bp_ctl = Module(new ifu_bp_ctl)
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val aln_ctl = Module(new ifu_aln_ctl)
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val ifc_ctl = Module(new ifu_ifc_ctl)
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// IFC wiring Inputs
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//ifc_ctl.io.active_clk := io.active_clk
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ifc_ctl.io.free_l2clk := io.free_l2clk
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ifc_ctl.io.scan_mode := io.scan_mode
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ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
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ifc_ctl.io.ifu_fb_consume1 := aln_ctl.io.ifu_fb_consume1
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ifc_ctl.io.ifu_fb_consume2 := aln_ctl.io.ifu_fb_consume2
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ifc_ctl.io.dec_ifc <> io.ifu_dec.dec_ifc
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ifc_ctl.io.exu_flush_final := io.exu_flush_final
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ifc_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
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ifc_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
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ifc_ctl.io.ic_dma_active := mem_ctl.io.ic_dma_active
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ifc_ctl.io.ic_write_stall := mem_ctl.io.ic_write_stall
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ifc_ctl.io.dma_ifc <> io.ifu_dma.dma_ifc
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ifc_ctl.io.ifu_ic_mb_empty := mem_ctl.io.ifu_ic_mb_empty
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ifc_ctl.io.exu_flush_path_final := io.exu_flush_path_final
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// ALN wiring Inputs
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aln_ctl.io.scan_mode := io.scan_mode
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aln_ctl.io.active_clk := io.active_clk
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aln_ctl.io.ifu_async_error_start := mem_ctl.io.ifu_async_error_start
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aln_ctl.io.iccm_rd_ecc_double_err := mem_ctl.io.iccm_rd_ecc_double_err
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aln_ctl.io.ic_access_fault_f := mem_ctl.io.ic_access_fault_f
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aln_ctl.io.ic_access_fault_type_f := mem_ctl.io.ic_access_fault_type_f
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aln_ctl.io.ifu_bp_fghr_f := bp_ctl.io.ifu_bp_fghr_f
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aln_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
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aln_ctl.io.ifu_bp_poffset_f := bp_ctl.io.ifu_bp_poffset_f
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aln_ctl.io.ifu_bp_hist0_f := bp_ctl.io.ifu_bp_hist0_f
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aln_ctl.io.ifu_bp_hist1_f := bp_ctl.io.ifu_bp_hist1_f
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aln_ctl.io.ifu_bp_pc4_f := bp_ctl.io.ifu_bp_pc4_f
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aln_ctl.io.ifu_bp_way_f := bp_ctl.io.ifu_bp_way_f
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aln_ctl.io.ifu_bp_valid_f := bp_ctl.io.ifu_bp_valid_f
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aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
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aln_ctl.io.exu_flush_final := io.exu_flush_final
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aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
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// io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst := aln_ctl.io.ifu_i0_cinst
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf := aln_ctl.io.ifu_i0_icaf
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type := aln_ctl.io.ifu_i0_icaf_type
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second := aln_ctl.io.ifu_i0_icaf_second
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc := aln_ctl.io.ifu_i0_dbecc
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index := aln_ctl.io.ifu_i0_bp_index
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io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr := aln_ctl.io.ifu_i0_bp_fghr
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag := aln_ctl.io.ifu_i0_bp_btag
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid := aln_ctl.io.ifu_i0_valid
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr := aln_ctl.io.ifu_i0_instr
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc := aln_ctl.io.ifu_i0_pc
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// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 := aln_ctl.io.ifu_i0_pc4
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// io.ifu_dec.dec_aln.ifu_pmu_instr_aligned := aln_ctl.io.ifu_pmu_instr_aligned
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// aln_ctl.io.i0_brp <> io.ifu_dec.dec_aln.aln_ib.i0_brp
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aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d
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aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f
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aln_ctl.io.ifu_fetch_data_f := mem_ctl.io.ic_data_f
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aln_ctl.io.ifu_fetch_val := mem_ctl.io.ifu_fetch_val
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aln_ctl.io.ifu_fetch_pc := ifc_ctl.io.ifc_fetch_addr_f
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// BP wiring Inputs
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bp_ctl.io.scan_mode := io.scan_mode
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bp_ctl.io.active_clk := io.active_clk
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bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
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bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
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bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
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bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
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bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
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bp_ctl.io.exu_flush_final := io.exu_flush_final
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bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
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bp_ctl.io.dec_fa_error_index := io.dec_fa_error_index
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// bp_ctl.btb_bank0_rd_data_way1_out.suggestName("bp_ctl.btb_bank0_rd_data_way1_out")
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// for(i <- 0 until BTB_ARRAY_DEPTH) {dontTouch(bp_ctl.btb_bank0_rd_data_way0_out(i))}
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// dontTouch(bp_ctl.btb_bank0_rd_data_way1_out(0))
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// dontTouch(bp_ctl.btb_bank0_rd_data_way0_f)
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// dontTouch(bp_ctl.btb_bank0_rd_data_way1_f)
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// dontTouch(bp_ctl.btb_bank0_rd_data_way0_p1_f)
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// dontTouch(bp_ctl.btb_bank0_rd_data_way1_p1_f)
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// mem-ctl Inputs
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mem_ctl.io.free_l2clk := io.free_l2clk
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mem_ctl.io.active_clk := io.active_clk
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mem_ctl.io.exu_flush_final := io.exu_flush_final
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mem_ctl.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
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mem_ctl.io.ifc_fetch_addr_bf := ifc_ctl.io.ifc_fetch_addr_bf
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mem_ctl.io.ifc_fetch_uncacheable_bf := ifc_ctl.io.ifc_fetch_uncacheable_bf
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mem_ctl.io.ifc_fetch_req_bf := ifc_ctl.io.ifc_fetch_req_bf
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mem_ctl.io.ifc_fetch_req_bf_raw := ifc_ctl.io.ifc_fetch_req_bf_raw
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mem_ctl.io.ifc_iccm_access_bf := ifc_ctl.io.ifc_iccm_access_bf
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mem_ctl.io.ifc_region_acc_fault_bf := ifc_ctl.io.ifc_region_acc_fault_bf
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mem_ctl.io.ifc_dma_access_ok := ifc_ctl.io.ifc_dma_access_ok
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mem_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
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mem_ctl.io.ifu_bp_inst_mask_f := bp_ctl.io.ifu_bp_inst_mask_f
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mem_ctl.io.ifu_axi <> io.ifu
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mem_ctl.io.ifu_bus_clk_en := io.ifu_bus_clk_en
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mem_ctl.io.dma_mem_ctl <> io.ifu_dma.dma_mem_ctl
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mem_ctl.io.ic <> io.ic
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mem_ctl.io.iccm <> io.iccm
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mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
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mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
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mem_ctl.io.scan_mode := io.scan_mode
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// DMA to the ICCM
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io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
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io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
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io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
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io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
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io.iccm_ready := mem_ctl.io.iccm_ready
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io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
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}
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object ifu_top extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
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} |