470 lines
29 KiB
Plaintext
470 lines
29 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit ahb_to_axi4 :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module ahb_to_axi4 :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}}
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wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10]
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_T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10]
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_T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10]
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_T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10]
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io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10]
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_T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10]
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_T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10]
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_T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10]
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io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10]
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io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10]
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_T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10]
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_T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10]
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wire master_wstrb : UInt<8>
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master_wstrb <= UInt<8>("h00")
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wire buf_state_en : UInt<1>
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buf_state_en <= UInt<1>("h00")
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wire buf_read_error_in : UInt<1>
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buf_read_error_in <= UInt<1>("h00")
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node ahb_hready = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 27:50]
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node _T_1 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
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node _T_2 = mux(_T_1, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_3 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 28:72]
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node ahb_htrans_in = and(_T_2, _T_3) @[ahb_to_axi4.scala 28:49]
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wire ahb_hwdata_q : UInt<64>
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ahb_hwdata_q <= UInt<64>("h00")
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wire buf_rdata_en : UInt<1>
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buf_rdata_en <= UInt<1>("h00")
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wire bus_clk : Clock @[ahb_to_axi4.scala 33:33]
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wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 34:33]
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wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 35:33]
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node _T_4 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 36:80]
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node _T_5 = and(ahb_hready, _T_4) @[ahb_to_axi4.scala 36:57]
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node ahb_addr_clk_en = and(io.bus_clk_en, _T_5) @[ahb_to_axi4.scala 36:43]
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node buf_rdata_clk_en = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 37:43]
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node _T_6 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 40:33]
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bus_clk <= _T_6 @[ahb_to_axi4.scala 40:19]
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node _T_7 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 41:33]
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ahb_addr_clk <= _T_7 @[ahb_to_axi4.scala 41:19]
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node _T_8 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 42:33]
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buf_rdata_clk <= _T_8 @[ahb_to_axi4.scala 42:19]
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reg buf_read_error : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when io.bus_clk_en : @[Reg.scala 28:19]
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buf_read_error <= buf_read_error_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg buf_rdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when buf_rdata_clk_en : @[Reg.scala 28:19]
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buf_rdata <= io.axi.r.bits.data @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_hresp_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when io.bus_clk_en : @[Reg.scala 28:19]
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ahb_hresp_q <= io.ahb.sig.in.hresp @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_hsize_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when ahb_addr_clk_en : @[Reg.scala 28:19]
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ahb_hsize_q <= io.ahb.sig.out.hsize @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_hwrite_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when ahb_addr_clk_en : @[Reg.scala 28:19]
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ahb_hwrite_q <= io.ahb.sig.out.hwrite @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_haddr_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when ahb_addr_clk_en : @[Reg.scala 28:19]
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ahb_haddr_q <= io.ahb.sig.out.haddr @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_hready_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when io.bus_clk_en : @[Reg.scala 28:19]
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ahb_hready_q <= ahb_hready @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg ahb_htrans_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when io.bus_clk_en : @[Reg.scala 28:19]
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ahb_htrans_q <= ahb_htrans_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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wire cmdbuf_wr_en : UInt<1>
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cmdbuf_wr_en <= UInt<1>("h00")
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node _T_9 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 60:70]
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node _T_10 = and(io.bus_clk_en, _T_9) @[lib.scala 383:57]
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reg cmdbuf_write : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_10 : @[Reg.scala 28:19]
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cmdbuf_write <= ahb_hwrite_q @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_11 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 61:44]
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node _T_12 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 61:82]
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node _T_13 = or(_T_11, _T_12) @[ahb_to_axi4.scala 61:63]
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node _T_14 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 61:104]
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node _T_15 = and(_T_13, _T_14) @[ahb_to_axi4.scala 61:102]
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node _T_16 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 61:144]
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node _T_17 = and(io.ahb.sig.in.hresp, _T_16) @[ahb_to_axi4.scala 61:142]
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node cmdbuf_rst = or(_T_15, _T_17) @[ahb_to_axi4.scala 61:119]
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node _T_18 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 62:64]
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wire cmdbuf_vld : UInt @[lib.scala 389:21]
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node _T_19 = eq(cmdbuf_rst, UInt<1>("h00")) @[lib.scala 391:73]
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node _T_20 = and(UInt<1>("h01"), _T_19) @[lib.scala 391:53]
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node _T_21 = or(_T_18, cmdbuf_rst) @[lib.scala 391:92]
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node _T_22 = and(_T_21, io.bus_clk_en) @[lib.scala 391:99]
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node _T_23 = bits(_T_22, 0, 0) @[lib.scala 8:44]
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reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_23 : @[Reg.scala 28:19]
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_T_24 <= _T_20 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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cmdbuf_vld <= _T_24 @[lib.scala 391:14]
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node _T_25 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 63:58]
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node _T_26 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 63:96]
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node _T_27 = or(_T_25, _T_26) @[ahb_to_axi4.scala 63:77]
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node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 63:39]
|
|
node cmdbuf_full = and(cmdbuf_vld, _T_28) @[ahb_to_axi4.scala 63:37]
|
|
node _T_29 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 64:48]
|
|
node _T_30 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 64:74]
|
|
node _T_31 = and(io.bus_clk_en, _T_30) @[lib.scala 383:57]
|
|
reg cmdbuf_size : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_31 : @[Reg.scala 28:19]
|
|
cmdbuf_size <= _T_29 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_32 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 65:70]
|
|
node _T_33 = and(io.bus_clk_en, _T_32) @[lib.scala 383:57]
|
|
reg cmdbuf_wstrb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_33 : @[Reg.scala 28:19]
|
|
cmdbuf_wstrb <= master_wstrb @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_34 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 66:64]
|
|
node _T_35 = and(_T_34, io.bus_clk_en) @[ahb_to_axi4.scala 66:66]
|
|
inst rvclkhdr of rvclkhdr @[lib.scala 399:23]
|
|
rvclkhdr.clock <= clock
|
|
rvclkhdr.reset <= reset
|
|
rvclkhdr.io.clk <= clock @[lib.scala 401:18]
|
|
rvclkhdr.io.en <= _T_35 @[lib.scala 402:17]
|
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
|
|
reg cmdbuf_addr : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_35 : @[Reg.scala 28:19]
|
|
cmdbuf_addr <= ahb_haddr_q @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_36 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 67:74]
|
|
node _T_37 = and(_T_36, io.bus_clk_en) @[ahb_to_axi4.scala 67:76]
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23]
|
|
rvclkhdr_1.clock <= clock
|
|
rvclkhdr_1.reset <= reset
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 401:18]
|
|
rvclkhdr_1.io.en <= _T_37 @[lib.scala 402:17]
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
|
|
reg cmdbuf_wdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_37 : @[Reg.scala 28:19]
|
|
cmdbuf_wdata <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_38 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
|
node ahb_addr_in_dccm_region_nc = eq(_T_38, UInt<4>("h0f")) @[lib.scala 84:47]
|
|
node _T_39 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
|
|
node ahb_addr_in_dccm = eq(_T_39, UInt<16>("h0f004")) @[lib.scala 87:29]
|
|
node _T_40 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
|
node ahb_addr_in_iccm_region_nc = eq(_T_40, UInt<4>("h0e")) @[lib.scala 84:47]
|
|
node _T_41 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
|
|
node ahb_addr_in_iccm = eq(_T_41, UInt<16>("h0ee00")) @[lib.scala 87:29]
|
|
node _T_42 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
|
node ahb_addr_in_pic_region_nc = eq(_T_42, UInt<4>("h0f")) @[lib.scala 84:47]
|
|
node _T_43 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
|
|
node ahb_addr_in_pic = eq(_T_43, UInt<17>("h01e018")) @[lib.scala 87:29]
|
|
wire buf_state : UInt<2>
|
|
buf_state <= UInt<2>("h00")
|
|
wire buf_nxtstate : UInt<2>
|
|
buf_nxtstate <= UInt<2>("h00")
|
|
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 76:31]
|
|
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 77:31]
|
|
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 78:31]
|
|
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 79:31]
|
|
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 80:31]
|
|
node _T_44 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
|
|
when _T_44 : @[Conditional.scala 40:58]
|
|
node _T_45 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 84:26]
|
|
buf_nxtstate <= _T_45 @[ahb_to_axi4.scala 84:20]
|
|
node _T_46 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 85:57]
|
|
node _T_47 = and(ahb_hready, _T_46) @[ahb_to_axi4.scala 85:34]
|
|
node _T_48 = and(_T_47, io.ahb.hsel) @[ahb_to_axi4.scala 85:61]
|
|
buf_state_en <= _T_48 @[ahb_to_axi4.scala 85:20]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_49 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
|
|
when _T_49 : @[Conditional.scala 39:67]
|
|
node _T_50 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 88:72]
|
|
node _T_51 = eq(_T_50, UInt<1>("h00")) @[ahb_to_axi4.scala 88:79]
|
|
node _T_52 = or(io.ahb.sig.in.hresp, _T_51) @[ahb_to_axi4.scala 88:48]
|
|
node _T_53 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 88:93]
|
|
node _T_54 = or(_T_52, _T_53) @[ahb_to_axi4.scala 88:91]
|
|
node _T_55 = bits(_T_54, 0, 0) @[ahb_to_axi4.scala 88:107]
|
|
node _T_56 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 88:124]
|
|
node _T_57 = mux(_T_55, UInt<2>("h00"), _T_56) @[ahb_to_axi4.scala 88:26]
|
|
buf_nxtstate <= _T_57 @[ahb_to_axi4.scala 88:20]
|
|
node _T_58 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 89:24]
|
|
node _T_59 = or(_T_58, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 89:37]
|
|
buf_state_en <= _T_59 @[ahb_to_axi4.scala 89:20]
|
|
node _T_60 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 90:23]
|
|
node _T_61 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 90:85]
|
|
node _T_62 = eq(_T_61, UInt<2>("h01")) @[ahb_to_axi4.scala 90:92]
|
|
node _T_63 = and(_T_62, io.ahb.hsel) @[ahb_to_axi4.scala 90:110]
|
|
node _T_64 = or(io.ahb.sig.in.hresp, _T_63) @[ahb_to_axi4.scala 90:60]
|
|
node _T_65 = eq(_T_64, UInt<1>("h00")) @[ahb_to_axi4.scala 90:38]
|
|
node _T_66 = and(_T_60, _T_65) @[ahb_to_axi4.scala 90:36]
|
|
cmdbuf_wr_en <= _T_66 @[ahb_to_axi4.scala 90:20]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_67 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
|
|
when _T_67 : @[Conditional.scala 39:67]
|
|
node _T_68 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 93:26]
|
|
buf_nxtstate <= _T_68 @[ahb_to_axi4.scala 93:20]
|
|
node _T_69 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 94:24]
|
|
node _T_70 = or(_T_69, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 94:37]
|
|
buf_state_en <= _T_70 @[ahb_to_axi4.scala 94:20]
|
|
node _T_71 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 95:23]
|
|
node _T_72 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 95:46]
|
|
node _T_73 = and(_T_71, _T_72) @[ahb_to_axi4.scala 95:44]
|
|
cmdbuf_wr_en <= _T_73 @[ahb_to_axi4.scala 95:20]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_74 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
|
|
when _T_74 : @[Conditional.scala 39:67]
|
|
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 98:20]
|
|
node _T_75 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 99:40]
|
|
node _T_76 = and(io.axi.r.valid, _T_75) @[ahb_to_axi4.scala 99:38]
|
|
buf_state_en <= _T_76 @[ahb_to_axi4.scala 99:20]
|
|
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 100:20]
|
|
node _T_77 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 101:61]
|
|
node _T_78 = orr(_T_77) @[ahb_to_axi4.scala 101:68]
|
|
node _T_79 = and(buf_state_en, _T_78) @[ahb_to_axi4.scala 101:41]
|
|
buf_read_error_in <= _T_79 @[ahb_to_axi4.scala 101:25]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_80 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 104:78]
|
|
node _T_81 = and(io.bus_clk_en, _T_80) @[lib.scala 383:57]
|
|
reg _T_82 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_81 : @[Reg.scala 28:19]
|
|
_T_82 <= buf_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
buf_state <= _T_82 @[ahb_to_axi4.scala 104:31]
|
|
node _T_83 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 106:54]
|
|
node _T_84 = eq(_T_83, UInt<1>("h00")) @[ahb_to_axi4.scala 106:60]
|
|
node _T_85 = bits(_T_84, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_86 = mux(_T_85, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_87 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 106:92]
|
|
node _T_88 = dshl(UInt<1>("h01"), _T_87) @[ahb_to_axi4.scala 106:78]
|
|
node _T_89 = and(_T_86, _T_88) @[ahb_to_axi4.scala 106:70]
|
|
node _T_90 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 107:24]
|
|
node _T_91 = eq(_T_90, UInt<1>("h01")) @[ahb_to_axi4.scala 107:30]
|
|
node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_93 = mux(_T_92, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_94 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 107:62]
|
|
node _T_95 = dshl(UInt<2>("h03"), _T_94) @[ahb_to_axi4.scala 107:48]
|
|
node _T_96 = and(_T_93, _T_95) @[ahb_to_axi4.scala 107:40]
|
|
node _T_97 = or(_T_89, _T_96) @[ahb_to_axi4.scala 106:109]
|
|
node _T_98 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 108:24]
|
|
node _T_99 = eq(_T_98, UInt<2>("h02")) @[ahb_to_axi4.scala 108:30]
|
|
node _T_100 = bits(_T_99, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_101 = mux(_T_100, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_102 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 108:62]
|
|
node _T_103 = dshl(UInt<4>("h0f"), _T_102) @[ahb_to_axi4.scala 108:48]
|
|
node _T_104 = and(_T_101, _T_103) @[ahb_to_axi4.scala 108:40]
|
|
node _T_105 = or(_T_97, _T_104) @[ahb_to_axi4.scala 107:79]
|
|
node _T_106 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 109:24]
|
|
node _T_107 = eq(_T_106, UInt<2>("h03")) @[ahb_to_axi4.scala 109:30]
|
|
node _T_108 = bits(_T_107, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_109 = mux(_T_108, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_110 = and(_T_109, UInt<8>("h0ff")) @[ahb_to_axi4.scala 109:40]
|
|
node _T_111 = or(_T_105, _T_110) @[ahb_to_axi4.scala 108:79]
|
|
master_wstrb <= _T_111 @[ahb_to_axi4.scala 106:31]
|
|
node _T_112 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 112:80]
|
|
node _T_113 = and(ahb_hresp_q, _T_112) @[ahb_to_axi4.scala 112:78]
|
|
node _T_114 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 112:98]
|
|
node _T_115 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 112:124]
|
|
node _T_116 = or(_T_114, _T_115) @[ahb_to_axi4.scala 112:111]
|
|
node _T_117 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 112:149]
|
|
node _T_118 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 112:168]
|
|
node _T_119 = or(_T_117, _T_118) @[ahb_to_axi4.scala 112:156]
|
|
node _T_120 = eq(_T_119, UInt<1>("h00")) @[ahb_to_axi4.scala 112:137]
|
|
node _T_121 = and(_T_116, _T_120) @[ahb_to_axi4.scala 112:135]
|
|
node _T_122 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 112:181]
|
|
node _T_123 = and(_T_121, _T_122) @[ahb_to_axi4.scala 112:179]
|
|
node _T_124 = mux(io.ahb.sig.in.hresp, _T_113, _T_123) @[ahb_to_axi4.scala 112:44]
|
|
io.ahb.sig.in.hready <= _T_124 @[ahb_to_axi4.scala 112:38]
|
|
node _T_125 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 113:50]
|
|
io.ahb.sig.in.hrdata <= _T_125 @[ahb_to_axi4.scala 113:38]
|
|
node _T_126 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 114:55]
|
|
node _T_127 = neq(_T_126, UInt<1>("h00")) @[ahb_to_axi4.scala 114:61]
|
|
node _T_128 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 114:83]
|
|
node _T_129 = and(_T_127, _T_128) @[ahb_to_axi4.scala 114:70]
|
|
node _T_130 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 115:26]
|
|
node _T_131 = eq(_T_130, UInt<1>("h00")) @[ahb_to_axi4.scala 115:7]
|
|
node _T_132 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 116:46]
|
|
node _T_133 = or(ahb_addr_in_iccm, _T_132) @[ahb_to_axi4.scala 116:26]
|
|
node _T_134 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:80]
|
|
node _T_135 = eq(_T_134, UInt<2>("h02")) @[ahb_to_axi4.scala 116:86]
|
|
node _T_136 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:109]
|
|
node _T_137 = eq(_T_136, UInt<2>("h03")) @[ahb_to_axi4.scala 116:115]
|
|
node _T_138 = or(_T_135, _T_137) @[ahb_to_axi4.scala 116:95]
|
|
node _T_139 = eq(_T_138, UInt<1>("h00")) @[ahb_to_axi4.scala 116:66]
|
|
node _T_140 = and(_T_133, _T_139) @[ahb_to_axi4.scala 116:64]
|
|
node _T_141 = or(_T_131, _T_140) @[ahb_to_axi4.scala 115:47]
|
|
node _T_142 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 117:20]
|
|
node _T_143 = eq(_T_142, UInt<1>("h01")) @[ahb_to_axi4.scala 117:26]
|
|
node _T_144 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 117:48]
|
|
node _T_145 = and(_T_143, _T_144) @[ahb_to_axi4.scala 117:35]
|
|
node _T_146 = or(_T_141, _T_145) @[ahb_to_axi4.scala 116:126]
|
|
node _T_147 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 118:20]
|
|
node _T_148 = eq(_T_147, UInt<2>("h02")) @[ahb_to_axi4.scala 118:26]
|
|
node _T_149 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 118:49]
|
|
node _T_150 = orr(_T_149) @[ahb_to_axi4.scala 118:56]
|
|
node _T_151 = and(_T_148, _T_150) @[ahb_to_axi4.scala 118:35]
|
|
node _T_152 = or(_T_146, _T_151) @[ahb_to_axi4.scala 117:55]
|
|
node _T_153 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 119:20]
|
|
node _T_154 = eq(_T_153, UInt<2>("h03")) @[ahb_to_axi4.scala 119:26]
|
|
node _T_155 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 119:49]
|
|
node _T_156 = orr(_T_155) @[ahb_to_axi4.scala 119:56]
|
|
node _T_157 = and(_T_154, _T_156) @[ahb_to_axi4.scala 119:35]
|
|
node _T_158 = or(_T_152, _T_157) @[ahb_to_axi4.scala 118:61]
|
|
node _T_159 = and(_T_129, _T_158) @[ahb_to_axi4.scala 114:94]
|
|
node _T_160 = or(_T_159, buf_read_error) @[ahb_to_axi4.scala 119:63]
|
|
node _T_161 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 121:20]
|
|
node _T_162 = and(ahb_hresp_q, _T_161) @[ahb_to_axi4.scala 121:18]
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node _T_163 = or(_T_160, _T_162) @[ahb_to_axi4.scala 120:20]
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io.ahb.sig.in.hresp <= _T_163 @[ahb_to_axi4.scala 114:38]
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node _T_164 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 124:47]
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io.axi.aw.valid <= _T_164 @[ahb_to_axi4.scala 124:33]
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io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 125:33]
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io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 126:33]
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node _T_165 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 127:59]
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node _T_166 = cat(UInt<1>("h00"), _T_165) @[Cat.scala 29:58]
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io.axi.aw.bits.size <= _T_166 @[ahb_to_axi4.scala 127:33]
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node _T_167 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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io.axi.aw.bits.prot <= _T_167 @[ahb_to_axi4.scala 128:33]
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node _T_168 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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io.axi.aw.bits.len <= _T_168 @[ahb_to_axi4.scala 129:33]
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io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 130:33]
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node _T_169 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 132:47]
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io.axi.w.valid <= _T_169 @[ahb_to_axi4.scala 132:33]
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io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 133:33]
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io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 134:33]
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io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 135:33]
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io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 137:33]
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node _T_170 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 139:49]
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node _T_171 = and(cmdbuf_vld, _T_170) @[ahb_to_axi4.scala 139:47]
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io.axi.ar.valid <= _T_171 @[ahb_to_axi4.scala 139:33]
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io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 140:33]
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io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 141:33]
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node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 142:59]
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node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58]
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io.axi.ar.bits.size <= _T_173 @[ahb_to_axi4.scala 142:33]
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node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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io.axi.ar.bits.prot <= _T_174 @[ahb_to_axi4.scala 143:33]
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node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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io.axi.ar.bits.len <= _T_175 @[ahb_to_axi4.scala 144:33]
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io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 145:33]
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io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 147:28]
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