114 lines
3.3 KiB
JSON
114 lines
3.3 KiB
JSON
[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"axi4_to_ahb.gated_latch",
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"resourceId":"/vsrc/gated_latch.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"axi4_to_ahb"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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] |