88 lines
1.8 KiB
Verilog
88 lines
1.8 KiB
Verilog
module reg1(
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input clock,
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input reset,
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input io_in,
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output io_out
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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`endif // RANDOMIZE_REG_INIT
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reg _T; // @[GCD.scala 32:20]
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assign io_out = _T; // @[GCD.scala 32:10]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {1{`RANDOM}};
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_T = _RAND_0[0:0];
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin
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_T = 1'h0;
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end
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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_T <= 1'h0;
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end else begin
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_T <= io_in;
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end
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end
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endmodule
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module top(
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input clock,
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input reset,
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input io_in,
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output io_out
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);
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wire r0_clock; // @[GCD.scala 41:18]
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wire r0_reset; // @[GCD.scala 41:18]
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wire r0_io_in; // @[GCD.scala 41:18]
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wire r0_io_out; // @[GCD.scala 41:18]
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reg1 r0 ( // @[GCD.scala 41:18]
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.clock(r0_clock),
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.reset(r0_reset),
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.io_in(r0_io_in),
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.io_out(r0_io_out)
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);
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assign io_out = r0_io_out; // @[GCD.scala 42:8]
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assign r0_clock = clock;
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assign r0_reset = ~reset; // @[GCD.scala 43:12]
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assign r0_io_in = io_in; // @[GCD.scala 42:8]
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endmodule
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