202 lines
5.4 KiB
Systemverilog
202 lines
5.4 KiB
Systemverilog
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// connects LSI master to external AXI slave and DMA slave
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module axi_lsu_dma_bridge
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#(
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parameter M_ID_WIDTH = 8,
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parameter S0_ID_WIDTH = 8
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)
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(
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input clk,
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input reset_l,
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// master read bus
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input m_arvalid,
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input [M_ID_WIDTH-1:0] m_arid,
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input[31:0] m_araddr,
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output m_arready,
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output m_rvalid,
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input m_rready,
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output [63:0] m_rdata,
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output [M_ID_WIDTH-1:0] m_rid,
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output [1:0] m_rresp,
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output m_rlast,
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// master write bus
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input m_awvalid,
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input [M_ID_WIDTH-1:0] m_awid,
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input[31:0] m_awaddr,
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output m_awready,
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input m_wvalid,
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output m_wready,
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output[1:0] m_bresp,
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output m_bvalid,
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output[M_ID_WIDTH-1:0] m_bid,
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input m_bready,
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// slave 0 if general ext memory
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output s0_arvalid,
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input s0_arready,
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input s0_rvalid,
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input[S0_ID_WIDTH-1:0] s0_rid,
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input[1:0] s0_rresp,
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input[63:0] s0_rdata,
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input s0_rlast,
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output s0_rready,
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output s0_awvalid,
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input s0_awready,
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output s0_wvalid,
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input s0_wready,
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input[1:0] s0_bresp,
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input s0_bvalid,
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input[S0_ID_WIDTH-1:0] s0_bid,
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output s0_bready,
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// slave 1 if DMA port
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output s1_arvalid,
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input s1_arready,
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input s1_rvalid,
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input[1:0] s1_rresp,
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input[63:0] s1_rdata,
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input s1_rlast,
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output s1_rready,
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output s1_awvalid,
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input s1_awready,
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output s1_wvalid,
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input s1_wready,
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input[1:0] s1_bresp,
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input s1_bvalid,
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output s1_bready
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);
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parameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs
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localparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);
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bit[31:0] iccm_real_base_addr = `RV_ICCM_SADR ;
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wire ar_slave_select;
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wire aw_slave_select;
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wire w_slave_select;
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wire rresp_select;
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wire bresp_select;
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wire ar_iccm_select;
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wire aw_iccm_select;
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reg [1:0] wsel_iptr, wsel_optr;
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reg [2:0] wsel_count;
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reg [3:0] wsel;
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reg [M_ID_WIDTH-1:0] arid [1<<IDFIFOSZ];
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reg [M_ID_WIDTH-1:0] awid [1<<IDFIFOSZ];
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reg [IDFIFOSZ-1:0] arid_cnt;
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reg [IDFIFOSZ-1:0] awid_cnt;
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reg [IDFIFOSZ-1:0] rid_cnt;
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reg [IDFIFOSZ-1:0] bid_cnt;
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// 1 select slave 1; 0 - slave 0
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assign ar_slave_select = ar_iccm_select;
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assign aw_slave_select = aw_iccm_select;
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assign ar_iccm_select = m_araddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
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assign aw_iccm_select = m_awaddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
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assign s0_arvalid = m_arvalid & ~ar_slave_select;
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assign s1_arvalid = m_arvalid & ar_slave_select;
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assign m_arready = ar_slave_select ? s1_arready : s0_arready;
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assign s0_awvalid = m_awvalid & ~aw_slave_select;
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assign s1_awvalid = m_awvalid & aw_slave_select;
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assign m_awready = aw_slave_select ? s1_awready : s0_awready;
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assign s0_wvalid = m_wvalid & ~w_slave_select;
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assign s1_wvalid = m_wvalid & w_slave_select;
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assign m_wready = w_slave_select ? s1_wready : s0_wready;
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assign w_slave_select = (wsel_count == 0 || wsel_count[2]) ? aw_slave_select : wsel[wsel_optr];
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assign m_rvalid = s0_rvalid | s1_rvalid;
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assign s0_rready = m_rready & ~rresp_select;
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assign s1_rready = m_rready & rresp_select;
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assign m_rdata = rresp_select ? s1_rdata : s0_rdata;
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assign m_rresp = rresp_select ? s1_rresp : s0_rresp;
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assign m_rid = rresp_select ? arid[rid_cnt] : s0_rid;
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assign m_rlast = rresp_select ? s1_rlast : s0_rlast;
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assign rresp_select = s1_rvalid & ~s0_rvalid;
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assign m_bvalid = s0_bvalid | s1_bvalid;
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assign s0_bready = m_bready & ~bresp_select;
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assign s1_bready = m_bready & bresp_select;
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assign m_bid = bresp_select ? awid[bid_cnt] : s0_bid;
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assign m_bresp = bresp_select ? s1_bresp : s0_bresp;
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assign bresp_select = s1_bvalid & ~s0_bvalid;
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// W-channel select fifo
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always @ (posedge clk or negedge reset_l)
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if(!reset_l) begin
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wsel_count <= '0;
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wsel_iptr <= '0;
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wsel_optr <= '0;
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end
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else begin
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if(m_awvalid & m_awready) begin
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wsel[wsel_iptr] <= aw_slave_select;
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if(!(m_wready & m_wvalid )) wsel_count <= wsel_count + 1;
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wsel_iptr <= wsel_iptr + 1;
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end
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if(m_wvalid & m_wready) begin
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if(!(m_awready & m_awvalid ) ) wsel_count <= wsel_count - 1;
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wsel_optr <= wsel_optr + 1;
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end
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end
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// id replacement for narrow ID slave
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always @ (posedge clk or negedge reset_l)
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if(!reset_l) begin
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arid_cnt <= '0;
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rid_cnt <= '0;
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end
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else begin
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if(ar_slave_select & m_arready & m_arvalid) begin
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arid[arid_cnt] <= m_arid;
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arid_cnt <= arid_cnt + 1;
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end
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if(rresp_select & m_rready & m_rvalid) begin
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rid_cnt <= rid_cnt + 1;
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end
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end
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always @ (posedge clk or negedge reset_l)
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if(!reset_l) begin
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awid_cnt <= '0;
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bid_cnt <= '0;
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end
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else begin
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if(aw_slave_select & m_awready & m_awvalid) begin
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awid[awid_cnt] <= m_awid;
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awid_cnt <= awid_cnt + 1;
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end
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if(bresp_select & m_bready & m_bvalid) begin
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bid_cnt <= bid_cnt + 1;
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end
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end
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endmodule
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