383 lines
12 KiB
Verilog
383 lines
12 KiB
Verilog
module rvjtag_tap(
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input clock,
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input reset,
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input io_trst,
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input io_tck,
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input io_tms,
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input io_tdi,
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output io_dmi_reset,
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output io_dmi_hard_reset,
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input [1:0] io_rd_status,
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input [1:0] io_dmi_stat,
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input [2:0] io_idle,
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input [3:0] io_version,
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input [30:0] io_jtag_id,
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input [31:0] io_rd_data,
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output io_tdo,
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output io_tdoEnable,
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output io_wr_en,
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output io_rd_en,
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output [31:0] io_wr_data
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [63:0] _RAND_0;
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_2;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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reg [31:0] _RAND_5;
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reg [63:0] _RAND_6;
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`endif // RANDOMIZE_REG_INIT
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reg [40:0] sr; // @[rvjtag_tap.scala 32:55]
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reg [3:0] state; // @[rvjtag_tap.scala 39:57]
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wire jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30]
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wire _T_2 = 4'h1 == state; // @[Conditional.scala 37:30]
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wire _T_4 = 4'h2 == state; // @[Conditional.scala 37:30]
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wire _T_6 = 4'h3 == state; // @[Conditional.scala 37:30]
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wire _T_8 = 4'h4 == state; // @[Conditional.scala 37:30]
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wire _T_10 = 4'h5 == state; // @[Conditional.scala 37:30]
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wire _T_12 = 4'h6 == state; // @[Conditional.scala 37:30]
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wire _T_14 = 4'h7 == state; // @[Conditional.scala 37:30]
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wire _T_16 = 4'h8 == state; // @[Conditional.scala 37:30]
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wire _T_18 = 4'h9 == state; // @[Conditional.scala 37:30]
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wire _T_20 = 4'ha == state; // @[Conditional.scala 37:30]
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wire _T_22 = 4'hb == state; // @[Conditional.scala 37:30]
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wire _T_24 = 4'hc == state; // @[Conditional.scala 37:30]
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wire _T_26 = 4'hd == state; // @[Conditional.scala 37:30]
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wire _T_28 = 4'he == state; // @[Conditional.scala 37:30]
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wire _T_30 = 4'hf == state; // @[Conditional.scala 37:30]
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wire _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67]
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wire _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
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wire _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67]
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wire _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
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wire _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67]
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wire _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
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wire _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67]
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wire _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
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wire _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67]
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wire _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
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wire _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
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wire _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
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wire _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67]
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wire _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
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wire _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
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wire _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
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wire _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
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wire _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
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wire _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
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wire _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
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wire _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
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wire _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
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wire _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
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wire _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
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wire _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
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wire _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
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wire _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
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wire _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67]
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wire _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67]
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wire _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
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wire _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
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wire _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
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wire _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
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wire _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67]
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wire _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
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wire _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
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wire _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
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wire _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
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wire _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
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wire _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
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wire _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
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wire _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
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wire _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
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wire _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
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wire _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
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wire capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
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wire shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58]
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wire update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
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wire capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58]
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wire shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
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wire update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
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wire _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98]
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reg [4:0] ir; // @[rvjtag_tap.scala 85:52]
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wire devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18]
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wire _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22]
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wire _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32]
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wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58]
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wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58]
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wire _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32]
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wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58]
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wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58]
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wire [40:0] _T_66 = {26'h0,io_idle,io_dmi_stat,6'h7,io_version}; // @[Cat.scala 29:58]
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wire [40:0] _T_70 = {7'h0,io_rd_data,io_rd_status}; // @[Cat.scala 29:58]
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wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58]
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wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58]
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reg _T_83; // @[rvjtag_tap.scala 106:37]
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wire _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82]
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reg _T_89; // @[rvjtag_tap.scala 108:67]
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reg _T_95; // @[rvjtag_tap.scala 109:62]
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wire _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67]
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reg [40:0] dr; // @[rvjtag_tap.scala 111:52]
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wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58]
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assign io_dmi_reset = _T_95; // @[rvjtag_tap.scala 109:52]
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assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57]
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assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28]
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assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16]
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assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14]
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assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14]
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assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {2{`RANDOM}};
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sr = _RAND_0[40:0];
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_RAND_1 = {1{`RANDOM}};
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state = _RAND_1[3:0];
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_RAND_2 = {1{`RANDOM}};
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ir = _RAND_2[4:0];
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_RAND_3 = {1{`RANDOM}};
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_T_83 = _RAND_3[0:0];
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_RAND_4 = {1{`RANDOM}};
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_T_89 = _RAND_4[0:0];
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_RAND_5 = {1{`RANDOM}};
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_T_95 = _RAND_5[0:0];
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_RAND_6 = {2{`RANDOM}};
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dr = _RAND_6[40:0];
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`endif // RANDOMIZE_REG_INIT
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if (io_trst) begin
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sr = 41'h0;
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end
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if (io_trst) begin
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state = 4'h0;
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end
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if (io_trst) begin
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ir = 5'h1;
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end
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if (reset) begin
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_T_83 = 1'h0;
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end
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if (io_trst) begin
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_T_89 = 1'h0;
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end
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if (io_trst) begin
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_T_95 = 1'h0;
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end
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if (io_trst) begin
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dr = 41'h0;
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end
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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sr <= 41'h0;
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end else if (shift_dr) begin
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if (dr_en[1]) begin
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sr <= _T_49;
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end else if (_T_53) begin
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sr <= _T_57;
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end else begin
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sr <= _T_59;
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end
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end else if (capture_dr) begin
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if (dr_en[0]) begin
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sr <= _T_66;
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end else if (dr_en[1]) begin
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sr <= _T_70;
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end else if (devid_sel) begin
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sr <= _T_73;
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end else begin
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sr <= 41'h0;
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end
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end else if (shift_ir) begin
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sr <= _T_78;
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end else if (capture_ir) begin
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sr <= 41'h1;
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end else begin
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sr <= 41'h0;
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end
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end
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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state <= 4'h0;
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end else if (jtag_reset) begin
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if (io_tms) begin
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state <= 4'h0;
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end else begin
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state <= 4'h1;
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end
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end else if (_T_2) begin
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if (io_tms) begin
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state <= 4'h2;
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end else begin
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state <= 4'h1;
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end
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end else if (_T_4) begin
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if (io_tms) begin
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state <= 4'h9;
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end else begin
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state <= 4'h3;
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end
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end else if (_T_6) begin
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if (io_tms) begin
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state <= 4'h5;
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end else begin
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state <= 4'h4;
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end
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end else if (_T_8) begin
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if (io_tms) begin
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state <= 4'h5;
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end else begin
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state <= 4'h4;
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end
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end else if (_T_10) begin
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if (io_tms) begin
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state <= 4'h8;
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end else begin
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state <= 4'h6;
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end
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end else if (_T_12) begin
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if (io_tms) begin
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state <= 4'h7;
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end else begin
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state <= 4'h6;
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end
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end else if (_T_14) begin
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if (io_tms) begin
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state <= 4'h8;
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end else begin
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state <= 4'h4;
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end
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end else if (_T_16) begin
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if (io_tms) begin
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state <= 4'h2;
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end else begin
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state <= 4'h1;
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end
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end else if (_T_18) begin
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if (io_tms) begin
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state <= 4'h0;
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end else begin
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state <= 4'ha;
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end
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end else if (_T_20) begin
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if (io_tms) begin
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state <= 4'hc;
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end else begin
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state <= 4'hb;
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end
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end else if (_T_22) begin
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if (io_tms) begin
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state <= 4'hc;
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end else begin
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state <= 4'hb;
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end
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end else if (_T_24) begin
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if (io_tms) begin
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state <= 4'hf;
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end else begin
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state <= 4'hd;
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end
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end else if (_T_26) begin
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if (io_tms) begin
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state <= 4'he;
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end else begin
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state <= 4'hd;
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end
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end else if (_T_28) begin
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if (io_tms) begin
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state <= 4'hf;
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end else begin
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state <= 4'hb;
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end
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end else if (_T_30) begin
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if (io_tms) begin
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state <= 4'h2;
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end else begin
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state <= 4'h1;
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end
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end else begin
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state <= 4'h0;
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end
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end
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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ir <= 5'h1;
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end else if (jtag_reset) begin
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ir <= 5'h1;
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end else if (update_ir) begin
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if (_T_34) begin
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ir <= 5'h1f;
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end else begin
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ir <= sr[4:0];
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end
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end else begin
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ir <= 5'h0;
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end
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end
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always @(posedge io_tck or posedge reset) begin
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if (reset) begin
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_T_83 <= 1'h0;
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end else begin
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_T_83 <= sr[0];
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end
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end
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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_T_89 <= 1'h0;
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end else begin
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_T_89 <= _T_86 & sr[17];
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end
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end
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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_T_95 <= 1'h0;
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end else begin
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_T_95 <= _T_86 & sr[16];
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end
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end
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always @(posedge io_tck or posedge io_trst) begin
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if (io_trst) begin
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dr <= 41'h0;
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end else if (_T_98) begin
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dr <= sr;
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end else begin
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dr <= _T_100;
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end
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end
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endmodule
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