29 lines
826 B
Plaintext
29 lines
826 B
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit rvdff :
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extmodule rvdff_verilog :
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input in : UInt<16>
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input clk : Clock
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input reset : UInt<1>
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output out : UInt<16>
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defname = rvdff_verilog
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parameter DATA_WIDTH = 32
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parameter MODE = "Sequential"
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parameter RESET = "Asynchronous"
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module rvdff :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>}
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inst m of rvdff_verilog @[GCD.scala 41:17]
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m.out is invalid
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m.reset is invalid
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m.clk is invalid
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m.in is invalid
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io.out <= m.out @[GCD.scala 43:8]
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m.reset <= io.reset @[GCD.scala 43:8]
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m.clk <= io.clk @[GCD.scala 43:8]
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m.in <= io.in @[GCD.scala 43:8]
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