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quasar/el2_ifu_bp_ctl.fir

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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_bp_ctl :
module el2_ifu_bp_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<32>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<7>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<7>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>}
io.ifu_bp_hit_taken_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 42:25]
io.ifu_bp_btb_target_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 43:26]
io.ifu_bp_inst_mask_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 44:25]
io.ifu_bp_fghr_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 45:20]
io.ifu_bp_way_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 46:19]
io.ifu_bp_ret_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 47:19]
io.ifu_bp_hist1_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 48:21]
io.ifu_bp_hist0_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 49:21]
io.ifu_bp_pc4_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 50:19]
io.ifu_bp_valid_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 51:21]
io.ifu_bp_poffset_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 52:23]
wire leak_one_f : UInt<1>
leak_one_f <= UInt<1>("h00")
node _T = not(leak_one_f) @[el2_ifu_bp_ctl.scala 67:43]
node exu_mp_valid = and(io.exu_mp_pkt.misp, _T) @[el2_ifu_bp_ctl.scala 67:41]
wire fetch_rd_tag_p1_f : UInt<5>
fetch_rd_tag_p1_f <= UInt<1>("h00")
wire fetch_rd_tag_f : UInt<5>
fetch_rd_tag_f <= UInt<1>("h00")
wire bht_dir_f : UInt<2>
bht_dir_f <= UInt<1>("h00")
wire dec_tlu_error_wb : UInt<1>
dec_tlu_error_wb <= UInt<1>("h00")
wire btb_error_addr_wb : UInt<7>
btb_error_addr_wb <= UInt<1>("h00")
wire btb_bank0_rd_data_way0_f : UInt<22>
btb_bank0_rd_data_way0_f <= UInt<1>("h00")
wire btb_bank0_rd_data_way1_f : UInt<22>
btb_bank0_rd_data_way1_f <= UInt<1>("h00")
wire btb_bank0_rd_data_way0_p1_f : UInt<22>
btb_bank0_rd_data_way0_p1_f <= UInt<1>("h00")
wire btb_bank0_rd_data_way1_p1_f : UInt<22>
btb_bank0_rd_data_way1_p1_f <= UInt<1>("h00")
wire eoc_mask : UInt<1>
eoc_mask <= UInt<1>("h00")
wire btb_lru_b0_f : UInt<256>
btb_lru_b0_f <= UInt<1>("h00")
wire dec_tlu_way_wb : UInt<1>
dec_tlu_way_wb <= UInt<1>("h00")
node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12]
node _T_2 = bits(io.ifc_fetch_addr_f, 17, 10) @[el2_lib.scala 182:46]
node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42]
node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80]
node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76]
node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 106:45]
node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 106:45]
node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12]
node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46]
node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42]
node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80]
node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76]
node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:33]
node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 111:23]
node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:46]
node btb_sel_f = cat(_T_11, _T_12) @[Cat.scala 29:58]
node _T_13 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:46]
node _T_14 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:70]
node _T_15 = not(_T_14) @[el2_ifu_bp_ctl.scala 114:50]
node fetch_start_f = cat(_T_13, _T_15) @[Cat.scala 29:58]
node _T_16 = eq(btb_error_addr_wb, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 117:72]
node branch_error_collision_f = and(dec_tlu_error_wb, _T_16) @[el2_ifu_bp_ctl.scala 117:51]
node _T_17 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 118:75]
node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 118:54]
node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 121:63]
node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 122:69]
node _T_18 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 125:46]
node _T_19 = and(_T_18, exu_mp_valid) @[el2_ifu_bp_ctl.scala 125:66]
node _T_20 = and(_T_19, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 125:81]
node _T_21 = eq(io.exu_mp_index, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 125:117]
node fetch_mp_collision_f = and(_T_20, _T_21) @[el2_ifu_bp_ctl.scala 125:102]
node _T_22 = eq(io.exu_mp_btag, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 126:49]
node _T_23 = and(_T_22, exu_mp_valid) @[el2_ifu_bp_ctl.scala 126:72]
node _T_24 = and(_T_23, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 126:87]
node _T_25 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 126:123]
node fetch_mp_collision_p1_f = and(_T_24, _T_25) @[el2_ifu_bp_ctl.scala 126:108]
reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 128:30]
leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 128:30]
reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 129:33]
dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 129:33]
reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 130:29]
exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 130:29]
reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 131:35]
exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 131:35]
node _T_26 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:47]
node _T_27 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:93]
node _T_28 = or(_T_26, _T_27) @[el2_ifu_bp_ctl.scala 133:76]
leak_one_f <= _T_28 @[el2_ifu_bp_ctl.scala 133:14]
node _T_29 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 136:50]
node _T_30 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[el2_ifu_bp_ctl.scala 136:82]
node _T_31 = eq(_T_30, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 136:97]
node _T_32 = and(_T_29, _T_31) @[el2_ifu_bp_ctl.scala 136:55]
node _T_33 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 137:22]
node _T_34 = not(_T_33) @[el2_ifu_bp_ctl.scala 137:3]
node _T_35 = and(_T_32, _T_34) @[el2_ifu_bp_ctl.scala 136:117]
node _T_36 = and(_T_35, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 137:54]
node _T_37 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 137:77]
node tag_match_way0_f = and(_T_36, _T_37) @[el2_ifu_bp_ctl.scala 137:75]
node _T_38 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[el2_ifu_bp_ctl.scala 139:50]
node _T_39 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[el2_ifu_bp_ctl.scala 139:82]
node _T_40 = eq(_T_39, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 139:97]
node _T_41 = and(_T_38, _T_40) @[el2_ifu_bp_ctl.scala 139:55]
node _T_42 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 140:22]
node _T_43 = not(_T_42) @[el2_ifu_bp_ctl.scala 140:3]
node _T_44 = and(_T_41, _T_43) @[el2_ifu_bp_ctl.scala 139:117]
node _T_45 = and(_T_44, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 140:54]
node _T_46 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 140:77]
node tag_match_way1_f = and(_T_45, _T_46) @[el2_ifu_bp_ctl.scala 140:75]
node _T_47 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 142:56]
node _T_48 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 142:91]
node _T_49 = eq(_T_48, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 142:106]
node _T_50 = and(_T_47, _T_49) @[el2_ifu_bp_ctl.scala 142:61]
node _T_51 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 143:24]
node _T_52 = not(_T_51) @[el2_ifu_bp_ctl.scala 143:5]
node _T_53 = and(_T_50, _T_52) @[el2_ifu_bp_ctl.scala 142:129]
node _T_54 = and(_T_53, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 143:56]
node _T_55 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 143:79]
node tag_match_way0_p1_f = and(_T_54, _T_55) @[el2_ifu_bp_ctl.scala 143:77]
node _T_56 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 145:56]
node _T_57 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 145:91]
node _T_58 = eq(_T_57, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 145:106]
node _T_59 = and(_T_56, _T_58) @[el2_ifu_bp_ctl.scala 145:61]
node _T_60 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 146:24]
node _T_61 = not(_T_60) @[el2_ifu_bp_ctl.scala 146:5]
node _T_62 = and(_T_59, _T_61) @[el2_ifu_bp_ctl.scala 145:129]
node _T_63 = and(_T_62, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 146:56]
node _T_64 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 146:79]
node tag_match_way1_p1_f = and(_T_63, _T_64) @[el2_ifu_bp_ctl.scala 146:77]
node _T_65 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 149:84]
node _T_66 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 149:117]
node _T_67 = xor(_T_65, _T_66) @[el2_ifu_bp_ctl.scala 149:91]
node _T_68 = and(tag_match_way0_f, _T_67) @[el2_ifu_bp_ctl.scala 149:56]
node _T_69 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 150:50]
node _T_70 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 150:83]
node _T_71 = xor(_T_69, _T_70) @[el2_ifu_bp_ctl.scala 150:57]
node _T_72 = not(_T_71) @[el2_ifu_bp_ctl.scala 150:24]
node _T_73 = and(tag_match_way0_f, _T_72) @[el2_ifu_bp_ctl.scala 150:22]
node tag_match_way0_expanded_f = cat(_T_68, _T_73) @[Cat.scala 29:58]
node _T_74 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 152:84]
node _T_75 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 152:117]
node _T_76 = xor(_T_74, _T_75) @[el2_ifu_bp_ctl.scala 152:91]
node _T_77 = and(tag_match_way1_f, _T_76) @[el2_ifu_bp_ctl.scala 152:56]
node _T_78 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 153:50]
node _T_79 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 153:83]
node _T_80 = xor(_T_78, _T_79) @[el2_ifu_bp_ctl.scala 153:57]
node _T_81 = not(_T_80) @[el2_ifu_bp_ctl.scala 153:24]
node _T_82 = and(tag_match_way1_f, _T_81) @[el2_ifu_bp_ctl.scala 153:22]
node tag_match_way1_expanded_f = cat(_T_77, _T_82) @[Cat.scala 29:58]
node _T_83 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 156:93]
node _T_84 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 156:129]
node _T_85 = xor(_T_83, _T_84) @[el2_ifu_bp_ctl.scala 156:100]
node _T_86 = and(tag_match_way0_p1_f, _T_85) @[el2_ifu_bp_ctl.scala 156:62]
node _T_87 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 157:56]
node _T_88 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 157:92]
node _T_89 = xor(_T_87, _T_88) @[el2_ifu_bp_ctl.scala 157:63]
node _T_90 = not(_T_89) @[el2_ifu_bp_ctl.scala 157:27]
node _T_91 = and(tag_match_way0_p1_f, _T_90) @[el2_ifu_bp_ctl.scala 157:25]
node tag_match_way0_expanded_p1_f = cat(_T_86, _T_91) @[Cat.scala 29:58]
node _T_92 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 159:93]
node _T_93 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 159:129]
node _T_94 = xor(_T_92, _T_93) @[el2_ifu_bp_ctl.scala 159:100]
node _T_95 = and(tag_match_way1_p1_f, _T_94) @[el2_ifu_bp_ctl.scala 159:62]
node _T_96 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 160:56]
node _T_97 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 160:92]
node _T_98 = xor(_T_96, _T_97) @[el2_ifu_bp_ctl.scala 160:63]
node _T_99 = not(_T_98) @[el2_ifu_bp_ctl.scala 160:27]
node _T_100 = and(tag_match_way1_p1_f, _T_99) @[el2_ifu_bp_ctl.scala 160:25]
node tag_match_way1_expanded_p1_f = cat(_T_95, _T_100) @[Cat.scala 29:58]
node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[el2_ifu_bp_ctl.scala 162:44]
node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[el2_ifu_bp_ctl.scala 164:50]
node _T_101 = bits(tag_match_way0_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 167:65]
node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_bp_ctl.scala 167:69]
node _T_103 = bits(tag_match_way1_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 168:30]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_bp_ctl.scala 168:34]
node _T_105 = mux(_T_102, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_106 = mux(_T_104, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_107 = or(_T_105, _T_106) @[Mux.scala 27:72]
wire btb_bank0e_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_bank0e_rd_data_f <= _T_107 @[Mux.scala 27:72]
node _T_108 = bits(tag_match_way0_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 170:65]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_bp_ctl.scala 170:69]
node _T_110 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 171:30]
node _T_111 = bits(_T_110, 0, 0) @[el2_ifu_bp_ctl.scala 171:34]
node _T_112 = mux(_T_109, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_113 = mux(_T_111, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_114 = or(_T_112, _T_113) @[Mux.scala 27:72]
wire btb_bank0o_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_bank0o_rd_data_f <= _T_114 @[Mux.scala 27:72]
node _T_115 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 173:71]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_bp_ctl.scala 173:75]
node _T_117 = bits(tag_match_way1_expanded_p1_f, 1, 1) @[el2_ifu_bp_ctl.scala 174:33]
node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_bp_ctl.scala 174:37]
node _T_119 = mux(_T_116, btb_bank0_rd_data_way0_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_118, btb_bank0_rd_data_way1_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = or(_T_119, _T_120) @[Mux.scala 27:72]
wire btb_bank0e_rd_data_p1_f : UInt<22> @[Mux.scala 27:72]
btb_bank0e_rd_data_p1_f <= _T_121 @[Mux.scala 27:72]
node _T_122 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 177:60]
node _T_123 = not(_T_122) @[el2_ifu_bp_ctl.scala 177:40]
node _T_124 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:60]
node _T_125 = mux(_T_123, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = mux(_T_124, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72]
wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_vbank0_rd_data_f <= _T_127 @[Mux.scala 27:72]
node _T_128 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 180:60]
node _T_129 = not(_T_128) @[el2_ifu_bp_ctl.scala 180:40]
node _T_130 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 181:60]
node _T_131 = mux(_T_129, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_132 = mux(_T_130, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_133 = or(_T_131, _T_132) @[Mux.scala 27:72]
wire btb_vbank1_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_vbank1_rd_data_f <= _T_133 @[Mux.scala 27:72]
node mp_wrindex_dec = dshl(UInt<1>("h00"), io.exu_mp_index) @[el2_ifu_bp_ctl.scala 184:38]
node fetch_wrindex_dec = dshl(UInt<1>("h00"), btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 185:41]
node fetch_wrindex_p1_dec = dshl(UInt<1>("h00"), btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 186:44]
node _T_134 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_135 = mux(_T_134, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node mp_wrlru_b0 = and(mp_wrindex_dec, _T_135) @[el2_ifu_bp_ctl.scala 187:36]
node _T_136 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 189:49]
node _T_137 = bits(_T_136, 0, 0) @[el2_ifu_bp_ctl.scala 189:53]
node _T_138 = not(_T_137) @[el2_ifu_bp_ctl.scala 189:29]
node _T_139 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:24]
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_bp_ctl.scala 190:28]
node _T_141 = bits(wayhit_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 190:51]
node _T_142 = bits(wayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:64]
node _T_143 = cat(_T_141, _T_142) @[Cat.scala 29:58]
node _T_144 = mux(_T_138, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_145 = mux(_T_140, _T_143, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_146 = or(_T_144, _T_145) @[Mux.scala 27:72]
wire _T_147 : UInt<2> @[Mux.scala 27:72]
_T_147 <= _T_146 @[Mux.scala 27:72]
node _T_148 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58]
node bht_valid_f = and(_T_147, _T_148) @[el2_ifu_bp_ctl.scala 190:71]
node _T_149 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 191:38]
node _T_150 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 191:53]
node _T_151 = or(_T_149, _T_150) @[el2_ifu_bp_ctl.scala 191:42]
node _T_152 = and(_T_151, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 191:58]
node _T_153 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 191:81]
node lru_update_valid_f = and(_T_152, _T_153) @[el2_ifu_bp_ctl.scala 191:79]
node _T_154 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
node _T_155 = mux(_T_154, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_155) @[el2_ifu_bp_ctl.scala 193:42]
node _T_156 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
node _T_157 = mux(_T_156, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_157) @[el2_ifu_bp_ctl.scala 194:48]
node _T_158 = not(mp_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:25]
node _T_159 = not(fetch_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:40]
node btb_lru_b0_hold = and(_T_158, _T_159) @[el2_ifu_bp_ctl.scala 196:38]
node _T_160 = bits(io.exu_mp_pkt.way, 0, 0) @[el2_ifu_bp_ctl.scala 200:45]
node _T_161 = not(_T_160) @[el2_ifu_bp_ctl.scala 200:33]
node _T_162 = bits(tag_match_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:22]
node _T_163 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 202:25]
node _T_164 = mux(_T_161, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_165 = mux(_T_162, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_166 = mux(_T_163, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_167 = or(_T_164, _T_165) @[Mux.scala 27:72]
node _T_168 = or(_T_167, _T_166) @[Mux.scala 27:72]
wire _T_169 : UInt<256> @[Mux.scala 27:72]
_T_169 <= _T_168 @[Mux.scala 27:72]
node _T_170 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 202:71]
node btb_lru_b0_ns = or(_T_169, _T_170) @[el2_ifu_bp_ctl.scala 202:53]
node _T_171 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 204:37]
node _T_172 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 204:78]
node _T_173 = orr(_T_172) @[el2_ifu_bp_ctl.scala 204:94]
node btb_lru_rd_f = mux(_T_171, exu_mp_way_f, _T_173) @[el2_ifu_bp_ctl.scala 204:25]
node _T_174 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 205:43]
node _T_175 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 205:87]
node _T_176 = orr(_T_175) @[el2_ifu_bp_ctl.scala 205:103]
node btb_lru_rd_p1_f = mux(_T_174, exu_mp_way_f, _T_176) @[el2_ifu_bp_ctl.scala 205:28]
node _T_177 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 207:53]
node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 207:33]
node _T_179 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
node _T_180 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 208:24]
node _T_181 = bits(_T_180, 0, 0) @[el2_ifu_bp_ctl.scala 208:28]
node _T_182 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
node _T_183 = mux(_T_178, _T_179, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_184 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_185 = or(_T_183, _T_184) @[Mux.scala 27:72]
wire btb_vlru_rd_f : UInt @[Mux.scala 27:72]
btb_vlru_rd_f <= _T_185 @[Mux.scala 27:72]
node _T_186 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 210:66]
node _T_187 = bits(_T_186, 0, 0) @[el2_ifu_bp_ctl.scala 210:70]
node _T_188 = not(_T_187) @[el2_ifu_bp_ctl.scala 210:46]
node _T_189 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 211:24]
node _T_190 = bits(_T_189, 0, 0) @[el2_ifu_bp_ctl.scala 211:28]
node _T_191 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 211:68]
node _T_192 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 211:97]
node _T_193 = cat(_T_191, _T_192) @[Cat.scala 29:58]
node _T_194 = mux(_T_188, tag_match_way1_expanded_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_195 = mux(_T_190, _T_193, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_196 = or(_T_194, _T_195) @[Mux.scala 27:72]
wire tag_match_vway1_expanded_f : UInt<2> @[Mux.scala 27:72]
tag_match_vway1_expanded_f <= _T_196 @[Mux.scala 27:72]
node _T_197 = not(bht_valid_f) @[el2_ifu_bp_ctl.scala 213:47]
node _T_198 = and(_T_197, btb_vlru_rd_f) @[el2_ifu_bp_ctl.scala 213:58]
node way_raw = or(tag_match_vway1_expanded_f, _T_198) @[el2_ifu_bp_ctl.scala 213:44]
node _T_199 = or(io.ifc_fetch_req_f, exu_mp_valid) @[el2_ifu_bp_ctl.scala 215:75]
node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_bp_ctl.scala 215:90]
reg _T_201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_200 : @[Reg.scala 28:19]
_T_201 <= btb_lru_b0_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
btb_lru_b0_f <= _T_201 @[el2_ifu_bp_ctl.scala 215:16]
node _T_202 = bits(io.ifc_fetch_addr_f, 5, 3) @[el2_ifu_bp_ctl.scala 217:37]
node eoc_near = andr(_T_202) @[el2_ifu_bp_ctl.scala 217:62]
node _T_203 = eq(eoc_near, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 218:15]
node _T_204 = bits(io.ifc_fetch_addr_f, 2, 1) @[el2_ifu_bp_ctl.scala 218:47]
node _T_205 = orr(_T_204) @[el2_ifu_bp_ctl.scala 218:56]
node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 218:27]
node _T_207 = or(_T_203, _T_206) @[el2_ifu_bp_ctl.scala 218:25]
eoc_mask <= _T_207 @[el2_ifu_bp_ctl.scala 218:12]
wire btb_sel_data_f : UInt<17>
btb_sel_data_f <= UInt<1>("h00")
wire hist1_raw : UInt<2>
hist1_raw <= UInt<1>("h00")
node btb_rd_tgt_f = bits(btb_sel_data_f, 16, 5) @[el2_ifu_bp_ctl.scala 221:36]
node btb_rd_pc4_f = bits(btb_sel_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 222:36]
node btb_rd_call_f = bits(btb_sel_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 223:37]
node btb_rd_ret_f = bits(btb_sel_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 224:36]
node _T_208 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 226:40]
node _T_209 = bits(_T_208, 0, 0) @[el2_ifu_bp_ctl.scala 226:44]
node _T_210 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 226:76]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_212 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 227:14]
node _T_213 = bits(_T_212, 0, 0) @[el2_ifu_bp_ctl.scala 227:18]
node _T_214 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 227:50]
node _T_215 = cat(_T_214, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_216 = mux(_T_209, _T_211, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_217 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
wire _T_219 : UInt<17> @[Mux.scala 27:72]
_T_219 <= _T_218 @[Mux.scala 27:72]
btb_sel_data_f <= _T_219 @[el2_ifu_bp_ctl.scala 226:18]
node _T_220 = and(bht_valid_f, hist1_raw) @[el2_ifu_bp_ctl.scala 229:39]
node _T_221 = orr(_T_220) @[el2_ifu_bp_ctl.scala 229:52]
node _T_222 = and(_T_221, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 229:56]
node _T_223 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 229:79]
node _T_224 = and(_T_222, _T_223) @[el2_ifu_bp_ctl.scala 229:77]
node _T_225 = not(io.dec_tlu_bpred_disable) @[el2_ifu_bp_ctl.scala 229:96]
node ifu_bp_hit_taken_f = and(_T_224, _T_225) @[el2_ifu_bp_ctl.scala 229:94]
node _T_226 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 231:52]
node _T_227 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 231:81]
node _T_228 = or(_T_226, _T_227) @[el2_ifu_bp_ctl.scala 231:59]
node _T_229 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 232:25]
node _T_230 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 232:54]
node _T_231 = or(_T_229, _T_230) @[el2_ifu_bp_ctl.scala 232:32]
node bht_force_taken_f = cat(_T_228, _T_231) @[Cat.scala 29:58]
wire bht_bank1_rd_data_f : UInt<2>
bht_bank1_rd_data_f <= UInt<1>("h00")
wire bht_bank0_rd_data_f : UInt<2>
bht_bank0_rd_data_f <= UInt<1>("h00")
wire bht_bank0_rd_data_p1_f : UInt<2>
bht_bank0_rd_data_p1_f <= UInt<1>("h00")
node _T_232 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 240:60]
node _T_233 = bits(_T_232, 0, 0) @[el2_ifu_bp_ctl.scala 240:64]
node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 240:40]
node _T_235 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 241:60]
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_bp_ctl.scala 241:64]
node _T_237 = mux(_T_234, bht_bank0_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_238 = mux(_T_236, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_239 = or(_T_237, _T_238) @[Mux.scala 27:72]
wire bht_vbank0_rd_data_f : UInt<2> @[Mux.scala 27:72]
bht_vbank0_rd_data_f <= _T_239 @[Mux.scala 27:72]
node _T_240 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 243:60]
node _T_241 = bits(_T_240, 0, 0) @[el2_ifu_bp_ctl.scala 243:64]
node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 243:40]
node _T_243 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 244:60]
node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_bp_ctl.scala 244:64]
node _T_245 = mux(_T_242, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_246 = mux(_T_244, bht_bank0_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_247 = or(_T_245, _T_246) @[Mux.scala 27:72]
wire bht_vbank1_rd_data_f : UInt<2> @[Mux.scala 27:72]
bht_vbank1_rd_data_f <= _T_247 @[Mux.scala 27:72]
node _T_248 = bits(bht_force_taken_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:38]
node _T_249 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:64]
node _T_250 = or(_T_248, _T_249) @[el2_ifu_bp_ctl.scala 245:42]
node _T_251 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:82]
node _T_252 = and(_T_250, _T_251) @[el2_ifu_bp_ctl.scala 245:69]
node _T_253 = bits(bht_force_taken_f, 0, 0) @[el2_ifu_bp_ctl.scala 246:41]
node _T_254 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 246:67]
node _T_255 = or(_T_253, _T_254) @[el2_ifu_bp_ctl.scala 246:45]
node _T_256 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 246:85]
node _T_257 = and(_T_255, _T_256) @[el2_ifu_bp_ctl.scala 246:72]
node _T_258 = cat(_T_252, _T_257) @[Cat.scala 29:58]
bht_dir_f <= _T_258 @[el2_ifu_bp_ctl.scala 245:13]
node _T_259 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 248:59]
node _T_260 = and(ifu_bp_hit_taken_f, _T_259) @[el2_ifu_bp_ctl.scala 248:48]
node _T_261 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 248:66]
node ifu_bp_inst_mask_f = or(_T_260, _T_261) @[el2_ifu_bp_ctl.scala 248:64]
node _T_262 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 251:60]
node _T_263 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 251:85]
node _T_264 = cat(_T_262, _T_263) @[Cat.scala 29:58]
node _T_265 = or(bht_force_taken_f, _T_264) @[el2_ifu_bp_ctl.scala 251:34]
hist1_raw <= _T_265 @[el2_ifu_bp_ctl.scala 251:13]
node _T_266 = bits(bht_vbank1_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 253:43]
node _T_267 = bits(bht_vbank0_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 253:68]
node hist0_raw = cat(_T_266, _T_267) @[Cat.scala 29:58]
node _T_268 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 255:30]
node _T_269 = bits(btb_vbank1_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 255:56]
node _T_270 = and(_T_268, _T_269) @[el2_ifu_bp_ctl.scala 255:34]
node _T_271 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 256:14]
node _T_272 = bits(btb_vbank0_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 256:40]
node _T_273 = and(_T_271, _T_272) @[el2_ifu_bp_ctl.scala 256:18]
node pc4_raw = cat(_T_270, _T_273) @[Cat.scala 29:58]
node _T_274 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 258:31]
node _T_275 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 258:58]
node _T_276 = not(_T_275) @[el2_ifu_bp_ctl.scala 258:37]
node _T_277 = and(_T_274, _T_276) @[el2_ifu_bp_ctl.scala 258:35]
node _T_278 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 258:87]
node _T_279 = and(_T_277, _T_278) @[el2_ifu_bp_ctl.scala 258:65]
node _T_280 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 259:32]
node _T_281 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 259:59]
node _T_282 = not(_T_281) @[el2_ifu_bp_ctl.scala 259:38]
node _T_283 = and(_T_280, _T_282) @[el2_ifu_bp_ctl.scala 259:36]
node _T_284 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 259:88]
node _T_285 = and(_T_283, _T_284) @[el2_ifu_bp_ctl.scala 259:66]
node pret_raw = cat(_T_279, _T_285) @[Cat.scala 29:58]
node _T_286 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 262:31]
node _T_287 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 262:49]
node num_valids = add(_T_286, _T_287) @[el2_ifu_bp_ctl.scala 262:35]
node _T_288 = and(btb_sel_f, bht_dir_f) @[el2_ifu_bp_ctl.scala 264:28]
node final_h = andr(_T_288) @[el2_ifu_bp_ctl.scala 264:41]
wire fghr : UInt<8>
fghr <= UInt<1>("h00")
node _T_289 = eq(num_valids, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 267:41]
node _T_290 = bits(_T_289, 0, 0) @[el2_ifu_bp_ctl.scala 267:49]
node _T_291 = bits(fghr, 5, 0) @[el2_ifu_bp_ctl.scala 267:65]
node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_293 = cat(_T_292, final_h) @[Cat.scala 29:58]
node _T_294 = eq(num_valids, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 268:16]
node _T_295 = bits(_T_294, 0, 0) @[el2_ifu_bp_ctl.scala 268:24]
node _T_296 = bits(fghr, 6, 0) @[el2_ifu_bp_ctl.scala 268:40]
node _T_297 = cat(_T_296, final_h) @[Cat.scala 29:58]
node _T_298 = eq(num_valids, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 269:16]
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_bp_ctl.scala 269:24]
node _T_300 = bits(fghr, 7, 0) @[el2_ifu_bp_ctl.scala 269:40]
node _T_301 = mux(_T_290, _T_293, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_295, _T_297, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_299, _T_300, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = or(_T_301, _T_302) @[Mux.scala 27:72]
node _T_305 = or(_T_304, _T_303) @[Mux.scala 27:72]
wire merged_ghr : UInt<8> @[Mux.scala 27:72]
merged_ghr <= _T_305 @[Mux.scala 27:72]
node _T_306 = bits(exu_flush_final_d1, 0, 0) @[el2_ifu_bp_ctl.scala 273:46]
node _T_307 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 274:6]
node _T_308 = and(_T_307, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 274:26]
node _T_309 = and(_T_308, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 274:47]
node _T_310 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 274:63]
node _T_311 = and(_T_309, _T_310) @[el2_ifu_bp_ctl.scala 274:61]
node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_bp_ctl.scala 274:79]
node _T_313 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 275:6]
node _T_314 = and(io.ifc_fetch_req_f, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 275:49]
node _T_315 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 275:65]
node _T_316 = and(_T_314, _T_315) @[el2_ifu_bp_ctl.scala 275:63]
node _T_317 = not(_T_316) @[el2_ifu_bp_ctl.scala 275:28]
node _T_318 = and(_T_313, _T_317) @[el2_ifu_bp_ctl.scala 275:26]
node _T_319 = bits(_T_318, 0, 0) @[el2_ifu_bp_ctl.scala 275:82]
node _T_320 = mux(_T_306, io.exu_mp_fghr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_321 = mux(_T_312, merged_ghr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_322 = mux(_T_319, fghr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_323 = or(_T_320, _T_321) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_322) @[Mux.scala 27:72]
wire fghr_ns : UInt<8> @[Mux.scala 27:72]
fghr_ns <= _T_324 @[Mux.scala 27:72]
reg _T_325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 277:18]
_T_325 <= fghr_ns @[el2_ifu_bp_ctl.scala 277:18]
fghr <= _T_325 @[el2_ifu_bp_ctl.scala 277:8]
io.ifu_bp_fghr_f <= fghr @[el2_ifu_bp_ctl.scala 278:20]
io.ifu_bp_way_f <= way_raw @[el2_ifu_bp_ctl.scala 280:19]
io.ifu_bp_hist1_f <= hist1_raw @[el2_ifu_bp_ctl.scala 281:21]
io.ifu_bp_hist0_f <= hist0_raw @[el2_ifu_bp_ctl.scala 282:21]
io.ifu_bp_pc4_f <= pc4_raw @[el2_ifu_bp_ctl.scala 283:19]
node _T_326 = bits(io.dec_tlu_bpred_disable, 0, 0) @[Bitwise.scala 72:15]
node _T_327 = mux(_T_326, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_328 = not(_T_327) @[el2_ifu_bp_ctl.scala 285:36]
node _T_329 = and(bht_valid_f, _T_328) @[el2_ifu_bp_ctl.scala 285:34]
io.ifu_bp_valid_f <= _T_329 @[el2_ifu_bp_ctl.scala 285:21]
io.ifu_bp_ret_f <= pret_raw @[el2_ifu_bp_ctl.scala 286:19]
node _T_330 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:30]
node _T_331 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:50]
node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 288:36]
node _T_333 = and(_T_330, _T_332) @[el2_ifu_bp_ctl.scala 288:34]
node _T_334 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:68]
node _T_335 = eq(_T_334, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 288:58]
node _T_336 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:87]
node _T_337 = and(_T_335, _T_336) @[el2_ifu_bp_ctl.scala 288:72]
node _T_338 = or(_T_333, _T_337) @[el2_ifu_bp_ctl.scala 288:55]
node _T_339 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:15]
node _T_340 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:34]
node _T_341 = and(_T_339, _T_340) @[el2_ifu_bp_ctl.scala 289:19]
node _T_342 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:52]
node _T_343 = eq(_T_342, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 289:42]
node _T_344 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:72]
node _T_345 = eq(_T_344, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 289:58]
node _T_346 = and(_T_343, _T_345) @[el2_ifu_bp_ctl.scala 289:56]
node _T_347 = or(_T_341, _T_346) @[el2_ifu_bp_ctl.scala 289:39]
node bloc_f = cat(_T_338, _T_347) @[Cat.scala 29:58]
node _T_348 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 291:31]
node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 291:21]
node _T_350 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 291:56]
node _T_351 = and(_T_349, _T_350) @[el2_ifu_bp_ctl.scala 291:35]
node _T_352 = eq(btb_rd_pc4_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 291:62]
node use_fa_plus = and(_T_351, _T_352) @[el2_ifu_bp_ctl.scala 291:60]
node _T_353 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:40]
node _T_354 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:55]
node _T_355 = and(_T_353, _T_354) @[el2_ifu_bp_ctl.scala 293:44]
node btb_fg_crossing_f = and(_T_355, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 293:59]
node _T_356 = bits(bloc_f, 1, 1) @[el2_ifu_bp_ctl.scala 294:40]
node bp_total_branch_offset_f = xor(_T_356, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 294:43]
node _T_357 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 296:89]
node _T_358 = and(io.ifc_fetch_req_f, _T_357) @[el2_ifu_bp_ctl.scala 296:87]
node _T_359 = and(_T_358, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 296:109]
node _T_360 = bits(_T_359, 0, 0) @[el2_ifu_bp_ctl.scala 296:124]
reg ifc_fetch_adder_prior : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_360 : @[Reg.scala 28:19]
ifc_fetch_adder_prior <= io.ifc_fetch_addr_f @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_361 = bits(use_fa_plus, 0, 0) @[el2_ifu_bp_ctl.scala 299:45]
node _T_362 = bits(btb_fg_crossing_f, 0, 0) @[el2_ifu_bp_ctl.scala 300:23]
node _T_363 = eq(btb_fg_crossing_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 301:6]
node _T_364 = eq(use_fa_plus, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 301:27]
node _T_365 = and(_T_363, _T_364) @[el2_ifu_bp_ctl.scala 301:25]
node _T_366 = bits(_T_365, 0, 0) @[el2_ifu_bp_ctl.scala 301:41]
node _T_367 = bits(io.ifc_fetch_addr_f, 31, 2) @[el2_ifu_bp_ctl.scala 301:68]
node _T_368 = mux(_T_361, fetch_addr_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_369 = mux(_T_362, ifc_fetch_adder_prior, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_370 = mux(_T_366, _T_367, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_371 = or(_T_368, _T_369) @[Mux.scala 27:72]
node _T_372 = or(_T_371, _T_370) @[Mux.scala 27:72]
wire adder_pc_in_f : UInt @[Mux.scala 27:72]
adder_pc_in_f <= _T_372 @[Mux.scala 27:72]
node _T_373 = bits(adder_pc_in_f, 31, 2) @[el2_ifu_bp_ctl.scala 303:58]
node _T_374 = cat(_T_373, bp_total_branch_offset_f) @[Cat.scala 29:58]
node _T_375 = cat(_T_374, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_376 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_377 = bits(_T_375, 12, 1) @[el2_lib.scala 199:28]
node _T_378 = bits(_T_376, 12, 1) @[el2_lib.scala 199:44]
node _T_379 = add(_T_377, _T_378) @[el2_lib.scala 199:35]
node _T_380 = cat(_T_379, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_381 = bits(_T_375, 31, 13) @[el2_lib.scala 200:20]
node _T_382 = add(_T_381, UInt<1>("h01")) @[el2_lib.scala 200:27]
node _T_383 = tail(_T_382, 1) @[el2_lib.scala 200:27]
node _T_384 = bits(_T_375, 31, 13) @[el2_lib.scala 201:20]
node _T_385 = add(_T_384, UInt<1>("h01")) @[el2_lib.scala 201:27]
node _T_386 = tail(_T_385, 1) @[el2_lib.scala 201:27]
node _T_387 = bits(_T_376, 12, 12) @[el2_lib.scala 202:22]
node _T_388 = bits(_T_380, 13, 13) @[el2_lib.scala 203:38]
node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lib.scala 203:27]
node _T_390 = xor(_T_387, _T_389) @[el2_lib.scala 203:25]
node _T_391 = bits(_T_390, 0, 0) @[el2_lib.scala 203:63]
node _T_392 = bits(_T_375, 31, 13) @[el2_lib.scala 203:75]
node _T_393 = eq(_T_387, UInt<1>("h00")) @[el2_lib.scala 204:8]
node _T_394 = bits(_T_380, 13, 13) @[el2_lib.scala 204:26]
node _T_395 = and(_T_393, _T_394) @[el2_lib.scala 204:14]
node _T_396 = bits(_T_395, 0, 0) @[el2_lib.scala 204:51]
node _T_397 = bits(_T_375, 31, 13) @[el2_lib.scala 204:64]
node _T_398 = add(_T_397, UInt<1>("h01")) @[el2_lib.scala 204:71]
node _T_399 = tail(_T_398, 1) @[el2_lib.scala 204:71]
node _T_400 = bits(_T_380, 13, 13) @[el2_lib.scala 205:26]
node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_lib.scala 205:15]
node _T_402 = and(_T_387, _T_401) @[el2_lib.scala 205:13]
node _T_403 = bits(_T_402, 0, 0) @[el2_lib.scala 205:51]
node _T_404 = bits(_T_375, 31, 13) @[el2_lib.scala 205:64]
node _T_405 = sub(_T_404, UInt<1>("h01")) @[el2_lib.scala 205:71]
node _T_406 = tail(_T_405, 1) @[el2_lib.scala 205:71]
node _T_407 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_408 = mux(_T_396, _T_399, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_409 = mux(_T_403, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_410 = or(_T_407, _T_408) @[Mux.scala 27:72]
node _T_411 = or(_T_410, _T_409) @[Mux.scala 27:72]
wire _T_412 : UInt<19> @[Mux.scala 27:72]
_T_412 <= _T_411 @[Mux.scala 27:72]
node _T_413 = bits(_T_380, 11, 1) @[el2_lib.scala 205:91]
node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
node bp_btb_target_adder_f = cat(_T_414, UInt<1>("h00")) @[Cat.scala 29:58]
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