161 lines
6.2 KiB
Scala
161 lines
6.2 KiB
Scala
package ifu
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import lib._
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import chisel3._
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import chisel3.util._
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class el2_ifu_ifc_ctrl extends Module with el2_lib {
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val io = IO(new Bundle{
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val free_clk = Input(Bool())
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val active_clk = Input(Bool())
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val rst_l = Input(Bool())
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val scan_mode = Input(Bool())
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val ic_hit_f = Input(Bool())
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val ifu_ic_mb_empty = Input(Bool())
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val ifu_fb_consume1 = Input(Bool())
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val ifu_fb_consume2 = Input(Bool())
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val dec_tlu_flush_noredir_wb = Input(Bool())
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val exu_flush_final = Input(Bool())
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val exu_flush_path_final = Input(UInt(31.W))
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val ifu_bp_hit_taken_f = Input(Bool())
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val ifu_bp_btb_target_f = Input(UInt(31.W))
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val ic_dma_active = Input(Bool())
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val ic_write_stall = Input(Bool())
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val dma_iccm_stall_any = Input(Bool())
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val dec_tlu_mrac_ff = Input(UInt(32.W))
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val ifc_fetch_addr_f = Output(UInt(31.W))
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val ifc_fetch_addr_bf = Output(UInt(31.W))
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val ifc_fetch_req_f = Output(Bool())
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val ifu_pmu_fetch_stall = Output(Bool())
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val ifc_fetch_uncacheable_bf = Output(Bool())
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val ifc_fetch_req_bf = Output(Bool())
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val ifc_fetch_req_bf_raw = Output(Bool())
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val ifc_iccm_access_bf = Output(Bool())
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val ifc_region_acc_fault_bf = Output(Bool())
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val ifc_dma_access_ok = Output(Bool())
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val test_out = Output(UInt())
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})
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io.ifc_region_acc_fault_bf := 0.U
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io.ifc_dma_access_ok := 0.U
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val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U)
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val fetch_addr_next = WireInit(UInt(32.W), init = 0.U)
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val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
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val fb_write_f = WireInit(UInt(4.W), init = 0.U)
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val fb_full_f_ns = WireInit(Bool(), init = 0.U)
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val fb_right = WireInit(Bool(), init = 0.U)
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val fb_right2 = WireInit(Bool(), init = 0.U)
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val fb_left = WireInit(Bool(), init = 0.U)
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val wfm = WireInit(Bool(), init = 0.U)
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val idle = WireInit(Bool(), init = 0.U)
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val sel_last_addr_bf = WireInit(Bool(), init = 0.U)
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val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
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val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
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val miss_f = WireInit(Bool(), init = 0.U)
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val miss_a = WireInit(Bool(), init = 0.U)
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val flush_fb = WireInit(Bool(), init = 0.U)
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val mb_empty_mod = WireInit(Bool(), init = 0.U)
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val goto_idle = WireInit(Bool(), init = 0.U)
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val leave_idle = WireInit(Bool(), init = 0.U)
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val fetch_bf_en = WireInit(Bool(), init = 0.U)
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val line_wrap = WireInit(Bool(), init = 0.U)
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//val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
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val state = WireInit(UInt(2.W), init = 0.U)
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val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
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val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
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val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f
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dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init=0.U)
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miss_a := RegNext(miss_f, init=0.U)
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sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
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sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
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sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
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// TODO: Make an assertion for the 1H-Mux under here
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io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
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sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
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sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
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sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
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io.test_out := io.ifc_fetch_addr_bf
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line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
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fetch_addr_next := Cat((io.ifc_fetch_addr_f(30,1)+1.U) |
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Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
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io.ifc_fetch_req_bf_raw := ~idle
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io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
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~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb
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fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
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miss_f := io.ifc_fetch_req_f & ~io.ic_hit_f & ~io.exu_flush_final
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mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a
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goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
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leave_idle := io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle
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val next_state_1 = (~state(1) & state(0) & miss_f & ~goto_idle) |
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(state(1) & ~mb_empty_mod & ~goto_idle)
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val next_state_0 = (~goto_idle & leave_idle) | (state(0) & ~goto_idle)
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state := RegNext(Cat(next_state_0, next_state_0), init = 0.U)
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flush_fb := io.exu_flush_final
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fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) |
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(io.ifu_fb_consume2 & io.ifc_fetch_req_f)
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fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
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fb_left := io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f
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fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
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(~flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
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(~flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
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(~flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)),
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(~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool -> fb_write_f(3,0)
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))
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fb_full_f_ns := RegNext(fb_write_ns(3), init = 0.U)
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idle := state === 0.U(2.W)
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wfm := state === 3.U(2.W)
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fb_full_f_ns := fb_write_ns(3)
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val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
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fb_write_f := RegNext(fb_write_ns, 0.U)
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io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
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~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
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val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
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rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
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else (0.U, 0.U)
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io.ifc_iccm_access_bf := iccm_acc_in_range_bf
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io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
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io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)
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io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
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}
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/*
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object ifu_ifc extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
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}*/
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