35 lines
1.1 KiB
Verilog
35 lines
1.1 KiB
Verilog
module EL2_IC_DATA(
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input clock,
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input reset,
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input io_rst_l,
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input io_clk_override,
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input [11:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input io_ic_rd_en,
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input [70:0] io_ic_wr_data_0,
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input [70:0] io_ic_wr_data_1,
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output [63:0] io_ic_rd_data,
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input [70:0] io_ic_debug_wr_data,
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output [70:0] io_ic_debug_rd_data,
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output [1:0] io_ic_parerr,
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output [1:0] io_ic_eccerr,
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input [14:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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input [1:0] io_ic_debug_way,
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input [63:0] io_ic_premux_data,
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input io_ic_sel_premux_data,
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input [1:0] io_ic_rd_hit,
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input io_scan_mode,
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input io_mask_0_0,
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input io_mask_0_1,
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input io_mask_1_0,
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input io_mask_1_1
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);
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
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endmodule
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