1284 lines
75 KiB
Plaintext
1284 lines
75 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dbg :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_6 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_7 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module dbg :
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input clock : Clock
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input reset : AsyncReset
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output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
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wire dbg_state : UInt<3>
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dbg_state <= UInt<3>("h00")
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wire dbg_state_en : UInt<1>
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dbg_state_en <= UInt<1>("h00")
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wire sb_state : UInt<4>
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sb_state <= UInt<4>("h00")
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wire sb_state_en : UInt<1>
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sb_state_en <= UInt<1>("h00")
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wire dmcontrol_reg : UInt<32>
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dmcontrol_reg <= UInt<32>("h00")
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wire sbaddress0_reg : UInt<32>
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sbaddress0_reg <= UInt<32>("h00")
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wire sbcs_sbbusy_wren : UInt<1>
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sbcs_sbbusy_wren <= UInt<1>("h00")
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wire sbcs_sberror_wren : UInt<1>
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sbcs_sberror_wren <= UInt<1>("h00")
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wire sb_bus_rdata : UInt<64>
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sb_bus_rdata <= UInt<64>("h00")
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wire sbaddress0_reg_wren1 : UInt<1>
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sbaddress0_reg_wren1 <= UInt<1>("h00")
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wire dmstatus_reg : UInt<32>
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dmstatus_reg <= UInt<32>("h00")
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wire dmstatus_havereset : UInt<1>
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dmstatus_havereset <= UInt<1>("h00")
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wire dmstatus_resumeack : UInt<1>
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dmstatus_resumeack <= UInt<1>("h00")
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wire dmstatus_unavail : UInt<1>
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dmstatus_unavail <= UInt<1>("h00")
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wire dmstatus_running : UInt<1>
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dmstatus_running <= UInt<1>("h00")
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wire dmstatus_halted : UInt<1>
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dmstatus_halted <= UInt<1>("h00")
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wire abstractcs_busy_wren : UInt<1>
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abstractcs_busy_wren <= UInt<1>("h00")
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wire abstractcs_busy_din : UInt<1>
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abstractcs_busy_din <= UInt<1>("h00")
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wire sb_bus_cmd_read : UInt<1>
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sb_bus_cmd_read <= UInt<1>("h00")
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wire sb_bus_cmd_write_addr : UInt<1>
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sb_bus_cmd_write_addr <= UInt<1>("h00")
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wire sb_bus_cmd_write_data : UInt<1>
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sb_bus_cmd_write_data <= UInt<1>("h00")
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wire sb_bus_rsp_read : UInt<1>
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sb_bus_rsp_read <= UInt<1>("h00")
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wire sb_bus_rsp_error : UInt<1>
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sb_bus_rsp_error <= UInt<1>("h00")
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wire sb_bus_rsp_write : UInt<1>
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sb_bus_rsp_write <= UInt<1>("h00")
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wire sbcs_sbbusy_din : UInt<1>
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sbcs_sbbusy_din <= UInt<1>("h00")
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wire sbcs_sberror_din : UInt<3>
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sbcs_sberror_din <= UInt<3>("h00")
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wire data1_reg : UInt<32>
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data1_reg <= UInt<32>("h00")
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wire sbcs_reg : UInt<32>
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sbcs_reg <= UInt<32>("h00")
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node _T = neq(dbg_state, UInt<3>("h00")) @[dbg.scala 95:51]
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node _T_1 = or(io.dmi_reg_en, _T) @[dbg.scala 95:38]
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node _T_2 = or(_T_1, dbg_state_en) @[dbg.scala 95:69]
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node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[dbg.scala 95:84]
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node dbg_free_clken = or(_T_3, io.clk_override) @[dbg.scala 95:108]
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node _T_4 = or(io.dmi_reg_en, sb_state_en) @[dbg.scala 96:37]
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node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63]
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node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51]
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node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86]
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inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[lib.scala 344:17]
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rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16]
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rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
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inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
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rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
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node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 99:42]
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node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 99:61]
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node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 99:65]
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node _T_10 = and(_T_7, _T_9) @[dbg.scala 99:45]
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node dbg_dm_rst_l = asAsyncReset(_T_10) @[dbg.scala 99:94]
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node _T_11 = asUInt(dbg_dm_rst_l) @[dbg.scala 101:38]
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node _T_12 = asUInt(reset) @[dbg.scala 101:55]
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node _T_13 = and(_T_11, _T_12) @[dbg.scala 101:41]
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node rst_temp = asAsyncReset(_T_13) @[dbg.scala 101:71]
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node _T_14 = asUInt(dbg_dm_rst_l) @[dbg.scala 103:32]
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node _T_15 = eq(_T_14, UInt<1>("h00")) @[dbg.scala 103:18]
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node rst_not = asAsyncReset(_T_15) @[dbg.scala 103:52]
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node _T_16 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 105:39]
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node _T_17 = eq(_T_16, UInt<1>("h00")) @[dbg.scala 105:25]
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node _T_18 = bits(_T_17, 0, 0) @[dbg.scala 105:50]
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io.dbg_core_rst_l <= _T_18 @[dbg.scala 105:21]
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node _T_19 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 106:36]
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node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 106:49]
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node _T_21 = and(_T_20, io.dmi_reg_wr_en) @[dbg.scala 106:65]
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node _T_22 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 106:96]
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node sbcs_wren = and(_T_21, _T_22) @[dbg.scala 106:84]
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node _T_23 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 107:60]
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node _T_24 = and(sbcs_wren, _T_23) @[dbg.scala 107:42]
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node _T_25 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 107:79]
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node _T_26 = and(_T_25, io.dmi_reg_en) @[dbg.scala 107:102]
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node _T_27 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 108:23]
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node _T_28 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 108:55]
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node _T_29 = or(_T_27, _T_28) @[dbg.scala 108:36]
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node _T_30 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 108:87]
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node _T_31 = or(_T_29, _T_30) @[dbg.scala 108:68]
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node _T_32 = and(_T_26, _T_31) @[dbg.scala 107:118]
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node sbcs_sbbusyerror_wren = or(_T_24, _T_32) @[dbg.scala 107:66]
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node _T_33 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 110:61]
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node _T_34 = and(sbcs_wren, _T_33) @[dbg.scala 110:43]
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node sbcs_sbbusyerror_din = not(_T_34) @[dbg.scala 110:31]
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reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
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temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusy_wren : @[Reg.scala 28:19]
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temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 120:31]
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reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_20 <= _T_35 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_36 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 124:31]
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reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_19_15 <= _T_36 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 128:31]
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reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (rst_not, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sberror_wren : @[Reg.scala 28:19]
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temp_sbcs_14_12 <= _T_37 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_38 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58]
|
|
node _T_39 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58]
|
|
node _T_40 = cat(_T_39, _T_38) @[Cat.scala 29:58]
|
|
node _T_41 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58]
|
|
node _T_42 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58]
|
|
node _T_43 = cat(_T_42, temp_sbcs_22) @[Cat.scala 29:58]
|
|
node _T_44 = cat(_T_43, _T_41) @[Cat.scala 29:58]
|
|
node _T_45 = cat(_T_44, _T_40) @[Cat.scala 29:58]
|
|
sbcs_reg <= _T_45 @[dbg.scala 130:12]
|
|
node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:33]
|
|
node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 132:42]
|
|
node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 132:77]
|
|
node _T_49 = and(_T_47, _T_48) @[dbg.scala 132:61]
|
|
node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:14]
|
|
node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 133:23]
|
|
node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 133:58]
|
|
node _T_53 = orr(_T_52) @[dbg.scala 133:65]
|
|
node _T_54 = and(_T_51, _T_53) @[dbg.scala 133:42]
|
|
node _T_55 = or(_T_49, _T_54) @[dbg.scala 132:81]
|
|
node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 134:14]
|
|
node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 134:23]
|
|
node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 134:58]
|
|
node _T_59 = orr(_T_58) @[dbg.scala 134:65]
|
|
node _T_60 = and(_T_57, _T_59) @[dbg.scala 134:42]
|
|
node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 133:69]
|
|
node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 136:35]
|
|
node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:42]
|
|
node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 137:51]
|
|
node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_64 = mux(_T_63, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 137:64]
|
|
node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:100]
|
|
node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 137:109]
|
|
node _T_68 = bits(_T_67, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_69 = mux(_T_68, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 137:122]
|
|
node _T_71 = or(_T_65, _T_70) @[dbg.scala 137:81]
|
|
node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:22]
|
|
node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 138:31]
|
|
node _T_74 = bits(_T_73, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_75 = mux(_T_74, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 138:44]
|
|
node _T_77 = or(_T_71, _T_76) @[dbg.scala 137:139]
|
|
node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:80]
|
|
node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 138:89]
|
|
node _T_80 = bits(_T_79, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_81 = mux(_T_80, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 138:102]
|
|
node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 138:61]
|
|
node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 140:41]
|
|
node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 140:79]
|
|
node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 140:60]
|
|
node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 141:37]
|
|
node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 141:60]
|
|
node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 141:76]
|
|
node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 141:74]
|
|
node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 142:44]
|
|
node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 143:41]
|
|
node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 143:79]
|
|
node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 143:60]
|
|
node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 144:37]
|
|
node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 144:60]
|
|
node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 144:76]
|
|
node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 144:74]
|
|
node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 145:44]
|
|
node _T_93 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_94 = mux(_T_93, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 146:49]
|
|
node _T_96 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_97 = mux(_T_96, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 147:47]
|
|
node _T_99 = and(_T_97, _T_98) @[dbg.scala 147:33]
|
|
node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 146:68]
|
|
node _T_100 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 149:49]
|
|
node _T_103 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 150:47]
|
|
node _T_106 = and(_T_104, _T_105) @[dbg.scala 150:33]
|
|
node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 149:68]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= dbg_dm_rst_l
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 371:17]
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
sbdata0_reg <= sbdata0_din @[lib.scala 374:16]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= dbg_dm_rst_l
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 371:17]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
sbdata1_reg <= sbdata1_din @[lib.scala 374:16]
|
|
node _T_107 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 160:44]
|
|
node _T_108 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 160:82]
|
|
node sbaddress0_reg_wren0 = and(_T_107, _T_108) @[dbg.scala 160:63]
|
|
node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 161:50]
|
|
node _T_109 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_111 = and(_T_110, io.dmi_reg_wdata) @[dbg.scala 162:59]
|
|
node _T_112 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_114 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
|
|
node _T_115 = add(sbaddress0_reg, _T_114) @[dbg.scala 163:54]
|
|
node _T_116 = tail(_T_115, 1) @[dbg.scala 163:54]
|
|
node _T_117 = and(_T_113, _T_116) @[dbg.scala 163:36]
|
|
node sbaddress0_reg_din = or(_T_111, _T_117) @[dbg.scala 162:78]
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
|
|
rvclkhdr_4.clock <= clock
|
|
rvclkhdr_4.reset <= dbg_dm_rst_l
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 371:17]
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg _T_118 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
_T_118 <= sbaddress0_reg_din @[lib.scala 374:16]
|
|
sbaddress0_reg <= _T_118 @[dbg.scala 164:18]
|
|
node _T_119 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 168:43]
|
|
node _T_120 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 168:81]
|
|
node _T_121 = and(_T_119, _T_120) @[dbg.scala 168:62]
|
|
node _T_122 = bits(sbcs_reg, 20, 20) @[dbg.scala 168:104]
|
|
node sbreadonaddr_access = and(_T_121, _T_122) @[dbg.scala 168:94]
|
|
node _T_123 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 169:45]
|
|
node _T_124 = and(io.dmi_reg_en, _T_123) @[dbg.scala 169:43]
|
|
node _T_125 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 169:82]
|
|
node _T_126 = and(_T_124, _T_125) @[dbg.scala 169:63]
|
|
node _T_127 = bits(sbcs_reg, 15, 15) @[dbg.scala 169:105]
|
|
node sbreadondata_access = and(_T_126, _T_127) @[dbg.scala 169:95]
|
|
node _T_128 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:40]
|
|
node _T_129 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 170:78]
|
|
node sbdata0wr_access = and(_T_128, _T_129) @[dbg.scala 170:59]
|
|
node _T_130 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 171:41]
|
|
node _T_131 = and(_T_130, io.dmi_reg_en) @[dbg.scala 171:54]
|
|
node dmcontrol_wren = and(_T_131, io.dmi_reg_wr_en) @[dbg.scala 171:70]
|
|
node _T_132 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 174:27]
|
|
node _T_133 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 174:53]
|
|
node _T_134 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 174:75]
|
|
node _T_135 = cat(_T_132, _T_133) @[Cat.scala 29:58]
|
|
node _T_136 = cat(_T_135, _T_134) @[Cat.scala 29:58]
|
|
reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp <= _T_136 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_137 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 178:76]
|
|
node _T_138 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31]
|
|
reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_137, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp_0 <= _T_138 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_139 = bits(dm_temp, 3, 2) @[dbg.scala 182:25]
|
|
node _T_140 = bits(dm_temp, 1, 1) @[dbg.scala 182:45]
|
|
node _T_141 = bits(dm_temp, 0, 0) @[dbg.scala 182:68]
|
|
node _T_142 = cat(UInt<26>("h00"), _T_141) @[Cat.scala 29:58]
|
|
node _T_143 = cat(_T_142, dm_temp_0) @[Cat.scala 29:58]
|
|
node _T_144 = cat(_T_139, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58]
|
|
node temp = cat(_T_145, _T_143) @[Cat.scala 29:58]
|
|
dmcontrol_reg <= temp @[dbg.scala 183:17]
|
|
reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 186:12]
|
|
dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 186:12]
|
|
node _T_146 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_147 = mux(_T_146, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_148 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_149 = mux(_T_148, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_150 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_151 = mux(_T_150, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_152 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_153 = mux(_T_152, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_154 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_155 = mux(_T_154, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_156 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
|
|
node _T_157 = cat(_T_153, _T_155) @[Cat.scala 29:58]
|
|
node _T_158 = cat(_T_157, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_159 = cat(_T_158, _T_156) @[Cat.scala 29:58]
|
|
node _T_160 = cat(UInt<2>("h00"), _T_151) @[Cat.scala 29:58]
|
|
node _T_161 = cat(UInt<12>("h00"), _T_147) @[Cat.scala 29:58]
|
|
node _T_162 = cat(_T_161, _T_149) @[Cat.scala 29:58]
|
|
node _T_163 = cat(_T_162, _T_160) @[Cat.scala 29:58]
|
|
node _T_164 = cat(_T_163, _T_159) @[Cat.scala 29:58]
|
|
dmstatus_reg <= _T_164 @[dbg.scala 189:16]
|
|
node _T_165 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 191:44]
|
|
node _T_166 = and(_T_165, io.dec_tlu_resume_ack) @[dbg.scala 191:66]
|
|
node _T_167 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 191:127]
|
|
node _T_168 = eq(_T_167, UInt<1>("h00")) @[dbg.scala 191:113]
|
|
node _T_169 = and(dmstatus_resumeack, _T_168) @[dbg.scala 191:111]
|
|
node dmstatus_resumeack_wren = or(_T_166, _T_169) @[dbg.scala 191:90]
|
|
node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 192:43]
|
|
node dmstatus_resumeack_din = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 192:65]
|
|
node _T_171 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 193:50]
|
|
node _T_172 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 193:81]
|
|
node _T_173 = and(_T_171, _T_172) @[dbg.scala 193:63]
|
|
node _T_174 = and(_T_173, io.dmi_reg_en) @[dbg.scala 193:85]
|
|
node dmstatus_havereset_wren = and(_T_174, io.dmi_reg_wr_en) @[dbg.scala 193:101]
|
|
node _T_175 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 194:49]
|
|
node _T_176 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 194:80]
|
|
node _T_177 = and(_T_175, _T_176) @[dbg.scala 194:62]
|
|
node _T_178 = and(_T_177, io.dmi_reg_en) @[dbg.scala 194:85]
|
|
node dmstatus_havereset_rst = and(_T_178, io.dmi_reg_wr_en) @[dbg.scala 194:101]
|
|
node temp_rst = asUInt(reset) @[dbg.scala 195:30]
|
|
node _T_179 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 196:37]
|
|
node _T_180 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 196:43]
|
|
node _T_181 = or(_T_179, _T_180) @[dbg.scala 196:41]
|
|
node _T_182 = bits(_T_181, 0, 0) @[dbg.scala 196:62]
|
|
dmstatus_unavail <= _T_182 @[dbg.scala 196:20]
|
|
node _T_183 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 197:42]
|
|
node _T_184 = not(_T_183) @[dbg.scala 197:23]
|
|
dmstatus_running <= _T_184 @[dbg.scala 197:20]
|
|
reg _T_185 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmstatus_resumeack_wren : @[Reg.scala 28:19]
|
|
_T_185 <= dmstatus_resumeack_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dmstatus_resumeack <= _T_185 @[dbg.scala 198:22]
|
|
node _T_186 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 203:37]
|
|
node _T_187 = and(io.dec_tlu_dbg_halted, _T_186) @[dbg.scala 203:35]
|
|
reg _T_188 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 203:12]
|
|
_T_188 <= _T_187 @[dbg.scala 203:12]
|
|
dmstatus_halted <= _T_188 @[dbg.scala 202:19]
|
|
node _T_189 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 207:16]
|
|
node _T_190 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 207:72]
|
|
node _T_191 = and(_T_189, _T_190) @[dbg.scala 207:70]
|
|
reg _T_192 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 207:12]
|
|
_T_192 <= _T_191 @[dbg.scala 207:12]
|
|
dmstatus_havereset <= _T_192 @[dbg.scala 206:22]
|
|
node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
|
|
wire abstractcs_reg : UInt<32>
|
|
abstractcs_reg <= UInt<32>("h02")
|
|
node _T_193 = bits(abstractcs_reg, 12, 12) @[dbg.scala 213:45]
|
|
node _T_194 = and(_T_193, io.dmi_reg_en) @[dbg.scala 213:50]
|
|
node _T_195 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 213:106]
|
|
node _T_196 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 213:138]
|
|
node _T_197 = or(_T_195, _T_196) @[dbg.scala 213:119]
|
|
node _T_198 = and(io.dmi_reg_wr_en, _T_197) @[dbg.scala 213:86]
|
|
node _T_199 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 213:171]
|
|
node _T_200 = or(_T_198, _T_199) @[dbg.scala 213:152]
|
|
node abstractcs_error_sel0 = and(_T_194, _T_200) @[dbg.scala 213:66]
|
|
node _T_201 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 214:45]
|
|
node _T_202 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 214:83]
|
|
node _T_203 = and(_T_201, _T_202) @[dbg.scala 214:64]
|
|
node _T_204 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:117]
|
|
node _T_205 = eq(_T_204, UInt<1>("h00")) @[dbg.scala 214:126]
|
|
node _T_206 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:154]
|
|
node _T_207 = eq(_T_206, UInt<2>("h02")) @[dbg.scala 214:163]
|
|
node _T_208 = or(_T_205, _T_207) @[dbg.scala 214:135]
|
|
node _T_209 = eq(_T_208, UInt<1>("h00")) @[dbg.scala 214:98]
|
|
node abstractcs_error_sel1 = and(_T_203, _T_209) @[dbg.scala 214:96]
|
|
node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 215:52]
|
|
node _T_210 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 216:45]
|
|
node _T_211 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 216:83]
|
|
node _T_212 = and(_T_210, _T_211) @[dbg.scala 216:64]
|
|
node _T_213 = bits(dmstatus_reg, 9, 9) @[dbg.scala 216:111]
|
|
node _T_214 = eq(_T_213, UInt<1>("h00")) @[dbg.scala 216:98]
|
|
node abstractcs_error_sel3 = and(_T_212, _T_214) @[dbg.scala 216:96]
|
|
node _T_215 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 217:48]
|
|
node _T_216 = and(_T_215, io.dmi_reg_en) @[dbg.scala 217:61]
|
|
node _T_217 = and(_T_216, io.dmi_reg_wr_en) @[dbg.scala 217:77]
|
|
node _T_218 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 218:23]
|
|
node _T_219 = neq(_T_218, UInt<3>("h02")) @[dbg.scala 218:32]
|
|
node _T_220 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 218:71]
|
|
node _T_221 = eq(_T_220, UInt<2>("h02")) @[dbg.scala 218:80]
|
|
node _T_222 = bits(data1_reg, 1, 0) @[dbg.scala 218:104]
|
|
node _T_223 = orr(_T_222) @[dbg.scala 218:111]
|
|
node _T_224 = and(_T_221, _T_223) @[dbg.scala 218:92]
|
|
node _T_225 = or(_T_219, _T_224) @[dbg.scala 218:51]
|
|
node abstractcs_error_sel4 = and(_T_217, _T_225) @[dbg.scala 217:96]
|
|
node _T_226 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 220:48]
|
|
node _T_227 = and(_T_226, io.dmi_reg_en) @[dbg.scala 220:61]
|
|
node abstractcs_error_sel5 = and(_T_227, io.dmi_reg_wr_en) @[dbg.scala 220:77]
|
|
node _T_228 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 221:54]
|
|
node _T_229 = or(_T_228, abstractcs_error_sel2) @[dbg.scala 221:78]
|
|
node _T_230 = or(_T_229, abstractcs_error_sel3) @[dbg.scala 221:102]
|
|
node _T_231 = or(_T_230, abstractcs_error_sel4) @[dbg.scala 221:126]
|
|
node abstractcs_error_selor = or(_T_231, abstractcs_error_sel5) @[dbg.scala 221:150]
|
|
node _T_232 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_233 = mux(_T_232, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_234 = and(_T_233, UInt<3>("h01")) @[dbg.scala 222:62]
|
|
node _T_235 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_236 = mux(_T_235, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_237 = and(_T_236, UInt<3>("h02")) @[dbg.scala 223:37]
|
|
node _T_238 = or(_T_234, _T_237) @[dbg.scala 222:79]
|
|
node _T_239 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_240 = mux(_T_239, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_241 = and(_T_240, UInt<3>("h03")) @[dbg.scala 224:37]
|
|
node _T_242 = or(_T_238, _T_241) @[dbg.scala 223:54]
|
|
node _T_243 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_245 = and(_T_244, UInt<3>("h04")) @[dbg.scala 225:37]
|
|
node _T_246 = or(_T_242, _T_245) @[dbg.scala 224:54]
|
|
node _T_247 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_249 = and(_T_248, UInt<3>("h07")) @[dbg.scala 226:37]
|
|
node _T_250 = or(_T_246, _T_249) @[dbg.scala 225:54]
|
|
node _T_251 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_253 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 227:57]
|
|
node _T_254 = not(_T_253) @[dbg.scala 227:40]
|
|
node _T_255 = and(_T_252, _T_254) @[dbg.scala 227:37]
|
|
node _T_256 = bits(abstractcs_reg, 10, 8) @[dbg.scala 227:91]
|
|
node _T_257 = and(_T_255, _T_256) @[dbg.scala 227:75]
|
|
node _T_258 = or(_T_250, _T_257) @[dbg.scala 226:54]
|
|
node _T_259 = not(abstractcs_error_selor) @[dbg.scala 228:15]
|
|
node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_262 = bits(abstractcs_reg, 10, 8) @[dbg.scala 228:66]
|
|
node _T_263 = and(_T_261, _T_262) @[dbg.scala 228:50]
|
|
node abstractcs_error_din = or(_T_258, _T_263) @[dbg.scala 227:100]
|
|
reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when abstractcs_busy_wren : @[Reg.scala 28:19]
|
|
abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_264 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 235:33]
|
|
reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 235:12]
|
|
abs_temp_10_8 <= _T_264 @[dbg.scala 235:12]
|
|
node _T_265 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
|
|
node _T_266 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
|
|
node _T_267 = cat(_T_266, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_268 = cat(_T_267, _T_265) @[Cat.scala 29:58]
|
|
abstractcs_reg <= _T_268 @[dbg.scala 238:18]
|
|
node _T_269 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 240:39]
|
|
node _T_270 = and(_T_269, io.dmi_reg_en) @[dbg.scala 240:52]
|
|
node _T_271 = and(_T_270, io.dmi_reg_wr_en) @[dbg.scala 240:68]
|
|
node _T_272 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 240:100]
|
|
node command_wren = and(_T_271, _T_272) @[dbg.scala 240:87]
|
|
node _T_273 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 241:41]
|
|
node _T_274 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 241:77]
|
|
node _T_275 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 241:113]
|
|
node _T_276 = cat(UInt<3>("h00"), _T_275) @[Cat.scala 29:58]
|
|
node _T_277 = cat(_T_273, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_278 = cat(_T_277, _T_274) @[Cat.scala 29:58]
|
|
node command_din = cat(_T_278, _T_276) @[Cat.scala 29:58]
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23]
|
|
rvclkhdr_5.clock <= clock
|
|
rvclkhdr_5.reset <= dbg_dm_rst_l
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_5.io.en <= command_wren @[lib.scala 371:17]
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
command_reg <= command_din @[lib.scala 374:16]
|
|
node _T_279 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 246:39]
|
|
node _T_280 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 246:77]
|
|
node _T_281 = and(_T_279, _T_280) @[dbg.scala 246:58]
|
|
node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 246:102]
|
|
node data0_reg_wren0 = and(_T_281, _T_282) @[dbg.scala 246:89]
|
|
node _T_283 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 247:59]
|
|
node _T_284 = and(io.core_dbg_cmd_done, _T_283) @[dbg.scala 247:46]
|
|
node _T_285 = bits(command_reg, 16, 16) @[dbg.scala 247:95]
|
|
node _T_286 = eq(_T_285, UInt<1>("h00")) @[dbg.scala 247:83]
|
|
node data0_reg_wren1 = and(_T_284, _T_286) @[dbg.scala 247:81]
|
|
node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 249:40]
|
|
node _T_287 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_288 = mux(_T_287, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_289 = and(_T_288, io.dmi_reg_wdata) @[dbg.scala 250:45]
|
|
node _T_290 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_291 = mux(_T_290, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_292 = and(_T_291, io.core_dbg_rddata) @[dbg.scala 250:92]
|
|
node data0_din = or(_T_289, _T_292) @[dbg.scala 250:64]
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23]
|
|
rvclkhdr_6.clock <= clock
|
|
rvclkhdr_6.reset <= dbg_dm_rst_l
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 371:17]
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
data0_reg <= data0_din @[lib.scala 374:16]
|
|
node _T_293 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 255:39]
|
|
node _T_294 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 255:77]
|
|
node _T_295 = and(_T_293, _T_294) @[dbg.scala 255:58]
|
|
node _T_296 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 255:102]
|
|
node data1_reg_wren = and(_T_295, _T_296) @[dbg.scala 255:89]
|
|
node _T_297 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_298 = mux(_T_297, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node data1_din = and(_T_298, io.dmi_reg_wdata) @[dbg.scala 256:44]
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23]
|
|
rvclkhdr_7.clock <= clock
|
|
rvclkhdr_7.reset <= dbg_dm_rst_l
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 371:17]
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
|
reg _T_299 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
_T_299 <= data1_din @[lib.scala 374:16]
|
|
data1_reg <= _T_299 @[dbg.scala 257:13]
|
|
wire dbg_nxtstate : UInt<3>
|
|
dbg_nxtstate <= UInt<3>("h00")
|
|
dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 262:16]
|
|
dbg_state_en <= UInt<1>("h00") @[dbg.scala 263:16]
|
|
abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 264:24]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 265:23]
|
|
io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 266:19]
|
|
io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 267:21]
|
|
node _T_300 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_300 : @[Conditional.scala 40:58]
|
|
node _T_301 = bits(dmstatus_reg, 9, 9) @[dbg.scala 270:39]
|
|
node _T_302 = or(_T_301, io.dec_tlu_mpc_halted_only) @[dbg.scala 270:43]
|
|
node _T_303 = mux(_T_302, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 270:26]
|
|
dbg_nxtstate <= _T_303 @[dbg.scala 270:20]
|
|
node _T_304 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 271:38]
|
|
node _T_305 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 271:45]
|
|
node _T_306 = and(_T_304, _T_305) @[dbg.scala 271:43]
|
|
node _T_307 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:83]
|
|
node _T_308 = or(_T_306, _T_307) @[dbg.scala 271:69]
|
|
node _T_309 = or(_T_308, io.dec_tlu_mpc_halted_only) @[dbg.scala 271:87]
|
|
node _T_310 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:133]
|
|
node _T_311 = eq(_T_310, UInt<1>("h00")) @[dbg.scala 271:119]
|
|
node _T_312 = and(_T_309, _T_311) @[dbg.scala 271:117]
|
|
dbg_state_en <= _T_312 @[dbg.scala 271:20]
|
|
node _T_313 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:40]
|
|
node _T_314 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:61]
|
|
node _T_315 = eq(_T_314, UInt<1>("h00")) @[dbg.scala 272:47]
|
|
node _T_316 = and(_T_313, _T_315) @[dbg.scala 272:45]
|
|
node _T_317 = bits(_T_316, 0, 0) @[dbg.scala 272:72]
|
|
io.dbg_halt_req <= _T_317 @[dbg.scala 272:23]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_318 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_318 : @[Conditional.scala 39:67]
|
|
node _T_319 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:40]
|
|
node _T_320 = mux(_T_319, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 275:26]
|
|
dbg_nxtstate <= _T_320 @[dbg.scala 275:20]
|
|
node _T_321 = bits(dmstatus_reg, 9, 9) @[dbg.scala 276:35]
|
|
node _T_322 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 276:54]
|
|
node _T_323 = or(_T_321, _T_322) @[dbg.scala 276:39]
|
|
dbg_state_en <= _T_323 @[dbg.scala 276:20]
|
|
node _T_324 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:59]
|
|
node _T_325 = and(dmcontrol_wren_Q, _T_324) @[dbg.scala 277:44]
|
|
node _T_326 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 277:81]
|
|
node _T_327 = not(_T_326) @[dbg.scala 277:67]
|
|
node _T_328 = and(_T_325, _T_327) @[dbg.scala 277:64]
|
|
node _T_329 = bits(_T_328, 0, 0) @[dbg.scala 277:102]
|
|
io.dbg_halt_req <= _T_329 @[dbg.scala 277:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_330 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_330 : @[Conditional.scala 39:67]
|
|
node _T_331 = bits(dmstatus_reg, 9, 9) @[dbg.scala 280:39]
|
|
node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 280:59]
|
|
node _T_333 = eq(_T_332, UInt<1>("h00")) @[dbg.scala 280:45]
|
|
node _T_334 = and(_T_331, _T_333) @[dbg.scala 280:43]
|
|
node _T_335 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 281:26]
|
|
node _T_336 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 281:47]
|
|
node _T_337 = eq(_T_336, UInt<1>("h00")) @[dbg.scala 281:33]
|
|
node _T_338 = and(_T_335, _T_337) @[dbg.scala 281:31]
|
|
node _T_339 = mux(_T_338, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 281:12]
|
|
node _T_340 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 282:26]
|
|
node _T_341 = mux(_T_340, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 282:12]
|
|
node _T_342 = mux(_T_334, _T_339, _T_341) @[dbg.scala 280:26]
|
|
dbg_nxtstate <= _T_342 @[dbg.scala 280:20]
|
|
node _T_343 = bits(dmstatus_reg, 9, 9) @[dbg.scala 283:35]
|
|
node _T_344 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 283:54]
|
|
node _T_345 = and(_T_343, _T_344) @[dbg.scala 283:39]
|
|
node _T_346 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:75]
|
|
node _T_347 = eq(_T_346, UInt<1>("h00")) @[dbg.scala 283:61]
|
|
node _T_348 = and(_T_345, _T_347) @[dbg.scala 283:59]
|
|
node _T_349 = and(_T_348, dmcontrol_wren_Q) @[dbg.scala 283:80]
|
|
node _T_350 = or(_T_349, command_wren) @[dbg.scala 283:99]
|
|
node _T_351 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 284:22]
|
|
node _T_352 = or(_T_350, _T_351) @[dbg.scala 283:114]
|
|
node _T_353 = bits(dmstatus_reg, 9, 9) @[dbg.scala 284:42]
|
|
node _T_354 = or(_T_353, io.dec_tlu_mpc_halted_only) @[dbg.scala 284:46]
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[dbg.scala 284:28]
|
|
node _T_356 = or(_T_352, _T_355) @[dbg.scala 284:26]
|
|
dbg_state_en <= _T_356 @[dbg.scala 283:20]
|
|
node _T_357 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 285:60]
|
|
node _T_358 = and(dbg_state_en, _T_357) @[dbg.scala 285:44]
|
|
abstractcs_busy_wren <= _T_358 @[dbg.scala 285:28]
|
|
abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 286:27]
|
|
node _T_359 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 287:58]
|
|
node _T_360 = and(dbg_state_en, _T_359) @[dbg.scala 287:42]
|
|
node _T_361 = bits(_T_360, 0, 0) @[dbg.scala 287:87]
|
|
io.dbg_resume_req <= _T_361 @[dbg.scala 287:25]
|
|
node _T_362 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59]
|
|
node _T_363 = and(dmcontrol_wren_Q, _T_362) @[dbg.scala 288:44]
|
|
node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81]
|
|
node _T_365 = not(_T_364) @[dbg.scala 288:67]
|
|
node _T_366 = and(_T_363, _T_365) @[dbg.scala 288:64]
|
|
node _T_367 = bits(_T_366, 0, 0) @[dbg.scala 288:102]
|
|
io.dbg_halt_req <= _T_367 @[dbg.scala 288:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_368 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_368 : @[Conditional.scala 39:67]
|
|
node _T_369 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40]
|
|
node _T_370 = bits(abstractcs_reg, 10, 8) @[dbg.scala 291:77]
|
|
node _T_371 = orr(_T_370) @[dbg.scala 291:85]
|
|
node _T_372 = mux(_T_371, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 291:62]
|
|
node _T_373 = mux(_T_369, UInt<3>("h00"), _T_372) @[dbg.scala 291:26]
|
|
dbg_nxtstate <= _T_373 @[dbg.scala 291:20]
|
|
node _T_374 = bits(abstractcs_reg, 10, 8) @[dbg.scala 292:71]
|
|
node _T_375 = orr(_T_374) @[dbg.scala 292:79]
|
|
node _T_376 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_375) @[dbg.scala 292:55]
|
|
node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:98]
|
|
node _T_378 = or(_T_376, _T_377) @[dbg.scala 292:83]
|
|
dbg_state_en <= _T_378 @[dbg.scala 292:20]
|
|
node _T_379 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59]
|
|
node _T_380 = and(dmcontrol_wren_Q, _T_379) @[dbg.scala 293:44]
|
|
node _T_381 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81]
|
|
node _T_382 = not(_T_381) @[dbg.scala 293:67]
|
|
node _T_383 = and(_T_380, _T_382) @[dbg.scala 293:64]
|
|
node _T_384 = bits(_T_383, 0, 0) @[dbg.scala 293:102]
|
|
io.dbg_halt_req <= _T_384 @[dbg.scala 293:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_385 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_385 : @[Conditional.scala 39:67]
|
|
node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40]
|
|
node _T_387 = mux(_T_386, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 296:26]
|
|
dbg_nxtstate <= _T_387 @[dbg.scala 296:20]
|
|
node _T_388 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 297:59]
|
|
node _T_389 = or(io.core_dbg_cmd_done, _T_388) @[dbg.scala 297:44]
|
|
dbg_state_en <= _T_389 @[dbg.scala 297:20]
|
|
node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 298:59]
|
|
node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 298:44]
|
|
node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 298:81]
|
|
node _T_393 = not(_T_392) @[dbg.scala 298:67]
|
|
node _T_394 = and(_T_391, _T_393) @[dbg.scala 298:64]
|
|
node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 298:102]
|
|
io.dbg_halt_req <= _T_395 @[dbg.scala 298:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_396 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_396 : @[Conditional.scala 39:67]
|
|
node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 301:40]
|
|
node _T_398 = mux(_T_397, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 301:26]
|
|
dbg_nxtstate <= _T_398 @[dbg.scala 301:20]
|
|
dbg_state_en <= UInt<1>("h01") @[dbg.scala 302:20]
|
|
abstractcs_busy_wren <= dbg_state_en @[dbg.scala 303:28]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 304:27]
|
|
node _T_399 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59]
|
|
node _T_400 = and(dmcontrol_wren_Q, _T_399) @[dbg.scala 305:44]
|
|
node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81]
|
|
node _T_402 = not(_T_401) @[dbg.scala 305:67]
|
|
node _T_403 = and(_T_400, _T_402) @[dbg.scala 305:64]
|
|
node _T_404 = bits(_T_403, 0, 0) @[dbg.scala 305:102]
|
|
io.dbg_halt_req <= _T_404 @[dbg.scala 305:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_405 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_405 : @[Conditional.scala 39:67]
|
|
dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 308:20]
|
|
node _T_406 = bits(dmstatus_reg, 17, 17) @[dbg.scala 309:35]
|
|
node _T_407 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 309:55]
|
|
node _T_408 = or(_T_406, _T_407) @[dbg.scala 309:40]
|
|
dbg_state_en <= _T_408 @[dbg.scala 309:20]
|
|
node _T_409 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 310:59]
|
|
node _T_410 = and(dmcontrol_wren_Q, _T_409) @[dbg.scala 310:44]
|
|
node _T_411 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 310:81]
|
|
node _T_412 = not(_T_411) @[dbg.scala 310:67]
|
|
node _T_413 = and(_T_410, _T_412) @[dbg.scala 310:64]
|
|
node _T_414 = bits(_T_413, 0, 0) @[dbg.scala 310:102]
|
|
io.dbg_halt_req <= _T_414 @[dbg.scala 310:23]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_415 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 313:52]
|
|
node _T_416 = bits(_T_415, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_417 = mux(_T_416, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_418 = and(_T_417, data0_reg) @[dbg.scala 313:71]
|
|
node _T_419 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 313:110]
|
|
node _T_420 = bits(_T_419, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_421 = mux(_T_420, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_422 = and(_T_421, data1_reg) @[dbg.scala 313:122]
|
|
node _T_423 = or(_T_418, _T_422) @[dbg.scala 313:83]
|
|
node _T_424 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 314:30]
|
|
node _T_425 = bits(_T_424, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_426 = mux(_T_425, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_427 = and(_T_426, dmcontrol_reg) @[dbg.scala 314:43]
|
|
node _T_428 = or(_T_423, _T_427) @[dbg.scala 313:134]
|
|
node _T_429 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 314:86]
|
|
node _T_430 = bits(_T_429, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_431 = mux(_T_430, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_432 = and(_T_431, dmstatus_reg) @[dbg.scala 314:99]
|
|
node _T_433 = or(_T_428, _T_432) @[dbg.scala 314:59]
|
|
node _T_434 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 315:30]
|
|
node _T_435 = bits(_T_434, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_436 = mux(_T_435, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_437 = and(_T_436, abstractcs_reg) @[dbg.scala 315:43]
|
|
node _T_438 = or(_T_433, _T_437) @[dbg.scala 314:114]
|
|
node _T_439 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 315:87]
|
|
node _T_440 = bits(_T_439, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_441 = mux(_T_440, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_442 = and(_T_441, command_reg) @[dbg.scala 315:100]
|
|
node _T_443 = or(_T_438, _T_442) @[dbg.scala 315:60]
|
|
node _T_444 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 316:30]
|
|
node _T_445 = bits(_T_444, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_446 = mux(_T_445, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_447 = and(_T_446, haltsum0_reg) @[dbg.scala 316:43]
|
|
node _T_448 = or(_T_443, _T_447) @[dbg.scala 315:114]
|
|
node _T_449 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 316:85]
|
|
node _T_450 = bits(_T_449, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_451 = mux(_T_450, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_452 = and(_T_451, sbcs_reg) @[dbg.scala 316:98]
|
|
node _T_453 = or(_T_448, _T_452) @[dbg.scala 316:58]
|
|
node _T_454 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 317:30]
|
|
node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_457 = and(_T_456, sbaddress0_reg) @[dbg.scala 317:43]
|
|
node _T_458 = or(_T_453, _T_457) @[dbg.scala 316:109]
|
|
node _T_459 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 317:87]
|
|
node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_461 = mux(_T_460, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_462 = and(_T_461, sbdata0_reg) @[dbg.scala 317:100]
|
|
node _T_463 = or(_T_458, _T_462) @[dbg.scala 317:60]
|
|
node _T_464 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 318:30]
|
|
node _T_465 = bits(_T_464, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_467 = and(_T_466, sbdata1_reg) @[dbg.scala 318:43]
|
|
node dmi_reg_rdata_din = or(_T_463, _T_467) @[dbg.scala 317:114]
|
|
reg _T_468 : UInt, rvclkhdr.io.l1clk with : (reset => (rst_temp, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dbg_state_en : @[Reg.scala 28:19]
|
|
_T_468 <= dbg_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dbg_state <= _T_468 @[dbg.scala 320:13]
|
|
reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when io.dmi_reg_en : @[Reg.scala 28:19]
|
|
_T_469 <= dmi_reg_rdata_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.dmi_reg_rdata <= _T_469 @[dbg.scala 325:20]
|
|
node _T_470 = bits(command_reg, 31, 24) @[dbg.scala 329:53]
|
|
node _T_471 = eq(_T_470, UInt<2>("h02")) @[dbg.scala 329:62]
|
|
node _T_472 = bits(data1_reg, 31, 2) @[dbg.scala 329:88]
|
|
node _T_473 = cat(_T_472, UInt<2>("h00")) @[Cat.scala 29:58]
|
|
node _T_474 = bits(command_reg, 11, 0) @[dbg.scala 329:138]
|
|
node _T_475 = cat(UInt<20>("h00"), _T_474) @[Cat.scala 29:58]
|
|
node _T_476 = mux(_T_471, _T_473, _T_475) @[dbg.scala 329:40]
|
|
io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_476 @[dbg.scala 329:34]
|
|
node _T_477 = bits(data0_reg, 31, 0) @[dbg.scala 330:50]
|
|
io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_477 @[dbg.scala 330:38]
|
|
node _T_478 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 331:50]
|
|
node _T_479 = bits(abstractcs_reg, 10, 8) @[dbg.scala 331:91]
|
|
node _T_480 = orr(_T_479) @[dbg.scala 331:99]
|
|
node _T_481 = eq(_T_480, UInt<1>("h00")) @[dbg.scala 331:75]
|
|
node _T_482 = and(_T_478, _T_481) @[dbg.scala 331:73]
|
|
node _T_483 = and(_T_482, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 331:104]
|
|
node _T_484 = bits(_T_483, 0, 0) @[dbg.scala 331:141]
|
|
io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_484 @[dbg.scala 331:35]
|
|
node _T_485 = bits(command_reg, 16, 16) @[dbg.scala 332:49]
|
|
node _T_486 = bits(_T_485, 0, 0) @[dbg.scala 332:60]
|
|
io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_486 @[dbg.scala 332:35]
|
|
node _T_487 = bits(command_reg, 31, 24) @[dbg.scala 333:53]
|
|
node _T_488 = eq(_T_487, UInt<2>("h02")) @[dbg.scala 333:62]
|
|
node _T_489 = bits(command_reg, 15, 12) @[dbg.scala 333:113]
|
|
node _T_490 = eq(_T_489, UInt<1>("h00")) @[dbg.scala 333:122]
|
|
node _T_491 = cat(UInt<1>("h00"), _T_490) @[Cat.scala 29:58]
|
|
node _T_492 = mux(_T_488, UInt<2>("h02"), _T_491) @[dbg.scala 333:40]
|
|
io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_492 @[dbg.scala 333:34]
|
|
node _T_493 = bits(command_reg, 21, 20) @[dbg.scala 334:33]
|
|
io.dbg_cmd_size <= _T_493 @[dbg.scala 334:19]
|
|
node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 335:47]
|
|
node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 335:88]
|
|
node _T_496 = orr(_T_495) @[dbg.scala 335:96]
|
|
node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 335:72]
|
|
node _T_498 = and(_T_494, _T_497) @[dbg.scala 335:70]
|
|
node _T_499 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 335:114]
|
|
node _T_500 = or(_T_498, _T_499) @[dbg.scala 335:101]
|
|
node _T_501 = bits(_T_500, 0, 0) @[dbg.scala 335:143]
|
|
io.dbg_dma_io.dbg_dma_bubble <= _T_501 @[dbg.scala 335:32]
|
|
wire sb_nxtstate : UInt<4>
|
|
sb_nxtstate <= UInt<4>("h00")
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 338:15]
|
|
sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 340:20]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 341:19]
|
|
sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 342:21]
|
|
sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 343:20]
|
|
sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 344:24]
|
|
node _T_502 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_502 : @[Conditional.scala 40:58]
|
|
node _T_503 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 347:25]
|
|
sb_nxtstate <= _T_503 @[dbg.scala 347:19]
|
|
node _T_504 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 348:39]
|
|
node _T_505 = or(_T_504, sbreadonaddr_access) @[dbg.scala 348:61]
|
|
sb_state_en <= _T_505 @[dbg.scala 348:19]
|
|
sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 349:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 350:23]
|
|
node _T_506 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 351:56]
|
|
node _T_507 = orr(_T_506) @[dbg.scala 351:65]
|
|
node _T_508 = and(sbcs_wren, _T_507) @[dbg.scala 351:38]
|
|
sbcs_sberror_wren <= _T_508 @[dbg.scala 351:25]
|
|
node _T_509 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 352:44]
|
|
node _T_510 = not(_T_509) @[dbg.scala 352:27]
|
|
node _T_511 = bits(sbcs_reg, 14, 12) @[dbg.scala 352:63]
|
|
node _T_512 = and(_T_510, _T_511) @[dbg.scala 352:53]
|
|
sbcs_sberror_din <= _T_512 @[dbg.scala 352:24]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_513 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_513 : @[Conditional.scala 39:67]
|
|
node _T_514 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 355:41]
|
|
node _T_515 = mux(_T_514, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 355:25]
|
|
sb_nxtstate <= _T_515 @[dbg.scala 355:19]
|
|
node _T_516 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 356:40]
|
|
node _T_517 = or(_T_516, sbcs_illegal_size) @[dbg.scala 356:57]
|
|
sb_state_en <= _T_517 @[dbg.scala 356:19]
|
|
node _T_518 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 357:43]
|
|
sbcs_sberror_wren <= _T_518 @[dbg.scala 357:25]
|
|
node _T_519 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 358:30]
|
|
sbcs_sberror_din <= _T_519 @[dbg.scala 358:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_520 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_520 : @[Conditional.scala 39:67]
|
|
node _T_521 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 361:41]
|
|
node _T_522 = mux(_T_521, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 361:25]
|
|
sb_nxtstate <= _T_522 @[dbg.scala 361:19]
|
|
node _T_523 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 362:40]
|
|
node _T_524 = or(_T_523, sbcs_illegal_size) @[dbg.scala 362:57]
|
|
sb_state_en <= _T_524 @[dbg.scala 362:19]
|
|
node _T_525 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 363:43]
|
|
sbcs_sberror_wren <= _T_525 @[dbg.scala 363:25]
|
|
node _T_526 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 364:30]
|
|
sbcs_sberror_din <= _T_526 @[dbg.scala 364:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_527 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_527 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h07") @[dbg.scala 367:19]
|
|
node _T_528 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 368:38]
|
|
sb_state_en <= _T_528 @[dbg.scala 368:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_529 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_529 : @[Conditional.scala 39:67]
|
|
node _T_530 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 371:48]
|
|
node _T_531 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 371:95]
|
|
node _T_532 = mux(_T_530, UInt<4>("h08"), _T_531) @[dbg.scala 371:25]
|
|
sb_nxtstate <= _T_532 @[dbg.scala 371:19]
|
|
node _T_533 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 372:45]
|
|
node _T_534 = and(_T_533, io.dbg_bus_clk_en) @[dbg.scala 372:70]
|
|
sb_state_en <= _T_534 @[dbg.scala 372:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_535 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_535 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 375:19]
|
|
node _T_536 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 376:44]
|
|
sb_state_en <= _T_536 @[dbg.scala 376:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_537 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_537 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 379:19]
|
|
node _T_538 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 380:44]
|
|
sb_state_en <= _T_538 @[dbg.scala 380:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_539 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_539 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 383:19]
|
|
node _T_540 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 384:38]
|
|
sb_state_en <= _T_540 @[dbg.scala 384:19]
|
|
node _T_541 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 385:40]
|
|
sbcs_sberror_wren <= _T_541 @[dbg.scala 385:25]
|
|
sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 386:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_542 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_542 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 389:19]
|
|
node _T_543 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 390:39]
|
|
sb_state_en <= _T_543 @[dbg.scala 390:19]
|
|
node _T_544 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 391:40]
|
|
sbcs_sberror_wren <= _T_544 @[dbg.scala 391:25]
|
|
sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 392:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_545 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_545 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 395:19]
|
|
sb_state_en <= UInt<1>("h01") @[dbg.scala 396:19]
|
|
sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 397:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 398:23]
|
|
node _T_546 = bits(sbcs_reg, 16, 16) @[dbg.scala 399:39]
|
|
sbaddress0_reg_wren1 <= _T_546 @[dbg.scala 399:28]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_547 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when sb_state_en : @[Reg.scala 28:19]
|
|
_T_547 <= sb_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
sb_state <= _T_547 @[dbg.scala 402:12]
|
|
node _T_548 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 406:41]
|
|
sb_bus_cmd_read <= _T_548 @[dbg.scala 406:19]
|
|
node _T_549 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 407:47]
|
|
sb_bus_cmd_write_addr <= _T_549 @[dbg.scala 407:25]
|
|
node _T_550 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 408:46]
|
|
sb_bus_cmd_write_data <= _T_550 @[dbg.scala 408:25]
|
|
node _T_551 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 409:40]
|
|
sb_bus_rsp_read <= _T_551 @[dbg.scala 409:19]
|
|
node _T_552 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 410:41]
|
|
sb_bus_rsp_write <= _T_552 @[dbg.scala 410:20]
|
|
node _T_553 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 411:62]
|
|
node _T_554 = orr(_T_553) @[dbg.scala 411:69]
|
|
node _T_555 = and(sb_bus_rsp_read, _T_554) @[dbg.scala 411:39]
|
|
node _T_556 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 411:115]
|
|
node _T_557 = orr(_T_556) @[dbg.scala 411:122]
|
|
node _T_558 = and(sb_bus_rsp_write, _T_557) @[dbg.scala 411:92]
|
|
node _T_559 = or(_T_555, _T_558) @[dbg.scala 411:73]
|
|
sb_bus_rsp_error <= _T_559 @[dbg.scala 411:20]
|
|
node _T_560 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 412:36]
|
|
node _T_561 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 412:71]
|
|
node _T_562 = or(_T_560, _T_561) @[dbg.scala 412:59]
|
|
node _T_563 = bits(_T_562, 0, 0) @[dbg.scala 412:106]
|
|
io.sb_axi.aw.valid <= _T_563 @[dbg.scala 412:22]
|
|
io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 413:26]
|
|
io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 414:24]
|
|
node _T_564 = bits(sbcs_reg, 19, 17) @[dbg.scala 415:37]
|
|
io.sb_axi.aw.bits.size <= _T_564 @[dbg.scala 415:26]
|
|
io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 416:26]
|
|
io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 417:27]
|
|
node _T_565 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 418:45]
|
|
io.sb_axi.aw.bits.region <= _T_565 @[dbg.scala 418:28]
|
|
io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 419:25]
|
|
io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 420:27]
|
|
io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 421:25]
|
|
io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 422:26]
|
|
node _T_566 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 423:35]
|
|
node _T_567 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 423:70]
|
|
node _T_568 = or(_T_566, _T_567) @[dbg.scala 423:58]
|
|
node _T_569 = bits(_T_568, 0, 0) @[dbg.scala 423:105]
|
|
io.sb_axi.w.valid <= _T_569 @[dbg.scala 423:21]
|
|
node _T_570 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:46]
|
|
node _T_571 = eq(_T_570, UInt<1>("h00")) @[dbg.scala 424:55]
|
|
node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_573 = mux(_T_572, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_574 = bits(sbdata0_reg, 7, 0) @[dbg.scala 424:87]
|
|
node _T_575 = cat(_T_574, _T_574) @[Cat.scala 29:58]
|
|
node _T_576 = cat(_T_575, _T_575) @[Cat.scala 29:58]
|
|
node _T_577 = cat(_T_576, _T_576) @[Cat.scala 29:58]
|
|
node _T_578 = and(_T_573, _T_577) @[dbg.scala 424:65]
|
|
node _T_579 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:116]
|
|
node _T_580 = eq(_T_579, UInt<1>("h01")) @[dbg.scala 424:125]
|
|
node _T_581 = bits(_T_580, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_582 = mux(_T_581, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_583 = bits(sbdata0_reg, 15, 0) @[dbg.scala 424:159]
|
|
node _T_584 = cat(_T_583, _T_583) @[Cat.scala 29:58]
|
|
node _T_585 = cat(_T_584, _T_584) @[Cat.scala 29:58]
|
|
node _T_586 = and(_T_582, _T_585) @[dbg.scala 424:138]
|
|
node _T_587 = or(_T_578, _T_586) @[dbg.scala 424:96]
|
|
node _T_588 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:23]
|
|
node _T_589 = eq(_T_588, UInt<2>("h02")) @[dbg.scala 425:32]
|
|
node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_591 = mux(_T_590, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_592 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:67]
|
|
node _T_593 = cat(_T_592, _T_592) @[Cat.scala 29:58]
|
|
node _T_594 = and(_T_591, _T_593) @[dbg.scala 425:45]
|
|
node _T_595 = or(_T_587, _T_594) @[dbg.scala 424:168]
|
|
node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:97]
|
|
node _T_597 = eq(_T_596, UInt<2>("h03")) @[dbg.scala 425:106]
|
|
node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_599 = mux(_T_598, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_600 = bits(sbdata1_reg, 31, 0) @[dbg.scala 425:136]
|
|
node _T_601 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:156]
|
|
node _T_602 = cat(_T_600, _T_601) @[Cat.scala 29:58]
|
|
node _T_603 = and(_T_599, _T_602) @[dbg.scala 425:119]
|
|
node _T_604 = or(_T_595, _T_603) @[dbg.scala 425:77]
|
|
io.sb_axi.w.bits.data <= _T_604 @[dbg.scala 424:25]
|
|
node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:45]
|
|
node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 427:54]
|
|
node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_608 = mux(_T_607, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_609 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 427:99]
|
|
node _T_610 = dshl(UInt<8>("h01"), _T_609) @[dbg.scala 427:82]
|
|
node _T_611 = and(_T_608, _T_610) @[dbg.scala 427:67]
|
|
node _T_612 = bits(sbcs_reg, 19, 17) @[dbg.scala 428:22]
|
|
node _T_613 = eq(_T_612, UInt<1>("h01")) @[dbg.scala 428:31]
|
|
node _T_614 = bits(_T_613, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_615 = mux(_T_614, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_616 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 428:80]
|
|
node _T_617 = cat(_T_616, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_618 = dshl(UInt<8>("h03"), _T_617) @[dbg.scala 428:59]
|
|
node _T_619 = and(_T_615, _T_618) @[dbg.scala 428:44]
|
|
node _T_620 = or(_T_611, _T_619) @[dbg.scala 427:107]
|
|
node _T_621 = bits(sbcs_reg, 19, 17) @[dbg.scala 429:22]
|
|
node _T_622 = eq(_T_621, UInt<2>("h02")) @[dbg.scala 429:31]
|
|
node _T_623 = bits(_T_622, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_624 = mux(_T_623, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_625 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 429:80]
|
|
node _T_626 = cat(_T_625, UInt<2>("h00")) @[Cat.scala 29:58]
|
|
node _T_627 = dshl(UInt<8>("h0f"), _T_626) @[dbg.scala 429:59]
|
|
node _T_628 = and(_T_624, _T_627) @[dbg.scala 429:44]
|
|
node _T_629 = or(_T_620, _T_628) @[dbg.scala 428:97]
|
|
node _T_630 = bits(sbcs_reg, 19, 17) @[dbg.scala 430:22]
|
|
node _T_631 = eq(_T_630, UInt<2>("h03")) @[dbg.scala 430:31]
|
|
node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_633 = mux(_T_632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_634 = and(_T_633, UInt<8>("h0ff")) @[dbg.scala 430:44]
|
|
node _T_635 = or(_T_629, _T_634) @[dbg.scala 429:100]
|
|
io.sb_axi.w.bits.strb <= _T_635 @[dbg.scala 427:25]
|
|
io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 432:25]
|
|
node _T_636 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 433:35]
|
|
node _T_637 = bits(_T_636, 0, 0) @[dbg.scala 433:64]
|
|
io.sb_axi.ar.valid <= _T_637 @[dbg.scala 433:22]
|
|
io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 434:26]
|
|
io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 435:24]
|
|
node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 436:37]
|
|
io.sb_axi.ar.bits.size <= _T_638 @[dbg.scala 436:26]
|
|
io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 437:26]
|
|
io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 438:27]
|
|
node _T_639 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 439:45]
|
|
io.sb_axi.ar.bits.region <= _T_639 @[dbg.scala 439:28]
|
|
io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 440:25]
|
|
io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 441:27]
|
|
io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 442:25]
|
|
io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 443:26]
|
|
io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 444:21]
|
|
io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 445:21]
|
|
node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 446:37]
|
|
node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 446:46]
|
|
node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_643 = mux(_T_642, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_644 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 446:84]
|
|
node _T_645 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 446:115]
|
|
node _T_646 = mul(UInt<4>("h08"), _T_645) @[dbg.scala 446:99]
|
|
node _T_647 = dshr(_T_644, _T_646) @[dbg.scala 446:92]
|
|
node _T_648 = and(_T_647, UInt<64>("h0ff")) @[dbg.scala 446:123]
|
|
node _T_649 = and(_T_643, _T_648) @[dbg.scala 446:59]
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node _T_650 = bits(sbcs_reg, 19, 17) @[dbg.scala 447:23]
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node _T_651 = eq(_T_650, UInt<1>("h01")) @[dbg.scala 447:32]
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node _T_652 = bits(_T_651, 0, 0) @[Bitwise.scala 72:15]
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node _T_653 = mux(_T_652, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_654 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 447:70]
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node _T_655 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 447:102]
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node _T_656 = mul(UInt<5>("h010"), _T_655) @[dbg.scala 447:86]
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node _T_657 = dshr(_T_654, _T_656) @[dbg.scala 447:78]
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node _T_658 = and(_T_657, UInt<64>("h0ffff")) @[dbg.scala 447:110]
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node _T_659 = and(_T_653, _T_658) @[dbg.scala 447:45]
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node _T_660 = or(_T_649, _T_659) @[dbg.scala 446:140]
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node _T_661 = bits(sbcs_reg, 19, 17) @[dbg.scala 448:23]
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node _T_662 = eq(_T_661, UInt<2>("h02")) @[dbg.scala 448:32]
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node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15]
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node _T_664 = mux(_T_663, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_665 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 448:70]
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node _T_666 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 448:102]
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node _T_667 = mul(UInt<6>("h020"), _T_666) @[dbg.scala 448:86]
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node _T_668 = dshr(_T_665, _T_667) @[dbg.scala 448:78]
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node _T_669 = and(_T_668, UInt<64>("h0ffffffff")) @[dbg.scala 448:107]
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node _T_670 = and(_T_664, _T_669) @[dbg.scala 448:45]
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node _T_671 = or(_T_660, _T_670) @[dbg.scala 447:129]
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node _T_672 = bits(sbcs_reg, 19, 17) @[dbg.scala 449:23]
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node _T_673 = eq(_T_672, UInt<2>("h03")) @[dbg.scala 449:32]
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node _T_674 = bits(_T_673, 0, 0) @[Bitwise.scala 72:15]
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node _T_675 = mux(_T_674, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_676 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 449:68]
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node _T_677 = and(_T_675, _T_676) @[dbg.scala 449:45]
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node _T_678 = or(_T_671, _T_677) @[dbg.scala 448:131]
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sb_bus_rdata <= _T_678 @[dbg.scala 446:16]
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io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 452:39]
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io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 453:39]
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io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 454:39]
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io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 455:39]
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io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 456:39]
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