48 lines
2.0 KiB
Verilog
48 lines
2.0 KiB
Verilog
module el2_ifu_ifc_ctrl(
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input clock,
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input reset,
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input io_free_clk,
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input io_active_clk,
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input io_rst_l,
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input io_scan_mode,
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input io_ic_hit_f,
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input io_ifu_ic_mb_empty,
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input io_ifu_fb_consume1,
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input io_ifu_fb_consume2,
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input io_dec_tlu_flush_noredir_wb,
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input io_exu_flush_final,
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input [31:0] io_exu_flush_path_final,
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input io_ifu_bp_hit_taken_f,
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input [31:0] io_ifu_bp_btb_target_f,
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input io_ic_dma_active,
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input io_ic_write_stall,
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input io_dma_iccm_stall_any,
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input [31:0] io_dec_tlu_mrac_ff,
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output [31:0] io_ifc_fetch_addr_f,
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output [31:0] io_ifc_fetch_addr_bf,
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output io_ifc_fetch_req_f,
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output io_ifu_pmu_fetch_stall,
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output io_ifc_fetch_uncacheable_bf,
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output io_ifc_fetch_req_bf,
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output io_ifc_fetch_req_bf_raw,
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output io_ifc_iccm_access_bf,
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output io_ifc_region_acc_fault_bf,
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output io_ifc_dma_access_ok,
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input io_testin,
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output [31:0] io_test1
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);
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wire [29:0] _T_35 = io_ifc_fetch_addr_f[31:2] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 88:53]
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wire [30:0] _T_36 = {_T_35,1'h0}; // @[Cat.scala 29:58]
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assign io_ifc_fetch_addr_f = 32'h0; // @[el2_ifu_ifc_ctrl.scala 39:23]
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assign io_ifc_fetch_addr_bf = 32'h0; // @[el2_ifu_ifc_ctrl.scala 40:24]
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assign io_ifc_fetch_req_f = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:22]
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assign io_ifu_pmu_fetch_stall = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:26]
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assign io_ifc_fetch_uncacheable_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:31]
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assign io_ifc_fetch_req_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 44:23]
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assign io_ifc_fetch_req_bf_raw = 1'h0; // @[el2_ifu_ifc_ctrl.scala 45:27]
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assign io_ifc_iccm_access_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 46:25]
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assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 47:30]
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assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 48:24]
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assign io_test1 = {{1'd0}, _T_36}; // @[el2_ifu_ifc_ctrl.scala 89:12]
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endmodule
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