11 lines
326 B
Verilog
11 lines
326 B
Verilog
module test(
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input clock,
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input reset,
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input [31:0] io_addr,
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output io_in_range,
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output io_in_region
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);
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assign io_in_range = io_addr[31:28] == 4'he; // @[el2_ifu_ifc_ctrl.scala 143:15]
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assign io_in_region = io_addr[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 142:16]
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endmodule
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