quasar/ifu.anno.json

[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_premux_data",
    "sources":[
      "~ifu|ifu>io_iccm_rd_data",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_wr_size",
    "sources":[
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_sz",
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_rw_addr",
    "sources":[
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_addr",
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_dec_i0_decode_d",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_sel_premux_data",
    "sources":[
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_wr_data",
    "sources":[
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_wdata",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_dec_i0_decode_d",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
    "sources":[
      "~ifu|ifu>io_dec_i0_decode_d"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_wr_data",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_rd_en",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_wr_en",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_addr",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_ready",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_dec_i0_decode_d",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_tag_array",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
    "sources":[
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
    "sources":[
      "~ifu|ifu>io_ic_eccerr",
      "~ifu|ifu>io_ic_tag_perr",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_rden",
    "sources":[
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_dec_i0_decode_d"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_debug_way",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_rw_addr",
    "sources":[
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_ic_rd_hit"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ic_rd_en",
    "sources":[
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_dec_i0_decode_d"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_wren",
    "sources":[
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
      "~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
      "~ifu|ifu>io_exu_flush_path_final",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
      "~ifu|ifu>io_dec_i0_decode_d",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
    "sources":[
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
      "~ifu|ifu>io_ic_rd_data",
      "~ifu|ifu>io_ifu_r_bits_id",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_r_valid",
      "~ifu|ifu>io_ifu_bus_clk_en",
      "~ifu|ifu>io_dec_i0_decode_d",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~ifu|ifu>io_iccm_dma_sb_error",
    "sources":[
      "~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
      "~ifu|ifu>io_iccm_rd_data_ecc",
      "~ifu|ifu>io_exu_flush_final",
      "~ifu|ifu>io_ic_rd_hit",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
      "~ifu|ifu>io_dec_tlu_flush_lower_wb",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
      "~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
      "~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxResourceAnno",
    "target":"ifu.gated_latch",
    "resourceId":"/vsrc/gated_latch.sv"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~ifu|ifu_mem_ctl>ifc_region_acc_okay"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"ifu"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]