13634 lines
934 KiB
Plaintext
13634 lines
934 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_mem_ctl :
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extmodule TEC_RV_ICG :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_8 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_8 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_9 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_9 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_10 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_10 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_11 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_11 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_12 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_12 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_13 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_13 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_14 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_14 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_15 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_15 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_16 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_16 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_17 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_17 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_18 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_18 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 408:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
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clkhdr.EN <= io.en @[el2_lib.scala 411:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
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extmodule TEC_RV_ICG_19 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_19 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_20 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_20 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_21 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_21 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_22 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_22 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_23 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_23 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_24 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_24 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
extmodule TEC_RV_ICG_25 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = TEC_RV_ICG
|
|
|
|
|
|
module rvclkhdr_25 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 408:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 409:14]
|
|
clkhdr.CK <= io.clk @[el2_lib.scala 410:18]
|
|
clkhdr.EN <= io.en @[el2_lib.scala 411:18]
|
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 412:18]
|
|
|
|
module el2_ifu_mem_ctl :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:20]
|
|
io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:20]
|
|
io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:24]
|
|
io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:25]
|
|
io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:21]
|
|
io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:19]
|
|
io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
|
|
io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21]
|
|
io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:20]
|
|
io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:23]
|
|
io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:22]
|
|
io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:22]
|
|
io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:21]
|
|
io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:18]
|
|
io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
|
|
io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:19]
|
|
io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
|
|
io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
|
|
io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
|
|
io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:21]
|
|
io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
|
|
io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
|
|
io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:20]
|
|
io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
|
|
io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:19]
|
|
io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:19]
|
|
io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:20]
|
|
io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:21]
|
|
io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:19]
|
|
io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:18]
|
|
io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:20]
|
|
io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:22]
|
|
io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:19]
|
|
io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
|
|
io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
|
|
io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
|
|
io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:21]
|
|
io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
|
|
io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:19]
|
|
io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:20]
|
|
io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:24]
|
|
io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:21]
|
|
io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:20]
|
|
io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:19]
|
|
io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:16]
|
|
io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:16]
|
|
io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:14]
|
|
io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:14]
|
|
io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
|
|
io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
|
|
io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:22]
|
|
io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:26]
|
|
io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:18]
|
|
io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:18]
|
|
io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:15]
|
|
io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:15]
|
|
io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:18]
|
|
io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:18]
|
|
io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:14]
|
|
io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:23]
|
|
io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
|
|
io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:28]
|
|
io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:28]
|
|
io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:20]
|
|
io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:27]
|
|
io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:23]
|
|
io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
|
|
io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:15]
|
|
io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:20]
|
|
io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:24]
|
|
io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:32]
|
|
io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:26]
|
|
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:27]
|
|
io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 200:18]
|
|
io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 201:22]
|
|
wire iccm_single_ecc_error : UInt<2>
|
|
iccm_single_ecc_error <= UInt<1>("h00")
|
|
wire ifc_fetch_req_f : UInt<1>
|
|
ifc_fetch_req_f <= UInt<1>("h00")
|
|
wire miss_pending : UInt<1>
|
|
miss_pending <= UInt<1>("h00")
|
|
wire scnd_miss_req : UInt<1>
|
|
scnd_miss_req <= UInt<1>("h00")
|
|
wire dma_iccm_req_f : UInt<1>
|
|
dma_iccm_req_f <= UInt<1>("h00")
|
|
wire iccm_correct_ecc : UInt<1>
|
|
iccm_correct_ecc <= UInt<1>("h00")
|
|
wire perr_state : UInt<3>
|
|
perr_state <= UInt<1>("h00")
|
|
wire err_stop_state : UInt<2>
|
|
err_stop_state <= UInt<1>("h00")
|
|
wire err_stop_fetch : UInt<1>
|
|
err_stop_fetch <= UInt<1>("h00")
|
|
wire miss_state : UInt<3>
|
|
miss_state <= UInt<1>("h00")
|
|
wire miss_nxtstate : UInt<3>
|
|
miss_nxtstate <= UInt<1>("h00")
|
|
wire miss_state_en : UInt<1>
|
|
miss_state_en <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_valid : UInt<1>
|
|
ifu_bus_rsp_valid <= UInt<1>("h00")
|
|
wire bus_ifu_bus_clk_en : UInt<1>
|
|
bus_ifu_bus_clk_en <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_ready : UInt<1>
|
|
ifu_bus_rsp_ready <= UInt<1>("h00")
|
|
wire uncacheable_miss_ff : UInt<1>
|
|
uncacheable_miss_ff <= UInt<1>("h00")
|
|
wire ic_act_miss_f : UInt<1>
|
|
ic_act_miss_f <= UInt<1>("h00")
|
|
wire ic_byp_hit_f : UInt<1>
|
|
ic_byp_hit_f <= UInt<1>("h00")
|
|
wire bus_new_data_beat_count : UInt<3>
|
|
bus_new_data_beat_count <= UInt<1>("h00")
|
|
wire bus_ifu_wr_en_ff : UInt<1>
|
|
bus_ifu_wr_en_ff <= UInt<1>("h00")
|
|
wire last_beat : UInt<1>
|
|
last_beat <= UInt<1>("h00")
|
|
wire last_data_recieved_ff : UInt<1>
|
|
last_data_recieved_ff <= UInt<1>("h00")
|
|
wire stream_eol_f : UInt<1>
|
|
stream_eol_f <= UInt<1>("h00")
|
|
wire ic_miss_under_miss_f : UInt<1>
|
|
ic_miss_under_miss_f <= UInt<1>("h00")
|
|
wire ic_ignore_2nd_miss_f : UInt<1>
|
|
ic_ignore_2nd_miss_f <= UInt<1>("h00")
|
|
reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 234:30]
|
|
flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 234:30]
|
|
node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 235:53]
|
|
node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 235:71]
|
|
node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 235:86]
|
|
node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 235:107]
|
|
node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 236:42]
|
|
inst rvclkhdr of rvclkhdr @[el2_lib.scala 417:22]
|
|
rvclkhdr.clock <= clock
|
|
rvclkhdr.reset <= reset
|
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr.io.en <= debug_c1_clken @[el2_lib.scala 419:16]
|
|
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_3 = bits(fetch_bf_f_c1_clken, 0, 0) @[el2_ifu_mem_ctl.scala 238:63]
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 417:22]
|
|
rvclkhdr_1.clock <= clock
|
|
rvclkhdr_1.reset <= reset
|
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_1.io.en <= _T_3 @[el2_lib.scala 419:16]
|
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_4 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 239:52]
|
|
node _T_5 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 239:78]
|
|
node _T_6 = and(_T_4, _T_5) @[el2_ifu_mem_ctl.scala 239:55]
|
|
io.iccm_dma_sb_error <= _T_6 @[el2_ifu_mem_ctl.scala 239:24]
|
|
node _T_7 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 240:57]
|
|
io.ifu_async_error_start <= _T_7 @[el2_ifu_mem_ctl.scala 240:28]
|
|
node _T_8 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 241:54]
|
|
node _T_9 = or(iccm_correct_ecc, _T_8) @[el2_ifu_mem_ctl.scala 241:40]
|
|
node _T_10 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 241:90]
|
|
node _T_11 = or(_T_9, _T_10) @[el2_ifu_mem_ctl.scala 241:72]
|
|
node _T_12 = or(_T_11, err_stop_fetch) @[el2_ifu_mem_ctl.scala 241:112]
|
|
node _T_13 = or(_T_12, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 241:129]
|
|
io.ic_dma_active <= _T_13 @[el2_ifu_mem_ctl.scala 241:20]
|
|
node _T_14 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 242:44]
|
|
node _T_15 = and(_T_14, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 242:65]
|
|
node _T_16 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 242:111]
|
|
node _T_17 = and(_T_15, _T_16) @[el2_ifu_mem_ctl.scala 242:85]
|
|
node _T_18 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:39]
|
|
node _T_19 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:71]
|
|
node _T_20 = or(_T_18, _T_19) @[el2_ifu_mem_ctl.scala 243:55]
|
|
node _T_21 = dshr(uncacheable_miss_ff, _T_20) @[el2_ifu_mem_ctl.scala 243:26]
|
|
node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_mem_ctl.scala 243:26]
|
|
node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:5]
|
|
node _T_24 = and(_T_17, _T_23) @[el2_ifu_mem_ctl.scala 242:116]
|
|
node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:91]
|
|
node scnd_miss_req_in = and(_T_24, _T_25) @[el2_ifu_mem_ctl.scala 243:89]
|
|
node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 245:52]
|
|
node _T_26 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_26 : @[Conditional.scala 40:58]
|
|
node _T_27 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 249:45]
|
|
node _T_28 = and(ic_act_miss_f, _T_27) @[el2_ifu_mem_ctl.scala 249:43]
|
|
node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_mem_ctl.scala 249:66]
|
|
node _T_30 = mux(_T_29, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 249:27]
|
|
miss_nxtstate <= _T_30 @[el2_ifu_mem_ctl.scala 249:21]
|
|
node _T_31 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:40]
|
|
node _T_32 = and(ic_act_miss_f, _T_31) @[el2_ifu_mem_ctl.scala 250:38]
|
|
miss_state_en <= _T_32 @[el2_ifu_mem_ctl.scala 250:21]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_33 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_33 : @[Conditional.scala 39:67]
|
|
node _T_34 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 252:112]
|
|
node _T_35 = or(last_data_recieved_ff, _T_34) @[el2_ifu_mem_ctl.scala 252:92]
|
|
node _T_36 = and(ic_byp_hit_f, _T_35) @[el2_ifu_mem_ctl.scala 252:66]
|
|
node _T_37 = and(_T_36, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 252:126]
|
|
node _T_38 = or(io.dec_tlu_force_halt, _T_37) @[el2_ifu_mem_ctl.scala 252:51]
|
|
node _T_39 = bits(_T_38, 0, 0) @[el2_ifu_mem_ctl.scala 252:150]
|
|
node _T_40 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 253:30]
|
|
node _T_41 = and(ic_byp_hit_f, _T_40) @[el2_ifu_mem_ctl.scala 253:27]
|
|
node _T_42 = and(_T_41, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 253:53]
|
|
node _T_43 = bits(_T_42, 0, 0) @[el2_ifu_mem_ctl.scala 253:77]
|
|
node _T_44 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:16]
|
|
node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:32]
|
|
node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 254:30]
|
|
node _T_47 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 254:72]
|
|
node _T_48 = and(_T_46, _T_47) @[el2_ifu_mem_ctl.scala 254:52]
|
|
node _T_49 = and(_T_48, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 254:85]
|
|
node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_mem_ctl.scala 254:109]
|
|
node _T_51 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 255:36]
|
|
node _T_52 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:51]
|
|
node _T_53 = and(_T_51, _T_52) @[el2_ifu_mem_ctl.scala 255:49]
|
|
node _T_54 = bits(_T_53, 0, 0) @[el2_ifu_mem_ctl.scala 255:73]
|
|
node _T_55 = or(ic_byp_hit_f, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 256:34]
|
|
node _T_56 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:56]
|
|
node _T_57 = and(_T_55, _T_56) @[el2_ifu_mem_ctl.scala 256:54]
|
|
node _T_58 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 256:97]
|
|
node _T_59 = eq(_T_58, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:78]
|
|
node _T_60 = and(_T_57, _T_59) @[el2_ifu_mem_ctl.scala 256:76]
|
|
node _T_61 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:112]
|
|
node _T_62 = and(_T_60, _T_61) @[el2_ifu_mem_ctl.scala 256:110]
|
|
node _T_63 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:136]
|
|
node _T_64 = and(_T_62, _T_63) @[el2_ifu_mem_ctl.scala 256:134]
|
|
node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_mem_ctl.scala 256:158]
|
|
node _T_66 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:22]
|
|
node _T_67 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:40]
|
|
node _T_68 = and(_T_66, _T_67) @[el2_ifu_mem_ctl.scala 257:37]
|
|
node _T_69 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 257:81]
|
|
node _T_70 = and(_T_68, _T_69) @[el2_ifu_mem_ctl.scala 257:60]
|
|
node _T_71 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:102]
|
|
node _T_72 = and(_T_70, _T_71) @[el2_ifu_mem_ctl.scala 257:100]
|
|
node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_mem_ctl.scala 257:124]
|
|
node _T_74 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 258:44]
|
|
node _T_75 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 258:89]
|
|
node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 258:70]
|
|
node _T_77 = and(_T_74, _T_76) @[el2_ifu_mem_ctl.scala 258:68]
|
|
node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_mem_ctl.scala 258:103]
|
|
node _T_79 = mux(_T_78, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 258:22]
|
|
node _T_80 = mux(_T_73, UInt<3>("h00"), _T_79) @[el2_ifu_mem_ctl.scala 257:20]
|
|
node _T_81 = mux(_T_65, UInt<3>("h06"), _T_80) @[el2_ifu_mem_ctl.scala 256:18]
|
|
node _T_82 = mux(_T_54, UInt<3>("h00"), _T_81) @[el2_ifu_mem_ctl.scala 255:16]
|
|
node _T_83 = mux(_T_50, UInt<3>("h01"), _T_82) @[el2_ifu_mem_ctl.scala 254:14]
|
|
node _T_84 = mux(_T_43, UInt<3>("h03"), _T_83) @[el2_ifu_mem_ctl.scala 253:12]
|
|
node _T_85 = mux(_T_39, UInt<3>("h00"), _T_84) @[el2_ifu_mem_ctl.scala 252:27]
|
|
miss_nxtstate <= _T_85 @[el2_ifu_mem_ctl.scala 252:21]
|
|
node _T_86 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 259:46]
|
|
node _T_87 = or(_T_86, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 259:67]
|
|
node _T_88 = or(_T_87, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 259:82]
|
|
node _T_89 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 259:125]
|
|
node _T_90 = or(_T_88, _T_89) @[el2_ifu_mem_ctl.scala 259:105]
|
|
node _T_91 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 259:160]
|
|
node _T_92 = and(bus_ifu_wr_en_ff, _T_91) @[el2_ifu_mem_ctl.scala 259:158]
|
|
node _T_93 = or(_T_90, _T_92) @[el2_ifu_mem_ctl.scala 259:138]
|
|
miss_state_en <= _T_93 @[el2_ifu_mem_ctl.scala 259:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_94 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_94 : @[Conditional.scala 39:67]
|
|
miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 262:21]
|
|
node _T_95 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 263:43]
|
|
node _T_96 = or(_T_95, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 263:59]
|
|
node _T_97 = or(_T_96, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 263:74]
|
|
miss_state_en <= _T_97 @[el2_ifu_mem_ctl.scala 263:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_98 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_98 : @[Conditional.scala 39:67]
|
|
node _T_99 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 266:49]
|
|
node _T_100 = or(_T_99, stream_eol_f) @[el2_ifu_mem_ctl.scala 266:72]
|
|
node _T_101 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 266:108]
|
|
node _T_102 = eq(_T_101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:89]
|
|
node _T_103 = and(_T_100, _T_102) @[el2_ifu_mem_ctl.scala 266:87]
|
|
node _T_104 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:124]
|
|
node _T_105 = and(_T_103, _T_104) @[el2_ifu_mem_ctl.scala 266:122]
|
|
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_mem_ctl.scala 266:148]
|
|
node _T_107 = mux(_T_106, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 266:27]
|
|
miss_nxtstate <= _T_107 @[el2_ifu_mem_ctl.scala 266:21]
|
|
node _T_108 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 267:43]
|
|
node _T_109 = or(_T_108, stream_eol_f) @[el2_ifu_mem_ctl.scala 267:67]
|
|
node _T_110 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 267:105]
|
|
node _T_111 = or(_T_109, _T_110) @[el2_ifu_mem_ctl.scala 267:84]
|
|
node _T_112 = or(_T_111, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 267:118]
|
|
miss_state_en <= _T_112 @[el2_ifu_mem_ctl.scala 267:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_113 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_113 : @[Conditional.scala 39:67]
|
|
node _T_114 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 270:69]
|
|
node _T_115 = eq(_T_114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:50]
|
|
node _T_116 = and(io.exu_flush_final, _T_115) @[el2_ifu_mem_ctl.scala 270:48]
|
|
node _T_117 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:84]
|
|
node _T_118 = and(_T_116, _T_117) @[el2_ifu_mem_ctl.scala 270:82]
|
|
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_mem_ctl.scala 270:108]
|
|
node _T_120 = mux(_T_119, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 270:27]
|
|
miss_nxtstate <= _T_120 @[el2_ifu_mem_ctl.scala 270:21]
|
|
node _T_121 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 271:63]
|
|
node _T_122 = or(io.exu_flush_final, _T_121) @[el2_ifu_mem_ctl.scala 271:43]
|
|
node _T_123 = or(_T_122, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 271:76]
|
|
miss_state_en <= _T_123 @[el2_ifu_mem_ctl.scala 271:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_124 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_124 : @[Conditional.scala 39:67]
|
|
node _T_125 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 274:71]
|
|
node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:52]
|
|
node _T_127 = and(ic_miss_under_miss_f, _T_126) @[el2_ifu_mem_ctl.scala 274:50]
|
|
node _T_128 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:86]
|
|
node _T_129 = and(_T_127, _T_128) @[el2_ifu_mem_ctl.scala 274:84]
|
|
node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_mem_ctl.scala 274:110]
|
|
node _T_131 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 275:56]
|
|
node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:37]
|
|
node _T_133 = and(ic_ignore_2nd_miss_f, _T_132) @[el2_ifu_mem_ctl.scala 275:35]
|
|
node _T_134 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:71]
|
|
node _T_135 = and(_T_133, _T_134) @[el2_ifu_mem_ctl.scala 275:69]
|
|
node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_mem_ctl.scala 275:95]
|
|
node _T_137 = mux(_T_136, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 275:12]
|
|
node _T_138 = mux(_T_130, UInt<3>("h05"), _T_137) @[el2_ifu_mem_ctl.scala 274:27]
|
|
miss_nxtstate <= _T_138 @[el2_ifu_mem_ctl.scala 274:21]
|
|
node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 276:42]
|
|
node _T_140 = or(_T_139, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 276:55]
|
|
node _T_141 = or(_T_140, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 276:78]
|
|
node _T_142 = or(_T_141, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 276:101]
|
|
miss_state_en <= _T_142 @[el2_ifu_mem_ctl.scala 276:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_143 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_143 : @[Conditional.scala 39:67]
|
|
node _T_144 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 280:31]
|
|
node _T_145 = bits(_T_144, 0, 0) @[el2_ifu_mem_ctl.scala 280:44]
|
|
node _T_146 = mux(_T_145, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 280:12]
|
|
node _T_147 = mux(io.exu_flush_final, _T_146, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 279:62]
|
|
node _T_148 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_147) @[el2_ifu_mem_ctl.scala 279:27]
|
|
miss_nxtstate <= _T_148 @[el2_ifu_mem_ctl.scala 279:21]
|
|
node _T_149 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 281:42]
|
|
node _T_150 = or(_T_149, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 281:55]
|
|
node _T_151 = or(_T_150, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 281:76]
|
|
miss_state_en <= _T_151 @[el2_ifu_mem_ctl.scala 281:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_152 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_152 : @[Conditional.scala 39:67]
|
|
node _T_153 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 285:31]
|
|
node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_mem_ctl.scala 285:44]
|
|
node _T_155 = mux(_T_154, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 285:12]
|
|
node _T_156 = mux(io.exu_flush_final, _T_155, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 284:62]
|
|
node _T_157 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_156) @[el2_ifu_mem_ctl.scala 284:27]
|
|
miss_nxtstate <= _T_157 @[el2_ifu_mem_ctl.scala 284:21]
|
|
node _T_158 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 286:42]
|
|
node _T_159 = or(_T_158, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 286:55]
|
|
node _T_160 = or(_T_159, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 286:76]
|
|
miss_state_en <= _T_160 @[el2_ifu_mem_ctl.scala 286:21]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_161 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 289:61]
|
|
reg _T_162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_161 : @[Reg.scala 28:19]
|
|
_T_162 <= miss_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
miss_state <= _T_162 @[el2_ifu_mem_ctl.scala 289:14]
|
|
wire crit_byp_hit_f : UInt<1>
|
|
crit_byp_hit_f <= UInt<1>("h00")
|
|
wire way_status_mb_scnd_ff : UInt<1>
|
|
way_status_mb_scnd_ff <= UInt<1>("h00")
|
|
wire way_status : UInt<1>
|
|
way_status <= UInt<1>("h00")
|
|
wire tagv_mb_scnd_ff : UInt<2>
|
|
tagv_mb_scnd_ff <= UInt<1>("h00")
|
|
wire ic_tag_valid : UInt<2>
|
|
ic_tag_valid <= UInt<1>("h00")
|
|
wire uncacheable_miss_scnd_ff : UInt<1>
|
|
uncacheable_miss_scnd_ff <= UInt<1>("h00")
|
|
wire imb_scnd_ff : UInt<31>
|
|
imb_scnd_ff <= UInt<1>("h00")
|
|
wire reset_all_tags : UInt<1>
|
|
reset_all_tags <= UInt<1>("h00")
|
|
wire bus_rd_addr_count : UInt<3>
|
|
bus_rd_addr_count <= UInt<1>("h00")
|
|
wire ifu_bus_rid_ff : UInt<3>
|
|
ifu_bus_rid_ff <= UInt<1>("h00")
|
|
node _T_163 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 300:30]
|
|
miss_pending <= _T_163 @[el2_ifu_mem_ctl.scala 300:16]
|
|
node _T_164 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 301:39]
|
|
node _T_165 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 301:73]
|
|
node _T_166 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 301:95]
|
|
node _T_167 = and(_T_165, _T_166) @[el2_ifu_mem_ctl.scala 301:93]
|
|
node crit_wd_byp_ok_ff = or(_T_164, _T_167) @[el2_ifu_mem_ctl.scala 301:58]
|
|
node _T_168 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 302:57]
|
|
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:38]
|
|
node _T_170 = and(miss_pending, _T_169) @[el2_ifu_mem_ctl.scala 302:36]
|
|
node _T_171 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 302:86]
|
|
node _T_172 = and(_T_171, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 302:106]
|
|
node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:72]
|
|
node _T_174 = and(_T_170, _T_173) @[el2_ifu_mem_ctl.scala 302:70]
|
|
node _T_175 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 303:37]
|
|
node _T_176 = and(_T_175, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 303:57]
|
|
node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 303:23]
|
|
node _T_178 = and(_T_174, _T_177) @[el2_ifu_mem_ctl.scala 302:128]
|
|
node _T_179 = or(_T_178, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 303:77]
|
|
node _T_180 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 304:36]
|
|
node _T_181 = and(miss_pending, _T_180) @[el2_ifu_mem_ctl.scala 304:19]
|
|
node sel_hold_imb = or(_T_179, _T_181) @[el2_ifu_mem_ctl.scala 303:93]
|
|
node _T_182 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 306:40]
|
|
node _T_183 = or(_T_182, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 306:57]
|
|
node _T_184 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 306:83]
|
|
node sel_hold_imb_scnd = and(_T_183, _T_184) @[el2_ifu_mem_ctl.scala 306:81]
|
|
node _T_185 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 307:46]
|
|
node way_status_mb_scnd_in = mux(_T_185, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 307:34]
|
|
node _T_186 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 309:40]
|
|
node _T_187 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 309:96]
|
|
node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_190 = and(_T_189, ic_tag_valid) @[el2_ifu_mem_ctl.scala 309:113]
|
|
node tagv_mb_scnd_in = mux(_T_186, tagv_mb_scnd_ff, _T_190) @[el2_ifu_mem_ctl.scala 309:28]
|
|
node _T_191 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 310:56]
|
|
node uncacheable_miss_scnd_in = mux(_T_191, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 310:37]
|
|
reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:38]
|
|
_T_192 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 311:38]
|
|
uncacheable_miss_scnd_ff <= _T_192 @[el2_ifu_mem_ctl.scala 311:28]
|
|
node _T_193 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 312:43]
|
|
node imb_scnd_in = mux(_T_193, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 312:24]
|
|
reg _T_194 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 313:25]
|
|
_T_194 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 313:25]
|
|
imb_scnd_ff <= _T_194 @[el2_ifu_mem_ctl.scala 313:15]
|
|
reg _T_195 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 314:35]
|
|
_T_195 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 314:35]
|
|
way_status_mb_scnd_ff <= _T_195 @[el2_ifu_mem_ctl.scala 314:25]
|
|
reg _T_196 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 315:29]
|
|
_T_196 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 315:29]
|
|
tagv_mb_scnd_ff <= _T_196 @[el2_ifu_mem_ctl.scala 315:19]
|
|
node _T_197 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_198 = mux(_T_197, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_198) @[el2_ifu_mem_ctl.scala 318:45]
|
|
wire ifc_iccm_access_f : UInt<1>
|
|
ifc_iccm_access_f <= UInt<1>("h00")
|
|
wire ifc_region_acc_fault_final_f : UInt<1>
|
|
ifc_region_acc_fault_final_f <= UInt<1>("h00")
|
|
node _T_199 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:48]
|
|
node _T_200 = and(ifc_fetch_req_f, _T_199) @[el2_ifu_mem_ctl.scala 321:46]
|
|
node _T_201 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:69]
|
|
node fetch_req_icache_f = and(_T_200, _T_201) @[el2_ifu_mem_ctl.scala 321:67]
|
|
node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 322:46]
|
|
node _T_202 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:45]
|
|
node _T_203 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 323:73]
|
|
node _T_204 = or(_T_202, _T_203) @[el2_ifu_mem_ctl.scala 323:59]
|
|
node _T_205 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 323:105]
|
|
node _T_206 = or(_T_204, _T_205) @[el2_ifu_mem_ctl.scala 323:91]
|
|
node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_206) @[el2_ifu_mem_ctl.scala 323:41]
|
|
wire stream_hit_f : UInt<1>
|
|
stream_hit_f <= UInt<1>("h00")
|
|
node _T_207 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 325:35]
|
|
node _T_208 = and(_T_207, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 325:52]
|
|
node _T_209 = and(_T_208, miss_pending) @[el2_ifu_mem_ctl.scala 325:73]
|
|
ic_byp_hit_f <= _T_209 @[el2_ifu_mem_ctl.scala 325:16]
|
|
wire sel_mb_addr_ff : UInt<1>
|
|
sel_mb_addr_ff <= UInt<1>("h00")
|
|
wire imb_ff : UInt<31>
|
|
imb_ff <= UInt<1>("h00")
|
|
wire ifu_fetch_addr_int_f : UInt<31>
|
|
ifu_fetch_addr_int_f <= UInt<1>("h00")
|
|
node _T_210 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 329:35]
|
|
node _T_211 = and(_T_210, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 329:39]
|
|
node _T_212 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:62]
|
|
node _T_213 = and(_T_211, _T_212) @[el2_ifu_mem_ctl.scala 329:60]
|
|
node _T_214 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:81]
|
|
node _T_215 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 329:108]
|
|
node _T_216 = or(_T_214, _T_215) @[el2_ifu_mem_ctl.scala 329:95]
|
|
node _T_217 = and(_T_213, _T_216) @[el2_ifu_mem_ctl.scala 329:78]
|
|
node _T_218 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:128]
|
|
node ic_act_hit_f = and(_T_217, _T_218) @[el2_ifu_mem_ctl.scala 329:126]
|
|
node _T_219 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 330:37]
|
|
node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:23]
|
|
node _T_221 = or(_T_220, reset_all_tags) @[el2_ifu_mem_ctl.scala 330:41]
|
|
node _T_222 = and(_T_221, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 330:59]
|
|
node _T_223 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:82]
|
|
node _T_224 = and(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 330:80]
|
|
node _T_225 = or(_T_224, scnd_miss_req) @[el2_ifu_mem_ctl.scala 330:97]
|
|
node _T_226 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:116]
|
|
node _T_227 = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 330:114]
|
|
ic_act_miss_f <= _T_227 @[el2_ifu_mem_ctl.scala 330:17]
|
|
node _T_228 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 331:28]
|
|
node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 331:42]
|
|
node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 331:60]
|
|
node _T_231 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 331:94]
|
|
node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 331:81]
|
|
node _T_233 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 332:12]
|
|
node _T_234 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 332:63]
|
|
node _T_235 = neq(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 332:39]
|
|
node _T_236 = and(_T_232, _T_235) @[el2_ifu_mem_ctl.scala 331:111]
|
|
node _T_237 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:93]
|
|
node _T_238 = and(_T_236, _T_237) @[el2_ifu_mem_ctl.scala 332:91]
|
|
node _T_239 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:116]
|
|
node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 332:114]
|
|
node _T_241 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:134]
|
|
node _T_242 = and(_T_240, _T_241) @[el2_ifu_mem_ctl.scala 332:132]
|
|
ic_miss_under_miss_f <= _T_242 @[el2_ifu_mem_ctl.scala 331:24]
|
|
node _T_243 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 333:42]
|
|
node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 333:28]
|
|
node _T_245 = or(_T_244, reset_all_tags) @[el2_ifu_mem_ctl.scala 333:46]
|
|
node _T_246 = and(_T_245, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 333:64]
|
|
node _T_247 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 333:99]
|
|
node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 333:85]
|
|
node _T_249 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 334:13]
|
|
node _T_250 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 334:62]
|
|
node _T_251 = eq(_T_249, _T_250) @[el2_ifu_mem_ctl.scala 334:39]
|
|
node _T_252 = or(_T_251, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 334:91]
|
|
node _T_253 = and(_T_248, _T_252) @[el2_ifu_mem_ctl.scala 333:117]
|
|
ic_ignore_2nd_miss_f <= _T_253 @[el2_ifu_mem_ctl.scala 333:24]
|
|
node _T_254 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 336:31]
|
|
node _T_255 = or(_T_254, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 336:46]
|
|
node _T_256 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 336:94]
|
|
node _T_257 = or(_T_255, _T_256) @[el2_ifu_mem_ctl.scala 336:62]
|
|
io.ic_hit_f <= _T_257 @[el2_ifu_mem_ctl.scala 336:15]
|
|
node _T_258 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 337:47]
|
|
node _T_259 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 337:98]
|
|
node _T_260 = mux(_T_259, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 337:84]
|
|
node uncacheable_miss_in = mux(_T_258, uncacheable_miss_scnd_ff, _T_260) @[el2_ifu_mem_ctl.scala 337:32]
|
|
node _T_261 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 338:34]
|
|
node _T_262 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 338:72]
|
|
node _T_263 = mux(_T_262, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 338:58]
|
|
node imb_in = mux(_T_261, imb_scnd_ff, _T_263) @[el2_ifu_mem_ctl.scala 338:19]
|
|
wire ifu_wr_cumulative_err_data : UInt<1>
|
|
ifu_wr_cumulative_err_data <= UInt<1>("h00")
|
|
node _T_264 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:38]
|
|
node _T_265 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:89]
|
|
node _T_266 = eq(_T_264, _T_265) @[el2_ifu_mem_ctl.scala 340:75]
|
|
node _T_267 = and(_T_266, scnd_miss_req) @[el2_ifu_mem_ctl.scala 340:127]
|
|
node _T_268 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 340:145]
|
|
node scnd_miss_index_match = and(_T_267, _T_268) @[el2_ifu_mem_ctl.scala 340:143]
|
|
wire way_status_mb_ff : UInt<1>
|
|
way_status_mb_ff <= UInt<1>("h00")
|
|
wire way_status_rep_new : UInt<1>
|
|
way_status_rep_new <= UInt<1>("h00")
|
|
node _T_269 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 343:47]
|
|
node _T_270 = and(scnd_miss_req, _T_269) @[el2_ifu_mem_ctl.scala 343:45]
|
|
node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_mem_ctl.scala 343:71]
|
|
node _T_272 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 344:26]
|
|
node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_mem_ctl.scala 344:52]
|
|
node _T_274 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 345:26]
|
|
node _T_275 = mux(_T_274, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 345:12]
|
|
node _T_276 = mux(_T_273, way_status_rep_new, _T_275) @[el2_ifu_mem_ctl.scala 344:10]
|
|
node way_status_mb_in = mux(_T_271, way_status_mb_scnd_ff, _T_276) @[el2_ifu_mem_ctl.scala 343:29]
|
|
wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 346:32]
|
|
wire tagv_mb_ff : UInt<2>
|
|
tagv_mb_ff <= UInt<1>("h00")
|
|
node _T_277 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 348:38]
|
|
node _T_278 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_280 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58]
|
|
node _T_281 = and(_T_279, _T_280) @[el2_ifu_mem_ctl.scala 348:110]
|
|
node _T_282 = or(tagv_mb_scnd_ff, _T_281) @[el2_ifu_mem_ctl.scala 348:62]
|
|
node _T_283 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 349:20]
|
|
node _T_284 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 349:77]
|
|
node _T_285 = bits(_T_284, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_286 = mux(_T_285, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_287 = and(ic_tag_valid, _T_286) @[el2_ifu_mem_ctl.scala 349:53]
|
|
node _T_288 = mux(_T_283, tagv_mb_ff, _T_287) @[el2_ifu_mem_ctl.scala 349:6]
|
|
node tagv_mb_in = mux(_T_277, _T_282, _T_288) @[el2_ifu_mem_ctl.scala 348:23]
|
|
wire scnd_miss_req_q : UInt<1>
|
|
scnd_miss_req_q <= UInt<1>("h00")
|
|
wire reset_ic_ff : UInt<1>
|
|
reset_ic_ff <= UInt<1>("h00")
|
|
node _T_289 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 352:36]
|
|
node _T_290 = and(miss_pending, _T_289) @[el2_ifu_mem_ctl.scala 352:34]
|
|
node _T_291 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 352:72]
|
|
node reset_ic_in = and(_T_290, _T_291) @[el2_ifu_mem_ctl.scala 352:53]
|
|
reg _T_292 : UInt, clock @[el2_ifu_mem_ctl.scala 353:25]
|
|
_T_292 <= reset_ic_in @[el2_ifu_mem_ctl.scala 353:25]
|
|
reset_ic_ff <= _T_292 @[el2_ifu_mem_ctl.scala 353:15]
|
|
reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 354:37]
|
|
fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 354:37]
|
|
reg _T_293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 355:34]
|
|
_T_293 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 355:34]
|
|
ifu_fetch_addr_int_f <= _T_293 @[el2_ifu_mem_ctl.scala 355:24]
|
|
reg _T_294 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 357:33]
|
|
_T_294 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 357:33]
|
|
uncacheable_miss_ff <= _T_294 @[el2_ifu_mem_ctl.scala 357:23]
|
|
reg _T_295 : UInt, clock @[el2_ifu_mem_ctl.scala 358:20]
|
|
_T_295 <= imb_in @[el2_ifu_mem_ctl.scala 358:20]
|
|
imb_ff <= _T_295 @[el2_ifu_mem_ctl.scala 358:10]
|
|
wire miss_addr : UInt<26>
|
|
miss_addr <= UInt<1>("h00")
|
|
node _T_296 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 360:26]
|
|
node _T_297 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 360:47]
|
|
node _T_298 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 361:25]
|
|
node _T_299 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 361:44]
|
|
node _T_300 = mux(_T_298, _T_299, miss_addr) @[el2_ifu_mem_ctl.scala 361:8]
|
|
node miss_addr_in = mux(_T_296, _T_297, _T_300) @[el2_ifu_mem_ctl.scala 360:25]
|
|
reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 362:23]
|
|
_T_301 <= miss_addr_in @[el2_ifu_mem_ctl.scala 362:23]
|
|
miss_addr <= _T_301 @[el2_ifu_mem_ctl.scala 362:13]
|
|
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 363:30]
|
|
_T_302 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 363:30]
|
|
way_status_mb_ff <= _T_302 @[el2_ifu_mem_ctl.scala 363:20]
|
|
reg _T_303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 364:24]
|
|
_T_303 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 364:24]
|
|
tagv_mb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 364:14]
|
|
wire stream_miss_f : UInt<1>
|
|
stream_miss_f <= UInt<1>("h00")
|
|
node _T_304 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 366:68]
|
|
node _T_305 = and(_T_304, flush_final_f) @[el2_ifu_mem_ctl.scala 366:87]
|
|
node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:55]
|
|
node _T_307 = and(io.ifc_fetch_req_bf, _T_306) @[el2_ifu_mem_ctl.scala 366:53]
|
|
node _T_308 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:106]
|
|
node ifc_fetch_req_qual_bf = and(_T_307, _T_308) @[el2_ifu_mem_ctl.scala 366:104]
|
|
reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 367:36]
|
|
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 367:36]
|
|
node _T_309 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 368:44]
|
|
node _T_310 = and(ifc_fetch_req_f_raw, _T_309) @[el2_ifu_mem_ctl.scala 368:42]
|
|
ifc_fetch_req_f <= _T_310 @[el2_ifu_mem_ctl.scala 368:19]
|
|
reg _T_311 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 369:31]
|
|
_T_311 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 369:31]
|
|
ifc_iccm_access_f <= _T_311 @[el2_ifu_mem_ctl.scala 369:21]
|
|
wire ifc_region_acc_fault_final_bf : UInt<1>
|
|
ifc_region_acc_fault_final_bf <= UInt<1>("h00")
|
|
reg _T_312 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 371:42]
|
|
_T_312 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 371:42]
|
|
ifc_region_acc_fault_final_f <= _T_312 @[el2_ifu_mem_ctl.scala 371:32]
|
|
reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 372:39]
|
|
ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 372:39]
|
|
node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
|
|
node _T_313 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 374:38]
|
|
node _T_314 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 374:68]
|
|
node _T_315 = or(_T_313, _T_314) @[el2_ifu_mem_ctl.scala 374:55]
|
|
node _T_316 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 374:103]
|
|
node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:84]
|
|
node _T_318 = and(_T_315, _T_317) @[el2_ifu_mem_ctl.scala 374:82]
|
|
node _T_319 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:119]
|
|
node ifu_ic_mb_empty = or(_T_318, _T_319) @[el2_ifu_mem_ctl.scala 374:117]
|
|
node ifu_miss_state_idle = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 375:40]
|
|
wire write_ic_16_bytes : UInt<1>
|
|
write_ic_16_bytes <= UInt<1>("h00")
|
|
wire reset_tag_valid_for_miss : UInt<1>
|
|
reset_tag_valid_for_miss <= UInt<1>("h00")
|
|
node _T_320 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 378:35]
|
|
node _T_321 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 378:57]
|
|
node _T_322 = and(_T_320, _T_321) @[el2_ifu_mem_ctl.scala 378:55]
|
|
node sel_mb_addr = or(_T_322, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 378:79]
|
|
node _T_323 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 379:50]
|
|
node _T_324 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 379:68]
|
|
node _T_325 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 379:124]
|
|
node _T_326 = cat(_T_324, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_327 = cat(_T_326, _T_325) @[Cat.scala 29:58]
|
|
node _T_328 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 380:50]
|
|
node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 380:37]
|
|
node _T_330 = mux(_T_323, _T_327, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_331 = mux(_T_329, ifu_fetch_addr_int_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_332 = or(_T_330, _T_331) @[Mux.scala 27:72]
|
|
wire ic_rw_addr : UInt<31> @[Mux.scala 27:72]
|
|
ic_rw_addr <= _T_332 @[Mux.scala 27:72]
|
|
wire bus_ifu_wr_en_ff_q : UInt<1>
|
|
bus_ifu_wr_en_ff_q <= UInt<1>("h00")
|
|
node _T_333 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 382:41]
|
|
node _T_334 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 382:63]
|
|
node _T_335 = and(_T_333, _T_334) @[el2_ifu_mem_ctl.scala 382:61]
|
|
node _T_336 = and(_T_335, last_beat) @[el2_ifu_mem_ctl.scala 382:84]
|
|
node sel_mb_status_addr = and(_T_336, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 382:96]
|
|
node _T_337 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 383:62]
|
|
node _T_338 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 383:116]
|
|
node _T_339 = cat(_T_337, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_340 = cat(_T_339, _T_338) @[Cat.scala 29:58]
|
|
node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_340, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 383:31]
|
|
reg _T_341 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 385:51]
|
|
_T_341 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 385:51]
|
|
sel_mb_addr_ff <= _T_341 @[el2_ifu_mem_ctl.scala 385:18]
|
|
wire ifu_bus_rdata_ff : UInt<64>
|
|
ifu_bus_rdata_ff <= UInt<1>("h00")
|
|
wire ic_miss_buff_half : UInt<64>
|
|
ic_miss_buff_half <= UInt<1>("h00")
|
|
wire _T_342 : UInt<1>[35] @[el2_lib.scala 327:18]
|
|
wire _T_343 : UInt<1>[35] @[el2_lib.scala 328:18]
|
|
wire _T_344 : UInt<1>[35] @[el2_lib.scala 329:18]
|
|
wire _T_345 : UInt<1>[31] @[el2_lib.scala 330:18]
|
|
wire _T_346 : UInt<1>[31] @[el2_lib.scala 331:18]
|
|
wire _T_347 : UInt<1>[31] @[el2_lib.scala 332:18]
|
|
wire _T_348 : UInt<1>[7] @[el2_lib.scala 333:18]
|
|
node _T_349 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 340:36]
|
|
_T_342[0] <= _T_349 @[el2_lib.scala 340:30]
|
|
node _T_350 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 341:36]
|
|
_T_343[0] <= _T_350 @[el2_lib.scala 341:30]
|
|
node _T_351 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 340:36]
|
|
_T_342[1] <= _T_351 @[el2_lib.scala 340:30]
|
|
node _T_352 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 342:36]
|
|
_T_344[0] <= _T_352 @[el2_lib.scala 342:30]
|
|
node _T_353 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 341:36]
|
|
_T_343[1] <= _T_353 @[el2_lib.scala 341:30]
|
|
node _T_354 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 342:36]
|
|
_T_344[1] <= _T_354 @[el2_lib.scala 342:30]
|
|
node _T_355 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 340:36]
|
|
_T_342[2] <= _T_355 @[el2_lib.scala 340:30]
|
|
node _T_356 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 341:36]
|
|
_T_343[2] <= _T_356 @[el2_lib.scala 341:30]
|
|
node _T_357 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 342:36]
|
|
_T_344[2] <= _T_357 @[el2_lib.scala 342:30]
|
|
node _T_358 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 340:36]
|
|
_T_342[3] <= _T_358 @[el2_lib.scala 340:30]
|
|
node _T_359 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 343:36]
|
|
_T_345[0] <= _T_359 @[el2_lib.scala 343:30]
|
|
node _T_360 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 341:36]
|
|
_T_343[3] <= _T_360 @[el2_lib.scala 341:30]
|
|
node _T_361 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 343:36]
|
|
_T_345[1] <= _T_361 @[el2_lib.scala 343:30]
|
|
node _T_362 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 340:36]
|
|
_T_342[4] <= _T_362 @[el2_lib.scala 340:30]
|
|
node _T_363 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 341:36]
|
|
_T_343[4] <= _T_363 @[el2_lib.scala 341:30]
|
|
node _T_364 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 343:36]
|
|
_T_345[2] <= _T_364 @[el2_lib.scala 343:30]
|
|
node _T_365 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 342:36]
|
|
_T_344[3] <= _T_365 @[el2_lib.scala 342:30]
|
|
node _T_366 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 343:36]
|
|
_T_345[3] <= _T_366 @[el2_lib.scala 343:30]
|
|
node _T_367 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 340:36]
|
|
_T_342[5] <= _T_367 @[el2_lib.scala 340:30]
|
|
node _T_368 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 342:36]
|
|
_T_344[4] <= _T_368 @[el2_lib.scala 342:30]
|
|
node _T_369 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 343:36]
|
|
_T_345[4] <= _T_369 @[el2_lib.scala 343:30]
|
|
node _T_370 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 341:36]
|
|
_T_343[5] <= _T_370 @[el2_lib.scala 341:30]
|
|
node _T_371 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 342:36]
|
|
_T_344[5] <= _T_371 @[el2_lib.scala 342:30]
|
|
node _T_372 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 343:36]
|
|
_T_345[5] <= _T_372 @[el2_lib.scala 343:30]
|
|
node _T_373 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 340:36]
|
|
_T_342[6] <= _T_373 @[el2_lib.scala 340:30]
|
|
node _T_374 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 341:36]
|
|
_T_343[6] <= _T_374 @[el2_lib.scala 341:30]
|
|
node _T_375 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 342:36]
|
|
_T_344[6] <= _T_375 @[el2_lib.scala 342:30]
|
|
node _T_376 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 343:36]
|
|
_T_345[6] <= _T_376 @[el2_lib.scala 343:30]
|
|
node _T_377 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 340:36]
|
|
_T_342[7] <= _T_377 @[el2_lib.scala 340:30]
|
|
node _T_378 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 344:36]
|
|
_T_346[0] <= _T_378 @[el2_lib.scala 344:30]
|
|
node _T_379 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 341:36]
|
|
_T_343[7] <= _T_379 @[el2_lib.scala 341:30]
|
|
node _T_380 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 344:36]
|
|
_T_346[1] <= _T_380 @[el2_lib.scala 344:30]
|
|
node _T_381 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 340:36]
|
|
_T_342[8] <= _T_381 @[el2_lib.scala 340:30]
|
|
node _T_382 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 341:36]
|
|
_T_343[8] <= _T_382 @[el2_lib.scala 341:30]
|
|
node _T_383 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 344:36]
|
|
_T_346[2] <= _T_383 @[el2_lib.scala 344:30]
|
|
node _T_384 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 342:36]
|
|
_T_344[7] <= _T_384 @[el2_lib.scala 342:30]
|
|
node _T_385 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 344:36]
|
|
_T_346[3] <= _T_385 @[el2_lib.scala 344:30]
|
|
node _T_386 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 340:36]
|
|
_T_342[9] <= _T_386 @[el2_lib.scala 340:30]
|
|
node _T_387 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 342:36]
|
|
_T_344[8] <= _T_387 @[el2_lib.scala 342:30]
|
|
node _T_388 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 344:36]
|
|
_T_346[4] <= _T_388 @[el2_lib.scala 344:30]
|
|
node _T_389 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 341:36]
|
|
_T_343[9] <= _T_389 @[el2_lib.scala 341:30]
|
|
node _T_390 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 342:36]
|
|
_T_344[9] <= _T_390 @[el2_lib.scala 342:30]
|
|
node _T_391 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 344:36]
|
|
_T_346[5] <= _T_391 @[el2_lib.scala 344:30]
|
|
node _T_392 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 340:36]
|
|
_T_342[10] <= _T_392 @[el2_lib.scala 340:30]
|
|
node _T_393 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 341:36]
|
|
_T_343[10] <= _T_393 @[el2_lib.scala 341:30]
|
|
node _T_394 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 342:36]
|
|
_T_344[10] <= _T_394 @[el2_lib.scala 342:30]
|
|
node _T_395 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 344:36]
|
|
_T_346[6] <= _T_395 @[el2_lib.scala 344:30]
|
|
node _T_396 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 343:36]
|
|
_T_345[7] <= _T_396 @[el2_lib.scala 343:30]
|
|
node _T_397 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 344:36]
|
|
_T_346[7] <= _T_397 @[el2_lib.scala 344:30]
|
|
node _T_398 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 340:36]
|
|
_T_342[11] <= _T_398 @[el2_lib.scala 340:30]
|
|
node _T_399 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 343:36]
|
|
_T_345[8] <= _T_399 @[el2_lib.scala 343:30]
|
|
node _T_400 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 344:36]
|
|
_T_346[8] <= _T_400 @[el2_lib.scala 344:30]
|
|
node _T_401 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 341:36]
|
|
_T_343[11] <= _T_401 @[el2_lib.scala 341:30]
|
|
node _T_402 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 343:36]
|
|
_T_345[9] <= _T_402 @[el2_lib.scala 343:30]
|
|
node _T_403 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 344:36]
|
|
_T_346[9] <= _T_403 @[el2_lib.scala 344:30]
|
|
node _T_404 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 340:36]
|
|
_T_342[12] <= _T_404 @[el2_lib.scala 340:30]
|
|
node _T_405 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 341:36]
|
|
_T_343[12] <= _T_405 @[el2_lib.scala 341:30]
|
|
node _T_406 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 343:36]
|
|
_T_345[10] <= _T_406 @[el2_lib.scala 343:30]
|
|
node _T_407 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 344:36]
|
|
_T_346[10] <= _T_407 @[el2_lib.scala 344:30]
|
|
node _T_408 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 342:36]
|
|
_T_344[11] <= _T_408 @[el2_lib.scala 342:30]
|
|
node _T_409 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 343:36]
|
|
_T_345[11] <= _T_409 @[el2_lib.scala 343:30]
|
|
node _T_410 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 344:36]
|
|
_T_346[11] <= _T_410 @[el2_lib.scala 344:30]
|
|
node _T_411 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 340:36]
|
|
_T_342[13] <= _T_411 @[el2_lib.scala 340:30]
|
|
node _T_412 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 342:36]
|
|
_T_344[12] <= _T_412 @[el2_lib.scala 342:30]
|
|
node _T_413 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 343:36]
|
|
_T_345[12] <= _T_413 @[el2_lib.scala 343:30]
|
|
node _T_414 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 344:36]
|
|
_T_346[12] <= _T_414 @[el2_lib.scala 344:30]
|
|
node _T_415 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 341:36]
|
|
_T_343[13] <= _T_415 @[el2_lib.scala 341:30]
|
|
node _T_416 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 342:36]
|
|
_T_344[13] <= _T_416 @[el2_lib.scala 342:30]
|
|
node _T_417 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 343:36]
|
|
_T_345[13] <= _T_417 @[el2_lib.scala 343:30]
|
|
node _T_418 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 344:36]
|
|
_T_346[13] <= _T_418 @[el2_lib.scala 344:30]
|
|
node _T_419 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 340:36]
|
|
_T_342[14] <= _T_419 @[el2_lib.scala 340:30]
|
|
node _T_420 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 341:36]
|
|
_T_343[14] <= _T_420 @[el2_lib.scala 341:30]
|
|
node _T_421 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 342:36]
|
|
_T_344[14] <= _T_421 @[el2_lib.scala 342:30]
|
|
node _T_422 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 343:36]
|
|
_T_345[14] <= _T_422 @[el2_lib.scala 343:30]
|
|
node _T_423 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 344:36]
|
|
_T_346[14] <= _T_423 @[el2_lib.scala 344:30]
|
|
node _T_424 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 340:36]
|
|
_T_342[15] <= _T_424 @[el2_lib.scala 340:30]
|
|
node _T_425 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 345:36]
|
|
_T_347[0] <= _T_425 @[el2_lib.scala 345:30]
|
|
node _T_426 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 341:36]
|
|
_T_343[15] <= _T_426 @[el2_lib.scala 341:30]
|
|
node _T_427 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 345:36]
|
|
_T_347[1] <= _T_427 @[el2_lib.scala 345:30]
|
|
node _T_428 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 340:36]
|
|
_T_342[16] <= _T_428 @[el2_lib.scala 340:30]
|
|
node _T_429 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 341:36]
|
|
_T_343[16] <= _T_429 @[el2_lib.scala 341:30]
|
|
node _T_430 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 345:36]
|
|
_T_347[2] <= _T_430 @[el2_lib.scala 345:30]
|
|
node _T_431 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 342:36]
|
|
_T_344[15] <= _T_431 @[el2_lib.scala 342:30]
|
|
node _T_432 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 345:36]
|
|
_T_347[3] <= _T_432 @[el2_lib.scala 345:30]
|
|
node _T_433 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 340:36]
|
|
_T_342[17] <= _T_433 @[el2_lib.scala 340:30]
|
|
node _T_434 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 342:36]
|
|
_T_344[16] <= _T_434 @[el2_lib.scala 342:30]
|
|
node _T_435 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 345:36]
|
|
_T_347[4] <= _T_435 @[el2_lib.scala 345:30]
|
|
node _T_436 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 341:36]
|
|
_T_343[17] <= _T_436 @[el2_lib.scala 341:30]
|
|
node _T_437 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 342:36]
|
|
_T_344[17] <= _T_437 @[el2_lib.scala 342:30]
|
|
node _T_438 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 345:36]
|
|
_T_347[5] <= _T_438 @[el2_lib.scala 345:30]
|
|
node _T_439 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 340:36]
|
|
_T_342[18] <= _T_439 @[el2_lib.scala 340:30]
|
|
node _T_440 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 341:36]
|
|
_T_343[18] <= _T_440 @[el2_lib.scala 341:30]
|
|
node _T_441 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 342:36]
|
|
_T_344[18] <= _T_441 @[el2_lib.scala 342:30]
|
|
node _T_442 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 345:36]
|
|
_T_347[6] <= _T_442 @[el2_lib.scala 345:30]
|
|
node _T_443 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 343:36]
|
|
_T_345[15] <= _T_443 @[el2_lib.scala 343:30]
|
|
node _T_444 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 345:36]
|
|
_T_347[7] <= _T_444 @[el2_lib.scala 345:30]
|
|
node _T_445 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 340:36]
|
|
_T_342[19] <= _T_445 @[el2_lib.scala 340:30]
|
|
node _T_446 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 343:36]
|
|
_T_345[16] <= _T_446 @[el2_lib.scala 343:30]
|
|
node _T_447 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 345:36]
|
|
_T_347[8] <= _T_447 @[el2_lib.scala 345:30]
|
|
node _T_448 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 341:36]
|
|
_T_343[19] <= _T_448 @[el2_lib.scala 341:30]
|
|
node _T_449 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 343:36]
|
|
_T_345[17] <= _T_449 @[el2_lib.scala 343:30]
|
|
node _T_450 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 345:36]
|
|
_T_347[9] <= _T_450 @[el2_lib.scala 345:30]
|
|
node _T_451 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 340:36]
|
|
_T_342[20] <= _T_451 @[el2_lib.scala 340:30]
|
|
node _T_452 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 341:36]
|
|
_T_343[20] <= _T_452 @[el2_lib.scala 341:30]
|
|
node _T_453 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 343:36]
|
|
_T_345[18] <= _T_453 @[el2_lib.scala 343:30]
|
|
node _T_454 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 345:36]
|
|
_T_347[10] <= _T_454 @[el2_lib.scala 345:30]
|
|
node _T_455 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 342:36]
|
|
_T_344[19] <= _T_455 @[el2_lib.scala 342:30]
|
|
node _T_456 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 343:36]
|
|
_T_345[19] <= _T_456 @[el2_lib.scala 343:30]
|
|
node _T_457 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 345:36]
|
|
_T_347[11] <= _T_457 @[el2_lib.scala 345:30]
|
|
node _T_458 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 340:36]
|
|
_T_342[21] <= _T_458 @[el2_lib.scala 340:30]
|
|
node _T_459 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 342:36]
|
|
_T_344[20] <= _T_459 @[el2_lib.scala 342:30]
|
|
node _T_460 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 343:36]
|
|
_T_345[20] <= _T_460 @[el2_lib.scala 343:30]
|
|
node _T_461 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 345:36]
|
|
_T_347[12] <= _T_461 @[el2_lib.scala 345:30]
|
|
node _T_462 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 341:36]
|
|
_T_343[21] <= _T_462 @[el2_lib.scala 341:30]
|
|
node _T_463 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 342:36]
|
|
_T_344[21] <= _T_463 @[el2_lib.scala 342:30]
|
|
node _T_464 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 343:36]
|
|
_T_345[21] <= _T_464 @[el2_lib.scala 343:30]
|
|
node _T_465 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 345:36]
|
|
_T_347[13] <= _T_465 @[el2_lib.scala 345:30]
|
|
node _T_466 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 340:36]
|
|
_T_342[22] <= _T_466 @[el2_lib.scala 340:30]
|
|
node _T_467 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 341:36]
|
|
_T_343[22] <= _T_467 @[el2_lib.scala 341:30]
|
|
node _T_468 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 342:36]
|
|
_T_344[22] <= _T_468 @[el2_lib.scala 342:30]
|
|
node _T_469 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 343:36]
|
|
_T_345[22] <= _T_469 @[el2_lib.scala 343:30]
|
|
node _T_470 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 345:36]
|
|
_T_347[14] <= _T_470 @[el2_lib.scala 345:30]
|
|
node _T_471 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 344:36]
|
|
_T_346[15] <= _T_471 @[el2_lib.scala 344:30]
|
|
node _T_472 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 345:36]
|
|
_T_347[15] <= _T_472 @[el2_lib.scala 345:30]
|
|
node _T_473 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 340:36]
|
|
_T_342[23] <= _T_473 @[el2_lib.scala 340:30]
|
|
node _T_474 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 344:36]
|
|
_T_346[16] <= _T_474 @[el2_lib.scala 344:30]
|
|
node _T_475 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 345:36]
|
|
_T_347[16] <= _T_475 @[el2_lib.scala 345:30]
|
|
node _T_476 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 341:36]
|
|
_T_343[23] <= _T_476 @[el2_lib.scala 341:30]
|
|
node _T_477 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 344:36]
|
|
_T_346[17] <= _T_477 @[el2_lib.scala 344:30]
|
|
node _T_478 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 345:36]
|
|
_T_347[17] <= _T_478 @[el2_lib.scala 345:30]
|
|
node _T_479 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 340:36]
|
|
_T_342[24] <= _T_479 @[el2_lib.scala 340:30]
|
|
node _T_480 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 341:36]
|
|
_T_343[24] <= _T_480 @[el2_lib.scala 341:30]
|
|
node _T_481 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 344:36]
|
|
_T_346[18] <= _T_481 @[el2_lib.scala 344:30]
|
|
node _T_482 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 345:36]
|
|
_T_347[18] <= _T_482 @[el2_lib.scala 345:30]
|
|
node _T_483 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 342:36]
|
|
_T_344[23] <= _T_483 @[el2_lib.scala 342:30]
|
|
node _T_484 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 344:36]
|
|
_T_346[19] <= _T_484 @[el2_lib.scala 344:30]
|
|
node _T_485 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 345:36]
|
|
_T_347[19] <= _T_485 @[el2_lib.scala 345:30]
|
|
node _T_486 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 340:36]
|
|
_T_342[25] <= _T_486 @[el2_lib.scala 340:30]
|
|
node _T_487 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 342:36]
|
|
_T_344[24] <= _T_487 @[el2_lib.scala 342:30]
|
|
node _T_488 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 344:36]
|
|
_T_346[20] <= _T_488 @[el2_lib.scala 344:30]
|
|
node _T_489 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 345:36]
|
|
_T_347[20] <= _T_489 @[el2_lib.scala 345:30]
|
|
node _T_490 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 341:36]
|
|
_T_343[25] <= _T_490 @[el2_lib.scala 341:30]
|
|
node _T_491 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 342:36]
|
|
_T_344[25] <= _T_491 @[el2_lib.scala 342:30]
|
|
node _T_492 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 344:36]
|
|
_T_346[21] <= _T_492 @[el2_lib.scala 344:30]
|
|
node _T_493 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 345:36]
|
|
_T_347[21] <= _T_493 @[el2_lib.scala 345:30]
|
|
node _T_494 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 340:36]
|
|
_T_342[26] <= _T_494 @[el2_lib.scala 340:30]
|
|
node _T_495 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 341:36]
|
|
_T_343[26] <= _T_495 @[el2_lib.scala 341:30]
|
|
node _T_496 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 342:36]
|
|
_T_344[26] <= _T_496 @[el2_lib.scala 342:30]
|
|
node _T_497 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 344:36]
|
|
_T_346[22] <= _T_497 @[el2_lib.scala 344:30]
|
|
node _T_498 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 345:36]
|
|
_T_347[22] <= _T_498 @[el2_lib.scala 345:30]
|
|
node _T_499 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 343:36]
|
|
_T_345[23] <= _T_499 @[el2_lib.scala 343:30]
|
|
node _T_500 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 344:36]
|
|
_T_346[23] <= _T_500 @[el2_lib.scala 344:30]
|
|
node _T_501 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 345:36]
|
|
_T_347[23] <= _T_501 @[el2_lib.scala 345:30]
|
|
node _T_502 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 340:36]
|
|
_T_342[27] <= _T_502 @[el2_lib.scala 340:30]
|
|
node _T_503 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 343:36]
|
|
_T_345[24] <= _T_503 @[el2_lib.scala 343:30]
|
|
node _T_504 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 344:36]
|
|
_T_346[24] <= _T_504 @[el2_lib.scala 344:30]
|
|
node _T_505 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 345:36]
|
|
_T_347[24] <= _T_505 @[el2_lib.scala 345:30]
|
|
node _T_506 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 341:36]
|
|
_T_343[27] <= _T_506 @[el2_lib.scala 341:30]
|
|
node _T_507 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 343:36]
|
|
_T_345[25] <= _T_507 @[el2_lib.scala 343:30]
|
|
node _T_508 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 344:36]
|
|
_T_346[25] <= _T_508 @[el2_lib.scala 344:30]
|
|
node _T_509 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 345:36]
|
|
_T_347[25] <= _T_509 @[el2_lib.scala 345:30]
|
|
node _T_510 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 340:36]
|
|
_T_342[28] <= _T_510 @[el2_lib.scala 340:30]
|
|
node _T_511 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 341:36]
|
|
_T_343[28] <= _T_511 @[el2_lib.scala 341:30]
|
|
node _T_512 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 343:36]
|
|
_T_345[26] <= _T_512 @[el2_lib.scala 343:30]
|
|
node _T_513 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 344:36]
|
|
_T_346[26] <= _T_513 @[el2_lib.scala 344:30]
|
|
node _T_514 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 345:36]
|
|
_T_347[26] <= _T_514 @[el2_lib.scala 345:30]
|
|
node _T_515 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 342:36]
|
|
_T_344[27] <= _T_515 @[el2_lib.scala 342:30]
|
|
node _T_516 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 343:36]
|
|
_T_345[27] <= _T_516 @[el2_lib.scala 343:30]
|
|
node _T_517 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 344:36]
|
|
_T_346[27] <= _T_517 @[el2_lib.scala 344:30]
|
|
node _T_518 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 345:36]
|
|
_T_347[27] <= _T_518 @[el2_lib.scala 345:30]
|
|
node _T_519 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 340:36]
|
|
_T_342[29] <= _T_519 @[el2_lib.scala 340:30]
|
|
node _T_520 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 342:36]
|
|
_T_344[28] <= _T_520 @[el2_lib.scala 342:30]
|
|
node _T_521 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 343:36]
|
|
_T_345[28] <= _T_521 @[el2_lib.scala 343:30]
|
|
node _T_522 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 344:36]
|
|
_T_346[28] <= _T_522 @[el2_lib.scala 344:30]
|
|
node _T_523 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 345:36]
|
|
_T_347[28] <= _T_523 @[el2_lib.scala 345:30]
|
|
node _T_524 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 341:36]
|
|
_T_343[29] <= _T_524 @[el2_lib.scala 341:30]
|
|
node _T_525 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 342:36]
|
|
_T_344[29] <= _T_525 @[el2_lib.scala 342:30]
|
|
node _T_526 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 343:36]
|
|
_T_345[29] <= _T_526 @[el2_lib.scala 343:30]
|
|
node _T_527 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 344:36]
|
|
_T_346[29] <= _T_527 @[el2_lib.scala 344:30]
|
|
node _T_528 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 345:36]
|
|
_T_347[29] <= _T_528 @[el2_lib.scala 345:30]
|
|
node _T_529 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 340:36]
|
|
_T_342[30] <= _T_529 @[el2_lib.scala 340:30]
|
|
node _T_530 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 341:36]
|
|
_T_343[30] <= _T_530 @[el2_lib.scala 341:30]
|
|
node _T_531 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 342:36]
|
|
_T_344[30] <= _T_531 @[el2_lib.scala 342:30]
|
|
node _T_532 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 343:36]
|
|
_T_345[30] <= _T_532 @[el2_lib.scala 343:30]
|
|
node _T_533 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 344:36]
|
|
_T_346[30] <= _T_533 @[el2_lib.scala 344:30]
|
|
node _T_534 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 345:36]
|
|
_T_347[30] <= _T_534 @[el2_lib.scala 345:30]
|
|
node _T_535 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 340:36]
|
|
_T_342[31] <= _T_535 @[el2_lib.scala 340:30]
|
|
node _T_536 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 346:36]
|
|
_T_348[0] <= _T_536 @[el2_lib.scala 346:30]
|
|
node _T_537 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 341:36]
|
|
_T_343[31] <= _T_537 @[el2_lib.scala 341:30]
|
|
node _T_538 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 346:36]
|
|
_T_348[1] <= _T_538 @[el2_lib.scala 346:30]
|
|
node _T_539 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 340:36]
|
|
_T_342[32] <= _T_539 @[el2_lib.scala 340:30]
|
|
node _T_540 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 341:36]
|
|
_T_343[32] <= _T_540 @[el2_lib.scala 341:30]
|
|
node _T_541 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 346:36]
|
|
_T_348[2] <= _T_541 @[el2_lib.scala 346:30]
|
|
node _T_542 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 342:36]
|
|
_T_344[31] <= _T_542 @[el2_lib.scala 342:30]
|
|
node _T_543 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 346:36]
|
|
_T_348[3] <= _T_543 @[el2_lib.scala 346:30]
|
|
node _T_544 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 340:36]
|
|
_T_342[33] <= _T_544 @[el2_lib.scala 340:30]
|
|
node _T_545 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 342:36]
|
|
_T_344[32] <= _T_545 @[el2_lib.scala 342:30]
|
|
node _T_546 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 346:36]
|
|
_T_348[4] <= _T_546 @[el2_lib.scala 346:30]
|
|
node _T_547 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 341:36]
|
|
_T_343[33] <= _T_547 @[el2_lib.scala 341:30]
|
|
node _T_548 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 342:36]
|
|
_T_344[33] <= _T_548 @[el2_lib.scala 342:30]
|
|
node _T_549 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 346:36]
|
|
_T_348[5] <= _T_549 @[el2_lib.scala 346:30]
|
|
node _T_550 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 340:36]
|
|
_T_342[34] <= _T_550 @[el2_lib.scala 340:30]
|
|
node _T_551 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 341:36]
|
|
_T_343[34] <= _T_551 @[el2_lib.scala 341:30]
|
|
node _T_552 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 342:36]
|
|
_T_344[34] <= _T_552 @[el2_lib.scala 342:30]
|
|
node _T_553 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 346:36]
|
|
_T_348[6] <= _T_553 @[el2_lib.scala 346:30]
|
|
node _T_554 = cat(_T_342[1], _T_342[0]) @[el2_lib.scala 348:27]
|
|
node _T_555 = cat(_T_342[3], _T_342[2]) @[el2_lib.scala 348:27]
|
|
node _T_556 = cat(_T_555, _T_554) @[el2_lib.scala 348:27]
|
|
node _T_557 = cat(_T_342[5], _T_342[4]) @[el2_lib.scala 348:27]
|
|
node _T_558 = cat(_T_342[7], _T_342[6]) @[el2_lib.scala 348:27]
|
|
node _T_559 = cat(_T_558, _T_557) @[el2_lib.scala 348:27]
|
|
node _T_560 = cat(_T_559, _T_556) @[el2_lib.scala 348:27]
|
|
node _T_561 = cat(_T_342[9], _T_342[8]) @[el2_lib.scala 348:27]
|
|
node _T_562 = cat(_T_342[11], _T_342[10]) @[el2_lib.scala 348:27]
|
|
node _T_563 = cat(_T_562, _T_561) @[el2_lib.scala 348:27]
|
|
node _T_564 = cat(_T_342[13], _T_342[12]) @[el2_lib.scala 348:27]
|
|
node _T_565 = cat(_T_342[16], _T_342[15]) @[el2_lib.scala 348:27]
|
|
node _T_566 = cat(_T_565, _T_342[14]) @[el2_lib.scala 348:27]
|
|
node _T_567 = cat(_T_566, _T_564) @[el2_lib.scala 348:27]
|
|
node _T_568 = cat(_T_567, _T_563) @[el2_lib.scala 348:27]
|
|
node _T_569 = cat(_T_568, _T_560) @[el2_lib.scala 348:27]
|
|
node _T_570 = cat(_T_342[18], _T_342[17]) @[el2_lib.scala 348:27]
|
|
node _T_571 = cat(_T_342[20], _T_342[19]) @[el2_lib.scala 348:27]
|
|
node _T_572 = cat(_T_571, _T_570) @[el2_lib.scala 348:27]
|
|
node _T_573 = cat(_T_342[22], _T_342[21]) @[el2_lib.scala 348:27]
|
|
node _T_574 = cat(_T_342[25], _T_342[24]) @[el2_lib.scala 348:27]
|
|
node _T_575 = cat(_T_574, _T_342[23]) @[el2_lib.scala 348:27]
|
|
node _T_576 = cat(_T_575, _T_573) @[el2_lib.scala 348:27]
|
|
node _T_577 = cat(_T_576, _T_572) @[el2_lib.scala 348:27]
|
|
node _T_578 = cat(_T_342[27], _T_342[26]) @[el2_lib.scala 348:27]
|
|
node _T_579 = cat(_T_342[29], _T_342[28]) @[el2_lib.scala 348:27]
|
|
node _T_580 = cat(_T_579, _T_578) @[el2_lib.scala 348:27]
|
|
node _T_581 = cat(_T_342[31], _T_342[30]) @[el2_lib.scala 348:27]
|
|
node _T_582 = cat(_T_342[34], _T_342[33]) @[el2_lib.scala 348:27]
|
|
node _T_583 = cat(_T_582, _T_342[32]) @[el2_lib.scala 348:27]
|
|
node _T_584 = cat(_T_583, _T_581) @[el2_lib.scala 348:27]
|
|
node _T_585 = cat(_T_584, _T_580) @[el2_lib.scala 348:27]
|
|
node _T_586 = cat(_T_585, _T_577) @[el2_lib.scala 348:27]
|
|
node _T_587 = cat(_T_586, _T_569) @[el2_lib.scala 348:27]
|
|
node _T_588 = xorr(_T_587) @[el2_lib.scala 348:34]
|
|
node _T_589 = cat(_T_343[1], _T_343[0]) @[el2_lib.scala 348:44]
|
|
node _T_590 = cat(_T_343[3], _T_343[2]) @[el2_lib.scala 348:44]
|
|
node _T_591 = cat(_T_590, _T_589) @[el2_lib.scala 348:44]
|
|
node _T_592 = cat(_T_343[5], _T_343[4]) @[el2_lib.scala 348:44]
|
|
node _T_593 = cat(_T_343[7], _T_343[6]) @[el2_lib.scala 348:44]
|
|
node _T_594 = cat(_T_593, _T_592) @[el2_lib.scala 348:44]
|
|
node _T_595 = cat(_T_594, _T_591) @[el2_lib.scala 348:44]
|
|
node _T_596 = cat(_T_343[9], _T_343[8]) @[el2_lib.scala 348:44]
|
|
node _T_597 = cat(_T_343[11], _T_343[10]) @[el2_lib.scala 348:44]
|
|
node _T_598 = cat(_T_597, _T_596) @[el2_lib.scala 348:44]
|
|
node _T_599 = cat(_T_343[13], _T_343[12]) @[el2_lib.scala 348:44]
|
|
node _T_600 = cat(_T_343[16], _T_343[15]) @[el2_lib.scala 348:44]
|
|
node _T_601 = cat(_T_600, _T_343[14]) @[el2_lib.scala 348:44]
|
|
node _T_602 = cat(_T_601, _T_599) @[el2_lib.scala 348:44]
|
|
node _T_603 = cat(_T_602, _T_598) @[el2_lib.scala 348:44]
|
|
node _T_604 = cat(_T_603, _T_595) @[el2_lib.scala 348:44]
|
|
node _T_605 = cat(_T_343[18], _T_343[17]) @[el2_lib.scala 348:44]
|
|
node _T_606 = cat(_T_343[20], _T_343[19]) @[el2_lib.scala 348:44]
|
|
node _T_607 = cat(_T_606, _T_605) @[el2_lib.scala 348:44]
|
|
node _T_608 = cat(_T_343[22], _T_343[21]) @[el2_lib.scala 348:44]
|
|
node _T_609 = cat(_T_343[25], _T_343[24]) @[el2_lib.scala 348:44]
|
|
node _T_610 = cat(_T_609, _T_343[23]) @[el2_lib.scala 348:44]
|
|
node _T_611 = cat(_T_610, _T_608) @[el2_lib.scala 348:44]
|
|
node _T_612 = cat(_T_611, _T_607) @[el2_lib.scala 348:44]
|
|
node _T_613 = cat(_T_343[27], _T_343[26]) @[el2_lib.scala 348:44]
|
|
node _T_614 = cat(_T_343[29], _T_343[28]) @[el2_lib.scala 348:44]
|
|
node _T_615 = cat(_T_614, _T_613) @[el2_lib.scala 348:44]
|
|
node _T_616 = cat(_T_343[31], _T_343[30]) @[el2_lib.scala 348:44]
|
|
node _T_617 = cat(_T_343[34], _T_343[33]) @[el2_lib.scala 348:44]
|
|
node _T_618 = cat(_T_617, _T_343[32]) @[el2_lib.scala 348:44]
|
|
node _T_619 = cat(_T_618, _T_616) @[el2_lib.scala 348:44]
|
|
node _T_620 = cat(_T_619, _T_615) @[el2_lib.scala 348:44]
|
|
node _T_621 = cat(_T_620, _T_612) @[el2_lib.scala 348:44]
|
|
node _T_622 = cat(_T_621, _T_604) @[el2_lib.scala 348:44]
|
|
node _T_623 = xorr(_T_622) @[el2_lib.scala 348:51]
|
|
node _T_624 = cat(_T_344[1], _T_344[0]) @[el2_lib.scala 348:61]
|
|
node _T_625 = cat(_T_344[3], _T_344[2]) @[el2_lib.scala 348:61]
|
|
node _T_626 = cat(_T_625, _T_624) @[el2_lib.scala 348:61]
|
|
node _T_627 = cat(_T_344[5], _T_344[4]) @[el2_lib.scala 348:61]
|
|
node _T_628 = cat(_T_344[7], _T_344[6]) @[el2_lib.scala 348:61]
|
|
node _T_629 = cat(_T_628, _T_627) @[el2_lib.scala 348:61]
|
|
node _T_630 = cat(_T_629, _T_626) @[el2_lib.scala 348:61]
|
|
node _T_631 = cat(_T_344[9], _T_344[8]) @[el2_lib.scala 348:61]
|
|
node _T_632 = cat(_T_344[11], _T_344[10]) @[el2_lib.scala 348:61]
|
|
node _T_633 = cat(_T_632, _T_631) @[el2_lib.scala 348:61]
|
|
node _T_634 = cat(_T_344[13], _T_344[12]) @[el2_lib.scala 348:61]
|
|
node _T_635 = cat(_T_344[16], _T_344[15]) @[el2_lib.scala 348:61]
|
|
node _T_636 = cat(_T_635, _T_344[14]) @[el2_lib.scala 348:61]
|
|
node _T_637 = cat(_T_636, _T_634) @[el2_lib.scala 348:61]
|
|
node _T_638 = cat(_T_637, _T_633) @[el2_lib.scala 348:61]
|
|
node _T_639 = cat(_T_638, _T_630) @[el2_lib.scala 348:61]
|
|
node _T_640 = cat(_T_344[18], _T_344[17]) @[el2_lib.scala 348:61]
|
|
node _T_641 = cat(_T_344[20], _T_344[19]) @[el2_lib.scala 348:61]
|
|
node _T_642 = cat(_T_641, _T_640) @[el2_lib.scala 348:61]
|
|
node _T_643 = cat(_T_344[22], _T_344[21]) @[el2_lib.scala 348:61]
|
|
node _T_644 = cat(_T_344[25], _T_344[24]) @[el2_lib.scala 348:61]
|
|
node _T_645 = cat(_T_644, _T_344[23]) @[el2_lib.scala 348:61]
|
|
node _T_646 = cat(_T_645, _T_643) @[el2_lib.scala 348:61]
|
|
node _T_647 = cat(_T_646, _T_642) @[el2_lib.scala 348:61]
|
|
node _T_648 = cat(_T_344[27], _T_344[26]) @[el2_lib.scala 348:61]
|
|
node _T_649 = cat(_T_344[29], _T_344[28]) @[el2_lib.scala 348:61]
|
|
node _T_650 = cat(_T_649, _T_648) @[el2_lib.scala 348:61]
|
|
node _T_651 = cat(_T_344[31], _T_344[30]) @[el2_lib.scala 348:61]
|
|
node _T_652 = cat(_T_344[34], _T_344[33]) @[el2_lib.scala 348:61]
|
|
node _T_653 = cat(_T_652, _T_344[32]) @[el2_lib.scala 348:61]
|
|
node _T_654 = cat(_T_653, _T_651) @[el2_lib.scala 348:61]
|
|
node _T_655 = cat(_T_654, _T_650) @[el2_lib.scala 348:61]
|
|
node _T_656 = cat(_T_655, _T_647) @[el2_lib.scala 348:61]
|
|
node _T_657 = cat(_T_656, _T_639) @[el2_lib.scala 348:61]
|
|
node _T_658 = xorr(_T_657) @[el2_lib.scala 348:68]
|
|
node _T_659 = cat(_T_345[2], _T_345[1]) @[el2_lib.scala 348:78]
|
|
node _T_660 = cat(_T_659, _T_345[0]) @[el2_lib.scala 348:78]
|
|
node _T_661 = cat(_T_345[4], _T_345[3]) @[el2_lib.scala 348:78]
|
|
node _T_662 = cat(_T_345[6], _T_345[5]) @[el2_lib.scala 348:78]
|
|
node _T_663 = cat(_T_662, _T_661) @[el2_lib.scala 348:78]
|
|
node _T_664 = cat(_T_663, _T_660) @[el2_lib.scala 348:78]
|
|
node _T_665 = cat(_T_345[8], _T_345[7]) @[el2_lib.scala 348:78]
|
|
node _T_666 = cat(_T_345[10], _T_345[9]) @[el2_lib.scala 348:78]
|
|
node _T_667 = cat(_T_666, _T_665) @[el2_lib.scala 348:78]
|
|
node _T_668 = cat(_T_345[12], _T_345[11]) @[el2_lib.scala 348:78]
|
|
node _T_669 = cat(_T_345[14], _T_345[13]) @[el2_lib.scala 348:78]
|
|
node _T_670 = cat(_T_669, _T_668) @[el2_lib.scala 348:78]
|
|
node _T_671 = cat(_T_670, _T_667) @[el2_lib.scala 348:78]
|
|
node _T_672 = cat(_T_671, _T_664) @[el2_lib.scala 348:78]
|
|
node _T_673 = cat(_T_345[16], _T_345[15]) @[el2_lib.scala 348:78]
|
|
node _T_674 = cat(_T_345[18], _T_345[17]) @[el2_lib.scala 348:78]
|
|
node _T_675 = cat(_T_674, _T_673) @[el2_lib.scala 348:78]
|
|
node _T_676 = cat(_T_345[20], _T_345[19]) @[el2_lib.scala 348:78]
|
|
node _T_677 = cat(_T_345[22], _T_345[21]) @[el2_lib.scala 348:78]
|
|
node _T_678 = cat(_T_677, _T_676) @[el2_lib.scala 348:78]
|
|
node _T_679 = cat(_T_678, _T_675) @[el2_lib.scala 348:78]
|
|
node _T_680 = cat(_T_345[24], _T_345[23]) @[el2_lib.scala 348:78]
|
|
node _T_681 = cat(_T_345[26], _T_345[25]) @[el2_lib.scala 348:78]
|
|
node _T_682 = cat(_T_681, _T_680) @[el2_lib.scala 348:78]
|
|
node _T_683 = cat(_T_345[28], _T_345[27]) @[el2_lib.scala 348:78]
|
|
node _T_684 = cat(_T_345[30], _T_345[29]) @[el2_lib.scala 348:78]
|
|
node _T_685 = cat(_T_684, _T_683) @[el2_lib.scala 348:78]
|
|
node _T_686 = cat(_T_685, _T_682) @[el2_lib.scala 348:78]
|
|
node _T_687 = cat(_T_686, _T_679) @[el2_lib.scala 348:78]
|
|
node _T_688 = cat(_T_687, _T_672) @[el2_lib.scala 348:78]
|
|
node _T_689 = xorr(_T_688) @[el2_lib.scala 348:85]
|
|
node _T_690 = cat(_T_346[2], _T_346[1]) @[el2_lib.scala 348:95]
|
|
node _T_691 = cat(_T_690, _T_346[0]) @[el2_lib.scala 348:95]
|
|
node _T_692 = cat(_T_346[4], _T_346[3]) @[el2_lib.scala 348:95]
|
|
node _T_693 = cat(_T_346[6], _T_346[5]) @[el2_lib.scala 348:95]
|
|
node _T_694 = cat(_T_693, _T_692) @[el2_lib.scala 348:95]
|
|
node _T_695 = cat(_T_694, _T_691) @[el2_lib.scala 348:95]
|
|
node _T_696 = cat(_T_346[8], _T_346[7]) @[el2_lib.scala 348:95]
|
|
node _T_697 = cat(_T_346[10], _T_346[9]) @[el2_lib.scala 348:95]
|
|
node _T_698 = cat(_T_697, _T_696) @[el2_lib.scala 348:95]
|
|
node _T_699 = cat(_T_346[12], _T_346[11]) @[el2_lib.scala 348:95]
|
|
node _T_700 = cat(_T_346[14], _T_346[13]) @[el2_lib.scala 348:95]
|
|
node _T_701 = cat(_T_700, _T_699) @[el2_lib.scala 348:95]
|
|
node _T_702 = cat(_T_701, _T_698) @[el2_lib.scala 348:95]
|
|
node _T_703 = cat(_T_702, _T_695) @[el2_lib.scala 348:95]
|
|
node _T_704 = cat(_T_346[16], _T_346[15]) @[el2_lib.scala 348:95]
|
|
node _T_705 = cat(_T_346[18], _T_346[17]) @[el2_lib.scala 348:95]
|
|
node _T_706 = cat(_T_705, _T_704) @[el2_lib.scala 348:95]
|
|
node _T_707 = cat(_T_346[20], _T_346[19]) @[el2_lib.scala 348:95]
|
|
node _T_708 = cat(_T_346[22], _T_346[21]) @[el2_lib.scala 348:95]
|
|
node _T_709 = cat(_T_708, _T_707) @[el2_lib.scala 348:95]
|
|
node _T_710 = cat(_T_709, _T_706) @[el2_lib.scala 348:95]
|
|
node _T_711 = cat(_T_346[24], _T_346[23]) @[el2_lib.scala 348:95]
|
|
node _T_712 = cat(_T_346[26], _T_346[25]) @[el2_lib.scala 348:95]
|
|
node _T_713 = cat(_T_712, _T_711) @[el2_lib.scala 348:95]
|
|
node _T_714 = cat(_T_346[28], _T_346[27]) @[el2_lib.scala 348:95]
|
|
node _T_715 = cat(_T_346[30], _T_346[29]) @[el2_lib.scala 348:95]
|
|
node _T_716 = cat(_T_715, _T_714) @[el2_lib.scala 348:95]
|
|
node _T_717 = cat(_T_716, _T_713) @[el2_lib.scala 348:95]
|
|
node _T_718 = cat(_T_717, _T_710) @[el2_lib.scala 348:95]
|
|
node _T_719 = cat(_T_718, _T_703) @[el2_lib.scala 348:95]
|
|
node _T_720 = xorr(_T_719) @[el2_lib.scala 348:102]
|
|
node _T_721 = cat(_T_347[2], _T_347[1]) @[el2_lib.scala 348:112]
|
|
node _T_722 = cat(_T_721, _T_347[0]) @[el2_lib.scala 348:112]
|
|
node _T_723 = cat(_T_347[4], _T_347[3]) @[el2_lib.scala 348:112]
|
|
node _T_724 = cat(_T_347[6], _T_347[5]) @[el2_lib.scala 348:112]
|
|
node _T_725 = cat(_T_724, _T_723) @[el2_lib.scala 348:112]
|
|
node _T_726 = cat(_T_725, _T_722) @[el2_lib.scala 348:112]
|
|
node _T_727 = cat(_T_347[8], _T_347[7]) @[el2_lib.scala 348:112]
|
|
node _T_728 = cat(_T_347[10], _T_347[9]) @[el2_lib.scala 348:112]
|
|
node _T_729 = cat(_T_728, _T_727) @[el2_lib.scala 348:112]
|
|
node _T_730 = cat(_T_347[12], _T_347[11]) @[el2_lib.scala 348:112]
|
|
node _T_731 = cat(_T_347[14], _T_347[13]) @[el2_lib.scala 348:112]
|
|
node _T_732 = cat(_T_731, _T_730) @[el2_lib.scala 348:112]
|
|
node _T_733 = cat(_T_732, _T_729) @[el2_lib.scala 348:112]
|
|
node _T_734 = cat(_T_733, _T_726) @[el2_lib.scala 348:112]
|
|
node _T_735 = cat(_T_347[16], _T_347[15]) @[el2_lib.scala 348:112]
|
|
node _T_736 = cat(_T_347[18], _T_347[17]) @[el2_lib.scala 348:112]
|
|
node _T_737 = cat(_T_736, _T_735) @[el2_lib.scala 348:112]
|
|
node _T_738 = cat(_T_347[20], _T_347[19]) @[el2_lib.scala 348:112]
|
|
node _T_739 = cat(_T_347[22], _T_347[21]) @[el2_lib.scala 348:112]
|
|
node _T_740 = cat(_T_739, _T_738) @[el2_lib.scala 348:112]
|
|
node _T_741 = cat(_T_740, _T_737) @[el2_lib.scala 348:112]
|
|
node _T_742 = cat(_T_347[24], _T_347[23]) @[el2_lib.scala 348:112]
|
|
node _T_743 = cat(_T_347[26], _T_347[25]) @[el2_lib.scala 348:112]
|
|
node _T_744 = cat(_T_743, _T_742) @[el2_lib.scala 348:112]
|
|
node _T_745 = cat(_T_347[28], _T_347[27]) @[el2_lib.scala 348:112]
|
|
node _T_746 = cat(_T_347[30], _T_347[29]) @[el2_lib.scala 348:112]
|
|
node _T_747 = cat(_T_746, _T_745) @[el2_lib.scala 348:112]
|
|
node _T_748 = cat(_T_747, _T_744) @[el2_lib.scala 348:112]
|
|
node _T_749 = cat(_T_748, _T_741) @[el2_lib.scala 348:112]
|
|
node _T_750 = cat(_T_749, _T_734) @[el2_lib.scala 348:112]
|
|
node _T_751 = xorr(_T_750) @[el2_lib.scala 348:119]
|
|
node _T_752 = cat(_T_348[2], _T_348[1]) @[el2_lib.scala 348:129]
|
|
node _T_753 = cat(_T_752, _T_348[0]) @[el2_lib.scala 348:129]
|
|
node _T_754 = cat(_T_348[4], _T_348[3]) @[el2_lib.scala 348:129]
|
|
node _T_755 = cat(_T_348[6], _T_348[5]) @[el2_lib.scala 348:129]
|
|
node _T_756 = cat(_T_755, _T_754) @[el2_lib.scala 348:129]
|
|
node _T_757 = cat(_T_756, _T_753) @[el2_lib.scala 348:129]
|
|
node _T_758 = xorr(_T_757) @[el2_lib.scala 348:136]
|
|
node _T_759 = cat(_T_720, _T_751) @[Cat.scala 29:58]
|
|
node _T_760 = cat(_T_759, _T_758) @[Cat.scala 29:58]
|
|
node _T_761 = cat(_T_658, _T_689) @[Cat.scala 29:58]
|
|
node _T_762 = cat(_T_588, _T_623) @[Cat.scala 29:58]
|
|
node _T_763 = cat(_T_762, _T_761) @[Cat.scala 29:58]
|
|
node ic_wr_ecc = cat(_T_763, _T_760) @[Cat.scala 29:58]
|
|
wire _T_764 : UInt<1>[35] @[el2_lib.scala 327:18]
|
|
wire _T_765 : UInt<1>[35] @[el2_lib.scala 328:18]
|
|
wire _T_766 : UInt<1>[35] @[el2_lib.scala 329:18]
|
|
wire _T_767 : UInt<1>[31] @[el2_lib.scala 330:18]
|
|
wire _T_768 : UInt<1>[31] @[el2_lib.scala 331:18]
|
|
wire _T_769 : UInt<1>[31] @[el2_lib.scala 332:18]
|
|
wire _T_770 : UInt<1>[7] @[el2_lib.scala 333:18]
|
|
node _T_771 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 340:36]
|
|
_T_764[0] <= _T_771 @[el2_lib.scala 340:30]
|
|
node _T_772 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 341:36]
|
|
_T_765[0] <= _T_772 @[el2_lib.scala 341:30]
|
|
node _T_773 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 340:36]
|
|
_T_764[1] <= _T_773 @[el2_lib.scala 340:30]
|
|
node _T_774 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 342:36]
|
|
_T_766[0] <= _T_774 @[el2_lib.scala 342:30]
|
|
node _T_775 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 341:36]
|
|
_T_765[1] <= _T_775 @[el2_lib.scala 341:30]
|
|
node _T_776 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 342:36]
|
|
_T_766[1] <= _T_776 @[el2_lib.scala 342:30]
|
|
node _T_777 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 340:36]
|
|
_T_764[2] <= _T_777 @[el2_lib.scala 340:30]
|
|
node _T_778 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 341:36]
|
|
_T_765[2] <= _T_778 @[el2_lib.scala 341:30]
|
|
node _T_779 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 342:36]
|
|
_T_766[2] <= _T_779 @[el2_lib.scala 342:30]
|
|
node _T_780 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 340:36]
|
|
_T_764[3] <= _T_780 @[el2_lib.scala 340:30]
|
|
node _T_781 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 343:36]
|
|
_T_767[0] <= _T_781 @[el2_lib.scala 343:30]
|
|
node _T_782 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 341:36]
|
|
_T_765[3] <= _T_782 @[el2_lib.scala 341:30]
|
|
node _T_783 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 343:36]
|
|
_T_767[1] <= _T_783 @[el2_lib.scala 343:30]
|
|
node _T_784 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 340:36]
|
|
_T_764[4] <= _T_784 @[el2_lib.scala 340:30]
|
|
node _T_785 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 341:36]
|
|
_T_765[4] <= _T_785 @[el2_lib.scala 341:30]
|
|
node _T_786 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 343:36]
|
|
_T_767[2] <= _T_786 @[el2_lib.scala 343:30]
|
|
node _T_787 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 342:36]
|
|
_T_766[3] <= _T_787 @[el2_lib.scala 342:30]
|
|
node _T_788 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 343:36]
|
|
_T_767[3] <= _T_788 @[el2_lib.scala 343:30]
|
|
node _T_789 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 340:36]
|
|
_T_764[5] <= _T_789 @[el2_lib.scala 340:30]
|
|
node _T_790 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 342:36]
|
|
_T_766[4] <= _T_790 @[el2_lib.scala 342:30]
|
|
node _T_791 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 343:36]
|
|
_T_767[4] <= _T_791 @[el2_lib.scala 343:30]
|
|
node _T_792 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 341:36]
|
|
_T_765[5] <= _T_792 @[el2_lib.scala 341:30]
|
|
node _T_793 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 342:36]
|
|
_T_766[5] <= _T_793 @[el2_lib.scala 342:30]
|
|
node _T_794 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 343:36]
|
|
_T_767[5] <= _T_794 @[el2_lib.scala 343:30]
|
|
node _T_795 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 340:36]
|
|
_T_764[6] <= _T_795 @[el2_lib.scala 340:30]
|
|
node _T_796 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 341:36]
|
|
_T_765[6] <= _T_796 @[el2_lib.scala 341:30]
|
|
node _T_797 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 342:36]
|
|
_T_766[6] <= _T_797 @[el2_lib.scala 342:30]
|
|
node _T_798 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 343:36]
|
|
_T_767[6] <= _T_798 @[el2_lib.scala 343:30]
|
|
node _T_799 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 340:36]
|
|
_T_764[7] <= _T_799 @[el2_lib.scala 340:30]
|
|
node _T_800 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 344:36]
|
|
_T_768[0] <= _T_800 @[el2_lib.scala 344:30]
|
|
node _T_801 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 341:36]
|
|
_T_765[7] <= _T_801 @[el2_lib.scala 341:30]
|
|
node _T_802 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 344:36]
|
|
_T_768[1] <= _T_802 @[el2_lib.scala 344:30]
|
|
node _T_803 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 340:36]
|
|
_T_764[8] <= _T_803 @[el2_lib.scala 340:30]
|
|
node _T_804 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 341:36]
|
|
_T_765[8] <= _T_804 @[el2_lib.scala 341:30]
|
|
node _T_805 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 344:36]
|
|
_T_768[2] <= _T_805 @[el2_lib.scala 344:30]
|
|
node _T_806 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 342:36]
|
|
_T_766[7] <= _T_806 @[el2_lib.scala 342:30]
|
|
node _T_807 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 344:36]
|
|
_T_768[3] <= _T_807 @[el2_lib.scala 344:30]
|
|
node _T_808 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 340:36]
|
|
_T_764[9] <= _T_808 @[el2_lib.scala 340:30]
|
|
node _T_809 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 342:36]
|
|
_T_766[8] <= _T_809 @[el2_lib.scala 342:30]
|
|
node _T_810 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 344:36]
|
|
_T_768[4] <= _T_810 @[el2_lib.scala 344:30]
|
|
node _T_811 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 341:36]
|
|
_T_765[9] <= _T_811 @[el2_lib.scala 341:30]
|
|
node _T_812 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 342:36]
|
|
_T_766[9] <= _T_812 @[el2_lib.scala 342:30]
|
|
node _T_813 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 344:36]
|
|
_T_768[5] <= _T_813 @[el2_lib.scala 344:30]
|
|
node _T_814 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 340:36]
|
|
_T_764[10] <= _T_814 @[el2_lib.scala 340:30]
|
|
node _T_815 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 341:36]
|
|
_T_765[10] <= _T_815 @[el2_lib.scala 341:30]
|
|
node _T_816 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 342:36]
|
|
_T_766[10] <= _T_816 @[el2_lib.scala 342:30]
|
|
node _T_817 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 344:36]
|
|
_T_768[6] <= _T_817 @[el2_lib.scala 344:30]
|
|
node _T_818 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 343:36]
|
|
_T_767[7] <= _T_818 @[el2_lib.scala 343:30]
|
|
node _T_819 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 344:36]
|
|
_T_768[7] <= _T_819 @[el2_lib.scala 344:30]
|
|
node _T_820 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 340:36]
|
|
_T_764[11] <= _T_820 @[el2_lib.scala 340:30]
|
|
node _T_821 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 343:36]
|
|
_T_767[8] <= _T_821 @[el2_lib.scala 343:30]
|
|
node _T_822 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 344:36]
|
|
_T_768[8] <= _T_822 @[el2_lib.scala 344:30]
|
|
node _T_823 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 341:36]
|
|
_T_765[11] <= _T_823 @[el2_lib.scala 341:30]
|
|
node _T_824 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 343:36]
|
|
_T_767[9] <= _T_824 @[el2_lib.scala 343:30]
|
|
node _T_825 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 344:36]
|
|
_T_768[9] <= _T_825 @[el2_lib.scala 344:30]
|
|
node _T_826 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 340:36]
|
|
_T_764[12] <= _T_826 @[el2_lib.scala 340:30]
|
|
node _T_827 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 341:36]
|
|
_T_765[12] <= _T_827 @[el2_lib.scala 341:30]
|
|
node _T_828 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 343:36]
|
|
_T_767[10] <= _T_828 @[el2_lib.scala 343:30]
|
|
node _T_829 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 344:36]
|
|
_T_768[10] <= _T_829 @[el2_lib.scala 344:30]
|
|
node _T_830 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 342:36]
|
|
_T_766[11] <= _T_830 @[el2_lib.scala 342:30]
|
|
node _T_831 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 343:36]
|
|
_T_767[11] <= _T_831 @[el2_lib.scala 343:30]
|
|
node _T_832 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 344:36]
|
|
_T_768[11] <= _T_832 @[el2_lib.scala 344:30]
|
|
node _T_833 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 340:36]
|
|
_T_764[13] <= _T_833 @[el2_lib.scala 340:30]
|
|
node _T_834 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 342:36]
|
|
_T_766[12] <= _T_834 @[el2_lib.scala 342:30]
|
|
node _T_835 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 343:36]
|
|
_T_767[12] <= _T_835 @[el2_lib.scala 343:30]
|
|
node _T_836 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 344:36]
|
|
_T_768[12] <= _T_836 @[el2_lib.scala 344:30]
|
|
node _T_837 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 341:36]
|
|
_T_765[13] <= _T_837 @[el2_lib.scala 341:30]
|
|
node _T_838 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 342:36]
|
|
_T_766[13] <= _T_838 @[el2_lib.scala 342:30]
|
|
node _T_839 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 343:36]
|
|
_T_767[13] <= _T_839 @[el2_lib.scala 343:30]
|
|
node _T_840 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 344:36]
|
|
_T_768[13] <= _T_840 @[el2_lib.scala 344:30]
|
|
node _T_841 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 340:36]
|
|
_T_764[14] <= _T_841 @[el2_lib.scala 340:30]
|
|
node _T_842 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 341:36]
|
|
_T_765[14] <= _T_842 @[el2_lib.scala 341:30]
|
|
node _T_843 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 342:36]
|
|
_T_766[14] <= _T_843 @[el2_lib.scala 342:30]
|
|
node _T_844 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 343:36]
|
|
_T_767[14] <= _T_844 @[el2_lib.scala 343:30]
|
|
node _T_845 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 344:36]
|
|
_T_768[14] <= _T_845 @[el2_lib.scala 344:30]
|
|
node _T_846 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 340:36]
|
|
_T_764[15] <= _T_846 @[el2_lib.scala 340:30]
|
|
node _T_847 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 345:36]
|
|
_T_769[0] <= _T_847 @[el2_lib.scala 345:30]
|
|
node _T_848 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 341:36]
|
|
_T_765[15] <= _T_848 @[el2_lib.scala 341:30]
|
|
node _T_849 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 345:36]
|
|
_T_769[1] <= _T_849 @[el2_lib.scala 345:30]
|
|
node _T_850 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 340:36]
|
|
_T_764[16] <= _T_850 @[el2_lib.scala 340:30]
|
|
node _T_851 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 341:36]
|
|
_T_765[16] <= _T_851 @[el2_lib.scala 341:30]
|
|
node _T_852 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 345:36]
|
|
_T_769[2] <= _T_852 @[el2_lib.scala 345:30]
|
|
node _T_853 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 342:36]
|
|
_T_766[15] <= _T_853 @[el2_lib.scala 342:30]
|
|
node _T_854 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 345:36]
|
|
_T_769[3] <= _T_854 @[el2_lib.scala 345:30]
|
|
node _T_855 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 340:36]
|
|
_T_764[17] <= _T_855 @[el2_lib.scala 340:30]
|
|
node _T_856 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 342:36]
|
|
_T_766[16] <= _T_856 @[el2_lib.scala 342:30]
|
|
node _T_857 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 345:36]
|
|
_T_769[4] <= _T_857 @[el2_lib.scala 345:30]
|
|
node _T_858 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 341:36]
|
|
_T_765[17] <= _T_858 @[el2_lib.scala 341:30]
|
|
node _T_859 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 342:36]
|
|
_T_766[17] <= _T_859 @[el2_lib.scala 342:30]
|
|
node _T_860 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 345:36]
|
|
_T_769[5] <= _T_860 @[el2_lib.scala 345:30]
|
|
node _T_861 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 340:36]
|
|
_T_764[18] <= _T_861 @[el2_lib.scala 340:30]
|
|
node _T_862 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 341:36]
|
|
_T_765[18] <= _T_862 @[el2_lib.scala 341:30]
|
|
node _T_863 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 342:36]
|
|
_T_766[18] <= _T_863 @[el2_lib.scala 342:30]
|
|
node _T_864 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 345:36]
|
|
_T_769[6] <= _T_864 @[el2_lib.scala 345:30]
|
|
node _T_865 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 343:36]
|
|
_T_767[15] <= _T_865 @[el2_lib.scala 343:30]
|
|
node _T_866 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 345:36]
|
|
_T_769[7] <= _T_866 @[el2_lib.scala 345:30]
|
|
node _T_867 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 340:36]
|
|
_T_764[19] <= _T_867 @[el2_lib.scala 340:30]
|
|
node _T_868 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 343:36]
|
|
_T_767[16] <= _T_868 @[el2_lib.scala 343:30]
|
|
node _T_869 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 345:36]
|
|
_T_769[8] <= _T_869 @[el2_lib.scala 345:30]
|
|
node _T_870 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 341:36]
|
|
_T_765[19] <= _T_870 @[el2_lib.scala 341:30]
|
|
node _T_871 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 343:36]
|
|
_T_767[17] <= _T_871 @[el2_lib.scala 343:30]
|
|
node _T_872 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 345:36]
|
|
_T_769[9] <= _T_872 @[el2_lib.scala 345:30]
|
|
node _T_873 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 340:36]
|
|
_T_764[20] <= _T_873 @[el2_lib.scala 340:30]
|
|
node _T_874 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 341:36]
|
|
_T_765[20] <= _T_874 @[el2_lib.scala 341:30]
|
|
node _T_875 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 343:36]
|
|
_T_767[18] <= _T_875 @[el2_lib.scala 343:30]
|
|
node _T_876 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 345:36]
|
|
_T_769[10] <= _T_876 @[el2_lib.scala 345:30]
|
|
node _T_877 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 342:36]
|
|
_T_766[19] <= _T_877 @[el2_lib.scala 342:30]
|
|
node _T_878 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 343:36]
|
|
_T_767[19] <= _T_878 @[el2_lib.scala 343:30]
|
|
node _T_879 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 345:36]
|
|
_T_769[11] <= _T_879 @[el2_lib.scala 345:30]
|
|
node _T_880 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 340:36]
|
|
_T_764[21] <= _T_880 @[el2_lib.scala 340:30]
|
|
node _T_881 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 342:36]
|
|
_T_766[20] <= _T_881 @[el2_lib.scala 342:30]
|
|
node _T_882 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 343:36]
|
|
_T_767[20] <= _T_882 @[el2_lib.scala 343:30]
|
|
node _T_883 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 345:36]
|
|
_T_769[12] <= _T_883 @[el2_lib.scala 345:30]
|
|
node _T_884 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 341:36]
|
|
_T_765[21] <= _T_884 @[el2_lib.scala 341:30]
|
|
node _T_885 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 342:36]
|
|
_T_766[21] <= _T_885 @[el2_lib.scala 342:30]
|
|
node _T_886 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 343:36]
|
|
_T_767[21] <= _T_886 @[el2_lib.scala 343:30]
|
|
node _T_887 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 345:36]
|
|
_T_769[13] <= _T_887 @[el2_lib.scala 345:30]
|
|
node _T_888 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 340:36]
|
|
_T_764[22] <= _T_888 @[el2_lib.scala 340:30]
|
|
node _T_889 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 341:36]
|
|
_T_765[22] <= _T_889 @[el2_lib.scala 341:30]
|
|
node _T_890 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 342:36]
|
|
_T_766[22] <= _T_890 @[el2_lib.scala 342:30]
|
|
node _T_891 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 343:36]
|
|
_T_767[22] <= _T_891 @[el2_lib.scala 343:30]
|
|
node _T_892 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 345:36]
|
|
_T_769[14] <= _T_892 @[el2_lib.scala 345:30]
|
|
node _T_893 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 344:36]
|
|
_T_768[15] <= _T_893 @[el2_lib.scala 344:30]
|
|
node _T_894 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 345:36]
|
|
_T_769[15] <= _T_894 @[el2_lib.scala 345:30]
|
|
node _T_895 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 340:36]
|
|
_T_764[23] <= _T_895 @[el2_lib.scala 340:30]
|
|
node _T_896 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 344:36]
|
|
_T_768[16] <= _T_896 @[el2_lib.scala 344:30]
|
|
node _T_897 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 345:36]
|
|
_T_769[16] <= _T_897 @[el2_lib.scala 345:30]
|
|
node _T_898 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 341:36]
|
|
_T_765[23] <= _T_898 @[el2_lib.scala 341:30]
|
|
node _T_899 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 344:36]
|
|
_T_768[17] <= _T_899 @[el2_lib.scala 344:30]
|
|
node _T_900 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 345:36]
|
|
_T_769[17] <= _T_900 @[el2_lib.scala 345:30]
|
|
node _T_901 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 340:36]
|
|
_T_764[24] <= _T_901 @[el2_lib.scala 340:30]
|
|
node _T_902 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 341:36]
|
|
_T_765[24] <= _T_902 @[el2_lib.scala 341:30]
|
|
node _T_903 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 344:36]
|
|
_T_768[18] <= _T_903 @[el2_lib.scala 344:30]
|
|
node _T_904 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 345:36]
|
|
_T_769[18] <= _T_904 @[el2_lib.scala 345:30]
|
|
node _T_905 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 342:36]
|
|
_T_766[23] <= _T_905 @[el2_lib.scala 342:30]
|
|
node _T_906 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 344:36]
|
|
_T_768[19] <= _T_906 @[el2_lib.scala 344:30]
|
|
node _T_907 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 345:36]
|
|
_T_769[19] <= _T_907 @[el2_lib.scala 345:30]
|
|
node _T_908 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 340:36]
|
|
_T_764[25] <= _T_908 @[el2_lib.scala 340:30]
|
|
node _T_909 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 342:36]
|
|
_T_766[24] <= _T_909 @[el2_lib.scala 342:30]
|
|
node _T_910 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 344:36]
|
|
_T_768[20] <= _T_910 @[el2_lib.scala 344:30]
|
|
node _T_911 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 345:36]
|
|
_T_769[20] <= _T_911 @[el2_lib.scala 345:30]
|
|
node _T_912 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 341:36]
|
|
_T_765[25] <= _T_912 @[el2_lib.scala 341:30]
|
|
node _T_913 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 342:36]
|
|
_T_766[25] <= _T_913 @[el2_lib.scala 342:30]
|
|
node _T_914 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 344:36]
|
|
_T_768[21] <= _T_914 @[el2_lib.scala 344:30]
|
|
node _T_915 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 345:36]
|
|
_T_769[21] <= _T_915 @[el2_lib.scala 345:30]
|
|
node _T_916 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 340:36]
|
|
_T_764[26] <= _T_916 @[el2_lib.scala 340:30]
|
|
node _T_917 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 341:36]
|
|
_T_765[26] <= _T_917 @[el2_lib.scala 341:30]
|
|
node _T_918 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 342:36]
|
|
_T_766[26] <= _T_918 @[el2_lib.scala 342:30]
|
|
node _T_919 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 344:36]
|
|
_T_768[22] <= _T_919 @[el2_lib.scala 344:30]
|
|
node _T_920 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 345:36]
|
|
_T_769[22] <= _T_920 @[el2_lib.scala 345:30]
|
|
node _T_921 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 343:36]
|
|
_T_767[23] <= _T_921 @[el2_lib.scala 343:30]
|
|
node _T_922 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 344:36]
|
|
_T_768[23] <= _T_922 @[el2_lib.scala 344:30]
|
|
node _T_923 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 345:36]
|
|
_T_769[23] <= _T_923 @[el2_lib.scala 345:30]
|
|
node _T_924 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 340:36]
|
|
_T_764[27] <= _T_924 @[el2_lib.scala 340:30]
|
|
node _T_925 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 343:36]
|
|
_T_767[24] <= _T_925 @[el2_lib.scala 343:30]
|
|
node _T_926 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 344:36]
|
|
_T_768[24] <= _T_926 @[el2_lib.scala 344:30]
|
|
node _T_927 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 345:36]
|
|
_T_769[24] <= _T_927 @[el2_lib.scala 345:30]
|
|
node _T_928 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 341:36]
|
|
_T_765[27] <= _T_928 @[el2_lib.scala 341:30]
|
|
node _T_929 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 343:36]
|
|
_T_767[25] <= _T_929 @[el2_lib.scala 343:30]
|
|
node _T_930 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 344:36]
|
|
_T_768[25] <= _T_930 @[el2_lib.scala 344:30]
|
|
node _T_931 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 345:36]
|
|
_T_769[25] <= _T_931 @[el2_lib.scala 345:30]
|
|
node _T_932 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 340:36]
|
|
_T_764[28] <= _T_932 @[el2_lib.scala 340:30]
|
|
node _T_933 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 341:36]
|
|
_T_765[28] <= _T_933 @[el2_lib.scala 341:30]
|
|
node _T_934 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 343:36]
|
|
_T_767[26] <= _T_934 @[el2_lib.scala 343:30]
|
|
node _T_935 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 344:36]
|
|
_T_768[26] <= _T_935 @[el2_lib.scala 344:30]
|
|
node _T_936 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 345:36]
|
|
_T_769[26] <= _T_936 @[el2_lib.scala 345:30]
|
|
node _T_937 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 342:36]
|
|
_T_766[27] <= _T_937 @[el2_lib.scala 342:30]
|
|
node _T_938 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 343:36]
|
|
_T_767[27] <= _T_938 @[el2_lib.scala 343:30]
|
|
node _T_939 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 344:36]
|
|
_T_768[27] <= _T_939 @[el2_lib.scala 344:30]
|
|
node _T_940 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 345:36]
|
|
_T_769[27] <= _T_940 @[el2_lib.scala 345:30]
|
|
node _T_941 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 340:36]
|
|
_T_764[29] <= _T_941 @[el2_lib.scala 340:30]
|
|
node _T_942 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 342:36]
|
|
_T_766[28] <= _T_942 @[el2_lib.scala 342:30]
|
|
node _T_943 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 343:36]
|
|
_T_767[28] <= _T_943 @[el2_lib.scala 343:30]
|
|
node _T_944 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 344:36]
|
|
_T_768[28] <= _T_944 @[el2_lib.scala 344:30]
|
|
node _T_945 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 345:36]
|
|
_T_769[28] <= _T_945 @[el2_lib.scala 345:30]
|
|
node _T_946 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 341:36]
|
|
_T_765[29] <= _T_946 @[el2_lib.scala 341:30]
|
|
node _T_947 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 342:36]
|
|
_T_766[29] <= _T_947 @[el2_lib.scala 342:30]
|
|
node _T_948 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 343:36]
|
|
_T_767[29] <= _T_948 @[el2_lib.scala 343:30]
|
|
node _T_949 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 344:36]
|
|
_T_768[29] <= _T_949 @[el2_lib.scala 344:30]
|
|
node _T_950 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 345:36]
|
|
_T_769[29] <= _T_950 @[el2_lib.scala 345:30]
|
|
node _T_951 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 340:36]
|
|
_T_764[30] <= _T_951 @[el2_lib.scala 340:30]
|
|
node _T_952 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 341:36]
|
|
_T_765[30] <= _T_952 @[el2_lib.scala 341:30]
|
|
node _T_953 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 342:36]
|
|
_T_766[30] <= _T_953 @[el2_lib.scala 342:30]
|
|
node _T_954 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 343:36]
|
|
_T_767[30] <= _T_954 @[el2_lib.scala 343:30]
|
|
node _T_955 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 344:36]
|
|
_T_768[30] <= _T_955 @[el2_lib.scala 344:30]
|
|
node _T_956 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 345:36]
|
|
_T_769[30] <= _T_956 @[el2_lib.scala 345:30]
|
|
node _T_957 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 340:36]
|
|
_T_764[31] <= _T_957 @[el2_lib.scala 340:30]
|
|
node _T_958 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 346:36]
|
|
_T_770[0] <= _T_958 @[el2_lib.scala 346:30]
|
|
node _T_959 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 341:36]
|
|
_T_765[31] <= _T_959 @[el2_lib.scala 341:30]
|
|
node _T_960 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 346:36]
|
|
_T_770[1] <= _T_960 @[el2_lib.scala 346:30]
|
|
node _T_961 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 340:36]
|
|
_T_764[32] <= _T_961 @[el2_lib.scala 340:30]
|
|
node _T_962 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 341:36]
|
|
_T_765[32] <= _T_962 @[el2_lib.scala 341:30]
|
|
node _T_963 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 346:36]
|
|
_T_770[2] <= _T_963 @[el2_lib.scala 346:30]
|
|
node _T_964 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 342:36]
|
|
_T_766[31] <= _T_964 @[el2_lib.scala 342:30]
|
|
node _T_965 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 346:36]
|
|
_T_770[3] <= _T_965 @[el2_lib.scala 346:30]
|
|
node _T_966 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 340:36]
|
|
_T_764[33] <= _T_966 @[el2_lib.scala 340:30]
|
|
node _T_967 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 342:36]
|
|
_T_766[32] <= _T_967 @[el2_lib.scala 342:30]
|
|
node _T_968 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 346:36]
|
|
_T_770[4] <= _T_968 @[el2_lib.scala 346:30]
|
|
node _T_969 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 341:36]
|
|
_T_765[33] <= _T_969 @[el2_lib.scala 341:30]
|
|
node _T_970 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 342:36]
|
|
_T_766[33] <= _T_970 @[el2_lib.scala 342:30]
|
|
node _T_971 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 346:36]
|
|
_T_770[5] <= _T_971 @[el2_lib.scala 346:30]
|
|
node _T_972 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 340:36]
|
|
_T_764[34] <= _T_972 @[el2_lib.scala 340:30]
|
|
node _T_973 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 341:36]
|
|
_T_765[34] <= _T_973 @[el2_lib.scala 341:30]
|
|
node _T_974 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 342:36]
|
|
_T_766[34] <= _T_974 @[el2_lib.scala 342:30]
|
|
node _T_975 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 346:36]
|
|
_T_770[6] <= _T_975 @[el2_lib.scala 346:30]
|
|
node _T_976 = cat(_T_764[1], _T_764[0]) @[el2_lib.scala 348:27]
|
|
node _T_977 = cat(_T_764[3], _T_764[2]) @[el2_lib.scala 348:27]
|
|
node _T_978 = cat(_T_977, _T_976) @[el2_lib.scala 348:27]
|
|
node _T_979 = cat(_T_764[5], _T_764[4]) @[el2_lib.scala 348:27]
|
|
node _T_980 = cat(_T_764[7], _T_764[6]) @[el2_lib.scala 348:27]
|
|
node _T_981 = cat(_T_980, _T_979) @[el2_lib.scala 348:27]
|
|
node _T_982 = cat(_T_981, _T_978) @[el2_lib.scala 348:27]
|
|
node _T_983 = cat(_T_764[9], _T_764[8]) @[el2_lib.scala 348:27]
|
|
node _T_984 = cat(_T_764[11], _T_764[10]) @[el2_lib.scala 348:27]
|
|
node _T_985 = cat(_T_984, _T_983) @[el2_lib.scala 348:27]
|
|
node _T_986 = cat(_T_764[13], _T_764[12]) @[el2_lib.scala 348:27]
|
|
node _T_987 = cat(_T_764[16], _T_764[15]) @[el2_lib.scala 348:27]
|
|
node _T_988 = cat(_T_987, _T_764[14]) @[el2_lib.scala 348:27]
|
|
node _T_989 = cat(_T_988, _T_986) @[el2_lib.scala 348:27]
|
|
node _T_990 = cat(_T_989, _T_985) @[el2_lib.scala 348:27]
|
|
node _T_991 = cat(_T_990, _T_982) @[el2_lib.scala 348:27]
|
|
node _T_992 = cat(_T_764[18], _T_764[17]) @[el2_lib.scala 348:27]
|
|
node _T_993 = cat(_T_764[20], _T_764[19]) @[el2_lib.scala 348:27]
|
|
node _T_994 = cat(_T_993, _T_992) @[el2_lib.scala 348:27]
|
|
node _T_995 = cat(_T_764[22], _T_764[21]) @[el2_lib.scala 348:27]
|
|
node _T_996 = cat(_T_764[25], _T_764[24]) @[el2_lib.scala 348:27]
|
|
node _T_997 = cat(_T_996, _T_764[23]) @[el2_lib.scala 348:27]
|
|
node _T_998 = cat(_T_997, _T_995) @[el2_lib.scala 348:27]
|
|
node _T_999 = cat(_T_998, _T_994) @[el2_lib.scala 348:27]
|
|
node _T_1000 = cat(_T_764[27], _T_764[26]) @[el2_lib.scala 348:27]
|
|
node _T_1001 = cat(_T_764[29], _T_764[28]) @[el2_lib.scala 348:27]
|
|
node _T_1002 = cat(_T_1001, _T_1000) @[el2_lib.scala 348:27]
|
|
node _T_1003 = cat(_T_764[31], _T_764[30]) @[el2_lib.scala 348:27]
|
|
node _T_1004 = cat(_T_764[34], _T_764[33]) @[el2_lib.scala 348:27]
|
|
node _T_1005 = cat(_T_1004, _T_764[32]) @[el2_lib.scala 348:27]
|
|
node _T_1006 = cat(_T_1005, _T_1003) @[el2_lib.scala 348:27]
|
|
node _T_1007 = cat(_T_1006, _T_1002) @[el2_lib.scala 348:27]
|
|
node _T_1008 = cat(_T_1007, _T_999) @[el2_lib.scala 348:27]
|
|
node _T_1009 = cat(_T_1008, _T_991) @[el2_lib.scala 348:27]
|
|
node _T_1010 = xorr(_T_1009) @[el2_lib.scala 348:34]
|
|
node _T_1011 = cat(_T_765[1], _T_765[0]) @[el2_lib.scala 348:44]
|
|
node _T_1012 = cat(_T_765[3], _T_765[2]) @[el2_lib.scala 348:44]
|
|
node _T_1013 = cat(_T_1012, _T_1011) @[el2_lib.scala 348:44]
|
|
node _T_1014 = cat(_T_765[5], _T_765[4]) @[el2_lib.scala 348:44]
|
|
node _T_1015 = cat(_T_765[7], _T_765[6]) @[el2_lib.scala 348:44]
|
|
node _T_1016 = cat(_T_1015, _T_1014) @[el2_lib.scala 348:44]
|
|
node _T_1017 = cat(_T_1016, _T_1013) @[el2_lib.scala 348:44]
|
|
node _T_1018 = cat(_T_765[9], _T_765[8]) @[el2_lib.scala 348:44]
|
|
node _T_1019 = cat(_T_765[11], _T_765[10]) @[el2_lib.scala 348:44]
|
|
node _T_1020 = cat(_T_1019, _T_1018) @[el2_lib.scala 348:44]
|
|
node _T_1021 = cat(_T_765[13], _T_765[12]) @[el2_lib.scala 348:44]
|
|
node _T_1022 = cat(_T_765[16], _T_765[15]) @[el2_lib.scala 348:44]
|
|
node _T_1023 = cat(_T_1022, _T_765[14]) @[el2_lib.scala 348:44]
|
|
node _T_1024 = cat(_T_1023, _T_1021) @[el2_lib.scala 348:44]
|
|
node _T_1025 = cat(_T_1024, _T_1020) @[el2_lib.scala 348:44]
|
|
node _T_1026 = cat(_T_1025, _T_1017) @[el2_lib.scala 348:44]
|
|
node _T_1027 = cat(_T_765[18], _T_765[17]) @[el2_lib.scala 348:44]
|
|
node _T_1028 = cat(_T_765[20], _T_765[19]) @[el2_lib.scala 348:44]
|
|
node _T_1029 = cat(_T_1028, _T_1027) @[el2_lib.scala 348:44]
|
|
node _T_1030 = cat(_T_765[22], _T_765[21]) @[el2_lib.scala 348:44]
|
|
node _T_1031 = cat(_T_765[25], _T_765[24]) @[el2_lib.scala 348:44]
|
|
node _T_1032 = cat(_T_1031, _T_765[23]) @[el2_lib.scala 348:44]
|
|
node _T_1033 = cat(_T_1032, _T_1030) @[el2_lib.scala 348:44]
|
|
node _T_1034 = cat(_T_1033, _T_1029) @[el2_lib.scala 348:44]
|
|
node _T_1035 = cat(_T_765[27], _T_765[26]) @[el2_lib.scala 348:44]
|
|
node _T_1036 = cat(_T_765[29], _T_765[28]) @[el2_lib.scala 348:44]
|
|
node _T_1037 = cat(_T_1036, _T_1035) @[el2_lib.scala 348:44]
|
|
node _T_1038 = cat(_T_765[31], _T_765[30]) @[el2_lib.scala 348:44]
|
|
node _T_1039 = cat(_T_765[34], _T_765[33]) @[el2_lib.scala 348:44]
|
|
node _T_1040 = cat(_T_1039, _T_765[32]) @[el2_lib.scala 348:44]
|
|
node _T_1041 = cat(_T_1040, _T_1038) @[el2_lib.scala 348:44]
|
|
node _T_1042 = cat(_T_1041, _T_1037) @[el2_lib.scala 348:44]
|
|
node _T_1043 = cat(_T_1042, _T_1034) @[el2_lib.scala 348:44]
|
|
node _T_1044 = cat(_T_1043, _T_1026) @[el2_lib.scala 348:44]
|
|
node _T_1045 = xorr(_T_1044) @[el2_lib.scala 348:51]
|
|
node _T_1046 = cat(_T_766[1], _T_766[0]) @[el2_lib.scala 348:61]
|
|
node _T_1047 = cat(_T_766[3], _T_766[2]) @[el2_lib.scala 348:61]
|
|
node _T_1048 = cat(_T_1047, _T_1046) @[el2_lib.scala 348:61]
|
|
node _T_1049 = cat(_T_766[5], _T_766[4]) @[el2_lib.scala 348:61]
|
|
node _T_1050 = cat(_T_766[7], _T_766[6]) @[el2_lib.scala 348:61]
|
|
node _T_1051 = cat(_T_1050, _T_1049) @[el2_lib.scala 348:61]
|
|
node _T_1052 = cat(_T_1051, _T_1048) @[el2_lib.scala 348:61]
|
|
node _T_1053 = cat(_T_766[9], _T_766[8]) @[el2_lib.scala 348:61]
|
|
node _T_1054 = cat(_T_766[11], _T_766[10]) @[el2_lib.scala 348:61]
|
|
node _T_1055 = cat(_T_1054, _T_1053) @[el2_lib.scala 348:61]
|
|
node _T_1056 = cat(_T_766[13], _T_766[12]) @[el2_lib.scala 348:61]
|
|
node _T_1057 = cat(_T_766[16], _T_766[15]) @[el2_lib.scala 348:61]
|
|
node _T_1058 = cat(_T_1057, _T_766[14]) @[el2_lib.scala 348:61]
|
|
node _T_1059 = cat(_T_1058, _T_1056) @[el2_lib.scala 348:61]
|
|
node _T_1060 = cat(_T_1059, _T_1055) @[el2_lib.scala 348:61]
|
|
node _T_1061 = cat(_T_1060, _T_1052) @[el2_lib.scala 348:61]
|
|
node _T_1062 = cat(_T_766[18], _T_766[17]) @[el2_lib.scala 348:61]
|
|
node _T_1063 = cat(_T_766[20], _T_766[19]) @[el2_lib.scala 348:61]
|
|
node _T_1064 = cat(_T_1063, _T_1062) @[el2_lib.scala 348:61]
|
|
node _T_1065 = cat(_T_766[22], _T_766[21]) @[el2_lib.scala 348:61]
|
|
node _T_1066 = cat(_T_766[25], _T_766[24]) @[el2_lib.scala 348:61]
|
|
node _T_1067 = cat(_T_1066, _T_766[23]) @[el2_lib.scala 348:61]
|
|
node _T_1068 = cat(_T_1067, _T_1065) @[el2_lib.scala 348:61]
|
|
node _T_1069 = cat(_T_1068, _T_1064) @[el2_lib.scala 348:61]
|
|
node _T_1070 = cat(_T_766[27], _T_766[26]) @[el2_lib.scala 348:61]
|
|
node _T_1071 = cat(_T_766[29], _T_766[28]) @[el2_lib.scala 348:61]
|
|
node _T_1072 = cat(_T_1071, _T_1070) @[el2_lib.scala 348:61]
|
|
node _T_1073 = cat(_T_766[31], _T_766[30]) @[el2_lib.scala 348:61]
|
|
node _T_1074 = cat(_T_766[34], _T_766[33]) @[el2_lib.scala 348:61]
|
|
node _T_1075 = cat(_T_1074, _T_766[32]) @[el2_lib.scala 348:61]
|
|
node _T_1076 = cat(_T_1075, _T_1073) @[el2_lib.scala 348:61]
|
|
node _T_1077 = cat(_T_1076, _T_1072) @[el2_lib.scala 348:61]
|
|
node _T_1078 = cat(_T_1077, _T_1069) @[el2_lib.scala 348:61]
|
|
node _T_1079 = cat(_T_1078, _T_1061) @[el2_lib.scala 348:61]
|
|
node _T_1080 = xorr(_T_1079) @[el2_lib.scala 348:68]
|
|
node _T_1081 = cat(_T_767[2], _T_767[1]) @[el2_lib.scala 348:78]
|
|
node _T_1082 = cat(_T_1081, _T_767[0]) @[el2_lib.scala 348:78]
|
|
node _T_1083 = cat(_T_767[4], _T_767[3]) @[el2_lib.scala 348:78]
|
|
node _T_1084 = cat(_T_767[6], _T_767[5]) @[el2_lib.scala 348:78]
|
|
node _T_1085 = cat(_T_1084, _T_1083) @[el2_lib.scala 348:78]
|
|
node _T_1086 = cat(_T_1085, _T_1082) @[el2_lib.scala 348:78]
|
|
node _T_1087 = cat(_T_767[8], _T_767[7]) @[el2_lib.scala 348:78]
|
|
node _T_1088 = cat(_T_767[10], _T_767[9]) @[el2_lib.scala 348:78]
|
|
node _T_1089 = cat(_T_1088, _T_1087) @[el2_lib.scala 348:78]
|
|
node _T_1090 = cat(_T_767[12], _T_767[11]) @[el2_lib.scala 348:78]
|
|
node _T_1091 = cat(_T_767[14], _T_767[13]) @[el2_lib.scala 348:78]
|
|
node _T_1092 = cat(_T_1091, _T_1090) @[el2_lib.scala 348:78]
|
|
node _T_1093 = cat(_T_1092, _T_1089) @[el2_lib.scala 348:78]
|
|
node _T_1094 = cat(_T_1093, _T_1086) @[el2_lib.scala 348:78]
|
|
node _T_1095 = cat(_T_767[16], _T_767[15]) @[el2_lib.scala 348:78]
|
|
node _T_1096 = cat(_T_767[18], _T_767[17]) @[el2_lib.scala 348:78]
|
|
node _T_1097 = cat(_T_1096, _T_1095) @[el2_lib.scala 348:78]
|
|
node _T_1098 = cat(_T_767[20], _T_767[19]) @[el2_lib.scala 348:78]
|
|
node _T_1099 = cat(_T_767[22], _T_767[21]) @[el2_lib.scala 348:78]
|
|
node _T_1100 = cat(_T_1099, _T_1098) @[el2_lib.scala 348:78]
|
|
node _T_1101 = cat(_T_1100, _T_1097) @[el2_lib.scala 348:78]
|
|
node _T_1102 = cat(_T_767[24], _T_767[23]) @[el2_lib.scala 348:78]
|
|
node _T_1103 = cat(_T_767[26], _T_767[25]) @[el2_lib.scala 348:78]
|
|
node _T_1104 = cat(_T_1103, _T_1102) @[el2_lib.scala 348:78]
|
|
node _T_1105 = cat(_T_767[28], _T_767[27]) @[el2_lib.scala 348:78]
|
|
node _T_1106 = cat(_T_767[30], _T_767[29]) @[el2_lib.scala 348:78]
|
|
node _T_1107 = cat(_T_1106, _T_1105) @[el2_lib.scala 348:78]
|
|
node _T_1108 = cat(_T_1107, _T_1104) @[el2_lib.scala 348:78]
|
|
node _T_1109 = cat(_T_1108, _T_1101) @[el2_lib.scala 348:78]
|
|
node _T_1110 = cat(_T_1109, _T_1094) @[el2_lib.scala 348:78]
|
|
node _T_1111 = xorr(_T_1110) @[el2_lib.scala 348:85]
|
|
node _T_1112 = cat(_T_768[2], _T_768[1]) @[el2_lib.scala 348:95]
|
|
node _T_1113 = cat(_T_1112, _T_768[0]) @[el2_lib.scala 348:95]
|
|
node _T_1114 = cat(_T_768[4], _T_768[3]) @[el2_lib.scala 348:95]
|
|
node _T_1115 = cat(_T_768[6], _T_768[5]) @[el2_lib.scala 348:95]
|
|
node _T_1116 = cat(_T_1115, _T_1114) @[el2_lib.scala 348:95]
|
|
node _T_1117 = cat(_T_1116, _T_1113) @[el2_lib.scala 348:95]
|
|
node _T_1118 = cat(_T_768[8], _T_768[7]) @[el2_lib.scala 348:95]
|
|
node _T_1119 = cat(_T_768[10], _T_768[9]) @[el2_lib.scala 348:95]
|
|
node _T_1120 = cat(_T_1119, _T_1118) @[el2_lib.scala 348:95]
|
|
node _T_1121 = cat(_T_768[12], _T_768[11]) @[el2_lib.scala 348:95]
|
|
node _T_1122 = cat(_T_768[14], _T_768[13]) @[el2_lib.scala 348:95]
|
|
node _T_1123 = cat(_T_1122, _T_1121) @[el2_lib.scala 348:95]
|
|
node _T_1124 = cat(_T_1123, _T_1120) @[el2_lib.scala 348:95]
|
|
node _T_1125 = cat(_T_1124, _T_1117) @[el2_lib.scala 348:95]
|
|
node _T_1126 = cat(_T_768[16], _T_768[15]) @[el2_lib.scala 348:95]
|
|
node _T_1127 = cat(_T_768[18], _T_768[17]) @[el2_lib.scala 348:95]
|
|
node _T_1128 = cat(_T_1127, _T_1126) @[el2_lib.scala 348:95]
|
|
node _T_1129 = cat(_T_768[20], _T_768[19]) @[el2_lib.scala 348:95]
|
|
node _T_1130 = cat(_T_768[22], _T_768[21]) @[el2_lib.scala 348:95]
|
|
node _T_1131 = cat(_T_1130, _T_1129) @[el2_lib.scala 348:95]
|
|
node _T_1132 = cat(_T_1131, _T_1128) @[el2_lib.scala 348:95]
|
|
node _T_1133 = cat(_T_768[24], _T_768[23]) @[el2_lib.scala 348:95]
|
|
node _T_1134 = cat(_T_768[26], _T_768[25]) @[el2_lib.scala 348:95]
|
|
node _T_1135 = cat(_T_1134, _T_1133) @[el2_lib.scala 348:95]
|
|
node _T_1136 = cat(_T_768[28], _T_768[27]) @[el2_lib.scala 348:95]
|
|
node _T_1137 = cat(_T_768[30], _T_768[29]) @[el2_lib.scala 348:95]
|
|
node _T_1138 = cat(_T_1137, _T_1136) @[el2_lib.scala 348:95]
|
|
node _T_1139 = cat(_T_1138, _T_1135) @[el2_lib.scala 348:95]
|
|
node _T_1140 = cat(_T_1139, _T_1132) @[el2_lib.scala 348:95]
|
|
node _T_1141 = cat(_T_1140, _T_1125) @[el2_lib.scala 348:95]
|
|
node _T_1142 = xorr(_T_1141) @[el2_lib.scala 348:102]
|
|
node _T_1143 = cat(_T_769[2], _T_769[1]) @[el2_lib.scala 348:112]
|
|
node _T_1144 = cat(_T_1143, _T_769[0]) @[el2_lib.scala 348:112]
|
|
node _T_1145 = cat(_T_769[4], _T_769[3]) @[el2_lib.scala 348:112]
|
|
node _T_1146 = cat(_T_769[6], _T_769[5]) @[el2_lib.scala 348:112]
|
|
node _T_1147 = cat(_T_1146, _T_1145) @[el2_lib.scala 348:112]
|
|
node _T_1148 = cat(_T_1147, _T_1144) @[el2_lib.scala 348:112]
|
|
node _T_1149 = cat(_T_769[8], _T_769[7]) @[el2_lib.scala 348:112]
|
|
node _T_1150 = cat(_T_769[10], _T_769[9]) @[el2_lib.scala 348:112]
|
|
node _T_1151 = cat(_T_1150, _T_1149) @[el2_lib.scala 348:112]
|
|
node _T_1152 = cat(_T_769[12], _T_769[11]) @[el2_lib.scala 348:112]
|
|
node _T_1153 = cat(_T_769[14], _T_769[13]) @[el2_lib.scala 348:112]
|
|
node _T_1154 = cat(_T_1153, _T_1152) @[el2_lib.scala 348:112]
|
|
node _T_1155 = cat(_T_1154, _T_1151) @[el2_lib.scala 348:112]
|
|
node _T_1156 = cat(_T_1155, _T_1148) @[el2_lib.scala 348:112]
|
|
node _T_1157 = cat(_T_769[16], _T_769[15]) @[el2_lib.scala 348:112]
|
|
node _T_1158 = cat(_T_769[18], _T_769[17]) @[el2_lib.scala 348:112]
|
|
node _T_1159 = cat(_T_1158, _T_1157) @[el2_lib.scala 348:112]
|
|
node _T_1160 = cat(_T_769[20], _T_769[19]) @[el2_lib.scala 348:112]
|
|
node _T_1161 = cat(_T_769[22], _T_769[21]) @[el2_lib.scala 348:112]
|
|
node _T_1162 = cat(_T_1161, _T_1160) @[el2_lib.scala 348:112]
|
|
node _T_1163 = cat(_T_1162, _T_1159) @[el2_lib.scala 348:112]
|
|
node _T_1164 = cat(_T_769[24], _T_769[23]) @[el2_lib.scala 348:112]
|
|
node _T_1165 = cat(_T_769[26], _T_769[25]) @[el2_lib.scala 348:112]
|
|
node _T_1166 = cat(_T_1165, _T_1164) @[el2_lib.scala 348:112]
|
|
node _T_1167 = cat(_T_769[28], _T_769[27]) @[el2_lib.scala 348:112]
|
|
node _T_1168 = cat(_T_769[30], _T_769[29]) @[el2_lib.scala 348:112]
|
|
node _T_1169 = cat(_T_1168, _T_1167) @[el2_lib.scala 348:112]
|
|
node _T_1170 = cat(_T_1169, _T_1166) @[el2_lib.scala 348:112]
|
|
node _T_1171 = cat(_T_1170, _T_1163) @[el2_lib.scala 348:112]
|
|
node _T_1172 = cat(_T_1171, _T_1156) @[el2_lib.scala 348:112]
|
|
node _T_1173 = xorr(_T_1172) @[el2_lib.scala 348:119]
|
|
node _T_1174 = cat(_T_770[2], _T_770[1]) @[el2_lib.scala 348:129]
|
|
node _T_1175 = cat(_T_1174, _T_770[0]) @[el2_lib.scala 348:129]
|
|
node _T_1176 = cat(_T_770[4], _T_770[3]) @[el2_lib.scala 348:129]
|
|
node _T_1177 = cat(_T_770[6], _T_770[5]) @[el2_lib.scala 348:129]
|
|
node _T_1178 = cat(_T_1177, _T_1176) @[el2_lib.scala 348:129]
|
|
node _T_1179 = cat(_T_1178, _T_1175) @[el2_lib.scala 348:129]
|
|
node _T_1180 = xorr(_T_1179) @[el2_lib.scala 348:136]
|
|
node _T_1181 = cat(_T_1142, _T_1173) @[Cat.scala 29:58]
|
|
node _T_1182 = cat(_T_1181, _T_1180) @[Cat.scala 29:58]
|
|
node _T_1183 = cat(_T_1080, _T_1111) @[Cat.scala 29:58]
|
|
node _T_1184 = cat(_T_1010, _T_1045) @[Cat.scala 29:58]
|
|
node _T_1185 = cat(_T_1184, _T_1183) @[Cat.scala 29:58]
|
|
node ic_miss_buff_ecc = cat(_T_1185, _T_1182) @[Cat.scala 29:58]
|
|
wire ic_wr_16bytes_data : UInt<142>
|
|
ic_wr_16bytes_data <= UInt<1>("h00")
|
|
node _T_1186 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 391:72]
|
|
node _T_1187 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 391:72]
|
|
io.ic_wr_data[0] <= _T_1186 @[el2_ifu_mem_ctl.scala 391:17]
|
|
io.ic_wr_data[1] <= _T_1187 @[el2_ifu_mem_ctl.scala 391:17]
|
|
io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 392:23]
|
|
wire ic_rd_parity_final_err : UInt<1>
|
|
ic_rd_parity_final_err <= UInt<1>("h00")
|
|
node _T_1188 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 394:56]
|
|
node _T_1189 = and(_T_1188, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 394:83]
|
|
node _T_1190 = or(_T_1189, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 394:99]
|
|
io.ic_error_start <= _T_1190 @[el2_ifu_mem_ctl.scala 394:21]
|
|
wire ic_debug_tag_val_rd_out : UInt<1>
|
|
ic_debug_tag_val_rd_out <= UInt<1>("h00")
|
|
wire ic_debug_ict_array_sel_ff : UInt<1>
|
|
ic_debug_ict_array_sel_ff <= UInt<1>("h00")
|
|
node _T_1191 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 397:63]
|
|
node _T_1192 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 397:121]
|
|
node _T_1193 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 397:161]
|
|
node _T_1194 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
|
|
node _T_1195 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
|
|
node _T_1196 = cat(_T_1195, _T_1194) @[Cat.scala 29:58]
|
|
node _T_1197 = cat(UInt<32>("h00"), _T_1193) @[Cat.scala 29:58]
|
|
node _T_1198 = cat(UInt<2>("h00"), _T_1192) @[Cat.scala 29:58]
|
|
node _T_1199 = cat(_T_1198, _T_1197) @[Cat.scala 29:58]
|
|
node _T_1200 = cat(_T_1199, _T_1196) @[Cat.scala 29:58]
|
|
node ifu_ic_debug_rd_data_in = mux(_T_1191, _T_1200, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 397:36]
|
|
reg _T_1201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 400:37]
|
|
_T_1201 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 400:37]
|
|
io.ifu_ic_debug_rd_data <= _T_1201 @[el2_ifu_mem_ctl.scala 400:27]
|
|
node _T_1202 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 401:74]
|
|
node _T_1203 = xorr(_T_1202) @[el2_lib.scala 208:13]
|
|
node _T_1204 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 401:74]
|
|
node _T_1205 = xorr(_T_1204) @[el2_lib.scala 208:13]
|
|
node _T_1206 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 401:74]
|
|
node _T_1207 = xorr(_T_1206) @[el2_lib.scala 208:13]
|
|
node _T_1208 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 401:74]
|
|
node _T_1209 = xorr(_T_1208) @[el2_lib.scala 208:13]
|
|
node _T_1210 = cat(_T_1209, _T_1207) @[Cat.scala 29:58]
|
|
node _T_1211 = cat(_T_1210, _T_1205) @[Cat.scala 29:58]
|
|
node ic_wr_parity = cat(_T_1211, _T_1203) @[Cat.scala 29:58]
|
|
node _T_1212 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 402:82]
|
|
node _T_1213 = xorr(_T_1212) @[el2_lib.scala 208:13]
|
|
node _T_1214 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 402:82]
|
|
node _T_1215 = xorr(_T_1214) @[el2_lib.scala 208:13]
|
|
node _T_1216 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 402:82]
|
|
node _T_1217 = xorr(_T_1216) @[el2_lib.scala 208:13]
|
|
node _T_1218 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 402:82]
|
|
node _T_1219 = xorr(_T_1218) @[el2_lib.scala 208:13]
|
|
node _T_1220 = cat(_T_1219, _T_1217) @[Cat.scala 29:58]
|
|
node _T_1221 = cat(_T_1220, _T_1215) @[Cat.scala 29:58]
|
|
node ic_miss_buff_parity = cat(_T_1221, _T_1213) @[Cat.scala 29:58]
|
|
node _T_1222 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 404:43]
|
|
node _T_1223 = bits(_T_1222, 0, 0) @[el2_ifu_mem_ctl.scala 404:47]
|
|
node _T_1224 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 404:117]
|
|
node _T_1225 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 404:201]
|
|
node _T_1226 = cat(ic_miss_buff_ecc, _T_1225) @[Cat.scala 29:58]
|
|
node _T_1227 = cat(ic_wr_ecc, _T_1224) @[Cat.scala 29:58]
|
|
node _T_1228 = cat(_T_1227, _T_1226) @[Cat.scala 29:58]
|
|
node _T_1229 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1230 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1231 = cat(_T_1230, _T_1229) @[Cat.scala 29:58]
|
|
node _T_1232 = mux(_T_1223, _T_1228, _T_1231) @[el2_ifu_mem_ctl.scala 404:28]
|
|
ic_wr_16bytes_data <= _T_1232 @[el2_ifu_mem_ctl.scala 404:22]
|
|
wire bus_ifu_wr_data_error_ff : UInt<1>
|
|
bus_ifu_wr_data_error_ff <= UInt<1>("h00")
|
|
wire ifu_wr_data_comb_err_ff : UInt<1>
|
|
ifu_wr_data_comb_err_ff <= UInt<1>("h00")
|
|
wire reset_beat_cnt : UInt<1>
|
|
reset_beat_cnt <= UInt<1>("h00")
|
|
node _T_1233 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 410:53]
|
|
node _T_1234 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:82]
|
|
node ifu_wr_cumulative_err = and(_T_1233, _T_1234) @[el2_ifu_mem_ctl.scala 410:80]
|
|
node _T_1235 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 411:55]
|
|
ifu_wr_cumulative_err_data <= _T_1235 @[el2_ifu_mem_ctl.scala 411:30]
|
|
reg _T_1236 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 412:61]
|
|
_T_1236 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 412:61]
|
|
ifu_wr_data_comb_err_ff <= _T_1236 @[el2_ifu_mem_ctl.scala 412:27]
|
|
wire ic_crit_wd_rdy : UInt<1>
|
|
ic_crit_wd_rdy <= UInt<1>("h00")
|
|
wire ifu_byp_data_err_new : UInt<1>
|
|
ifu_byp_data_err_new <= UInt<1>("h00")
|
|
node _T_1237 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 415:51]
|
|
node _T_1238 = or(ic_crit_wd_rdy, _T_1237) @[el2_ifu_mem_ctl.scala 415:38]
|
|
node _T_1239 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 415:77]
|
|
node _T_1240 = or(_T_1238, _T_1239) @[el2_ifu_mem_ctl.scala 415:64]
|
|
node _T_1241 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 415:98]
|
|
node sel_byp_data = and(_T_1240, _T_1241) @[el2_ifu_mem_ctl.scala 415:96]
|
|
node _T_1242 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 416:51]
|
|
node _T_1243 = or(ic_crit_wd_rdy, _T_1242) @[el2_ifu_mem_ctl.scala 416:38]
|
|
node _T_1244 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 416:77]
|
|
node _T_1245 = or(_T_1243, _T_1244) @[el2_ifu_mem_ctl.scala 416:64]
|
|
node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:21]
|
|
node _T_1247 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:98]
|
|
node sel_ic_data = and(_T_1246, _T_1247) @[el2_ifu_mem_ctl.scala 416:96]
|
|
wire ic_byp_data_only_new : UInt<80>
|
|
ic_byp_data_only_new <= UInt<1>("h00")
|
|
node _T_1248 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 420:81]
|
|
node _T_1249 = or(sel_byp_data, _T_1248) @[el2_ifu_mem_ctl.scala 420:47]
|
|
node _T_1250 = bits(_T_1249, 0, 0) @[el2_ifu_mem_ctl.scala 420:140]
|
|
node _T_1251 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1252 = mux(_T_1251, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1253 = and(_T_1252, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 422:64]
|
|
node _T_1254 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1255 = mux(_T_1254, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1256 = and(_T_1255, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 422:109]
|
|
node ic_premux_data = or(_T_1253, _T_1256) @[el2_ifu_mem_ctl.scala 422:83]
|
|
node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 424:58]
|
|
node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 426:42]
|
|
node _T_1257 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 428:40]
|
|
node fetch_req_f_qual = and(io.ic_hit_f, _T_1257) @[el2_ifu_mem_ctl.scala 428:38]
|
|
wire ifc_region_acc_fault_memory_f : UInt<1>
|
|
ifc_region_acc_fault_memory_f <= UInt<1>("h00")
|
|
node _T_1258 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 430:57]
|
|
node _T_1259 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 430:82]
|
|
node _T_1260 = and(_T_1258, _T_1259) @[el2_ifu_mem_ctl.scala 430:80]
|
|
io.ic_access_fault_f <= _T_1260 @[el2_ifu_mem_ctl.scala 430:24]
|
|
node _T_1261 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 431:62]
|
|
node _T_1262 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 432:32]
|
|
node _T_1263 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 433:47]
|
|
node _T_1264 = mux(_T_1263, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 433:10]
|
|
node _T_1265 = mux(_T_1262, UInt<2>("h02"), _T_1264) @[el2_ifu_mem_ctl.scala 432:8]
|
|
node _T_1266 = mux(_T_1261, UInt<1>("h01"), _T_1265) @[el2_ifu_mem_ctl.scala 431:35]
|
|
io.ic_access_fault_type_f <= _T_1266 @[el2_ifu_mem_ctl.scala 431:29]
|
|
wire ifu_bp_inst_mask_f : UInt<1>
|
|
ifu_bp_inst_mask_f <= UInt<1>("h00")
|
|
node _T_1267 = and(fetch_req_f_qual, ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 435:45]
|
|
node _T_1268 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1269 = eq(ifu_fetch_addr_int_f, _T_1268) @[el2_ifu_mem_ctl.scala 435:77]
|
|
node _T_1270 = eq(_T_1269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:68]
|
|
node _T_1271 = and(_T_1267, _T_1270) @[el2_ifu_mem_ctl.scala 435:66]
|
|
node _T_1272 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 435:128]
|
|
node _T_1273 = and(_T_1271, _T_1272) @[el2_ifu_mem_ctl.scala 435:111]
|
|
node _T_1274 = cat(_T_1273, fetch_req_f_qual) @[Cat.scala 29:58]
|
|
io.ic_fetch_val_f <= _T_1274 @[el2_ifu_mem_ctl.scala 435:21]
|
|
node _T_1275 = bits(io.ic_rd_data, 1, 0) @[el2_ifu_mem_ctl.scala 436:33]
|
|
node two_byte_instr = neq(_T_1275, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:39]
|
|
wire ic_miss_buff_data_in : UInt<64>
|
|
ic_miss_buff_data_in <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_tag : UInt<3>
|
|
ifu_bus_rsp_tag <= UInt<1>("h00")
|
|
wire bus_ifu_wr_en : UInt<1>
|
|
bus_ifu_wr_en <= UInt<1>("h00")
|
|
node _T_1276 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_0 = and(bus_ifu_wr_en, _T_1276) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1277 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_1 = and(bus_ifu_wr_en, _T_1277) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1278 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_2 = and(bus_ifu_wr_en, _T_1278) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1279 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_3 = and(bus_ifu_wr_en, _T_1279) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1280 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_4 = and(bus_ifu_wr_en, _T_1280) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1281 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_5 = and(bus_ifu_wr_en, _T_1281) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1282 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_6 = and(bus_ifu_wr_en, _T_1282) @[el2_ifu_mem_ctl.scala 442:73]
|
|
node _T_1283 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:91]
|
|
node write_fill_data_7 = and(bus_ifu_wr_en, _T_1283) @[el2_ifu_mem_ctl.scala 442:73]
|
|
wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 443:31]
|
|
node _T_1284 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1285 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1284 : @[Reg.scala 28:19]
|
|
_T_1285 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[0] <= _T_1285 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1286 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1287 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1286 : @[Reg.scala 28:19]
|
|
_T_1287 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[1] <= _T_1287 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1288 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1289 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1288 : @[Reg.scala 28:19]
|
|
_T_1289 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[2] <= _T_1289 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1290 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1291 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1290 : @[Reg.scala 28:19]
|
|
_T_1291 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[3] <= _T_1291 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1292 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1292 : @[Reg.scala 28:19]
|
|
_T_1293 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[4] <= _T_1293 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1294 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1294 : @[Reg.scala 28:19]
|
|
_T_1295 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[5] <= _T_1295 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1296 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1296 : @[Reg.scala 28:19]
|
|
_T_1297 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[6] <= _T_1297 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1298 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1299 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1298 : @[Reg.scala 28:19]
|
|
_T_1299 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[7] <= _T_1299 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1300 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1300 : @[Reg.scala 28:19]
|
|
_T_1301 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[8] <= _T_1301 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1302 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1302 : @[Reg.scala 28:19]
|
|
_T_1303 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[9] <= _T_1303 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1304 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1305 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1304 : @[Reg.scala 28:19]
|
|
_T_1305 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[10] <= _T_1305 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1306 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1307 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1306 : @[Reg.scala 28:19]
|
|
_T_1307 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[11] <= _T_1307 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1308 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1308 : @[Reg.scala 28:19]
|
|
_T_1309 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[12] <= _T_1309 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1310 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1310 : @[Reg.scala 28:19]
|
|
_T_1311 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[13] <= _T_1311 @[el2_ifu_mem_ctl.scala 446:28]
|
|
node _T_1312 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 445:91]
|
|
reg _T_1313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1312 : @[Reg.scala 28:19]
|
|
_T_1313 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[14] <= _T_1313 @[el2_ifu_mem_ctl.scala 445:26]
|
|
node _T_1314 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 446:93]
|
|
reg _T_1315 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1314 : @[Reg.scala 28:19]
|
|
_T_1315 <= ic_miss_buff_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[15] <= _T_1315 @[el2_ifu_mem_ctl.scala 446:28]
|
|
wire ic_miss_buff_data_valid : UInt<8>
|
|
ic_miss_buff_data_valid <= UInt<1>("h00")
|
|
node _T_1316 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 448:113]
|
|
node _T_1317 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
|
|
node _T_1318 = and(_T_1316, _T_1317) @[el2_ifu_mem_ctl.scala 448:116]
|
|
node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1318) @[el2_ifu_mem_ctl.scala 448:88]
|
|
node _T_1319 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 448:113]
|
|
node _T_1320 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
|
|
node _T_1321 = and(_T_1319, _T_1320) @[el2_ifu_mem_ctl.scala 448:116]
|
|
node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1321) @[el2_ifu_mem_ctl.scala 448:88]
|
|
node _T_1322 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 448:113]
|
|
node _T_1323 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
|
|
node _T_1324 = and(_T_1322, _T_1323) @[el2_ifu_mem_ctl.scala 448:116]
|
|
node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1324) @[el2_ifu_mem_ctl.scala 448:88]
|
|
node _T_1325 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 448:113]
|
|
node _T_1326 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
|
|
node _T_1327 = and(_T_1325, _T_1326) @[el2_ifu_mem_ctl.scala 448:116]
|
|
node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1327) @[el2_ifu_mem_ctl.scala 448:88]
|
|
node _T_1328 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 448:113]
|
|
node _T_1329 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
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node _T_1330 = and(_T_1328, _T_1329) @[el2_ifu_mem_ctl.scala 448:116]
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node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1330) @[el2_ifu_mem_ctl.scala 448:88]
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node _T_1331 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 448:113]
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node _T_1332 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
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node _T_1333 = and(_T_1331, _T_1332) @[el2_ifu_mem_ctl.scala 448:116]
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node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1333) @[el2_ifu_mem_ctl.scala 448:88]
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node _T_1334 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 448:113]
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node _T_1335 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
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node _T_1336 = and(_T_1334, _T_1335) @[el2_ifu_mem_ctl.scala 448:116]
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node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1336) @[el2_ifu_mem_ctl.scala 448:88]
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node _T_1337 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 448:113]
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node _T_1338 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 448:118]
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node _T_1339 = and(_T_1337, _T_1338) @[el2_ifu_mem_ctl.scala 448:116]
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node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1339) @[el2_ifu_mem_ctl.scala 448:88]
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node _T_1340 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58]
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node _T_1341 = cat(_T_1340, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58]
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node _T_1342 = cat(_T_1341, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58]
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node _T_1343 = cat(_T_1342, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58]
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node _T_1344 = cat(_T_1343, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58]
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node _T_1345 = cat(_T_1344, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58]
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node _T_1346 = cat(_T_1345, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58]
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reg _T_1347 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 449:60]
|
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_T_1347 <= _T_1346 @[el2_ifu_mem_ctl.scala 449:60]
|
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ic_miss_buff_data_valid <= _T_1347 @[el2_ifu_mem_ctl.scala 449:27]
|
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wire bus_ifu_wr_data_error : UInt<1>
|
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bus_ifu_wr_data_error <= UInt<1>("h00")
|
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wire ic_miss_buff_data_error : UInt<8>
|
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ic_miss_buff_data_error <= UInt<1>("h00")
|
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node _T_1348 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
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node _T_1349 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 453:28]
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node _T_1350 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
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node _T_1351 = and(_T_1349, _T_1350) @[el2_ifu_mem_ctl.scala 453:32]
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node ic_miss_buff_data_error_in_0 = mux(_T_1348, bus_ifu_wr_data_error, _T_1351) @[el2_ifu_mem_ctl.scala 452:72]
|
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node _T_1352 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
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node _T_1353 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 453:28]
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node _T_1354 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
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node _T_1355 = and(_T_1353, _T_1354) @[el2_ifu_mem_ctl.scala 453:32]
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node ic_miss_buff_data_error_in_1 = mux(_T_1352, bus_ifu_wr_data_error, _T_1355) @[el2_ifu_mem_ctl.scala 452:72]
|
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node _T_1356 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
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node _T_1357 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 453:28]
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node _T_1358 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
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node _T_1359 = and(_T_1357, _T_1358) @[el2_ifu_mem_ctl.scala 453:32]
|
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node ic_miss_buff_data_error_in_2 = mux(_T_1356, bus_ifu_wr_data_error, _T_1359) @[el2_ifu_mem_ctl.scala 452:72]
|
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node _T_1360 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
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node _T_1361 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 453:28]
|
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node _T_1362 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
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node _T_1363 = and(_T_1361, _T_1362) @[el2_ifu_mem_ctl.scala 453:32]
|
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node ic_miss_buff_data_error_in_3 = mux(_T_1360, bus_ifu_wr_data_error, _T_1363) @[el2_ifu_mem_ctl.scala 452:72]
|
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node _T_1364 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
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node _T_1365 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 453:28]
|
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node _T_1366 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
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node _T_1367 = and(_T_1365, _T_1366) @[el2_ifu_mem_ctl.scala 453:32]
|
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node ic_miss_buff_data_error_in_4 = mux(_T_1364, bus_ifu_wr_data_error, _T_1367) @[el2_ifu_mem_ctl.scala 452:72]
|
|
node _T_1368 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
|
node _T_1369 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 453:28]
|
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node _T_1370 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
|
node _T_1371 = and(_T_1369, _T_1370) @[el2_ifu_mem_ctl.scala 453:32]
|
|
node ic_miss_buff_data_error_in_5 = mux(_T_1368, bus_ifu_wr_data_error, _T_1371) @[el2_ifu_mem_ctl.scala 452:72]
|
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node _T_1372 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
|
node _T_1373 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 453:28]
|
|
node _T_1374 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
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node _T_1375 = and(_T_1373, _T_1374) @[el2_ifu_mem_ctl.scala 453:32]
|
|
node ic_miss_buff_data_error_in_6 = mux(_T_1372, bus_ifu_wr_data_error, _T_1375) @[el2_ifu_mem_ctl.scala 452:72]
|
|
node _T_1376 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 452:92]
|
|
node _T_1377 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 453:28]
|
|
node _T_1378 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:34]
|
|
node _T_1379 = and(_T_1377, _T_1378) @[el2_ifu_mem_ctl.scala 453:32]
|
|
node ic_miss_buff_data_error_in_7 = mux(_T_1376, bus_ifu_wr_data_error, _T_1379) @[el2_ifu_mem_ctl.scala 452:72]
|
|
node _T_1380 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58]
|
|
node _T_1381 = cat(_T_1380, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58]
|
|
node _T_1382 = cat(_T_1381, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58]
|
|
node _T_1383 = cat(_T_1382, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58]
|
|
node _T_1384 = cat(_T_1383, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58]
|
|
node _T_1385 = cat(_T_1384, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58]
|
|
node _T_1386 = cat(_T_1385, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58]
|
|
reg _T_1387 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 454:60]
|
|
_T_1387 <= _T_1386 @[el2_ifu_mem_ctl.scala 454:60]
|
|
ic_miss_buff_data_error <= _T_1387 @[el2_ifu_mem_ctl.scala 454:27]
|
|
node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 457:28]
|
|
node _T_1388 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 458:42]
|
|
node _T_1389 = add(_T_1388, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 458:70]
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node bypass_index_5_3_inc = tail(_T_1389, 1) @[el2_ifu_mem_ctl.scala 458:70]
|
|
node _T_1390 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1392 = bits(_T_1391, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1393 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1394 = eq(_T_1393, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1395 = bits(_T_1394, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1396 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1397 = eq(_T_1396, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1398 = bits(_T_1397, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1399 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1400 = eq(_T_1399, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1401 = bits(_T_1400, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1402 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1403 = eq(_T_1402, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1404 = bits(_T_1403, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1405 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1406 = eq(_T_1405, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1407 = bits(_T_1406, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1408 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1409 = eq(_T_1408, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1410 = bits(_T_1409, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1411 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 459:87]
|
|
node _T_1412 = eq(_T_1411, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 459:114]
|
|
node _T_1413 = bits(_T_1412, 0, 0) @[el2_ifu_mem_ctl.scala 459:122]
|
|
node _T_1414 = mux(_T_1392, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1415 = mux(_T_1395, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1416 = mux(_T_1398, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1417 = mux(_T_1401, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1418 = mux(_T_1404, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1419 = mux(_T_1407, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1420 = mux(_T_1410, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1421 = mux(_T_1413, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1422 = or(_T_1414, _T_1415) @[Mux.scala 27:72]
|
|
node _T_1423 = or(_T_1422, _T_1416) @[Mux.scala 27:72]
|
|
node _T_1424 = or(_T_1423, _T_1417) @[Mux.scala 27:72]
|
|
node _T_1425 = or(_T_1424, _T_1418) @[Mux.scala 27:72]
|
|
node _T_1426 = or(_T_1425, _T_1419) @[Mux.scala 27:72]
|
|
node _T_1427 = or(_T_1426, _T_1420) @[Mux.scala 27:72]
|
|
node _T_1428 = or(_T_1427, _T_1421) @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72]
|
|
bypass_valid_value_check <= _T_1428 @[Mux.scala 27:72]
|
|
node _T_1429 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 460:71]
|
|
node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:58]
|
|
node _T_1431 = and(bypass_valid_value_check, _T_1430) @[el2_ifu_mem_ctl.scala 460:56]
|
|
node _T_1432 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 460:90]
|
|
node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:77]
|
|
node _T_1434 = and(_T_1431, _T_1433) @[el2_ifu_mem_ctl.scala 460:75]
|
|
node _T_1435 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 461:71]
|
|
node _T_1436 = eq(_T_1435, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 461:58]
|
|
node _T_1437 = and(bypass_valid_value_check, _T_1436) @[el2_ifu_mem_ctl.scala 461:56]
|
|
node _T_1438 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 461:89]
|
|
node _T_1439 = and(_T_1437, _T_1438) @[el2_ifu_mem_ctl.scala 461:75]
|
|
node _T_1440 = or(_T_1434, _T_1439) @[el2_ifu_mem_ctl.scala 460:95]
|
|
node _T_1441 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 462:70]
|
|
node _T_1442 = and(bypass_valid_value_check, _T_1441) @[el2_ifu_mem_ctl.scala 462:56]
|
|
node _T_1443 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 462:89]
|
|
node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 462:76]
|
|
node _T_1445 = and(_T_1442, _T_1444) @[el2_ifu_mem_ctl.scala 462:74]
|
|
node _T_1446 = or(_T_1440, _T_1445) @[el2_ifu_mem_ctl.scala 461:94]
|
|
node _T_1447 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 463:47]
|
|
node _T_1448 = and(bypass_valid_value_check, _T_1447) @[el2_ifu_mem_ctl.scala 463:33]
|
|
node _T_1449 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 463:65]
|
|
node _T_1450 = and(_T_1448, _T_1449) @[el2_ifu_mem_ctl.scala 463:51]
|
|
node _T_1451 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1452 = bits(_T_1451, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1453 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1454 = bits(_T_1453, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1455 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1456 = bits(_T_1455, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1457 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1458 = bits(_T_1457, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1459 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1460 = bits(_T_1459, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1461 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1462 = bits(_T_1461, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1463 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1464 = bits(_T_1463, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1465 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 463:132]
|
|
node _T_1466 = bits(_T_1465, 0, 0) @[el2_ifu_mem_ctl.scala 463:140]
|
|
node _T_1467 = mux(_T_1452, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1468 = mux(_T_1454, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1469 = mux(_T_1456, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1470 = mux(_T_1458, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1471 = mux(_T_1460, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1472 = mux(_T_1462, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1473 = mux(_T_1464, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1474 = mux(_T_1466, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1475 = or(_T_1467, _T_1468) @[Mux.scala 27:72]
|
|
node _T_1476 = or(_T_1475, _T_1469) @[Mux.scala 27:72]
|
|
node _T_1477 = or(_T_1476, _T_1470) @[Mux.scala 27:72]
|
|
node _T_1478 = or(_T_1477, _T_1471) @[Mux.scala 27:72]
|
|
node _T_1479 = or(_T_1478, _T_1472) @[Mux.scala 27:72]
|
|
node _T_1480 = or(_T_1479, _T_1473) @[Mux.scala 27:72]
|
|
node _T_1481 = or(_T_1480, _T_1474) @[Mux.scala 27:72]
|
|
wire _T_1482 : UInt<1> @[Mux.scala 27:72]
|
|
_T_1482 <= _T_1481 @[Mux.scala 27:72]
|
|
node _T_1483 = and(_T_1450, _T_1482) @[el2_ifu_mem_ctl.scala 463:69]
|
|
node _T_1484 = or(_T_1446, _T_1483) @[el2_ifu_mem_ctl.scala 462:94]
|
|
node _T_1485 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 464:70]
|
|
node _T_1486 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1487 = eq(_T_1485, _T_1486) @[el2_ifu_mem_ctl.scala 464:95]
|
|
node _T_1488 = and(bypass_valid_value_check, _T_1487) @[el2_ifu_mem_ctl.scala 464:56]
|
|
node bypass_data_ready_in = or(_T_1484, _T_1488) @[el2_ifu_mem_ctl.scala 463:181]
|
|
wire ic_crit_wd_rdy_new_ff : UInt<1>
|
|
ic_crit_wd_rdy_new_ff <= UInt<1>("h00")
|
|
node _T_1489 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 468:53]
|
|
node _T_1490 = and(_T_1489, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 468:73]
|
|
node _T_1491 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 468:98]
|
|
node _T_1492 = and(_T_1490, _T_1491) @[el2_ifu_mem_ctl.scala 468:96]
|
|
node _T_1493 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 468:120]
|
|
node _T_1494 = and(_T_1492, _T_1493) @[el2_ifu_mem_ctl.scala 468:118]
|
|
node _T_1495 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:75]
|
|
node _T_1496 = and(crit_wd_byp_ok_ff, _T_1495) @[el2_ifu_mem_ctl.scala 469:73]
|
|
node _T_1497 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:98]
|
|
node _T_1498 = and(_T_1496, _T_1497) @[el2_ifu_mem_ctl.scala 469:96]
|
|
node _T_1499 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 469:120]
|
|
node _T_1500 = and(_T_1498, _T_1499) @[el2_ifu_mem_ctl.scala 469:118]
|
|
node _T_1501 = or(_T_1494, _T_1500) @[el2_ifu_mem_ctl.scala 468:143]
|
|
node _T_1502 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 470:54]
|
|
node _T_1503 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:76]
|
|
node _T_1504 = and(_T_1502, _T_1503) @[el2_ifu_mem_ctl.scala 470:74]
|
|
node _T_1505 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:98]
|
|
node _T_1506 = and(_T_1504, _T_1505) @[el2_ifu_mem_ctl.scala 470:96]
|
|
node ic_crit_wd_rdy_new_in = or(_T_1501, _T_1506) @[el2_ifu_mem_ctl.scala 469:143]
|
|
reg _T_1507 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 471:58]
|
|
_T_1507 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 471:58]
|
|
ic_crit_wd_rdy_new_ff <= _T_1507 @[el2_ifu_mem_ctl.scala 471:25]
|
|
node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 472:45]
|
|
node _T_1508 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 473:51]
|
|
node byp_fetch_index_0 = cat(_T_1508, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_1509 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 474:51]
|
|
node byp_fetch_index_1 = cat(_T_1509, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1510 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 475:49]
|
|
node _T_1511 = add(_T_1510, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 475:75]
|
|
node byp_fetch_index_inc = tail(_T_1511, 1) @[el2_ifu_mem_ctl.scala 475:75]
|
|
node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1512 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1514 = bits(_T_1513, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1515 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1516 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1517 = eq(_T_1516, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1518 = bits(_T_1517, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1519 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1520 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1521 = eq(_T_1520, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1522 = bits(_T_1521, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1523 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1524 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1525 = eq(_T_1524, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1526 = bits(_T_1525, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1527 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1528 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1529 = eq(_T_1528, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1530 = bits(_T_1529, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1531 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1532 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1533 = eq(_T_1532, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1534 = bits(_T_1533, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1535 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1536 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1537 = eq(_T_1536, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1538 = bits(_T_1537, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1539 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1540 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 478:93]
|
|
node _T_1541 = eq(_T_1540, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 478:118]
|
|
node _T_1542 = bits(_T_1541, 0, 0) @[el2_ifu_mem_ctl.scala 478:126]
|
|
node _T_1543 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 478:157]
|
|
node _T_1544 = mux(_T_1514, _T_1515, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1545 = mux(_T_1518, _T_1519, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1546 = mux(_T_1522, _T_1523, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1547 = mux(_T_1526, _T_1527, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1548 = mux(_T_1530, _T_1531, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1549 = mux(_T_1534, _T_1535, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1550 = mux(_T_1538, _T_1539, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1551 = mux(_T_1542, _T_1543, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1552 = or(_T_1544, _T_1545) @[Mux.scala 27:72]
|
|
node _T_1553 = or(_T_1552, _T_1546) @[Mux.scala 27:72]
|
|
node _T_1554 = or(_T_1553, _T_1547) @[Mux.scala 27:72]
|
|
node _T_1555 = or(_T_1554, _T_1548) @[Mux.scala 27:72]
|
|
node _T_1556 = or(_T_1555, _T_1549) @[Mux.scala 27:72]
|
|
node _T_1557 = or(_T_1556, _T_1550) @[Mux.scala 27:72]
|
|
node _T_1558 = or(_T_1557, _T_1551) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass <= _T_1558 @[Mux.scala 27:72]
|
|
node _T_1559 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1560 = bits(_T_1559, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1561 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1562 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1563 = bits(_T_1562, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1564 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1565 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1566 = bits(_T_1565, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1567 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1568 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1569 = bits(_T_1568, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1570 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1571 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1572 = bits(_T_1571, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1573 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1574 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1575 = bits(_T_1574, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1576 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1577 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1578 = bits(_T_1577, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1579 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1580 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 479:104]
|
|
node _T_1581 = bits(_T_1580, 0, 0) @[el2_ifu_mem_ctl.scala 479:112]
|
|
node _T_1582 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 479:143]
|
|
node _T_1583 = mux(_T_1560, _T_1561, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1584 = mux(_T_1563, _T_1564, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1585 = mux(_T_1566, _T_1567, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1586 = mux(_T_1569, _T_1570, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1587 = mux(_T_1572, _T_1573, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1588 = mux(_T_1575, _T_1576, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1589 = mux(_T_1578, _T_1579, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1590 = mux(_T_1581, _T_1582, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1591 = or(_T_1583, _T_1584) @[Mux.scala 27:72]
|
|
node _T_1592 = or(_T_1591, _T_1585) @[Mux.scala 27:72]
|
|
node _T_1593 = or(_T_1592, _T_1586) @[Mux.scala 27:72]
|
|
node _T_1594 = or(_T_1593, _T_1587) @[Mux.scala 27:72]
|
|
node _T_1595 = or(_T_1594, _T_1588) @[Mux.scala 27:72]
|
|
node _T_1596 = or(_T_1595, _T_1589) @[Mux.scala 27:72]
|
|
node _T_1597 = or(_T_1596, _T_1590) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass_inc <= _T_1597 @[Mux.scala 27:72]
|
|
node _T_1598 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 482:28]
|
|
node _T_1599 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 482:52]
|
|
node _T_1600 = and(_T_1598, _T_1599) @[el2_ifu_mem_ctl.scala 482:31]
|
|
when _T_1600 : @[el2_ifu_mem_ctl.scala 482:56]
|
|
ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 483:26]
|
|
skip @[el2_ifu_mem_ctl.scala 482:56]
|
|
else : @[el2_ifu_mem_ctl.scala 484:5]
|
|
node _T_1601 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 484:70]
|
|
ifu_byp_data_err_new <= _T_1601 @[el2_ifu_mem_ctl.scala 484:36]
|
|
skip @[el2_ifu_mem_ctl.scala 484:5]
|
|
node _T_1602 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 486:59]
|
|
node _T_1603 = bits(_T_1602, 0, 0) @[el2_ifu_mem_ctl.scala 486:63]
|
|
node _T_1604 = eq(_T_1603, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 486:38]
|
|
node _T_1605 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1606 = bits(_T_1605, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1607 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1608 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1609 = bits(_T_1608, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1610 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1611 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1612 = bits(_T_1611, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1613 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1614 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1615 = bits(_T_1614, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1616 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1617 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1618 = bits(_T_1617, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1619 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1620 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1621 = bits(_T_1620, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1622 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1623 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1624 = bits(_T_1623, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1625 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1626 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1627 = bits(_T_1626, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1628 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1629 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1630 = bits(_T_1629, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1631 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1632 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1633 = bits(_T_1632, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1634 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1635 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1636 = bits(_T_1635, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1637 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1638 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1639 = bits(_T_1638, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1640 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1641 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1642 = bits(_T_1641, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1643 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1644 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1645 = bits(_T_1644, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1646 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1647 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1648 = bits(_T_1647, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1649 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1650 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:73]
|
|
node _T_1651 = bits(_T_1650, 0, 0) @[el2_ifu_mem_ctl.scala 487:81]
|
|
node _T_1652 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 487:109]
|
|
node _T_1653 = mux(_T_1606, _T_1607, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1654 = mux(_T_1609, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1655 = mux(_T_1612, _T_1613, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1656 = mux(_T_1615, _T_1616, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1657 = mux(_T_1618, _T_1619, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1658 = mux(_T_1621, _T_1622, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1659 = mux(_T_1624, _T_1625, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1660 = mux(_T_1627, _T_1628, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1661 = mux(_T_1630, _T_1631, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1662 = mux(_T_1633, _T_1634, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1663 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1664 = mux(_T_1639, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1665 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1666 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1667 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1668 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1669 = or(_T_1653, _T_1654) @[Mux.scala 27:72]
|
|
node _T_1670 = or(_T_1669, _T_1655) @[Mux.scala 27:72]
|
|
node _T_1671 = or(_T_1670, _T_1656) @[Mux.scala 27:72]
|
|
node _T_1672 = or(_T_1671, _T_1657) @[Mux.scala 27:72]
|
|
node _T_1673 = or(_T_1672, _T_1658) @[Mux.scala 27:72]
|
|
node _T_1674 = or(_T_1673, _T_1659) @[Mux.scala 27:72]
|
|
node _T_1675 = or(_T_1674, _T_1660) @[Mux.scala 27:72]
|
|
node _T_1676 = or(_T_1675, _T_1661) @[Mux.scala 27:72]
|
|
node _T_1677 = or(_T_1676, _T_1662) @[Mux.scala 27:72]
|
|
node _T_1678 = or(_T_1677, _T_1663) @[Mux.scala 27:72]
|
|
node _T_1679 = or(_T_1678, _T_1664) @[Mux.scala 27:72]
|
|
node _T_1680 = or(_T_1679, _T_1665) @[Mux.scala 27:72]
|
|
node _T_1681 = or(_T_1680, _T_1666) @[Mux.scala 27:72]
|
|
node _T_1682 = or(_T_1681, _T_1667) @[Mux.scala 27:72]
|
|
node _T_1683 = or(_T_1682, _T_1668) @[Mux.scala 27:72]
|
|
wire _T_1684 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1684 <= _T_1683 @[Mux.scala 27:72]
|
|
node _T_1685 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1686 = bits(_T_1685, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1687 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1688 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1689 = bits(_T_1688, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1690 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1691 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1692 = bits(_T_1691, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1693 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1694 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1695 = bits(_T_1694, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1696 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1697 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1698 = bits(_T_1697, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1699 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1700 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1701 = bits(_T_1700, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1702 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1703 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1704 = bits(_T_1703, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1705 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1706 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1707 = bits(_T_1706, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1708 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1709 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1710 = bits(_T_1709, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1711 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1712 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1713 = bits(_T_1712, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1714 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1715 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1716 = bits(_T_1715, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1717 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1718 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1719 = bits(_T_1718, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1720 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1721 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1722 = bits(_T_1721, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1723 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1724 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1725 = bits(_T_1724, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1726 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1727 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1728 = bits(_T_1727, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1729 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1730 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:179]
|
|
node _T_1731 = bits(_T_1730, 0, 0) @[el2_ifu_mem_ctl.scala 487:187]
|
|
node _T_1732 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 487:215]
|
|
node _T_1733 = mux(_T_1686, _T_1687, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1734 = mux(_T_1689, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1735 = mux(_T_1692, _T_1693, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1736 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1737 = mux(_T_1698, _T_1699, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1738 = mux(_T_1701, _T_1702, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1739 = mux(_T_1704, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1740 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1741 = mux(_T_1710, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1742 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1743 = mux(_T_1716, _T_1717, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1744 = mux(_T_1719, _T_1720, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1745 = mux(_T_1722, _T_1723, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1746 = mux(_T_1725, _T_1726, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1747 = mux(_T_1728, _T_1729, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1748 = mux(_T_1731, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1749 = or(_T_1733, _T_1734) @[Mux.scala 27:72]
|
|
node _T_1750 = or(_T_1749, _T_1735) @[Mux.scala 27:72]
|
|
node _T_1751 = or(_T_1750, _T_1736) @[Mux.scala 27:72]
|
|
node _T_1752 = or(_T_1751, _T_1737) @[Mux.scala 27:72]
|
|
node _T_1753 = or(_T_1752, _T_1738) @[Mux.scala 27:72]
|
|
node _T_1754 = or(_T_1753, _T_1739) @[Mux.scala 27:72]
|
|
node _T_1755 = or(_T_1754, _T_1740) @[Mux.scala 27:72]
|
|
node _T_1756 = or(_T_1755, _T_1741) @[Mux.scala 27:72]
|
|
node _T_1757 = or(_T_1756, _T_1742) @[Mux.scala 27:72]
|
|
node _T_1758 = or(_T_1757, _T_1743) @[Mux.scala 27:72]
|
|
node _T_1759 = or(_T_1758, _T_1744) @[Mux.scala 27:72]
|
|
node _T_1760 = or(_T_1759, _T_1745) @[Mux.scala 27:72]
|
|
node _T_1761 = or(_T_1760, _T_1746) @[Mux.scala 27:72]
|
|
node _T_1762 = or(_T_1761, _T_1747) @[Mux.scala 27:72]
|
|
node _T_1763 = or(_T_1762, _T_1748) @[Mux.scala 27:72]
|
|
wire _T_1764 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1764 <= _T_1763 @[Mux.scala 27:72]
|
|
node _T_1765 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1766 = bits(_T_1765, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1767 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1768 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1769 = bits(_T_1768, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1770 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1771 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1772 = bits(_T_1771, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1773 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1774 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1775 = bits(_T_1774, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1776 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1777 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1778 = bits(_T_1777, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1779 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1780 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1781 = bits(_T_1780, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1782 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1783 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1784 = bits(_T_1783, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1785 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1786 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1787 = bits(_T_1786, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1788 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1789 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1790 = bits(_T_1789, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1791 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1792 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1793 = bits(_T_1792, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1794 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1795 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1796 = bits(_T_1795, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1797 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1798 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1799 = bits(_T_1798, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1800 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1801 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1802 = bits(_T_1801, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1803 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1804 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1805 = bits(_T_1804, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1806 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1807 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1808 = bits(_T_1807, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1809 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1810 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 487:285]
|
|
node _T_1811 = bits(_T_1810, 0, 0) @[el2_ifu_mem_ctl.scala 487:293]
|
|
node _T_1812 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 487:321]
|
|
node _T_1813 = mux(_T_1766, _T_1767, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1814 = mux(_T_1769, _T_1770, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1815 = mux(_T_1772, _T_1773, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1816 = mux(_T_1775, _T_1776, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1817 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1818 = mux(_T_1781, _T_1782, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1819 = mux(_T_1784, _T_1785, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1820 = mux(_T_1787, _T_1788, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1821 = mux(_T_1790, _T_1791, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1822 = mux(_T_1793, _T_1794, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1823 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1824 = mux(_T_1799, _T_1800, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1825 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1826 = mux(_T_1805, _T_1806, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1827 = mux(_T_1808, _T_1809, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1828 = mux(_T_1811, _T_1812, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1829 = or(_T_1813, _T_1814) @[Mux.scala 27:72]
|
|
node _T_1830 = or(_T_1829, _T_1815) @[Mux.scala 27:72]
|
|
node _T_1831 = or(_T_1830, _T_1816) @[Mux.scala 27:72]
|
|
node _T_1832 = or(_T_1831, _T_1817) @[Mux.scala 27:72]
|
|
node _T_1833 = or(_T_1832, _T_1818) @[Mux.scala 27:72]
|
|
node _T_1834 = or(_T_1833, _T_1819) @[Mux.scala 27:72]
|
|
node _T_1835 = or(_T_1834, _T_1820) @[Mux.scala 27:72]
|
|
node _T_1836 = or(_T_1835, _T_1821) @[Mux.scala 27:72]
|
|
node _T_1837 = or(_T_1836, _T_1822) @[Mux.scala 27:72]
|
|
node _T_1838 = or(_T_1837, _T_1823) @[Mux.scala 27:72]
|
|
node _T_1839 = or(_T_1838, _T_1824) @[Mux.scala 27:72]
|
|
node _T_1840 = or(_T_1839, _T_1825) @[Mux.scala 27:72]
|
|
node _T_1841 = or(_T_1840, _T_1826) @[Mux.scala 27:72]
|
|
node _T_1842 = or(_T_1841, _T_1827) @[Mux.scala 27:72]
|
|
node _T_1843 = or(_T_1842, _T_1828) @[Mux.scala 27:72]
|
|
wire _T_1844 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1844 <= _T_1843 @[Mux.scala 27:72]
|
|
node _T_1845 = cat(_T_1684, _T_1764) @[Cat.scala 29:58]
|
|
node _T_1846 = cat(_T_1845, _T_1844) @[Cat.scala 29:58]
|
|
node _T_1847 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1848 = bits(_T_1847, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1849 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1850 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1851 = bits(_T_1850, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1852 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1853 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1854 = bits(_T_1853, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1855 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1856 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1857 = bits(_T_1856, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1858 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1859 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1860 = bits(_T_1859, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1861 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1862 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1863 = bits(_T_1862, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1864 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1865 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1866 = bits(_T_1865, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1867 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1868 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1869 = bits(_T_1868, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1870 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1871 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1872 = bits(_T_1871, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1873 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1874 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1875 = bits(_T_1874, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1876 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1877 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1878 = bits(_T_1877, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1879 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1880 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1881 = bits(_T_1880, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1882 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1883 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1884 = bits(_T_1883, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1885 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1886 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1887 = bits(_T_1886, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1888 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1889 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1890 = bits(_T_1889, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1891 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1892 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:73]
|
|
node _T_1893 = bits(_T_1892, 0, 0) @[el2_ifu_mem_ctl.scala 488:81]
|
|
node _T_1894 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 488:109]
|
|
node _T_1895 = mux(_T_1848, _T_1849, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1896 = mux(_T_1851, _T_1852, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1897 = mux(_T_1854, _T_1855, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1898 = mux(_T_1857, _T_1858, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1899 = mux(_T_1860, _T_1861, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1900 = mux(_T_1863, _T_1864, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1901 = mux(_T_1866, _T_1867, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1902 = mux(_T_1869, _T_1870, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1903 = mux(_T_1872, _T_1873, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1904 = mux(_T_1875, _T_1876, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1905 = mux(_T_1878, _T_1879, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1906 = mux(_T_1881, _T_1882, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1907 = mux(_T_1884, _T_1885, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1908 = mux(_T_1887, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1909 = mux(_T_1890, _T_1891, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1910 = mux(_T_1893, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1911 = or(_T_1895, _T_1896) @[Mux.scala 27:72]
|
|
node _T_1912 = or(_T_1911, _T_1897) @[Mux.scala 27:72]
|
|
node _T_1913 = or(_T_1912, _T_1898) @[Mux.scala 27:72]
|
|
node _T_1914 = or(_T_1913, _T_1899) @[Mux.scala 27:72]
|
|
node _T_1915 = or(_T_1914, _T_1900) @[Mux.scala 27:72]
|
|
node _T_1916 = or(_T_1915, _T_1901) @[Mux.scala 27:72]
|
|
node _T_1917 = or(_T_1916, _T_1902) @[Mux.scala 27:72]
|
|
node _T_1918 = or(_T_1917, _T_1903) @[Mux.scala 27:72]
|
|
node _T_1919 = or(_T_1918, _T_1904) @[Mux.scala 27:72]
|
|
node _T_1920 = or(_T_1919, _T_1905) @[Mux.scala 27:72]
|
|
node _T_1921 = or(_T_1920, _T_1906) @[Mux.scala 27:72]
|
|
node _T_1922 = or(_T_1921, _T_1907) @[Mux.scala 27:72]
|
|
node _T_1923 = or(_T_1922, _T_1908) @[Mux.scala 27:72]
|
|
node _T_1924 = or(_T_1923, _T_1909) @[Mux.scala 27:72]
|
|
node _T_1925 = or(_T_1924, _T_1910) @[Mux.scala 27:72]
|
|
wire _T_1926 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1926 <= _T_1925 @[Mux.scala 27:72]
|
|
node _T_1927 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1928 = bits(_T_1927, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1929 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1930 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1931 = bits(_T_1930, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1932 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1933 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1934 = bits(_T_1933, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1935 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1936 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1937 = bits(_T_1936, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1938 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1939 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1940 = bits(_T_1939, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1941 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1942 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1943 = bits(_T_1942, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1944 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1945 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1946 = bits(_T_1945, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1947 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1948 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1949 = bits(_T_1948, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1950 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1951 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1952 = bits(_T_1951, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1953 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1954 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1955 = bits(_T_1954, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1956 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1957 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1958 = bits(_T_1957, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1959 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1960 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1961 = bits(_T_1960, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1962 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1963 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1964 = bits(_T_1963, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1965 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1966 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1967 = bits(_T_1966, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1968 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1969 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1970 = bits(_T_1969, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1971 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1972 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:183]
|
|
node _T_1973 = bits(_T_1972, 0, 0) @[el2_ifu_mem_ctl.scala 488:191]
|
|
node _T_1974 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 488:219]
|
|
node _T_1975 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1976 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1977 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1978 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1979 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1980 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1981 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1982 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1983 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1984 = mux(_T_1955, _T_1956, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1985 = mux(_T_1958, _T_1959, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1986 = mux(_T_1961, _T_1962, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1987 = mux(_T_1964, _T_1965, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1988 = mux(_T_1967, _T_1968, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1989 = mux(_T_1970, _T_1971, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1990 = mux(_T_1973, _T_1974, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1991 = or(_T_1975, _T_1976) @[Mux.scala 27:72]
|
|
node _T_1992 = or(_T_1991, _T_1977) @[Mux.scala 27:72]
|
|
node _T_1993 = or(_T_1992, _T_1978) @[Mux.scala 27:72]
|
|
node _T_1994 = or(_T_1993, _T_1979) @[Mux.scala 27:72]
|
|
node _T_1995 = or(_T_1994, _T_1980) @[Mux.scala 27:72]
|
|
node _T_1996 = or(_T_1995, _T_1981) @[Mux.scala 27:72]
|
|
node _T_1997 = or(_T_1996, _T_1982) @[Mux.scala 27:72]
|
|
node _T_1998 = or(_T_1997, _T_1983) @[Mux.scala 27:72]
|
|
node _T_1999 = or(_T_1998, _T_1984) @[Mux.scala 27:72]
|
|
node _T_2000 = or(_T_1999, _T_1985) @[Mux.scala 27:72]
|
|
node _T_2001 = or(_T_2000, _T_1986) @[Mux.scala 27:72]
|
|
node _T_2002 = or(_T_2001, _T_1987) @[Mux.scala 27:72]
|
|
node _T_2003 = or(_T_2002, _T_1988) @[Mux.scala 27:72]
|
|
node _T_2004 = or(_T_2003, _T_1989) @[Mux.scala 27:72]
|
|
node _T_2005 = or(_T_2004, _T_1990) @[Mux.scala 27:72]
|
|
wire _T_2006 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2006 <= _T_2005 @[Mux.scala 27:72]
|
|
node _T_2007 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2008 = bits(_T_2007, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2009 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2010 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2011 = bits(_T_2010, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2012 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2013 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2014 = bits(_T_2013, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2015 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2016 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2017 = bits(_T_2016, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2018 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2019 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2020 = bits(_T_2019, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2021 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2022 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2023 = bits(_T_2022, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2024 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2025 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2026 = bits(_T_2025, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2027 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2028 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2029 = bits(_T_2028, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2030 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2031 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2032 = bits(_T_2031, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2033 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2034 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2035 = bits(_T_2034, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2036 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2037 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2038 = bits(_T_2037, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2039 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2040 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2041 = bits(_T_2040, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2042 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2043 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2044 = bits(_T_2043, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2045 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2046 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2047 = bits(_T_2046, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2048 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2049 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2050 = bits(_T_2049, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2051 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2052 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 488:289]
|
|
node _T_2053 = bits(_T_2052, 0, 0) @[el2_ifu_mem_ctl.scala 488:297]
|
|
node _T_2054 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 488:325]
|
|
node _T_2055 = mux(_T_2008, _T_2009, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2056 = mux(_T_2011, _T_2012, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2057 = mux(_T_2014, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2058 = mux(_T_2017, _T_2018, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2059 = mux(_T_2020, _T_2021, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2060 = mux(_T_2023, _T_2024, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2061 = mux(_T_2026, _T_2027, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2062 = mux(_T_2029, _T_2030, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2063 = mux(_T_2032, _T_2033, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2064 = mux(_T_2035, _T_2036, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2065 = mux(_T_2038, _T_2039, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2066 = mux(_T_2041, _T_2042, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2067 = mux(_T_2044, _T_2045, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2068 = mux(_T_2047, _T_2048, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2069 = mux(_T_2050, _T_2051, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2070 = mux(_T_2053, _T_2054, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2071 = or(_T_2055, _T_2056) @[Mux.scala 27:72]
|
|
node _T_2072 = or(_T_2071, _T_2057) @[Mux.scala 27:72]
|
|
node _T_2073 = or(_T_2072, _T_2058) @[Mux.scala 27:72]
|
|
node _T_2074 = or(_T_2073, _T_2059) @[Mux.scala 27:72]
|
|
node _T_2075 = or(_T_2074, _T_2060) @[Mux.scala 27:72]
|
|
node _T_2076 = or(_T_2075, _T_2061) @[Mux.scala 27:72]
|
|
node _T_2077 = or(_T_2076, _T_2062) @[Mux.scala 27:72]
|
|
node _T_2078 = or(_T_2077, _T_2063) @[Mux.scala 27:72]
|
|
node _T_2079 = or(_T_2078, _T_2064) @[Mux.scala 27:72]
|
|
node _T_2080 = or(_T_2079, _T_2065) @[Mux.scala 27:72]
|
|
node _T_2081 = or(_T_2080, _T_2066) @[Mux.scala 27:72]
|
|
node _T_2082 = or(_T_2081, _T_2067) @[Mux.scala 27:72]
|
|
node _T_2083 = or(_T_2082, _T_2068) @[Mux.scala 27:72]
|
|
node _T_2084 = or(_T_2083, _T_2069) @[Mux.scala 27:72]
|
|
node _T_2085 = or(_T_2084, _T_2070) @[Mux.scala 27:72]
|
|
wire _T_2086 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2086 <= _T_2085 @[Mux.scala 27:72]
|
|
node _T_2087 = cat(_T_1926, _T_2006) @[Cat.scala 29:58]
|
|
node _T_2088 = cat(_T_2087, _T_2086) @[Cat.scala 29:58]
|
|
node ic_byp_data_only_pre_new = mux(_T_1604, _T_1846, _T_2088) @[el2_ifu_mem_ctl.scala 486:37]
|
|
node _T_2089 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 490:52]
|
|
node _T_2090 = bits(_T_2089, 0, 0) @[el2_ifu_mem_ctl.scala 490:62]
|
|
node _T_2091 = eq(_T_2090, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 490:31]
|
|
node _T_2092 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 490:128]
|
|
node _T_2093 = cat(UInt<16>("h00"), _T_2092) @[Cat.scala 29:58]
|
|
node _T_2094 = mux(_T_2091, ic_byp_data_only_pre_new, _T_2093) @[el2_ifu_mem_ctl.scala 490:30]
|
|
ic_byp_data_only_new <= _T_2094 @[el2_ifu_mem_ctl.scala 490:24]
|
|
node _T_2095 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 492:27]
|
|
node _T_2096 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 492:75]
|
|
node miss_wrap_f = neq(_T_2095, _T_2096) @[el2_ifu_mem_ctl.scala 492:51]
|
|
node _T_2097 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2098 = eq(_T_2097, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2099 = bits(_T_2098, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2100 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2101 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2102 = eq(_T_2101, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2103 = bits(_T_2102, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2104 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2105 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2106 = eq(_T_2105, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2107 = bits(_T_2106, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2108 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2109 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2110 = eq(_T_2109, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2111 = bits(_T_2110, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2112 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2113 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2114 = eq(_T_2113, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2115 = bits(_T_2114, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2116 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2117 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2118 = eq(_T_2117, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2119 = bits(_T_2118, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2120 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2121 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2122 = eq(_T_2121, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2123 = bits(_T_2122, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2124 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2125 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 493:102]
|
|
node _T_2126 = eq(_T_2125, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 493:127]
|
|
node _T_2127 = bits(_T_2126, 0, 0) @[el2_ifu_mem_ctl.scala 493:135]
|
|
node _T_2128 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 493:166]
|
|
node _T_2129 = mux(_T_2099, _T_2100, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2130 = mux(_T_2103, _T_2104, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2131 = mux(_T_2107, _T_2108, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2132 = mux(_T_2111, _T_2112, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2133 = mux(_T_2115, _T_2116, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2134 = mux(_T_2119, _T_2120, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2135 = mux(_T_2123, _T_2124, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2136 = mux(_T_2127, _T_2128, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2137 = or(_T_2129, _T_2130) @[Mux.scala 27:72]
|
|
node _T_2138 = or(_T_2137, _T_2131) @[Mux.scala 27:72]
|
|
node _T_2139 = or(_T_2138, _T_2132) @[Mux.scala 27:72]
|
|
node _T_2140 = or(_T_2139, _T_2133) @[Mux.scala 27:72]
|
|
node _T_2141 = or(_T_2140, _T_2134) @[Mux.scala 27:72]
|
|
node _T_2142 = or(_T_2141, _T_2135) @[Mux.scala 27:72]
|
|
node _T_2143 = or(_T_2142, _T_2136) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_bypass_index <= _T_2143 @[Mux.scala 27:72]
|
|
node _T_2144 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2145 = bits(_T_2144, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2146 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2147 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2148 = bits(_T_2147, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2149 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2150 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2151 = bits(_T_2150, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2152 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2153 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2154 = bits(_T_2153, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2155 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2156 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2157 = bits(_T_2156, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2158 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2159 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2160 = bits(_T_2159, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2161 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2162 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2163 = bits(_T_2162, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2164 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2165 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 494:110]
|
|
node _T_2166 = bits(_T_2165, 0, 0) @[el2_ifu_mem_ctl.scala 494:118]
|
|
node _T_2167 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 494:149]
|
|
node _T_2168 = mux(_T_2145, _T_2146, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2169 = mux(_T_2148, _T_2149, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2170 = mux(_T_2151, _T_2152, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2171 = mux(_T_2154, _T_2155, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2172 = mux(_T_2157, _T_2158, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2173 = mux(_T_2160, _T_2161, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2174 = mux(_T_2163, _T_2164, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2175 = mux(_T_2166, _T_2167, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2176 = or(_T_2168, _T_2169) @[Mux.scala 27:72]
|
|
node _T_2177 = or(_T_2176, _T_2170) @[Mux.scala 27:72]
|
|
node _T_2178 = or(_T_2177, _T_2171) @[Mux.scala 27:72]
|
|
node _T_2179 = or(_T_2178, _T_2172) @[Mux.scala 27:72]
|
|
node _T_2180 = or(_T_2179, _T_2173) @[Mux.scala 27:72]
|
|
node _T_2181 = or(_T_2180, _T_2174) @[Mux.scala 27:72]
|
|
node _T_2182 = or(_T_2181, _T_2175) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_inc_bypass_index <= _T_2182 @[Mux.scala 27:72]
|
|
node _T_2183 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 495:85]
|
|
node _T_2184 = eq(_T_2183, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 495:69]
|
|
node _T_2185 = and(ic_miss_buff_data_valid_bypass_index, _T_2184) @[el2_ifu_mem_ctl.scala 495:67]
|
|
node _T_2186 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 495:107]
|
|
node _T_2187 = eq(_T_2186, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 495:91]
|
|
node _T_2188 = and(_T_2185, _T_2187) @[el2_ifu_mem_ctl.scala 495:89]
|
|
node _T_2189 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 496:61]
|
|
node _T_2190 = eq(_T_2189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 496:45]
|
|
node _T_2191 = and(ic_miss_buff_data_valid_bypass_index, _T_2190) @[el2_ifu_mem_ctl.scala 496:43]
|
|
node _T_2192 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 496:83]
|
|
node _T_2193 = and(_T_2191, _T_2192) @[el2_ifu_mem_ctl.scala 496:65]
|
|
node _T_2194 = or(_T_2188, _T_2193) @[el2_ifu_mem_ctl.scala 495:112]
|
|
node _T_2195 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 497:61]
|
|
node _T_2196 = and(ic_miss_buff_data_valid_bypass_index, _T_2195) @[el2_ifu_mem_ctl.scala 497:43]
|
|
node _T_2197 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 497:83]
|
|
node _T_2198 = eq(_T_2197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 497:67]
|
|
node _T_2199 = and(_T_2196, _T_2198) @[el2_ifu_mem_ctl.scala 497:65]
|
|
node _T_2200 = or(_T_2194, _T_2199) @[el2_ifu_mem_ctl.scala 496:88]
|
|
node _T_2201 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 498:61]
|
|
node _T_2202 = and(ic_miss_buff_data_valid_bypass_index, _T_2201) @[el2_ifu_mem_ctl.scala 498:43]
|
|
node _T_2203 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 498:83]
|
|
node _T_2204 = and(_T_2202, _T_2203) @[el2_ifu_mem_ctl.scala 498:65]
|
|
node _T_2205 = and(_T_2204, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 498:87]
|
|
node _T_2206 = or(_T_2200, _T_2205) @[el2_ifu_mem_ctl.scala 497:88]
|
|
node _T_2207 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 499:61]
|
|
node _T_2208 = eq(_T_2207, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 499:45]
|
|
node _T_2209 = and(ic_miss_buff_data_valid_bypass_index, _T_2208) @[el2_ifu_mem_ctl.scala 499:43]
|
|
node _T_2210 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 499:83]
|
|
node _T_2211 = eq(_T_2210, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 499:67]
|
|
node _T_2212 = and(_T_2209, _T_2211) @[el2_ifu_mem_ctl.scala 499:65]
|
|
node _T_2213 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 499:105]
|
|
node _T_2214 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2215 = eq(_T_2213, _T_2214) @[el2_ifu_mem_ctl.scala 499:131]
|
|
node _T_2216 = and(_T_2212, _T_2215) @[el2_ifu_mem_ctl.scala 499:87]
|
|
node miss_buff_hit_unq_f = or(_T_2206, _T_2216) @[el2_ifu_mem_ctl.scala 498:131]
|
|
node _T_2217 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 501:30]
|
|
node _T_2218 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 501:68]
|
|
node _T_2219 = and(miss_buff_hit_unq_f, _T_2218) @[el2_ifu_mem_ctl.scala 501:66]
|
|
node _T_2220 = and(_T_2217, _T_2219) @[el2_ifu_mem_ctl.scala 501:43]
|
|
stream_hit_f <= _T_2220 @[el2_ifu_mem_ctl.scala 501:16]
|
|
node _T_2221 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 502:31]
|
|
node _T_2222 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 502:69]
|
|
node _T_2223 = and(miss_buff_hit_unq_f, _T_2222) @[el2_ifu_mem_ctl.scala 502:67]
|
|
node _T_2224 = and(_T_2221, _T_2223) @[el2_ifu_mem_ctl.scala 502:44]
|
|
node _T_2225 = and(_T_2224, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 502:83]
|
|
stream_miss_f <= _T_2225 @[el2_ifu_mem_ctl.scala 502:17]
|
|
node _T_2226 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 503:35]
|
|
node _T_2227 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2228 = eq(_T_2226, _T_2227) @[el2_ifu_mem_ctl.scala 503:60]
|
|
node _T_2229 = and(_T_2228, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 503:92]
|
|
node _T_2230 = and(_T_2229, stream_hit_f) @[el2_ifu_mem_ctl.scala 503:110]
|
|
stream_eol_f <= _T_2230 @[el2_ifu_mem_ctl.scala 503:16]
|
|
node _T_2231 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 504:55]
|
|
node _T_2232 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 504:87]
|
|
node _T_2233 = or(_T_2231, _T_2232) @[el2_ifu_mem_ctl.scala 504:74]
|
|
node _T_2234 = and(miss_buff_hit_unq_f, _T_2233) @[el2_ifu_mem_ctl.scala 504:41]
|
|
crit_byp_hit_f <= _T_2234 @[el2_ifu_mem_ctl.scala 504:18]
|
|
node _T_2235 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 507:37]
|
|
node _T_2236 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 507:70]
|
|
node _T_2237 = eq(_T_2236, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 507:55]
|
|
node other_tag = cat(_T_2235, _T_2237) @[Cat.scala 29:58]
|
|
node _T_2238 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2239 = bits(_T_2238, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2240 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2241 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2242 = bits(_T_2241, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2243 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2244 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2245 = bits(_T_2244, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2246 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2247 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2248 = bits(_T_2247, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2249 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2250 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2251 = bits(_T_2250, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2252 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2253 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2254 = bits(_T_2253, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2255 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2256 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2257 = bits(_T_2256, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2258 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2259 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 508:81]
|
|
node _T_2260 = bits(_T_2259, 0, 0) @[el2_ifu_mem_ctl.scala 508:89]
|
|
node _T_2261 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 508:120]
|
|
node _T_2262 = mux(_T_2239, _T_2240, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2263 = mux(_T_2242, _T_2243, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2264 = mux(_T_2245, _T_2246, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2265 = mux(_T_2248, _T_2249, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2266 = mux(_T_2251, _T_2252, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2267 = mux(_T_2254, _T_2255, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2268 = mux(_T_2257, _T_2258, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2269 = mux(_T_2260, _T_2261, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2270 = or(_T_2262, _T_2263) @[Mux.scala 27:72]
|
|
node _T_2271 = or(_T_2270, _T_2264) @[Mux.scala 27:72]
|
|
node _T_2272 = or(_T_2271, _T_2265) @[Mux.scala 27:72]
|
|
node _T_2273 = or(_T_2272, _T_2266) @[Mux.scala 27:72]
|
|
node _T_2274 = or(_T_2273, _T_2267) @[Mux.scala 27:72]
|
|
node _T_2275 = or(_T_2274, _T_2268) @[Mux.scala 27:72]
|
|
node _T_2276 = or(_T_2275, _T_2269) @[Mux.scala 27:72]
|
|
wire second_half_available : UInt<1> @[Mux.scala 27:72]
|
|
second_half_available <= _T_2276 @[Mux.scala 27:72]
|
|
node _T_2277 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 509:46]
|
|
write_ic_16_bytes <= _T_2277 @[el2_ifu_mem_ctl.scala 509:21]
|
|
node _T_2278 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2279 = eq(_T_2278, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2280 = bits(_T_2279, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2281 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2282 = eq(_T_2281, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2283 = bits(_T_2282, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2284 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2285 = eq(_T_2284, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2286 = bits(_T_2285, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2287 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2288 = eq(_T_2287, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2289 = bits(_T_2288, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2290 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2291 = eq(_T_2290, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2292 = bits(_T_2291, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2293 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2294 = eq(_T_2293, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2295 = bits(_T_2294, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2296 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2297 = eq(_T_2296, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2298 = bits(_T_2297, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2299 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2300 = eq(_T_2299, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2301 = bits(_T_2300, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2302 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2303 = eq(_T_2302, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2304 = bits(_T_2303, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2305 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2306 = eq(_T_2305, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2307 = bits(_T_2306, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2308 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2309 = eq(_T_2308, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2310 = bits(_T_2309, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2311 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2312 = eq(_T_2311, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2313 = bits(_T_2312, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2314 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2315 = eq(_T_2314, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2316 = bits(_T_2315, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2317 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2318 = eq(_T_2317, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2319 = bits(_T_2318, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2320 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2321 = eq(_T_2320, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2322 = bits(_T_2321, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2323 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2324 = eq(_T_2323, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 510:89]
|
|
node _T_2325 = bits(_T_2324, 0, 0) @[el2_ifu_mem_ctl.scala 510:97]
|
|
node _T_2326 = mux(_T_2280, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2327 = mux(_T_2283, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2328 = mux(_T_2286, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2329 = mux(_T_2289, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2330 = mux(_T_2292, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2331 = mux(_T_2295, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2332 = mux(_T_2298, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2333 = mux(_T_2301, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2334 = mux(_T_2304, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2335 = mux(_T_2307, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2336 = mux(_T_2310, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2337 = mux(_T_2313, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2338 = mux(_T_2316, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2339 = mux(_T_2319, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2340 = mux(_T_2322, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2341 = mux(_T_2325, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2342 = or(_T_2326, _T_2327) @[Mux.scala 27:72]
|
|
node _T_2343 = or(_T_2342, _T_2328) @[Mux.scala 27:72]
|
|
node _T_2344 = or(_T_2343, _T_2329) @[Mux.scala 27:72]
|
|
node _T_2345 = or(_T_2344, _T_2330) @[Mux.scala 27:72]
|
|
node _T_2346 = or(_T_2345, _T_2331) @[Mux.scala 27:72]
|
|
node _T_2347 = or(_T_2346, _T_2332) @[Mux.scala 27:72]
|
|
node _T_2348 = or(_T_2347, _T_2333) @[Mux.scala 27:72]
|
|
node _T_2349 = or(_T_2348, _T_2334) @[Mux.scala 27:72]
|
|
node _T_2350 = or(_T_2349, _T_2335) @[Mux.scala 27:72]
|
|
node _T_2351 = or(_T_2350, _T_2336) @[Mux.scala 27:72]
|
|
node _T_2352 = or(_T_2351, _T_2337) @[Mux.scala 27:72]
|
|
node _T_2353 = or(_T_2352, _T_2338) @[Mux.scala 27:72]
|
|
node _T_2354 = or(_T_2353, _T_2339) @[Mux.scala 27:72]
|
|
node _T_2355 = or(_T_2354, _T_2340) @[Mux.scala 27:72]
|
|
node _T_2356 = or(_T_2355, _T_2341) @[Mux.scala 27:72]
|
|
wire _T_2357 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2357 <= _T_2356 @[Mux.scala 27:72]
|
|
node _T_2358 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2359 = eq(_T_2358, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2360 = bits(_T_2359, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2361 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2362 = eq(_T_2361, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2363 = bits(_T_2362, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2364 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2365 = eq(_T_2364, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2366 = bits(_T_2365, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2367 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2368 = eq(_T_2367, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2369 = bits(_T_2368, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2370 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2371 = eq(_T_2370, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2372 = bits(_T_2371, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2373 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2374 = eq(_T_2373, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2375 = bits(_T_2374, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2376 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2377 = eq(_T_2376, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2378 = bits(_T_2377, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2379 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2380 = eq(_T_2379, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 511:64]
|
|
node _T_2381 = bits(_T_2380, 0, 0) @[el2_ifu_mem_ctl.scala 511:72]
|
|
node _T_2382 = mux(_T_2360, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2383 = mux(_T_2363, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2384 = mux(_T_2366, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2385 = mux(_T_2369, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2386 = mux(_T_2372, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2387 = mux(_T_2375, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2388 = mux(_T_2378, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2389 = mux(_T_2381, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2390 = or(_T_2382, _T_2383) @[Mux.scala 27:72]
|
|
node _T_2391 = or(_T_2390, _T_2384) @[Mux.scala 27:72]
|
|
node _T_2392 = or(_T_2391, _T_2385) @[Mux.scala 27:72]
|
|
node _T_2393 = or(_T_2392, _T_2386) @[Mux.scala 27:72]
|
|
node _T_2394 = or(_T_2393, _T_2387) @[Mux.scala 27:72]
|
|
node _T_2395 = or(_T_2394, _T_2388) @[Mux.scala 27:72]
|
|
node _T_2396 = or(_T_2395, _T_2389) @[Mux.scala 27:72]
|
|
wire _T_2397 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2397 <= _T_2396 @[Mux.scala 27:72]
|
|
node _T_2398 = cat(_T_2357, _T_2397) @[Cat.scala 29:58]
|
|
ic_miss_buff_half <= _T_2398 @[el2_ifu_mem_ctl.scala 510:21]
|
|
node _T_2399 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 513:44]
|
|
node _T_2400 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 513:91]
|
|
node _T_2401 = eq(_T_2400, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 513:60]
|
|
node _T_2402 = and(_T_2399, _T_2401) @[el2_ifu_mem_ctl.scala 513:58]
|
|
ic_rd_parity_final_err <= _T_2402 @[el2_ifu_mem_ctl.scala 513:26]
|
|
wire ifu_ic_rw_int_addr_ff : UInt<6>
|
|
ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
|
|
wire perr_sb_write_status : UInt<1>
|
|
perr_sb_write_status <= UInt<1>("h00")
|
|
reg perr_ic_index_ff : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_sb_write_status : @[Reg.scala 28:19]
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
wire perr_sel_invalidate : UInt<1>
|
|
perr_sel_invalidate <= UInt<1>("h00")
|
|
node _T_2403 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15]
|
|
node perr_err_inv_way = mux(_T_2403, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2404 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 520:34]
|
|
iccm_correct_ecc <= _T_2404 @[el2_ifu_mem_ctl.scala 520:20]
|
|
node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 521:37]
|
|
reg dma_sb_err_state_ff : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 522:61]
|
|
dma_sb_err_state_ff <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 522:61]
|
|
wire perr_nxtstate : UInt<3>
|
|
perr_nxtstate <= UInt<1>("h00")
|
|
wire perr_state_en : UInt<1>
|
|
perr_state_en <= UInt<1>("h00")
|
|
wire iccm_error_start : UInt<1>
|
|
iccm_error_start <= UInt<1>("h00")
|
|
node _T_2405 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2405 : @[Conditional.scala 40:58]
|
|
node _T_2406 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 530:89]
|
|
node _T_2407 = and(io.ic_error_start, _T_2406) @[el2_ifu_mem_ctl.scala 530:87]
|
|
node _T_2408 = bits(_T_2407, 0, 0) @[el2_ifu_mem_ctl.scala 530:110]
|
|
node _T_2409 = mux(_T_2408, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 530:67]
|
|
node _T_2410 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2409) @[el2_ifu_mem_ctl.scala 530:27]
|
|
perr_nxtstate <= _T_2410 @[el2_ifu_mem_ctl.scala 530:21]
|
|
node _T_2411 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 531:44]
|
|
node _T_2412 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 531:67]
|
|
node _T_2413 = and(_T_2411, _T_2412) @[el2_ifu_mem_ctl.scala 531:65]
|
|
node _T_2414 = or(_T_2413, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 531:88]
|
|
node _T_2415 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 531:114]
|
|
node _T_2416 = and(_T_2414, _T_2415) @[el2_ifu_mem_ctl.scala 531:112]
|
|
perr_state_en <= _T_2416 @[el2_ifu_mem_ctl.scala 531:21]
|
|
perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 532:28]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2417 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2417 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 535:21]
|
|
node _T_2418 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 536:50]
|
|
perr_state_en <= _T_2418 @[el2_ifu_mem_ctl.scala 536:21]
|
|
node _T_2419 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 537:56]
|
|
perr_sel_invalidate <= _T_2419 @[el2_ifu_mem_ctl.scala 537:27]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2420 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2420 : @[Conditional.scala 39:67]
|
|
node _T_2421 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 540:54]
|
|
node _T_2422 = or(_T_2421, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 540:84]
|
|
node _T_2423 = bits(_T_2422, 0, 0) @[el2_ifu_mem_ctl.scala 540:115]
|
|
node _T_2424 = mux(_T_2423, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 540:27]
|
|
perr_nxtstate <= _T_2424 @[el2_ifu_mem_ctl.scala 540:21]
|
|
node _T_2425 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 541:50]
|
|
perr_state_en <= _T_2425 @[el2_ifu_mem_ctl.scala 541:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2426 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2426 : @[Conditional.scala 39:67]
|
|
node _T_2427 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 544:27]
|
|
perr_nxtstate <= _T_2427 @[el2_ifu_mem_ctl.scala 544:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 545:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2428 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2428 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 548:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 549:21]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2429 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_state_en : @[Reg.scala 28:19]
|
|
_T_2429 <= perr_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
perr_state <= _T_2429 @[el2_ifu_mem_ctl.scala 552:14]
|
|
wire err_stop_nxtstate : UInt<2>
|
|
err_stop_nxtstate <= UInt<1>("h00")
|
|
wire err_stop_state_en : UInt<1>
|
|
err_stop_state_en <= UInt<1>("h00")
|
|
wire iccm_correction_state : UInt<1>
|
|
iccm_correction_state <= UInt<1>("h00")
|
|
node _T_2430 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2430 : @[Conditional.scala 40:58]
|
|
err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 560:25]
|
|
node _T_2431 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 561:66]
|
|
node _T_2432 = and(io.dec_tlu_flush_err_wb, _T_2431) @[el2_ifu_mem_ctl.scala 561:52]
|
|
node _T_2433 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 561:83]
|
|
node _T_2434 = and(_T_2432, _T_2433) @[el2_ifu_mem_ctl.scala 561:81]
|
|
err_stop_state_en <= _T_2434 @[el2_ifu_mem_ctl.scala 561:25]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2435 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2435 : @[Conditional.scala 39:67]
|
|
node _T_2436 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 564:59]
|
|
node _T_2437 = or(_T_2436, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 564:86]
|
|
node _T_2438 = bits(_T_2437, 0, 0) @[el2_ifu_mem_ctl.scala 564:117]
|
|
node _T_2439 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 565:31]
|
|
node _T_2440 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 565:56]
|
|
node _T_2441 = and(_T_2440, two_byte_instr) @[el2_ifu_mem_ctl.scala 565:59]
|
|
node _T_2442 = or(_T_2439, _T_2441) @[el2_ifu_mem_ctl.scala 565:38]
|
|
node _T_2443 = bits(_T_2442, 0, 0) @[el2_ifu_mem_ctl.scala 565:83]
|
|
node _T_2444 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 566:31]
|
|
node _T_2445 = bits(_T_2444, 0, 0) @[el2_ifu_mem_ctl.scala 566:41]
|
|
node _T_2446 = mux(_T_2445, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 566:14]
|
|
node _T_2447 = mux(_T_2443, UInt<2>("h03"), _T_2446) @[el2_ifu_mem_ctl.scala 565:12]
|
|
node _T_2448 = mux(_T_2438, UInt<2>("h00"), _T_2447) @[el2_ifu_mem_ctl.scala 564:31]
|
|
err_stop_nxtstate <= _T_2448 @[el2_ifu_mem_ctl.scala 564:25]
|
|
node _T_2449 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 567:54]
|
|
node _T_2450 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 567:99]
|
|
node _T_2451 = or(_T_2449, _T_2450) @[el2_ifu_mem_ctl.scala 567:81]
|
|
node _T_2452 = or(_T_2451, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 567:103]
|
|
node _T_2453 = or(_T_2452, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 567:126]
|
|
err_stop_state_en <= _T_2453 @[el2_ifu_mem_ctl.scala 567:25]
|
|
node _T_2454 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 568:43]
|
|
node _T_2455 = eq(_T_2454, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 568:48]
|
|
node _T_2456 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 568:75]
|
|
node _T_2457 = and(_T_2456, two_byte_instr) @[el2_ifu_mem_ctl.scala 568:79]
|
|
node _T_2458 = or(_T_2455, _T_2457) @[el2_ifu_mem_ctl.scala 568:56]
|
|
node _T_2459 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 568:122]
|
|
node _T_2460 = eq(_T_2459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 568:101]
|
|
node _T_2461 = and(_T_2458, _T_2460) @[el2_ifu_mem_ctl.scala 568:99]
|
|
err_stop_fetch <= _T_2461 @[el2_ifu_mem_ctl.scala 568:22]
|
|
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 569:29]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2462 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2462 : @[Conditional.scala 39:67]
|
|
node _T_2463 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 572:59]
|
|
node _T_2464 = or(_T_2463, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 572:86]
|
|
node _T_2465 = bits(_T_2464, 0, 0) @[el2_ifu_mem_ctl.scala 572:111]
|
|
node _T_2466 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 573:46]
|
|
node _T_2467 = bits(_T_2466, 0, 0) @[el2_ifu_mem_ctl.scala 573:50]
|
|
node _T_2468 = mux(_T_2467, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 573:29]
|
|
node _T_2469 = mux(_T_2465, UInt<2>("h00"), _T_2468) @[el2_ifu_mem_ctl.scala 572:31]
|
|
err_stop_nxtstate <= _T_2469 @[el2_ifu_mem_ctl.scala 572:25]
|
|
node _T_2470 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 574:54]
|
|
node _T_2471 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 574:99]
|
|
node _T_2472 = or(_T_2470, _T_2471) @[el2_ifu_mem_ctl.scala 574:81]
|
|
node _T_2473 = or(_T_2472, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 574:103]
|
|
err_stop_state_en <= _T_2473 @[el2_ifu_mem_ctl.scala 574:25]
|
|
node _T_2474 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 575:41]
|
|
node _T_2475 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 575:47]
|
|
node _T_2476 = and(_T_2474, _T_2475) @[el2_ifu_mem_ctl.scala 575:45]
|
|
node _T_2477 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 575:69]
|
|
node _T_2478 = and(_T_2476, _T_2477) @[el2_ifu_mem_ctl.scala 575:67]
|
|
err_stop_fetch <= _T_2478 @[el2_ifu_mem_ctl.scala 575:22]
|
|
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 576:29]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2479 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2479 : @[Conditional.scala 39:67]
|
|
node _T_2480 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 579:62]
|
|
node _T_2481 = and(io.dec_tlu_flush_lower_wb, _T_2480) @[el2_ifu_mem_ctl.scala 579:60]
|
|
node _T_2482 = or(_T_2481, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 579:88]
|
|
node _T_2483 = or(_T_2482, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 579:115]
|
|
node _T_2484 = bits(_T_2483, 0, 0) @[el2_ifu_mem_ctl.scala 579:140]
|
|
node _T_2485 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 580:60]
|
|
node _T_2486 = mux(_T_2485, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 580:29]
|
|
node _T_2487 = mux(_T_2484, UInt<2>("h00"), _T_2486) @[el2_ifu_mem_ctl.scala 579:31]
|
|
err_stop_nxtstate <= _T_2487 @[el2_ifu_mem_ctl.scala 579:25]
|
|
node _T_2488 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 581:54]
|
|
node _T_2489 = or(_T_2488, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 581:81]
|
|
err_stop_state_en <= _T_2489 @[el2_ifu_mem_ctl.scala 581:25]
|
|
err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 582:22]
|
|
iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 583:29]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2490 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when err_stop_state_en : @[Reg.scala 28:19]
|
|
_T_2490 <= err_stop_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
err_stop_state <= _T_2490 @[el2_ifu_mem_ctl.scala 586:18]
|
|
bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 587:22]
|
|
reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 588:61]
|
|
bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 588:61]
|
|
reg _T_2491 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 589:52]
|
|
_T_2491 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 589:52]
|
|
scnd_miss_req_q <= _T_2491 @[el2_ifu_mem_ctl.scala 589:19]
|
|
reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 590:57]
|
|
scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 590:57]
|
|
wire bus_cmd_req_hold : UInt<1>
|
|
bus_cmd_req_hold <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_valid : UInt<1>
|
|
ifu_bus_cmd_valid <= UInt<1>("h00")
|
|
wire bus_cmd_beat_count : UInt<3>
|
|
bus_cmd_beat_count <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_ready : UInt<1>
|
|
ifu_bus_cmd_ready <= UInt<1>("h00")
|
|
node _T_2492 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 595:45]
|
|
node _T_2493 = or(_T_2492, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 595:64]
|
|
node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:87]
|
|
node _T_2495 = and(_T_2493, _T_2494) @[el2_ifu_mem_ctl.scala 595:85]
|
|
node _T_2496 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2497 = eq(bus_cmd_beat_count, _T_2496) @[el2_ifu_mem_ctl.scala 595:133]
|
|
node _T_2498 = and(_T_2497, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 595:164]
|
|
node _T_2499 = and(_T_2498, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 595:184]
|
|
node _T_2500 = and(_T_2499, miss_pending) @[el2_ifu_mem_ctl.scala 595:204]
|
|
node _T_2501 = eq(_T_2500, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:112]
|
|
node ifc_bus_ic_req_ff_in = and(_T_2495, _T_2501) @[el2_ifu_mem_ctl.scala 595:110]
|
|
node _T_2502 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 596:80]
|
|
reg _T_2503 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2502 : @[Reg.scala 28:19]
|
|
_T_2503 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_cmd_valid <= _T_2503 @[el2_ifu_mem_ctl.scala 596:21]
|
|
wire bus_cmd_sent : UInt<1>
|
|
bus_cmd_sent <= UInt<1>("h00")
|
|
node _T_2504 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 598:39]
|
|
node _T_2505 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:61]
|
|
node _T_2506 = and(_T_2504, _T_2505) @[el2_ifu_mem_ctl.scala 598:59]
|
|
node _T_2507 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:77]
|
|
node bus_cmd_req_in = and(_T_2506, _T_2507) @[el2_ifu_mem_ctl.scala 598:75]
|
|
reg _T_2508 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 599:49]
|
|
_T_2508 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 599:49]
|
|
bus_cmd_sent <= _T_2508 @[el2_ifu_mem_ctl.scala 599:16]
|
|
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 601:22]
|
|
node _T_2509 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2510 = mux(_T_2509, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2511 = and(bus_rd_addr_count, _T_2510) @[el2_ifu_mem_ctl.scala 602:40]
|
|
io.ifu_axi_arid <= _T_2511 @[el2_ifu_mem_ctl.scala 602:19]
|
|
node _T_2512 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
node _T_2513 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2514 = mux(_T_2513, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2515 = and(_T_2512, _T_2514) @[el2_ifu_mem_ctl.scala 603:57]
|
|
io.ifu_axi_araddr <= _T_2515 @[el2_ifu_mem_ctl.scala 603:21]
|
|
io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 604:21]
|
|
io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 605:22]
|
|
node _T_2516 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 606:43]
|
|
io.ifu_axi_arregion <= _T_2516 @[el2_ifu_mem_ctl.scala 606:23]
|
|
io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 607:22]
|
|
io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 608:21]
|
|
reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rvalid_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_arvalid_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rresp_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rresp_ff <= io.ifu_axi_rresp @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg _T_2517 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2517 <= io.ifu_axi_rdata @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rdata_ff <= _T_2517 @[el2_ifu_mem_ctl.scala 618:20]
|
|
reg _T_2518 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2518 <= io.ifu_axi_rid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rid_ff <= _T_2518 @[el2_ifu_mem_ctl.scala 619:18]
|
|
ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 620:21]
|
|
ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 621:21]
|
|
ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 622:21]
|
|
ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 623:19]
|
|
ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 624:21]
|
|
node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 626:42]
|
|
node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 627:45]
|
|
node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 628:51]
|
|
node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 629:49]
|
|
node _T_2519 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 630:35]
|
|
node _T_2520 = and(_T_2519, miss_pending) @[el2_ifu_mem_ctl.scala 630:53]
|
|
node _T_2521 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:70]
|
|
node _T_2522 = and(_T_2520, _T_2521) @[el2_ifu_mem_ctl.scala 630:68]
|
|
bus_cmd_sent <= _T_2522 @[el2_ifu_mem_ctl.scala 630:16]
|
|
wire bus_last_data_beat : UInt<1>
|
|
bus_last_data_beat <= UInt<1>("h00")
|
|
node _T_2523 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 632:50]
|
|
node _T_2524 = and(bus_ifu_wr_en_ff, _T_2523) @[el2_ifu_mem_ctl.scala 632:48]
|
|
node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 632:72]
|
|
node bus_inc_data_beat_cnt = and(_T_2524, _T_2525) @[el2_ifu_mem_ctl.scala 632:70]
|
|
node _T_2526 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 633:68]
|
|
node _T_2527 = or(ic_act_miss_f, _T_2526) @[el2_ifu_mem_ctl.scala 633:48]
|
|
node bus_reset_data_beat_cnt = or(_T_2527, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 633:91]
|
|
node _T_2528 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:32]
|
|
node _T_2529 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:57]
|
|
node bus_hold_data_beat_cnt = and(_T_2528, _T_2529) @[el2_ifu_mem_ctl.scala 634:55]
|
|
wire bus_data_beat_count : UInt<3>
|
|
bus_data_beat_count <= UInt<1>("h00")
|
|
node _T_2530 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 636:115]
|
|
node _T_2531 = tail(_T_2530, 1) @[el2_ifu_mem_ctl.scala 636:115]
|
|
node _T_2532 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2533 = mux(bus_inc_data_beat_cnt, _T_2531, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2534 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2535 = or(_T_2532, _T_2533) @[Mux.scala 27:72]
|
|
node _T_2536 = or(_T_2535, _T_2534) @[Mux.scala 27:72]
|
|
wire _T_2537 : UInt<3> @[Mux.scala 27:72]
|
|
_T_2537 <= _T_2536 @[Mux.scala 27:72]
|
|
bus_new_data_beat_count <= _T_2537 @[el2_ifu_mem_ctl.scala 636:27]
|
|
reg _T_2538 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 637:56]
|
|
_T_2538 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 637:56]
|
|
bus_data_beat_count <= _T_2538 @[el2_ifu_mem_ctl.scala 637:23]
|
|
node _T_2539 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 638:49]
|
|
node _T_2540 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 638:73]
|
|
node _T_2541 = and(_T_2539, _T_2540) @[el2_ifu_mem_ctl.scala 638:71]
|
|
node _T_2542 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 638:116]
|
|
node _T_2543 = and(last_data_recieved_ff, _T_2542) @[el2_ifu_mem_ctl.scala 638:114]
|
|
node last_data_recieved_in = or(_T_2541, _T_2543) @[el2_ifu_mem_ctl.scala 638:89]
|
|
reg _T_2544 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 639:58]
|
|
_T_2544 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 639:58]
|
|
last_data_recieved_ff <= _T_2544 @[el2_ifu_mem_ctl.scala 639:25]
|
|
node _T_2545 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 641:35]
|
|
node _T_2546 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 641:56]
|
|
node _T_2547 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 642:39]
|
|
node _T_2548 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 643:45]
|
|
node _T_2549 = tail(_T_2548, 1) @[el2_ifu_mem_ctl.scala 643:45]
|
|
node _T_2550 = mux(bus_cmd_sent, _T_2549, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 643:12]
|
|
node _T_2551 = mux(scnd_miss_req_q, _T_2547, _T_2550) @[el2_ifu_mem_ctl.scala 642:10]
|
|
node bus_new_rd_addr_count = mux(_T_2545, _T_2546, _T_2551) @[el2_ifu_mem_ctl.scala 641:34]
|
|
node _T_2552 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 644:81]
|
|
node _T_2553 = or(_T_2552, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 644:97]
|
|
reg _T_2554 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2553 : @[Reg.scala 28:19]
|
|
_T_2554 <= bus_new_rd_addr_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_rd_addr_count <= _T_2554 @[el2_ifu_mem_ctl.scala 644:21]
|
|
node _T_2555 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 646:48]
|
|
node _T_2556 = and(_T_2555, miss_pending) @[el2_ifu_mem_ctl.scala 646:68]
|
|
node _T_2557 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 646:85]
|
|
node bus_inc_cmd_beat_cnt = and(_T_2556, _T_2557) @[el2_ifu_mem_ctl.scala 646:83]
|
|
node _T_2558 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 647:51]
|
|
node _T_2559 = and(ic_act_miss_f, _T_2558) @[el2_ifu_mem_ctl.scala 647:49]
|
|
node bus_reset_cmd_beat_cnt_0 = or(_T_2559, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 647:73]
|
|
node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 648:57]
|
|
node _T_2560 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 649:31]
|
|
node _T_2561 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 649:71]
|
|
node _T_2562 = or(_T_2561, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 649:87]
|
|
node _T_2563 = eq(_T_2562, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 649:55]
|
|
node bus_hold_cmd_beat_cnt = and(_T_2560, _T_2563) @[el2_ifu_mem_ctl.scala 649:53]
|
|
node _T_2564 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 650:46]
|
|
node bus_cmd_beat_en = or(_T_2564, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 650:62]
|
|
node _T_2565 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 651:107]
|
|
node _T_2566 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 652:46]
|
|
node _T_2567 = tail(_T_2566, 1) @[el2_ifu_mem_ctl.scala 652:46]
|
|
node _T_2568 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2569 = mux(_T_2565, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2570 = mux(bus_inc_cmd_beat_cnt, _T_2567, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2571 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2572 = or(_T_2568, _T_2569) @[Mux.scala 27:72]
|
|
node _T_2573 = or(_T_2572, _T_2570) @[Mux.scala 27:72]
|
|
node _T_2574 = or(_T_2573, _T_2571) @[Mux.scala 27:72]
|
|
wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72]
|
|
bus_new_cmd_beat_count <= _T_2574 @[Mux.scala 27:72]
|
|
node _T_2575 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 653:84]
|
|
node _T_2576 = or(_T_2575, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 653:100]
|
|
node _T_2577 = and(_T_2576, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 653:125]
|
|
reg _T_2578 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2577 : @[Reg.scala 28:19]
|
|
_T_2578 <= bus_new_cmd_beat_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_cmd_beat_count <= _T_2578 @[el2_ifu_mem_ctl.scala 653:22]
|
|
node _T_2579 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 654:69]
|
|
node _T_2580 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 654:101]
|
|
node _T_2581 = mux(uncacheable_miss_ff, _T_2579, _T_2580) @[el2_ifu_mem_ctl.scala 654:28]
|
|
bus_last_data_beat <= _T_2581 @[el2_ifu_mem_ctl.scala 654:22]
|
|
node _T_2582 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 655:35]
|
|
bus_ifu_wr_en <= _T_2582 @[el2_ifu_mem_ctl.scala 655:17]
|
|
node _T_2583 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 656:41]
|
|
bus_ifu_wr_en_ff <= _T_2583 @[el2_ifu_mem_ctl.scala 656:20]
|
|
node _T_2584 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 657:44]
|
|
node _T_2585 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 657:61]
|
|
node _T_2586 = and(_T_2584, _T_2585) @[el2_ifu_mem_ctl.scala 657:59]
|
|
node _T_2587 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 657:103]
|
|
node _T_2588 = eq(_T_2587, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 657:84]
|
|
node _T_2589 = and(_T_2586, _T_2588) @[el2_ifu_mem_ctl.scala 657:82]
|
|
node _T_2590 = and(_T_2589, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 657:108]
|
|
bus_ifu_wr_en_ff_q <= _T_2590 @[el2_ifu_mem_ctl.scala 657:22]
|
|
node _T_2591 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 658:51]
|
|
node _T_2592 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 658:68]
|
|
node bus_ifu_wr_en_ff_wo_err = and(_T_2591, _T_2592) @[el2_ifu_mem_ctl.scala 658:66]
|
|
reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 659:61]
|
|
ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 659:61]
|
|
node _T_2593 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 660:66]
|
|
node _T_2594 = and(ic_act_miss_f_delayed, _T_2593) @[el2_ifu_mem_ctl.scala 660:53]
|
|
node _T_2595 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:86]
|
|
node _T_2596 = and(_T_2594, _T_2595) @[el2_ifu_mem_ctl.scala 660:84]
|
|
reset_tag_valid_for_miss <= _T_2596 @[el2_ifu_mem_ctl.scala 660:28]
|
|
node _T_2597 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 661:47]
|
|
node _T_2598 = and(_T_2597, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 661:50]
|
|
node _T_2599 = and(_T_2598, miss_pending) @[el2_ifu_mem_ctl.scala 661:68]
|
|
bus_ifu_wr_data_error <= _T_2599 @[el2_ifu_mem_ctl.scala 661:25]
|
|
node _T_2600 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 662:48]
|
|
node _T_2601 = and(_T_2600, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 662:52]
|
|
node _T_2602 = and(_T_2601, miss_pending) @[el2_ifu_mem_ctl.scala 662:73]
|
|
bus_ifu_wr_data_error_ff <= _T_2602 @[el2_ifu_mem_ctl.scala 662:28]
|
|
wire ifc_dma_access_ok_d : UInt<1>
|
|
ifc_dma_access_ok_d <= UInt<1>("h00")
|
|
reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 664:62]
|
|
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 664:62]
|
|
node _T_2603 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 665:43]
|
|
ic_crit_wd_rdy <= _T_2603 @[el2_ifu_mem_ctl.scala 665:18]
|
|
node _T_2604 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 666:35]
|
|
last_beat <= _T_2604 @[el2_ifu_mem_ctl.scala 666:13]
|
|
reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 667:18]
|
|
node _T_2605 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:50]
|
|
node _T_2606 = and(io.ifc_dma_access_ok, _T_2605) @[el2_ifu_mem_ctl.scala 669:47]
|
|
node _T_2607 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:70]
|
|
node _T_2608 = and(_T_2606, _T_2607) @[el2_ifu_mem_ctl.scala 669:68]
|
|
ifc_dma_access_ok_d <= _T_2608 @[el2_ifu_mem_ctl.scala 669:23]
|
|
node _T_2609 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 670:54]
|
|
node _T_2610 = and(io.ifc_dma_access_ok, _T_2609) @[el2_ifu_mem_ctl.scala 670:51]
|
|
node _T_2611 = and(_T_2610, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 670:72]
|
|
node _T_2612 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 670:111]
|
|
node _T_2613 = and(_T_2611, _T_2612) @[el2_ifu_mem_ctl.scala 670:97]
|
|
node _T_2614 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 670:129]
|
|
node iccm_ready = and(_T_2613, _T_2614) @[el2_ifu_mem_ctl.scala 670:127]
|
|
reg _T_2615 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 672:51]
|
|
_T_2615 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 672:51]
|
|
dma_iccm_req_f <= _T_2615 @[el2_ifu_mem_ctl.scala 672:18]
|
|
node _T_2616 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 673:40]
|
|
node _T_2617 = and(_T_2616, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 673:58]
|
|
node _T_2618 = or(_T_2617, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 673:79]
|
|
io.iccm_wren <= _T_2618 @[el2_ifu_mem_ctl.scala 673:16]
|
|
node _T_2619 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 674:40]
|
|
node _T_2620 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 674:60]
|
|
node _T_2621 = and(_T_2619, _T_2620) @[el2_ifu_mem_ctl.scala 674:58]
|
|
node _T_2622 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 674:104]
|
|
node _T_2623 = or(_T_2621, _T_2622) @[el2_ifu_mem_ctl.scala 674:79]
|
|
io.iccm_rden <= _T_2623 @[el2_ifu_mem_ctl.scala 674:16]
|
|
node _T_2624 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 675:43]
|
|
node _T_2625 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 675:63]
|
|
node iccm_dma_rden = and(_T_2624, _T_2625) @[el2_ifu_mem_ctl.scala 675:61]
|
|
node _T_2626 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2627 = mux(_T_2626, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2628 = and(_T_2627, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 676:47]
|
|
io.iccm_wr_size <= _T_2628 @[el2_ifu_mem_ctl.scala 676:19]
|
|
node _T_2629 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 677:54]
|
|
wire _T_2630 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2631 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2632 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2633 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2634 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2635 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2636 = bits(_T_2629, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2631[0] <= _T_2636 @[el2_lib.scala 262:30]
|
|
node _T_2637 = bits(_T_2629, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2632[0] <= _T_2637 @[el2_lib.scala 263:30]
|
|
node _T_2638 = bits(_T_2629, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2635[0] <= _T_2638 @[el2_lib.scala 266:30]
|
|
node _T_2639 = bits(_T_2629, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2630[0] <= _T_2639 @[el2_lib.scala 261:30]
|
|
node _T_2640 = bits(_T_2629, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2632[1] <= _T_2640 @[el2_lib.scala 263:30]
|
|
node _T_2641 = bits(_T_2629, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2635[1] <= _T_2641 @[el2_lib.scala 266:30]
|
|
node _T_2642 = bits(_T_2629, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2632[2] <= _T_2642 @[el2_lib.scala 263:30]
|
|
node _T_2643 = bits(_T_2629, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2635[2] <= _T_2643 @[el2_lib.scala 266:30]
|
|
node _T_2644 = bits(_T_2629, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2630[1] <= _T_2644 @[el2_lib.scala 261:30]
|
|
node _T_2645 = bits(_T_2629, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2631[1] <= _T_2645 @[el2_lib.scala 262:30]
|
|
node _T_2646 = bits(_T_2629, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2635[3] <= _T_2646 @[el2_lib.scala 266:30]
|
|
node _T_2647 = bits(_T_2629, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2631[2] <= _T_2647 @[el2_lib.scala 262:30]
|
|
node _T_2648 = bits(_T_2629, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2635[4] <= _T_2648 @[el2_lib.scala 266:30]
|
|
node _T_2649 = bits(_T_2629, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2630[2] <= _T_2649 @[el2_lib.scala 261:30]
|
|
node _T_2650 = bits(_T_2629, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2635[5] <= _T_2650 @[el2_lib.scala 266:30]
|
|
node _T_2651 = bits(_T_2629, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2630[3] <= _T_2651 @[el2_lib.scala 261:30]
|
|
node _T_2652 = bits(_T_2629, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2631[3] <= _T_2652 @[el2_lib.scala 262:30]
|
|
node _T_2653 = bits(_T_2629, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2632[3] <= _T_2653 @[el2_lib.scala 263:30]
|
|
node _T_2654 = bits(_T_2629, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2633[0] <= _T_2654 @[el2_lib.scala 264:30]
|
|
node _T_2655 = bits(_T_2629, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2634[0] <= _T_2655 @[el2_lib.scala 265:30]
|
|
node _T_2656 = bits(_T_2629, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2631[4] <= _T_2656 @[el2_lib.scala 262:30]
|
|
node _T_2657 = bits(_T_2629, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2632[4] <= _T_2657 @[el2_lib.scala 263:30]
|
|
node _T_2658 = bits(_T_2629, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2633[1] <= _T_2658 @[el2_lib.scala 264:30]
|
|
node _T_2659 = bits(_T_2629, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2634[1] <= _T_2659 @[el2_lib.scala 265:30]
|
|
node _T_2660 = bits(_T_2629, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2630[4] <= _T_2660 @[el2_lib.scala 261:30]
|
|
node _T_2661 = bits(_T_2629, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2632[5] <= _T_2661 @[el2_lib.scala 263:30]
|
|
node _T_2662 = bits(_T_2629, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2633[2] <= _T_2662 @[el2_lib.scala 264:30]
|
|
node _T_2663 = bits(_T_2629, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2634[2] <= _T_2663 @[el2_lib.scala 265:30]
|
|
node _T_2664 = bits(_T_2629, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2632[6] <= _T_2664 @[el2_lib.scala 263:30]
|
|
node _T_2665 = bits(_T_2629, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2633[3] <= _T_2665 @[el2_lib.scala 264:30]
|
|
node _T_2666 = bits(_T_2629, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2634[3] <= _T_2666 @[el2_lib.scala 265:30]
|
|
node _T_2667 = bits(_T_2629, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2630[5] <= _T_2667 @[el2_lib.scala 261:30]
|
|
node _T_2668 = bits(_T_2629, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2631[5] <= _T_2668 @[el2_lib.scala 262:30]
|
|
node _T_2669 = bits(_T_2629, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2633[4] <= _T_2669 @[el2_lib.scala 264:30]
|
|
node _T_2670 = bits(_T_2629, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2634[4] <= _T_2670 @[el2_lib.scala 265:30]
|
|
node _T_2671 = bits(_T_2629, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2631[6] <= _T_2671 @[el2_lib.scala 262:30]
|
|
node _T_2672 = bits(_T_2629, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2633[5] <= _T_2672 @[el2_lib.scala 264:30]
|
|
node _T_2673 = bits(_T_2629, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2634[5] <= _T_2673 @[el2_lib.scala 265:30]
|
|
node _T_2674 = bits(_T_2629, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2630[6] <= _T_2674 @[el2_lib.scala 261:30]
|
|
node _T_2675 = bits(_T_2629, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2633[6] <= _T_2675 @[el2_lib.scala 264:30]
|
|
node _T_2676 = bits(_T_2629, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2634[6] <= _T_2676 @[el2_lib.scala 265:30]
|
|
node _T_2677 = bits(_T_2629, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2633[7] <= _T_2677 @[el2_lib.scala 264:30]
|
|
node _T_2678 = bits(_T_2629, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2634[7] <= _T_2678 @[el2_lib.scala 265:30]
|
|
node _T_2679 = bits(_T_2629, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2630[7] <= _T_2679 @[el2_lib.scala 261:30]
|
|
node _T_2680 = bits(_T_2629, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2631[7] <= _T_2680 @[el2_lib.scala 262:30]
|
|
node _T_2681 = bits(_T_2629, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2632[7] <= _T_2681 @[el2_lib.scala 263:30]
|
|
node _T_2682 = bits(_T_2629, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2634[8] <= _T_2682 @[el2_lib.scala 265:30]
|
|
node _T_2683 = bits(_T_2629, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2631[8] <= _T_2683 @[el2_lib.scala 262:30]
|
|
node _T_2684 = bits(_T_2629, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2632[8] <= _T_2684 @[el2_lib.scala 263:30]
|
|
node _T_2685 = bits(_T_2629, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2634[9] <= _T_2685 @[el2_lib.scala 265:30]
|
|
node _T_2686 = bits(_T_2629, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2630[8] <= _T_2686 @[el2_lib.scala 261:30]
|
|
node _T_2687 = bits(_T_2629, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2632[9] <= _T_2687 @[el2_lib.scala 263:30]
|
|
node _T_2688 = bits(_T_2629, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2634[10] <= _T_2688 @[el2_lib.scala 265:30]
|
|
node _T_2689 = bits(_T_2629, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2632[10] <= _T_2689 @[el2_lib.scala 263:30]
|
|
node _T_2690 = bits(_T_2629, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2634[11] <= _T_2690 @[el2_lib.scala 265:30]
|
|
node _T_2691 = bits(_T_2629, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2630[9] <= _T_2691 @[el2_lib.scala 261:30]
|
|
node _T_2692 = bits(_T_2629, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2631[9] <= _T_2692 @[el2_lib.scala 262:30]
|
|
node _T_2693 = bits(_T_2629, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2634[12] <= _T_2693 @[el2_lib.scala 265:30]
|
|
node _T_2694 = bits(_T_2629, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2631[10] <= _T_2694 @[el2_lib.scala 262:30]
|
|
node _T_2695 = bits(_T_2629, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2634[13] <= _T_2695 @[el2_lib.scala 265:30]
|
|
node _T_2696 = bits(_T_2629, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2630[10] <= _T_2696 @[el2_lib.scala 261:30]
|
|
node _T_2697 = bits(_T_2629, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2634[14] <= _T_2697 @[el2_lib.scala 265:30]
|
|
node _T_2698 = bits(_T_2629, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2630[11] <= _T_2698 @[el2_lib.scala 261:30]
|
|
node _T_2699 = bits(_T_2629, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2631[11] <= _T_2699 @[el2_lib.scala 262:30]
|
|
node _T_2700 = bits(_T_2629, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2632[11] <= _T_2700 @[el2_lib.scala 263:30]
|
|
node _T_2701 = bits(_T_2629, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2633[8] <= _T_2701 @[el2_lib.scala 264:30]
|
|
node _T_2702 = bits(_T_2629, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2631[12] <= _T_2702 @[el2_lib.scala 262:30]
|
|
node _T_2703 = bits(_T_2629, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2632[12] <= _T_2703 @[el2_lib.scala 263:30]
|
|
node _T_2704 = bits(_T_2629, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2633[9] <= _T_2704 @[el2_lib.scala 264:30]
|
|
node _T_2705 = bits(_T_2629, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2630[12] <= _T_2705 @[el2_lib.scala 261:30]
|
|
node _T_2706 = bits(_T_2629, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2632[13] <= _T_2706 @[el2_lib.scala 263:30]
|
|
node _T_2707 = bits(_T_2629, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2633[10] <= _T_2707 @[el2_lib.scala 264:30]
|
|
node _T_2708 = bits(_T_2629, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2632[14] <= _T_2708 @[el2_lib.scala 263:30]
|
|
node _T_2709 = bits(_T_2629, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2633[11] <= _T_2709 @[el2_lib.scala 264:30]
|
|
node _T_2710 = bits(_T_2629, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2630[13] <= _T_2710 @[el2_lib.scala 261:30]
|
|
node _T_2711 = bits(_T_2629, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2631[13] <= _T_2711 @[el2_lib.scala 262:30]
|
|
node _T_2712 = bits(_T_2629, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2633[12] <= _T_2712 @[el2_lib.scala 264:30]
|
|
node _T_2713 = bits(_T_2629, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2631[14] <= _T_2713 @[el2_lib.scala 262:30]
|
|
node _T_2714 = bits(_T_2629, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2633[13] <= _T_2714 @[el2_lib.scala 264:30]
|
|
node _T_2715 = bits(_T_2629, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2630[14] <= _T_2715 @[el2_lib.scala 261:30]
|
|
node _T_2716 = bits(_T_2629, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2633[14] <= _T_2716 @[el2_lib.scala 264:30]
|
|
node _T_2717 = bits(_T_2629, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2630[15] <= _T_2717 @[el2_lib.scala 261:30]
|
|
node _T_2718 = bits(_T_2629, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2631[15] <= _T_2718 @[el2_lib.scala 262:30]
|
|
node _T_2719 = bits(_T_2629, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2632[15] <= _T_2719 @[el2_lib.scala 263:30]
|
|
node _T_2720 = bits(_T_2629, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2631[16] <= _T_2720 @[el2_lib.scala 262:30]
|
|
node _T_2721 = bits(_T_2629, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2632[16] <= _T_2721 @[el2_lib.scala 263:30]
|
|
node _T_2722 = bits(_T_2629, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2630[16] <= _T_2722 @[el2_lib.scala 261:30]
|
|
node _T_2723 = bits(_T_2629, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2632[17] <= _T_2723 @[el2_lib.scala 263:30]
|
|
node _T_2724 = bits(_T_2629, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2630[17] <= _T_2724 @[el2_lib.scala 261:30]
|
|
node _T_2725 = bits(_T_2629, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2631[17] <= _T_2725 @[el2_lib.scala 262:30]
|
|
node _T_2726 = cat(_T_2630[1], _T_2630[0]) @[el2_lib.scala 268:22]
|
|
node _T_2727 = cat(_T_2630[3], _T_2630[2]) @[el2_lib.scala 268:22]
|
|
node _T_2728 = cat(_T_2727, _T_2726) @[el2_lib.scala 268:22]
|
|
node _T_2729 = cat(_T_2630[5], _T_2630[4]) @[el2_lib.scala 268:22]
|
|
node _T_2730 = cat(_T_2630[8], _T_2630[7]) @[el2_lib.scala 268:22]
|
|
node _T_2731 = cat(_T_2730, _T_2630[6]) @[el2_lib.scala 268:22]
|
|
node _T_2732 = cat(_T_2731, _T_2729) @[el2_lib.scala 268:22]
|
|
node _T_2733 = cat(_T_2732, _T_2728) @[el2_lib.scala 268:22]
|
|
node _T_2734 = cat(_T_2630[10], _T_2630[9]) @[el2_lib.scala 268:22]
|
|
node _T_2735 = cat(_T_2630[12], _T_2630[11]) @[el2_lib.scala 268:22]
|
|
node _T_2736 = cat(_T_2735, _T_2734) @[el2_lib.scala 268:22]
|
|
node _T_2737 = cat(_T_2630[14], _T_2630[13]) @[el2_lib.scala 268:22]
|
|
node _T_2738 = cat(_T_2630[17], _T_2630[16]) @[el2_lib.scala 268:22]
|
|
node _T_2739 = cat(_T_2738, _T_2630[15]) @[el2_lib.scala 268:22]
|
|
node _T_2740 = cat(_T_2739, _T_2737) @[el2_lib.scala 268:22]
|
|
node _T_2741 = cat(_T_2740, _T_2736) @[el2_lib.scala 268:22]
|
|
node _T_2742 = cat(_T_2741, _T_2733) @[el2_lib.scala 268:22]
|
|
node _T_2743 = xorr(_T_2742) @[el2_lib.scala 268:29]
|
|
node _T_2744 = cat(_T_2631[1], _T_2631[0]) @[el2_lib.scala 268:39]
|
|
node _T_2745 = cat(_T_2631[3], _T_2631[2]) @[el2_lib.scala 268:39]
|
|
node _T_2746 = cat(_T_2745, _T_2744) @[el2_lib.scala 268:39]
|
|
node _T_2747 = cat(_T_2631[5], _T_2631[4]) @[el2_lib.scala 268:39]
|
|
node _T_2748 = cat(_T_2631[8], _T_2631[7]) @[el2_lib.scala 268:39]
|
|
node _T_2749 = cat(_T_2748, _T_2631[6]) @[el2_lib.scala 268:39]
|
|
node _T_2750 = cat(_T_2749, _T_2747) @[el2_lib.scala 268:39]
|
|
node _T_2751 = cat(_T_2750, _T_2746) @[el2_lib.scala 268:39]
|
|
node _T_2752 = cat(_T_2631[10], _T_2631[9]) @[el2_lib.scala 268:39]
|
|
node _T_2753 = cat(_T_2631[12], _T_2631[11]) @[el2_lib.scala 268:39]
|
|
node _T_2754 = cat(_T_2753, _T_2752) @[el2_lib.scala 268:39]
|
|
node _T_2755 = cat(_T_2631[14], _T_2631[13]) @[el2_lib.scala 268:39]
|
|
node _T_2756 = cat(_T_2631[17], _T_2631[16]) @[el2_lib.scala 268:39]
|
|
node _T_2757 = cat(_T_2756, _T_2631[15]) @[el2_lib.scala 268:39]
|
|
node _T_2758 = cat(_T_2757, _T_2755) @[el2_lib.scala 268:39]
|
|
node _T_2759 = cat(_T_2758, _T_2754) @[el2_lib.scala 268:39]
|
|
node _T_2760 = cat(_T_2759, _T_2751) @[el2_lib.scala 268:39]
|
|
node _T_2761 = xorr(_T_2760) @[el2_lib.scala 268:46]
|
|
node _T_2762 = cat(_T_2632[1], _T_2632[0]) @[el2_lib.scala 268:56]
|
|
node _T_2763 = cat(_T_2632[3], _T_2632[2]) @[el2_lib.scala 268:56]
|
|
node _T_2764 = cat(_T_2763, _T_2762) @[el2_lib.scala 268:56]
|
|
node _T_2765 = cat(_T_2632[5], _T_2632[4]) @[el2_lib.scala 268:56]
|
|
node _T_2766 = cat(_T_2632[8], _T_2632[7]) @[el2_lib.scala 268:56]
|
|
node _T_2767 = cat(_T_2766, _T_2632[6]) @[el2_lib.scala 268:56]
|
|
node _T_2768 = cat(_T_2767, _T_2765) @[el2_lib.scala 268:56]
|
|
node _T_2769 = cat(_T_2768, _T_2764) @[el2_lib.scala 268:56]
|
|
node _T_2770 = cat(_T_2632[10], _T_2632[9]) @[el2_lib.scala 268:56]
|
|
node _T_2771 = cat(_T_2632[12], _T_2632[11]) @[el2_lib.scala 268:56]
|
|
node _T_2772 = cat(_T_2771, _T_2770) @[el2_lib.scala 268:56]
|
|
node _T_2773 = cat(_T_2632[14], _T_2632[13]) @[el2_lib.scala 268:56]
|
|
node _T_2774 = cat(_T_2632[17], _T_2632[16]) @[el2_lib.scala 268:56]
|
|
node _T_2775 = cat(_T_2774, _T_2632[15]) @[el2_lib.scala 268:56]
|
|
node _T_2776 = cat(_T_2775, _T_2773) @[el2_lib.scala 268:56]
|
|
node _T_2777 = cat(_T_2776, _T_2772) @[el2_lib.scala 268:56]
|
|
node _T_2778 = cat(_T_2777, _T_2769) @[el2_lib.scala 268:56]
|
|
node _T_2779 = xorr(_T_2778) @[el2_lib.scala 268:63]
|
|
node _T_2780 = cat(_T_2633[2], _T_2633[1]) @[el2_lib.scala 268:73]
|
|
node _T_2781 = cat(_T_2780, _T_2633[0]) @[el2_lib.scala 268:73]
|
|
node _T_2782 = cat(_T_2633[4], _T_2633[3]) @[el2_lib.scala 268:73]
|
|
node _T_2783 = cat(_T_2633[6], _T_2633[5]) @[el2_lib.scala 268:73]
|
|
node _T_2784 = cat(_T_2783, _T_2782) @[el2_lib.scala 268:73]
|
|
node _T_2785 = cat(_T_2784, _T_2781) @[el2_lib.scala 268:73]
|
|
node _T_2786 = cat(_T_2633[8], _T_2633[7]) @[el2_lib.scala 268:73]
|
|
node _T_2787 = cat(_T_2633[10], _T_2633[9]) @[el2_lib.scala 268:73]
|
|
node _T_2788 = cat(_T_2787, _T_2786) @[el2_lib.scala 268:73]
|
|
node _T_2789 = cat(_T_2633[12], _T_2633[11]) @[el2_lib.scala 268:73]
|
|
node _T_2790 = cat(_T_2633[14], _T_2633[13]) @[el2_lib.scala 268:73]
|
|
node _T_2791 = cat(_T_2790, _T_2789) @[el2_lib.scala 268:73]
|
|
node _T_2792 = cat(_T_2791, _T_2788) @[el2_lib.scala 268:73]
|
|
node _T_2793 = cat(_T_2792, _T_2785) @[el2_lib.scala 268:73]
|
|
node _T_2794 = xorr(_T_2793) @[el2_lib.scala 268:80]
|
|
node _T_2795 = cat(_T_2634[2], _T_2634[1]) @[el2_lib.scala 268:90]
|
|
node _T_2796 = cat(_T_2795, _T_2634[0]) @[el2_lib.scala 268:90]
|
|
node _T_2797 = cat(_T_2634[4], _T_2634[3]) @[el2_lib.scala 268:90]
|
|
node _T_2798 = cat(_T_2634[6], _T_2634[5]) @[el2_lib.scala 268:90]
|
|
node _T_2799 = cat(_T_2798, _T_2797) @[el2_lib.scala 268:90]
|
|
node _T_2800 = cat(_T_2799, _T_2796) @[el2_lib.scala 268:90]
|
|
node _T_2801 = cat(_T_2634[8], _T_2634[7]) @[el2_lib.scala 268:90]
|
|
node _T_2802 = cat(_T_2634[10], _T_2634[9]) @[el2_lib.scala 268:90]
|
|
node _T_2803 = cat(_T_2802, _T_2801) @[el2_lib.scala 268:90]
|
|
node _T_2804 = cat(_T_2634[12], _T_2634[11]) @[el2_lib.scala 268:90]
|
|
node _T_2805 = cat(_T_2634[14], _T_2634[13]) @[el2_lib.scala 268:90]
|
|
node _T_2806 = cat(_T_2805, _T_2804) @[el2_lib.scala 268:90]
|
|
node _T_2807 = cat(_T_2806, _T_2803) @[el2_lib.scala 268:90]
|
|
node _T_2808 = cat(_T_2807, _T_2800) @[el2_lib.scala 268:90]
|
|
node _T_2809 = xorr(_T_2808) @[el2_lib.scala 268:97]
|
|
node _T_2810 = cat(_T_2635[2], _T_2635[1]) @[el2_lib.scala 268:107]
|
|
node _T_2811 = cat(_T_2810, _T_2635[0]) @[el2_lib.scala 268:107]
|
|
node _T_2812 = cat(_T_2635[5], _T_2635[4]) @[el2_lib.scala 268:107]
|
|
node _T_2813 = cat(_T_2812, _T_2635[3]) @[el2_lib.scala 268:107]
|
|
node _T_2814 = cat(_T_2813, _T_2811) @[el2_lib.scala 268:107]
|
|
node _T_2815 = xorr(_T_2814) @[el2_lib.scala 268:114]
|
|
node _T_2816 = cat(_T_2794, _T_2809) @[Cat.scala 29:58]
|
|
node _T_2817 = cat(_T_2816, _T_2815) @[Cat.scala 29:58]
|
|
node _T_2818 = cat(_T_2743, _T_2761) @[Cat.scala 29:58]
|
|
node _T_2819 = cat(_T_2818, _T_2779) @[Cat.scala 29:58]
|
|
node _T_2820 = cat(_T_2819, _T_2817) @[Cat.scala 29:58]
|
|
node _T_2821 = xorr(_T_2629) @[el2_lib.scala 269:13]
|
|
node _T_2822 = xorr(_T_2820) @[el2_lib.scala 269:23]
|
|
node _T_2823 = xor(_T_2821, _T_2822) @[el2_lib.scala 269:18]
|
|
node _T_2824 = cat(_T_2823, _T_2820) @[Cat.scala 29:58]
|
|
node _T_2825 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 677:93]
|
|
wire _T_2826 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2827 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2828 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2829 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2830 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2831 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2832 = bits(_T_2825, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2827[0] <= _T_2832 @[el2_lib.scala 262:30]
|
|
node _T_2833 = bits(_T_2825, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2828[0] <= _T_2833 @[el2_lib.scala 263:30]
|
|
node _T_2834 = bits(_T_2825, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2831[0] <= _T_2834 @[el2_lib.scala 266:30]
|
|
node _T_2835 = bits(_T_2825, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2826[0] <= _T_2835 @[el2_lib.scala 261:30]
|
|
node _T_2836 = bits(_T_2825, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2828[1] <= _T_2836 @[el2_lib.scala 263:30]
|
|
node _T_2837 = bits(_T_2825, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2831[1] <= _T_2837 @[el2_lib.scala 266:30]
|
|
node _T_2838 = bits(_T_2825, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2828[2] <= _T_2838 @[el2_lib.scala 263:30]
|
|
node _T_2839 = bits(_T_2825, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2831[2] <= _T_2839 @[el2_lib.scala 266:30]
|
|
node _T_2840 = bits(_T_2825, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2826[1] <= _T_2840 @[el2_lib.scala 261:30]
|
|
node _T_2841 = bits(_T_2825, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2827[1] <= _T_2841 @[el2_lib.scala 262:30]
|
|
node _T_2842 = bits(_T_2825, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2831[3] <= _T_2842 @[el2_lib.scala 266:30]
|
|
node _T_2843 = bits(_T_2825, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2827[2] <= _T_2843 @[el2_lib.scala 262:30]
|
|
node _T_2844 = bits(_T_2825, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2831[4] <= _T_2844 @[el2_lib.scala 266:30]
|
|
node _T_2845 = bits(_T_2825, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2826[2] <= _T_2845 @[el2_lib.scala 261:30]
|
|
node _T_2846 = bits(_T_2825, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2831[5] <= _T_2846 @[el2_lib.scala 266:30]
|
|
node _T_2847 = bits(_T_2825, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2826[3] <= _T_2847 @[el2_lib.scala 261:30]
|
|
node _T_2848 = bits(_T_2825, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2827[3] <= _T_2848 @[el2_lib.scala 262:30]
|
|
node _T_2849 = bits(_T_2825, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2828[3] <= _T_2849 @[el2_lib.scala 263:30]
|
|
node _T_2850 = bits(_T_2825, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2829[0] <= _T_2850 @[el2_lib.scala 264:30]
|
|
node _T_2851 = bits(_T_2825, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2830[0] <= _T_2851 @[el2_lib.scala 265:30]
|
|
node _T_2852 = bits(_T_2825, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2827[4] <= _T_2852 @[el2_lib.scala 262:30]
|
|
node _T_2853 = bits(_T_2825, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2828[4] <= _T_2853 @[el2_lib.scala 263:30]
|
|
node _T_2854 = bits(_T_2825, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2829[1] <= _T_2854 @[el2_lib.scala 264:30]
|
|
node _T_2855 = bits(_T_2825, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2830[1] <= _T_2855 @[el2_lib.scala 265:30]
|
|
node _T_2856 = bits(_T_2825, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2826[4] <= _T_2856 @[el2_lib.scala 261:30]
|
|
node _T_2857 = bits(_T_2825, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2828[5] <= _T_2857 @[el2_lib.scala 263:30]
|
|
node _T_2858 = bits(_T_2825, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2829[2] <= _T_2858 @[el2_lib.scala 264:30]
|
|
node _T_2859 = bits(_T_2825, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2830[2] <= _T_2859 @[el2_lib.scala 265:30]
|
|
node _T_2860 = bits(_T_2825, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2828[6] <= _T_2860 @[el2_lib.scala 263:30]
|
|
node _T_2861 = bits(_T_2825, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2829[3] <= _T_2861 @[el2_lib.scala 264:30]
|
|
node _T_2862 = bits(_T_2825, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2830[3] <= _T_2862 @[el2_lib.scala 265:30]
|
|
node _T_2863 = bits(_T_2825, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2826[5] <= _T_2863 @[el2_lib.scala 261:30]
|
|
node _T_2864 = bits(_T_2825, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2827[5] <= _T_2864 @[el2_lib.scala 262:30]
|
|
node _T_2865 = bits(_T_2825, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2829[4] <= _T_2865 @[el2_lib.scala 264:30]
|
|
node _T_2866 = bits(_T_2825, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2830[4] <= _T_2866 @[el2_lib.scala 265:30]
|
|
node _T_2867 = bits(_T_2825, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2827[6] <= _T_2867 @[el2_lib.scala 262:30]
|
|
node _T_2868 = bits(_T_2825, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2829[5] <= _T_2868 @[el2_lib.scala 264:30]
|
|
node _T_2869 = bits(_T_2825, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2830[5] <= _T_2869 @[el2_lib.scala 265:30]
|
|
node _T_2870 = bits(_T_2825, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2826[6] <= _T_2870 @[el2_lib.scala 261:30]
|
|
node _T_2871 = bits(_T_2825, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2829[6] <= _T_2871 @[el2_lib.scala 264:30]
|
|
node _T_2872 = bits(_T_2825, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2830[6] <= _T_2872 @[el2_lib.scala 265:30]
|
|
node _T_2873 = bits(_T_2825, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2829[7] <= _T_2873 @[el2_lib.scala 264:30]
|
|
node _T_2874 = bits(_T_2825, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2830[7] <= _T_2874 @[el2_lib.scala 265:30]
|
|
node _T_2875 = bits(_T_2825, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2826[7] <= _T_2875 @[el2_lib.scala 261:30]
|
|
node _T_2876 = bits(_T_2825, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2827[7] <= _T_2876 @[el2_lib.scala 262:30]
|
|
node _T_2877 = bits(_T_2825, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2828[7] <= _T_2877 @[el2_lib.scala 263:30]
|
|
node _T_2878 = bits(_T_2825, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2830[8] <= _T_2878 @[el2_lib.scala 265:30]
|
|
node _T_2879 = bits(_T_2825, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2827[8] <= _T_2879 @[el2_lib.scala 262:30]
|
|
node _T_2880 = bits(_T_2825, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2828[8] <= _T_2880 @[el2_lib.scala 263:30]
|
|
node _T_2881 = bits(_T_2825, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2830[9] <= _T_2881 @[el2_lib.scala 265:30]
|
|
node _T_2882 = bits(_T_2825, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2826[8] <= _T_2882 @[el2_lib.scala 261:30]
|
|
node _T_2883 = bits(_T_2825, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2828[9] <= _T_2883 @[el2_lib.scala 263:30]
|
|
node _T_2884 = bits(_T_2825, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2830[10] <= _T_2884 @[el2_lib.scala 265:30]
|
|
node _T_2885 = bits(_T_2825, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2828[10] <= _T_2885 @[el2_lib.scala 263:30]
|
|
node _T_2886 = bits(_T_2825, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2830[11] <= _T_2886 @[el2_lib.scala 265:30]
|
|
node _T_2887 = bits(_T_2825, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2826[9] <= _T_2887 @[el2_lib.scala 261:30]
|
|
node _T_2888 = bits(_T_2825, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2827[9] <= _T_2888 @[el2_lib.scala 262:30]
|
|
node _T_2889 = bits(_T_2825, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2830[12] <= _T_2889 @[el2_lib.scala 265:30]
|
|
node _T_2890 = bits(_T_2825, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2827[10] <= _T_2890 @[el2_lib.scala 262:30]
|
|
node _T_2891 = bits(_T_2825, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2830[13] <= _T_2891 @[el2_lib.scala 265:30]
|
|
node _T_2892 = bits(_T_2825, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2826[10] <= _T_2892 @[el2_lib.scala 261:30]
|
|
node _T_2893 = bits(_T_2825, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2830[14] <= _T_2893 @[el2_lib.scala 265:30]
|
|
node _T_2894 = bits(_T_2825, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2826[11] <= _T_2894 @[el2_lib.scala 261:30]
|
|
node _T_2895 = bits(_T_2825, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2827[11] <= _T_2895 @[el2_lib.scala 262:30]
|
|
node _T_2896 = bits(_T_2825, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2828[11] <= _T_2896 @[el2_lib.scala 263:30]
|
|
node _T_2897 = bits(_T_2825, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2829[8] <= _T_2897 @[el2_lib.scala 264:30]
|
|
node _T_2898 = bits(_T_2825, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2827[12] <= _T_2898 @[el2_lib.scala 262:30]
|
|
node _T_2899 = bits(_T_2825, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2828[12] <= _T_2899 @[el2_lib.scala 263:30]
|
|
node _T_2900 = bits(_T_2825, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2829[9] <= _T_2900 @[el2_lib.scala 264:30]
|
|
node _T_2901 = bits(_T_2825, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2826[12] <= _T_2901 @[el2_lib.scala 261:30]
|
|
node _T_2902 = bits(_T_2825, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2828[13] <= _T_2902 @[el2_lib.scala 263:30]
|
|
node _T_2903 = bits(_T_2825, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2829[10] <= _T_2903 @[el2_lib.scala 264:30]
|
|
node _T_2904 = bits(_T_2825, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2828[14] <= _T_2904 @[el2_lib.scala 263:30]
|
|
node _T_2905 = bits(_T_2825, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2829[11] <= _T_2905 @[el2_lib.scala 264:30]
|
|
node _T_2906 = bits(_T_2825, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2826[13] <= _T_2906 @[el2_lib.scala 261:30]
|
|
node _T_2907 = bits(_T_2825, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2827[13] <= _T_2907 @[el2_lib.scala 262:30]
|
|
node _T_2908 = bits(_T_2825, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2829[12] <= _T_2908 @[el2_lib.scala 264:30]
|
|
node _T_2909 = bits(_T_2825, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2827[14] <= _T_2909 @[el2_lib.scala 262:30]
|
|
node _T_2910 = bits(_T_2825, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2829[13] <= _T_2910 @[el2_lib.scala 264:30]
|
|
node _T_2911 = bits(_T_2825, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2826[14] <= _T_2911 @[el2_lib.scala 261:30]
|
|
node _T_2912 = bits(_T_2825, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2829[14] <= _T_2912 @[el2_lib.scala 264:30]
|
|
node _T_2913 = bits(_T_2825, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2826[15] <= _T_2913 @[el2_lib.scala 261:30]
|
|
node _T_2914 = bits(_T_2825, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2827[15] <= _T_2914 @[el2_lib.scala 262:30]
|
|
node _T_2915 = bits(_T_2825, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2828[15] <= _T_2915 @[el2_lib.scala 263:30]
|
|
node _T_2916 = bits(_T_2825, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2827[16] <= _T_2916 @[el2_lib.scala 262:30]
|
|
node _T_2917 = bits(_T_2825, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2828[16] <= _T_2917 @[el2_lib.scala 263:30]
|
|
node _T_2918 = bits(_T_2825, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2826[16] <= _T_2918 @[el2_lib.scala 261:30]
|
|
node _T_2919 = bits(_T_2825, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2828[17] <= _T_2919 @[el2_lib.scala 263:30]
|
|
node _T_2920 = bits(_T_2825, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2826[17] <= _T_2920 @[el2_lib.scala 261:30]
|
|
node _T_2921 = bits(_T_2825, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2827[17] <= _T_2921 @[el2_lib.scala 262:30]
|
|
node _T_2922 = cat(_T_2826[1], _T_2826[0]) @[el2_lib.scala 268:22]
|
|
node _T_2923 = cat(_T_2826[3], _T_2826[2]) @[el2_lib.scala 268:22]
|
|
node _T_2924 = cat(_T_2923, _T_2922) @[el2_lib.scala 268:22]
|
|
node _T_2925 = cat(_T_2826[5], _T_2826[4]) @[el2_lib.scala 268:22]
|
|
node _T_2926 = cat(_T_2826[8], _T_2826[7]) @[el2_lib.scala 268:22]
|
|
node _T_2927 = cat(_T_2926, _T_2826[6]) @[el2_lib.scala 268:22]
|
|
node _T_2928 = cat(_T_2927, _T_2925) @[el2_lib.scala 268:22]
|
|
node _T_2929 = cat(_T_2928, _T_2924) @[el2_lib.scala 268:22]
|
|
node _T_2930 = cat(_T_2826[10], _T_2826[9]) @[el2_lib.scala 268:22]
|
|
node _T_2931 = cat(_T_2826[12], _T_2826[11]) @[el2_lib.scala 268:22]
|
|
node _T_2932 = cat(_T_2931, _T_2930) @[el2_lib.scala 268:22]
|
|
node _T_2933 = cat(_T_2826[14], _T_2826[13]) @[el2_lib.scala 268:22]
|
|
node _T_2934 = cat(_T_2826[17], _T_2826[16]) @[el2_lib.scala 268:22]
|
|
node _T_2935 = cat(_T_2934, _T_2826[15]) @[el2_lib.scala 268:22]
|
|
node _T_2936 = cat(_T_2935, _T_2933) @[el2_lib.scala 268:22]
|
|
node _T_2937 = cat(_T_2936, _T_2932) @[el2_lib.scala 268:22]
|
|
node _T_2938 = cat(_T_2937, _T_2929) @[el2_lib.scala 268:22]
|
|
node _T_2939 = xorr(_T_2938) @[el2_lib.scala 268:29]
|
|
node _T_2940 = cat(_T_2827[1], _T_2827[0]) @[el2_lib.scala 268:39]
|
|
node _T_2941 = cat(_T_2827[3], _T_2827[2]) @[el2_lib.scala 268:39]
|
|
node _T_2942 = cat(_T_2941, _T_2940) @[el2_lib.scala 268:39]
|
|
node _T_2943 = cat(_T_2827[5], _T_2827[4]) @[el2_lib.scala 268:39]
|
|
node _T_2944 = cat(_T_2827[8], _T_2827[7]) @[el2_lib.scala 268:39]
|
|
node _T_2945 = cat(_T_2944, _T_2827[6]) @[el2_lib.scala 268:39]
|
|
node _T_2946 = cat(_T_2945, _T_2943) @[el2_lib.scala 268:39]
|
|
node _T_2947 = cat(_T_2946, _T_2942) @[el2_lib.scala 268:39]
|
|
node _T_2948 = cat(_T_2827[10], _T_2827[9]) @[el2_lib.scala 268:39]
|
|
node _T_2949 = cat(_T_2827[12], _T_2827[11]) @[el2_lib.scala 268:39]
|
|
node _T_2950 = cat(_T_2949, _T_2948) @[el2_lib.scala 268:39]
|
|
node _T_2951 = cat(_T_2827[14], _T_2827[13]) @[el2_lib.scala 268:39]
|
|
node _T_2952 = cat(_T_2827[17], _T_2827[16]) @[el2_lib.scala 268:39]
|
|
node _T_2953 = cat(_T_2952, _T_2827[15]) @[el2_lib.scala 268:39]
|
|
node _T_2954 = cat(_T_2953, _T_2951) @[el2_lib.scala 268:39]
|
|
node _T_2955 = cat(_T_2954, _T_2950) @[el2_lib.scala 268:39]
|
|
node _T_2956 = cat(_T_2955, _T_2947) @[el2_lib.scala 268:39]
|
|
node _T_2957 = xorr(_T_2956) @[el2_lib.scala 268:46]
|
|
node _T_2958 = cat(_T_2828[1], _T_2828[0]) @[el2_lib.scala 268:56]
|
|
node _T_2959 = cat(_T_2828[3], _T_2828[2]) @[el2_lib.scala 268:56]
|
|
node _T_2960 = cat(_T_2959, _T_2958) @[el2_lib.scala 268:56]
|
|
node _T_2961 = cat(_T_2828[5], _T_2828[4]) @[el2_lib.scala 268:56]
|
|
node _T_2962 = cat(_T_2828[8], _T_2828[7]) @[el2_lib.scala 268:56]
|
|
node _T_2963 = cat(_T_2962, _T_2828[6]) @[el2_lib.scala 268:56]
|
|
node _T_2964 = cat(_T_2963, _T_2961) @[el2_lib.scala 268:56]
|
|
node _T_2965 = cat(_T_2964, _T_2960) @[el2_lib.scala 268:56]
|
|
node _T_2966 = cat(_T_2828[10], _T_2828[9]) @[el2_lib.scala 268:56]
|
|
node _T_2967 = cat(_T_2828[12], _T_2828[11]) @[el2_lib.scala 268:56]
|
|
node _T_2968 = cat(_T_2967, _T_2966) @[el2_lib.scala 268:56]
|
|
node _T_2969 = cat(_T_2828[14], _T_2828[13]) @[el2_lib.scala 268:56]
|
|
node _T_2970 = cat(_T_2828[17], _T_2828[16]) @[el2_lib.scala 268:56]
|
|
node _T_2971 = cat(_T_2970, _T_2828[15]) @[el2_lib.scala 268:56]
|
|
node _T_2972 = cat(_T_2971, _T_2969) @[el2_lib.scala 268:56]
|
|
node _T_2973 = cat(_T_2972, _T_2968) @[el2_lib.scala 268:56]
|
|
node _T_2974 = cat(_T_2973, _T_2965) @[el2_lib.scala 268:56]
|
|
node _T_2975 = xorr(_T_2974) @[el2_lib.scala 268:63]
|
|
node _T_2976 = cat(_T_2829[2], _T_2829[1]) @[el2_lib.scala 268:73]
|
|
node _T_2977 = cat(_T_2976, _T_2829[0]) @[el2_lib.scala 268:73]
|
|
node _T_2978 = cat(_T_2829[4], _T_2829[3]) @[el2_lib.scala 268:73]
|
|
node _T_2979 = cat(_T_2829[6], _T_2829[5]) @[el2_lib.scala 268:73]
|
|
node _T_2980 = cat(_T_2979, _T_2978) @[el2_lib.scala 268:73]
|
|
node _T_2981 = cat(_T_2980, _T_2977) @[el2_lib.scala 268:73]
|
|
node _T_2982 = cat(_T_2829[8], _T_2829[7]) @[el2_lib.scala 268:73]
|
|
node _T_2983 = cat(_T_2829[10], _T_2829[9]) @[el2_lib.scala 268:73]
|
|
node _T_2984 = cat(_T_2983, _T_2982) @[el2_lib.scala 268:73]
|
|
node _T_2985 = cat(_T_2829[12], _T_2829[11]) @[el2_lib.scala 268:73]
|
|
node _T_2986 = cat(_T_2829[14], _T_2829[13]) @[el2_lib.scala 268:73]
|
|
node _T_2987 = cat(_T_2986, _T_2985) @[el2_lib.scala 268:73]
|
|
node _T_2988 = cat(_T_2987, _T_2984) @[el2_lib.scala 268:73]
|
|
node _T_2989 = cat(_T_2988, _T_2981) @[el2_lib.scala 268:73]
|
|
node _T_2990 = xorr(_T_2989) @[el2_lib.scala 268:80]
|
|
node _T_2991 = cat(_T_2830[2], _T_2830[1]) @[el2_lib.scala 268:90]
|
|
node _T_2992 = cat(_T_2991, _T_2830[0]) @[el2_lib.scala 268:90]
|
|
node _T_2993 = cat(_T_2830[4], _T_2830[3]) @[el2_lib.scala 268:90]
|
|
node _T_2994 = cat(_T_2830[6], _T_2830[5]) @[el2_lib.scala 268:90]
|
|
node _T_2995 = cat(_T_2994, _T_2993) @[el2_lib.scala 268:90]
|
|
node _T_2996 = cat(_T_2995, _T_2992) @[el2_lib.scala 268:90]
|
|
node _T_2997 = cat(_T_2830[8], _T_2830[7]) @[el2_lib.scala 268:90]
|
|
node _T_2998 = cat(_T_2830[10], _T_2830[9]) @[el2_lib.scala 268:90]
|
|
node _T_2999 = cat(_T_2998, _T_2997) @[el2_lib.scala 268:90]
|
|
node _T_3000 = cat(_T_2830[12], _T_2830[11]) @[el2_lib.scala 268:90]
|
|
node _T_3001 = cat(_T_2830[14], _T_2830[13]) @[el2_lib.scala 268:90]
|
|
node _T_3002 = cat(_T_3001, _T_3000) @[el2_lib.scala 268:90]
|
|
node _T_3003 = cat(_T_3002, _T_2999) @[el2_lib.scala 268:90]
|
|
node _T_3004 = cat(_T_3003, _T_2996) @[el2_lib.scala 268:90]
|
|
node _T_3005 = xorr(_T_3004) @[el2_lib.scala 268:97]
|
|
node _T_3006 = cat(_T_2831[2], _T_2831[1]) @[el2_lib.scala 268:107]
|
|
node _T_3007 = cat(_T_3006, _T_2831[0]) @[el2_lib.scala 268:107]
|
|
node _T_3008 = cat(_T_2831[5], _T_2831[4]) @[el2_lib.scala 268:107]
|
|
node _T_3009 = cat(_T_3008, _T_2831[3]) @[el2_lib.scala 268:107]
|
|
node _T_3010 = cat(_T_3009, _T_3007) @[el2_lib.scala 268:107]
|
|
node _T_3011 = xorr(_T_3010) @[el2_lib.scala 268:114]
|
|
node _T_3012 = cat(_T_2990, _T_3005) @[Cat.scala 29:58]
|
|
node _T_3013 = cat(_T_3012, _T_3011) @[Cat.scala 29:58]
|
|
node _T_3014 = cat(_T_2939, _T_2957) @[Cat.scala 29:58]
|
|
node _T_3015 = cat(_T_3014, _T_2975) @[Cat.scala 29:58]
|
|
node _T_3016 = cat(_T_3015, _T_3013) @[Cat.scala 29:58]
|
|
node _T_3017 = xorr(_T_2825) @[el2_lib.scala 269:13]
|
|
node _T_3018 = xorr(_T_3016) @[el2_lib.scala 269:23]
|
|
node _T_3019 = xor(_T_3017, _T_3018) @[el2_lib.scala 269:18]
|
|
node _T_3020 = cat(_T_3019, _T_3016) @[Cat.scala 29:58]
|
|
node dma_mem_ecc = cat(_T_2824, _T_3020) @[Cat.scala 29:58]
|
|
wire iccm_ecc_corr_data_ff : UInt<39>
|
|
iccm_ecc_corr_data_ff <= UInt<1>("h00")
|
|
node _T_3021 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 679:67]
|
|
node _T_3022 = eq(_T_3021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 679:45]
|
|
node _T_3023 = and(iccm_correct_ecc, _T_3022) @[el2_ifu_mem_ctl.scala 679:43]
|
|
node _T_3024 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58]
|
|
node _T_3025 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 680:20]
|
|
node _T_3026 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 680:43]
|
|
node _T_3027 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 680:63]
|
|
node _T_3028 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 680:86]
|
|
node _T_3029 = cat(_T_3027, _T_3028) @[Cat.scala 29:58]
|
|
node _T_3030 = cat(_T_3025, _T_3026) @[Cat.scala 29:58]
|
|
node _T_3031 = cat(_T_3030, _T_3029) @[Cat.scala 29:58]
|
|
node _T_3032 = mux(_T_3023, _T_3024, _T_3031) @[el2_ifu_mem_ctl.scala 679:25]
|
|
io.iccm_wr_data <= _T_3032 @[el2_ifu_mem_ctl.scala 679:19]
|
|
wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 681:33]
|
|
iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 682:26]
|
|
iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 683:26]
|
|
wire dma_mem_addr_ff : UInt<2>
|
|
dma_mem_addr_ff <= UInt<1>("h00")
|
|
node _T_3033 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 685:51]
|
|
node _T_3034 = bits(_T_3033, 0, 0) @[el2_ifu_mem_ctl.scala 685:55]
|
|
node iccm_dma_rdata_1_muxed = mux(_T_3034, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 685:35]
|
|
wire iccm_double_ecc_error : UInt<2>
|
|
iccm_double_ecc_error <= UInt<1>("h00")
|
|
node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 687:53]
|
|
node _T_3035 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58]
|
|
node _T_3036 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58]
|
|
node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3035, _T_3036) @[el2_ifu_mem_ctl.scala 688:30]
|
|
reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 689:54]
|
|
dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 689:54]
|
|
reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 690:69]
|
|
iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 690:69]
|
|
io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 691:20]
|
|
node _T_3037 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 693:69]
|
|
reg _T_3038 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 693:53]
|
|
_T_3038 <= _T_3037 @[el2_ifu_mem_ctl.scala 693:53]
|
|
dma_mem_addr_ff <= _T_3038 @[el2_ifu_mem_ctl.scala 693:19]
|
|
reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 694:59]
|
|
iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 694:59]
|
|
reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 695:71]
|
|
iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 695:71]
|
|
io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 696:22]
|
|
reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 697:74]
|
|
iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 697:74]
|
|
io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 698:25]
|
|
reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 699:70]
|
|
iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 699:70]
|
|
io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 700:21]
|
|
wire iccm_ecc_corr_index_ff : UInt<14>
|
|
iccm_ecc_corr_index_ff <= UInt<1>("h00")
|
|
node _T_3039 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 702:46]
|
|
node _T_3040 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 702:67]
|
|
node _T_3041 = and(_T_3039, _T_3040) @[el2_ifu_mem_ctl.scala 702:65]
|
|
node _T_3042 = and(iccm_ready, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 703:31]
|
|
node _T_3043 = eq(_T_3042, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:9]
|
|
node _T_3044 = and(_T_3043, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 703:50]
|
|
node _T_3045 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_3046 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 703:124]
|
|
node _T_3047 = mux(_T_3044, _T_3045, _T_3046) @[el2_ifu_mem_ctl.scala 703:8]
|
|
node _T_3048 = mux(_T_3041, io.dma_mem_addr, _T_3047) @[el2_ifu_mem_ctl.scala 702:25]
|
|
io.iccm_rw_addr <= _T_3048 @[el2_ifu_mem_ctl.scala 702:19]
|
|
node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58]
|
|
node _T_3049 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 705:76]
|
|
node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3049) @[el2_ifu_mem_ctl.scala 705:53]
|
|
node _T_3050 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 708:75]
|
|
node _T_3051 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:93]
|
|
node _T_3052 = and(_T_3050, _T_3051) @[el2_ifu_mem_ctl.scala 708:91]
|
|
node _T_3053 = and(_T_3052, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 708:113]
|
|
node _T_3054 = or(_T_3053, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 708:130]
|
|
node _T_3055 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:154]
|
|
node _T_3056 = and(_T_3054, _T_3055) @[el2_ifu_mem_ctl.scala 708:152]
|
|
node _T_3057 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 708:75]
|
|
node _T_3058 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:93]
|
|
node _T_3059 = and(_T_3057, _T_3058) @[el2_ifu_mem_ctl.scala 708:91]
|
|
node _T_3060 = and(_T_3059, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 708:113]
|
|
node _T_3061 = or(_T_3060, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 708:130]
|
|
node _T_3062 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 708:154]
|
|
node _T_3063 = and(_T_3061, _T_3062) @[el2_ifu_mem_ctl.scala 708:152]
|
|
node iccm_ecc_word_enable = cat(_T_3063, _T_3056) @[Cat.scala 29:58]
|
|
node _T_3064 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 709:73]
|
|
node _T_3065 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 709:93]
|
|
node _T_3066 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 709:128]
|
|
wire _T_3067 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3068 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3069 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3070 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3071 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3072 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3073 = bits(_T_3065, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3067[0] <= _T_3073 @[el2_lib.scala 293:30]
|
|
node _T_3074 = bits(_T_3065, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3068[0] <= _T_3074 @[el2_lib.scala 294:30]
|
|
node _T_3075 = bits(_T_3065, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3067[1] <= _T_3075 @[el2_lib.scala 293:30]
|
|
node _T_3076 = bits(_T_3065, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3069[0] <= _T_3076 @[el2_lib.scala 295:30]
|
|
node _T_3077 = bits(_T_3065, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3068[1] <= _T_3077 @[el2_lib.scala 294:30]
|
|
node _T_3078 = bits(_T_3065, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3069[1] <= _T_3078 @[el2_lib.scala 295:30]
|
|
node _T_3079 = bits(_T_3065, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3067[2] <= _T_3079 @[el2_lib.scala 293:30]
|
|
node _T_3080 = bits(_T_3065, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3068[2] <= _T_3080 @[el2_lib.scala 294:30]
|
|
node _T_3081 = bits(_T_3065, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3069[2] <= _T_3081 @[el2_lib.scala 295:30]
|
|
node _T_3082 = bits(_T_3065, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3067[3] <= _T_3082 @[el2_lib.scala 293:30]
|
|
node _T_3083 = bits(_T_3065, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3070[0] <= _T_3083 @[el2_lib.scala 296:30]
|
|
node _T_3084 = bits(_T_3065, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3068[3] <= _T_3084 @[el2_lib.scala 294:30]
|
|
node _T_3085 = bits(_T_3065, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3070[1] <= _T_3085 @[el2_lib.scala 296:30]
|
|
node _T_3086 = bits(_T_3065, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3067[4] <= _T_3086 @[el2_lib.scala 293:30]
|
|
node _T_3087 = bits(_T_3065, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3068[4] <= _T_3087 @[el2_lib.scala 294:30]
|
|
node _T_3088 = bits(_T_3065, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3070[2] <= _T_3088 @[el2_lib.scala 296:30]
|
|
node _T_3089 = bits(_T_3065, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3069[3] <= _T_3089 @[el2_lib.scala 295:30]
|
|
node _T_3090 = bits(_T_3065, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3070[3] <= _T_3090 @[el2_lib.scala 296:30]
|
|
node _T_3091 = bits(_T_3065, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3067[5] <= _T_3091 @[el2_lib.scala 293:30]
|
|
node _T_3092 = bits(_T_3065, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3069[4] <= _T_3092 @[el2_lib.scala 295:30]
|
|
node _T_3093 = bits(_T_3065, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3070[4] <= _T_3093 @[el2_lib.scala 296:30]
|
|
node _T_3094 = bits(_T_3065, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3068[5] <= _T_3094 @[el2_lib.scala 294:30]
|
|
node _T_3095 = bits(_T_3065, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3069[5] <= _T_3095 @[el2_lib.scala 295:30]
|
|
node _T_3096 = bits(_T_3065, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3070[5] <= _T_3096 @[el2_lib.scala 296:30]
|
|
node _T_3097 = bits(_T_3065, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3067[6] <= _T_3097 @[el2_lib.scala 293:30]
|
|
node _T_3098 = bits(_T_3065, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3068[6] <= _T_3098 @[el2_lib.scala 294:30]
|
|
node _T_3099 = bits(_T_3065, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3069[6] <= _T_3099 @[el2_lib.scala 295:30]
|
|
node _T_3100 = bits(_T_3065, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3070[6] <= _T_3100 @[el2_lib.scala 296:30]
|
|
node _T_3101 = bits(_T_3065, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3067[7] <= _T_3101 @[el2_lib.scala 293:30]
|
|
node _T_3102 = bits(_T_3065, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3071[0] <= _T_3102 @[el2_lib.scala 297:30]
|
|
node _T_3103 = bits(_T_3065, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3068[7] <= _T_3103 @[el2_lib.scala 294:30]
|
|
node _T_3104 = bits(_T_3065, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3071[1] <= _T_3104 @[el2_lib.scala 297:30]
|
|
node _T_3105 = bits(_T_3065, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3067[8] <= _T_3105 @[el2_lib.scala 293:30]
|
|
node _T_3106 = bits(_T_3065, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3068[8] <= _T_3106 @[el2_lib.scala 294:30]
|
|
node _T_3107 = bits(_T_3065, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3071[2] <= _T_3107 @[el2_lib.scala 297:30]
|
|
node _T_3108 = bits(_T_3065, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3069[7] <= _T_3108 @[el2_lib.scala 295:30]
|
|
node _T_3109 = bits(_T_3065, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3071[3] <= _T_3109 @[el2_lib.scala 297:30]
|
|
node _T_3110 = bits(_T_3065, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3067[9] <= _T_3110 @[el2_lib.scala 293:30]
|
|
node _T_3111 = bits(_T_3065, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3069[8] <= _T_3111 @[el2_lib.scala 295:30]
|
|
node _T_3112 = bits(_T_3065, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3071[4] <= _T_3112 @[el2_lib.scala 297:30]
|
|
node _T_3113 = bits(_T_3065, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3068[9] <= _T_3113 @[el2_lib.scala 294:30]
|
|
node _T_3114 = bits(_T_3065, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3069[9] <= _T_3114 @[el2_lib.scala 295:30]
|
|
node _T_3115 = bits(_T_3065, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3071[5] <= _T_3115 @[el2_lib.scala 297:30]
|
|
node _T_3116 = bits(_T_3065, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3067[10] <= _T_3116 @[el2_lib.scala 293:30]
|
|
node _T_3117 = bits(_T_3065, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3068[10] <= _T_3117 @[el2_lib.scala 294:30]
|
|
node _T_3118 = bits(_T_3065, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3069[10] <= _T_3118 @[el2_lib.scala 295:30]
|
|
node _T_3119 = bits(_T_3065, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3071[6] <= _T_3119 @[el2_lib.scala 297:30]
|
|
node _T_3120 = bits(_T_3065, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3070[7] <= _T_3120 @[el2_lib.scala 296:30]
|
|
node _T_3121 = bits(_T_3065, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3071[7] <= _T_3121 @[el2_lib.scala 297:30]
|
|
node _T_3122 = bits(_T_3065, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3067[11] <= _T_3122 @[el2_lib.scala 293:30]
|
|
node _T_3123 = bits(_T_3065, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3070[8] <= _T_3123 @[el2_lib.scala 296:30]
|
|
node _T_3124 = bits(_T_3065, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3071[8] <= _T_3124 @[el2_lib.scala 297:30]
|
|
node _T_3125 = bits(_T_3065, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3068[11] <= _T_3125 @[el2_lib.scala 294:30]
|
|
node _T_3126 = bits(_T_3065, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3070[9] <= _T_3126 @[el2_lib.scala 296:30]
|
|
node _T_3127 = bits(_T_3065, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3071[9] <= _T_3127 @[el2_lib.scala 297:30]
|
|
node _T_3128 = bits(_T_3065, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3067[12] <= _T_3128 @[el2_lib.scala 293:30]
|
|
node _T_3129 = bits(_T_3065, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3068[12] <= _T_3129 @[el2_lib.scala 294:30]
|
|
node _T_3130 = bits(_T_3065, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3070[10] <= _T_3130 @[el2_lib.scala 296:30]
|
|
node _T_3131 = bits(_T_3065, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3071[10] <= _T_3131 @[el2_lib.scala 297:30]
|
|
node _T_3132 = bits(_T_3065, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3069[11] <= _T_3132 @[el2_lib.scala 295:30]
|
|
node _T_3133 = bits(_T_3065, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3070[11] <= _T_3133 @[el2_lib.scala 296:30]
|
|
node _T_3134 = bits(_T_3065, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3071[11] <= _T_3134 @[el2_lib.scala 297:30]
|
|
node _T_3135 = bits(_T_3065, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3067[13] <= _T_3135 @[el2_lib.scala 293:30]
|
|
node _T_3136 = bits(_T_3065, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3069[12] <= _T_3136 @[el2_lib.scala 295:30]
|
|
node _T_3137 = bits(_T_3065, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3070[12] <= _T_3137 @[el2_lib.scala 296:30]
|
|
node _T_3138 = bits(_T_3065, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3071[12] <= _T_3138 @[el2_lib.scala 297:30]
|
|
node _T_3139 = bits(_T_3065, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3068[13] <= _T_3139 @[el2_lib.scala 294:30]
|
|
node _T_3140 = bits(_T_3065, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3069[13] <= _T_3140 @[el2_lib.scala 295:30]
|
|
node _T_3141 = bits(_T_3065, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3070[13] <= _T_3141 @[el2_lib.scala 296:30]
|
|
node _T_3142 = bits(_T_3065, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3071[13] <= _T_3142 @[el2_lib.scala 297:30]
|
|
node _T_3143 = bits(_T_3065, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3067[14] <= _T_3143 @[el2_lib.scala 293:30]
|
|
node _T_3144 = bits(_T_3065, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3068[14] <= _T_3144 @[el2_lib.scala 294:30]
|
|
node _T_3145 = bits(_T_3065, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3069[14] <= _T_3145 @[el2_lib.scala 295:30]
|
|
node _T_3146 = bits(_T_3065, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3070[14] <= _T_3146 @[el2_lib.scala 296:30]
|
|
node _T_3147 = bits(_T_3065, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3071[14] <= _T_3147 @[el2_lib.scala 297:30]
|
|
node _T_3148 = bits(_T_3065, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3067[15] <= _T_3148 @[el2_lib.scala 293:30]
|
|
node _T_3149 = bits(_T_3065, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3072[0] <= _T_3149 @[el2_lib.scala 298:30]
|
|
node _T_3150 = bits(_T_3065, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3068[15] <= _T_3150 @[el2_lib.scala 294:30]
|
|
node _T_3151 = bits(_T_3065, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3072[1] <= _T_3151 @[el2_lib.scala 298:30]
|
|
node _T_3152 = bits(_T_3065, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3067[16] <= _T_3152 @[el2_lib.scala 293:30]
|
|
node _T_3153 = bits(_T_3065, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3068[16] <= _T_3153 @[el2_lib.scala 294:30]
|
|
node _T_3154 = bits(_T_3065, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3072[2] <= _T_3154 @[el2_lib.scala 298:30]
|
|
node _T_3155 = bits(_T_3065, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3069[15] <= _T_3155 @[el2_lib.scala 295:30]
|
|
node _T_3156 = bits(_T_3065, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3072[3] <= _T_3156 @[el2_lib.scala 298:30]
|
|
node _T_3157 = bits(_T_3065, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3067[17] <= _T_3157 @[el2_lib.scala 293:30]
|
|
node _T_3158 = bits(_T_3065, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3069[16] <= _T_3158 @[el2_lib.scala 295:30]
|
|
node _T_3159 = bits(_T_3065, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3072[4] <= _T_3159 @[el2_lib.scala 298:30]
|
|
node _T_3160 = bits(_T_3065, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3068[17] <= _T_3160 @[el2_lib.scala 294:30]
|
|
node _T_3161 = bits(_T_3065, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3069[17] <= _T_3161 @[el2_lib.scala 295:30]
|
|
node _T_3162 = bits(_T_3065, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3072[5] <= _T_3162 @[el2_lib.scala 298:30]
|
|
node _T_3163 = xorr(_T_3065) @[el2_lib.scala 301:30]
|
|
node _T_3164 = xorr(_T_3066) @[el2_lib.scala 301:44]
|
|
node _T_3165 = xor(_T_3163, _T_3164) @[el2_lib.scala 301:35]
|
|
node _T_3166 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3167 = and(_T_3165, _T_3166) @[el2_lib.scala 301:50]
|
|
node _T_3168 = bits(_T_3066, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3169 = cat(_T_3072[2], _T_3072[1]) @[el2_lib.scala 301:76]
|
|
node _T_3170 = cat(_T_3169, _T_3072[0]) @[el2_lib.scala 301:76]
|
|
node _T_3171 = cat(_T_3072[5], _T_3072[4]) @[el2_lib.scala 301:76]
|
|
node _T_3172 = cat(_T_3171, _T_3072[3]) @[el2_lib.scala 301:76]
|
|
node _T_3173 = cat(_T_3172, _T_3170) @[el2_lib.scala 301:76]
|
|
node _T_3174 = xorr(_T_3173) @[el2_lib.scala 301:83]
|
|
node _T_3175 = xor(_T_3168, _T_3174) @[el2_lib.scala 301:71]
|
|
node _T_3176 = bits(_T_3066, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3177 = cat(_T_3071[2], _T_3071[1]) @[el2_lib.scala 301:103]
|
|
node _T_3178 = cat(_T_3177, _T_3071[0]) @[el2_lib.scala 301:103]
|
|
node _T_3179 = cat(_T_3071[4], _T_3071[3]) @[el2_lib.scala 301:103]
|
|
node _T_3180 = cat(_T_3071[6], _T_3071[5]) @[el2_lib.scala 301:103]
|
|
node _T_3181 = cat(_T_3180, _T_3179) @[el2_lib.scala 301:103]
|
|
node _T_3182 = cat(_T_3181, _T_3178) @[el2_lib.scala 301:103]
|
|
node _T_3183 = cat(_T_3071[8], _T_3071[7]) @[el2_lib.scala 301:103]
|
|
node _T_3184 = cat(_T_3071[10], _T_3071[9]) @[el2_lib.scala 301:103]
|
|
node _T_3185 = cat(_T_3184, _T_3183) @[el2_lib.scala 301:103]
|
|
node _T_3186 = cat(_T_3071[12], _T_3071[11]) @[el2_lib.scala 301:103]
|
|
node _T_3187 = cat(_T_3071[14], _T_3071[13]) @[el2_lib.scala 301:103]
|
|
node _T_3188 = cat(_T_3187, _T_3186) @[el2_lib.scala 301:103]
|
|
node _T_3189 = cat(_T_3188, _T_3185) @[el2_lib.scala 301:103]
|
|
node _T_3190 = cat(_T_3189, _T_3182) @[el2_lib.scala 301:103]
|
|
node _T_3191 = xorr(_T_3190) @[el2_lib.scala 301:110]
|
|
node _T_3192 = xor(_T_3176, _T_3191) @[el2_lib.scala 301:98]
|
|
node _T_3193 = bits(_T_3066, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3194 = cat(_T_3070[2], _T_3070[1]) @[el2_lib.scala 301:130]
|
|
node _T_3195 = cat(_T_3194, _T_3070[0]) @[el2_lib.scala 301:130]
|
|
node _T_3196 = cat(_T_3070[4], _T_3070[3]) @[el2_lib.scala 301:130]
|
|
node _T_3197 = cat(_T_3070[6], _T_3070[5]) @[el2_lib.scala 301:130]
|
|
node _T_3198 = cat(_T_3197, _T_3196) @[el2_lib.scala 301:130]
|
|
node _T_3199 = cat(_T_3198, _T_3195) @[el2_lib.scala 301:130]
|
|
node _T_3200 = cat(_T_3070[8], _T_3070[7]) @[el2_lib.scala 301:130]
|
|
node _T_3201 = cat(_T_3070[10], _T_3070[9]) @[el2_lib.scala 301:130]
|
|
node _T_3202 = cat(_T_3201, _T_3200) @[el2_lib.scala 301:130]
|
|
node _T_3203 = cat(_T_3070[12], _T_3070[11]) @[el2_lib.scala 301:130]
|
|
node _T_3204 = cat(_T_3070[14], _T_3070[13]) @[el2_lib.scala 301:130]
|
|
node _T_3205 = cat(_T_3204, _T_3203) @[el2_lib.scala 301:130]
|
|
node _T_3206 = cat(_T_3205, _T_3202) @[el2_lib.scala 301:130]
|
|
node _T_3207 = cat(_T_3206, _T_3199) @[el2_lib.scala 301:130]
|
|
node _T_3208 = xorr(_T_3207) @[el2_lib.scala 301:137]
|
|
node _T_3209 = xor(_T_3193, _T_3208) @[el2_lib.scala 301:125]
|
|
node _T_3210 = bits(_T_3066, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3211 = cat(_T_3069[1], _T_3069[0]) @[el2_lib.scala 301:157]
|
|
node _T_3212 = cat(_T_3069[3], _T_3069[2]) @[el2_lib.scala 301:157]
|
|
node _T_3213 = cat(_T_3212, _T_3211) @[el2_lib.scala 301:157]
|
|
node _T_3214 = cat(_T_3069[5], _T_3069[4]) @[el2_lib.scala 301:157]
|
|
node _T_3215 = cat(_T_3069[8], _T_3069[7]) @[el2_lib.scala 301:157]
|
|
node _T_3216 = cat(_T_3215, _T_3069[6]) @[el2_lib.scala 301:157]
|
|
node _T_3217 = cat(_T_3216, _T_3214) @[el2_lib.scala 301:157]
|
|
node _T_3218 = cat(_T_3217, _T_3213) @[el2_lib.scala 301:157]
|
|
node _T_3219 = cat(_T_3069[10], _T_3069[9]) @[el2_lib.scala 301:157]
|
|
node _T_3220 = cat(_T_3069[12], _T_3069[11]) @[el2_lib.scala 301:157]
|
|
node _T_3221 = cat(_T_3220, _T_3219) @[el2_lib.scala 301:157]
|
|
node _T_3222 = cat(_T_3069[14], _T_3069[13]) @[el2_lib.scala 301:157]
|
|
node _T_3223 = cat(_T_3069[17], _T_3069[16]) @[el2_lib.scala 301:157]
|
|
node _T_3224 = cat(_T_3223, _T_3069[15]) @[el2_lib.scala 301:157]
|
|
node _T_3225 = cat(_T_3224, _T_3222) @[el2_lib.scala 301:157]
|
|
node _T_3226 = cat(_T_3225, _T_3221) @[el2_lib.scala 301:157]
|
|
node _T_3227 = cat(_T_3226, _T_3218) @[el2_lib.scala 301:157]
|
|
node _T_3228 = xorr(_T_3227) @[el2_lib.scala 301:164]
|
|
node _T_3229 = xor(_T_3210, _T_3228) @[el2_lib.scala 301:152]
|
|
node _T_3230 = bits(_T_3066, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3231 = cat(_T_3068[1], _T_3068[0]) @[el2_lib.scala 301:184]
|
|
node _T_3232 = cat(_T_3068[3], _T_3068[2]) @[el2_lib.scala 301:184]
|
|
node _T_3233 = cat(_T_3232, _T_3231) @[el2_lib.scala 301:184]
|
|
node _T_3234 = cat(_T_3068[5], _T_3068[4]) @[el2_lib.scala 301:184]
|
|
node _T_3235 = cat(_T_3068[8], _T_3068[7]) @[el2_lib.scala 301:184]
|
|
node _T_3236 = cat(_T_3235, _T_3068[6]) @[el2_lib.scala 301:184]
|
|
node _T_3237 = cat(_T_3236, _T_3234) @[el2_lib.scala 301:184]
|
|
node _T_3238 = cat(_T_3237, _T_3233) @[el2_lib.scala 301:184]
|
|
node _T_3239 = cat(_T_3068[10], _T_3068[9]) @[el2_lib.scala 301:184]
|
|
node _T_3240 = cat(_T_3068[12], _T_3068[11]) @[el2_lib.scala 301:184]
|
|
node _T_3241 = cat(_T_3240, _T_3239) @[el2_lib.scala 301:184]
|
|
node _T_3242 = cat(_T_3068[14], _T_3068[13]) @[el2_lib.scala 301:184]
|
|
node _T_3243 = cat(_T_3068[17], _T_3068[16]) @[el2_lib.scala 301:184]
|
|
node _T_3244 = cat(_T_3243, _T_3068[15]) @[el2_lib.scala 301:184]
|
|
node _T_3245 = cat(_T_3244, _T_3242) @[el2_lib.scala 301:184]
|
|
node _T_3246 = cat(_T_3245, _T_3241) @[el2_lib.scala 301:184]
|
|
node _T_3247 = cat(_T_3246, _T_3238) @[el2_lib.scala 301:184]
|
|
node _T_3248 = xorr(_T_3247) @[el2_lib.scala 301:191]
|
|
node _T_3249 = xor(_T_3230, _T_3248) @[el2_lib.scala 301:179]
|
|
node _T_3250 = bits(_T_3066, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3251 = cat(_T_3067[1], _T_3067[0]) @[el2_lib.scala 301:211]
|
|
node _T_3252 = cat(_T_3067[3], _T_3067[2]) @[el2_lib.scala 301:211]
|
|
node _T_3253 = cat(_T_3252, _T_3251) @[el2_lib.scala 301:211]
|
|
node _T_3254 = cat(_T_3067[5], _T_3067[4]) @[el2_lib.scala 301:211]
|
|
node _T_3255 = cat(_T_3067[8], _T_3067[7]) @[el2_lib.scala 301:211]
|
|
node _T_3256 = cat(_T_3255, _T_3067[6]) @[el2_lib.scala 301:211]
|
|
node _T_3257 = cat(_T_3256, _T_3254) @[el2_lib.scala 301:211]
|
|
node _T_3258 = cat(_T_3257, _T_3253) @[el2_lib.scala 301:211]
|
|
node _T_3259 = cat(_T_3067[10], _T_3067[9]) @[el2_lib.scala 301:211]
|
|
node _T_3260 = cat(_T_3067[12], _T_3067[11]) @[el2_lib.scala 301:211]
|
|
node _T_3261 = cat(_T_3260, _T_3259) @[el2_lib.scala 301:211]
|
|
node _T_3262 = cat(_T_3067[14], _T_3067[13]) @[el2_lib.scala 301:211]
|
|
node _T_3263 = cat(_T_3067[17], _T_3067[16]) @[el2_lib.scala 301:211]
|
|
node _T_3264 = cat(_T_3263, _T_3067[15]) @[el2_lib.scala 301:211]
|
|
node _T_3265 = cat(_T_3264, _T_3262) @[el2_lib.scala 301:211]
|
|
node _T_3266 = cat(_T_3265, _T_3261) @[el2_lib.scala 301:211]
|
|
node _T_3267 = cat(_T_3266, _T_3258) @[el2_lib.scala 301:211]
|
|
node _T_3268 = xorr(_T_3267) @[el2_lib.scala 301:218]
|
|
node _T_3269 = xor(_T_3250, _T_3268) @[el2_lib.scala 301:206]
|
|
node _T_3270 = cat(_T_3229, _T_3249) @[Cat.scala 29:58]
|
|
node _T_3271 = cat(_T_3270, _T_3269) @[Cat.scala 29:58]
|
|
node _T_3272 = cat(_T_3192, _T_3209) @[Cat.scala 29:58]
|
|
node _T_3273 = cat(_T_3167, _T_3175) @[Cat.scala 29:58]
|
|
node _T_3274 = cat(_T_3273, _T_3272) @[Cat.scala 29:58]
|
|
node _T_3275 = cat(_T_3274, _T_3271) @[Cat.scala 29:58]
|
|
node _T_3276 = neq(_T_3275, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3277 = and(_T_3064, _T_3276) @[el2_lib.scala 302:32]
|
|
node _T_3278 = bits(_T_3275, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3279 = and(_T_3277, _T_3278) @[el2_lib.scala 302:53]
|
|
node _T_3280 = neq(_T_3275, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3281 = and(_T_3064, _T_3280) @[el2_lib.scala 303:32]
|
|
node _T_3282 = bits(_T_3275, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3283 = not(_T_3282) @[el2_lib.scala 303:55]
|
|
node _T_3284 = and(_T_3281, _T_3283) @[el2_lib.scala 303:53]
|
|
wire _T_3285 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3286 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3287 = eq(_T_3286, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3285[0] <= _T_3287 @[el2_lib.scala 307:23]
|
|
node _T_3288 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3289 = eq(_T_3288, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3285[1] <= _T_3289 @[el2_lib.scala 307:23]
|
|
node _T_3290 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3291 = eq(_T_3290, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3285[2] <= _T_3291 @[el2_lib.scala 307:23]
|
|
node _T_3292 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3293 = eq(_T_3292, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3285[3] <= _T_3293 @[el2_lib.scala 307:23]
|
|
node _T_3294 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3295 = eq(_T_3294, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3285[4] <= _T_3295 @[el2_lib.scala 307:23]
|
|
node _T_3296 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3297 = eq(_T_3296, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3285[5] <= _T_3297 @[el2_lib.scala 307:23]
|
|
node _T_3298 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3299 = eq(_T_3298, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3285[6] <= _T_3299 @[el2_lib.scala 307:23]
|
|
node _T_3300 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3301 = eq(_T_3300, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3285[7] <= _T_3301 @[el2_lib.scala 307:23]
|
|
node _T_3302 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3303 = eq(_T_3302, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3285[8] <= _T_3303 @[el2_lib.scala 307:23]
|
|
node _T_3304 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3305 = eq(_T_3304, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3285[9] <= _T_3305 @[el2_lib.scala 307:23]
|
|
node _T_3306 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3307 = eq(_T_3306, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3285[10] <= _T_3307 @[el2_lib.scala 307:23]
|
|
node _T_3308 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3309 = eq(_T_3308, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3285[11] <= _T_3309 @[el2_lib.scala 307:23]
|
|
node _T_3310 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3311 = eq(_T_3310, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3285[12] <= _T_3311 @[el2_lib.scala 307:23]
|
|
node _T_3312 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3313 = eq(_T_3312, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3285[13] <= _T_3313 @[el2_lib.scala 307:23]
|
|
node _T_3314 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3315 = eq(_T_3314, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3285[14] <= _T_3315 @[el2_lib.scala 307:23]
|
|
node _T_3316 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3317 = eq(_T_3316, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3285[15] <= _T_3317 @[el2_lib.scala 307:23]
|
|
node _T_3318 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3319 = eq(_T_3318, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3285[16] <= _T_3319 @[el2_lib.scala 307:23]
|
|
node _T_3320 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3321 = eq(_T_3320, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3285[17] <= _T_3321 @[el2_lib.scala 307:23]
|
|
node _T_3322 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3323 = eq(_T_3322, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3285[18] <= _T_3323 @[el2_lib.scala 307:23]
|
|
node _T_3324 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3325 = eq(_T_3324, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3285[19] <= _T_3325 @[el2_lib.scala 307:23]
|
|
node _T_3326 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3327 = eq(_T_3326, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3285[20] <= _T_3327 @[el2_lib.scala 307:23]
|
|
node _T_3328 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3329 = eq(_T_3328, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3285[21] <= _T_3329 @[el2_lib.scala 307:23]
|
|
node _T_3330 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3331 = eq(_T_3330, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3285[22] <= _T_3331 @[el2_lib.scala 307:23]
|
|
node _T_3332 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3333 = eq(_T_3332, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3285[23] <= _T_3333 @[el2_lib.scala 307:23]
|
|
node _T_3334 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3335 = eq(_T_3334, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3285[24] <= _T_3335 @[el2_lib.scala 307:23]
|
|
node _T_3336 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3337 = eq(_T_3336, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3285[25] <= _T_3337 @[el2_lib.scala 307:23]
|
|
node _T_3338 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3339 = eq(_T_3338, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3285[26] <= _T_3339 @[el2_lib.scala 307:23]
|
|
node _T_3340 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3341 = eq(_T_3340, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3285[27] <= _T_3341 @[el2_lib.scala 307:23]
|
|
node _T_3342 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3343 = eq(_T_3342, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3285[28] <= _T_3343 @[el2_lib.scala 307:23]
|
|
node _T_3344 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3345 = eq(_T_3344, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3285[29] <= _T_3345 @[el2_lib.scala 307:23]
|
|
node _T_3346 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3347 = eq(_T_3346, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3285[30] <= _T_3347 @[el2_lib.scala 307:23]
|
|
node _T_3348 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3349 = eq(_T_3348, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3285[31] <= _T_3349 @[el2_lib.scala 307:23]
|
|
node _T_3350 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3351 = eq(_T_3350, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3285[32] <= _T_3351 @[el2_lib.scala 307:23]
|
|
node _T_3352 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3353 = eq(_T_3352, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3285[33] <= _T_3353 @[el2_lib.scala 307:23]
|
|
node _T_3354 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3355 = eq(_T_3354, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3285[34] <= _T_3355 @[el2_lib.scala 307:23]
|
|
node _T_3356 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3357 = eq(_T_3356, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3285[35] <= _T_3357 @[el2_lib.scala 307:23]
|
|
node _T_3358 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3359 = eq(_T_3358, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3285[36] <= _T_3359 @[el2_lib.scala 307:23]
|
|
node _T_3360 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3361 = eq(_T_3360, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3285[37] <= _T_3361 @[el2_lib.scala 307:23]
|
|
node _T_3362 = bits(_T_3275, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3363 = eq(_T_3362, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3285[38] <= _T_3363 @[el2_lib.scala 307:23]
|
|
node _T_3364 = bits(_T_3066, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3365 = bits(_T_3065, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3366 = bits(_T_3066, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3367 = bits(_T_3065, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3368 = bits(_T_3066, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3369 = bits(_T_3065, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3370 = bits(_T_3066, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3371 = bits(_T_3065, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3372 = bits(_T_3066, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3373 = bits(_T_3065, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3374 = bits(_T_3066, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3375 = cat(_T_3373, _T_3374) @[Cat.scala 29:58]
|
|
node _T_3376 = cat(_T_3370, _T_3371) @[Cat.scala 29:58]
|
|
node _T_3377 = cat(_T_3376, _T_3372) @[Cat.scala 29:58]
|
|
node _T_3378 = cat(_T_3377, _T_3375) @[Cat.scala 29:58]
|
|
node _T_3379 = cat(_T_3367, _T_3368) @[Cat.scala 29:58]
|
|
node _T_3380 = cat(_T_3379, _T_3369) @[Cat.scala 29:58]
|
|
node _T_3381 = cat(_T_3364, _T_3365) @[Cat.scala 29:58]
|
|
node _T_3382 = cat(_T_3381, _T_3366) @[Cat.scala 29:58]
|
|
node _T_3383 = cat(_T_3382, _T_3380) @[Cat.scala 29:58]
|
|
node _T_3384 = cat(_T_3383, _T_3378) @[Cat.scala 29:58]
|
|
node _T_3385 = bits(_T_3279, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3386 = cat(_T_3285[1], _T_3285[0]) @[el2_lib.scala 310:69]
|
|
node _T_3387 = cat(_T_3285[3], _T_3285[2]) @[el2_lib.scala 310:69]
|
|
node _T_3388 = cat(_T_3387, _T_3386) @[el2_lib.scala 310:69]
|
|
node _T_3389 = cat(_T_3285[5], _T_3285[4]) @[el2_lib.scala 310:69]
|
|
node _T_3390 = cat(_T_3285[8], _T_3285[7]) @[el2_lib.scala 310:69]
|
|
node _T_3391 = cat(_T_3390, _T_3285[6]) @[el2_lib.scala 310:69]
|
|
node _T_3392 = cat(_T_3391, _T_3389) @[el2_lib.scala 310:69]
|
|
node _T_3393 = cat(_T_3392, _T_3388) @[el2_lib.scala 310:69]
|
|
node _T_3394 = cat(_T_3285[10], _T_3285[9]) @[el2_lib.scala 310:69]
|
|
node _T_3395 = cat(_T_3285[13], _T_3285[12]) @[el2_lib.scala 310:69]
|
|
node _T_3396 = cat(_T_3395, _T_3285[11]) @[el2_lib.scala 310:69]
|
|
node _T_3397 = cat(_T_3396, _T_3394) @[el2_lib.scala 310:69]
|
|
node _T_3398 = cat(_T_3285[15], _T_3285[14]) @[el2_lib.scala 310:69]
|
|
node _T_3399 = cat(_T_3285[18], _T_3285[17]) @[el2_lib.scala 310:69]
|
|
node _T_3400 = cat(_T_3399, _T_3285[16]) @[el2_lib.scala 310:69]
|
|
node _T_3401 = cat(_T_3400, _T_3398) @[el2_lib.scala 310:69]
|
|
node _T_3402 = cat(_T_3401, _T_3397) @[el2_lib.scala 310:69]
|
|
node _T_3403 = cat(_T_3402, _T_3393) @[el2_lib.scala 310:69]
|
|
node _T_3404 = cat(_T_3285[20], _T_3285[19]) @[el2_lib.scala 310:69]
|
|
node _T_3405 = cat(_T_3285[23], _T_3285[22]) @[el2_lib.scala 310:69]
|
|
node _T_3406 = cat(_T_3405, _T_3285[21]) @[el2_lib.scala 310:69]
|
|
node _T_3407 = cat(_T_3406, _T_3404) @[el2_lib.scala 310:69]
|
|
node _T_3408 = cat(_T_3285[25], _T_3285[24]) @[el2_lib.scala 310:69]
|
|
node _T_3409 = cat(_T_3285[28], _T_3285[27]) @[el2_lib.scala 310:69]
|
|
node _T_3410 = cat(_T_3409, _T_3285[26]) @[el2_lib.scala 310:69]
|
|
node _T_3411 = cat(_T_3410, _T_3408) @[el2_lib.scala 310:69]
|
|
node _T_3412 = cat(_T_3411, _T_3407) @[el2_lib.scala 310:69]
|
|
node _T_3413 = cat(_T_3285[30], _T_3285[29]) @[el2_lib.scala 310:69]
|
|
node _T_3414 = cat(_T_3285[33], _T_3285[32]) @[el2_lib.scala 310:69]
|
|
node _T_3415 = cat(_T_3414, _T_3285[31]) @[el2_lib.scala 310:69]
|
|
node _T_3416 = cat(_T_3415, _T_3413) @[el2_lib.scala 310:69]
|
|
node _T_3417 = cat(_T_3285[35], _T_3285[34]) @[el2_lib.scala 310:69]
|
|
node _T_3418 = cat(_T_3285[38], _T_3285[37]) @[el2_lib.scala 310:69]
|
|
node _T_3419 = cat(_T_3418, _T_3285[36]) @[el2_lib.scala 310:69]
|
|
node _T_3420 = cat(_T_3419, _T_3417) @[el2_lib.scala 310:69]
|
|
node _T_3421 = cat(_T_3420, _T_3416) @[el2_lib.scala 310:69]
|
|
node _T_3422 = cat(_T_3421, _T_3412) @[el2_lib.scala 310:69]
|
|
node _T_3423 = cat(_T_3422, _T_3403) @[el2_lib.scala 310:69]
|
|
node _T_3424 = xor(_T_3423, _T_3384) @[el2_lib.scala 310:76]
|
|
node _T_3425 = mux(_T_3385, _T_3424, _T_3384) @[el2_lib.scala 310:31]
|
|
node _T_3426 = bits(_T_3425, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3427 = bits(_T_3425, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3428 = bits(_T_3425, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3429 = bits(_T_3425, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3430 = bits(_T_3425, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3431 = cat(_T_3429, _T_3430) @[Cat.scala 29:58]
|
|
node _T_3432 = cat(_T_3426, _T_3427) @[Cat.scala 29:58]
|
|
node _T_3433 = cat(_T_3432, _T_3428) @[Cat.scala 29:58]
|
|
node _T_3434 = cat(_T_3433, _T_3431) @[Cat.scala 29:58]
|
|
node _T_3435 = bits(_T_3425, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3436 = bits(_T_3275, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3437 = eq(_T_3436, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3438 = xor(_T_3435, _T_3437) @[el2_lib.scala 313:44]
|
|
node _T_3439 = bits(_T_3425, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3440 = bits(_T_3425, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3441 = bits(_T_3425, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3442 = bits(_T_3425, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3443 = bits(_T_3425, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3444 = cat(_T_3441, _T_3442) @[Cat.scala 29:58]
|
|
node _T_3445 = cat(_T_3444, _T_3443) @[Cat.scala 29:58]
|
|
node _T_3446 = cat(_T_3438, _T_3439) @[Cat.scala 29:58]
|
|
node _T_3447 = cat(_T_3446, _T_3440) @[Cat.scala 29:58]
|
|
node _T_3448 = cat(_T_3447, _T_3445) @[Cat.scala 29:58]
|
|
node _T_3449 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 709:73]
|
|
node _T_3450 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 709:93]
|
|
node _T_3451 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 709:128]
|
|
wire _T_3452 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3453 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3454 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3455 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3456 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3457 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3458 = bits(_T_3450, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3452[0] <= _T_3458 @[el2_lib.scala 293:30]
|
|
node _T_3459 = bits(_T_3450, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3453[0] <= _T_3459 @[el2_lib.scala 294:30]
|
|
node _T_3460 = bits(_T_3450, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3452[1] <= _T_3460 @[el2_lib.scala 293:30]
|
|
node _T_3461 = bits(_T_3450, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3454[0] <= _T_3461 @[el2_lib.scala 295:30]
|
|
node _T_3462 = bits(_T_3450, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3453[1] <= _T_3462 @[el2_lib.scala 294:30]
|
|
node _T_3463 = bits(_T_3450, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3454[1] <= _T_3463 @[el2_lib.scala 295:30]
|
|
node _T_3464 = bits(_T_3450, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3452[2] <= _T_3464 @[el2_lib.scala 293:30]
|
|
node _T_3465 = bits(_T_3450, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3453[2] <= _T_3465 @[el2_lib.scala 294:30]
|
|
node _T_3466 = bits(_T_3450, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3454[2] <= _T_3466 @[el2_lib.scala 295:30]
|
|
node _T_3467 = bits(_T_3450, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3452[3] <= _T_3467 @[el2_lib.scala 293:30]
|
|
node _T_3468 = bits(_T_3450, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3455[0] <= _T_3468 @[el2_lib.scala 296:30]
|
|
node _T_3469 = bits(_T_3450, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3453[3] <= _T_3469 @[el2_lib.scala 294:30]
|
|
node _T_3470 = bits(_T_3450, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3455[1] <= _T_3470 @[el2_lib.scala 296:30]
|
|
node _T_3471 = bits(_T_3450, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3452[4] <= _T_3471 @[el2_lib.scala 293:30]
|
|
node _T_3472 = bits(_T_3450, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3453[4] <= _T_3472 @[el2_lib.scala 294:30]
|
|
node _T_3473 = bits(_T_3450, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3455[2] <= _T_3473 @[el2_lib.scala 296:30]
|
|
node _T_3474 = bits(_T_3450, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3454[3] <= _T_3474 @[el2_lib.scala 295:30]
|
|
node _T_3475 = bits(_T_3450, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3455[3] <= _T_3475 @[el2_lib.scala 296:30]
|
|
node _T_3476 = bits(_T_3450, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3452[5] <= _T_3476 @[el2_lib.scala 293:30]
|
|
node _T_3477 = bits(_T_3450, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3454[4] <= _T_3477 @[el2_lib.scala 295:30]
|
|
node _T_3478 = bits(_T_3450, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3455[4] <= _T_3478 @[el2_lib.scala 296:30]
|
|
node _T_3479 = bits(_T_3450, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3453[5] <= _T_3479 @[el2_lib.scala 294:30]
|
|
node _T_3480 = bits(_T_3450, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3454[5] <= _T_3480 @[el2_lib.scala 295:30]
|
|
node _T_3481 = bits(_T_3450, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3455[5] <= _T_3481 @[el2_lib.scala 296:30]
|
|
node _T_3482 = bits(_T_3450, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3452[6] <= _T_3482 @[el2_lib.scala 293:30]
|
|
node _T_3483 = bits(_T_3450, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3453[6] <= _T_3483 @[el2_lib.scala 294:30]
|
|
node _T_3484 = bits(_T_3450, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3454[6] <= _T_3484 @[el2_lib.scala 295:30]
|
|
node _T_3485 = bits(_T_3450, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3455[6] <= _T_3485 @[el2_lib.scala 296:30]
|
|
node _T_3486 = bits(_T_3450, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3452[7] <= _T_3486 @[el2_lib.scala 293:30]
|
|
node _T_3487 = bits(_T_3450, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3456[0] <= _T_3487 @[el2_lib.scala 297:30]
|
|
node _T_3488 = bits(_T_3450, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3453[7] <= _T_3488 @[el2_lib.scala 294:30]
|
|
node _T_3489 = bits(_T_3450, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3456[1] <= _T_3489 @[el2_lib.scala 297:30]
|
|
node _T_3490 = bits(_T_3450, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3452[8] <= _T_3490 @[el2_lib.scala 293:30]
|
|
node _T_3491 = bits(_T_3450, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3453[8] <= _T_3491 @[el2_lib.scala 294:30]
|
|
node _T_3492 = bits(_T_3450, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3456[2] <= _T_3492 @[el2_lib.scala 297:30]
|
|
node _T_3493 = bits(_T_3450, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3454[7] <= _T_3493 @[el2_lib.scala 295:30]
|
|
node _T_3494 = bits(_T_3450, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3456[3] <= _T_3494 @[el2_lib.scala 297:30]
|
|
node _T_3495 = bits(_T_3450, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3452[9] <= _T_3495 @[el2_lib.scala 293:30]
|
|
node _T_3496 = bits(_T_3450, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3454[8] <= _T_3496 @[el2_lib.scala 295:30]
|
|
node _T_3497 = bits(_T_3450, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3456[4] <= _T_3497 @[el2_lib.scala 297:30]
|
|
node _T_3498 = bits(_T_3450, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3453[9] <= _T_3498 @[el2_lib.scala 294:30]
|
|
node _T_3499 = bits(_T_3450, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3454[9] <= _T_3499 @[el2_lib.scala 295:30]
|
|
node _T_3500 = bits(_T_3450, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3456[5] <= _T_3500 @[el2_lib.scala 297:30]
|
|
node _T_3501 = bits(_T_3450, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3452[10] <= _T_3501 @[el2_lib.scala 293:30]
|
|
node _T_3502 = bits(_T_3450, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3453[10] <= _T_3502 @[el2_lib.scala 294:30]
|
|
node _T_3503 = bits(_T_3450, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3454[10] <= _T_3503 @[el2_lib.scala 295:30]
|
|
node _T_3504 = bits(_T_3450, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3456[6] <= _T_3504 @[el2_lib.scala 297:30]
|
|
node _T_3505 = bits(_T_3450, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3455[7] <= _T_3505 @[el2_lib.scala 296:30]
|
|
node _T_3506 = bits(_T_3450, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3456[7] <= _T_3506 @[el2_lib.scala 297:30]
|
|
node _T_3507 = bits(_T_3450, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3452[11] <= _T_3507 @[el2_lib.scala 293:30]
|
|
node _T_3508 = bits(_T_3450, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3455[8] <= _T_3508 @[el2_lib.scala 296:30]
|
|
node _T_3509 = bits(_T_3450, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3456[8] <= _T_3509 @[el2_lib.scala 297:30]
|
|
node _T_3510 = bits(_T_3450, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3453[11] <= _T_3510 @[el2_lib.scala 294:30]
|
|
node _T_3511 = bits(_T_3450, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3455[9] <= _T_3511 @[el2_lib.scala 296:30]
|
|
node _T_3512 = bits(_T_3450, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3456[9] <= _T_3512 @[el2_lib.scala 297:30]
|
|
node _T_3513 = bits(_T_3450, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3452[12] <= _T_3513 @[el2_lib.scala 293:30]
|
|
node _T_3514 = bits(_T_3450, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3453[12] <= _T_3514 @[el2_lib.scala 294:30]
|
|
node _T_3515 = bits(_T_3450, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3455[10] <= _T_3515 @[el2_lib.scala 296:30]
|
|
node _T_3516 = bits(_T_3450, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3456[10] <= _T_3516 @[el2_lib.scala 297:30]
|
|
node _T_3517 = bits(_T_3450, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3454[11] <= _T_3517 @[el2_lib.scala 295:30]
|
|
node _T_3518 = bits(_T_3450, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3455[11] <= _T_3518 @[el2_lib.scala 296:30]
|
|
node _T_3519 = bits(_T_3450, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3456[11] <= _T_3519 @[el2_lib.scala 297:30]
|
|
node _T_3520 = bits(_T_3450, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3452[13] <= _T_3520 @[el2_lib.scala 293:30]
|
|
node _T_3521 = bits(_T_3450, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3454[12] <= _T_3521 @[el2_lib.scala 295:30]
|
|
node _T_3522 = bits(_T_3450, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3455[12] <= _T_3522 @[el2_lib.scala 296:30]
|
|
node _T_3523 = bits(_T_3450, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3456[12] <= _T_3523 @[el2_lib.scala 297:30]
|
|
node _T_3524 = bits(_T_3450, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3453[13] <= _T_3524 @[el2_lib.scala 294:30]
|
|
node _T_3525 = bits(_T_3450, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3454[13] <= _T_3525 @[el2_lib.scala 295:30]
|
|
node _T_3526 = bits(_T_3450, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3455[13] <= _T_3526 @[el2_lib.scala 296:30]
|
|
node _T_3527 = bits(_T_3450, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3456[13] <= _T_3527 @[el2_lib.scala 297:30]
|
|
node _T_3528 = bits(_T_3450, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3452[14] <= _T_3528 @[el2_lib.scala 293:30]
|
|
node _T_3529 = bits(_T_3450, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3453[14] <= _T_3529 @[el2_lib.scala 294:30]
|
|
node _T_3530 = bits(_T_3450, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3454[14] <= _T_3530 @[el2_lib.scala 295:30]
|
|
node _T_3531 = bits(_T_3450, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3455[14] <= _T_3531 @[el2_lib.scala 296:30]
|
|
node _T_3532 = bits(_T_3450, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3456[14] <= _T_3532 @[el2_lib.scala 297:30]
|
|
node _T_3533 = bits(_T_3450, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3452[15] <= _T_3533 @[el2_lib.scala 293:30]
|
|
node _T_3534 = bits(_T_3450, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3457[0] <= _T_3534 @[el2_lib.scala 298:30]
|
|
node _T_3535 = bits(_T_3450, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3453[15] <= _T_3535 @[el2_lib.scala 294:30]
|
|
node _T_3536 = bits(_T_3450, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3457[1] <= _T_3536 @[el2_lib.scala 298:30]
|
|
node _T_3537 = bits(_T_3450, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3452[16] <= _T_3537 @[el2_lib.scala 293:30]
|
|
node _T_3538 = bits(_T_3450, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3453[16] <= _T_3538 @[el2_lib.scala 294:30]
|
|
node _T_3539 = bits(_T_3450, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3457[2] <= _T_3539 @[el2_lib.scala 298:30]
|
|
node _T_3540 = bits(_T_3450, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3454[15] <= _T_3540 @[el2_lib.scala 295:30]
|
|
node _T_3541 = bits(_T_3450, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3457[3] <= _T_3541 @[el2_lib.scala 298:30]
|
|
node _T_3542 = bits(_T_3450, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3452[17] <= _T_3542 @[el2_lib.scala 293:30]
|
|
node _T_3543 = bits(_T_3450, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3454[16] <= _T_3543 @[el2_lib.scala 295:30]
|
|
node _T_3544 = bits(_T_3450, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3457[4] <= _T_3544 @[el2_lib.scala 298:30]
|
|
node _T_3545 = bits(_T_3450, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3453[17] <= _T_3545 @[el2_lib.scala 294:30]
|
|
node _T_3546 = bits(_T_3450, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3454[17] <= _T_3546 @[el2_lib.scala 295:30]
|
|
node _T_3547 = bits(_T_3450, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3457[5] <= _T_3547 @[el2_lib.scala 298:30]
|
|
node _T_3548 = xorr(_T_3450) @[el2_lib.scala 301:30]
|
|
node _T_3549 = xorr(_T_3451) @[el2_lib.scala 301:44]
|
|
node _T_3550 = xor(_T_3548, _T_3549) @[el2_lib.scala 301:35]
|
|
node _T_3551 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3552 = and(_T_3550, _T_3551) @[el2_lib.scala 301:50]
|
|
node _T_3553 = bits(_T_3451, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3554 = cat(_T_3457[2], _T_3457[1]) @[el2_lib.scala 301:76]
|
|
node _T_3555 = cat(_T_3554, _T_3457[0]) @[el2_lib.scala 301:76]
|
|
node _T_3556 = cat(_T_3457[5], _T_3457[4]) @[el2_lib.scala 301:76]
|
|
node _T_3557 = cat(_T_3556, _T_3457[3]) @[el2_lib.scala 301:76]
|
|
node _T_3558 = cat(_T_3557, _T_3555) @[el2_lib.scala 301:76]
|
|
node _T_3559 = xorr(_T_3558) @[el2_lib.scala 301:83]
|
|
node _T_3560 = xor(_T_3553, _T_3559) @[el2_lib.scala 301:71]
|
|
node _T_3561 = bits(_T_3451, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3562 = cat(_T_3456[2], _T_3456[1]) @[el2_lib.scala 301:103]
|
|
node _T_3563 = cat(_T_3562, _T_3456[0]) @[el2_lib.scala 301:103]
|
|
node _T_3564 = cat(_T_3456[4], _T_3456[3]) @[el2_lib.scala 301:103]
|
|
node _T_3565 = cat(_T_3456[6], _T_3456[5]) @[el2_lib.scala 301:103]
|
|
node _T_3566 = cat(_T_3565, _T_3564) @[el2_lib.scala 301:103]
|
|
node _T_3567 = cat(_T_3566, _T_3563) @[el2_lib.scala 301:103]
|
|
node _T_3568 = cat(_T_3456[8], _T_3456[7]) @[el2_lib.scala 301:103]
|
|
node _T_3569 = cat(_T_3456[10], _T_3456[9]) @[el2_lib.scala 301:103]
|
|
node _T_3570 = cat(_T_3569, _T_3568) @[el2_lib.scala 301:103]
|
|
node _T_3571 = cat(_T_3456[12], _T_3456[11]) @[el2_lib.scala 301:103]
|
|
node _T_3572 = cat(_T_3456[14], _T_3456[13]) @[el2_lib.scala 301:103]
|
|
node _T_3573 = cat(_T_3572, _T_3571) @[el2_lib.scala 301:103]
|
|
node _T_3574 = cat(_T_3573, _T_3570) @[el2_lib.scala 301:103]
|
|
node _T_3575 = cat(_T_3574, _T_3567) @[el2_lib.scala 301:103]
|
|
node _T_3576 = xorr(_T_3575) @[el2_lib.scala 301:110]
|
|
node _T_3577 = xor(_T_3561, _T_3576) @[el2_lib.scala 301:98]
|
|
node _T_3578 = bits(_T_3451, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3579 = cat(_T_3455[2], _T_3455[1]) @[el2_lib.scala 301:130]
|
|
node _T_3580 = cat(_T_3579, _T_3455[0]) @[el2_lib.scala 301:130]
|
|
node _T_3581 = cat(_T_3455[4], _T_3455[3]) @[el2_lib.scala 301:130]
|
|
node _T_3582 = cat(_T_3455[6], _T_3455[5]) @[el2_lib.scala 301:130]
|
|
node _T_3583 = cat(_T_3582, _T_3581) @[el2_lib.scala 301:130]
|
|
node _T_3584 = cat(_T_3583, _T_3580) @[el2_lib.scala 301:130]
|
|
node _T_3585 = cat(_T_3455[8], _T_3455[7]) @[el2_lib.scala 301:130]
|
|
node _T_3586 = cat(_T_3455[10], _T_3455[9]) @[el2_lib.scala 301:130]
|
|
node _T_3587 = cat(_T_3586, _T_3585) @[el2_lib.scala 301:130]
|
|
node _T_3588 = cat(_T_3455[12], _T_3455[11]) @[el2_lib.scala 301:130]
|
|
node _T_3589 = cat(_T_3455[14], _T_3455[13]) @[el2_lib.scala 301:130]
|
|
node _T_3590 = cat(_T_3589, _T_3588) @[el2_lib.scala 301:130]
|
|
node _T_3591 = cat(_T_3590, _T_3587) @[el2_lib.scala 301:130]
|
|
node _T_3592 = cat(_T_3591, _T_3584) @[el2_lib.scala 301:130]
|
|
node _T_3593 = xorr(_T_3592) @[el2_lib.scala 301:137]
|
|
node _T_3594 = xor(_T_3578, _T_3593) @[el2_lib.scala 301:125]
|
|
node _T_3595 = bits(_T_3451, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3596 = cat(_T_3454[1], _T_3454[0]) @[el2_lib.scala 301:157]
|
|
node _T_3597 = cat(_T_3454[3], _T_3454[2]) @[el2_lib.scala 301:157]
|
|
node _T_3598 = cat(_T_3597, _T_3596) @[el2_lib.scala 301:157]
|
|
node _T_3599 = cat(_T_3454[5], _T_3454[4]) @[el2_lib.scala 301:157]
|
|
node _T_3600 = cat(_T_3454[8], _T_3454[7]) @[el2_lib.scala 301:157]
|
|
node _T_3601 = cat(_T_3600, _T_3454[6]) @[el2_lib.scala 301:157]
|
|
node _T_3602 = cat(_T_3601, _T_3599) @[el2_lib.scala 301:157]
|
|
node _T_3603 = cat(_T_3602, _T_3598) @[el2_lib.scala 301:157]
|
|
node _T_3604 = cat(_T_3454[10], _T_3454[9]) @[el2_lib.scala 301:157]
|
|
node _T_3605 = cat(_T_3454[12], _T_3454[11]) @[el2_lib.scala 301:157]
|
|
node _T_3606 = cat(_T_3605, _T_3604) @[el2_lib.scala 301:157]
|
|
node _T_3607 = cat(_T_3454[14], _T_3454[13]) @[el2_lib.scala 301:157]
|
|
node _T_3608 = cat(_T_3454[17], _T_3454[16]) @[el2_lib.scala 301:157]
|
|
node _T_3609 = cat(_T_3608, _T_3454[15]) @[el2_lib.scala 301:157]
|
|
node _T_3610 = cat(_T_3609, _T_3607) @[el2_lib.scala 301:157]
|
|
node _T_3611 = cat(_T_3610, _T_3606) @[el2_lib.scala 301:157]
|
|
node _T_3612 = cat(_T_3611, _T_3603) @[el2_lib.scala 301:157]
|
|
node _T_3613 = xorr(_T_3612) @[el2_lib.scala 301:164]
|
|
node _T_3614 = xor(_T_3595, _T_3613) @[el2_lib.scala 301:152]
|
|
node _T_3615 = bits(_T_3451, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3616 = cat(_T_3453[1], _T_3453[0]) @[el2_lib.scala 301:184]
|
|
node _T_3617 = cat(_T_3453[3], _T_3453[2]) @[el2_lib.scala 301:184]
|
|
node _T_3618 = cat(_T_3617, _T_3616) @[el2_lib.scala 301:184]
|
|
node _T_3619 = cat(_T_3453[5], _T_3453[4]) @[el2_lib.scala 301:184]
|
|
node _T_3620 = cat(_T_3453[8], _T_3453[7]) @[el2_lib.scala 301:184]
|
|
node _T_3621 = cat(_T_3620, _T_3453[6]) @[el2_lib.scala 301:184]
|
|
node _T_3622 = cat(_T_3621, _T_3619) @[el2_lib.scala 301:184]
|
|
node _T_3623 = cat(_T_3622, _T_3618) @[el2_lib.scala 301:184]
|
|
node _T_3624 = cat(_T_3453[10], _T_3453[9]) @[el2_lib.scala 301:184]
|
|
node _T_3625 = cat(_T_3453[12], _T_3453[11]) @[el2_lib.scala 301:184]
|
|
node _T_3626 = cat(_T_3625, _T_3624) @[el2_lib.scala 301:184]
|
|
node _T_3627 = cat(_T_3453[14], _T_3453[13]) @[el2_lib.scala 301:184]
|
|
node _T_3628 = cat(_T_3453[17], _T_3453[16]) @[el2_lib.scala 301:184]
|
|
node _T_3629 = cat(_T_3628, _T_3453[15]) @[el2_lib.scala 301:184]
|
|
node _T_3630 = cat(_T_3629, _T_3627) @[el2_lib.scala 301:184]
|
|
node _T_3631 = cat(_T_3630, _T_3626) @[el2_lib.scala 301:184]
|
|
node _T_3632 = cat(_T_3631, _T_3623) @[el2_lib.scala 301:184]
|
|
node _T_3633 = xorr(_T_3632) @[el2_lib.scala 301:191]
|
|
node _T_3634 = xor(_T_3615, _T_3633) @[el2_lib.scala 301:179]
|
|
node _T_3635 = bits(_T_3451, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3636 = cat(_T_3452[1], _T_3452[0]) @[el2_lib.scala 301:211]
|
|
node _T_3637 = cat(_T_3452[3], _T_3452[2]) @[el2_lib.scala 301:211]
|
|
node _T_3638 = cat(_T_3637, _T_3636) @[el2_lib.scala 301:211]
|
|
node _T_3639 = cat(_T_3452[5], _T_3452[4]) @[el2_lib.scala 301:211]
|
|
node _T_3640 = cat(_T_3452[8], _T_3452[7]) @[el2_lib.scala 301:211]
|
|
node _T_3641 = cat(_T_3640, _T_3452[6]) @[el2_lib.scala 301:211]
|
|
node _T_3642 = cat(_T_3641, _T_3639) @[el2_lib.scala 301:211]
|
|
node _T_3643 = cat(_T_3642, _T_3638) @[el2_lib.scala 301:211]
|
|
node _T_3644 = cat(_T_3452[10], _T_3452[9]) @[el2_lib.scala 301:211]
|
|
node _T_3645 = cat(_T_3452[12], _T_3452[11]) @[el2_lib.scala 301:211]
|
|
node _T_3646 = cat(_T_3645, _T_3644) @[el2_lib.scala 301:211]
|
|
node _T_3647 = cat(_T_3452[14], _T_3452[13]) @[el2_lib.scala 301:211]
|
|
node _T_3648 = cat(_T_3452[17], _T_3452[16]) @[el2_lib.scala 301:211]
|
|
node _T_3649 = cat(_T_3648, _T_3452[15]) @[el2_lib.scala 301:211]
|
|
node _T_3650 = cat(_T_3649, _T_3647) @[el2_lib.scala 301:211]
|
|
node _T_3651 = cat(_T_3650, _T_3646) @[el2_lib.scala 301:211]
|
|
node _T_3652 = cat(_T_3651, _T_3643) @[el2_lib.scala 301:211]
|
|
node _T_3653 = xorr(_T_3652) @[el2_lib.scala 301:218]
|
|
node _T_3654 = xor(_T_3635, _T_3653) @[el2_lib.scala 301:206]
|
|
node _T_3655 = cat(_T_3614, _T_3634) @[Cat.scala 29:58]
|
|
node _T_3656 = cat(_T_3655, _T_3654) @[Cat.scala 29:58]
|
|
node _T_3657 = cat(_T_3577, _T_3594) @[Cat.scala 29:58]
|
|
node _T_3658 = cat(_T_3552, _T_3560) @[Cat.scala 29:58]
|
|
node _T_3659 = cat(_T_3658, _T_3657) @[Cat.scala 29:58]
|
|
node _T_3660 = cat(_T_3659, _T_3656) @[Cat.scala 29:58]
|
|
node _T_3661 = neq(_T_3660, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3662 = and(_T_3449, _T_3661) @[el2_lib.scala 302:32]
|
|
node _T_3663 = bits(_T_3660, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3664 = and(_T_3662, _T_3663) @[el2_lib.scala 302:53]
|
|
node _T_3665 = neq(_T_3660, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3666 = and(_T_3449, _T_3665) @[el2_lib.scala 303:32]
|
|
node _T_3667 = bits(_T_3660, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3668 = not(_T_3667) @[el2_lib.scala 303:55]
|
|
node _T_3669 = and(_T_3666, _T_3668) @[el2_lib.scala 303:53]
|
|
wire _T_3670 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3671 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3672 = eq(_T_3671, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3670[0] <= _T_3672 @[el2_lib.scala 307:23]
|
|
node _T_3673 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3674 = eq(_T_3673, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3670[1] <= _T_3674 @[el2_lib.scala 307:23]
|
|
node _T_3675 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3676 = eq(_T_3675, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3670[2] <= _T_3676 @[el2_lib.scala 307:23]
|
|
node _T_3677 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3678 = eq(_T_3677, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3670[3] <= _T_3678 @[el2_lib.scala 307:23]
|
|
node _T_3679 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3680 = eq(_T_3679, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3670[4] <= _T_3680 @[el2_lib.scala 307:23]
|
|
node _T_3681 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3682 = eq(_T_3681, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3670[5] <= _T_3682 @[el2_lib.scala 307:23]
|
|
node _T_3683 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3684 = eq(_T_3683, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3670[6] <= _T_3684 @[el2_lib.scala 307:23]
|
|
node _T_3685 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3686 = eq(_T_3685, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3670[7] <= _T_3686 @[el2_lib.scala 307:23]
|
|
node _T_3687 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3688 = eq(_T_3687, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3670[8] <= _T_3688 @[el2_lib.scala 307:23]
|
|
node _T_3689 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3690 = eq(_T_3689, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3670[9] <= _T_3690 @[el2_lib.scala 307:23]
|
|
node _T_3691 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3692 = eq(_T_3691, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3670[10] <= _T_3692 @[el2_lib.scala 307:23]
|
|
node _T_3693 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3694 = eq(_T_3693, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3670[11] <= _T_3694 @[el2_lib.scala 307:23]
|
|
node _T_3695 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3696 = eq(_T_3695, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3670[12] <= _T_3696 @[el2_lib.scala 307:23]
|
|
node _T_3697 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3698 = eq(_T_3697, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3670[13] <= _T_3698 @[el2_lib.scala 307:23]
|
|
node _T_3699 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3700 = eq(_T_3699, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3670[14] <= _T_3700 @[el2_lib.scala 307:23]
|
|
node _T_3701 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3702 = eq(_T_3701, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3670[15] <= _T_3702 @[el2_lib.scala 307:23]
|
|
node _T_3703 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3704 = eq(_T_3703, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3670[16] <= _T_3704 @[el2_lib.scala 307:23]
|
|
node _T_3705 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3706 = eq(_T_3705, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3670[17] <= _T_3706 @[el2_lib.scala 307:23]
|
|
node _T_3707 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3708 = eq(_T_3707, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3670[18] <= _T_3708 @[el2_lib.scala 307:23]
|
|
node _T_3709 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3710 = eq(_T_3709, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3670[19] <= _T_3710 @[el2_lib.scala 307:23]
|
|
node _T_3711 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3712 = eq(_T_3711, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3670[20] <= _T_3712 @[el2_lib.scala 307:23]
|
|
node _T_3713 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3714 = eq(_T_3713, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3670[21] <= _T_3714 @[el2_lib.scala 307:23]
|
|
node _T_3715 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3716 = eq(_T_3715, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3670[22] <= _T_3716 @[el2_lib.scala 307:23]
|
|
node _T_3717 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3718 = eq(_T_3717, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3670[23] <= _T_3718 @[el2_lib.scala 307:23]
|
|
node _T_3719 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3720 = eq(_T_3719, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3670[24] <= _T_3720 @[el2_lib.scala 307:23]
|
|
node _T_3721 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3722 = eq(_T_3721, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3670[25] <= _T_3722 @[el2_lib.scala 307:23]
|
|
node _T_3723 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3724 = eq(_T_3723, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3670[26] <= _T_3724 @[el2_lib.scala 307:23]
|
|
node _T_3725 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3726 = eq(_T_3725, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3670[27] <= _T_3726 @[el2_lib.scala 307:23]
|
|
node _T_3727 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3728 = eq(_T_3727, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3670[28] <= _T_3728 @[el2_lib.scala 307:23]
|
|
node _T_3729 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3730 = eq(_T_3729, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3670[29] <= _T_3730 @[el2_lib.scala 307:23]
|
|
node _T_3731 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3732 = eq(_T_3731, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3670[30] <= _T_3732 @[el2_lib.scala 307:23]
|
|
node _T_3733 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3734 = eq(_T_3733, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3670[31] <= _T_3734 @[el2_lib.scala 307:23]
|
|
node _T_3735 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3736 = eq(_T_3735, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3670[32] <= _T_3736 @[el2_lib.scala 307:23]
|
|
node _T_3737 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3738 = eq(_T_3737, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3670[33] <= _T_3738 @[el2_lib.scala 307:23]
|
|
node _T_3739 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3740 = eq(_T_3739, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3670[34] <= _T_3740 @[el2_lib.scala 307:23]
|
|
node _T_3741 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3742 = eq(_T_3741, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3670[35] <= _T_3742 @[el2_lib.scala 307:23]
|
|
node _T_3743 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3744 = eq(_T_3743, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3670[36] <= _T_3744 @[el2_lib.scala 307:23]
|
|
node _T_3745 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3746 = eq(_T_3745, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3670[37] <= _T_3746 @[el2_lib.scala 307:23]
|
|
node _T_3747 = bits(_T_3660, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3748 = eq(_T_3747, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3670[38] <= _T_3748 @[el2_lib.scala 307:23]
|
|
node _T_3749 = bits(_T_3451, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3750 = bits(_T_3450, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3751 = bits(_T_3451, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3752 = bits(_T_3450, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3753 = bits(_T_3451, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3754 = bits(_T_3450, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3755 = bits(_T_3451, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3756 = bits(_T_3450, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3757 = bits(_T_3451, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3758 = bits(_T_3450, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3759 = bits(_T_3451, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3760 = cat(_T_3758, _T_3759) @[Cat.scala 29:58]
|
|
node _T_3761 = cat(_T_3755, _T_3756) @[Cat.scala 29:58]
|
|
node _T_3762 = cat(_T_3761, _T_3757) @[Cat.scala 29:58]
|
|
node _T_3763 = cat(_T_3762, _T_3760) @[Cat.scala 29:58]
|
|
node _T_3764 = cat(_T_3752, _T_3753) @[Cat.scala 29:58]
|
|
node _T_3765 = cat(_T_3764, _T_3754) @[Cat.scala 29:58]
|
|
node _T_3766 = cat(_T_3749, _T_3750) @[Cat.scala 29:58]
|
|
node _T_3767 = cat(_T_3766, _T_3751) @[Cat.scala 29:58]
|
|
node _T_3768 = cat(_T_3767, _T_3765) @[Cat.scala 29:58]
|
|
node _T_3769 = cat(_T_3768, _T_3763) @[Cat.scala 29:58]
|
|
node _T_3770 = bits(_T_3664, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3771 = cat(_T_3670[1], _T_3670[0]) @[el2_lib.scala 310:69]
|
|
node _T_3772 = cat(_T_3670[3], _T_3670[2]) @[el2_lib.scala 310:69]
|
|
node _T_3773 = cat(_T_3772, _T_3771) @[el2_lib.scala 310:69]
|
|
node _T_3774 = cat(_T_3670[5], _T_3670[4]) @[el2_lib.scala 310:69]
|
|
node _T_3775 = cat(_T_3670[8], _T_3670[7]) @[el2_lib.scala 310:69]
|
|
node _T_3776 = cat(_T_3775, _T_3670[6]) @[el2_lib.scala 310:69]
|
|
node _T_3777 = cat(_T_3776, _T_3774) @[el2_lib.scala 310:69]
|
|
node _T_3778 = cat(_T_3777, _T_3773) @[el2_lib.scala 310:69]
|
|
node _T_3779 = cat(_T_3670[10], _T_3670[9]) @[el2_lib.scala 310:69]
|
|
node _T_3780 = cat(_T_3670[13], _T_3670[12]) @[el2_lib.scala 310:69]
|
|
node _T_3781 = cat(_T_3780, _T_3670[11]) @[el2_lib.scala 310:69]
|
|
node _T_3782 = cat(_T_3781, _T_3779) @[el2_lib.scala 310:69]
|
|
node _T_3783 = cat(_T_3670[15], _T_3670[14]) @[el2_lib.scala 310:69]
|
|
node _T_3784 = cat(_T_3670[18], _T_3670[17]) @[el2_lib.scala 310:69]
|
|
node _T_3785 = cat(_T_3784, _T_3670[16]) @[el2_lib.scala 310:69]
|
|
node _T_3786 = cat(_T_3785, _T_3783) @[el2_lib.scala 310:69]
|
|
node _T_3787 = cat(_T_3786, _T_3782) @[el2_lib.scala 310:69]
|
|
node _T_3788 = cat(_T_3787, _T_3778) @[el2_lib.scala 310:69]
|
|
node _T_3789 = cat(_T_3670[20], _T_3670[19]) @[el2_lib.scala 310:69]
|
|
node _T_3790 = cat(_T_3670[23], _T_3670[22]) @[el2_lib.scala 310:69]
|
|
node _T_3791 = cat(_T_3790, _T_3670[21]) @[el2_lib.scala 310:69]
|
|
node _T_3792 = cat(_T_3791, _T_3789) @[el2_lib.scala 310:69]
|
|
node _T_3793 = cat(_T_3670[25], _T_3670[24]) @[el2_lib.scala 310:69]
|
|
node _T_3794 = cat(_T_3670[28], _T_3670[27]) @[el2_lib.scala 310:69]
|
|
node _T_3795 = cat(_T_3794, _T_3670[26]) @[el2_lib.scala 310:69]
|
|
node _T_3796 = cat(_T_3795, _T_3793) @[el2_lib.scala 310:69]
|
|
node _T_3797 = cat(_T_3796, _T_3792) @[el2_lib.scala 310:69]
|
|
node _T_3798 = cat(_T_3670[30], _T_3670[29]) @[el2_lib.scala 310:69]
|
|
node _T_3799 = cat(_T_3670[33], _T_3670[32]) @[el2_lib.scala 310:69]
|
|
node _T_3800 = cat(_T_3799, _T_3670[31]) @[el2_lib.scala 310:69]
|
|
node _T_3801 = cat(_T_3800, _T_3798) @[el2_lib.scala 310:69]
|
|
node _T_3802 = cat(_T_3670[35], _T_3670[34]) @[el2_lib.scala 310:69]
|
|
node _T_3803 = cat(_T_3670[38], _T_3670[37]) @[el2_lib.scala 310:69]
|
|
node _T_3804 = cat(_T_3803, _T_3670[36]) @[el2_lib.scala 310:69]
|
|
node _T_3805 = cat(_T_3804, _T_3802) @[el2_lib.scala 310:69]
|
|
node _T_3806 = cat(_T_3805, _T_3801) @[el2_lib.scala 310:69]
|
|
node _T_3807 = cat(_T_3806, _T_3797) @[el2_lib.scala 310:69]
|
|
node _T_3808 = cat(_T_3807, _T_3788) @[el2_lib.scala 310:69]
|
|
node _T_3809 = xor(_T_3808, _T_3769) @[el2_lib.scala 310:76]
|
|
node _T_3810 = mux(_T_3770, _T_3809, _T_3769) @[el2_lib.scala 310:31]
|
|
node _T_3811 = bits(_T_3810, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3812 = bits(_T_3810, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3813 = bits(_T_3810, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3814 = bits(_T_3810, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3815 = bits(_T_3810, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3816 = cat(_T_3814, _T_3815) @[Cat.scala 29:58]
|
|
node _T_3817 = cat(_T_3811, _T_3812) @[Cat.scala 29:58]
|
|
node _T_3818 = cat(_T_3817, _T_3813) @[Cat.scala 29:58]
|
|
node _T_3819 = cat(_T_3818, _T_3816) @[Cat.scala 29:58]
|
|
node _T_3820 = bits(_T_3810, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3821 = bits(_T_3660, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3822 = eq(_T_3821, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3823 = xor(_T_3820, _T_3822) @[el2_lib.scala 313:44]
|
|
node _T_3824 = bits(_T_3810, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3825 = bits(_T_3810, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3826 = bits(_T_3810, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3827 = bits(_T_3810, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3828 = bits(_T_3810, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3829 = cat(_T_3826, _T_3827) @[Cat.scala 29:58]
|
|
node _T_3830 = cat(_T_3829, _T_3828) @[Cat.scala 29:58]
|
|
node _T_3831 = cat(_T_3823, _T_3824) @[Cat.scala 29:58]
|
|
node _T_3832 = cat(_T_3831, _T_3825) @[Cat.scala 29:58]
|
|
node _T_3833 = cat(_T_3832, _T_3830) @[Cat.scala 29:58]
|
|
wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 710:32]
|
|
wire _T_3834 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 711:32]
|
|
_T_3834[0] <= _T_3448 @[el2_ifu_mem_ctl.scala 711:32]
|
|
_T_3834[1] <= _T_3833 @[el2_ifu_mem_ctl.scala 711:32]
|
|
iccm_corrected_ecc[0] <= _T_3834[0] @[el2_ifu_mem_ctl.scala 711:22]
|
|
iccm_corrected_ecc[1] <= _T_3834[1] @[el2_ifu_mem_ctl.scala 711:22]
|
|
wire _T_3835 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 712:33]
|
|
_T_3835[0] <= _T_3434 @[el2_ifu_mem_ctl.scala 712:33]
|
|
_T_3835[1] <= _T_3819 @[el2_ifu_mem_ctl.scala 712:33]
|
|
iccm_corrected_data[0] <= _T_3835[0] @[el2_ifu_mem_ctl.scala 712:23]
|
|
iccm_corrected_data[1] <= _T_3835[1] @[el2_ifu_mem_ctl.scala 712:23]
|
|
node _T_3836 = cat(_T_3279, _T_3664) @[Cat.scala 29:58]
|
|
iccm_single_ecc_error <= _T_3836 @[el2_ifu_mem_ctl.scala 713:25]
|
|
node _T_3837 = cat(_T_3284, _T_3669) @[Cat.scala 29:58]
|
|
iccm_double_ecc_error <= _T_3837 @[el2_ifu_mem_ctl.scala 714:25]
|
|
node _T_3838 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 715:54]
|
|
node _T_3839 = and(_T_3838, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 715:58]
|
|
node _T_3840 = and(_T_3839, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 715:78]
|
|
io.iccm_rd_ecc_single_err <= _T_3840 @[el2_ifu_mem_ctl.scala 715:29]
|
|
node _T_3841 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 716:54]
|
|
node _T_3842 = and(_T_3841, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 716:58]
|
|
io.iccm_rd_ecc_double_err <= _T_3842 @[el2_ifu_mem_ctl.scala 716:29]
|
|
node _T_3843 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 717:60]
|
|
node _T_3844 = bits(_T_3843, 0, 0) @[el2_ifu_mem_ctl.scala 717:64]
|
|
node iccm_corrected_data_f_mux = mux(_T_3844, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 717:38]
|
|
node _T_3845 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 718:59]
|
|
node _T_3846 = bits(_T_3845, 0, 0) @[el2_ifu_mem_ctl.scala 718:63]
|
|
node iccm_corrected_ecc_f_mux = mux(_T_3846, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 718:37]
|
|
wire iccm_rd_ecc_single_err_ff : UInt<1>
|
|
iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
|
|
node _T_3847 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:76]
|
|
node _T_3848 = and(io.iccm_rd_ecc_single_err, _T_3847) @[el2_ifu_mem_ctl.scala 720:74]
|
|
node _T_3849 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:106]
|
|
node _T_3850 = and(_T_3848, _T_3849) @[el2_ifu_mem_ctl.scala 720:104]
|
|
node iccm_ecc_write_status = or(_T_3850, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 720:127]
|
|
node _T_3851 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 721:67]
|
|
node _T_3852 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 721:98]
|
|
node iccm_rd_ecc_single_err_hold_in = and(_T_3851, _T_3852) @[el2_ifu_mem_ctl.scala 721:96]
|
|
iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 722:20]
|
|
wire iccm_rw_addr_f : UInt<14>
|
|
iccm_rw_addr_f <= UInt<1>("h00")
|
|
node _T_3853 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 724:57]
|
|
node _T_3854 = bits(_T_3853, 0, 0) @[el2_ifu_mem_ctl.scala 724:67]
|
|
node _T_3855 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:102]
|
|
node _T_3856 = tail(_T_3855, 1) @[el2_ifu_mem_ctl.scala 724:102]
|
|
node iccm_ecc_corr_index_in = mux(_T_3854, iccm_rw_addr_f, _T_3856) @[el2_ifu_mem_ctl.scala 724:35]
|
|
node _T_3857 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 725:67]
|
|
reg _T_3858 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 725:51]
|
|
_T_3858 <= _T_3857 @[el2_ifu_mem_ctl.scala 725:51]
|
|
iccm_rw_addr_f <= _T_3858 @[el2_ifu_mem_ctl.scala 725:18]
|
|
reg _T_3859 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 726:62]
|
|
_T_3859 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 726:62]
|
|
iccm_rd_ecc_single_err_ff <= _T_3859 @[el2_ifu_mem_ctl.scala 726:29]
|
|
node _T_3860 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
|
|
node _T_3861 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 727:152]
|
|
reg _T_3862 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3861 : @[Reg.scala 28:19]
|
|
_T_3862 <= _T_3860 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_data_ff <= _T_3862 @[el2_ifu_mem_ctl.scala 727:25]
|
|
node _T_3863 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 728:119]
|
|
reg _T_3864 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3863 : @[Reg.scala 28:19]
|
|
_T_3864 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_index_ff <= _T_3864 @[el2_ifu_mem_ctl.scala 728:26]
|
|
node _T_3865 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:41]
|
|
node _T_3866 = and(io.ifc_fetch_req_bf, _T_3865) @[el2_ifu_mem_ctl.scala 729:39]
|
|
node _T_3867 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:72]
|
|
node _T_3868 = and(_T_3866, _T_3867) @[el2_ifu_mem_ctl.scala 729:70]
|
|
node _T_3869 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 730:19]
|
|
node _T_3870 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:34]
|
|
node _T_3871 = and(_T_3869, _T_3870) @[el2_ifu_mem_ctl.scala 730:32]
|
|
node _T_3872 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 731:19]
|
|
node _T_3873 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 731:39]
|
|
node _T_3874 = and(_T_3872, _T_3873) @[el2_ifu_mem_ctl.scala 731:37]
|
|
node _T_3875 = or(_T_3871, _T_3874) @[el2_ifu_mem_ctl.scala 730:88]
|
|
node _T_3876 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 732:19]
|
|
node _T_3877 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 732:43]
|
|
node _T_3878 = and(_T_3876, _T_3877) @[el2_ifu_mem_ctl.scala 732:41]
|
|
node _T_3879 = or(_T_3875, _T_3878) @[el2_ifu_mem_ctl.scala 731:88]
|
|
node _T_3880 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 733:19]
|
|
node _T_3881 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 733:37]
|
|
node _T_3882 = and(_T_3880, _T_3881) @[el2_ifu_mem_ctl.scala 733:35]
|
|
node _T_3883 = or(_T_3879, _T_3882) @[el2_ifu_mem_ctl.scala 732:88]
|
|
node _T_3884 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 734:19]
|
|
node _T_3885 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:40]
|
|
node _T_3886 = and(_T_3884, _T_3885) @[el2_ifu_mem_ctl.scala 734:38]
|
|
node _T_3887 = or(_T_3883, _T_3886) @[el2_ifu_mem_ctl.scala 733:88]
|
|
node _T_3888 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 735:19]
|
|
node _T_3889 = and(_T_3888, miss_state_en) @[el2_ifu_mem_ctl.scala 735:37]
|
|
node _T_3890 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 735:71]
|
|
node _T_3891 = and(_T_3889, _T_3890) @[el2_ifu_mem_ctl.scala 735:54]
|
|
node _T_3892 = or(_T_3887, _T_3891) @[el2_ifu_mem_ctl.scala 734:57]
|
|
node _T_3893 = eq(_T_3892, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:5]
|
|
node _T_3894 = and(_T_3868, _T_3893) @[el2_ifu_mem_ctl.scala 729:96]
|
|
node _T_3895 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 736:28]
|
|
node _T_3896 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:52]
|
|
node _T_3897 = and(_T_3895, _T_3896) @[el2_ifu_mem_ctl.scala 736:50]
|
|
node _T_3898 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:83]
|
|
node _T_3899 = and(_T_3897, _T_3898) @[el2_ifu_mem_ctl.scala 736:81]
|
|
node _T_3900 = or(_T_3894, _T_3899) @[el2_ifu_mem_ctl.scala 735:93]
|
|
io.ic_rd_en <= _T_3900 @[el2_ifu_mem_ctl.scala 729:15]
|
|
wire bus_ic_wr_en : UInt<1>
|
|
bus_ic_wr_en <= UInt<1>("h00")
|
|
node _T_3901 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_3902 = mux(_T_3901, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_3903 = and(bus_ic_wr_en, _T_3902) @[el2_ifu_mem_ctl.scala 738:31]
|
|
io.ic_wr_en <= _T_3903 @[el2_ifu_mem_ctl.scala 738:15]
|
|
node _T_3904 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 739:59]
|
|
node _T_3905 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 739:91]
|
|
node _T_3906 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 739:127]
|
|
node _T_3907 = or(_T_3906, stream_eol_f) @[el2_ifu_mem_ctl.scala 739:151]
|
|
node _T_3908 = eq(_T_3907, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:106]
|
|
node _T_3909 = and(_T_3905, _T_3908) @[el2_ifu_mem_ctl.scala 739:104]
|
|
node _T_3910 = or(_T_3904, _T_3909) @[el2_ifu_mem_ctl.scala 739:77]
|
|
node _T_3911 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 739:191]
|
|
node _T_3912 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:205]
|
|
node _T_3913 = and(_T_3911, _T_3912) @[el2_ifu_mem_ctl.scala 739:203]
|
|
node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:172]
|
|
node _T_3915 = and(_T_3910, _T_3914) @[el2_ifu_mem_ctl.scala 739:170]
|
|
node _T_3916 = eq(_T_3915, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:44]
|
|
node _T_3917 = and(write_ic_16_bytes, _T_3916) @[el2_ifu_mem_ctl.scala 739:42]
|
|
io.ic_write_stall <= _T_3917 @[el2_ifu_mem_ctl.scala 739:21]
|
|
reg _T_3918 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 740:53]
|
|
_T_3918 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 740:53]
|
|
reset_all_tags <= _T_3918 @[el2_ifu_mem_ctl.scala 740:18]
|
|
node _T_3919 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:20]
|
|
node _T_3920 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 742:64]
|
|
node _T_3921 = eq(_T_3920, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:50]
|
|
node _T_3922 = and(_T_3919, _T_3921) @[el2_ifu_mem_ctl.scala 742:48]
|
|
node _T_3923 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:81]
|
|
node ic_valid = and(_T_3922, _T_3923) @[el2_ifu_mem_ctl.scala 742:79]
|
|
node _T_3924 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 743:61]
|
|
node _T_3925 = and(_T_3924, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 743:82]
|
|
node _T_3926 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 743:123]
|
|
node _T_3927 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 744:25]
|
|
node ifu_status_wr_addr_w_debug = mux(_T_3925, _T_3926, _T_3927) @[el2_ifu_mem_ctl.scala 743:41]
|
|
reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 746:14]
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 746:14]
|
|
wire way_status_wr_en : UInt<1>
|
|
way_status_wr_en <= UInt<1>("h00")
|
|
node _T_3928 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 749:74]
|
|
node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3928) @[el2_ifu_mem_ctl.scala 749:53]
|
|
reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 751:14]
|
|
way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 751:14]
|
|
wire way_status_new : UInt<1>
|
|
way_status_new <= UInt<1>("h00")
|
|
node _T_3929 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 754:56]
|
|
node _T_3930 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_3931 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 755:83]
|
|
node _T_3932 = mux(UInt<1>("h01"), _T_3930, _T_3931) @[el2_ifu_mem_ctl.scala 755:10]
|
|
node way_status_new_w_debug = mux(_T_3929, _T_3932, way_status_new) @[el2_ifu_mem_ctl.scala 754:37]
|
|
reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 757:14]
|
|
way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 757:14]
|
|
node _T_3933 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_0 = eq(_T_3933, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3934 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_1 = eq(_T_3934, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3935 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_2 = eq(_T_3935, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3936 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_3 = eq(_T_3936, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3937 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_4 = eq(_T_3937, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3938 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_5 = eq(_T_3938, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3939 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_6 = eq(_T_3939, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3940 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_7 = eq(_T_3940, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3941 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_8 = eq(_T_3941, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3942 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_9 = eq(_T_3942, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3943 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_10 = eq(_T_3943, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3944 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_11 = eq(_T_3944, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3945 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_12 = eq(_T_3945, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3946 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_13 = eq(_T_3946, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3947 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_14 = eq(_T_3947, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
node _T_3948 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 759:89]
|
|
node way_status_clken_15 = eq(_T_3948, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 759:132]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 417:22]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= reset
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_2.io.en <= way_status_clken_0 @[el2_lib.scala 419:16]
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 417:22]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= reset
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_3.io.en <= way_status_clken_1 @[el2_lib.scala 419:16]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 417:22]
|
|
rvclkhdr_4.clock <= clock
|
|
rvclkhdr_4.reset <= reset
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_4.io.en <= way_status_clken_2 @[el2_lib.scala 419:16]
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 417:22]
|
|
rvclkhdr_5.clock <= clock
|
|
rvclkhdr_5.reset <= reset
|
|
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_5.io.en <= way_status_clken_3 @[el2_lib.scala 419:16]
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 417:22]
|
|
rvclkhdr_6.clock <= clock
|
|
rvclkhdr_6.reset <= reset
|
|
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_6.io.en <= way_status_clken_4 @[el2_lib.scala 419:16]
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 417:22]
|
|
rvclkhdr_7.clock <= clock
|
|
rvclkhdr_7.reset <= reset
|
|
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_7.io.en <= way_status_clken_5 @[el2_lib.scala 419:16]
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 417:22]
|
|
rvclkhdr_8.clock <= clock
|
|
rvclkhdr_8.reset <= reset
|
|
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_8.io.en <= way_status_clken_6 @[el2_lib.scala 419:16]
|
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 417:22]
|
|
rvclkhdr_9.clock <= clock
|
|
rvclkhdr_9.reset <= reset
|
|
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_9.io.en <= way_status_clken_7 @[el2_lib.scala 419:16]
|
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 417:22]
|
|
rvclkhdr_10.clock <= clock
|
|
rvclkhdr_10.reset <= reset
|
|
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_10.io.en <= way_status_clken_8 @[el2_lib.scala 419:16]
|
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 417:22]
|
|
rvclkhdr_11.clock <= clock
|
|
rvclkhdr_11.reset <= reset
|
|
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_11.io.en <= way_status_clken_9 @[el2_lib.scala 419:16]
|
|
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 417:22]
|
|
rvclkhdr_12.clock <= clock
|
|
rvclkhdr_12.reset <= reset
|
|
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_12.io.en <= way_status_clken_10 @[el2_lib.scala 419:16]
|
|
rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 417:22]
|
|
rvclkhdr_13.clock <= clock
|
|
rvclkhdr_13.reset <= reset
|
|
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_13.io.en <= way_status_clken_11 @[el2_lib.scala 419:16]
|
|
rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 417:22]
|
|
rvclkhdr_14.clock <= clock
|
|
rvclkhdr_14.reset <= reset
|
|
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_14.io.en <= way_status_clken_12 @[el2_lib.scala 419:16]
|
|
rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 417:22]
|
|
rvclkhdr_15.clock <= clock
|
|
rvclkhdr_15.reset <= reset
|
|
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_15.io.en <= way_status_clken_13 @[el2_lib.scala 419:16]
|
|
rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 417:22]
|
|
rvclkhdr_16.clock <= clock
|
|
rvclkhdr_16.reset <= reset
|
|
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_16.io.en <= way_status_clken_14 @[el2_lib.scala 419:16]
|
|
rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 417:22]
|
|
rvclkhdr_17.clock <= clock
|
|
rvclkhdr_17.reset <= reset
|
|
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_17.io.en <= way_status_clken_15 @[el2_lib.scala 419:16]
|
|
rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 761:30]
|
|
node _T_3949 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3950 = and(_T_3949, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3951 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3950 : @[Reg.scala 28:19]
|
|
_T_3951 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[0] <= _T_3951 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3952 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3953 = and(_T_3952, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3954 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3953 : @[Reg.scala 28:19]
|
|
_T_3954 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[1] <= _T_3954 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3955 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3956 = and(_T_3955, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3957 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3956 : @[Reg.scala 28:19]
|
|
_T_3957 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[2] <= _T_3957 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3958 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3959 = and(_T_3958, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3960 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3959 : @[Reg.scala 28:19]
|
|
_T_3960 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[3] <= _T_3960 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3961 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3962 = and(_T_3961, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3963 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3962 : @[Reg.scala 28:19]
|
|
_T_3963 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[4] <= _T_3963 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3964 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3965 = and(_T_3964, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3966 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3965 : @[Reg.scala 28:19]
|
|
_T_3966 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[5] <= _T_3966 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3967 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3968 = and(_T_3967, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3969 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3968 : @[Reg.scala 28:19]
|
|
_T_3969 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[6] <= _T_3969 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3970 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3971 = and(_T_3970, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3972 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3971 : @[Reg.scala 28:19]
|
|
_T_3972 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[7] <= _T_3972 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3973 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3974 = and(_T_3973, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3975 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3974 : @[Reg.scala 28:19]
|
|
_T_3975 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[8] <= _T_3975 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3976 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3977 = and(_T_3976, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3978 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3977 : @[Reg.scala 28:19]
|
|
_T_3978 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[9] <= _T_3978 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3979 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3980 = and(_T_3979, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3981 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3980 : @[Reg.scala 28:19]
|
|
_T_3981 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[10] <= _T_3981 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3982 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3983 = and(_T_3982, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3984 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3983 : @[Reg.scala 28:19]
|
|
_T_3984 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[11] <= _T_3984 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3985 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3986 = and(_T_3985, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3987 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3986 : @[Reg.scala 28:19]
|
|
_T_3987 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[12] <= _T_3987 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3988 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3989 = and(_T_3988, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3990 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3989 : @[Reg.scala 28:19]
|
|
_T_3990 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[13] <= _T_3990 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3991 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3992 = and(_T_3991, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3993 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3992 : @[Reg.scala 28:19]
|
|
_T_3993 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[14] <= _T_3993 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3994 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3995 = and(_T_3994, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3996 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3995 : @[Reg.scala 28:19]
|
|
_T_3996 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[15] <= _T_3996 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_3997 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_3998 = and(_T_3997, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_3999 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3998 : @[Reg.scala 28:19]
|
|
_T_3999 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[16] <= _T_3999 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4000 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4001 = and(_T_4000, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4002 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4001 : @[Reg.scala 28:19]
|
|
_T_4002 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[17] <= _T_4002 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4003 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4004 = and(_T_4003, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4005 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4004 : @[Reg.scala 28:19]
|
|
_T_4005 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[18] <= _T_4005 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4006 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4007 = and(_T_4006, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4008 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4007 : @[Reg.scala 28:19]
|
|
_T_4008 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[19] <= _T_4008 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4009 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4010 = and(_T_4009, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4011 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4010 : @[Reg.scala 28:19]
|
|
_T_4011 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[20] <= _T_4011 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4012 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4013 = and(_T_4012, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4014 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4013 : @[Reg.scala 28:19]
|
|
_T_4014 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[21] <= _T_4014 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4015 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4016 = and(_T_4015, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4017 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4016 : @[Reg.scala 28:19]
|
|
_T_4017 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[22] <= _T_4017 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4018 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4019 = and(_T_4018, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4020 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4019 : @[Reg.scala 28:19]
|
|
_T_4020 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[23] <= _T_4020 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4021 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4022 = and(_T_4021, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4023 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4022 : @[Reg.scala 28:19]
|
|
_T_4023 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[24] <= _T_4023 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4024 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4026 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4025 : @[Reg.scala 28:19]
|
|
_T_4026 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[25] <= _T_4026 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4027 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4028 = and(_T_4027, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4029 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4028 : @[Reg.scala 28:19]
|
|
_T_4029 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[26] <= _T_4029 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4030 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4031 = and(_T_4030, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4032 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4031 : @[Reg.scala 28:19]
|
|
_T_4032 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[27] <= _T_4032 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4033 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4034 = and(_T_4033, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4035 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4034 : @[Reg.scala 28:19]
|
|
_T_4035 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[28] <= _T_4035 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4036 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4037 = and(_T_4036, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4038 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4037 : @[Reg.scala 28:19]
|
|
_T_4038 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[29] <= _T_4038 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4039 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4040 = and(_T_4039, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4041 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4040 : @[Reg.scala 28:19]
|
|
_T_4041 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[30] <= _T_4041 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4042 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4043 = and(_T_4042, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4044 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4043 : @[Reg.scala 28:19]
|
|
_T_4044 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[31] <= _T_4044 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4045 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4046 = and(_T_4045, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4047 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4046 : @[Reg.scala 28:19]
|
|
_T_4047 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[32] <= _T_4047 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4048 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4049 = and(_T_4048, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4050 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4049 : @[Reg.scala 28:19]
|
|
_T_4050 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[33] <= _T_4050 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4051 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4052 = and(_T_4051, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4053 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4052 : @[Reg.scala 28:19]
|
|
_T_4053 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[34] <= _T_4053 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4054 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4055 = and(_T_4054, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4056 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4055 : @[Reg.scala 28:19]
|
|
_T_4056 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[35] <= _T_4056 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4057 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4058 = and(_T_4057, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4059 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4058 : @[Reg.scala 28:19]
|
|
_T_4059 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[36] <= _T_4059 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4060 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4062 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4061 : @[Reg.scala 28:19]
|
|
_T_4062 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[37] <= _T_4062 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4063 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4064 = and(_T_4063, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4065 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4064 : @[Reg.scala 28:19]
|
|
_T_4065 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[38] <= _T_4065 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4066 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4067 = and(_T_4066, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4068 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4067 : @[Reg.scala 28:19]
|
|
_T_4068 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[39] <= _T_4068 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4069 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4070 = and(_T_4069, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4071 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4070 : @[Reg.scala 28:19]
|
|
_T_4071 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[40] <= _T_4071 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4072 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4073 = and(_T_4072, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4074 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4073 : @[Reg.scala 28:19]
|
|
_T_4074 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[41] <= _T_4074 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4075 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4076 = and(_T_4075, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4077 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4076 : @[Reg.scala 28:19]
|
|
_T_4077 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[42] <= _T_4077 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4078 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4079 = and(_T_4078, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4080 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4079 : @[Reg.scala 28:19]
|
|
_T_4080 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[43] <= _T_4080 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4081 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4082 = and(_T_4081, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4083 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4082 : @[Reg.scala 28:19]
|
|
_T_4083 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[44] <= _T_4083 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4084 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4086 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4085 : @[Reg.scala 28:19]
|
|
_T_4086 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[45] <= _T_4086 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4087 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4088 = and(_T_4087, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4089 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4088 : @[Reg.scala 28:19]
|
|
_T_4089 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[46] <= _T_4089 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4090 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4091 = and(_T_4090, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4092 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4091 : @[Reg.scala 28:19]
|
|
_T_4092 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[47] <= _T_4092 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4093 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4094 = and(_T_4093, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4095 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4094 : @[Reg.scala 28:19]
|
|
_T_4095 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[48] <= _T_4095 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4096 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4097 = and(_T_4096, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4098 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4097 : @[Reg.scala 28:19]
|
|
_T_4098 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[49] <= _T_4098 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4099 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4100 = and(_T_4099, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4101 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4100 : @[Reg.scala 28:19]
|
|
_T_4101 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[50] <= _T_4101 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4102 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4103 = and(_T_4102, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4104 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4103 : @[Reg.scala 28:19]
|
|
_T_4104 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[51] <= _T_4104 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4105 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4106 = and(_T_4105, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4107 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4106 : @[Reg.scala 28:19]
|
|
_T_4107 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[52] <= _T_4107 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4108 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4109 = and(_T_4108, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4110 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4109 : @[Reg.scala 28:19]
|
|
_T_4110 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[53] <= _T_4110 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4111 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4112 = and(_T_4111, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4113 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4112 : @[Reg.scala 28:19]
|
|
_T_4113 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[54] <= _T_4113 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4114 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4115 = and(_T_4114, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4116 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4115 : @[Reg.scala 28:19]
|
|
_T_4116 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[55] <= _T_4116 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4117 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4118 = and(_T_4117, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4119 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4118 : @[Reg.scala 28:19]
|
|
_T_4119 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[56] <= _T_4119 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4120 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4122 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4121 : @[Reg.scala 28:19]
|
|
_T_4122 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[57] <= _T_4122 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4123 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4124 = and(_T_4123, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4125 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4124 : @[Reg.scala 28:19]
|
|
_T_4125 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[58] <= _T_4125 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4126 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4127 = and(_T_4126, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4128 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4127 : @[Reg.scala 28:19]
|
|
_T_4128 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[59] <= _T_4128 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4129 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4130 = and(_T_4129, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4131 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4130 : @[Reg.scala 28:19]
|
|
_T_4131 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[60] <= _T_4131 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4132 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4133 = and(_T_4132, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4134 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4133 : @[Reg.scala 28:19]
|
|
_T_4134 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[61] <= _T_4134 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4135 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4136 = and(_T_4135, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4137 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4136 : @[Reg.scala 28:19]
|
|
_T_4137 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[62] <= _T_4137 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4138 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4139 = and(_T_4138, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4140 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4139 : @[Reg.scala 28:19]
|
|
_T_4140 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[63] <= _T_4140 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4141 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4142 = and(_T_4141, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4143 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4142 : @[Reg.scala 28:19]
|
|
_T_4143 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[64] <= _T_4143 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4144 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4146 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4145 : @[Reg.scala 28:19]
|
|
_T_4146 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[65] <= _T_4146 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4147 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4148 = and(_T_4147, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4149 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4148 : @[Reg.scala 28:19]
|
|
_T_4149 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[66] <= _T_4149 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4150 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4151 = and(_T_4150, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4152 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4151 : @[Reg.scala 28:19]
|
|
_T_4152 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[67] <= _T_4152 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4153 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4154 = and(_T_4153, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4155 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4154 : @[Reg.scala 28:19]
|
|
_T_4155 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[68] <= _T_4155 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4156 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4157 = and(_T_4156, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4158 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4157 : @[Reg.scala 28:19]
|
|
_T_4158 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[69] <= _T_4158 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4159 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4160 = and(_T_4159, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4161 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4160 : @[Reg.scala 28:19]
|
|
_T_4161 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[70] <= _T_4161 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4162 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4163 = and(_T_4162, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4164 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4163 : @[Reg.scala 28:19]
|
|
_T_4164 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[71] <= _T_4164 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4165 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4166 = and(_T_4165, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4167 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4166 : @[Reg.scala 28:19]
|
|
_T_4167 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[72] <= _T_4167 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4168 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4169 = and(_T_4168, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4170 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4169 : @[Reg.scala 28:19]
|
|
_T_4170 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[73] <= _T_4170 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4171 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4172 = and(_T_4171, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4173 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4172 : @[Reg.scala 28:19]
|
|
_T_4173 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[74] <= _T_4173 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4174 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4175 = and(_T_4174, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4176 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4175 : @[Reg.scala 28:19]
|
|
_T_4176 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[75] <= _T_4176 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4177 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4178 = and(_T_4177, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4179 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4178 : @[Reg.scala 28:19]
|
|
_T_4179 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[76] <= _T_4179 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4180 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4182 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4181 : @[Reg.scala 28:19]
|
|
_T_4182 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[77] <= _T_4182 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4183 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4184 = and(_T_4183, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4185 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4184 : @[Reg.scala 28:19]
|
|
_T_4185 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[78] <= _T_4185 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4186 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4187 = and(_T_4186, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4188 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4187 : @[Reg.scala 28:19]
|
|
_T_4188 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[79] <= _T_4188 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4189 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4190 = and(_T_4189, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4191 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4190 : @[Reg.scala 28:19]
|
|
_T_4191 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[80] <= _T_4191 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4192 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4193 = and(_T_4192, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4194 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4193 : @[Reg.scala 28:19]
|
|
_T_4194 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[81] <= _T_4194 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4195 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4196 = and(_T_4195, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4197 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4196 : @[Reg.scala 28:19]
|
|
_T_4197 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[82] <= _T_4197 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4198 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4199 = and(_T_4198, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4200 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4199 : @[Reg.scala 28:19]
|
|
_T_4200 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[83] <= _T_4200 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4201 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4202 = and(_T_4201, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4203 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4202 : @[Reg.scala 28:19]
|
|
_T_4203 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[84] <= _T_4203 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4204 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4206 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4205 : @[Reg.scala 28:19]
|
|
_T_4206 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[85] <= _T_4206 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4207 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4208 = and(_T_4207, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4209 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4208 : @[Reg.scala 28:19]
|
|
_T_4209 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[86] <= _T_4209 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4210 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4211 = and(_T_4210, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4212 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4211 : @[Reg.scala 28:19]
|
|
_T_4212 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[87] <= _T_4212 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4213 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4214 = and(_T_4213, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4215 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4214 : @[Reg.scala 28:19]
|
|
_T_4215 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[88] <= _T_4215 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4216 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4217 = and(_T_4216, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4218 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4217 : @[Reg.scala 28:19]
|
|
_T_4218 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[89] <= _T_4218 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4219 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4220 = and(_T_4219, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4221 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4220 : @[Reg.scala 28:19]
|
|
_T_4221 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[90] <= _T_4221 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4222 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4223 = and(_T_4222, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4224 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4223 : @[Reg.scala 28:19]
|
|
_T_4224 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[91] <= _T_4224 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4225 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4226 = and(_T_4225, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4227 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4226 : @[Reg.scala 28:19]
|
|
_T_4227 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[92] <= _T_4227 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4228 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4229 = and(_T_4228, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4230 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4229 : @[Reg.scala 28:19]
|
|
_T_4230 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[93] <= _T_4230 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4231 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4232 = and(_T_4231, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4233 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4232 : @[Reg.scala 28:19]
|
|
_T_4233 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[94] <= _T_4233 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4234 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4235 = and(_T_4234, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4236 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4235 : @[Reg.scala 28:19]
|
|
_T_4236 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[95] <= _T_4236 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4237 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4238 = and(_T_4237, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4239 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4238 : @[Reg.scala 28:19]
|
|
_T_4239 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[96] <= _T_4239 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4240 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4242 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4241 : @[Reg.scala 28:19]
|
|
_T_4242 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[97] <= _T_4242 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4243 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4244 = and(_T_4243, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4245 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4244 : @[Reg.scala 28:19]
|
|
_T_4245 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[98] <= _T_4245 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4246 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4247 = and(_T_4246, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4248 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4247 : @[Reg.scala 28:19]
|
|
_T_4248 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[99] <= _T_4248 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4249 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4250 = and(_T_4249, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4251 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4250 : @[Reg.scala 28:19]
|
|
_T_4251 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[100] <= _T_4251 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4252 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4253 = and(_T_4252, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4254 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4253 : @[Reg.scala 28:19]
|
|
_T_4254 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[101] <= _T_4254 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4255 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4256 = and(_T_4255, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4257 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4256 : @[Reg.scala 28:19]
|
|
_T_4257 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[102] <= _T_4257 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4258 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4259 = and(_T_4258, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4260 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4259 : @[Reg.scala 28:19]
|
|
_T_4260 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[103] <= _T_4260 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4261 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4262 = and(_T_4261, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4263 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4262 : @[Reg.scala 28:19]
|
|
_T_4263 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[104] <= _T_4263 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4264 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4266 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4265 : @[Reg.scala 28:19]
|
|
_T_4266 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[105] <= _T_4266 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4267 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4268 = and(_T_4267, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4269 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4268 : @[Reg.scala 28:19]
|
|
_T_4269 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[106] <= _T_4269 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4270 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4271 = and(_T_4270, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4272 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4271 : @[Reg.scala 28:19]
|
|
_T_4272 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[107] <= _T_4272 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4273 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4274 = and(_T_4273, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4275 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4274 : @[Reg.scala 28:19]
|
|
_T_4275 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[108] <= _T_4275 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4276 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4277 = and(_T_4276, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4278 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4277 : @[Reg.scala 28:19]
|
|
_T_4278 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[109] <= _T_4278 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4279 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4280 = and(_T_4279, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4281 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4280 : @[Reg.scala 28:19]
|
|
_T_4281 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[110] <= _T_4281 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4282 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4283 = and(_T_4282, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4284 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4283 : @[Reg.scala 28:19]
|
|
_T_4284 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[111] <= _T_4284 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4285 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4286 = and(_T_4285, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4287 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4286 : @[Reg.scala 28:19]
|
|
_T_4287 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[112] <= _T_4287 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4288 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4289 = and(_T_4288, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4290 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4289 : @[Reg.scala 28:19]
|
|
_T_4290 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[113] <= _T_4290 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4291 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4292 = and(_T_4291, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4293 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4292 : @[Reg.scala 28:19]
|
|
_T_4293 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[114] <= _T_4293 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4294 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4295 = and(_T_4294, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4296 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4295 : @[Reg.scala 28:19]
|
|
_T_4296 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[115] <= _T_4296 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4297 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4298 = and(_T_4297, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4299 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4298 : @[Reg.scala 28:19]
|
|
_T_4299 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[116] <= _T_4299 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4300 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4302 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4301 : @[Reg.scala 28:19]
|
|
_T_4302 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[117] <= _T_4302 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4303 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4304 = and(_T_4303, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4305 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4304 : @[Reg.scala 28:19]
|
|
_T_4305 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[118] <= _T_4305 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4306 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4307 = and(_T_4306, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4308 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4307 : @[Reg.scala 28:19]
|
|
_T_4308 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[119] <= _T_4308 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4309 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4310 = and(_T_4309, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4311 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4310 : @[Reg.scala 28:19]
|
|
_T_4311 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[120] <= _T_4311 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4312 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4313 = and(_T_4312, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4314 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4313 : @[Reg.scala 28:19]
|
|
_T_4314 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[121] <= _T_4314 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4315 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4316 = and(_T_4315, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4317 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4316 : @[Reg.scala 28:19]
|
|
_T_4317 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[122] <= _T_4317 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4318 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4319 = and(_T_4318, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4320 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4319 : @[Reg.scala 28:19]
|
|
_T_4320 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[123] <= _T_4320 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4321 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4322 = and(_T_4321, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4323 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4322 : @[Reg.scala 28:19]
|
|
_T_4323 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[124] <= _T_4323 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4324 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4326 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4325 : @[Reg.scala 28:19]
|
|
_T_4326 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[125] <= _T_4326 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4327 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4328 = and(_T_4327, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4329 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4328 : @[Reg.scala 28:19]
|
|
_T_4329 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[126] <= _T_4329 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4330 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:65]
|
|
node _T_4331 = and(_T_4330, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 764:73]
|
|
reg _T_4332 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4331 : @[Reg.scala 28:19]
|
|
_T_4332 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[127] <= _T_4332 @[el2_ifu_mem_ctl.scala 763:33]
|
|
node _T_4333 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4334 = bits(_T_4333, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4335 = mux(_T_4334, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4336 = and(_T_4335, way_status_out[0]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4337 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4338 = bits(_T_4337, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4339 = mux(_T_4338, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4340 = and(_T_4339, way_status_out[1]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4341 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4342 = bits(_T_4341, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4343 = mux(_T_4342, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4344 = and(_T_4343, way_status_out[2]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4345 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4346 = bits(_T_4345, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4347 = mux(_T_4346, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4348 = and(_T_4347, way_status_out[3]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4349 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4350 = bits(_T_4349, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4351 = mux(_T_4350, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4352 = and(_T_4351, way_status_out[4]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4353 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4354 = bits(_T_4353, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4355 = mux(_T_4354, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4356 = and(_T_4355, way_status_out[5]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4357 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4358 = bits(_T_4357, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4359 = mux(_T_4358, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4360 = and(_T_4359, way_status_out[6]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4361 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4362 = bits(_T_4361, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4363 = mux(_T_4362, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4364 = and(_T_4363, way_status_out[7]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4365 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4366 = bits(_T_4365, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4367 = mux(_T_4366, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4368 = and(_T_4367, way_status_out[8]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4369 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4370 = bits(_T_4369, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4371 = mux(_T_4370, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4372 = and(_T_4371, way_status_out[9]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4373 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4374 = bits(_T_4373, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4375 = mux(_T_4374, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4376 = and(_T_4375, way_status_out[10]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4377 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4378 = bits(_T_4377, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4379 = mux(_T_4378, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4380 = and(_T_4379, way_status_out[11]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4381 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4382 = bits(_T_4381, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4383 = mux(_T_4382, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4384 = and(_T_4383, way_status_out[12]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4385 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4386 = bits(_T_4385, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4387 = mux(_T_4386, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4388 = and(_T_4387, way_status_out[13]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4390 = bits(_T_4389, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4391 = mux(_T_4390, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4392 = and(_T_4391, way_status_out[14]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4394 = bits(_T_4393, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4395 = mux(_T_4394, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4396 = and(_T_4395, way_status_out[15]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4397 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4398 = bits(_T_4397, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4399 = mux(_T_4398, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4400 = and(_T_4399, way_status_out[16]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4401 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4402 = bits(_T_4401, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4403 = mux(_T_4402, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4404 = and(_T_4403, way_status_out[17]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4406 = bits(_T_4405, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4407 = mux(_T_4406, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4408 = and(_T_4407, way_status_out[18]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4410 = bits(_T_4409, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4411 = mux(_T_4410, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4412 = and(_T_4411, way_status_out[19]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4414 = bits(_T_4413, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4415 = mux(_T_4414, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4416 = and(_T_4415, way_status_out[20]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4418 = bits(_T_4417, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4419 = mux(_T_4418, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4420 = and(_T_4419, way_status_out[21]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4422 = bits(_T_4421, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4423 = mux(_T_4422, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4424 = and(_T_4423, way_status_out[22]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4426 = bits(_T_4425, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4427 = mux(_T_4426, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4428 = and(_T_4427, way_status_out[23]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4429 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4430 = bits(_T_4429, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4431 = mux(_T_4430, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4432 = and(_T_4431, way_status_out[24]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4433 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4434 = bits(_T_4433, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4435 = mux(_T_4434, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4436 = and(_T_4435, way_status_out[25]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4437 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4438 = bits(_T_4437, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4439 = mux(_T_4438, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4440 = and(_T_4439, way_status_out[26]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4441 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4442 = bits(_T_4441, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4443 = mux(_T_4442, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4444 = and(_T_4443, way_status_out[27]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4445 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4446 = bits(_T_4445, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4447 = mux(_T_4446, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4448 = and(_T_4447, way_status_out[28]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4449 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4450 = bits(_T_4449, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4451 = mux(_T_4450, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4452 = and(_T_4451, way_status_out[29]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4453 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4454 = bits(_T_4453, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4455 = mux(_T_4454, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4456 = and(_T_4455, way_status_out[30]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4457 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4458 = bits(_T_4457, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4459 = mux(_T_4458, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4460 = and(_T_4459, way_status_out[31]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4462 = bits(_T_4461, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4463 = mux(_T_4462, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4464 = and(_T_4463, way_status_out[32]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4466 = bits(_T_4465, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4467 = mux(_T_4466, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4468 = and(_T_4467, way_status_out[33]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4470 = bits(_T_4469, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4471 = mux(_T_4470, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4472 = and(_T_4471, way_status_out[34]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4474 = bits(_T_4473, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4475 = mux(_T_4474, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4476 = and(_T_4475, way_status_out[35]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4478 = bits(_T_4477, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4479 = mux(_T_4478, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4480 = and(_T_4479, way_status_out[36]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4482 = bits(_T_4481, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4483 = mux(_T_4482, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4484 = and(_T_4483, way_status_out[37]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4486 = bits(_T_4485, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4487 = mux(_T_4486, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4488 = and(_T_4487, way_status_out[38]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4490 = bits(_T_4489, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4491 = mux(_T_4490, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4492 = and(_T_4491, way_status_out[39]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4493 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4494 = bits(_T_4493, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4495 = mux(_T_4494, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4496 = and(_T_4495, way_status_out[40]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4498 = bits(_T_4497, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4499 = mux(_T_4498, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4500 = and(_T_4499, way_status_out[41]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4501 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4502 = bits(_T_4501, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4503 = mux(_T_4502, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4504 = and(_T_4503, way_status_out[42]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4506 = bits(_T_4505, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4507 = mux(_T_4506, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4508 = and(_T_4507, way_status_out[43]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4509 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4510 = bits(_T_4509, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4511 = mux(_T_4510, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4512 = and(_T_4511, way_status_out[44]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4513 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4514 = bits(_T_4513, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4515 = mux(_T_4514, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4516 = and(_T_4515, way_status_out[45]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4517 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4518 = bits(_T_4517, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4519 = mux(_T_4518, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4520 = and(_T_4519, way_status_out[46]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4521 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4522 = bits(_T_4521, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4523 = mux(_T_4522, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4524 = and(_T_4523, way_status_out[47]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4525 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4526 = bits(_T_4525, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4527 = mux(_T_4526, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4528 = and(_T_4527, way_status_out[48]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4529 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4530 = bits(_T_4529, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4531 = mux(_T_4530, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4532 = and(_T_4531, way_status_out[49]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4533 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4534 = bits(_T_4533, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4535 = mux(_T_4534, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4536 = and(_T_4535, way_status_out[50]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4537 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4538 = bits(_T_4537, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4539 = mux(_T_4538, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4540 = and(_T_4539, way_status_out[51]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4541 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4542 = bits(_T_4541, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4543 = mux(_T_4542, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4544 = and(_T_4543, way_status_out[52]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4545 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4546 = bits(_T_4545, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4547 = mux(_T_4546, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4548 = and(_T_4547, way_status_out[53]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4549 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4550 = bits(_T_4549, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4551 = mux(_T_4550, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4552 = and(_T_4551, way_status_out[54]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4553 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4554 = bits(_T_4553, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4555 = mux(_T_4554, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4556 = and(_T_4555, way_status_out[55]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4557 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4558 = bits(_T_4557, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4559 = mux(_T_4558, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4560 = and(_T_4559, way_status_out[56]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4561 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4562 = bits(_T_4561, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4563 = mux(_T_4562, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4564 = and(_T_4563, way_status_out[57]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4566 = bits(_T_4565, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4567 = mux(_T_4566, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4568 = and(_T_4567, way_status_out[58]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4569 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4570 = bits(_T_4569, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4571 = mux(_T_4570, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4572 = and(_T_4571, way_status_out[59]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4573 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4574 = bits(_T_4573, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4575 = mux(_T_4574, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4576 = and(_T_4575, way_status_out[60]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4577 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4578 = bits(_T_4577, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4579 = mux(_T_4578, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4580 = and(_T_4579, way_status_out[61]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4581 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4582 = bits(_T_4581, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4583 = mux(_T_4582, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4584 = and(_T_4583, way_status_out[62]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4585 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4586 = bits(_T_4585, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4587 = mux(_T_4586, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4588 = and(_T_4587, way_status_out[63]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4590 = bits(_T_4589, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4591 = mux(_T_4590, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4592 = and(_T_4591, way_status_out[64]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4594 = bits(_T_4593, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4595 = mux(_T_4594, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4596 = and(_T_4595, way_status_out[65]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4598 = bits(_T_4597, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4599 = mux(_T_4598, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4600 = and(_T_4599, way_status_out[66]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4602 = bits(_T_4601, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4603 = mux(_T_4602, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4604 = and(_T_4603, way_status_out[67]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4606 = bits(_T_4605, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4607 = mux(_T_4606, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4608 = and(_T_4607, way_status_out[68]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4610 = bits(_T_4609, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4611 = mux(_T_4610, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4612 = and(_T_4611, way_status_out[69]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4614 = bits(_T_4613, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4615 = mux(_T_4614, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4616 = and(_T_4615, way_status_out[70]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4618 = bits(_T_4617, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4619 = mux(_T_4618, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4620 = and(_T_4619, way_status_out[71]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4621 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4622 = bits(_T_4621, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4623 = mux(_T_4622, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4624 = and(_T_4623, way_status_out[72]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4625 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4626 = bits(_T_4625, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4627 = mux(_T_4626, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4628 = and(_T_4627, way_status_out[73]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4629 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4630 = bits(_T_4629, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4631 = mux(_T_4630, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4632 = and(_T_4631, way_status_out[74]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4633 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4634 = bits(_T_4633, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4635 = mux(_T_4634, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4636 = and(_T_4635, way_status_out[75]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4637 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4638 = bits(_T_4637, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4639 = mux(_T_4638, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4640 = and(_T_4639, way_status_out[76]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4641 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4642 = bits(_T_4641, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4643 = mux(_T_4642, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4644 = and(_T_4643, way_status_out[77]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4645 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4646 = bits(_T_4645, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4647 = mux(_T_4646, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4648 = and(_T_4647, way_status_out[78]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4649 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4650 = bits(_T_4649, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4651 = mux(_T_4650, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4652 = and(_T_4651, way_status_out[79]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4653 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4654 = bits(_T_4653, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4655 = mux(_T_4654, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4656 = and(_T_4655, way_status_out[80]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4657 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4658 = bits(_T_4657, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4659 = mux(_T_4658, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4660 = and(_T_4659, way_status_out[81]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4661 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4662 = bits(_T_4661, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4663 = mux(_T_4662, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4664 = and(_T_4663, way_status_out[82]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4665 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4666 = bits(_T_4665, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4667 = mux(_T_4666, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4668 = and(_T_4667, way_status_out[83]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4669 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4670 = bits(_T_4669, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4671 = mux(_T_4670, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4672 = and(_T_4671, way_status_out[84]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4674 = bits(_T_4673, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4675 = mux(_T_4674, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4676 = and(_T_4675, way_status_out[85]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4678 = bits(_T_4677, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4679 = mux(_T_4678, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4680 = and(_T_4679, way_status_out[86]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4682 = bits(_T_4681, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4683 = mux(_T_4682, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4684 = and(_T_4683, way_status_out[87]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4686 = bits(_T_4685, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4687 = mux(_T_4686, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4688 = and(_T_4687, way_status_out[88]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4690 = bits(_T_4689, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4691 = mux(_T_4690, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4692 = and(_T_4691, way_status_out[89]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4694 = bits(_T_4693, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4695 = mux(_T_4694, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4696 = and(_T_4695, way_status_out[90]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4698 = bits(_T_4697, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4699 = mux(_T_4698, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4700 = and(_T_4699, way_status_out[91]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4702 = bits(_T_4701, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4703 = mux(_T_4702, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4704 = and(_T_4703, way_status_out[92]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4706 = bits(_T_4705, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4707 = mux(_T_4706, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4708 = and(_T_4707, way_status_out[93]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4710 = bits(_T_4709, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4711 = mux(_T_4710, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4712 = and(_T_4711, way_status_out[94]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4714 = bits(_T_4713, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4715 = mux(_T_4714, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4716 = and(_T_4715, way_status_out[95]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4718 = bits(_T_4717, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4719 = mux(_T_4718, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4720 = and(_T_4719, way_status_out[96]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4722 = bits(_T_4721, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4723 = mux(_T_4722, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4724 = and(_T_4723, way_status_out[97]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4726 = bits(_T_4725, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4727 = mux(_T_4726, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4728 = and(_T_4727, way_status_out[98]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4730 = bits(_T_4729, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4731 = mux(_T_4730, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4732 = and(_T_4731, way_status_out[99]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4734 = bits(_T_4733, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4735 = mux(_T_4734, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4736 = and(_T_4735, way_status_out[100]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4738 = bits(_T_4737, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4739 = mux(_T_4738, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4740 = and(_T_4739, way_status_out[101]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4742 = bits(_T_4741, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4743 = mux(_T_4742, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4744 = and(_T_4743, way_status_out[102]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4746 = bits(_T_4745, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4747 = mux(_T_4746, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4748 = and(_T_4747, way_status_out[103]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4750 = bits(_T_4749, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4751 = mux(_T_4750, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4752 = and(_T_4751, way_status_out[104]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4754 = bits(_T_4753, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4755 = mux(_T_4754, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4756 = and(_T_4755, way_status_out[105]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4758 = bits(_T_4757, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4759 = mux(_T_4758, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4760 = and(_T_4759, way_status_out[106]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4762 = bits(_T_4761, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4763 = mux(_T_4762, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4764 = and(_T_4763, way_status_out[107]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4766 = bits(_T_4765, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4767 = mux(_T_4766, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4768 = and(_T_4767, way_status_out[108]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4770 = bits(_T_4769, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4771 = mux(_T_4770, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4772 = and(_T_4771, way_status_out[109]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4774 = bits(_T_4773, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4775 = mux(_T_4774, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4776 = and(_T_4775, way_status_out[110]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4778 = bits(_T_4777, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4779 = mux(_T_4778, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4780 = and(_T_4779, way_status_out[111]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4782 = bits(_T_4781, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4783 = mux(_T_4782, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4784 = and(_T_4783, way_status_out[112]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4786 = bits(_T_4785, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4787 = mux(_T_4786, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4788 = and(_T_4787, way_status_out[113]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4790 = bits(_T_4789, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4791 = mux(_T_4790, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4792 = and(_T_4791, way_status_out[114]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4794 = bits(_T_4793, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4795 = mux(_T_4794, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4796 = and(_T_4795, way_status_out[115]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4798 = bits(_T_4797, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4799 = mux(_T_4798, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4800 = and(_T_4799, way_status_out[116]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4801 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4802 = bits(_T_4801, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4803 = mux(_T_4802, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4804 = and(_T_4803, way_status_out[117]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4805 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4806 = bits(_T_4805, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4807 = mux(_T_4806, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4808 = and(_T_4807, way_status_out[118]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4809 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4810 = bits(_T_4809, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4811 = mux(_T_4810, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4812 = and(_T_4811, way_status_out[119]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4813 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4814 = bits(_T_4813, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4815 = mux(_T_4814, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4816 = and(_T_4815, way_status_out[120]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4817 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4818 = bits(_T_4817, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4819 = mux(_T_4818, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4820 = and(_T_4819, way_status_out[121]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4821 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4822 = bits(_T_4821, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4823 = mux(_T_4822, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4824 = and(_T_4823, way_status_out[122]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4826 = bits(_T_4825, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4827 = mux(_T_4826, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4828 = and(_T_4827, way_status_out[123]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4829 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4830 = bits(_T_4829, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4831 = mux(_T_4830, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4832 = and(_T_4831, way_status_out[124]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4833 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4834 = bits(_T_4833, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4835 = mux(_T_4834, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4836 = and(_T_4835, way_status_out[125]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4837 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4838 = bits(_T_4837, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4839 = mux(_T_4838, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4840 = and(_T_4839, way_status_out[126]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4841 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 766:121]
|
|
node _T_4842 = bits(_T_4841, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4843 = mux(_T_4842, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4844 = and(_T_4843, way_status_out[127]) @[el2_ifu_mem_ctl.scala 766:130]
|
|
node _T_4845 = cat(_T_4844, _T_4840) @[Cat.scala 29:58]
|
|
node _T_4846 = cat(_T_4845, _T_4836) @[Cat.scala 29:58]
|
|
node _T_4847 = cat(_T_4846, _T_4832) @[Cat.scala 29:58]
|
|
node _T_4848 = cat(_T_4847, _T_4828) @[Cat.scala 29:58]
|
|
node _T_4849 = cat(_T_4848, _T_4824) @[Cat.scala 29:58]
|
|
node _T_4850 = cat(_T_4849, _T_4820) @[Cat.scala 29:58]
|
|
node _T_4851 = cat(_T_4850, _T_4816) @[Cat.scala 29:58]
|
|
node _T_4852 = cat(_T_4851, _T_4812) @[Cat.scala 29:58]
|
|
node _T_4853 = cat(_T_4852, _T_4808) @[Cat.scala 29:58]
|
|
node _T_4854 = cat(_T_4853, _T_4804) @[Cat.scala 29:58]
|
|
node _T_4855 = cat(_T_4854, _T_4800) @[Cat.scala 29:58]
|
|
node _T_4856 = cat(_T_4855, _T_4796) @[Cat.scala 29:58]
|
|
node _T_4857 = cat(_T_4856, _T_4792) @[Cat.scala 29:58]
|
|
node _T_4858 = cat(_T_4857, _T_4788) @[Cat.scala 29:58]
|
|
node _T_4859 = cat(_T_4858, _T_4784) @[Cat.scala 29:58]
|
|
node _T_4860 = cat(_T_4859, _T_4780) @[Cat.scala 29:58]
|
|
node _T_4861 = cat(_T_4860, _T_4776) @[Cat.scala 29:58]
|
|
node _T_4862 = cat(_T_4861, _T_4772) @[Cat.scala 29:58]
|
|
node _T_4863 = cat(_T_4862, _T_4768) @[Cat.scala 29:58]
|
|
node _T_4864 = cat(_T_4863, _T_4764) @[Cat.scala 29:58]
|
|
node _T_4865 = cat(_T_4864, _T_4760) @[Cat.scala 29:58]
|
|
node _T_4866 = cat(_T_4865, _T_4756) @[Cat.scala 29:58]
|
|
node _T_4867 = cat(_T_4866, _T_4752) @[Cat.scala 29:58]
|
|
node _T_4868 = cat(_T_4867, _T_4748) @[Cat.scala 29:58]
|
|
node _T_4869 = cat(_T_4868, _T_4744) @[Cat.scala 29:58]
|
|
node _T_4870 = cat(_T_4869, _T_4740) @[Cat.scala 29:58]
|
|
node _T_4871 = cat(_T_4870, _T_4736) @[Cat.scala 29:58]
|
|
node _T_4872 = cat(_T_4871, _T_4732) @[Cat.scala 29:58]
|
|
node _T_4873 = cat(_T_4872, _T_4728) @[Cat.scala 29:58]
|
|
node _T_4874 = cat(_T_4873, _T_4724) @[Cat.scala 29:58]
|
|
node _T_4875 = cat(_T_4874, _T_4720) @[Cat.scala 29:58]
|
|
node _T_4876 = cat(_T_4875, _T_4716) @[Cat.scala 29:58]
|
|
node _T_4877 = cat(_T_4876, _T_4712) @[Cat.scala 29:58]
|
|
node _T_4878 = cat(_T_4877, _T_4708) @[Cat.scala 29:58]
|
|
node _T_4879 = cat(_T_4878, _T_4704) @[Cat.scala 29:58]
|
|
node _T_4880 = cat(_T_4879, _T_4700) @[Cat.scala 29:58]
|
|
node _T_4881 = cat(_T_4880, _T_4696) @[Cat.scala 29:58]
|
|
node _T_4882 = cat(_T_4881, _T_4692) @[Cat.scala 29:58]
|
|
node _T_4883 = cat(_T_4882, _T_4688) @[Cat.scala 29:58]
|
|
node _T_4884 = cat(_T_4883, _T_4684) @[Cat.scala 29:58]
|
|
node _T_4885 = cat(_T_4884, _T_4680) @[Cat.scala 29:58]
|
|
node _T_4886 = cat(_T_4885, _T_4676) @[Cat.scala 29:58]
|
|
node _T_4887 = cat(_T_4886, _T_4672) @[Cat.scala 29:58]
|
|
node _T_4888 = cat(_T_4887, _T_4668) @[Cat.scala 29:58]
|
|
node _T_4889 = cat(_T_4888, _T_4664) @[Cat.scala 29:58]
|
|
node _T_4890 = cat(_T_4889, _T_4660) @[Cat.scala 29:58]
|
|
node _T_4891 = cat(_T_4890, _T_4656) @[Cat.scala 29:58]
|
|
node _T_4892 = cat(_T_4891, _T_4652) @[Cat.scala 29:58]
|
|
node _T_4893 = cat(_T_4892, _T_4648) @[Cat.scala 29:58]
|
|
node _T_4894 = cat(_T_4893, _T_4644) @[Cat.scala 29:58]
|
|
node _T_4895 = cat(_T_4894, _T_4640) @[Cat.scala 29:58]
|
|
node _T_4896 = cat(_T_4895, _T_4636) @[Cat.scala 29:58]
|
|
node _T_4897 = cat(_T_4896, _T_4632) @[Cat.scala 29:58]
|
|
node _T_4898 = cat(_T_4897, _T_4628) @[Cat.scala 29:58]
|
|
node _T_4899 = cat(_T_4898, _T_4624) @[Cat.scala 29:58]
|
|
node _T_4900 = cat(_T_4899, _T_4620) @[Cat.scala 29:58]
|
|
node _T_4901 = cat(_T_4900, _T_4616) @[Cat.scala 29:58]
|
|
node _T_4902 = cat(_T_4901, _T_4612) @[Cat.scala 29:58]
|
|
node _T_4903 = cat(_T_4902, _T_4608) @[Cat.scala 29:58]
|
|
node _T_4904 = cat(_T_4903, _T_4604) @[Cat.scala 29:58]
|
|
node _T_4905 = cat(_T_4904, _T_4600) @[Cat.scala 29:58]
|
|
node _T_4906 = cat(_T_4905, _T_4596) @[Cat.scala 29:58]
|
|
node _T_4907 = cat(_T_4906, _T_4592) @[Cat.scala 29:58]
|
|
node _T_4908 = cat(_T_4907, _T_4588) @[Cat.scala 29:58]
|
|
node _T_4909 = cat(_T_4908, _T_4584) @[Cat.scala 29:58]
|
|
node _T_4910 = cat(_T_4909, _T_4580) @[Cat.scala 29:58]
|
|
node _T_4911 = cat(_T_4910, _T_4576) @[Cat.scala 29:58]
|
|
node _T_4912 = cat(_T_4911, _T_4572) @[Cat.scala 29:58]
|
|
node _T_4913 = cat(_T_4912, _T_4568) @[Cat.scala 29:58]
|
|
node _T_4914 = cat(_T_4913, _T_4564) @[Cat.scala 29:58]
|
|
node _T_4915 = cat(_T_4914, _T_4560) @[Cat.scala 29:58]
|
|
node _T_4916 = cat(_T_4915, _T_4556) @[Cat.scala 29:58]
|
|
node _T_4917 = cat(_T_4916, _T_4552) @[Cat.scala 29:58]
|
|
node _T_4918 = cat(_T_4917, _T_4548) @[Cat.scala 29:58]
|
|
node _T_4919 = cat(_T_4918, _T_4544) @[Cat.scala 29:58]
|
|
node _T_4920 = cat(_T_4919, _T_4540) @[Cat.scala 29:58]
|
|
node _T_4921 = cat(_T_4920, _T_4536) @[Cat.scala 29:58]
|
|
node _T_4922 = cat(_T_4921, _T_4532) @[Cat.scala 29:58]
|
|
node _T_4923 = cat(_T_4922, _T_4528) @[Cat.scala 29:58]
|
|
node _T_4924 = cat(_T_4923, _T_4524) @[Cat.scala 29:58]
|
|
node _T_4925 = cat(_T_4924, _T_4520) @[Cat.scala 29:58]
|
|
node _T_4926 = cat(_T_4925, _T_4516) @[Cat.scala 29:58]
|
|
node _T_4927 = cat(_T_4926, _T_4512) @[Cat.scala 29:58]
|
|
node _T_4928 = cat(_T_4927, _T_4508) @[Cat.scala 29:58]
|
|
node _T_4929 = cat(_T_4928, _T_4504) @[Cat.scala 29:58]
|
|
node _T_4930 = cat(_T_4929, _T_4500) @[Cat.scala 29:58]
|
|
node _T_4931 = cat(_T_4930, _T_4496) @[Cat.scala 29:58]
|
|
node _T_4932 = cat(_T_4931, _T_4492) @[Cat.scala 29:58]
|
|
node _T_4933 = cat(_T_4932, _T_4488) @[Cat.scala 29:58]
|
|
node _T_4934 = cat(_T_4933, _T_4484) @[Cat.scala 29:58]
|
|
node _T_4935 = cat(_T_4934, _T_4480) @[Cat.scala 29:58]
|
|
node _T_4936 = cat(_T_4935, _T_4476) @[Cat.scala 29:58]
|
|
node _T_4937 = cat(_T_4936, _T_4472) @[Cat.scala 29:58]
|
|
node _T_4938 = cat(_T_4937, _T_4468) @[Cat.scala 29:58]
|
|
node _T_4939 = cat(_T_4938, _T_4464) @[Cat.scala 29:58]
|
|
node _T_4940 = cat(_T_4939, _T_4460) @[Cat.scala 29:58]
|
|
node _T_4941 = cat(_T_4940, _T_4456) @[Cat.scala 29:58]
|
|
node _T_4942 = cat(_T_4941, _T_4452) @[Cat.scala 29:58]
|
|
node _T_4943 = cat(_T_4942, _T_4448) @[Cat.scala 29:58]
|
|
node _T_4944 = cat(_T_4943, _T_4444) @[Cat.scala 29:58]
|
|
node _T_4945 = cat(_T_4944, _T_4440) @[Cat.scala 29:58]
|
|
node _T_4946 = cat(_T_4945, _T_4436) @[Cat.scala 29:58]
|
|
node _T_4947 = cat(_T_4946, _T_4432) @[Cat.scala 29:58]
|
|
node _T_4948 = cat(_T_4947, _T_4428) @[Cat.scala 29:58]
|
|
node _T_4949 = cat(_T_4948, _T_4424) @[Cat.scala 29:58]
|
|
node _T_4950 = cat(_T_4949, _T_4420) @[Cat.scala 29:58]
|
|
node _T_4951 = cat(_T_4950, _T_4416) @[Cat.scala 29:58]
|
|
node _T_4952 = cat(_T_4951, _T_4412) @[Cat.scala 29:58]
|
|
node _T_4953 = cat(_T_4952, _T_4408) @[Cat.scala 29:58]
|
|
node _T_4954 = cat(_T_4953, _T_4404) @[Cat.scala 29:58]
|
|
node _T_4955 = cat(_T_4954, _T_4400) @[Cat.scala 29:58]
|
|
node _T_4956 = cat(_T_4955, _T_4396) @[Cat.scala 29:58]
|
|
node _T_4957 = cat(_T_4956, _T_4392) @[Cat.scala 29:58]
|
|
node _T_4958 = cat(_T_4957, _T_4388) @[Cat.scala 29:58]
|
|
node _T_4959 = cat(_T_4958, _T_4384) @[Cat.scala 29:58]
|
|
node _T_4960 = cat(_T_4959, _T_4380) @[Cat.scala 29:58]
|
|
node _T_4961 = cat(_T_4960, _T_4376) @[Cat.scala 29:58]
|
|
node _T_4962 = cat(_T_4961, _T_4372) @[Cat.scala 29:58]
|
|
node _T_4963 = cat(_T_4962, _T_4368) @[Cat.scala 29:58]
|
|
node _T_4964 = cat(_T_4963, _T_4364) @[Cat.scala 29:58]
|
|
node _T_4965 = cat(_T_4964, _T_4360) @[Cat.scala 29:58]
|
|
node _T_4966 = cat(_T_4965, _T_4356) @[Cat.scala 29:58]
|
|
node _T_4967 = cat(_T_4966, _T_4352) @[Cat.scala 29:58]
|
|
node _T_4968 = cat(_T_4967, _T_4348) @[Cat.scala 29:58]
|
|
node _T_4969 = cat(_T_4968, _T_4344) @[Cat.scala 29:58]
|
|
node _T_4970 = cat(_T_4969, _T_4340) @[Cat.scala 29:58]
|
|
node _T_4971 = cat(_T_4970, _T_4336) @[Cat.scala 29:58]
|
|
way_status <= _T_4971 @[el2_ifu_mem_ctl.scala 766:16]
|
|
node _T_4972 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 767:61]
|
|
node _T_4973 = and(_T_4972, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 767:82]
|
|
node _T_4974 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 768:23]
|
|
node _T_4975 = bits(ic_rw_addr, 11, 5) @[el2_ifu_mem_ctl.scala 768:89]
|
|
node ifu_ic_rw_int_addr_w_debug = mux(_T_4973, _T_4974, _T_4975) @[el2_ifu_mem_ctl.scala 767:41]
|
|
reg _T_4976 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 770:14]
|
|
_T_4976 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 770:14]
|
|
ifu_ic_rw_int_addr_ff <= _T_4976 @[el2_ifu_mem_ctl.scala 769:27]
|
|
wire ifu_tag_wren : UInt<2>
|
|
ifu_tag_wren <= UInt<1>("h00")
|
|
wire ic_debug_tag_wr_en : UInt<2>
|
|
ic_debug_tag_wr_en <= UInt<1>("h00")
|
|
node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 774:45]
|
|
reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 776:14]
|
|
ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 776:14]
|
|
node _T_4977 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 778:50]
|
|
node _T_4978 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 778:94]
|
|
node ic_valid_w_debug = mux(_T_4977, _T_4978, ic_valid) @[el2_ifu_mem_ctl.scala 778:31]
|
|
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 780:14]
|
|
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 780:14]
|
|
node _T_4979 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_4980 = eq(_T_4979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_4981 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_4982 = and(_T_4980, _T_4981) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_4983 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_4984 = eq(_T_4983, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_4985 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_4986 = and(_T_4984, _T_4985) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_4987 = or(_T_4982, _T_4986) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_4988 = or(_T_4987, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node _T_4989 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_4990 = eq(_T_4989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_4991 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_4992 = and(_T_4990, _T_4991) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_4993 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_4994 = eq(_T_4993, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_4995 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_4996 = and(_T_4994, _T_4995) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_4997 = or(_T_4992, _T_4996) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_4998 = or(_T_4997, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node tag_valid_clken_0 = cat(_T_4988, _T_4998) @[Cat.scala 29:58]
|
|
node _T_4999 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5000 = eq(_T_4999, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5001 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5002 = and(_T_5000, _T_5001) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5003 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5004 = eq(_T_5003, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5005 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5006 = and(_T_5004, _T_5005) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5007 = or(_T_5002, _T_5006) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5008 = or(_T_5007, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node _T_5009 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5010 = eq(_T_5009, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5012 = and(_T_5010, _T_5011) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5013 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5014 = eq(_T_5013, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5015 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5016 = and(_T_5014, _T_5015) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5017 = or(_T_5012, _T_5016) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5018 = or(_T_5017, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node tag_valid_clken_1 = cat(_T_5008, _T_5018) @[Cat.scala 29:58]
|
|
node _T_5019 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5020 = eq(_T_5019, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5021 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5022 = and(_T_5020, _T_5021) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5023 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5024 = eq(_T_5023, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5025 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5026 = and(_T_5024, _T_5025) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5027 = or(_T_5022, _T_5026) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5028 = or(_T_5027, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node _T_5029 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5030 = eq(_T_5029, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5031 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5032 = and(_T_5030, _T_5031) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5033 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5034 = eq(_T_5033, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5035 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5036 = and(_T_5034, _T_5035) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5037 = or(_T_5032, _T_5036) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5038 = or(_T_5037, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node tag_valid_clken_2 = cat(_T_5028, _T_5038) @[Cat.scala 29:58]
|
|
node _T_5039 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5040 = eq(_T_5039, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5041 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5042 = and(_T_5040, _T_5041) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5043 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5044 = eq(_T_5043, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5045 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5046 = and(_T_5044, _T_5045) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5047 = or(_T_5042, _T_5046) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5048 = or(_T_5047, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node _T_5049 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 784:35]
|
|
node _T_5050 = eq(_T_5049, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 784:82]
|
|
node _T_5051 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:108]
|
|
node _T_5052 = and(_T_5050, _T_5051) @[el2_ifu_mem_ctl.scala 784:91]
|
|
node _T_5053 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 785:27]
|
|
node _T_5054 = eq(_T_5053, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 785:74]
|
|
node _T_5055 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 785:101]
|
|
node _T_5056 = and(_T_5054, _T_5055) @[el2_ifu_mem_ctl.scala 785:83]
|
|
node _T_5057 = or(_T_5052, _T_5056) @[el2_ifu_mem_ctl.scala 784:113]
|
|
node _T_5058 = or(_T_5057, reset_all_tags) @[el2_ifu_mem_ctl.scala 785:106]
|
|
node tag_valid_clken_3 = cat(_T_5048, _T_5058) @[Cat.scala 29:58]
|
|
node _T_5059 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 417:22]
|
|
rvclkhdr_18.clock <= clock
|
|
rvclkhdr_18.reset <= reset
|
|
rvclkhdr_18.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_18.io.en <= _T_5059 @[el2_lib.scala 419:16]
|
|
rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5060 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 417:22]
|
|
rvclkhdr_19.clock <= clock
|
|
rvclkhdr_19.reset <= reset
|
|
rvclkhdr_19.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_19.io.en <= _T_5060 @[el2_lib.scala 419:16]
|
|
rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5061 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 417:22]
|
|
rvclkhdr_20.clock <= clock
|
|
rvclkhdr_20.reset <= reset
|
|
rvclkhdr_20.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_20.io.en <= _T_5061 @[el2_lib.scala 419:16]
|
|
rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5062 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 417:22]
|
|
rvclkhdr_21.clock <= clock
|
|
rvclkhdr_21.reset <= reset
|
|
rvclkhdr_21.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_21.io.en <= _T_5062 @[el2_lib.scala 419:16]
|
|
rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5063 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 417:22]
|
|
rvclkhdr_22.clock <= clock
|
|
rvclkhdr_22.reset <= reset
|
|
rvclkhdr_22.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_22.io.en <= _T_5063 @[el2_lib.scala 419:16]
|
|
rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5064 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 417:22]
|
|
rvclkhdr_23.clock <= clock
|
|
rvclkhdr_23.reset <= reset
|
|
rvclkhdr_23.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_23.io.en <= _T_5064 @[el2_lib.scala 419:16]
|
|
rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5065 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 417:22]
|
|
rvclkhdr_24.clock <= clock
|
|
rvclkhdr_24.reset <= reset
|
|
rvclkhdr_24.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_24.io.en <= _T_5065 @[el2_lib.scala 419:16]
|
|
rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
node _T_5066 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 787:135]
|
|
inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 417:22]
|
|
rvclkhdr_25.clock <= clock
|
|
rvclkhdr_25.reset <= reset
|
|
rvclkhdr_25.io.clk <= clock @[el2_lib.scala 418:17]
|
|
rvclkhdr_25.io.en <= _T_5066 @[el2_lib.scala 419:16]
|
|
rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 420:23]
|
|
wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 788:32]
|
|
node _T_5067 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5068 = eq(_T_5067, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5069 = and(ic_valid_ff, _T_5068) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5070 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5071 = and(_T_5069, _T_5070) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5072 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5073 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5074 = and(_T_5072, _T_5073) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5075 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5076 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5077 = and(_T_5075, _T_5076) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5078 = or(_T_5074, _T_5077) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5079 = bits(_T_5078, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5080 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5079 : @[Reg.scala 28:19]
|
|
_T_5080 <= _T_5071 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][0] <= _T_5080 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5081 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5082 = eq(_T_5081, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5083 = and(ic_valid_ff, _T_5082) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5084 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5085 = and(_T_5083, _T_5084) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5086 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5087 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5088 = and(_T_5086, _T_5087) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5089 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5090 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5091 = and(_T_5089, _T_5090) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5092 = or(_T_5088, _T_5091) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5093 = bits(_T_5092, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5094 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5093 : @[Reg.scala 28:19]
|
|
_T_5094 <= _T_5085 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][1] <= _T_5094 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5095 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5096 = eq(_T_5095, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5097 = and(ic_valid_ff, _T_5096) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5099 = and(_T_5097, _T_5098) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5100 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5101 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5102 = and(_T_5100, _T_5101) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5103 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5104 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5105 = and(_T_5103, _T_5104) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5106 = or(_T_5102, _T_5105) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5107 = bits(_T_5106, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5108 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5107 : @[Reg.scala 28:19]
|
|
_T_5108 <= _T_5099 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][2] <= _T_5108 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5110 = eq(_T_5109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5111 = and(ic_valid_ff, _T_5110) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5113 = and(_T_5111, _T_5112) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5114 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5115 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5116 = and(_T_5114, _T_5115) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5117 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5118 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5119 = and(_T_5117, _T_5118) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5120 = or(_T_5116, _T_5119) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5121 = bits(_T_5120, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5122 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5121 : @[Reg.scala 28:19]
|
|
_T_5122 <= _T_5113 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][3] <= _T_5122 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5123 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5124 = eq(_T_5123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5125 = and(ic_valid_ff, _T_5124) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5126 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5127 = and(_T_5125, _T_5126) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5128 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5129 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5130 = and(_T_5128, _T_5129) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5131 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5132 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5133 = and(_T_5131, _T_5132) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5134 = or(_T_5130, _T_5133) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5135 = bits(_T_5134, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5136 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5135 : @[Reg.scala 28:19]
|
|
_T_5136 <= _T_5127 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][4] <= _T_5136 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5137 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5138 = eq(_T_5137, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5139 = and(ic_valid_ff, _T_5138) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5140 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5141 = and(_T_5139, _T_5140) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5142 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5143 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5144 = and(_T_5142, _T_5143) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5145 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5146 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5147 = and(_T_5145, _T_5146) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5148 = or(_T_5144, _T_5147) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5149 = bits(_T_5148, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5150 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5149 : @[Reg.scala 28:19]
|
|
_T_5150 <= _T_5141 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][5] <= _T_5150 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5151 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5152 = eq(_T_5151, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5153 = and(ic_valid_ff, _T_5152) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5154 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5155 = and(_T_5153, _T_5154) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5156 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5157 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5158 = and(_T_5156, _T_5157) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5159 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5160 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5161 = and(_T_5159, _T_5160) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5162 = or(_T_5158, _T_5161) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5163 = bits(_T_5162, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5164 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5163 : @[Reg.scala 28:19]
|
|
_T_5164 <= _T_5155 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][6] <= _T_5164 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5165 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5166 = eq(_T_5165, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5167 = and(ic_valid_ff, _T_5166) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5169 = and(_T_5167, _T_5168) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5170 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5172 = and(_T_5170, _T_5171) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5173 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5174 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5175 = and(_T_5173, _T_5174) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5176 = or(_T_5172, _T_5175) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5177 = bits(_T_5176, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5178 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5177 : @[Reg.scala 28:19]
|
|
_T_5178 <= _T_5169 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][7] <= _T_5178 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5179 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5180 = eq(_T_5179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5181 = and(ic_valid_ff, _T_5180) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5182 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5183 = and(_T_5181, _T_5182) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5184 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5185 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5186 = and(_T_5184, _T_5185) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5187 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5188 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5189 = and(_T_5187, _T_5188) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5190 = or(_T_5186, _T_5189) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5191 = bits(_T_5190, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5192 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5191 : @[Reg.scala 28:19]
|
|
_T_5192 <= _T_5183 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][8] <= _T_5192 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5193 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5194 = eq(_T_5193, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5195 = and(ic_valid_ff, _T_5194) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5196 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5197 = and(_T_5195, _T_5196) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5198 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5199 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5200 = and(_T_5198, _T_5199) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5201 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5202 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5203 = and(_T_5201, _T_5202) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5204 = or(_T_5200, _T_5203) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5205 = bits(_T_5204, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5206 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5205 : @[Reg.scala 28:19]
|
|
_T_5206 <= _T_5197 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][9] <= _T_5206 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5207 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5208 = eq(_T_5207, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5209 = and(ic_valid_ff, _T_5208) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5210 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5211 = and(_T_5209, _T_5210) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5212 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5213 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5214 = and(_T_5212, _T_5213) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5215 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5217 = and(_T_5215, _T_5216) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5218 = or(_T_5214, _T_5217) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5219 = bits(_T_5218, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5220 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5219 : @[Reg.scala 28:19]
|
|
_T_5220 <= _T_5211 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][10] <= _T_5220 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5221 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5222 = eq(_T_5221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5223 = and(ic_valid_ff, _T_5222) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5224 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5225 = and(_T_5223, _T_5224) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5226 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5227 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5228 = and(_T_5226, _T_5227) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5229 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5230 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5231 = and(_T_5229, _T_5230) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5232 = or(_T_5228, _T_5231) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5233 = bits(_T_5232, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5234 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5233 : @[Reg.scala 28:19]
|
|
_T_5234 <= _T_5225 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][11] <= _T_5234 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5235 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5236 = eq(_T_5235, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5237 = and(ic_valid_ff, _T_5236) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5239 = and(_T_5237, _T_5238) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5240 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5241 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5242 = and(_T_5240, _T_5241) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5243 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5244 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5245 = and(_T_5243, _T_5244) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5246 = or(_T_5242, _T_5245) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5247 = bits(_T_5246, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5248 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5247 : @[Reg.scala 28:19]
|
|
_T_5248 <= _T_5239 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][12] <= _T_5248 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5249 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5250 = eq(_T_5249, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5251 = and(ic_valid_ff, _T_5250) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5252 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5253 = and(_T_5251, _T_5252) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5254 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5255 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5256 = and(_T_5254, _T_5255) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5257 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5258 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5259 = and(_T_5257, _T_5258) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5260 = or(_T_5256, _T_5259) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5261 = bits(_T_5260, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5262 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5261 : @[Reg.scala 28:19]
|
|
_T_5262 <= _T_5253 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][13] <= _T_5262 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5263 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5264 = eq(_T_5263, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5265 = and(ic_valid_ff, _T_5264) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5266 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5267 = and(_T_5265, _T_5266) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5268 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5269 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5270 = and(_T_5268, _T_5269) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5271 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5272 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5273 = and(_T_5271, _T_5272) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5274 = or(_T_5270, _T_5273) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5275 = bits(_T_5274, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5276 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5275 : @[Reg.scala 28:19]
|
|
_T_5276 <= _T_5267 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][14] <= _T_5276 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5278 = eq(_T_5277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5279 = and(ic_valid_ff, _T_5278) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5281 = and(_T_5279, _T_5280) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5282 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5283 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5284 = and(_T_5282, _T_5283) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5285 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5286 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5287 = and(_T_5285, _T_5286) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5288 = or(_T_5284, _T_5287) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5289 = bits(_T_5288, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5290 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5289 : @[Reg.scala 28:19]
|
|
_T_5290 <= _T_5281 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][15] <= _T_5290 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5291 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5292 = eq(_T_5291, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5293 = and(ic_valid_ff, _T_5292) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5294 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5295 = and(_T_5293, _T_5294) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5296 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5297 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5298 = and(_T_5296, _T_5297) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5299 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5300 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5301 = and(_T_5299, _T_5300) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5302 = or(_T_5298, _T_5301) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5303 = bits(_T_5302, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5304 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5303 : @[Reg.scala 28:19]
|
|
_T_5304 <= _T_5295 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][16] <= _T_5304 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5305 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5306 = eq(_T_5305, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5307 = and(ic_valid_ff, _T_5306) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5309 = and(_T_5307, _T_5308) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5310 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5311 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5312 = and(_T_5310, _T_5311) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5313 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5314 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5315 = and(_T_5313, _T_5314) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5316 = or(_T_5312, _T_5315) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5317 = bits(_T_5316, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5318 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5317 : @[Reg.scala 28:19]
|
|
_T_5318 <= _T_5309 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][17] <= _T_5318 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5319 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5320 = eq(_T_5319, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5321 = and(ic_valid_ff, _T_5320) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5322 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5323 = and(_T_5321, _T_5322) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5324 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5325 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5326 = and(_T_5324, _T_5325) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5327 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5328 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5329 = and(_T_5327, _T_5328) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5330 = or(_T_5326, _T_5329) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5331 = bits(_T_5330, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5332 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5331 : @[Reg.scala 28:19]
|
|
_T_5332 <= _T_5323 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][18] <= _T_5332 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5334 = eq(_T_5333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5335 = and(ic_valid_ff, _T_5334) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5337 = and(_T_5335, _T_5336) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5338 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5340 = and(_T_5338, _T_5339) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5341 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5343 = and(_T_5341, _T_5342) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5344 = or(_T_5340, _T_5343) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5345 = bits(_T_5344, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5346 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5345 : @[Reg.scala 28:19]
|
|
_T_5346 <= _T_5337 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][19] <= _T_5346 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5347 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5348 = eq(_T_5347, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5349 = and(ic_valid_ff, _T_5348) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5350 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5351 = and(_T_5349, _T_5350) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5352 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5353 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5354 = and(_T_5352, _T_5353) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5355 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5356 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5357 = and(_T_5355, _T_5356) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5358 = or(_T_5354, _T_5357) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5359 = bits(_T_5358, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5360 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5359 : @[Reg.scala 28:19]
|
|
_T_5360 <= _T_5351 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][20] <= _T_5360 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5361 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5362 = eq(_T_5361, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5363 = and(ic_valid_ff, _T_5362) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5364 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5365 = and(_T_5363, _T_5364) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5366 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5367 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5368 = and(_T_5366, _T_5367) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5369 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5370 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5371 = and(_T_5369, _T_5370) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5372 = or(_T_5368, _T_5371) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5373 = bits(_T_5372, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5374 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5373 : @[Reg.scala 28:19]
|
|
_T_5374 <= _T_5365 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][21] <= _T_5374 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5375 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5376 = eq(_T_5375, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5377 = and(ic_valid_ff, _T_5376) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5379 = and(_T_5377, _T_5378) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5380 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5381 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5382 = and(_T_5380, _T_5381) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5383 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5384 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5385 = and(_T_5383, _T_5384) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5386 = or(_T_5382, _T_5385) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5387 = bits(_T_5386, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5388 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5387 : @[Reg.scala 28:19]
|
|
_T_5388 <= _T_5379 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][22] <= _T_5388 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5390 = eq(_T_5389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5391 = and(ic_valid_ff, _T_5390) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5393 = and(_T_5391, _T_5392) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5394 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5396 = and(_T_5394, _T_5395) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5397 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5398 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5399 = and(_T_5397, _T_5398) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5400 = or(_T_5396, _T_5399) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5401 = bits(_T_5400, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5402 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5401 : @[Reg.scala 28:19]
|
|
_T_5402 <= _T_5393 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][23] <= _T_5402 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5403 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5404 = eq(_T_5403, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5405 = and(ic_valid_ff, _T_5404) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5406 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5407 = and(_T_5405, _T_5406) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5408 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5409 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5410 = and(_T_5408, _T_5409) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5411 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5412 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5413 = and(_T_5411, _T_5412) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5414 = or(_T_5410, _T_5413) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5415 = bits(_T_5414, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5416 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5415 : @[Reg.scala 28:19]
|
|
_T_5416 <= _T_5407 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][24] <= _T_5416 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5417 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5418 = eq(_T_5417, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5419 = and(ic_valid_ff, _T_5418) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5420 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5421 = and(_T_5419, _T_5420) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5422 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5423 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5424 = and(_T_5422, _T_5423) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5425 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5426 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5427 = and(_T_5425, _T_5426) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5428 = or(_T_5424, _T_5427) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5429 = bits(_T_5428, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5430 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5429 : @[Reg.scala 28:19]
|
|
_T_5430 <= _T_5421 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][25] <= _T_5430 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5431 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5432 = eq(_T_5431, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5433 = and(ic_valid_ff, _T_5432) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5434 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5435 = and(_T_5433, _T_5434) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5436 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5437 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5438 = and(_T_5436, _T_5437) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5439 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5440 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5441 = and(_T_5439, _T_5440) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5442 = or(_T_5438, _T_5441) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5443 = bits(_T_5442, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5444 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5443 : @[Reg.scala 28:19]
|
|
_T_5444 <= _T_5435 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][26] <= _T_5444 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5445 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5446 = eq(_T_5445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5447 = and(ic_valid_ff, _T_5446) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5449 = and(_T_5447, _T_5448) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5450 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5451 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5452 = and(_T_5450, _T_5451) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5453 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5454 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5455 = and(_T_5453, _T_5454) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5456 = or(_T_5452, _T_5455) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5457 = bits(_T_5456, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5458 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5457 : @[Reg.scala 28:19]
|
|
_T_5458 <= _T_5449 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][27] <= _T_5458 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5459 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5460 = eq(_T_5459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5461 = and(ic_valid_ff, _T_5460) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5462 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5463 = and(_T_5461, _T_5462) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5464 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5465 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5466 = and(_T_5464, _T_5465) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5467 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5468 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5469 = and(_T_5467, _T_5468) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5470 = or(_T_5466, _T_5469) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5471 = bits(_T_5470, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5472 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5471 : @[Reg.scala 28:19]
|
|
_T_5472 <= _T_5463 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][28] <= _T_5472 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5473 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5474 = eq(_T_5473, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5475 = and(ic_valid_ff, _T_5474) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5476 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5477 = and(_T_5475, _T_5476) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5478 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5479 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5480 = and(_T_5478, _T_5479) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5481 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5482 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5483 = and(_T_5481, _T_5482) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5484 = or(_T_5480, _T_5483) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5485 = bits(_T_5484, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5486 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5485 : @[Reg.scala 28:19]
|
|
_T_5486 <= _T_5477 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][29] <= _T_5486 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5487 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5488 = eq(_T_5487, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5489 = and(ic_valid_ff, _T_5488) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5490 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5491 = and(_T_5489, _T_5490) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5492 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5493 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5494 = and(_T_5492, _T_5493) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5495 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5496 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5497 = and(_T_5495, _T_5496) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5498 = or(_T_5494, _T_5497) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5499 = bits(_T_5498, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5500 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5499 : @[Reg.scala 28:19]
|
|
_T_5500 <= _T_5491 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][30] <= _T_5500 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5502 = eq(_T_5501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5503 = and(ic_valid_ff, _T_5502) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5505 = and(_T_5503, _T_5504) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5506 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5507 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5508 = and(_T_5506, _T_5507) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5509 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5511 = and(_T_5509, _T_5510) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5512 = or(_T_5508, _T_5511) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5513 = bits(_T_5512, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5514 : UInt<1>, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5513 : @[Reg.scala 28:19]
|
|
_T_5514 <= _T_5505 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][31] <= _T_5514 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5515 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5516 = eq(_T_5515, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5517 = and(ic_valid_ff, _T_5516) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5519 = and(_T_5517, _T_5518) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5520 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5521 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5522 = and(_T_5520, _T_5521) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5523 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5524 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5525 = and(_T_5523, _T_5524) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5526 = or(_T_5522, _T_5525) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5527 = bits(_T_5526, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5528 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5527 : @[Reg.scala 28:19]
|
|
_T_5528 <= _T_5519 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][0] <= _T_5528 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5529 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5530 = eq(_T_5529, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5531 = and(ic_valid_ff, _T_5530) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5532 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5533 = and(_T_5531, _T_5532) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5534 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5535 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5536 = and(_T_5534, _T_5535) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5537 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5538 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5539 = and(_T_5537, _T_5538) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5540 = or(_T_5536, _T_5539) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5541 = bits(_T_5540, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5542 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5541 : @[Reg.scala 28:19]
|
|
_T_5542 <= _T_5533 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][1] <= _T_5542 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5543 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5544 = eq(_T_5543, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5545 = and(ic_valid_ff, _T_5544) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5546 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5547 = and(_T_5545, _T_5546) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5548 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5549 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5550 = and(_T_5548, _T_5549) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5551 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5552 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5553 = and(_T_5551, _T_5552) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5554 = or(_T_5550, _T_5553) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5555 = bits(_T_5554, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5556 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5555 : @[Reg.scala 28:19]
|
|
_T_5556 <= _T_5547 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][2] <= _T_5556 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5558 = eq(_T_5557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5559 = and(ic_valid_ff, _T_5558) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5561 = and(_T_5559, _T_5560) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5562 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5563 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5564 = and(_T_5562, _T_5563) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5565 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5566 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5567 = and(_T_5565, _T_5566) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5568 = or(_T_5564, _T_5567) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5569 = bits(_T_5568, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5570 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5569 : @[Reg.scala 28:19]
|
|
_T_5570 <= _T_5561 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][3] <= _T_5570 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5571 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5572 = eq(_T_5571, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5573 = and(ic_valid_ff, _T_5572) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5574 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5575 = and(_T_5573, _T_5574) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5576 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5577 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5578 = and(_T_5576, _T_5577) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5579 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5580 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5581 = and(_T_5579, _T_5580) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5582 = or(_T_5578, _T_5581) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5583 = bits(_T_5582, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5584 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5583 : @[Reg.scala 28:19]
|
|
_T_5584 <= _T_5575 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][4] <= _T_5584 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5585 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5586 = eq(_T_5585, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5587 = and(ic_valid_ff, _T_5586) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5589 = and(_T_5587, _T_5588) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5590 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5591 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5592 = and(_T_5590, _T_5591) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5593 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5594 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5595 = and(_T_5593, _T_5594) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5596 = or(_T_5592, _T_5595) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5597 = bits(_T_5596, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5598 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5597 : @[Reg.scala 28:19]
|
|
_T_5598 <= _T_5589 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][5] <= _T_5598 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5599 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5600 = eq(_T_5599, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5601 = and(ic_valid_ff, _T_5600) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5602 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5603 = and(_T_5601, _T_5602) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5604 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5605 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5606 = and(_T_5604, _T_5605) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5607 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5608 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5609 = and(_T_5607, _T_5608) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5610 = or(_T_5606, _T_5609) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5611 = bits(_T_5610, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5612 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5611 : @[Reg.scala 28:19]
|
|
_T_5612 <= _T_5603 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][6] <= _T_5612 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5613 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5614 = eq(_T_5613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5615 = and(ic_valid_ff, _T_5614) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5616 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5617 = and(_T_5615, _T_5616) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5618 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5619 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5620 = and(_T_5618, _T_5619) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5621 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5622 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5623 = and(_T_5621, _T_5622) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5624 = or(_T_5620, _T_5623) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5625 = bits(_T_5624, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5626 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5625 : @[Reg.scala 28:19]
|
|
_T_5626 <= _T_5617 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][7] <= _T_5626 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5627 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5628 = eq(_T_5627, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5629 = and(ic_valid_ff, _T_5628) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5630 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5631 = and(_T_5629, _T_5630) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5632 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5633 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5634 = and(_T_5632, _T_5633) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5635 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5636 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5637 = and(_T_5635, _T_5636) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5638 = or(_T_5634, _T_5637) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5639 = bits(_T_5638, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5640 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5639 : @[Reg.scala 28:19]
|
|
_T_5640 <= _T_5631 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][8] <= _T_5640 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5641 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5642 = eq(_T_5641, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5643 = and(ic_valid_ff, _T_5642) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5644 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5645 = and(_T_5643, _T_5644) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5646 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5647 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5648 = and(_T_5646, _T_5647) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5649 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5650 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5651 = and(_T_5649, _T_5650) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5652 = or(_T_5648, _T_5651) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5653 = bits(_T_5652, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5654 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5653 : @[Reg.scala 28:19]
|
|
_T_5654 <= _T_5645 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][9] <= _T_5654 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5655 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5656 = eq(_T_5655, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5657 = and(ic_valid_ff, _T_5656) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5658 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5659 = and(_T_5657, _T_5658) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5660 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5661 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5662 = and(_T_5660, _T_5661) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5663 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5664 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5665 = and(_T_5663, _T_5664) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5666 = or(_T_5662, _T_5665) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5667 = bits(_T_5666, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5668 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5667 : @[Reg.scala 28:19]
|
|
_T_5668 <= _T_5659 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][10] <= _T_5668 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5670 = eq(_T_5669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5671 = and(ic_valid_ff, _T_5670) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5673 = and(_T_5671, _T_5672) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5674 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5675 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5676 = and(_T_5674, _T_5675) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5677 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5678 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5679 = and(_T_5677, _T_5678) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5680 = or(_T_5676, _T_5679) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5681 = bits(_T_5680, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5682 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5681 : @[Reg.scala 28:19]
|
|
_T_5682 <= _T_5673 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][11] <= _T_5682 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5683 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5684 = eq(_T_5683, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5685 = and(ic_valid_ff, _T_5684) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5686 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5687 = and(_T_5685, _T_5686) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5688 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5689 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5690 = and(_T_5688, _T_5689) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5691 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5692 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5693 = and(_T_5691, _T_5692) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5694 = or(_T_5690, _T_5693) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5695 = bits(_T_5694, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5696 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5695 : @[Reg.scala 28:19]
|
|
_T_5696 <= _T_5687 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][12] <= _T_5696 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5697 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5698 = eq(_T_5697, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5699 = and(ic_valid_ff, _T_5698) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5700 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5701 = and(_T_5699, _T_5700) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5702 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5703 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5704 = and(_T_5702, _T_5703) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5705 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5706 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5707 = and(_T_5705, _T_5706) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5708 = or(_T_5704, _T_5707) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5709 = bits(_T_5708, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5710 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5709 : @[Reg.scala 28:19]
|
|
_T_5710 <= _T_5701 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][13] <= _T_5710 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5711 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5712 = eq(_T_5711, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5713 = and(ic_valid_ff, _T_5712) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5714 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5715 = and(_T_5713, _T_5714) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5716 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5717 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5718 = and(_T_5716, _T_5717) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5719 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5720 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5721 = and(_T_5719, _T_5720) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5722 = or(_T_5718, _T_5721) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5723 = bits(_T_5722, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5724 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5723 : @[Reg.scala 28:19]
|
|
_T_5724 <= _T_5715 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][14] <= _T_5724 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5725 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5726 = eq(_T_5725, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5727 = and(ic_valid_ff, _T_5726) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5729 = and(_T_5727, _T_5728) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5730 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5731 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5732 = and(_T_5730, _T_5731) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5733 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5734 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5735 = and(_T_5733, _T_5734) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5736 = or(_T_5732, _T_5735) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5737 = bits(_T_5736, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5738 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5737 : @[Reg.scala 28:19]
|
|
_T_5738 <= _T_5729 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][15] <= _T_5738 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5739 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5740 = eq(_T_5739, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5741 = and(ic_valid_ff, _T_5740) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5742 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5743 = and(_T_5741, _T_5742) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5744 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5745 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5746 = and(_T_5744, _T_5745) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5747 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5748 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5749 = and(_T_5747, _T_5748) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5750 = or(_T_5746, _T_5749) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5751 = bits(_T_5750, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5752 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5751 : @[Reg.scala 28:19]
|
|
_T_5752 <= _T_5743 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][16] <= _T_5752 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5753 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5754 = eq(_T_5753, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5755 = and(ic_valid_ff, _T_5754) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5756 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5757 = and(_T_5755, _T_5756) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5758 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5759 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5760 = and(_T_5758, _T_5759) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5761 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5762 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5763 = and(_T_5761, _T_5762) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5764 = or(_T_5760, _T_5763) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5765 = bits(_T_5764, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5766 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5765 : @[Reg.scala 28:19]
|
|
_T_5766 <= _T_5757 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][17] <= _T_5766 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5767 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5768 = eq(_T_5767, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5769 = and(ic_valid_ff, _T_5768) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5770 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5771 = and(_T_5769, _T_5770) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5772 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5773 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5774 = and(_T_5772, _T_5773) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5775 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5776 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5777 = and(_T_5775, _T_5776) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5778 = or(_T_5774, _T_5777) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5779 = bits(_T_5778, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5780 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5779 : @[Reg.scala 28:19]
|
|
_T_5780 <= _T_5771 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][18] <= _T_5780 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5782 = eq(_T_5781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5783 = and(ic_valid_ff, _T_5782) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5785 = and(_T_5783, _T_5784) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5786 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5787 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5788 = and(_T_5786, _T_5787) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5789 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5791 = and(_T_5789, _T_5790) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5792 = or(_T_5788, _T_5791) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5793 = bits(_T_5792, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5794 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5793 : @[Reg.scala 28:19]
|
|
_T_5794 <= _T_5785 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][19] <= _T_5794 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5795 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5797 = and(ic_valid_ff, _T_5796) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5802 = and(_T_5800, _T_5801) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5803 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5804 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5805 = and(_T_5803, _T_5804) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5806 = or(_T_5802, _T_5805) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5807 = bits(_T_5806, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5808 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5807 : @[Reg.scala 28:19]
|
|
_T_5808 <= _T_5799 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][20] <= _T_5808 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5809 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5810 = eq(_T_5809, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5811 = and(ic_valid_ff, _T_5810) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5812 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5813 = and(_T_5811, _T_5812) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5814 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5815 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5816 = and(_T_5814, _T_5815) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5817 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5818 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5819 = and(_T_5817, _T_5818) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5820 = or(_T_5816, _T_5819) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5821 = bits(_T_5820, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5822 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5821 : @[Reg.scala 28:19]
|
|
_T_5822 <= _T_5813 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][21] <= _T_5822 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5823 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5824 = eq(_T_5823, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5825 = and(ic_valid_ff, _T_5824) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5826 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5827 = and(_T_5825, _T_5826) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5828 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5829 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5830 = and(_T_5828, _T_5829) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5831 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5832 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5833 = and(_T_5831, _T_5832) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5834 = or(_T_5830, _T_5833) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5835 = bits(_T_5834, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5836 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5835 : @[Reg.scala 28:19]
|
|
_T_5836 <= _T_5827 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][22] <= _T_5836 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5838 = eq(_T_5837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5839 = and(ic_valid_ff, _T_5838) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5841 = and(_T_5839, _T_5840) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5842 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5843 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5844 = and(_T_5842, _T_5843) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5845 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5847 = and(_T_5845, _T_5846) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5848 = or(_T_5844, _T_5847) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5849 = bits(_T_5848, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5850 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5849 : @[Reg.scala 28:19]
|
|
_T_5850 <= _T_5841 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][23] <= _T_5850 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5851 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5852 = eq(_T_5851, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5853 = and(ic_valid_ff, _T_5852) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5854 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5855 = and(_T_5853, _T_5854) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5856 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5857 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5858 = and(_T_5856, _T_5857) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5859 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5860 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5861 = and(_T_5859, _T_5860) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5862 = or(_T_5858, _T_5861) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5863 = bits(_T_5862, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5864 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5863 : @[Reg.scala 28:19]
|
|
_T_5864 <= _T_5855 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][24] <= _T_5864 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5865 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5866 = eq(_T_5865, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5867 = and(ic_valid_ff, _T_5866) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5868 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5869 = and(_T_5867, _T_5868) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5870 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5871 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5872 = and(_T_5870, _T_5871) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5873 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5874 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5875 = and(_T_5873, _T_5874) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5876 = or(_T_5872, _T_5875) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5877 = bits(_T_5876, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5878 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5877 : @[Reg.scala 28:19]
|
|
_T_5878 <= _T_5869 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][25] <= _T_5878 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5879 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5880 = eq(_T_5879, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5881 = and(ic_valid_ff, _T_5880) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5882 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5883 = and(_T_5881, _T_5882) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5884 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5885 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5886 = and(_T_5884, _T_5885) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5887 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5888 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5889 = and(_T_5887, _T_5888) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5890 = or(_T_5886, _T_5889) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5891 = bits(_T_5890, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5892 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5891 : @[Reg.scala 28:19]
|
|
_T_5892 <= _T_5883 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][26] <= _T_5892 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5893 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5894 = eq(_T_5893, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5895 = and(ic_valid_ff, _T_5894) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5896 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5897 = and(_T_5895, _T_5896) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5898 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5899 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5900 = and(_T_5898, _T_5899) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5901 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5902 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5903 = and(_T_5901, _T_5902) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5904 = or(_T_5900, _T_5903) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5905 = bits(_T_5904, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5906 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5905 : @[Reg.scala 28:19]
|
|
_T_5906 <= _T_5897 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][27] <= _T_5906 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5907 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5908 = eq(_T_5907, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5909 = and(ic_valid_ff, _T_5908) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5910 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5911 = and(_T_5909, _T_5910) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5912 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5913 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5914 = and(_T_5912, _T_5913) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5915 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5916 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5917 = and(_T_5915, _T_5916) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5918 = or(_T_5914, _T_5917) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5919 = bits(_T_5918, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5920 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5919 : @[Reg.scala 28:19]
|
|
_T_5920 <= _T_5911 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][28] <= _T_5920 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5921 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5922 = eq(_T_5921, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5923 = and(ic_valid_ff, _T_5922) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5924 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5925 = and(_T_5923, _T_5924) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5926 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5927 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5928 = and(_T_5926, _T_5927) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5929 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5930 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5931 = and(_T_5929, _T_5930) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5932 = or(_T_5928, _T_5931) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5933 = bits(_T_5932, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5934 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5933 : @[Reg.scala 28:19]
|
|
_T_5934 <= _T_5925 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][29] <= _T_5934 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5935 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5936 = eq(_T_5935, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5937 = and(ic_valid_ff, _T_5936) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5938 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5939 = and(_T_5937, _T_5938) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5940 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5941 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5942 = and(_T_5940, _T_5941) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5943 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5944 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5945 = and(_T_5943, _T_5944) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5946 = or(_T_5942, _T_5945) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5947 = bits(_T_5946, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5948 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5947 : @[Reg.scala 28:19]
|
|
_T_5948 <= _T_5939 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][30] <= _T_5948 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5950 = eq(_T_5949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5951 = and(ic_valid_ff, _T_5950) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5953 = and(_T_5951, _T_5952) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5954 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5956 = and(_T_5954, _T_5955) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5957 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5958 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5959 = and(_T_5957, _T_5958) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5960 = or(_T_5956, _T_5959) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5961 = bits(_T_5960, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5962 : UInt<1>, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5961 : @[Reg.scala 28:19]
|
|
_T_5962 <= _T_5953 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][31] <= _T_5962 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5963 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5964 = eq(_T_5963, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5965 = and(ic_valid_ff, _T_5964) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5966 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5967 = and(_T_5965, _T_5966) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5968 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5969 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5970 = and(_T_5968, _T_5969) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5971 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5972 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5973 = and(_T_5971, _T_5972) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5974 = or(_T_5970, _T_5973) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5975 = bits(_T_5974, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5976 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5975 : @[Reg.scala 28:19]
|
|
_T_5976 <= _T_5967 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][32] <= _T_5976 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5977 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5978 = eq(_T_5977, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5979 = and(ic_valid_ff, _T_5978) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5980 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5981 = and(_T_5979, _T_5980) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5982 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5983 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5984 = and(_T_5982, _T_5983) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5985 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_5986 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_5987 = and(_T_5985, _T_5986) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_5988 = or(_T_5984, _T_5987) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_5989 = bits(_T_5988, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_5990 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5989 : @[Reg.scala 28:19]
|
|
_T_5990 <= _T_5981 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][33] <= _T_5990 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_5991 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_5992 = eq(_T_5991, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_5993 = and(ic_valid_ff, _T_5992) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_5994 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_5995 = and(_T_5993, _T_5994) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_5996 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_5997 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_5998 = and(_T_5996, _T_5997) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_5999 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6000 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6001 = and(_T_5999, _T_6000) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6002 = or(_T_5998, _T_6001) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6003 = bits(_T_6002, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6004 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6003 : @[Reg.scala 28:19]
|
|
_T_6004 <= _T_5995 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][34] <= _T_6004 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6006 = eq(_T_6005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6007 = and(ic_valid_ff, _T_6006) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6009 = and(_T_6007, _T_6008) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6010 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6011 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6012 = and(_T_6010, _T_6011) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6013 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6014 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6015 = and(_T_6013, _T_6014) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6016 = or(_T_6012, _T_6015) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6017 = bits(_T_6016, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6018 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6017 : @[Reg.scala 28:19]
|
|
_T_6018 <= _T_6009 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][35] <= _T_6018 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6019 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6020 = eq(_T_6019, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6021 = and(ic_valid_ff, _T_6020) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6022 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6023 = and(_T_6021, _T_6022) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6024 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6025 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6026 = and(_T_6024, _T_6025) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6027 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6028 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6029 = and(_T_6027, _T_6028) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6030 = or(_T_6026, _T_6029) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6031 = bits(_T_6030, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6032 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6031 : @[Reg.scala 28:19]
|
|
_T_6032 <= _T_6023 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][36] <= _T_6032 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6033 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6034 = eq(_T_6033, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6035 = and(ic_valid_ff, _T_6034) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6036 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6037 = and(_T_6035, _T_6036) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6038 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6039 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6040 = and(_T_6038, _T_6039) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6041 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6042 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6043 = and(_T_6041, _T_6042) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6044 = or(_T_6040, _T_6043) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6045 = bits(_T_6044, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6046 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6045 : @[Reg.scala 28:19]
|
|
_T_6046 <= _T_6037 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][37] <= _T_6046 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6047 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6048 = eq(_T_6047, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6049 = and(ic_valid_ff, _T_6048) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6050 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6051 = and(_T_6049, _T_6050) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6052 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6053 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6054 = and(_T_6052, _T_6053) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6055 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6056 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6057 = and(_T_6055, _T_6056) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6058 = or(_T_6054, _T_6057) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6059 = bits(_T_6058, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6060 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6059 : @[Reg.scala 28:19]
|
|
_T_6060 <= _T_6051 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][38] <= _T_6060 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6062 = eq(_T_6061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6063 = and(ic_valid_ff, _T_6062) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6065 = and(_T_6063, _T_6064) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6067 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6068 = and(_T_6066, _T_6067) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6069 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6070 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6071 = and(_T_6069, _T_6070) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6072 = or(_T_6068, _T_6071) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6073 = bits(_T_6072, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6074 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6073 : @[Reg.scala 28:19]
|
|
_T_6074 <= _T_6065 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][39] <= _T_6074 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6075 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6076 = eq(_T_6075, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6077 = and(ic_valid_ff, _T_6076) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6079 = and(_T_6077, _T_6078) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6081 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6082 = and(_T_6080, _T_6081) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6083 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6084 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6085 = and(_T_6083, _T_6084) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6086 = or(_T_6082, _T_6085) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6087 = bits(_T_6086, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6088 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6087 : @[Reg.scala 28:19]
|
|
_T_6088 <= _T_6079 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][40] <= _T_6088 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6089 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6090 = eq(_T_6089, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6091 = and(ic_valid_ff, _T_6090) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6092 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6093 = and(_T_6091, _T_6092) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6095 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6096 = and(_T_6094, _T_6095) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6097 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6098 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6099 = and(_T_6097, _T_6098) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6100 = or(_T_6096, _T_6099) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6101 = bits(_T_6100, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6102 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6101 : @[Reg.scala 28:19]
|
|
_T_6102 <= _T_6093 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][41] <= _T_6102 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6103 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6104 = eq(_T_6103, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6105 = and(ic_valid_ff, _T_6104) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6106 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6107 = and(_T_6105, _T_6106) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6109 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6110 = and(_T_6108, _T_6109) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6111 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6112 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6113 = and(_T_6111, _T_6112) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6114 = or(_T_6110, _T_6113) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6115 = bits(_T_6114, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6116 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6115 : @[Reg.scala 28:19]
|
|
_T_6116 <= _T_6107 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][42] <= _T_6116 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6117 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6118 = eq(_T_6117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6119 = and(ic_valid_ff, _T_6118) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6120 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6121 = and(_T_6119, _T_6120) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6122 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6123 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6124 = and(_T_6122, _T_6123) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6125 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6126 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6127 = and(_T_6125, _T_6126) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6128 = or(_T_6124, _T_6127) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6129 = bits(_T_6128, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6130 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6129 : @[Reg.scala 28:19]
|
|
_T_6130 <= _T_6121 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][43] <= _T_6130 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6131 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6132 = eq(_T_6131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6133 = and(ic_valid_ff, _T_6132) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6134 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6135 = and(_T_6133, _T_6134) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6136 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6137 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6138 = and(_T_6136, _T_6137) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6139 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6140 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6141 = and(_T_6139, _T_6140) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6142 = or(_T_6138, _T_6141) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6143 = bits(_T_6142, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6144 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6143 : @[Reg.scala 28:19]
|
|
_T_6144 <= _T_6135 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][44] <= _T_6144 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6145 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6146 = eq(_T_6145, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6147 = and(ic_valid_ff, _T_6146) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6148 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6149 = and(_T_6147, _T_6148) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6150 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6151 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6152 = and(_T_6150, _T_6151) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6153 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6154 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6155 = and(_T_6153, _T_6154) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6156 = or(_T_6152, _T_6155) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6157 = bits(_T_6156, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6158 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6157 : @[Reg.scala 28:19]
|
|
_T_6158 <= _T_6149 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][45] <= _T_6158 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6159 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6160 = eq(_T_6159, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6161 = and(ic_valid_ff, _T_6160) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6162 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6163 = and(_T_6161, _T_6162) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6164 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6165 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6166 = and(_T_6164, _T_6165) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6167 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6168 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6169 = and(_T_6167, _T_6168) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6170 = or(_T_6166, _T_6169) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6171 = bits(_T_6170, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6172 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6171 : @[Reg.scala 28:19]
|
|
_T_6172 <= _T_6163 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][46] <= _T_6172 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6173 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6174 = eq(_T_6173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6175 = and(ic_valid_ff, _T_6174) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6176 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6177 = and(_T_6175, _T_6176) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6178 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6179 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6180 = and(_T_6178, _T_6179) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6181 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6182 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6184 = or(_T_6180, _T_6183) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6185 = bits(_T_6184, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6186 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6185 : @[Reg.scala 28:19]
|
|
_T_6186 <= _T_6177 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][47] <= _T_6186 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6187 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6188 = eq(_T_6187, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6189 = and(ic_valid_ff, _T_6188) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6190 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6191 = and(_T_6189, _T_6190) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6192 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6193 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6194 = and(_T_6192, _T_6193) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6195 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6196 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6197 = and(_T_6195, _T_6196) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6198 = or(_T_6194, _T_6197) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6199 = bits(_T_6198, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6200 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6199 : @[Reg.scala 28:19]
|
|
_T_6200 <= _T_6191 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][48] <= _T_6200 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6201 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6202 = eq(_T_6201, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6203 = and(ic_valid_ff, _T_6202) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6204 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6205 = and(_T_6203, _T_6204) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6206 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6207 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6208 = and(_T_6206, _T_6207) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6209 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6210 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6211 = and(_T_6209, _T_6210) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6212 = or(_T_6208, _T_6211) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6213 = bits(_T_6212, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6214 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6213 : @[Reg.scala 28:19]
|
|
_T_6214 <= _T_6205 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][49] <= _T_6214 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6215 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6216 = eq(_T_6215, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6217 = and(ic_valid_ff, _T_6216) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6218 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6219 = and(_T_6217, _T_6218) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6220 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6221 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6222 = and(_T_6220, _T_6221) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6223 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6224 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6225 = and(_T_6223, _T_6224) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6226 = or(_T_6222, _T_6225) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6227 = bits(_T_6226, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6228 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6227 : @[Reg.scala 28:19]
|
|
_T_6228 <= _T_6219 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][50] <= _T_6228 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6230 = eq(_T_6229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6231 = and(ic_valid_ff, _T_6230) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6233 = and(_T_6231, _T_6232) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6234 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6235 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6236 = and(_T_6234, _T_6235) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6237 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6238 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6239 = and(_T_6237, _T_6238) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6240 = or(_T_6236, _T_6239) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6241 = bits(_T_6240, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6242 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6241 : @[Reg.scala 28:19]
|
|
_T_6242 <= _T_6233 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][51] <= _T_6242 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6243 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6244 = eq(_T_6243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6245 = and(ic_valid_ff, _T_6244) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6246 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6247 = and(_T_6245, _T_6246) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6248 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6249 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6250 = and(_T_6248, _T_6249) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6251 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6252 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6253 = and(_T_6251, _T_6252) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6254 = or(_T_6250, _T_6253) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6255 = bits(_T_6254, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6256 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6255 : @[Reg.scala 28:19]
|
|
_T_6256 <= _T_6247 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][52] <= _T_6256 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6257 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6258 = eq(_T_6257, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6259 = and(ic_valid_ff, _T_6258) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6260 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6261 = and(_T_6259, _T_6260) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6262 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6263 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6264 = and(_T_6262, _T_6263) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6265 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6266 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6267 = and(_T_6265, _T_6266) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6268 = or(_T_6264, _T_6267) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6269 = bits(_T_6268, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6270 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6269 : @[Reg.scala 28:19]
|
|
_T_6270 <= _T_6261 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][53] <= _T_6270 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6271 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6272 = eq(_T_6271, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6273 = and(ic_valid_ff, _T_6272) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6274 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6275 = and(_T_6273, _T_6274) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6276 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6277 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6278 = and(_T_6276, _T_6277) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6279 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6280 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6281 = and(_T_6279, _T_6280) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6282 = or(_T_6278, _T_6281) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6283 = bits(_T_6282, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6284 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6283 : @[Reg.scala 28:19]
|
|
_T_6284 <= _T_6275 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][54] <= _T_6284 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6286 = eq(_T_6285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6287 = and(ic_valid_ff, _T_6286) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6289 = and(_T_6287, _T_6288) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6290 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6292 = and(_T_6290, _T_6291) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6293 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6294 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6295 = and(_T_6293, _T_6294) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6296 = or(_T_6292, _T_6295) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6297 = bits(_T_6296, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6298 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6297 : @[Reg.scala 28:19]
|
|
_T_6298 <= _T_6289 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][55] <= _T_6298 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6299 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6300 = eq(_T_6299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6301 = and(ic_valid_ff, _T_6300) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6302 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6303 = and(_T_6301, _T_6302) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6304 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6305 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6306 = and(_T_6304, _T_6305) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6307 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6308 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6309 = and(_T_6307, _T_6308) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6310 = or(_T_6306, _T_6309) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6311 = bits(_T_6310, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6312 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6311 : @[Reg.scala 28:19]
|
|
_T_6312 <= _T_6303 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][56] <= _T_6312 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6313 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6314 = eq(_T_6313, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6315 = and(ic_valid_ff, _T_6314) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6316 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6317 = and(_T_6315, _T_6316) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6318 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6319 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6320 = and(_T_6318, _T_6319) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6321 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6322 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6323 = and(_T_6321, _T_6322) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6324 = or(_T_6320, _T_6323) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6325 = bits(_T_6324, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6326 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6325 : @[Reg.scala 28:19]
|
|
_T_6326 <= _T_6317 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][57] <= _T_6326 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6327 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6328 = eq(_T_6327, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6329 = and(ic_valid_ff, _T_6328) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6330 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6331 = and(_T_6329, _T_6330) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6332 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6333 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6334 = and(_T_6332, _T_6333) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6335 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6336 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6337 = and(_T_6335, _T_6336) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6338 = or(_T_6334, _T_6337) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6339 = bits(_T_6338, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6340 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6339 : @[Reg.scala 28:19]
|
|
_T_6340 <= _T_6331 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][58] <= _T_6340 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6341 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6342 = eq(_T_6341, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6343 = and(ic_valid_ff, _T_6342) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6344 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6345 = and(_T_6343, _T_6344) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6346 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6347 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6348 = and(_T_6346, _T_6347) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6349 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6351 = and(_T_6349, _T_6350) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6352 = or(_T_6348, _T_6351) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6353 = bits(_T_6352, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6354 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6353 : @[Reg.scala 28:19]
|
|
_T_6354 <= _T_6345 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][59] <= _T_6354 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6355 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6356 = eq(_T_6355, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6357 = and(ic_valid_ff, _T_6356) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6359 = and(_T_6357, _T_6358) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6360 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6361 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6362 = and(_T_6360, _T_6361) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6363 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6364 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6365 = and(_T_6363, _T_6364) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6366 = or(_T_6362, _T_6365) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6367 = bits(_T_6366, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6368 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6367 : @[Reg.scala 28:19]
|
|
_T_6368 <= _T_6359 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][60] <= _T_6368 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6369 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6370 = eq(_T_6369, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6371 = and(ic_valid_ff, _T_6370) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6372 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6373 = and(_T_6371, _T_6372) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6374 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6375 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6376 = and(_T_6374, _T_6375) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6377 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6378 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6379 = and(_T_6377, _T_6378) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6380 = or(_T_6376, _T_6379) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6381 = bits(_T_6380, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6382 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6381 : @[Reg.scala 28:19]
|
|
_T_6382 <= _T_6373 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][61] <= _T_6382 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6383 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6384 = eq(_T_6383, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6385 = and(ic_valid_ff, _T_6384) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6386 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6387 = and(_T_6385, _T_6386) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6388 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6389 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6390 = and(_T_6388, _T_6389) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6391 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6392 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6393 = and(_T_6391, _T_6392) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6394 = or(_T_6390, _T_6393) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6395 = bits(_T_6394, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6396 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6395 : @[Reg.scala 28:19]
|
|
_T_6396 <= _T_6387 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][62] <= _T_6396 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6397 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6398 = eq(_T_6397, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6399 = and(ic_valid_ff, _T_6398) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6400 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6401 = and(_T_6399, _T_6400) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6402 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6403 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6404 = and(_T_6402, _T_6403) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6405 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6406 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6407 = and(_T_6405, _T_6406) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6408 = or(_T_6404, _T_6407) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6409 = bits(_T_6408, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6410 : UInt<1>, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6409 : @[Reg.scala 28:19]
|
|
_T_6410 <= _T_6401 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][63] <= _T_6410 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6411 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6412 = eq(_T_6411, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6413 = and(ic_valid_ff, _T_6412) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6414 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6415 = and(_T_6413, _T_6414) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6416 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6417 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6418 = and(_T_6416, _T_6417) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6419 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6420 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6421 = and(_T_6419, _T_6420) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6422 = or(_T_6418, _T_6421) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6423 = bits(_T_6422, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6424 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6423 : @[Reg.scala 28:19]
|
|
_T_6424 <= _T_6415 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][32] <= _T_6424 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6425 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6426 = eq(_T_6425, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6427 = and(ic_valid_ff, _T_6426) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6428 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6429 = and(_T_6427, _T_6428) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6431 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6432 = and(_T_6430, _T_6431) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6433 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6434 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6435 = and(_T_6433, _T_6434) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6436 = or(_T_6432, _T_6435) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6437 = bits(_T_6436, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6438 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6437 : @[Reg.scala 28:19]
|
|
_T_6438 <= _T_6429 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][33] <= _T_6438 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6439 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6440 = eq(_T_6439, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6441 = and(ic_valid_ff, _T_6440) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6442 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6443 = and(_T_6441, _T_6442) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6444 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6445 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6446 = and(_T_6444, _T_6445) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6447 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6448 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6449 = and(_T_6447, _T_6448) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6450 = or(_T_6446, _T_6449) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6451 = bits(_T_6450, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6452 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6451 : @[Reg.scala 28:19]
|
|
_T_6452 <= _T_6443 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][34] <= _T_6452 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6453 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6454 = eq(_T_6453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6455 = and(ic_valid_ff, _T_6454) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6456 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6457 = and(_T_6455, _T_6456) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6458 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6459 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6460 = and(_T_6458, _T_6459) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6461 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6462 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6463 = and(_T_6461, _T_6462) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6464 = or(_T_6460, _T_6463) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6465 = bits(_T_6464, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6466 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6465 : @[Reg.scala 28:19]
|
|
_T_6466 <= _T_6457 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][35] <= _T_6466 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6467 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6468 = eq(_T_6467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6469 = and(ic_valid_ff, _T_6468) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6470 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6471 = and(_T_6469, _T_6470) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6472 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6473 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6474 = and(_T_6472, _T_6473) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6475 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6476 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6477 = and(_T_6475, _T_6476) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6478 = or(_T_6474, _T_6477) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6479 = bits(_T_6478, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6480 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6479 : @[Reg.scala 28:19]
|
|
_T_6480 <= _T_6471 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][36] <= _T_6480 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6481 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6482 = eq(_T_6481, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6483 = and(ic_valid_ff, _T_6482) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6484 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6485 = and(_T_6483, _T_6484) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6486 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6487 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6488 = and(_T_6486, _T_6487) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6489 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6490 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6491 = and(_T_6489, _T_6490) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6492 = or(_T_6488, _T_6491) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6493 = bits(_T_6492, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6494 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6493 : @[Reg.scala 28:19]
|
|
_T_6494 <= _T_6485 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][37] <= _T_6494 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6495 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6496 = eq(_T_6495, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6497 = and(ic_valid_ff, _T_6496) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6499 = and(_T_6497, _T_6498) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6500 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6501 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6502 = and(_T_6500, _T_6501) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6503 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6504 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6505 = and(_T_6503, _T_6504) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6506 = or(_T_6502, _T_6505) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6507 = bits(_T_6506, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6508 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6507 : @[Reg.scala 28:19]
|
|
_T_6508 <= _T_6499 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][38] <= _T_6508 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6510 = eq(_T_6509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6511 = and(ic_valid_ff, _T_6510) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6513 = and(_T_6511, _T_6512) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6514 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6515 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6516 = and(_T_6514, _T_6515) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6517 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6518 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6520 = or(_T_6516, _T_6519) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6521 = bits(_T_6520, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6522 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6521 : @[Reg.scala 28:19]
|
|
_T_6522 <= _T_6513 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][39] <= _T_6522 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6523 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6524 = eq(_T_6523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6525 = and(ic_valid_ff, _T_6524) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6526 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6527 = and(_T_6525, _T_6526) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6528 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6529 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6530 = and(_T_6528, _T_6529) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6531 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6532 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6533 = and(_T_6531, _T_6532) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6534 = or(_T_6530, _T_6533) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6535 = bits(_T_6534, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6536 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6535 : @[Reg.scala 28:19]
|
|
_T_6536 <= _T_6527 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][40] <= _T_6536 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6537 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6538 = eq(_T_6537, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6539 = and(ic_valid_ff, _T_6538) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6540 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6541 = and(_T_6539, _T_6540) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6542 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6543 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6544 = and(_T_6542, _T_6543) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6545 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6546 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6547 = and(_T_6545, _T_6546) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6548 = or(_T_6544, _T_6547) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6549 = bits(_T_6548, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6550 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6549 : @[Reg.scala 28:19]
|
|
_T_6550 <= _T_6541 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][41] <= _T_6550 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6551 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6552 = eq(_T_6551, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6553 = and(ic_valid_ff, _T_6552) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6554 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6555 = and(_T_6553, _T_6554) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6556 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6557 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6558 = and(_T_6556, _T_6557) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6559 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6560 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6561 = and(_T_6559, _T_6560) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6562 = or(_T_6558, _T_6561) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6563 = bits(_T_6562, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6564 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6563 : @[Reg.scala 28:19]
|
|
_T_6564 <= _T_6555 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][42] <= _T_6564 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6566 = eq(_T_6565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6567 = and(ic_valid_ff, _T_6566) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6569 = and(_T_6567, _T_6568) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6570 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6571 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6572 = and(_T_6570, _T_6571) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6573 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6574 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6575 = and(_T_6573, _T_6574) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6576 = or(_T_6572, _T_6575) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6577 = bits(_T_6576, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6578 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6577 : @[Reg.scala 28:19]
|
|
_T_6578 <= _T_6569 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][43] <= _T_6578 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6579 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6580 = eq(_T_6579, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6581 = and(ic_valid_ff, _T_6580) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6582 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6583 = and(_T_6581, _T_6582) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6584 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6585 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6586 = and(_T_6584, _T_6585) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6587 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6588 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6589 = and(_T_6587, _T_6588) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6590 = or(_T_6586, _T_6589) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6591 = bits(_T_6590, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6592 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6591 : @[Reg.scala 28:19]
|
|
_T_6592 <= _T_6583 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][44] <= _T_6592 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6593 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6594 = eq(_T_6593, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6595 = and(ic_valid_ff, _T_6594) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6596 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6597 = and(_T_6595, _T_6596) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6598 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6599 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6600 = and(_T_6598, _T_6599) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6601 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6602 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6603 = and(_T_6601, _T_6602) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6604 = or(_T_6600, _T_6603) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6605 = bits(_T_6604, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6606 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6605 : @[Reg.scala 28:19]
|
|
_T_6606 <= _T_6597 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][45] <= _T_6606 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6607 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6608 = eq(_T_6607, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6609 = and(ic_valid_ff, _T_6608) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6610 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6611 = and(_T_6609, _T_6610) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6612 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6613 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6614 = and(_T_6612, _T_6613) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6615 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6616 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6617 = and(_T_6615, _T_6616) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6618 = or(_T_6614, _T_6617) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6619 = bits(_T_6618, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6620 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6619 : @[Reg.scala 28:19]
|
|
_T_6620 <= _T_6611 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][46] <= _T_6620 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6621 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6622 = eq(_T_6621, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6623 = and(ic_valid_ff, _T_6622) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6624 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6625 = and(_T_6623, _T_6624) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6626 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6627 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6628 = and(_T_6626, _T_6627) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6629 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6630 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6631 = and(_T_6629, _T_6630) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6632 = or(_T_6628, _T_6631) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6633 = bits(_T_6632, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6634 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6633 : @[Reg.scala 28:19]
|
|
_T_6634 <= _T_6625 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][47] <= _T_6634 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6635 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6636 = eq(_T_6635, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6637 = and(ic_valid_ff, _T_6636) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6639 = and(_T_6637, _T_6638) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6640 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6641 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6642 = and(_T_6640, _T_6641) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6643 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6644 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6645 = and(_T_6643, _T_6644) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6646 = or(_T_6642, _T_6645) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6647 = bits(_T_6646, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6648 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6647 : @[Reg.scala 28:19]
|
|
_T_6648 <= _T_6639 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][48] <= _T_6648 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6649 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6650 = eq(_T_6649, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6651 = and(ic_valid_ff, _T_6650) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6652 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6653 = and(_T_6651, _T_6652) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6654 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6655 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6656 = and(_T_6654, _T_6655) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6657 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6658 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6659 = and(_T_6657, _T_6658) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6660 = or(_T_6656, _T_6659) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6661 = bits(_T_6660, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6662 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6661 : @[Reg.scala 28:19]
|
|
_T_6662 <= _T_6653 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][49] <= _T_6662 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6663 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6664 = eq(_T_6663, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6665 = and(ic_valid_ff, _T_6664) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6666 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6667 = and(_T_6665, _T_6666) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6668 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6669 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6670 = and(_T_6668, _T_6669) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6671 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6672 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6673 = and(_T_6671, _T_6672) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6674 = or(_T_6670, _T_6673) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6676 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6675 : @[Reg.scala 28:19]
|
|
_T_6676 <= _T_6667 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][50] <= _T_6676 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6677 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6678 = eq(_T_6677, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6679 = and(ic_valid_ff, _T_6678) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6680 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6681 = and(_T_6679, _T_6680) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6682 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6683 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6684 = and(_T_6682, _T_6683) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6685 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6686 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6687 = and(_T_6685, _T_6686) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6688 = or(_T_6684, _T_6687) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6689 = bits(_T_6688, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6690 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6689 : @[Reg.scala 28:19]
|
|
_T_6690 <= _T_6681 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][51] <= _T_6690 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6691 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6692 = eq(_T_6691, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6693 = and(ic_valid_ff, _T_6692) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6694 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6695 = and(_T_6693, _T_6694) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6696 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6697 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6698 = and(_T_6696, _T_6697) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6699 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6700 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6701 = and(_T_6699, _T_6700) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6702 = or(_T_6698, _T_6701) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6703 = bits(_T_6702, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6704 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6703 : @[Reg.scala 28:19]
|
|
_T_6704 <= _T_6695 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][52] <= _T_6704 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6705 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6706 = eq(_T_6705, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6707 = and(ic_valid_ff, _T_6706) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6709 = and(_T_6707, _T_6708) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6711 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6712 = and(_T_6710, _T_6711) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6713 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6714 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6715 = and(_T_6713, _T_6714) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6716 = or(_T_6712, _T_6715) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6717 = bits(_T_6716, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6718 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6717 : @[Reg.scala 28:19]
|
|
_T_6718 <= _T_6709 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][53] <= _T_6718 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6719 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6720 = eq(_T_6719, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6721 = and(ic_valid_ff, _T_6720) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6722 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6723 = and(_T_6721, _T_6722) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6725 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6726 = and(_T_6724, _T_6725) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6727 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6728 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6729 = and(_T_6727, _T_6728) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6730 = or(_T_6726, _T_6729) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6731 = bits(_T_6730, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6732 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6731 : @[Reg.scala 28:19]
|
|
_T_6732 <= _T_6723 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][54] <= _T_6732 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6734 = eq(_T_6733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6735 = and(ic_valid_ff, _T_6734) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6737 = and(_T_6735, _T_6736) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6738 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6739 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6740 = and(_T_6738, _T_6739) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6741 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6742 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6743 = and(_T_6741, _T_6742) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6744 = or(_T_6740, _T_6743) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6745 = bits(_T_6744, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6746 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6745 : @[Reg.scala 28:19]
|
|
_T_6746 <= _T_6737 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][55] <= _T_6746 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6747 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6748 = eq(_T_6747, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6749 = and(ic_valid_ff, _T_6748) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6750 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6751 = and(_T_6749, _T_6750) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6752 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6753 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6754 = and(_T_6752, _T_6753) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6755 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6756 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6757 = and(_T_6755, _T_6756) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6758 = or(_T_6754, _T_6757) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6759 = bits(_T_6758, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6760 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6759 : @[Reg.scala 28:19]
|
|
_T_6760 <= _T_6751 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][56] <= _T_6760 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6761 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6762 = eq(_T_6761, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6763 = and(ic_valid_ff, _T_6762) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6764 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6765 = and(_T_6763, _T_6764) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6766 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6767 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6768 = and(_T_6766, _T_6767) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6769 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6770 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6771 = and(_T_6769, _T_6770) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6772 = or(_T_6768, _T_6771) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6773 = bits(_T_6772, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6774 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6773 : @[Reg.scala 28:19]
|
|
_T_6774 <= _T_6765 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][57] <= _T_6774 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6775 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6776 = eq(_T_6775, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6777 = and(ic_valid_ff, _T_6776) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6779 = and(_T_6777, _T_6778) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6780 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6781 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6782 = and(_T_6780, _T_6781) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6783 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6784 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6785 = and(_T_6783, _T_6784) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6786 = or(_T_6782, _T_6785) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6787 = bits(_T_6786, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6788 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6787 : @[Reg.scala 28:19]
|
|
_T_6788 <= _T_6779 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][58] <= _T_6788 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6790 = eq(_T_6789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6791 = and(ic_valid_ff, _T_6790) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6793 = and(_T_6791, _T_6792) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6794 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6796 = and(_T_6794, _T_6795) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6797 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6799 = and(_T_6797, _T_6798) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6800 = or(_T_6796, _T_6799) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6802 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6801 : @[Reg.scala 28:19]
|
|
_T_6802 <= _T_6793 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][59] <= _T_6802 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6803 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6804 = eq(_T_6803, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6805 = and(ic_valid_ff, _T_6804) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6806 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6807 = and(_T_6805, _T_6806) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6808 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6809 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6810 = and(_T_6808, _T_6809) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6811 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6812 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6813 = and(_T_6811, _T_6812) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6814 = or(_T_6810, _T_6813) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6815 = bits(_T_6814, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6816 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6815 : @[Reg.scala 28:19]
|
|
_T_6816 <= _T_6807 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][60] <= _T_6816 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6817 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6818 = eq(_T_6817, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6819 = and(ic_valid_ff, _T_6818) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6820 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6821 = and(_T_6819, _T_6820) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6822 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6823 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6824 = and(_T_6822, _T_6823) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6825 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6826 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6827 = and(_T_6825, _T_6826) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6828 = or(_T_6824, _T_6827) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6829 = bits(_T_6828, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6830 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6829 : @[Reg.scala 28:19]
|
|
_T_6830 <= _T_6821 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][61] <= _T_6830 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6831 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6832 = eq(_T_6831, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6833 = and(ic_valid_ff, _T_6832) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6834 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6835 = and(_T_6833, _T_6834) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6836 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6837 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6838 = and(_T_6836, _T_6837) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6839 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6840 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6841 = and(_T_6839, _T_6840) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6842 = or(_T_6838, _T_6841) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6843 = bits(_T_6842, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6844 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6843 : @[Reg.scala 28:19]
|
|
_T_6844 <= _T_6835 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][62] <= _T_6844 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6845 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6847 = and(ic_valid_ff, _T_6846) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6849 = and(_T_6847, _T_6848) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6852 = and(_T_6850, _T_6851) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6854 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6855 = and(_T_6853, _T_6854) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6856 = or(_T_6852, _T_6855) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6857 = bits(_T_6856, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6858 : UInt<1>, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6857 : @[Reg.scala 28:19]
|
|
_T_6858 <= _T_6849 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][63] <= _T_6858 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6859 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6860 = eq(_T_6859, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6861 = and(ic_valid_ff, _T_6860) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6862 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6863 = and(_T_6861, _T_6862) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6865 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6866 = and(_T_6864, _T_6865) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6867 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6868 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6869 = and(_T_6867, _T_6868) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6870 = or(_T_6866, _T_6869) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6871 = bits(_T_6870, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6872 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6871 : @[Reg.scala 28:19]
|
|
_T_6872 <= _T_6863 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][64] <= _T_6872 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6873 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6874 = eq(_T_6873, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6875 = and(ic_valid_ff, _T_6874) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6876 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6877 = and(_T_6875, _T_6876) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6878 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6879 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6880 = and(_T_6878, _T_6879) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6881 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6882 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6883 = and(_T_6881, _T_6882) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6884 = or(_T_6880, _T_6883) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6885 = bits(_T_6884, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6886 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6885 : @[Reg.scala 28:19]
|
|
_T_6886 <= _T_6877 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][65] <= _T_6886 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6887 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6888 = eq(_T_6887, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6889 = and(ic_valid_ff, _T_6888) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6890 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6891 = and(_T_6889, _T_6890) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6892 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6893 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6894 = and(_T_6892, _T_6893) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6895 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6896 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6897 = and(_T_6895, _T_6896) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6898 = or(_T_6894, _T_6897) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6899 = bits(_T_6898, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6900 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6899 : @[Reg.scala 28:19]
|
|
_T_6900 <= _T_6891 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][66] <= _T_6900 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6901 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6902 = eq(_T_6901, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6903 = and(ic_valid_ff, _T_6902) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6904 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6905 = and(_T_6903, _T_6904) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6907 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6908 = and(_T_6906, _T_6907) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6909 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6910 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6911 = and(_T_6909, _T_6910) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6912 = or(_T_6908, _T_6911) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6913 = bits(_T_6912, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6914 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6913 : @[Reg.scala 28:19]
|
|
_T_6914 <= _T_6905 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][67] <= _T_6914 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6915 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6916 = eq(_T_6915, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6917 = and(ic_valid_ff, _T_6916) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6919 = and(_T_6917, _T_6918) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6921 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6922 = and(_T_6920, _T_6921) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6923 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6924 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6925 = and(_T_6923, _T_6924) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6926 = or(_T_6922, _T_6925) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6928 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6927 : @[Reg.scala 28:19]
|
|
_T_6928 <= _T_6919 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][68] <= _T_6928 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6929 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6930 = eq(_T_6929, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6931 = and(ic_valid_ff, _T_6930) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6932 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6933 = and(_T_6931, _T_6932) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6934 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6935 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6936 = and(_T_6934, _T_6935) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6937 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6938 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6939 = and(_T_6937, _T_6938) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6940 = or(_T_6936, _T_6939) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6941 = bits(_T_6940, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6942 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6941 : @[Reg.scala 28:19]
|
|
_T_6942 <= _T_6933 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][69] <= _T_6942 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6943 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6944 = eq(_T_6943, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6945 = and(ic_valid_ff, _T_6944) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6946 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6947 = and(_T_6945, _T_6946) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6948 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6949 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6950 = and(_T_6948, _T_6949) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6951 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6952 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6953 = and(_T_6951, _T_6952) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6954 = or(_T_6950, _T_6953) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6955 = bits(_T_6954, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6956 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6955 : @[Reg.scala 28:19]
|
|
_T_6956 <= _T_6947 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][70] <= _T_6956 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6958 = eq(_T_6957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6959 = and(ic_valid_ff, _T_6958) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6961 = and(_T_6959, _T_6960) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6962 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6963 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6964 = and(_T_6962, _T_6963) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6965 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6966 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6967 = and(_T_6965, _T_6966) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6968 = or(_T_6964, _T_6967) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6969 = bits(_T_6968, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6970 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6969 : @[Reg.scala 28:19]
|
|
_T_6970 <= _T_6961 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][71] <= _T_6970 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6971 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6972 = eq(_T_6971, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6973 = and(ic_valid_ff, _T_6972) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6974 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6975 = and(_T_6973, _T_6974) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6976 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6977 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6978 = and(_T_6976, _T_6977) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6979 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6980 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6981 = and(_T_6979, _T_6980) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6982 = or(_T_6978, _T_6981) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6983 = bits(_T_6982, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6984 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6983 : @[Reg.scala 28:19]
|
|
_T_6984 <= _T_6975 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][72] <= _T_6984 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6985 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_6986 = eq(_T_6985, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_6987 = and(ic_valid_ff, _T_6986) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_6988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_6989 = and(_T_6987, _T_6988) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_6990 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_6991 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_6992 = and(_T_6990, _T_6991) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_6993 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_6994 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_6995 = and(_T_6993, _T_6994) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_6996 = or(_T_6992, _T_6995) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_6997 = bits(_T_6996, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_6998 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6997 : @[Reg.scala 28:19]
|
|
_T_6998 <= _T_6989 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][73] <= _T_6998 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_6999 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7000 = eq(_T_6999, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7001 = and(ic_valid_ff, _T_7000) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7002 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7003 = and(_T_7001, _T_7002) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7004 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7005 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7006 = and(_T_7004, _T_7005) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7007 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7008 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7009 = and(_T_7007, _T_7008) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7010 = or(_T_7006, _T_7009) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7011 = bits(_T_7010, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7012 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7011 : @[Reg.scala 28:19]
|
|
_T_7012 <= _T_7003 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][74] <= _T_7012 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7014 = eq(_T_7013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7015 = and(ic_valid_ff, _T_7014) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7017 = and(_T_7015, _T_7016) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7018 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7019 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7020 = and(_T_7018, _T_7019) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7021 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7022 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7023 = and(_T_7021, _T_7022) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7024 = or(_T_7020, _T_7023) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7025 = bits(_T_7024, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7026 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7025 : @[Reg.scala 28:19]
|
|
_T_7026 <= _T_7017 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][75] <= _T_7026 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7027 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7028 = eq(_T_7027, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7029 = and(ic_valid_ff, _T_7028) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7030 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7031 = and(_T_7029, _T_7030) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7032 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7033 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7034 = and(_T_7032, _T_7033) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7035 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7036 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7037 = and(_T_7035, _T_7036) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7038 = or(_T_7034, _T_7037) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7039 = bits(_T_7038, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7040 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7039 : @[Reg.scala 28:19]
|
|
_T_7040 <= _T_7031 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][76] <= _T_7040 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7041 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7042 = eq(_T_7041, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7043 = and(ic_valid_ff, _T_7042) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7044 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7045 = and(_T_7043, _T_7044) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7046 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7047 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7048 = and(_T_7046, _T_7047) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7049 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7050 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7051 = and(_T_7049, _T_7050) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7052 = or(_T_7048, _T_7051) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7054 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7053 : @[Reg.scala 28:19]
|
|
_T_7054 <= _T_7045 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][77] <= _T_7054 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7055 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7056 = eq(_T_7055, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7057 = and(ic_valid_ff, _T_7056) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7059 = and(_T_7057, _T_7058) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7060 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7061 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7062 = and(_T_7060, _T_7061) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7063 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7064 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7065 = and(_T_7063, _T_7064) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7066 = or(_T_7062, _T_7065) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7067 = bits(_T_7066, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7068 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7067 : @[Reg.scala 28:19]
|
|
_T_7068 <= _T_7059 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][78] <= _T_7068 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7070 = eq(_T_7069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7071 = and(ic_valid_ff, _T_7070) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7073 = and(_T_7071, _T_7072) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7074 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7075 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7076 = and(_T_7074, _T_7075) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7077 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7078 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7079 = and(_T_7077, _T_7078) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7080 = or(_T_7076, _T_7079) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7081 = bits(_T_7080, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7082 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7081 : @[Reg.scala 28:19]
|
|
_T_7082 <= _T_7073 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][79] <= _T_7082 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7083 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7084 = eq(_T_7083, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7085 = and(ic_valid_ff, _T_7084) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7086 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7087 = and(_T_7085, _T_7086) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7088 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7089 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7090 = and(_T_7088, _T_7089) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7091 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7092 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7093 = and(_T_7091, _T_7092) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7094 = or(_T_7090, _T_7093) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7095 = bits(_T_7094, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7096 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7095 : @[Reg.scala 28:19]
|
|
_T_7096 <= _T_7087 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][80] <= _T_7096 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7097 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7098 = eq(_T_7097, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7099 = and(ic_valid_ff, _T_7098) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7100 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7101 = and(_T_7099, _T_7100) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7102 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7103 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7104 = and(_T_7102, _T_7103) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7105 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7106 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7107 = and(_T_7105, _T_7106) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7108 = or(_T_7104, _T_7107) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7109 = bits(_T_7108, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7110 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7109 : @[Reg.scala 28:19]
|
|
_T_7110 <= _T_7101 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][81] <= _T_7110 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7111 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7112 = eq(_T_7111, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7113 = and(ic_valid_ff, _T_7112) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7114 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7115 = and(_T_7113, _T_7114) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7116 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7117 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7118 = and(_T_7116, _T_7117) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7119 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7120 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7121 = and(_T_7119, _T_7120) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7122 = or(_T_7118, _T_7121) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7123 = bits(_T_7122, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7124 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7123 : @[Reg.scala 28:19]
|
|
_T_7124 <= _T_7115 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][82] <= _T_7124 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7125 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7126 = eq(_T_7125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7127 = and(ic_valid_ff, _T_7126) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7129 = and(_T_7127, _T_7128) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7131 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7132 = and(_T_7130, _T_7131) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7133 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7134 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7135 = and(_T_7133, _T_7134) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7136 = or(_T_7132, _T_7135) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7137 = bits(_T_7136, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7138 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7137 : @[Reg.scala 28:19]
|
|
_T_7138 <= _T_7129 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][83] <= _T_7138 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7139 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7140 = eq(_T_7139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7141 = and(ic_valid_ff, _T_7140) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7142 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7143 = and(_T_7141, _T_7142) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7145 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7146 = and(_T_7144, _T_7145) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7147 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7148 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7149 = and(_T_7147, _T_7148) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7150 = or(_T_7146, _T_7149) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7151 = bits(_T_7150, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7152 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7151 : @[Reg.scala 28:19]
|
|
_T_7152 <= _T_7143 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][84] <= _T_7152 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7153 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7154 = eq(_T_7153, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7155 = and(ic_valid_ff, _T_7154) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7156 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7157 = and(_T_7155, _T_7156) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7159 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7160 = and(_T_7158, _T_7159) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7161 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7162 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7163 = and(_T_7161, _T_7162) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7164 = or(_T_7160, _T_7163) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7165 = bits(_T_7164, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7166 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7165 : @[Reg.scala 28:19]
|
|
_T_7166 <= _T_7157 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][85] <= _T_7166 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7167 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7168 = eq(_T_7167, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7169 = and(ic_valid_ff, _T_7168) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7170 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7171 = and(_T_7169, _T_7170) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7173 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7174 = and(_T_7172, _T_7173) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7175 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7176 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7177 = and(_T_7175, _T_7176) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7178 = or(_T_7174, _T_7177) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7180 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7179 : @[Reg.scala 28:19]
|
|
_T_7180 <= _T_7171 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][86] <= _T_7180 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7181 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7182 = eq(_T_7181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7183 = and(ic_valid_ff, _T_7182) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7184 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7185 = and(_T_7183, _T_7184) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7187 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7188 = and(_T_7186, _T_7187) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7189 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7190 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7192 = or(_T_7188, _T_7191) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7193 = bits(_T_7192, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7194 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7193 : @[Reg.scala 28:19]
|
|
_T_7194 <= _T_7185 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][87] <= _T_7194 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7195 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7196 = eq(_T_7195, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7197 = and(ic_valid_ff, _T_7196) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7199 = and(_T_7197, _T_7198) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7201 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7202 = and(_T_7200, _T_7201) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7203 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7204 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7205 = and(_T_7203, _T_7204) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7206 = or(_T_7202, _T_7205) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7207 = bits(_T_7206, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7208 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7207 : @[Reg.scala 28:19]
|
|
_T_7208 <= _T_7199 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][88] <= _T_7208 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7209 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7210 = eq(_T_7209, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7211 = and(ic_valid_ff, _T_7210) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7212 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7213 = and(_T_7211, _T_7212) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7215 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7216 = and(_T_7214, _T_7215) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7217 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7218 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7219 = and(_T_7217, _T_7218) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7220 = or(_T_7216, _T_7219) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7221 = bits(_T_7220, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7222 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7221 : @[Reg.scala 28:19]
|
|
_T_7222 <= _T_7213 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][89] <= _T_7222 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7223 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7224 = eq(_T_7223, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7225 = and(ic_valid_ff, _T_7224) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7226 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7227 = and(_T_7225, _T_7226) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7229 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7230 = and(_T_7228, _T_7229) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7231 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7232 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7233 = and(_T_7231, _T_7232) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7234 = or(_T_7230, _T_7233) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7235 = bits(_T_7234, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7236 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7235 : @[Reg.scala 28:19]
|
|
_T_7236 <= _T_7227 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][90] <= _T_7236 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7238 = eq(_T_7237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7239 = and(ic_valid_ff, _T_7238) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7241 = and(_T_7239, _T_7240) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7243 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7244 = and(_T_7242, _T_7243) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7245 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7246 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7247 = and(_T_7245, _T_7246) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7248 = or(_T_7244, _T_7247) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7249 = bits(_T_7248, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7250 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7249 : @[Reg.scala 28:19]
|
|
_T_7250 <= _T_7241 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][91] <= _T_7250 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7252 = eq(_T_7251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7253 = and(ic_valid_ff, _T_7252) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7255 = and(_T_7253, _T_7254) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7256 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7257 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7258 = and(_T_7256, _T_7257) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7259 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7260 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7261 = and(_T_7259, _T_7260) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7262 = or(_T_7258, _T_7261) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7263 = bits(_T_7262, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7264 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7263 : @[Reg.scala 28:19]
|
|
_T_7264 <= _T_7255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][92] <= _T_7264 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7265 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7266 = eq(_T_7265, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7267 = and(ic_valid_ff, _T_7266) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7269 = and(_T_7267, _T_7268) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7271 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7272 = and(_T_7270, _T_7271) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7273 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7274 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7275 = and(_T_7273, _T_7274) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7276 = or(_T_7272, _T_7275) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7277 = bits(_T_7276, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7278 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7277 : @[Reg.scala 28:19]
|
|
_T_7278 <= _T_7269 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][93] <= _T_7278 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7279 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7280 = eq(_T_7279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7281 = and(ic_valid_ff, _T_7280) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7282 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7283 = and(_T_7281, _T_7282) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7284 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7285 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7286 = and(_T_7284, _T_7285) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7287 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7288 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7289 = and(_T_7287, _T_7288) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7290 = or(_T_7286, _T_7289) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7291 = bits(_T_7290, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7292 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7291 : @[Reg.scala 28:19]
|
|
_T_7292 <= _T_7283 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][94] <= _T_7292 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7294 = eq(_T_7293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7295 = and(ic_valid_ff, _T_7294) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7297 = and(_T_7295, _T_7296) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7298 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7299 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7300 = and(_T_7298, _T_7299) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7301 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7302 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7303 = and(_T_7301, _T_7302) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7304 = or(_T_7300, _T_7303) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7306 : UInt<1>, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7305 : @[Reg.scala 28:19]
|
|
_T_7306 <= _T_7297 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][95] <= _T_7306 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7307 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7308 = eq(_T_7307, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7309 = and(ic_valid_ff, _T_7308) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7310 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7311 = and(_T_7309, _T_7310) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7312 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7313 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7314 = and(_T_7312, _T_7313) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7315 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7316 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7317 = and(_T_7315, _T_7316) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7318 = or(_T_7314, _T_7317) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7319 = bits(_T_7318, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7320 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7319 : @[Reg.scala 28:19]
|
|
_T_7320 <= _T_7311 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][64] <= _T_7320 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7321 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7322 = eq(_T_7321, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7323 = and(ic_valid_ff, _T_7322) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7324 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7325 = and(_T_7323, _T_7324) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7326 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7327 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7328 = and(_T_7326, _T_7327) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7329 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7330 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7331 = and(_T_7329, _T_7330) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7332 = or(_T_7328, _T_7331) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7333 = bits(_T_7332, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7334 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7333 : @[Reg.scala 28:19]
|
|
_T_7334 <= _T_7325 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][65] <= _T_7334 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7335 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7336 = eq(_T_7335, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7337 = and(ic_valid_ff, _T_7336) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7338 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7339 = and(_T_7337, _T_7338) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7340 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7341 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7342 = and(_T_7340, _T_7341) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7343 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7344 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7345 = and(_T_7343, _T_7344) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7346 = or(_T_7342, _T_7345) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7347 = bits(_T_7346, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7348 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7347 : @[Reg.scala 28:19]
|
|
_T_7348 <= _T_7339 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][66] <= _T_7348 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7350 = eq(_T_7349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7351 = and(ic_valid_ff, _T_7350) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7353 = and(_T_7351, _T_7352) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7354 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7355 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7356 = and(_T_7354, _T_7355) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7357 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7358 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7359 = and(_T_7357, _T_7358) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7360 = or(_T_7356, _T_7359) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7361 = bits(_T_7360, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7362 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7361 : @[Reg.scala 28:19]
|
|
_T_7362 <= _T_7353 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][67] <= _T_7362 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7363 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7364 = eq(_T_7363, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7365 = and(ic_valid_ff, _T_7364) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7366 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7367 = and(_T_7365, _T_7366) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7368 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7369 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7370 = and(_T_7368, _T_7369) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7371 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7372 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7373 = and(_T_7371, _T_7372) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7374 = or(_T_7370, _T_7373) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7375 = bits(_T_7374, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7376 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7375 : @[Reg.scala 28:19]
|
|
_T_7376 <= _T_7367 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][68] <= _T_7376 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7377 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7378 = eq(_T_7377, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7379 = and(ic_valid_ff, _T_7378) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7380 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7381 = and(_T_7379, _T_7380) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7382 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7383 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7384 = and(_T_7382, _T_7383) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7385 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7386 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7387 = and(_T_7385, _T_7386) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7388 = or(_T_7384, _T_7387) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7389 = bits(_T_7388, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7390 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7389 : @[Reg.scala 28:19]
|
|
_T_7390 <= _T_7381 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][69] <= _T_7390 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7391 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7392 = eq(_T_7391, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7393 = and(ic_valid_ff, _T_7392) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7394 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7395 = and(_T_7393, _T_7394) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7396 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7397 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7398 = and(_T_7396, _T_7397) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7399 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7400 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7401 = and(_T_7399, _T_7400) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7402 = or(_T_7398, _T_7401) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7403 = bits(_T_7402, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7404 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7403 : @[Reg.scala 28:19]
|
|
_T_7404 <= _T_7395 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][70] <= _T_7404 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7405 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7406 = eq(_T_7405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7407 = and(ic_valid_ff, _T_7406) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7409 = and(_T_7407, _T_7408) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7411 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7412 = and(_T_7410, _T_7411) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7413 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7414 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7415 = and(_T_7413, _T_7414) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7416 = or(_T_7412, _T_7415) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7417 = bits(_T_7416, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7418 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7417 : @[Reg.scala 28:19]
|
|
_T_7418 <= _T_7409 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][71] <= _T_7418 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7419 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7420 = eq(_T_7419, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7421 = and(ic_valid_ff, _T_7420) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7422 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7423 = and(_T_7421, _T_7422) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7424 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7425 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7426 = and(_T_7424, _T_7425) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7427 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7428 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7429 = and(_T_7427, _T_7428) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7430 = or(_T_7426, _T_7429) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7432 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7431 : @[Reg.scala 28:19]
|
|
_T_7432 <= _T_7423 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][72] <= _T_7432 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7433 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7434 = eq(_T_7433, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7435 = and(ic_valid_ff, _T_7434) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7436 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7437 = and(_T_7435, _T_7436) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7438 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7439 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7440 = and(_T_7438, _T_7439) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7441 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7442 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7443 = and(_T_7441, _T_7442) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7444 = or(_T_7440, _T_7443) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7445 = bits(_T_7444, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7446 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7445 : @[Reg.scala 28:19]
|
|
_T_7446 <= _T_7437 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][73] <= _T_7446 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7447 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7448 = eq(_T_7447, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7449 = and(ic_valid_ff, _T_7448) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7450 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7451 = and(_T_7449, _T_7450) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7452 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7453 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7454 = and(_T_7452, _T_7453) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7455 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7456 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7457 = and(_T_7455, _T_7456) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7458 = or(_T_7454, _T_7457) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7459 = bits(_T_7458, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7460 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7459 : @[Reg.scala 28:19]
|
|
_T_7460 <= _T_7451 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][74] <= _T_7460 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7462 = eq(_T_7461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7463 = and(ic_valid_ff, _T_7462) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7465 = and(_T_7463, _T_7464) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7466 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7467 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7468 = and(_T_7466, _T_7467) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7469 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7470 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7471 = and(_T_7469, _T_7470) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7472 = or(_T_7468, _T_7471) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7473 = bits(_T_7472, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7474 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7473 : @[Reg.scala 28:19]
|
|
_T_7474 <= _T_7465 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][75] <= _T_7474 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7475 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7477 = and(ic_valid_ff, _T_7476) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7479 = and(_T_7477, _T_7478) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7481 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7482 = and(_T_7480, _T_7481) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7484 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7485 = and(_T_7483, _T_7484) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7486 = or(_T_7482, _T_7485) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7487 = bits(_T_7486, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7488 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7487 : @[Reg.scala 28:19]
|
|
_T_7488 <= _T_7479 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][76] <= _T_7488 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7489 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7490 = eq(_T_7489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7491 = and(ic_valid_ff, _T_7490) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7492 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7493 = and(_T_7491, _T_7492) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7494 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7495 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7496 = and(_T_7494, _T_7495) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7497 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7498 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7499 = and(_T_7497, _T_7498) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7500 = or(_T_7496, _T_7499) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7501 = bits(_T_7500, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7502 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7501 : @[Reg.scala 28:19]
|
|
_T_7502 <= _T_7493 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][77] <= _T_7502 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7503 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7504 = eq(_T_7503, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7505 = and(ic_valid_ff, _T_7504) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7506 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7507 = and(_T_7505, _T_7506) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7508 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7509 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7510 = and(_T_7508, _T_7509) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7511 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7512 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7513 = and(_T_7511, _T_7512) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7514 = or(_T_7510, _T_7513) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7515 = bits(_T_7514, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7516 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7515 : @[Reg.scala 28:19]
|
|
_T_7516 <= _T_7507 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][78] <= _T_7516 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7518 = eq(_T_7517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7519 = and(ic_valid_ff, _T_7518) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7521 = and(_T_7519, _T_7520) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7522 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7523 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7524 = and(_T_7522, _T_7523) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7525 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7526 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7527 = and(_T_7525, _T_7526) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7528 = or(_T_7524, _T_7527) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7529 = bits(_T_7528, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7530 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7529 : @[Reg.scala 28:19]
|
|
_T_7530 <= _T_7521 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][79] <= _T_7530 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7531 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7532 = eq(_T_7531, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7533 = and(ic_valid_ff, _T_7532) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7534 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7535 = and(_T_7533, _T_7534) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7536 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7537 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7538 = and(_T_7536, _T_7537) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7539 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7540 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7541 = and(_T_7539, _T_7540) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7542 = or(_T_7538, _T_7541) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7543 = bits(_T_7542, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7544 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7543 : @[Reg.scala 28:19]
|
|
_T_7544 <= _T_7535 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][80] <= _T_7544 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7545 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7546 = eq(_T_7545, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7547 = and(ic_valid_ff, _T_7546) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7548 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7549 = and(_T_7547, _T_7548) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7550 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7551 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7552 = and(_T_7550, _T_7551) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7553 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7554 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7555 = and(_T_7553, _T_7554) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7556 = or(_T_7552, _T_7555) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7558 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7557 : @[Reg.scala 28:19]
|
|
_T_7558 <= _T_7549 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][81] <= _T_7558 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7559 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7560 = eq(_T_7559, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7561 = and(ic_valid_ff, _T_7560) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7562 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7563 = and(_T_7561, _T_7562) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7564 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7565 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7566 = and(_T_7564, _T_7565) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7567 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7568 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7569 = and(_T_7567, _T_7568) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7570 = or(_T_7566, _T_7569) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7571 = bits(_T_7570, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7572 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7571 : @[Reg.scala 28:19]
|
|
_T_7572 <= _T_7563 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][82] <= _T_7572 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7573 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7574 = eq(_T_7573, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7575 = and(ic_valid_ff, _T_7574) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7576 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7577 = and(_T_7575, _T_7576) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7578 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7579 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7580 = and(_T_7578, _T_7579) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7581 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7582 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7583 = and(_T_7581, _T_7582) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7584 = or(_T_7580, _T_7583) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7585 = bits(_T_7584, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7586 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7585 : @[Reg.scala 28:19]
|
|
_T_7586 <= _T_7577 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][83] <= _T_7586 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7587 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7588 = eq(_T_7587, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7589 = and(ic_valid_ff, _T_7588) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7590 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7591 = and(_T_7589, _T_7590) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7592 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7593 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7594 = and(_T_7592, _T_7593) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7595 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7596 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7597 = and(_T_7595, _T_7596) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7598 = or(_T_7594, _T_7597) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7599 = bits(_T_7598, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7600 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7599 : @[Reg.scala 28:19]
|
|
_T_7600 <= _T_7591 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][84] <= _T_7600 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7601 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7602 = eq(_T_7601, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7603 = and(ic_valid_ff, _T_7602) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7604 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7605 = and(_T_7603, _T_7604) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7606 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7607 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7608 = and(_T_7606, _T_7607) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7609 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7610 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7611 = and(_T_7609, _T_7610) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7612 = or(_T_7608, _T_7611) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7613 = bits(_T_7612, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7614 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7613 : @[Reg.scala 28:19]
|
|
_T_7614 <= _T_7605 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][85] <= _T_7614 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7615 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7616 = eq(_T_7615, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7617 = and(ic_valid_ff, _T_7616) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7619 = and(_T_7617, _T_7618) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7621 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7622 = and(_T_7620, _T_7621) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7623 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7624 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7625 = and(_T_7623, _T_7624) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7626 = or(_T_7622, _T_7625) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7627 = bits(_T_7626, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7628 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7627 : @[Reg.scala 28:19]
|
|
_T_7628 <= _T_7619 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][86] <= _T_7628 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7630 = eq(_T_7629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7631 = and(ic_valid_ff, _T_7630) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7633 = and(_T_7631, _T_7632) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7634 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7635 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7636 = and(_T_7634, _T_7635) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7637 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7638 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7639 = and(_T_7637, _T_7638) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7640 = or(_T_7636, _T_7639) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7641 = bits(_T_7640, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7642 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7641 : @[Reg.scala 28:19]
|
|
_T_7642 <= _T_7633 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][87] <= _T_7642 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7643 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7644 = eq(_T_7643, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7645 = and(ic_valid_ff, _T_7644) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7646 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7647 = and(_T_7645, _T_7646) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7648 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7649 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7650 = and(_T_7648, _T_7649) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7651 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7652 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7653 = and(_T_7651, _T_7652) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7654 = or(_T_7650, _T_7653) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7655 = bits(_T_7654, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7656 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7655 : @[Reg.scala 28:19]
|
|
_T_7656 <= _T_7647 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][88] <= _T_7656 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7657 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7658 = eq(_T_7657, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7659 = and(ic_valid_ff, _T_7658) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7660 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7661 = and(_T_7659, _T_7660) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7662 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7663 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7664 = and(_T_7662, _T_7663) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7665 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7666 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7667 = and(_T_7665, _T_7666) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7668 = or(_T_7664, _T_7667) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7669 = bits(_T_7668, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7670 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7669 : @[Reg.scala 28:19]
|
|
_T_7670 <= _T_7661 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][89] <= _T_7670 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7671 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7672 = eq(_T_7671, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7673 = and(ic_valid_ff, _T_7672) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7674 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7675 = and(_T_7673, _T_7674) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7676 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7677 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7678 = and(_T_7676, _T_7677) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7679 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7680 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7681 = and(_T_7679, _T_7680) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7682 = or(_T_7678, _T_7681) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7684 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7683 : @[Reg.scala 28:19]
|
|
_T_7684 <= _T_7675 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][90] <= _T_7684 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7686 = eq(_T_7685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7687 = and(ic_valid_ff, _T_7686) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7689 = and(_T_7687, _T_7688) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7691 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7692 = and(_T_7690, _T_7691) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7693 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7694 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7695 = and(_T_7693, _T_7694) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7696 = or(_T_7692, _T_7695) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7697 = bits(_T_7696, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7698 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7697 : @[Reg.scala 28:19]
|
|
_T_7698 <= _T_7689 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][91] <= _T_7698 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7700 = eq(_T_7699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7701 = and(ic_valid_ff, _T_7700) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7703 = and(_T_7701, _T_7702) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7705 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7706 = and(_T_7704, _T_7705) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7707 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7708 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7709 = and(_T_7707, _T_7708) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7710 = or(_T_7706, _T_7709) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7711 = bits(_T_7710, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7712 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7711 : @[Reg.scala 28:19]
|
|
_T_7712 <= _T_7703 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][92] <= _T_7712 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7713 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7714 = eq(_T_7713, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7715 = and(ic_valid_ff, _T_7714) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7716 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7717 = and(_T_7715, _T_7716) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7718 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7719 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7720 = and(_T_7718, _T_7719) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7721 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7722 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7723 = and(_T_7721, _T_7722) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7724 = or(_T_7720, _T_7723) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7725 = bits(_T_7724, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7726 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7725 : @[Reg.scala 28:19]
|
|
_T_7726 <= _T_7717 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][93] <= _T_7726 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7727 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7728 = eq(_T_7727, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7729 = and(ic_valid_ff, _T_7728) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7730 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7731 = and(_T_7729, _T_7730) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7733 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7734 = and(_T_7732, _T_7733) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7735 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7736 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7737 = and(_T_7735, _T_7736) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7738 = or(_T_7734, _T_7737) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7739 = bits(_T_7738, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7740 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7739 : @[Reg.scala 28:19]
|
|
_T_7740 <= _T_7731 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][94] <= _T_7740 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7742 = eq(_T_7741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7743 = and(ic_valid_ff, _T_7742) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7745 = and(_T_7743, _T_7744) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7747 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7748 = and(_T_7746, _T_7747) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7749 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7751 = and(_T_7749, _T_7750) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7752 = or(_T_7748, _T_7751) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7753 = bits(_T_7752, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7754 : UInt<1>, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7753 : @[Reg.scala 28:19]
|
|
_T_7754 <= _T_7745 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][95] <= _T_7754 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7755 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7756 = eq(_T_7755, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7757 = and(ic_valid_ff, _T_7756) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7759 = and(_T_7757, _T_7758) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7761 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7762 = and(_T_7760, _T_7761) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7763 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7764 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7765 = and(_T_7763, _T_7764) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7766 = or(_T_7762, _T_7765) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7767 = bits(_T_7766, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7768 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7767 : @[Reg.scala 28:19]
|
|
_T_7768 <= _T_7759 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][96] <= _T_7768 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7769 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7770 = eq(_T_7769, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7771 = and(ic_valid_ff, _T_7770) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7772 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7773 = and(_T_7771, _T_7772) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7775 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7776 = and(_T_7774, _T_7775) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7777 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7778 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7779 = and(_T_7777, _T_7778) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7780 = or(_T_7776, _T_7779) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7781 = bits(_T_7780, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7782 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7781 : @[Reg.scala 28:19]
|
|
_T_7782 <= _T_7773 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][97] <= _T_7782 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7783 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7784 = eq(_T_7783, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7785 = and(ic_valid_ff, _T_7784) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7786 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7787 = and(_T_7785, _T_7786) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7789 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7790 = and(_T_7788, _T_7789) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7791 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7792 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7793 = and(_T_7791, _T_7792) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7794 = or(_T_7790, _T_7793) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7795 = bits(_T_7794, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7796 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7795 : @[Reg.scala 28:19]
|
|
_T_7796 <= _T_7787 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][98] <= _T_7796 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7797 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7798 = eq(_T_7797, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7799 = and(ic_valid_ff, _T_7798) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7800 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7801 = and(_T_7799, _T_7800) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7802 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7803 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7804 = and(_T_7802, _T_7803) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7805 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7806 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7807 = and(_T_7805, _T_7806) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7808 = or(_T_7804, _T_7807) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7810 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7809 : @[Reg.scala 28:19]
|
|
_T_7810 <= _T_7801 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][99] <= _T_7810 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7811 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7812 = eq(_T_7811, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7813 = and(ic_valid_ff, _T_7812) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7814 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7815 = and(_T_7813, _T_7814) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7817 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7818 = and(_T_7816, _T_7817) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7819 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7820 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7821 = and(_T_7819, _T_7820) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7822 = or(_T_7818, _T_7821) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7823 = bits(_T_7822, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7824 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7823 : @[Reg.scala 28:19]
|
|
_T_7824 <= _T_7815 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][100] <= _T_7824 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7825 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7826 = eq(_T_7825, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7827 = and(ic_valid_ff, _T_7826) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7829 = and(_T_7827, _T_7828) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7831 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7832 = and(_T_7830, _T_7831) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7833 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7834 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7835 = and(_T_7833, _T_7834) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7836 = or(_T_7832, _T_7835) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7837 = bits(_T_7836, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7838 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7837 : @[Reg.scala 28:19]
|
|
_T_7838 <= _T_7829 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][101] <= _T_7838 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7839 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7840 = eq(_T_7839, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7841 = and(ic_valid_ff, _T_7840) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7842 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7843 = and(_T_7841, _T_7842) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7844 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7845 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7846 = and(_T_7844, _T_7845) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7847 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7848 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7849 = and(_T_7847, _T_7848) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7850 = or(_T_7846, _T_7849) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7851 = bits(_T_7850, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7852 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7851 : @[Reg.scala 28:19]
|
|
_T_7852 <= _T_7843 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][102] <= _T_7852 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7853 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7854 = eq(_T_7853, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7855 = and(ic_valid_ff, _T_7854) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7856 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7857 = and(_T_7855, _T_7856) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7859 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7860 = and(_T_7858, _T_7859) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7861 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7862 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7863 = and(_T_7861, _T_7862) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7864 = or(_T_7860, _T_7863) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7865 = bits(_T_7864, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7866 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7865 : @[Reg.scala 28:19]
|
|
_T_7866 <= _T_7857 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][103] <= _T_7866 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7867 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7868 = eq(_T_7867, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7869 = and(ic_valid_ff, _T_7868) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7870 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7871 = and(_T_7869, _T_7870) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7873 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7874 = and(_T_7872, _T_7873) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7875 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7876 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7877 = and(_T_7875, _T_7876) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7878 = or(_T_7874, _T_7877) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7879 = bits(_T_7878, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7880 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7879 : @[Reg.scala 28:19]
|
|
_T_7880 <= _T_7871 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][104] <= _T_7880 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7881 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7882 = eq(_T_7881, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7883 = and(ic_valid_ff, _T_7882) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7884 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7885 = and(_T_7883, _T_7884) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7886 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7887 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7888 = and(_T_7886, _T_7887) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7889 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7890 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7891 = and(_T_7889, _T_7890) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7892 = or(_T_7888, _T_7891) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7893 = bits(_T_7892, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7894 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7893 : @[Reg.scala 28:19]
|
|
_T_7894 <= _T_7885 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][105] <= _T_7894 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7895 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7896 = eq(_T_7895, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7897 = and(ic_valid_ff, _T_7896) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7898 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7899 = and(_T_7897, _T_7898) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7901 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7902 = and(_T_7900, _T_7901) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7903 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7904 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7905 = and(_T_7903, _T_7904) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7906 = or(_T_7902, _T_7905) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7907 = bits(_T_7906, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7908 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7907 : @[Reg.scala 28:19]
|
|
_T_7908 <= _T_7899 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][106] <= _T_7908 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7910 = eq(_T_7909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7911 = and(ic_valid_ff, _T_7910) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7913 = and(_T_7911, _T_7912) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7915 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7916 = and(_T_7914, _T_7915) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7917 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7918 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7919 = and(_T_7917, _T_7918) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7920 = or(_T_7916, _T_7919) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7921 = bits(_T_7920, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7922 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7921 : @[Reg.scala 28:19]
|
|
_T_7922 <= _T_7913 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][107] <= _T_7922 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7923 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7924 = eq(_T_7923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7925 = and(ic_valid_ff, _T_7924) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7926 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7927 = and(_T_7925, _T_7926) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7929 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7930 = and(_T_7928, _T_7929) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7931 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7932 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7933 = and(_T_7931, _T_7932) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7934 = or(_T_7930, _T_7933) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7936 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7935 : @[Reg.scala 28:19]
|
|
_T_7936 <= _T_7927 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][108] <= _T_7936 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7937 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7938 = eq(_T_7937, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7939 = and(ic_valid_ff, _T_7938) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7940 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7941 = and(_T_7939, _T_7940) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7942 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7943 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7944 = and(_T_7942, _T_7943) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7945 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7946 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7947 = and(_T_7945, _T_7946) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7948 = or(_T_7944, _T_7947) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7949 = bits(_T_7948, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7950 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7949 : @[Reg.scala 28:19]
|
|
_T_7950 <= _T_7941 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][109] <= _T_7950 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7951 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7952 = eq(_T_7951, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7953 = and(ic_valid_ff, _T_7952) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7954 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7955 = and(_T_7953, _T_7954) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7956 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7957 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7958 = and(_T_7956, _T_7957) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7959 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7960 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7961 = and(_T_7959, _T_7960) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7962 = or(_T_7958, _T_7961) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7963 = bits(_T_7962, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7964 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7963 : @[Reg.scala 28:19]
|
|
_T_7964 <= _T_7955 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][110] <= _T_7964 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7966 = eq(_T_7965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7967 = and(ic_valid_ff, _T_7966) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7969 = and(_T_7967, _T_7968) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7970 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7971 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7972 = and(_T_7970, _T_7971) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7973 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7974 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7975 = and(_T_7973, _T_7974) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7976 = or(_T_7972, _T_7975) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7977 = bits(_T_7976, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7978 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7977 : @[Reg.scala 28:19]
|
|
_T_7978 <= _T_7969 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][111] <= _T_7978 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7979 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7980 = eq(_T_7979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7981 = and(ic_valid_ff, _T_7980) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7982 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7983 = and(_T_7981, _T_7982) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7984 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7985 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_7986 = and(_T_7984, _T_7985) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_7987 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_7988 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_7989 = and(_T_7987, _T_7988) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_7990 = or(_T_7986, _T_7989) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_7991 = bits(_T_7990, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_7992 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7991 : @[Reg.scala 28:19]
|
|
_T_7992 <= _T_7983 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][112] <= _T_7992 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_7993 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_7994 = eq(_T_7993, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_7995 = and(ic_valid_ff, _T_7994) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_7996 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_7997 = and(_T_7995, _T_7996) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_7998 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_7999 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8000 = and(_T_7998, _T_7999) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8001 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8002 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8003 = and(_T_8001, _T_8002) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8004 = or(_T_8000, _T_8003) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8005 = bits(_T_8004, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8006 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8005 : @[Reg.scala 28:19]
|
|
_T_8006 <= _T_7997 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][113] <= _T_8006 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8007 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8008 = eq(_T_8007, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8009 = and(ic_valid_ff, _T_8008) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8010 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8011 = and(_T_8009, _T_8010) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8012 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8013 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8014 = and(_T_8012, _T_8013) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8015 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8016 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8017 = and(_T_8015, _T_8016) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8018 = or(_T_8014, _T_8017) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8019 = bits(_T_8018, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8020 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8019 : @[Reg.scala 28:19]
|
|
_T_8020 <= _T_8011 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][114] <= _T_8020 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8022 = eq(_T_8021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8023 = and(ic_valid_ff, _T_8022) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8025 = and(_T_8023, _T_8024) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8026 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8027 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8028 = and(_T_8026, _T_8027) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8029 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8030 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8031 = and(_T_8029, _T_8030) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8032 = or(_T_8028, _T_8031) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8033 = bits(_T_8032, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8034 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8033 : @[Reg.scala 28:19]
|
|
_T_8034 <= _T_8025 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][115] <= _T_8034 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8035 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8036 = eq(_T_8035, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8037 = and(ic_valid_ff, _T_8036) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8039 = and(_T_8037, _T_8038) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8040 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8041 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8042 = and(_T_8040, _T_8041) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8043 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8044 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8045 = and(_T_8043, _T_8044) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8046 = or(_T_8042, _T_8045) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8047 = bits(_T_8046, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8048 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8047 : @[Reg.scala 28:19]
|
|
_T_8048 <= _T_8039 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][116] <= _T_8048 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8049 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8050 = eq(_T_8049, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8051 = and(ic_valid_ff, _T_8050) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8052 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8053 = and(_T_8051, _T_8052) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8054 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8055 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8056 = and(_T_8054, _T_8055) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8057 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8058 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8059 = and(_T_8057, _T_8058) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8060 = or(_T_8056, _T_8059) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8062 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8061 : @[Reg.scala 28:19]
|
|
_T_8062 <= _T_8053 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][117] <= _T_8062 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8063 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8064 = eq(_T_8063, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8065 = and(ic_valid_ff, _T_8064) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8066 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8067 = and(_T_8065, _T_8066) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8068 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8069 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8070 = and(_T_8068, _T_8069) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8071 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8072 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8073 = and(_T_8071, _T_8072) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8074 = or(_T_8070, _T_8073) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8075 = bits(_T_8074, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8076 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8075 : @[Reg.scala 28:19]
|
|
_T_8076 <= _T_8067 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][118] <= _T_8076 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8077 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8078 = eq(_T_8077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8079 = and(ic_valid_ff, _T_8078) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8080 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8081 = and(_T_8079, _T_8080) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8082 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8083 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8084 = and(_T_8082, _T_8083) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8085 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8086 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8087 = and(_T_8085, _T_8086) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8088 = or(_T_8084, _T_8087) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8089 = bits(_T_8088, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8090 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8089 : @[Reg.scala 28:19]
|
|
_T_8090 <= _T_8081 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][119] <= _T_8090 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8091 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8092 = eq(_T_8091, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8093 = and(ic_valid_ff, _T_8092) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8094 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8095 = and(_T_8093, _T_8094) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8096 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8097 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8098 = and(_T_8096, _T_8097) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8099 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8100 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8101 = and(_T_8099, _T_8100) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8102 = or(_T_8098, _T_8101) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8103 = bits(_T_8102, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8104 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8103 : @[Reg.scala 28:19]
|
|
_T_8104 <= _T_8095 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][120] <= _T_8104 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8105 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8106 = eq(_T_8105, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8107 = and(ic_valid_ff, _T_8106) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8108 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8109 = and(_T_8107, _T_8108) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8111 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8112 = and(_T_8110, _T_8111) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8113 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8114 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8115 = and(_T_8113, _T_8114) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8116 = or(_T_8112, _T_8115) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8117 = bits(_T_8116, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8118 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8117 : @[Reg.scala 28:19]
|
|
_T_8118 <= _T_8109 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][121] <= _T_8118 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8119 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8120 = eq(_T_8119, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8121 = and(ic_valid_ff, _T_8120) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8122 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8123 = and(_T_8121, _T_8122) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8125 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8126 = and(_T_8124, _T_8125) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8127 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8128 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8129 = and(_T_8127, _T_8128) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8130 = or(_T_8126, _T_8129) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8131 = bits(_T_8130, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8132 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8131 : @[Reg.scala 28:19]
|
|
_T_8132 <= _T_8123 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][122] <= _T_8132 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8133 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8134 = eq(_T_8133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8135 = and(ic_valid_ff, _T_8134) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8136 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8137 = and(_T_8135, _T_8136) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8139 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8140 = and(_T_8138, _T_8139) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8141 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8142 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8143 = and(_T_8141, _T_8142) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8144 = or(_T_8140, _T_8143) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8145 = bits(_T_8144, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8146 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8145 : @[Reg.scala 28:19]
|
|
_T_8146 <= _T_8137 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][123] <= _T_8146 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8147 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8148 = eq(_T_8147, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8149 = and(ic_valid_ff, _T_8148) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8150 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8153 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8154 = and(_T_8152, _T_8153) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8155 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8156 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8157 = and(_T_8155, _T_8156) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8158 = or(_T_8154, _T_8157) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8159 = bits(_T_8158, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8160 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8159 : @[Reg.scala 28:19]
|
|
_T_8160 <= _T_8151 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][124] <= _T_8160 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8161 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8162 = eq(_T_8161, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8163 = and(ic_valid_ff, _T_8162) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8164 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8165 = and(_T_8163, _T_8164) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8167 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8168 = and(_T_8166, _T_8167) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8169 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8170 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8171 = and(_T_8169, _T_8170) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8172 = or(_T_8168, _T_8171) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8173 = bits(_T_8172, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8174 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8173 : @[Reg.scala 28:19]
|
|
_T_8174 <= _T_8165 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][125] <= _T_8174 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8175 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8176 = eq(_T_8175, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8177 = and(ic_valid_ff, _T_8176) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8179 = and(_T_8177, _T_8178) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8181 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8182 = and(_T_8180, _T_8181) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8183 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8184 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8185 = and(_T_8183, _T_8184) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8186 = or(_T_8182, _T_8185) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8188 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8187 : @[Reg.scala 28:19]
|
|
_T_8188 <= _T_8179 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][126] <= _T_8188 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8190 = eq(_T_8189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8191 = and(ic_valid_ff, _T_8190) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8193 = and(_T_8191, _T_8192) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8195 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8196 = and(_T_8194, _T_8195) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8197 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8198 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8200 = or(_T_8196, _T_8199) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8201 = bits(_T_8200, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8202 : UInt<1>, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8201 : @[Reg.scala 28:19]
|
|
_T_8202 <= _T_8193 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][127] <= _T_8202 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8203 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8204 = eq(_T_8203, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8205 = and(ic_valid_ff, _T_8204) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8206 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8207 = and(_T_8205, _T_8206) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8209 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8210 = and(_T_8208, _T_8209) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8211 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8212 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8213 = and(_T_8211, _T_8212) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8214 = or(_T_8210, _T_8213) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8215 = bits(_T_8214, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8216 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8215 : @[Reg.scala 28:19]
|
|
_T_8216 <= _T_8207 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][96] <= _T_8216 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8217 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8218 = eq(_T_8217, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8219 = and(ic_valid_ff, _T_8218) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8220 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8221 = and(_T_8219, _T_8220) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8223 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8224 = and(_T_8222, _T_8223) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8225 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8226 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8227 = and(_T_8225, _T_8226) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8228 = or(_T_8224, _T_8227) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8229 = bits(_T_8228, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8230 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8229 : @[Reg.scala 28:19]
|
|
_T_8230 <= _T_8221 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][97] <= _T_8230 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8231 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8232 = eq(_T_8231, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8233 = and(ic_valid_ff, _T_8232) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8234 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8235 = and(_T_8233, _T_8234) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8237 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8238 = and(_T_8236, _T_8237) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8239 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8240 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8241 = and(_T_8239, _T_8240) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8242 = or(_T_8238, _T_8241) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8243 = bits(_T_8242, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8244 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8243 : @[Reg.scala 28:19]
|
|
_T_8244 <= _T_8235 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][98] <= _T_8244 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8246 = eq(_T_8245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8247 = and(ic_valid_ff, _T_8246) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8249 = and(_T_8247, _T_8248) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8251 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8252 = and(_T_8250, _T_8251) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8253 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8254 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8255 = and(_T_8253, _T_8254) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8256 = or(_T_8252, _T_8255) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8257 = bits(_T_8256, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8258 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8257 : @[Reg.scala 28:19]
|
|
_T_8258 <= _T_8249 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][99] <= _T_8258 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8259 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8260 = eq(_T_8259, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8261 = and(ic_valid_ff, _T_8260) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8262 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8263 = and(_T_8261, _T_8262) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8264 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8265 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8266 = and(_T_8264, _T_8265) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8267 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8268 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8269 = and(_T_8267, _T_8268) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8270 = or(_T_8266, _T_8269) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8271 = bits(_T_8270, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8272 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8271 : @[Reg.scala 28:19]
|
|
_T_8272 <= _T_8263 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][100] <= _T_8272 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8273 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8274 = eq(_T_8273, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8275 = and(ic_valid_ff, _T_8274) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8276 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8277 = and(_T_8275, _T_8276) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8278 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8279 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8280 = and(_T_8278, _T_8279) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8281 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8282 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8283 = and(_T_8281, _T_8282) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8284 = or(_T_8280, _T_8283) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8285 = bits(_T_8284, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8286 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8285 : @[Reg.scala 28:19]
|
|
_T_8286 <= _T_8277 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][101] <= _T_8286 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8287 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8288 = eq(_T_8287, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8289 = and(ic_valid_ff, _T_8288) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8290 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8291 = and(_T_8289, _T_8290) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8292 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8293 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8294 = and(_T_8292, _T_8293) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8295 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8296 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8297 = and(_T_8295, _T_8296) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8298 = or(_T_8294, _T_8297) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8299 = bits(_T_8298, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8300 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8299 : @[Reg.scala 28:19]
|
|
_T_8300 <= _T_8291 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][102] <= _T_8300 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8301 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8302 = eq(_T_8301, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8303 = and(ic_valid_ff, _T_8302) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8304 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8305 = and(_T_8303, _T_8304) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8306 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8307 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8308 = and(_T_8306, _T_8307) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8309 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8310 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8311 = and(_T_8309, _T_8310) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8312 = or(_T_8308, _T_8311) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8314 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8313 : @[Reg.scala 28:19]
|
|
_T_8314 <= _T_8305 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][103] <= _T_8314 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8315 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8316 = eq(_T_8315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8317 = and(ic_valid_ff, _T_8316) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8319 = and(_T_8317, _T_8318) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8321 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8322 = and(_T_8320, _T_8321) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8323 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8324 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8325 = and(_T_8323, _T_8324) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8326 = or(_T_8322, _T_8325) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8327 = bits(_T_8326, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8328 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8327 : @[Reg.scala 28:19]
|
|
_T_8328 <= _T_8319 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][104] <= _T_8328 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8329 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8330 = eq(_T_8329, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8331 = and(ic_valid_ff, _T_8330) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8332 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8333 = and(_T_8331, _T_8332) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8334 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8335 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8336 = and(_T_8334, _T_8335) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8337 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8338 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8339 = and(_T_8337, _T_8338) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8340 = or(_T_8336, _T_8339) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8341 = bits(_T_8340, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8342 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8341 : @[Reg.scala 28:19]
|
|
_T_8342 <= _T_8333 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][105] <= _T_8342 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8343 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8344 = eq(_T_8343, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8345 = and(ic_valid_ff, _T_8344) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8346 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8347 = and(_T_8345, _T_8346) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8348 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8349 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8350 = and(_T_8348, _T_8349) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8351 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8352 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8353 = and(_T_8351, _T_8352) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8354 = or(_T_8350, _T_8353) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8355 = bits(_T_8354, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8356 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8355 : @[Reg.scala 28:19]
|
|
_T_8356 <= _T_8347 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][106] <= _T_8356 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8357 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8358 = eq(_T_8357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8359 = and(ic_valid_ff, _T_8358) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8360 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8361 = and(_T_8359, _T_8360) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8362 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8363 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8364 = and(_T_8362, _T_8363) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8365 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8366 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8367 = and(_T_8365, _T_8366) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8368 = or(_T_8364, _T_8367) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8369 = bits(_T_8368, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8370 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8369 : @[Reg.scala 28:19]
|
|
_T_8370 <= _T_8361 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][107] <= _T_8370 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8371 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8372 = eq(_T_8371, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8373 = and(ic_valid_ff, _T_8372) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8374 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8375 = and(_T_8373, _T_8374) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8376 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8377 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8378 = and(_T_8376, _T_8377) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8379 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8380 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8381 = and(_T_8379, _T_8380) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8382 = or(_T_8378, _T_8381) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8383 = bits(_T_8382, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8384 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8383 : @[Reg.scala 28:19]
|
|
_T_8384 <= _T_8375 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][108] <= _T_8384 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8385 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8386 = eq(_T_8385, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8387 = and(ic_valid_ff, _T_8386) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8388 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8389 = and(_T_8387, _T_8388) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8390 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8391 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8392 = and(_T_8390, _T_8391) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8393 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8394 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8395 = and(_T_8393, _T_8394) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8396 = or(_T_8392, _T_8395) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8397 = bits(_T_8396, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8398 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8397 : @[Reg.scala 28:19]
|
|
_T_8398 <= _T_8389 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][109] <= _T_8398 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8399 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8400 = eq(_T_8399, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8401 = and(ic_valid_ff, _T_8400) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8402 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8403 = and(_T_8401, _T_8402) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8404 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8405 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8406 = and(_T_8404, _T_8405) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8407 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8408 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8409 = and(_T_8407, _T_8408) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8410 = or(_T_8406, _T_8409) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8411 = bits(_T_8410, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8412 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8411 : @[Reg.scala 28:19]
|
|
_T_8412 <= _T_8403 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][110] <= _T_8412 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8414 = eq(_T_8413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8415 = and(ic_valid_ff, _T_8414) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8417 = and(_T_8415, _T_8416) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8418 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8419 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8420 = and(_T_8418, _T_8419) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8421 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8422 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8423 = and(_T_8421, _T_8422) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8424 = or(_T_8420, _T_8423) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8425 = bits(_T_8424, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8426 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8425 : @[Reg.scala 28:19]
|
|
_T_8426 <= _T_8417 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][111] <= _T_8426 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8427 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8428 = eq(_T_8427, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8429 = and(ic_valid_ff, _T_8428) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8430 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8431 = and(_T_8429, _T_8430) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8432 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8433 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8434 = and(_T_8432, _T_8433) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8435 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8436 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8437 = and(_T_8435, _T_8436) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8438 = or(_T_8434, _T_8437) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8440 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8439 : @[Reg.scala 28:19]
|
|
_T_8440 <= _T_8431 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][112] <= _T_8440 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8441 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8442 = eq(_T_8441, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8443 = and(ic_valid_ff, _T_8442) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8444 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8445 = and(_T_8443, _T_8444) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8446 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8447 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8448 = and(_T_8446, _T_8447) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8449 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8450 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8451 = and(_T_8449, _T_8450) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8452 = or(_T_8448, _T_8451) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8453 = bits(_T_8452, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8454 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8453 : @[Reg.scala 28:19]
|
|
_T_8454 <= _T_8445 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][113] <= _T_8454 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8455 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8456 = eq(_T_8455, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8457 = and(ic_valid_ff, _T_8456) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8459 = and(_T_8457, _T_8458) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8460 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8461 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8462 = and(_T_8460, _T_8461) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8463 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8464 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8465 = and(_T_8463, _T_8464) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8466 = or(_T_8462, _T_8465) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8467 = bits(_T_8466, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8468 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8467 : @[Reg.scala 28:19]
|
|
_T_8468 <= _T_8459 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][114] <= _T_8468 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8470 = eq(_T_8469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8471 = and(ic_valid_ff, _T_8470) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8473 = and(_T_8471, _T_8472) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8475 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8476 = and(_T_8474, _T_8475) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8477 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8478 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8479 = and(_T_8477, _T_8478) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8480 = or(_T_8476, _T_8479) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8481 = bits(_T_8480, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8482 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8481 : @[Reg.scala 28:19]
|
|
_T_8482 <= _T_8473 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][115] <= _T_8482 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8483 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8484 = eq(_T_8483, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8485 = and(ic_valid_ff, _T_8484) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8486 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8487 = and(_T_8485, _T_8486) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8488 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8489 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8490 = and(_T_8488, _T_8489) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8491 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8492 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8493 = and(_T_8491, _T_8492) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8494 = or(_T_8490, _T_8493) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8495 = bits(_T_8494, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8496 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8495 : @[Reg.scala 28:19]
|
|
_T_8496 <= _T_8487 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][116] <= _T_8496 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8497 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8498 = eq(_T_8497, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8499 = and(ic_valid_ff, _T_8498) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8500 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8501 = and(_T_8499, _T_8500) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8502 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8503 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8504 = and(_T_8502, _T_8503) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8505 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8506 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8507 = and(_T_8505, _T_8506) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8508 = or(_T_8504, _T_8507) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8509 = bits(_T_8508, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8510 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8509 : @[Reg.scala 28:19]
|
|
_T_8510 <= _T_8501 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][117] <= _T_8510 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8511 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8512 = eq(_T_8511, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8513 = and(ic_valid_ff, _T_8512) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8514 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8515 = and(_T_8513, _T_8514) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8516 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8517 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8518 = and(_T_8516, _T_8517) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8519 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8520 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8521 = and(_T_8519, _T_8520) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8522 = or(_T_8518, _T_8521) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8523 = bits(_T_8522, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8524 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8523 : @[Reg.scala 28:19]
|
|
_T_8524 <= _T_8515 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][118] <= _T_8524 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8525 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8527 = and(ic_valid_ff, _T_8526) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8529 = and(_T_8527, _T_8528) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8531 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8532 = and(_T_8530, _T_8531) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8534 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8535 = and(_T_8533, _T_8534) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8536 = or(_T_8532, _T_8535) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8537 = bits(_T_8536, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8538 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8537 : @[Reg.scala 28:19]
|
|
_T_8538 <= _T_8529 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][119] <= _T_8538 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8539 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8540 = eq(_T_8539, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8541 = and(ic_valid_ff, _T_8540) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8542 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8543 = and(_T_8541, _T_8542) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8544 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8545 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8546 = and(_T_8544, _T_8545) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8547 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8548 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8549 = and(_T_8547, _T_8548) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8550 = or(_T_8546, _T_8549) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8551 = bits(_T_8550, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8552 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8551 : @[Reg.scala 28:19]
|
|
_T_8552 <= _T_8543 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][120] <= _T_8552 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8553 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8554 = eq(_T_8553, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8555 = and(ic_valid_ff, _T_8554) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8556 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8557 = and(_T_8555, _T_8556) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8558 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8559 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8560 = and(_T_8558, _T_8559) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8561 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8562 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8563 = and(_T_8561, _T_8562) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8564 = or(_T_8560, _T_8563) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8566 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8565 : @[Reg.scala 28:19]
|
|
_T_8566 <= _T_8557 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][121] <= _T_8566 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8567 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8568 = eq(_T_8567, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8569 = and(ic_valid_ff, _T_8568) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8570 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8571 = and(_T_8569, _T_8570) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8572 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8573 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8574 = and(_T_8572, _T_8573) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8575 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8576 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8577 = and(_T_8575, _T_8576) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8578 = or(_T_8574, _T_8577) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8579 = bits(_T_8578, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8580 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8579 : @[Reg.scala 28:19]
|
|
_T_8580 <= _T_8571 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][122] <= _T_8580 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8581 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8582 = eq(_T_8581, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8583 = and(ic_valid_ff, _T_8582) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8584 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8585 = and(_T_8583, _T_8584) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8586 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8587 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8588 = and(_T_8586, _T_8587) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8589 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8590 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8591 = and(_T_8589, _T_8590) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8592 = or(_T_8588, _T_8591) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8593 = bits(_T_8592, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8594 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8593 : @[Reg.scala 28:19]
|
|
_T_8594 <= _T_8585 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][123] <= _T_8594 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8595 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8596 = eq(_T_8595, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8597 = and(ic_valid_ff, _T_8596) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8599 = and(_T_8597, _T_8598) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8601 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8602 = and(_T_8600, _T_8601) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8603 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8604 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8605 = and(_T_8603, _T_8604) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8606 = or(_T_8602, _T_8605) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8607 = bits(_T_8606, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8608 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8607 : @[Reg.scala 28:19]
|
|
_T_8608 <= _T_8599 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][124] <= _T_8608 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8609 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8610 = eq(_T_8609, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8611 = and(ic_valid_ff, _T_8610) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8612 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8613 = and(_T_8611, _T_8612) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8614 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8615 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8616 = and(_T_8614, _T_8615) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8617 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8618 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8619 = and(_T_8617, _T_8618) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8620 = or(_T_8616, _T_8619) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8621 = bits(_T_8620, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8622 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8621 : @[Reg.scala 28:19]
|
|
_T_8622 <= _T_8613 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][125] <= _T_8622 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8623 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8624 = eq(_T_8623, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8625 = and(ic_valid_ff, _T_8624) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8626 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8627 = and(_T_8625, _T_8626) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8628 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8629 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8630 = and(_T_8628, _T_8629) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8631 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8632 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8633 = and(_T_8631, _T_8632) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8634 = or(_T_8630, _T_8633) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8635 = bits(_T_8634, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8636 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8635 : @[Reg.scala 28:19]
|
|
_T_8636 <= _T_8627 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][126] <= _T_8636 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8637 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 791:49]
|
|
node _T_8638 = eq(_T_8637, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:33]
|
|
node _T_8639 = and(ic_valid_ff, _T_8638) @[el2_ifu_mem_ctl.scala 791:31]
|
|
node _T_8640 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 791:58]
|
|
node _T_8641 = and(_T_8639, _T_8640) @[el2_ifu_mem_ctl.scala 791:56]
|
|
node _T_8642 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 792:36]
|
|
node _T_8643 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:75]
|
|
node _T_8644 = and(_T_8642, _T_8643) @[el2_ifu_mem_ctl.scala 792:58]
|
|
node _T_8645 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 792:101]
|
|
node _T_8646 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 792:140]
|
|
node _T_8647 = and(_T_8645, _T_8646) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_8648 = or(_T_8644, _T_8647) @[el2_ifu_mem_ctl.scala 792:80]
|
|
node _T_8649 = bits(_T_8648, 0, 0) @[el2_ifu_mem_ctl.scala 792:146]
|
|
reg _T_8650 : UInt<1>, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8649 : @[Reg.scala 28:19]
|
|
_T_8650 <= _T_8641 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][127] <= _T_8650 @[el2_ifu_mem_ctl.scala 790:39]
|
|
node _T_8651 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8652 = mux(_T_8651, UInt<1>("h00"), ic_tag_valid_out[0][0]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8653 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8654 = mux(_T_8653, UInt<1>("h00"), ic_tag_valid_out[0][1]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8655 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8656 = mux(_T_8655, UInt<1>("h00"), ic_tag_valid_out[0][2]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8657 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8658 = mux(_T_8657, UInt<1>("h00"), ic_tag_valid_out[0][3]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8659 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8660 = mux(_T_8659, UInt<1>("h00"), ic_tag_valid_out[0][4]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8661 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8662 = mux(_T_8661, UInt<1>("h00"), ic_tag_valid_out[0][5]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8663 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8664 = mux(_T_8663, UInt<1>("h00"), ic_tag_valid_out[0][6]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8665 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8666 = mux(_T_8665, UInt<1>("h00"), ic_tag_valid_out[0][7]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8667 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8668 = mux(_T_8667, UInt<1>("h00"), ic_tag_valid_out[0][8]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8669 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8670 = mux(_T_8669, UInt<1>("h00"), ic_tag_valid_out[0][9]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8671 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8672 = mux(_T_8671, UInt<1>("h00"), ic_tag_valid_out[0][10]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8673 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8674 = mux(_T_8673, UInt<1>("h00"), ic_tag_valid_out[0][11]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8675 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8676 = mux(_T_8675, UInt<1>("h00"), ic_tag_valid_out[0][12]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8677 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8678 = mux(_T_8677, UInt<1>("h00"), ic_tag_valid_out[0][13]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8679 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8680 = mux(_T_8679, UInt<1>("h00"), ic_tag_valid_out[0][14]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8682 = mux(_T_8681, UInt<1>("h00"), ic_tag_valid_out[0][15]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8683 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8684 = mux(_T_8683, UInt<1>("h00"), ic_tag_valid_out[0][16]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8685 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8686 = mux(_T_8685, UInt<1>("h00"), ic_tag_valid_out[0][17]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8687 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8688 = mux(_T_8687, UInt<1>("h00"), ic_tag_valid_out[0][18]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8690 = mux(_T_8689, UInt<1>("h00"), ic_tag_valid_out[0][19]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8691 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8692 = mux(_T_8691, UInt<1>("h00"), ic_tag_valid_out[0][20]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8693 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8694 = mux(_T_8693, UInt<1>("h00"), ic_tag_valid_out[0][21]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8696 = mux(_T_8695, UInt<1>("h00"), ic_tag_valid_out[0][22]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8697 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8698 = mux(_T_8697, UInt<1>("h00"), ic_tag_valid_out[0][23]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8699 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8700 = mux(_T_8699, UInt<1>("h00"), ic_tag_valid_out[0][24]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8701 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8702 = mux(_T_8701, UInt<1>("h00"), ic_tag_valid_out[0][25]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8703 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8704 = mux(_T_8703, UInt<1>("h00"), ic_tag_valid_out[0][26]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8705 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8706 = mux(_T_8705, UInt<1>("h00"), ic_tag_valid_out[0][27]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8707 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8708 = mux(_T_8707, UInt<1>("h00"), ic_tag_valid_out[0][28]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8709 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8710 = mux(_T_8709, UInt<1>("h00"), ic_tag_valid_out[0][29]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8711 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8712 = mux(_T_8711, UInt<1>("h00"), ic_tag_valid_out[0][30]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8713 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8714 = mux(_T_8713, UInt<1>("h00"), ic_tag_valid_out[0][31]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8716 = mux(_T_8715, UInt<1>("h00"), ic_tag_valid_out[0][32]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8718 = mux(_T_8717, UInt<1>("h00"), ic_tag_valid_out[0][33]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8720 = mux(_T_8719, UInt<1>("h00"), ic_tag_valid_out[0][34]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8722 = mux(_T_8721, UInt<1>("h00"), ic_tag_valid_out[0][35]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8724 = mux(_T_8723, UInt<1>("h00"), ic_tag_valid_out[0][36]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8726 = mux(_T_8725, UInt<1>("h00"), ic_tag_valid_out[0][37]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8727 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8728 = mux(_T_8727, UInt<1>("h00"), ic_tag_valid_out[0][38]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8730 = mux(_T_8729, UInt<1>("h00"), ic_tag_valid_out[0][39]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8731 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8732 = mux(_T_8731, UInt<1>("h00"), ic_tag_valid_out[0][40]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8733 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8734 = mux(_T_8733, UInt<1>("h00"), ic_tag_valid_out[0][41]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8735 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8736 = mux(_T_8735, UInt<1>("h00"), ic_tag_valid_out[0][42]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8737 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8738 = mux(_T_8737, UInt<1>("h00"), ic_tag_valid_out[0][43]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8739 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8740 = mux(_T_8739, UInt<1>("h00"), ic_tag_valid_out[0][44]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8741 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8742 = mux(_T_8741, UInt<1>("h00"), ic_tag_valid_out[0][45]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8743 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8744 = mux(_T_8743, UInt<1>("h00"), ic_tag_valid_out[0][46]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8745 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8746 = mux(_T_8745, UInt<1>("h00"), ic_tag_valid_out[0][47]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8747 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8748 = mux(_T_8747, UInt<1>("h00"), ic_tag_valid_out[0][48]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8749 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8750 = mux(_T_8749, UInt<1>("h00"), ic_tag_valid_out[0][49]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8751 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8752 = mux(_T_8751, UInt<1>("h00"), ic_tag_valid_out[0][50]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8753 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8754 = mux(_T_8753, UInt<1>("h00"), ic_tag_valid_out[0][51]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8755 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8756 = mux(_T_8755, UInt<1>("h00"), ic_tag_valid_out[0][52]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8757 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8758 = mux(_T_8757, UInt<1>("h00"), ic_tag_valid_out[0][53]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8759 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8760 = mux(_T_8759, UInt<1>("h00"), ic_tag_valid_out[0][54]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8761 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8762 = mux(_T_8761, UInt<1>("h00"), ic_tag_valid_out[0][55]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8763 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8764 = mux(_T_8763, UInt<1>("h00"), ic_tag_valid_out[0][56]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8765 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8766 = mux(_T_8765, UInt<1>("h00"), ic_tag_valid_out[0][57]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8767 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8768 = mux(_T_8767, UInt<1>("h00"), ic_tag_valid_out[0][58]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8769 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8770 = mux(_T_8769, UInt<1>("h00"), ic_tag_valid_out[0][59]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8771 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8772 = mux(_T_8771, UInt<1>("h00"), ic_tag_valid_out[0][60]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8773 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8774 = mux(_T_8773, UInt<1>("h00"), ic_tag_valid_out[0][61]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8775 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8776 = mux(_T_8775, UInt<1>("h00"), ic_tag_valid_out[0][62]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8777 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8778 = mux(_T_8777, UInt<1>("h00"), ic_tag_valid_out[0][63]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8780 = mux(_T_8779, UInt<1>("h00"), ic_tag_valid_out[0][64]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8782 = mux(_T_8781, UInt<1>("h00"), ic_tag_valid_out[0][65]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8784 = mux(_T_8783, UInt<1>("h00"), ic_tag_valid_out[0][66]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8786 = mux(_T_8785, UInt<1>("h00"), ic_tag_valid_out[0][67]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8788 = mux(_T_8787, UInt<1>("h00"), ic_tag_valid_out[0][68]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8790 = mux(_T_8789, UInt<1>("h00"), ic_tag_valid_out[0][69]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8792 = mux(_T_8791, UInt<1>("h00"), ic_tag_valid_out[0][70]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8794 = mux(_T_8793, UInt<1>("h00"), ic_tag_valid_out[0][71]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8796 = mux(_T_8795, UInt<1>("h00"), ic_tag_valid_out[0][72]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8798 = mux(_T_8797, UInt<1>("h00"), ic_tag_valid_out[0][73]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8799 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8800 = mux(_T_8799, UInt<1>("h00"), ic_tag_valid_out[0][74]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8801 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8802 = mux(_T_8801, UInt<1>("h00"), ic_tag_valid_out[0][75]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8803 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8804 = mux(_T_8803, UInt<1>("h00"), ic_tag_valid_out[0][76]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8805 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8806 = mux(_T_8805, UInt<1>("h00"), ic_tag_valid_out[0][77]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8807 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8808 = mux(_T_8807, UInt<1>("h00"), ic_tag_valid_out[0][78]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8809 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8810 = mux(_T_8809, UInt<1>("h00"), ic_tag_valid_out[0][79]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8811 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8812 = mux(_T_8811, UInt<1>("h00"), ic_tag_valid_out[0][80]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8813 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8814 = mux(_T_8813, UInt<1>("h00"), ic_tag_valid_out[0][81]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8816 = mux(_T_8815, UInt<1>("h00"), ic_tag_valid_out[0][82]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8817 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8818 = mux(_T_8817, UInt<1>("h00"), ic_tag_valid_out[0][83]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8819 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8820 = mux(_T_8819, UInt<1>("h00"), ic_tag_valid_out[0][84]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8821 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8822 = mux(_T_8821, UInt<1>("h00"), ic_tag_valid_out[0][85]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8823 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8824 = mux(_T_8823, UInt<1>("h00"), ic_tag_valid_out[0][86]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8826 = mux(_T_8825, UInt<1>("h00"), ic_tag_valid_out[0][87]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8827 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8828 = mux(_T_8827, UInt<1>("h00"), ic_tag_valid_out[0][88]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8829 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8830 = mux(_T_8829, UInt<1>("h00"), ic_tag_valid_out[0][89]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8831 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8832 = mux(_T_8831, UInt<1>("h00"), ic_tag_valid_out[0][90]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8833 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8834 = mux(_T_8833, UInt<1>("h00"), ic_tag_valid_out[0][91]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8835 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8836 = mux(_T_8835, UInt<1>("h00"), ic_tag_valid_out[0][92]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8837 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8838 = mux(_T_8837, UInt<1>("h00"), ic_tag_valid_out[0][93]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8839 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8840 = mux(_T_8839, UInt<1>("h00"), ic_tag_valid_out[0][94]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8841 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8842 = mux(_T_8841, UInt<1>("h00"), ic_tag_valid_out[0][95]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8843 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8844 = mux(_T_8843, UInt<1>("h00"), ic_tag_valid_out[0][96]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8846 = mux(_T_8845, UInt<1>("h00"), ic_tag_valid_out[0][97]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8847 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8848 = mux(_T_8847, UInt<1>("h00"), ic_tag_valid_out[0][98]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8849 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8850 = mux(_T_8849, UInt<1>("h00"), ic_tag_valid_out[0][99]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8851 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8852 = mux(_T_8851, UInt<1>("h00"), ic_tag_valid_out[0][100]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8853 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8854 = mux(_T_8853, UInt<1>("h00"), ic_tag_valid_out[0][101]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8856 = mux(_T_8855, UInt<1>("h00"), ic_tag_valid_out[0][102]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8857 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8858 = mux(_T_8857, UInt<1>("h00"), ic_tag_valid_out[0][103]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8859 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8860 = mux(_T_8859, UInt<1>("h00"), ic_tag_valid_out[0][104]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8861 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8862 = mux(_T_8861, UInt<1>("h00"), ic_tag_valid_out[0][105]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8863 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8864 = mux(_T_8863, UInt<1>("h00"), ic_tag_valid_out[0][106]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8865 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8866 = mux(_T_8865, UInt<1>("h00"), ic_tag_valid_out[0][107]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8867 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8868 = mux(_T_8867, UInt<1>("h00"), ic_tag_valid_out[0][108]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8869 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8870 = mux(_T_8869, UInt<1>("h00"), ic_tag_valid_out[0][109]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8871 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8872 = mux(_T_8871, UInt<1>("h00"), ic_tag_valid_out[0][110]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8873 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8874 = mux(_T_8873, UInt<1>("h00"), ic_tag_valid_out[0][111]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8876 = mux(_T_8875, UInt<1>("h00"), ic_tag_valid_out[0][112]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8877 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8878 = mux(_T_8877, UInt<1>("h00"), ic_tag_valid_out[0][113]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8880 = mux(_T_8879, UInt<1>("h00"), ic_tag_valid_out[0][114]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8881 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8882 = mux(_T_8881, UInt<1>("h00"), ic_tag_valid_out[0][115]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8883 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8884 = mux(_T_8883, UInt<1>("h00"), ic_tag_valid_out[0][116]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8886 = mux(_T_8885, UInt<1>("h00"), ic_tag_valid_out[0][117]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8887 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8888 = mux(_T_8887, UInt<1>("h00"), ic_tag_valid_out[0][118]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8889 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8890 = mux(_T_8889, UInt<1>("h00"), ic_tag_valid_out[0][119]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8891 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8892 = mux(_T_8891, UInt<1>("h00"), ic_tag_valid_out[0][120]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8893 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8894 = mux(_T_8893, UInt<1>("h00"), ic_tag_valid_out[0][121]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8895 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8896 = mux(_T_8895, UInt<1>("h00"), ic_tag_valid_out[0][122]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8897 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8898 = mux(_T_8897, UInt<1>("h00"), ic_tag_valid_out[0][123]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8899 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8900 = mux(_T_8899, UInt<1>("h00"), ic_tag_valid_out[0][124]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8901 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8902 = mux(_T_8901, UInt<1>("h00"), ic_tag_valid_out[0][125]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8903 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8904 = mux(_T_8903, UInt<1>("h00"), ic_tag_valid_out[0][126]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_8906 = mux(_T_8905, UInt<1>("h00"), ic_tag_valid_out[0][127]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_8907 = or(_T_8652, _T_8654) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8908 = or(_T_8907, _T_8656) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8909 = or(_T_8908, _T_8658) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8910 = or(_T_8909, _T_8660) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8911 = or(_T_8910, _T_8662) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8912 = or(_T_8911, _T_8664) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8913 = or(_T_8912, _T_8666) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8914 = or(_T_8913, _T_8668) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8915 = or(_T_8914, _T_8670) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8916 = or(_T_8915, _T_8672) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8917 = or(_T_8916, _T_8674) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8918 = or(_T_8917, _T_8676) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8919 = or(_T_8918, _T_8678) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8920 = or(_T_8919, _T_8680) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8921 = or(_T_8920, _T_8682) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8922 = or(_T_8921, _T_8684) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8923 = or(_T_8922, _T_8686) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8924 = or(_T_8923, _T_8688) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8925 = or(_T_8924, _T_8690) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8926 = or(_T_8925, _T_8692) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8927 = or(_T_8926, _T_8694) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8928 = or(_T_8927, _T_8696) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8929 = or(_T_8928, _T_8698) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8930 = or(_T_8929, _T_8700) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8931 = or(_T_8930, _T_8702) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8932 = or(_T_8931, _T_8704) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8933 = or(_T_8932, _T_8706) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8934 = or(_T_8933, _T_8708) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8935 = or(_T_8934, _T_8710) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8936 = or(_T_8935, _T_8712) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8937 = or(_T_8936, _T_8714) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8938 = or(_T_8937, _T_8716) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8939 = or(_T_8938, _T_8718) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8940 = or(_T_8939, _T_8720) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8941 = or(_T_8940, _T_8722) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8942 = or(_T_8941, _T_8724) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8943 = or(_T_8942, _T_8726) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8944 = or(_T_8943, _T_8728) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8945 = or(_T_8944, _T_8730) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8946 = or(_T_8945, _T_8732) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8947 = or(_T_8946, _T_8734) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8948 = or(_T_8947, _T_8736) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8949 = or(_T_8948, _T_8738) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8950 = or(_T_8949, _T_8740) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8951 = or(_T_8950, _T_8742) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8952 = or(_T_8951, _T_8744) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8953 = or(_T_8952, _T_8746) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8954 = or(_T_8953, _T_8748) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8955 = or(_T_8954, _T_8750) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8956 = or(_T_8955, _T_8752) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8957 = or(_T_8956, _T_8754) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8958 = or(_T_8957, _T_8756) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8959 = or(_T_8958, _T_8758) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8960 = or(_T_8959, _T_8760) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8961 = or(_T_8960, _T_8762) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8962 = or(_T_8961, _T_8764) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8963 = or(_T_8962, _T_8766) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8964 = or(_T_8963, _T_8768) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8965 = or(_T_8964, _T_8770) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8966 = or(_T_8965, _T_8772) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8967 = or(_T_8966, _T_8774) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8968 = or(_T_8967, _T_8776) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8969 = or(_T_8968, _T_8778) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8970 = or(_T_8969, _T_8780) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8971 = or(_T_8970, _T_8782) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8972 = or(_T_8971, _T_8784) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8973 = or(_T_8972, _T_8786) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8974 = or(_T_8973, _T_8788) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8975 = or(_T_8974, _T_8790) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8976 = or(_T_8975, _T_8792) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8977 = or(_T_8976, _T_8794) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8978 = or(_T_8977, _T_8796) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8979 = or(_T_8978, _T_8798) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8980 = or(_T_8979, _T_8800) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8981 = or(_T_8980, _T_8802) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8982 = or(_T_8981, _T_8804) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8983 = or(_T_8982, _T_8806) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8984 = or(_T_8983, _T_8808) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8985 = or(_T_8984, _T_8810) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8986 = or(_T_8985, _T_8812) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8987 = or(_T_8986, _T_8814) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8988 = or(_T_8987, _T_8816) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8989 = or(_T_8988, _T_8818) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8990 = or(_T_8989, _T_8820) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8991 = or(_T_8990, _T_8822) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8992 = or(_T_8991, _T_8824) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8993 = or(_T_8992, _T_8826) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8994 = or(_T_8993, _T_8828) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8995 = or(_T_8994, _T_8830) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8996 = or(_T_8995, _T_8832) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8997 = or(_T_8996, _T_8834) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8998 = or(_T_8997, _T_8836) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_8999 = or(_T_8998, _T_8838) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9000 = or(_T_8999, _T_8840) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9001 = or(_T_9000, _T_8842) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9002 = or(_T_9001, _T_8844) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9003 = or(_T_9002, _T_8846) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9004 = or(_T_9003, _T_8848) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9005 = or(_T_9004, _T_8850) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9006 = or(_T_9005, _T_8852) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9007 = or(_T_9006, _T_8854) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9008 = or(_T_9007, _T_8856) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9009 = or(_T_9008, _T_8858) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9010 = or(_T_9009, _T_8860) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9011 = or(_T_9010, _T_8862) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9012 = or(_T_9011, _T_8864) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9013 = or(_T_9012, _T_8866) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9014 = or(_T_9013, _T_8868) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9015 = or(_T_9014, _T_8870) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9016 = or(_T_9015, _T_8872) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9017 = or(_T_9016, _T_8874) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9018 = or(_T_9017, _T_8876) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9019 = or(_T_9018, _T_8878) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9020 = or(_T_9019, _T_8880) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9021 = or(_T_9020, _T_8882) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9022 = or(_T_9021, _T_8884) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9023 = or(_T_9022, _T_8886) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9024 = or(_T_9023, _T_8888) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9025 = or(_T_9024, _T_8890) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9026 = or(_T_9025, _T_8892) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9027 = or(_T_9026, _T_8894) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9028 = or(_T_9027, _T_8896) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9029 = or(_T_9028, _T_8898) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9030 = or(_T_9029, _T_8900) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9031 = or(_T_9030, _T_8902) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9032 = or(_T_9031, _T_8904) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9033 = or(_T_9032, _T_8906) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9034 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9035 = mux(_T_9034, UInt<1>("h00"), ic_tag_valid_out[1][0]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9036 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9037 = mux(_T_9036, UInt<1>("h00"), ic_tag_valid_out[1][1]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9038 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9039 = mux(_T_9038, UInt<1>("h00"), ic_tag_valid_out[1][2]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9040 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9041 = mux(_T_9040, UInt<1>("h00"), ic_tag_valid_out[1][3]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9043 = mux(_T_9042, UInt<1>("h00"), ic_tag_valid_out[1][4]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9044 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9045 = mux(_T_9044, UInt<1>("h00"), ic_tag_valid_out[1][5]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9046 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9047 = mux(_T_9046, UInt<1>("h00"), ic_tag_valid_out[1][6]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9049 = mux(_T_9048, UInt<1>("h00"), ic_tag_valid_out[1][7]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9050 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9051 = mux(_T_9050, UInt<1>("h00"), ic_tag_valid_out[1][8]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9053 = mux(_T_9052, UInt<1>("h00"), ic_tag_valid_out[1][9]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9054 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9055 = mux(_T_9054, UInt<1>("h00"), ic_tag_valid_out[1][10]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9056 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9057 = mux(_T_9056, UInt<1>("h00"), ic_tag_valid_out[1][11]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9059 = mux(_T_9058, UInt<1>("h00"), ic_tag_valid_out[1][12]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9060 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9061 = mux(_T_9060, UInt<1>("h00"), ic_tag_valid_out[1][13]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9062 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9063 = mux(_T_9062, UInt<1>("h00"), ic_tag_valid_out[1][14]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9065 = mux(_T_9064, UInt<1>("h00"), ic_tag_valid_out[1][15]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9066 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9067 = mux(_T_9066, UInt<1>("h00"), ic_tag_valid_out[1][16]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9068 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9069 = mux(_T_9068, UInt<1>("h00"), ic_tag_valid_out[1][17]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9070 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9071 = mux(_T_9070, UInt<1>("h00"), ic_tag_valid_out[1][18]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9072 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9073 = mux(_T_9072, UInt<1>("h00"), ic_tag_valid_out[1][19]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9075 = mux(_T_9074, UInt<1>("h00"), ic_tag_valid_out[1][20]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9076 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9077 = mux(_T_9076, UInt<1>("h00"), ic_tag_valid_out[1][21]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9078 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9079 = mux(_T_9078, UInt<1>("h00"), ic_tag_valid_out[1][22]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9081 = mux(_T_9080, UInt<1>("h00"), ic_tag_valid_out[1][23]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9082 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9083 = mux(_T_9082, UInt<1>("h00"), ic_tag_valid_out[1][24]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9084 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9085 = mux(_T_9084, UInt<1>("h00"), ic_tag_valid_out[1][25]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9087 = mux(_T_9086, UInt<1>("h00"), ic_tag_valid_out[1][26]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9088 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9089 = mux(_T_9088, UInt<1>("h00"), ic_tag_valid_out[1][27]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9091 = mux(_T_9090, UInt<1>("h00"), ic_tag_valid_out[1][28]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9092 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9093 = mux(_T_9092, UInt<1>("h00"), ic_tag_valid_out[1][29]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9094 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9095 = mux(_T_9094, UInt<1>("h00"), ic_tag_valid_out[1][30]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9097 = mux(_T_9096, UInt<1>("h00"), ic_tag_valid_out[1][31]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9099 = mux(_T_9098, UInt<1>("h00"), ic_tag_valid_out[1][32]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9101 = mux(_T_9100, UInt<1>("h00"), ic_tag_valid_out[1][33]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9103 = mux(_T_9102, UInt<1>("h00"), ic_tag_valid_out[1][34]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9105 = mux(_T_9104, UInt<1>("h00"), ic_tag_valid_out[1][35]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9107 = mux(_T_9106, UInt<1>("h00"), ic_tag_valid_out[1][36]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9109 = mux(_T_9108, UInt<1>("h00"), ic_tag_valid_out[1][37]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9110 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9111 = mux(_T_9110, UInt<1>("h00"), ic_tag_valid_out[1][38]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9113 = mux(_T_9112, UInt<1>("h00"), ic_tag_valid_out[1][39]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9115 = mux(_T_9114, UInt<1>("h00"), ic_tag_valid_out[1][40]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9116 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9117 = mux(_T_9116, UInt<1>("h00"), ic_tag_valid_out[1][41]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9118 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9119 = mux(_T_9118, UInt<1>("h00"), ic_tag_valid_out[1][42]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9121 = mux(_T_9120, UInt<1>("h00"), ic_tag_valid_out[1][43]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9123 = mux(_T_9122, UInt<1>("h00"), ic_tag_valid_out[1][44]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9124 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9125 = mux(_T_9124, UInt<1>("h00"), ic_tag_valid_out[1][45]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9126 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9127 = mux(_T_9126, UInt<1>("h00"), ic_tag_valid_out[1][46]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9129 = mux(_T_9128, UInt<1>("h00"), ic_tag_valid_out[1][47]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9130 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9131 = mux(_T_9130, UInt<1>("h00"), ic_tag_valid_out[1][48]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9133 = mux(_T_9132, UInt<1>("h00"), ic_tag_valid_out[1][49]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9134 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9135 = mux(_T_9134, UInt<1>("h00"), ic_tag_valid_out[1][50]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9136 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9137 = mux(_T_9136, UInt<1>("h00"), ic_tag_valid_out[1][51]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9139 = mux(_T_9138, UInt<1>("h00"), ic_tag_valid_out[1][52]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9140 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9141 = mux(_T_9140, UInt<1>("h00"), ic_tag_valid_out[1][53]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9142 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9143 = mux(_T_9142, UInt<1>("h00"), ic_tag_valid_out[1][54]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9145 = mux(_T_9144, UInt<1>("h00"), ic_tag_valid_out[1][55]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9146 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9147 = mux(_T_9146, UInt<1>("h00"), ic_tag_valid_out[1][56]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9148 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9149 = mux(_T_9148, UInt<1>("h00"), ic_tag_valid_out[1][57]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9150 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9151 = mux(_T_9150, UInt<1>("h00"), ic_tag_valid_out[1][58]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9152 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9153 = mux(_T_9152, UInt<1>("h00"), ic_tag_valid_out[1][59]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9155 = mux(_T_9154, UInt<1>("h00"), ic_tag_valid_out[1][60]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9156 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9157 = mux(_T_9156, UInt<1>("h00"), ic_tag_valid_out[1][61]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9158 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9159 = mux(_T_9158, UInt<1>("h00"), ic_tag_valid_out[1][62]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9161 = mux(_T_9160, UInt<1>("h00"), ic_tag_valid_out[1][63]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9163 = mux(_T_9162, UInt<1>("h00"), ic_tag_valid_out[1][64]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9165 = mux(_T_9164, UInt<1>("h00"), ic_tag_valid_out[1][65]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9167 = mux(_T_9166, UInt<1>("h00"), ic_tag_valid_out[1][66]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9169 = mux(_T_9168, UInt<1>("h00"), ic_tag_valid_out[1][67]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9171 = mux(_T_9170, UInt<1>("h00"), ic_tag_valid_out[1][68]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9173 = mux(_T_9172, UInt<1>("h00"), ic_tag_valid_out[1][69]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9175 = mux(_T_9174, UInt<1>("h00"), ic_tag_valid_out[1][70]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9177 = mux(_T_9176, UInt<1>("h00"), ic_tag_valid_out[1][71]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9179 = mux(_T_9178, UInt<1>("h00"), ic_tag_valid_out[1][72]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9181 = mux(_T_9180, UInt<1>("h00"), ic_tag_valid_out[1][73]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9183 = mux(_T_9182, UInt<1>("h00"), ic_tag_valid_out[1][74]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9185 = mux(_T_9184, UInt<1>("h00"), ic_tag_valid_out[1][75]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9187 = mux(_T_9186, UInt<1>("h00"), ic_tag_valid_out[1][76]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9189 = mux(_T_9188, UInt<1>("h00"), ic_tag_valid_out[1][77]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9191 = mux(_T_9190, UInt<1>("h00"), ic_tag_valid_out[1][78]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9193 = mux(_T_9192, UInt<1>("h00"), ic_tag_valid_out[1][79]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9195 = mux(_T_9194, UInt<1>("h00"), ic_tag_valid_out[1][80]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9197 = mux(_T_9196, UInt<1>("h00"), ic_tag_valid_out[1][81]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9199 = mux(_T_9198, UInt<1>("h00"), ic_tag_valid_out[1][82]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9201 = mux(_T_9200, UInt<1>("h00"), ic_tag_valid_out[1][83]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9203 = mux(_T_9202, UInt<1>("h00"), ic_tag_valid_out[1][84]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9205 = mux(_T_9204, UInt<1>("h00"), ic_tag_valid_out[1][85]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9207 = mux(_T_9206, UInt<1>("h00"), ic_tag_valid_out[1][86]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9209 = mux(_T_9208, UInt<1>("h00"), ic_tag_valid_out[1][87]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9211 = mux(_T_9210, UInt<1>("h00"), ic_tag_valid_out[1][88]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9213 = mux(_T_9212, UInt<1>("h00"), ic_tag_valid_out[1][89]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9215 = mux(_T_9214, UInt<1>("h00"), ic_tag_valid_out[1][90]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9217 = mux(_T_9216, UInt<1>("h00"), ic_tag_valid_out[1][91]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9219 = mux(_T_9218, UInt<1>("h00"), ic_tag_valid_out[1][92]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9221 = mux(_T_9220, UInt<1>("h00"), ic_tag_valid_out[1][93]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9223 = mux(_T_9222, UInt<1>("h00"), ic_tag_valid_out[1][94]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9225 = mux(_T_9224, UInt<1>("h00"), ic_tag_valid_out[1][95]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9227 = mux(_T_9226, UInt<1>("h00"), ic_tag_valid_out[1][96]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9229 = mux(_T_9228, UInt<1>("h00"), ic_tag_valid_out[1][97]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9231 = mux(_T_9230, UInt<1>("h00"), ic_tag_valid_out[1][98]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9233 = mux(_T_9232, UInt<1>("h00"), ic_tag_valid_out[1][99]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9235 = mux(_T_9234, UInt<1>("h00"), ic_tag_valid_out[1][100]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9237 = mux(_T_9236, UInt<1>("h00"), ic_tag_valid_out[1][101]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9238 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9239 = mux(_T_9238, UInt<1>("h00"), ic_tag_valid_out[1][102]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9241 = mux(_T_9240, UInt<1>("h00"), ic_tag_valid_out[1][103]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9243 = mux(_T_9242, UInt<1>("h00"), ic_tag_valid_out[1][104]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9244 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9245 = mux(_T_9244, UInt<1>("h00"), ic_tag_valid_out[1][105]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9246 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9247 = mux(_T_9246, UInt<1>("h00"), ic_tag_valid_out[1][106]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9248 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9249 = mux(_T_9248, UInt<1>("h00"), ic_tag_valid_out[1][107]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9251 = mux(_T_9250, UInt<1>("h00"), ic_tag_valid_out[1][108]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9252 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9253 = mux(_T_9252, UInt<1>("h00"), ic_tag_valid_out[1][109]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9254 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9255 = mux(_T_9254, UInt<1>("h00"), ic_tag_valid_out[1][110]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9256 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9257 = mux(_T_9256, UInt<1>("h00"), ic_tag_valid_out[1][111]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9258 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9259 = mux(_T_9258, UInt<1>("h00"), ic_tag_valid_out[1][112]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9260 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9261 = mux(_T_9260, UInt<1>("h00"), ic_tag_valid_out[1][113]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9262 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9263 = mux(_T_9262, UInt<1>("h00"), ic_tag_valid_out[1][114]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9264 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9265 = mux(_T_9264, UInt<1>("h00"), ic_tag_valid_out[1][115]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9266 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9267 = mux(_T_9266, UInt<1>("h00"), ic_tag_valid_out[1][116]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9268 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9269 = mux(_T_9268, UInt<1>("h00"), ic_tag_valid_out[1][117]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9271 = mux(_T_9270, UInt<1>("h00"), ic_tag_valid_out[1][118]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9272 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9273 = mux(_T_9272, UInt<1>("h00"), ic_tag_valid_out[1][119]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9274 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9275 = mux(_T_9274, UInt<1>("h00"), ic_tag_valid_out[1][120]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9276 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9277 = mux(_T_9276, UInt<1>("h00"), ic_tag_valid_out[1][121]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9278 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9279 = mux(_T_9278, UInt<1>("h00"), ic_tag_valid_out[1][122]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9280 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9281 = mux(_T_9280, UInt<1>("h00"), ic_tag_valid_out[1][123]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9283 = mux(_T_9282, UInt<1>("h00"), ic_tag_valid_out[1][124]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9284 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9285 = mux(_T_9284, UInt<1>("h00"), ic_tag_valid_out[1][125]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9286 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9287 = mux(_T_9286, UInt<1>("h00"), ic_tag_valid_out[1][126]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9288 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 796:33]
|
|
node _T_9289 = mux(_T_9288, UInt<1>("h00"), ic_tag_valid_out[1][127]) @[el2_ifu_mem_ctl.scala 796:10]
|
|
node _T_9290 = or(_T_9035, _T_9037) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9291 = or(_T_9290, _T_9039) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9292 = or(_T_9291, _T_9041) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9293 = or(_T_9292, _T_9043) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9294 = or(_T_9293, _T_9045) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9295 = or(_T_9294, _T_9047) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9296 = or(_T_9295, _T_9049) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9297 = or(_T_9296, _T_9051) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9298 = or(_T_9297, _T_9053) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9299 = or(_T_9298, _T_9055) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9300 = or(_T_9299, _T_9057) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9301 = or(_T_9300, _T_9059) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9302 = or(_T_9301, _T_9061) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9303 = or(_T_9302, _T_9063) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9304 = or(_T_9303, _T_9065) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9305 = or(_T_9304, _T_9067) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9306 = or(_T_9305, _T_9069) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9307 = or(_T_9306, _T_9071) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9308 = or(_T_9307, _T_9073) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9309 = or(_T_9308, _T_9075) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9310 = or(_T_9309, _T_9077) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9311 = or(_T_9310, _T_9079) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9312 = or(_T_9311, _T_9081) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9313 = or(_T_9312, _T_9083) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9314 = or(_T_9313, _T_9085) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9315 = or(_T_9314, _T_9087) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9316 = or(_T_9315, _T_9089) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9317 = or(_T_9316, _T_9091) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9318 = or(_T_9317, _T_9093) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9319 = or(_T_9318, _T_9095) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9320 = or(_T_9319, _T_9097) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9321 = or(_T_9320, _T_9099) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9322 = or(_T_9321, _T_9101) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9323 = or(_T_9322, _T_9103) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9324 = or(_T_9323, _T_9105) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9325 = or(_T_9324, _T_9107) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9326 = or(_T_9325, _T_9109) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9327 = or(_T_9326, _T_9111) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9328 = or(_T_9327, _T_9113) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9329 = or(_T_9328, _T_9115) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9330 = or(_T_9329, _T_9117) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9331 = or(_T_9330, _T_9119) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9332 = or(_T_9331, _T_9121) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9333 = or(_T_9332, _T_9123) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9334 = or(_T_9333, _T_9125) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9335 = or(_T_9334, _T_9127) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9336 = or(_T_9335, _T_9129) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9337 = or(_T_9336, _T_9131) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9338 = or(_T_9337, _T_9133) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9339 = or(_T_9338, _T_9135) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9340 = or(_T_9339, _T_9137) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9341 = or(_T_9340, _T_9139) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9342 = or(_T_9341, _T_9141) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9343 = or(_T_9342, _T_9143) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9344 = or(_T_9343, _T_9145) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9345 = or(_T_9344, _T_9147) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9346 = or(_T_9345, _T_9149) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9347 = or(_T_9346, _T_9151) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9348 = or(_T_9347, _T_9153) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9349 = or(_T_9348, _T_9155) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9350 = or(_T_9349, _T_9157) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9351 = or(_T_9350, _T_9159) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9352 = or(_T_9351, _T_9161) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9353 = or(_T_9352, _T_9163) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9354 = or(_T_9353, _T_9165) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9355 = or(_T_9354, _T_9167) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9356 = or(_T_9355, _T_9169) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9357 = or(_T_9356, _T_9171) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9358 = or(_T_9357, _T_9173) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9359 = or(_T_9358, _T_9175) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9360 = or(_T_9359, _T_9177) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9361 = or(_T_9360, _T_9179) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9362 = or(_T_9361, _T_9181) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9363 = or(_T_9362, _T_9183) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9364 = or(_T_9363, _T_9185) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9365 = or(_T_9364, _T_9187) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9366 = or(_T_9365, _T_9189) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9367 = or(_T_9366, _T_9191) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9368 = or(_T_9367, _T_9193) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9369 = or(_T_9368, _T_9195) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9370 = or(_T_9369, _T_9197) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9371 = or(_T_9370, _T_9199) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9372 = or(_T_9371, _T_9201) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9373 = or(_T_9372, _T_9203) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9374 = or(_T_9373, _T_9205) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9375 = or(_T_9374, _T_9207) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9376 = or(_T_9375, _T_9209) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9377 = or(_T_9376, _T_9211) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9378 = or(_T_9377, _T_9213) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9379 = or(_T_9378, _T_9215) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9380 = or(_T_9379, _T_9217) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9381 = or(_T_9380, _T_9219) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9382 = or(_T_9381, _T_9221) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9383 = or(_T_9382, _T_9223) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9384 = or(_T_9383, _T_9225) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9385 = or(_T_9384, _T_9227) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9386 = or(_T_9385, _T_9229) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9387 = or(_T_9386, _T_9231) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9388 = or(_T_9387, _T_9233) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9389 = or(_T_9388, _T_9235) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9390 = or(_T_9389, _T_9237) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9391 = or(_T_9390, _T_9239) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9392 = or(_T_9391, _T_9241) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9393 = or(_T_9392, _T_9243) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9394 = or(_T_9393, _T_9245) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9395 = or(_T_9394, _T_9247) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9396 = or(_T_9395, _T_9249) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9397 = or(_T_9396, _T_9251) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9398 = or(_T_9397, _T_9253) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9399 = or(_T_9398, _T_9255) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9400 = or(_T_9399, _T_9257) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9401 = or(_T_9400, _T_9259) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9402 = or(_T_9401, _T_9261) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9403 = or(_T_9402, _T_9263) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9404 = or(_T_9403, _T_9265) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9405 = or(_T_9404, _T_9267) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9406 = or(_T_9405, _T_9269) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9407 = or(_T_9406, _T_9271) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9408 = or(_T_9407, _T_9273) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9409 = or(_T_9408, _T_9275) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9410 = or(_T_9409, _T_9277) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9411 = or(_T_9410, _T_9279) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9412 = or(_T_9411, _T_9281) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9413 = or(_T_9412, _T_9283) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9414 = or(_T_9413, _T_9285) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9415 = or(_T_9414, _T_9287) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node _T_9416 = or(_T_9415, _T_9289) @[el2_ifu_mem_ctl.scala 796:91]
|
|
node ic_tag_valid_unq = cat(_T_9416, _T_9033) @[Cat.scala 29:58]
|
|
wire way_status_hit_new : UInt<1>
|
|
way_status_hit_new <= UInt<1>("h00")
|
|
node _T_9417 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 821:33]
|
|
node _T_9418 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 821:63]
|
|
node _T_9419 = and(_T_9417, _T_9418) @[el2_ifu_mem_ctl.scala 821:51]
|
|
node _T_9420 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 821:79]
|
|
node _T_9421 = and(_T_9419, _T_9420) @[el2_ifu_mem_ctl.scala 821:67]
|
|
node _T_9422 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 821:97]
|
|
node _T_9423 = eq(_T_9422, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 821:86]
|
|
node _T_9424 = or(_T_9421, _T_9423) @[el2_ifu_mem_ctl.scala 821:84]
|
|
replace_way_mb_any[0] <= _T_9424 @[el2_ifu_mem_ctl.scala 821:29]
|
|
node _T_9425 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 822:62]
|
|
node _T_9426 = and(way_status_mb_ff, _T_9425) @[el2_ifu_mem_ctl.scala 822:50]
|
|
node _T_9427 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 822:78]
|
|
node _T_9428 = and(_T_9426, _T_9427) @[el2_ifu_mem_ctl.scala 822:66]
|
|
node _T_9429 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 822:96]
|
|
node _T_9430 = eq(_T_9429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 822:85]
|
|
node _T_9431 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 822:112]
|
|
node _T_9432 = and(_T_9430, _T_9431) @[el2_ifu_mem_ctl.scala 822:100]
|
|
node _T_9433 = or(_T_9428, _T_9432) @[el2_ifu_mem_ctl.scala 822:83]
|
|
replace_way_mb_any[1] <= _T_9433 @[el2_ifu_mem_ctl.scala 822:29]
|
|
node _T_9434 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 823:41]
|
|
way_status_hit_new <= _T_9434 @[el2_ifu_mem_ctl.scala 823:26]
|
|
way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 824:26]
|
|
node _T_9435 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 826:47]
|
|
node _T_9436 = bits(_T_9435, 0, 0) @[el2_ifu_mem_ctl.scala 826:60]
|
|
node _T_9437 = mux(_T_9436, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 826:26]
|
|
way_status_new <= _T_9437 @[el2_ifu_mem_ctl.scala 826:20]
|
|
node _T_9438 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 827:45]
|
|
node _T_9439 = or(_T_9438, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 827:58]
|
|
way_status_wr_en <= _T_9439 @[el2_ifu_mem_ctl.scala 827:22]
|
|
node _T_9440 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 828:74]
|
|
node bus_wren_0 = and(_T_9440, miss_pending) @[el2_ifu_mem_ctl.scala 828:98]
|
|
node _T_9441 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 828:74]
|
|
node bus_wren_1 = and(_T_9441, miss_pending) @[el2_ifu_mem_ctl.scala 828:98]
|
|
node _T_9442 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 830:84]
|
|
node _T_9443 = and(_T_9442, miss_pending) @[el2_ifu_mem_ctl.scala 830:108]
|
|
node bus_wren_last_0 = and(_T_9443, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 830:123]
|
|
node _T_9444 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 830:84]
|
|
node _T_9445 = and(_T_9444, miss_pending) @[el2_ifu_mem_ctl.scala 830:108]
|
|
node bus_wren_last_1 = and(_T_9445, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 830:123]
|
|
node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 831:84]
|
|
node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 831:84]
|
|
node _T_9446 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 832:73]
|
|
node _T_9447 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 832:73]
|
|
node _T_9448 = cat(_T_9447, _T_9446) @[Cat.scala 29:58]
|
|
ifu_tag_wren <= _T_9448 @[el2_ifu_mem_ctl.scala 832:18]
|
|
node _T_9449 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 847:63]
|
|
node _T_9450 = and(_T_9449, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 847:85]
|
|
node _T_9451 = bits(_T_9450, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_9452 = mux(_T_9451, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_9453 = and(ic_tag_valid_unq, _T_9452) @[el2_ifu_mem_ctl.scala 847:39]
|
|
io.ic_tag_valid <= _T_9453 @[el2_ifu_mem_ctl.scala 847:19]
|
|
wire ic_debug_rd_en_ff : UInt<1>
|
|
ic_debug_rd_en_ff <= UInt<1>("h00")
|
|
wire ic_debug_way_ff : UInt<2>
|
|
ic_debug_way_ff <= UInt<1>("h00")
|
|
node _T_9454 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_9455 = mux(_T_9454, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_9456 = and(ic_debug_way_ff, _T_9455) @[el2_ifu_mem_ctl.scala 850:67]
|
|
node _T_9457 = and(ic_tag_valid_unq, _T_9456) @[el2_ifu_mem_ctl.scala 850:48]
|
|
node _T_9458 = orr(_T_9457) @[el2_ifu_mem_ctl.scala 850:115]
|
|
ic_debug_tag_val_rd_out <= _T_9458 @[el2_ifu_mem_ctl.scala 850:27]
|
|
reg _T_9459 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 852:58]
|
|
_T_9459 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 852:58]
|
|
io.ifu_pmu_bus_trxn <= _T_9459 @[el2_ifu_mem_ctl.scala 852:23]
|
|
reg _T_9460 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 853:58]
|
|
_T_9460 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 853:58]
|
|
io.ifu_pmu_bus_busy <= _T_9460 @[el2_ifu_mem_ctl.scala 853:23]
|
|
reg _T_9461 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 854:59]
|
|
_T_9461 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 854:59]
|
|
io.ifu_pmu_bus_error <= _T_9461 @[el2_ifu_mem_ctl.scala 854:24]
|
|
node _T_9462 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 855:78]
|
|
node _T_9463 = and(ifu_bus_arvalid_ff, _T_9462) @[el2_ifu_mem_ctl.scala 855:76]
|
|
node _T_9464 = and(_T_9463, miss_pending) @[el2_ifu_mem_ctl.scala 855:98]
|
|
reg _T_9465 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 855:56]
|
|
_T_9465 <= _T_9464 @[el2_ifu_mem_ctl.scala 855:56]
|
|
io.ifu_pmu_ic_hit <= _T_9465 @[el2_ifu_mem_ctl.scala 855:21]
|
|
reg _T_9466 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 856:57]
|
|
_T_9466 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 856:57]
|
|
io.ifu_pmu_ic_miss <= _T_9466 @[el2_ifu_mem_ctl.scala 856:22]
|
|
io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 857:20]
|
|
node _T_9467 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 858:66]
|
|
io.ic_debug_tag_array <= _T_9467 @[el2_ifu_mem_ctl.scala 858:25]
|
|
io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 859:21]
|
|
io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 860:21]
|
|
node _T_9468 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 861:64]
|
|
node _T_9469 = eq(_T_9468, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 861:71]
|
|
node _T_9470 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 861:117]
|
|
node _T_9471 = eq(_T_9470, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 861:124]
|
|
node _T_9472 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 862:43]
|
|
node _T_9473 = eq(_T_9472, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 862:50]
|
|
node _T_9474 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 862:96]
|
|
node _T_9475 = eq(_T_9474, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 862:103]
|
|
node _T_9476 = cat(_T_9473, _T_9475) @[Cat.scala 29:58]
|
|
node _T_9477 = cat(_T_9469, _T_9471) @[Cat.scala 29:58]
|
|
node _T_9478 = cat(_T_9477, _T_9476) @[Cat.scala 29:58]
|
|
io.ic_debug_way <= _T_9478 @[el2_ifu_mem_ctl.scala 861:19]
|
|
node _T_9479 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 863:65]
|
|
node _T_9480 = bits(_T_9479, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_9481 = mux(_T_9480, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_9482 = and(_T_9481, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 863:90]
|
|
ic_debug_tag_wr_en <= _T_9482 @[el2_ifu_mem_ctl.scala 863:22]
|
|
node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 864:53]
|
|
node _T_9483 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 865:72]
|
|
reg _T_9484 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9483 : @[Reg.scala 28:19]
|
|
_T_9484 <= io.ic_debug_way @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_way_ff <= _T_9484 @[el2_ifu_mem_ctl.scala 865:19]
|
|
node _T_9485 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 866:92]
|
|
reg _T_9486 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9485 : @[Reg.scala 28:19]
|
|
_T_9486 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_ict_array_sel_ff <= _T_9486 @[el2_ifu_mem_ctl.scala 866:29]
|
|
reg _T_9487 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 867:54]
|
|
_T_9487 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 867:54]
|
|
ic_debug_rd_en_ff <= _T_9487 @[el2_ifu_mem_ctl.scala 867:21]
|
|
node _T_9488 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 868:111]
|
|
reg _T_9489 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9488 : @[Reg.scala 28:19]
|
|
_T_9489 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.ifu_ic_debug_rd_data_valid <= _T_9489 @[el2_ifu_mem_ctl.scala 868:33]
|
|
node _T_9490 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9491 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9492 = cat(_T_9491, _T_9490) @[Cat.scala 29:58]
|
|
node _T_9493 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_9494 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_9495 = cat(_T_9494, _T_9493) @[Cat.scala 29:58]
|
|
node _T_9496 = cat(_T_9495, _T_9492) @[Cat.scala 29:58]
|
|
node _T_9497 = orr(_T_9496) @[el2_ifu_mem_ctl.scala 869:213]
|
|
node _T_9498 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9499 = or(_T_9498, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 870:62]
|
|
node _T_9500 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 870:110]
|
|
node _T_9501 = eq(_T_9499, _T_9500) @[el2_ifu_mem_ctl.scala 870:85]
|
|
node _T_9502 = and(UInt<1>("h01"), _T_9501) @[el2_ifu_mem_ctl.scala 870:27]
|
|
node _T_9503 = or(_T_9497, _T_9502) @[el2_ifu_mem_ctl.scala 869:216]
|
|
node _T_9504 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9505 = or(_T_9504, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 871:62]
|
|
node _T_9506 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 871:110]
|
|
node _T_9507 = eq(_T_9505, _T_9506) @[el2_ifu_mem_ctl.scala 871:85]
|
|
node _T_9508 = and(UInt<1>("h01"), _T_9507) @[el2_ifu_mem_ctl.scala 871:27]
|
|
node _T_9509 = or(_T_9503, _T_9508) @[el2_ifu_mem_ctl.scala 870:134]
|
|
node _T_9510 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9511 = or(_T_9510, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 872:62]
|
|
node _T_9512 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 872:110]
|
|
node _T_9513 = eq(_T_9511, _T_9512) @[el2_ifu_mem_ctl.scala 872:85]
|
|
node _T_9514 = and(UInt<1>("h01"), _T_9513) @[el2_ifu_mem_ctl.scala 872:27]
|
|
node _T_9515 = or(_T_9509, _T_9514) @[el2_ifu_mem_ctl.scala 871:134]
|
|
node _T_9516 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9517 = or(_T_9516, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 873:62]
|
|
node _T_9518 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 873:110]
|
|
node _T_9519 = eq(_T_9517, _T_9518) @[el2_ifu_mem_ctl.scala 873:85]
|
|
node _T_9520 = and(UInt<1>("h01"), _T_9519) @[el2_ifu_mem_ctl.scala 873:27]
|
|
node _T_9521 = or(_T_9515, _T_9520) @[el2_ifu_mem_ctl.scala 872:134]
|
|
node _T_9522 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_9523 = or(_T_9522, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 874:62]
|
|
node _T_9524 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 874:110]
|
|
node _T_9525 = eq(_T_9523, _T_9524) @[el2_ifu_mem_ctl.scala 874:85]
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node _T_9526 = and(UInt<1>("h00"), _T_9525) @[el2_ifu_mem_ctl.scala 874:27]
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node _T_9527 = or(_T_9521, _T_9526) @[el2_ifu_mem_ctl.scala 873:134]
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node _T_9528 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_9529 = or(_T_9528, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 875:62]
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node _T_9530 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 875:110]
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node _T_9531 = eq(_T_9529, _T_9530) @[el2_ifu_mem_ctl.scala 875:85]
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node _T_9532 = and(UInt<1>("h00"), _T_9531) @[el2_ifu_mem_ctl.scala 875:27]
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node _T_9533 = or(_T_9527, _T_9532) @[el2_ifu_mem_ctl.scala 874:134]
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node _T_9534 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_9535 = or(_T_9534, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 876:62]
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node _T_9536 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 876:110]
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node _T_9537 = eq(_T_9535, _T_9536) @[el2_ifu_mem_ctl.scala 876:85]
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node _T_9538 = and(UInt<1>("h00"), _T_9537) @[el2_ifu_mem_ctl.scala 876:27]
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node _T_9539 = or(_T_9533, _T_9538) @[el2_ifu_mem_ctl.scala 875:134]
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node _T_9540 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_9541 = or(_T_9540, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 877:62]
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node _T_9542 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 877:110]
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node _T_9543 = eq(_T_9541, _T_9542) @[el2_ifu_mem_ctl.scala 877:85]
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node _T_9544 = and(UInt<1>("h00"), _T_9543) @[el2_ifu_mem_ctl.scala 877:27]
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node ifc_region_acc_okay = or(_T_9539, _T_9544) @[el2_ifu_mem_ctl.scala 876:134]
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node _T_9545 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 878:40]
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node _T_9546 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 878:65]
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node _T_9547 = and(_T_9545, _T_9546) @[el2_ifu_mem_ctl.scala 878:63]
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node ifc_region_acc_fault_memory_bf = and(_T_9547, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 878:86]
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node _T_9548 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 879:63]
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ifc_region_acc_fault_final_bf <= _T_9548 @[el2_ifu_mem_ctl.scala 879:33]
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reg _T_9549 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 880:66]
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_T_9549 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 880:66]
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ifc_region_acc_fault_memory_f <= _T_9549 @[el2_ifu_mem_ctl.scala 880:33]
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