22 lines
516 B
Verilog
22 lines
516 B
Verilog
module rvdff(
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input [31:0] io_in,
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output [31:0] io_out
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);
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assign io_out = io_in; // @[GCD.scala 12:10]
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endmodule
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module caller(
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input clock,
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input reset,
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input [31:0] io_in,
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output [31:0] io_out
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);
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wire [31:0] u0_io_in; // @[GCD.scala 21:18]
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wire [31:0] u0_io_out; // @[GCD.scala 21:18]
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rvdff u0 ( // @[GCD.scala 21:18]
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.io_in(u0_io_in),
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.io_out(u0_io_out)
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);
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assign io_out = u0_io_out; // @[GCD.scala 22:6]
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assign u0_io_in = io_in; // @[GCD.scala 22:6]
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endmodule
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