71 lines
1.8 KiB
Verilog
71 lines
1.8 KiB
Verilog
module rvdffs(
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input clock,
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input reset,
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input [31:0] io_din,
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input io_en,
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input io_clear,
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output [31:0] io_out
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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`endif // RANDOMIZE_REG_INIT
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wire [9:0] _T_9 = {io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
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wire [18:0] _T_18 = {_T_9,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
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wire [27:0] _T_27 = {_T_18,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
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wire [31:0] _T_31 = {_T_27,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
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wire [31:0] _T_32 = io_din & _T_31; // @[el2_ifu_ic_mem.scala 93:30]
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reg [31:0] _T_33; // @[Reg.scala 27:20]
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assign io_out = _T_33; // @[el2_ifu_ic_mem.scala 93:10]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {1{`RANDOM}};
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_T_33 = _RAND_0[31:0];
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`endif // RANDOMIZE_REG_INIT
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge clock) begin
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if (reset) begin
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_T_33 <= 32'h0;
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end else if (io_en) begin
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_T_33 <= _T_32;
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end
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end
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endmodule
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