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quasar/EL2_IC_DATA.fir

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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit EL2_IC_DATA :
module EL2_IC_DATA :
input clock : Clock
input reset : UInt<1>
output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip test_in : UInt<71>, test : UInt}
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23]
io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 196:16]
io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 197:16]
io.test <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 198:11]
node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 200:70]
node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 200:68]
node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15]
node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 200:94]
node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 201:70]
node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 201:68]
wire _T_6 : UInt<1>[2] @[el2_lib.scala 185:48]
_T_6[0] <= _T_5 @[el2_lib.scala 185:48]
_T_6[1] <= _T_5 @[el2_lib.scala 185:48]
node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58]
node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 201:94]
wire ic_bank_wr_data : UInt<71>
ic_bank_wr_data <= UInt<1>("h00")
wire ic_rd_en_with_debug : UInt<1>
ic_rd_en_with_debug <= UInt<1>("h00")
node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 206:45]
node _T_9 = bits(_T_8, 0, 0) @[el2_ifu_ic_mem.scala 206:66]
node _T_10 = cat(io.ic_debug_addr, UInt<2>("h00")) @[Cat.scala 29:58]
node ic_rw_addr_q = mux(_T_9, _T_10, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 206:25]
node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 208:38]
node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 208:79]
node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 208:79]
node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 210:113]
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 210:38]
node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 210:17]
node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 210:113]
node _T_20 = bits(_T_19, 0, 0) @[Bitwise.scala 72:15]
node _T_21 = mux(_T_20, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 210:38]
node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 210:17]
node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 211:111]
node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:111]
node ic_debug_sel_sb = cat(_T_26, _T_24) @[Cat.scala 29:58]
node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 212:77]
node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
node _T_30 = bits(ic_bank_wr_data, 0, 0) @[el2_ifu_ic_mem.scala 212:144]
node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, _T_30) @[el2_ifu_ic_mem.scala 212:60]
node _T_31 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 212:77]
node _T_32 = and(_T_31, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
node _T_33 = bits(_T_32, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
node _T_34 = bits(ic_bank_wr_data, 1, 1) @[el2_ifu_ic_mem.scala 212:144]
node ic_sb_wr_data_1 = mux(_T_33, io.ic_debug_wr_data, _T_34) @[el2_ifu_ic_mem.scala 212:60]
node _T_35 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
node _T_36 = bits(_T_35, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
node _T_38 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
node _T_39 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
node _T_40 = bits(_T_39, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
node _T_41 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
node _T_42 = eq(_T_41, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
node _T_43 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
node _T_44 = and(_T_42, _T_43) @[el2_ifu_ic_mem.scala 215:98]
node _T_45 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
node _T_46 = bits(_T_45, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
node _T_47 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
node _T_48 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
node _T_51 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
node _T_52 = eq(_T_51, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
node _T_53 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ic_mem.scala 217:99]
node _T_55 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_56 = mux(_T_40, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_57 = mux(_T_46, _T_47, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_58 = mux(_T_50, _T_54, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_59 = or(_T_55, _T_56) @[Mux.scala 27:72]
node _T_60 = or(_T_59, _T_57) @[Mux.scala 27:72]
node _T_61 = or(_T_60, _T_58) @[Mux.scala 27:72]
wire _T_62 : UInt<1> @[Mux.scala 27:72]
_T_62 <= _T_61 @[Mux.scala 27:72]
node _T_63 = and(_T_62, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
node _T_64 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
node _T_67 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
node _T_68 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
node _T_69 = bits(_T_68, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
node _T_70 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
node _T_71 = eq(_T_70, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
node _T_72 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ic_mem.scala 215:98]
node _T_74 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
node _T_75 = bits(_T_74, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
node _T_76 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
node _T_77 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
node _T_79 = bits(_T_78, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
node _T_80 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
node _T_81 = eq(_T_80, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
node _T_82 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
node _T_83 = and(_T_81, _T_82) @[el2_ifu_ic_mem.scala 217:99]
node _T_84 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_69, _T_73, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_75, _T_76, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_79, _T_83, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = or(_T_84, _T_85) @[Mux.scala 27:72]
node _T_89 = or(_T_88, _T_86) @[Mux.scala 27:72]
node _T_90 = or(_T_89, _T_87) @[Mux.scala 27:72]
wire _T_91 : UInt<1> @[Mux.scala 27:72]
_T_91 <= _T_90 @[Mux.scala 27:72]
node _T_92 = and(_T_91, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
node ic_b_rden = cat(_T_92, _T_63) @[Cat.scala 29:58]
node _T_93 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 218:89]
node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15]
node ic_b_sb_rden_0 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_95 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 218:89]
node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 72:15]
node ic_b_sb_rden_1 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_97 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
node _T_98 = or(_T_97, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_99 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
node _T_100 = or(_T_98, _T_99) @[el2_ifu_ic_mem.scala 220:43]
node _T_101 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
node _T_102 = or(_T_101, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_103 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
node _T_104 = or(_T_102, _T_103) @[el2_ifu_ic_mem.scala 220:43]
node ic_bank_way_clken_0 = cat(_T_100, _T_104) @[Cat.scala 29:58]
node _T_105 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
node _T_106 = or(_T_105, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_107 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
node _T_108 = or(_T_106, _T_107) @[el2_ifu_ic_mem.scala 220:43]
node _T_109 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
node _T_110 = or(_T_109, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_111 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
node _T_112 = or(_T_110, _T_111) @[el2_ifu_ic_mem.scala 220:43]
node ic_bank_way_clken_1 = cat(_T_108, _T_112) @[Cat.scala 29:58]
node _T_113 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 222:74]
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 222:61]
node _T_115 = and(io.ic_debug_rd_en, _T_114) @[el2_ifu_ic_mem.scala 222:58]
node _T_116 = or(io.ic_rd_en, _T_115) @[el2_ifu_ic_mem.scala 222:38]
ic_rd_en_with_debug <= _T_116 @[el2_ifu_ic_mem.scala 222:23]
node _T_117 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 224:37]
node _T_118 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 224:71]
node _T_119 = eq(_T_118, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 224:77]
node _T_120 = and(_T_117, _T_119) @[el2_ifu_ic_mem.scala 224:56]
node _T_121 = and(_T_120, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 224:86]
node _T_122 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 224:124]
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 224:110]
node ic_rw_addr_wrap = and(_T_121, _T_123) @[el2_ifu_ic_mem.scala 224:108]
node _T_124 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 226:40]
node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_ic_mem.scala 226:58]
node _T_126 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 226:77]
node _T_127 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 227:21]
node _T_128 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 227:82]
node _T_129 = cat(_T_127, _T_128) @[Cat.scala 29:58]
node _T_130 = mux(_T_125, _T_126, _T_129) @[el2_ifu_ic_mem.scala 226:38]
node _T_131 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 228:17]
wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 226:34]
ic_rw_addr_bank_q[0] <= _T_130 @[el2_ifu_ic_mem.scala 226:34]
ic_rw_addr_bank_q[1] <= _T_131 @[el2_ifu_ic_mem.scala 226:34]
reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 233:29]
ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 233:29]
node _T_132 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 234:43]
reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:30]
ic_rw_addr_ff <= _T_132 @[el2_ifu_ic_mem.scala 234:30]
reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:38]
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 235:38]
reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:34]
ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 236:34]
node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 238:84]
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21]
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 245:73]
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 246:83]
node _T_137 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 247:26]
node _T_138 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:52]
node _T_139 = and(_T_137, _T_138) @[el2_ifu_ic_mem.scala 247:30]
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
when _T_140 : @[el2_ifu_ic_mem.scala 247:64]
infer mport _T_141 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15]
_T_141[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
skip @[el2_ifu_ic_mem.scala 247:64]
else : @[el2_ifu_ic_mem.scala 249:69]
node _T_142 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 249:33]
node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
node _T_144 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 249:57]
node _T_145 = and(_T_143, _T_144) @[el2_ifu_ic_mem.scala 249:36]
node _T_146 = bits(_T_145, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
when _T_146 : @[el2_ifu_ic_mem.scala 249:69]
infer mport _T_147 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26]
io.test <= _T_147[0][0] @[el2_ifu_ic_mem.scala 250:15]
skip @[el2_ifu_ic_mem.scala 249:69]
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 245:73]
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 246:83]
node _T_150 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 247:26]
node _T_151 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:52]
node _T_152 = and(_T_150, _T_151) @[el2_ifu_ic_mem.scala 247:30]
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
when _T_153 : @[el2_ifu_ic_mem.scala 247:64]
infer mport _T_154 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15]
_T_154[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
skip @[el2_ifu_ic_mem.scala 247:64]
else : @[el2_ifu_ic_mem.scala 249:69]
node _T_155 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 249:33]
node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
node _T_157 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 249:57]
node _T_158 = and(_T_156, _T_157) @[el2_ifu_ic_mem.scala 249:36]
node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
when _T_159 : @[el2_ifu_ic_mem.scala 249:69]
infer mport _T_160 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26]
io.test <= _T_160[1][0] @[el2_ifu_ic_mem.scala 250:15]
skip @[el2_ifu_ic_mem.scala 249:69]
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 245:73]
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 246:83]
node _T_163 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 247:26]
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:52]
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 247:30]
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
when _T_166 : @[el2_ifu_ic_mem.scala 247:64]
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15]
_T_167[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
skip @[el2_ifu_ic_mem.scala 247:64]
else : @[el2_ifu_ic_mem.scala 249:69]
node _T_168 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 249:33]
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
node _T_170 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 249:57]
node _T_171 = and(_T_169, _T_170) @[el2_ifu_ic_mem.scala 249:36]
node _T_172 = bits(_T_171, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
when _T_172 : @[el2_ifu_ic_mem.scala 249:69]
infer mport _T_173 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26]
io.test <= _T_173[0][1] @[el2_ifu_ic_mem.scala 250:15]
skip @[el2_ifu_ic_mem.scala 249:69]
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 245:73]
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 246:83]
node _T_176 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 247:26]
node _T_177 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:52]
node _T_178 = and(_T_176, _T_177) @[el2_ifu_ic_mem.scala 247:30]
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
when _T_179 : @[el2_ifu_ic_mem.scala 247:64]
infer mport _T_180 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15]
_T_180[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
skip @[el2_ifu_ic_mem.scala 247:64]
else : @[el2_ifu_ic_mem.scala 249:69]
node _T_181 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 249:33]
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
node _T_183 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 249:57]
node _T_184 = and(_T_182, _T_183) @[el2_ifu_ic_mem.scala 249:36]
node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
when _T_185 : @[el2_ifu_ic_mem.scala 249:69]
infer mport _T_186 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26]
io.test <= _T_186[1][1] @[el2_ifu_ic_mem.scala 250:15]
skip @[el2_ifu_ic_mem.scala 249:69]
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