1335 lines
80 KiB
Plaintext
1335 lines
80 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_dbg :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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module el2_dbg :
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input clock : Clock
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input reset : AsyncReset
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output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
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wire dbg_state : UInt<3>
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dbg_state <= UInt<3>("h00")
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wire dbg_state_en : UInt<1>
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dbg_state_en <= UInt<1>("h00")
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wire sb_state : UInt<4>
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sb_state <= UInt<4>("h00")
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wire sb_state_en : UInt<1>
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sb_state_en <= UInt<1>("h00")
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wire dmcontrol_reg : UInt<32>
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dmcontrol_reg <= UInt<32>("h00")
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wire sbaddress0_reg : UInt<32>
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sbaddress0_reg <= UInt<32>("h00")
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wire sbcs_sbbusy_wren : UInt<1>
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sbcs_sbbusy_wren <= UInt<1>("h00")
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wire sbcs_sberror_wren : UInt<1>
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sbcs_sberror_wren <= UInt<1>("h00")
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wire sb_bus_rdata : UInt<64>
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sb_bus_rdata <= UInt<64>("h00")
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wire sbaddress0_reg_wren1 : UInt<1>
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sbaddress0_reg_wren1 <= UInt<1>("h00")
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wire dmstatus_reg : UInt<32>
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dmstatus_reg <= UInt<32>("h00")
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wire dmstatus_havereset : UInt<1>
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dmstatus_havereset <= UInt<1>("h00")
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wire dmstatus_resumeack : UInt<1>
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dmstatus_resumeack <= UInt<1>("h00")
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wire dmstatus_unavail : UInt<1>
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dmstatus_unavail <= UInt<1>("h00")
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wire dmstatus_running : UInt<1>
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dmstatus_running <= UInt<1>("h00")
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wire dmstatus_halted : UInt<1>
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dmstatus_halted <= UInt<1>("h00")
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wire abstractcs_busy_wren : UInt<1>
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abstractcs_busy_wren <= UInt<1>("h00")
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wire abstractcs_busy_din : UInt<1>
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abstractcs_busy_din <= UInt<1>("h00")
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wire sb_bus_cmd_read : UInt<1>
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sb_bus_cmd_read <= UInt<1>("h00")
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wire sb_bus_cmd_write_addr : UInt<1>
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sb_bus_cmd_write_addr <= UInt<1>("h00")
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wire sb_bus_cmd_write_data : UInt<1>
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sb_bus_cmd_write_data <= UInt<1>("h00")
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wire sb_bus_rsp_read : UInt<1>
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sb_bus_rsp_read <= UInt<1>("h00")
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wire sb_bus_rsp_error : UInt<1>
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sb_bus_rsp_error <= UInt<1>("h00")
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wire sb_bus_rsp_write : UInt<1>
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sb_bus_rsp_write <= UInt<1>("h00")
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wire sbcs_sbbusy_din : UInt<1>
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sbcs_sbbusy_din <= UInt<1>("h00")
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wire sbcs_sberror_din : UInt<3>
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sbcs_sberror_din <= UInt<3>("h00")
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wire data1_reg : UInt<32>
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data1_reg <= UInt<32>("h00")
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wire sbcs_reg : UInt<32>
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sbcs_reg <= UInt<32>("h00")
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node _T = neq(dbg_state, UInt<3>("h00")) @[el2_dbg.scala 126:51]
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node _T_1 = or(io.dmi_reg_en, _T) @[el2_dbg.scala 126:38]
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node _T_2 = or(_T_1, dbg_state_en) @[el2_dbg.scala 126:69]
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node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[el2_dbg.scala 126:84]
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node dbg_free_clken = or(_T_3, io.clk_override) @[el2_dbg.scala 126:108]
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node _T_4 = or(io.dmi_reg_en, sb_state_en) @[el2_dbg.scala 127:37]
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node _T_5 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 127:63]
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node _T_6 = or(_T_4, _T_5) @[el2_dbg.scala 127:51]
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node sb_free_clken = or(_T_6, io.clk_override) @[el2_dbg.scala 127:86]
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inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
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rvclkhdr.io.en <= dbg_free_clken @[el2_lib.scala 485:16]
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rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
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inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
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rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
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node _T_7 = asUInt(io.dbg_rst_l) @[el2_dbg.scala 130:42]
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node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:61]
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node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:65]
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node _T_10 = and(_T_7, _T_9) @[el2_dbg.scala 130:45]
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node dbg_dm_rst_l = asAsyncReset(_T_10) @[el2_dbg.scala 130:94]
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node _T_11 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 131:39]
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node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_dbg.scala 131:25]
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node _T_13 = bits(_T_12, 0, 0) @[el2_dbg.scala 131:50]
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io.dbg_core_rst_l <= _T_13 @[el2_dbg.scala 131:21]
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node _T_14 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 132:36]
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node _T_15 = and(_T_14, io.dmi_reg_en) @[el2_dbg.scala 132:49]
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node _T_16 = and(_T_15, io.dmi_reg_wr_en) @[el2_dbg.scala 132:65]
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node _T_17 = eq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 132:96]
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node sbcs_wren = and(_T_16, _T_17) @[el2_dbg.scala 132:84]
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node _T_18 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 133:60]
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node _T_19 = and(sbcs_wren, _T_18) @[el2_dbg.scala 133:42]
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node _T_20 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 133:79]
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node _T_21 = and(_T_20, io.dmi_reg_en) @[el2_dbg.scala 133:102]
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node _T_22 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 134:23]
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node _T_23 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 134:55]
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node _T_24 = or(_T_22, _T_23) @[el2_dbg.scala 134:36]
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node _T_25 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 134:87]
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node _T_26 = or(_T_24, _T_25) @[el2_dbg.scala 134:68]
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node _T_27 = and(_T_21, _T_26) @[el2_dbg.scala 133:118]
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node sbcs_sbbusyerror_wren = or(_T_19, _T_27) @[el2_dbg.scala 133:66]
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node _T_28 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 136:61]
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node _T_29 = and(sbcs_wren, _T_28) @[el2_dbg.scala 136:43]
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node sbcs_sbbusyerror_din = not(_T_29) @[el2_dbg.scala 136:31]
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node _T_30 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 137:74]
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node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_dbg.scala 137:54]
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node _T_32 = asAsyncReset(_T_31) @[el2_dbg.scala 137:90]
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reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
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temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_33 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 141:74]
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node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_dbg.scala 141:54]
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node _T_35 = asAsyncReset(_T_34) @[el2_dbg.scala 141:90]
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reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_35, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusy_wren : @[Reg.scala 28:19]
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temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_36 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 145:74]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dbg.scala 145:54]
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node _T_38 = asAsyncReset(_T_37) @[el2_dbg.scala 145:90]
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node _T_39 = bits(io.dmi_reg_wdata, 20, 20) @[el2_dbg.scala 146:31]
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reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_38, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_20 <= _T_39 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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|
node _T_40 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 149:77]
|
|
node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dbg.scala 149:57]
|
|
node _T_42 = asAsyncReset(_T_41) @[el2_dbg.scala 149:93]
|
|
node _T_43 = bits(io.dmi_reg_wdata, 19, 15) @[el2_dbg.scala 150:31]
|
|
reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_42, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when sbcs_wren : @[Reg.scala 28:19]
|
|
temp_sbcs_19_15 <= _T_43 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_44 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 153:77]
|
|
node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dbg.scala 153:57]
|
|
node _T_46 = asAsyncReset(_T_45) @[el2_dbg.scala 153:93]
|
|
node _T_47 = bits(sbcs_sberror_din, 2, 0) @[el2_dbg.scala 154:31]
|
|
reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_46, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when sbcs_sberror_wren : @[Reg.scala 28:19]
|
|
temp_sbcs_14_12 <= _T_47 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_48 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58]
|
|
node _T_49 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58]
|
|
node _T_50 = cat(_T_49, _T_48) @[Cat.scala 29:58]
|
|
node _T_51 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58]
|
|
node _T_52 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58]
|
|
node _T_53 = cat(_T_52, temp_sbcs_22) @[Cat.scala 29:58]
|
|
node _T_54 = cat(_T_53, _T_51) @[Cat.scala 29:58]
|
|
node _T_55 = cat(_T_54, _T_50) @[Cat.scala 29:58]
|
|
sbcs_reg <= _T_55 @[el2_dbg.scala 156:12]
|
|
node _T_56 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 158:33]
|
|
node _T_57 = eq(_T_56, UInt<1>("h01")) @[el2_dbg.scala 158:42]
|
|
node _T_58 = bits(sbaddress0_reg, 0, 0) @[el2_dbg.scala 158:72]
|
|
node _T_59 = and(_T_57, _T_58) @[el2_dbg.scala 158:56]
|
|
node _T_60 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 159:14]
|
|
node _T_61 = eq(_T_60, UInt<2>("h02")) @[el2_dbg.scala 159:23]
|
|
node _T_62 = bits(sbaddress0_reg, 1, 0) @[el2_dbg.scala 159:53]
|
|
node _T_63 = orr(_T_62) @[el2_dbg.scala 159:60]
|
|
node _T_64 = and(_T_61, _T_63) @[el2_dbg.scala 159:37]
|
|
node _T_65 = or(_T_59, _T_64) @[el2_dbg.scala 158:76]
|
|
node _T_66 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 160:14]
|
|
node _T_67 = eq(_T_66, UInt<2>("h03")) @[el2_dbg.scala 160:23]
|
|
node _T_68 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 160:53]
|
|
node _T_69 = orr(_T_68) @[el2_dbg.scala 160:60]
|
|
node _T_70 = and(_T_67, _T_69) @[el2_dbg.scala 160:37]
|
|
node sbcs_unaligned = or(_T_65, _T_70) @[el2_dbg.scala 159:64]
|
|
node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[el2_dbg.scala 162:35]
|
|
node _T_71 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:42]
|
|
node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dbg.scala 163:51]
|
|
node _T_73 = bits(_T_72, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_74 = mux(_T_73, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_75 = and(_T_74, UInt<1>("h01")) @[el2_dbg.scala 163:64]
|
|
node _T_76 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:95]
|
|
node _T_77 = eq(_T_76, UInt<1>("h01")) @[el2_dbg.scala 163:104]
|
|
node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_80 = and(_T_79, UInt<2>("h02")) @[el2_dbg.scala 163:117]
|
|
node _T_81 = or(_T_75, _T_80) @[el2_dbg.scala 163:76]
|
|
node _T_82 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:22]
|
|
node _T_83 = eq(_T_82, UInt<2>("h02")) @[el2_dbg.scala 164:31]
|
|
node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_85 = mux(_T_84, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_86 = and(_T_85, UInt<3>("h04")) @[el2_dbg.scala 164:44]
|
|
node _T_87 = or(_T_81, _T_86) @[el2_dbg.scala 163:129]
|
|
node _T_88 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:75]
|
|
node _T_89 = eq(_T_88, UInt<2>("h03")) @[el2_dbg.scala 164:84]
|
|
node _T_90 = bits(_T_89, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_91 = mux(_T_90, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_92 = and(_T_91, UInt<4>("h08")) @[el2_dbg.scala 164:97]
|
|
node sbaddress0_incr = or(_T_87, _T_92) @[el2_dbg.scala 164:56]
|
|
node _T_93 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 166:41]
|
|
node _T_94 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 166:79]
|
|
node sbdata0_reg_wren0 = and(_T_93, _T_94) @[el2_dbg.scala 166:60]
|
|
node _T_95 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 167:37]
|
|
node _T_96 = and(_T_95, sb_state_en) @[el2_dbg.scala 167:60]
|
|
node _T_97 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 167:76]
|
|
node sbdata0_reg_wren1 = and(_T_96, _T_97) @[el2_dbg.scala 167:74]
|
|
node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[el2_dbg.scala 168:44]
|
|
node _T_98 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 169:41]
|
|
node _T_99 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 169:79]
|
|
node sbdata1_reg_wren0 = and(_T_98, _T_99) @[el2_dbg.scala 169:60]
|
|
node _T_100 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 170:37]
|
|
node _T_101 = and(_T_100, sb_state_en) @[el2_dbg.scala 170:60]
|
|
node _T_102 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 170:76]
|
|
node sbdata1_reg_wren1 = and(_T_101, _T_102) @[el2_dbg.scala 170:74]
|
|
node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[el2_dbg.scala 171:44]
|
|
node _T_103 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_105 = and(_T_104, io.dmi_reg_wdata) @[el2_dbg.scala 172:49]
|
|
node _T_106 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_107 = mux(_T_106, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_108 = bits(sb_bus_rdata, 31, 0) @[el2_dbg.scala 173:47]
|
|
node _T_109 = and(_T_107, _T_108) @[el2_dbg.scala 173:33]
|
|
node sbdata0_din = or(_T_105, _T_109) @[el2_dbg.scala 172:68]
|
|
node _T_110 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_111 = mux(_T_110, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_112 = and(_T_111, io.dmi_reg_wdata) @[el2_dbg.scala 175:49]
|
|
node _T_113 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_114 = mux(_T_113, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_115 = bits(sb_bus_rdata, 63, 32) @[el2_dbg.scala 176:47]
|
|
node _T_116 = and(_T_114, _T_115) @[el2_dbg.scala 176:33]
|
|
node sbdata1_din = or(_T_112, _T_116) @[el2_dbg.scala 175:68]
|
|
node _T_117 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 178:52]
|
|
node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dbg.scala 178:32]
|
|
node _T_119 = asAsyncReset(_T_118) @[el2_dbg.scala 178:68]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= _T_119
|
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_2.io.en <= sbdata0_reg_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_119, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
sbdata0_reg <= sbdata0_din @[el2_lib.scala 514:16]
|
|
node _T_120 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 182:52]
|
|
node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_dbg.scala 182:32]
|
|
node _T_122 = asAsyncReset(_T_121) @[el2_dbg.scala 182:68]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= _T_122
|
|
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_3.io.en <= sbdata1_reg_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_122, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
sbdata1_reg <= sbdata1_din @[el2_lib.scala 514:16]
|
|
node _T_123 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 186:44]
|
|
node _T_124 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 186:82]
|
|
node sbaddress0_reg_wren0 = and(_T_123, _T_124) @[el2_dbg.scala 186:63]
|
|
node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[el2_dbg.scala 187:50]
|
|
node _T_125 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_127 = and(_T_126, io.dmi_reg_wdata) @[el2_dbg.scala 188:59]
|
|
node _T_128 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_130 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
|
|
node _T_131 = add(sbaddress0_reg, _T_130) @[el2_dbg.scala 189:54]
|
|
node _T_132 = tail(_T_131, 1) @[el2_dbg.scala 189:54]
|
|
node _T_133 = and(_T_129, _T_132) @[el2_dbg.scala 189:36]
|
|
node sbaddress0_reg_din = or(_T_127, _T_133) @[el2_dbg.scala 188:78]
|
|
node _T_134 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 190:52]
|
|
node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dbg.scala 190:32]
|
|
node _T_136 = asAsyncReset(_T_135) @[el2_dbg.scala 190:68]
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
|
|
rvclkhdr_4.clock <= clock
|
|
rvclkhdr_4.reset <= _T_136
|
|
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_4.io.en <= sbaddress0_reg_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_136, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
_T_137 <= sbaddress0_reg_din @[el2_lib.scala 514:16]
|
|
sbaddress0_reg <= _T_137 @[el2_dbg.scala 190:18]
|
|
node _T_138 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 194:43]
|
|
node _T_139 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 194:81]
|
|
node _T_140 = and(_T_138, _T_139) @[el2_dbg.scala 194:62]
|
|
node _T_141 = bits(sbcs_reg, 20, 20) @[el2_dbg.scala 194:104]
|
|
node sbreadonaddr_access = and(_T_140, _T_141) @[el2_dbg.scala 194:94]
|
|
node _T_142 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[el2_dbg.scala 195:45]
|
|
node _T_143 = and(io.dmi_reg_en, _T_142) @[el2_dbg.scala 195:43]
|
|
node _T_144 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 195:82]
|
|
node _T_145 = and(_T_143, _T_144) @[el2_dbg.scala 195:63]
|
|
node _T_146 = bits(sbcs_reg, 15, 15) @[el2_dbg.scala 195:105]
|
|
node sbreadondata_access = and(_T_145, _T_146) @[el2_dbg.scala 195:95]
|
|
node _T_147 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 196:40]
|
|
node _T_148 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 196:78]
|
|
node sbdata0wr_access = and(_T_147, _T_148) @[el2_dbg.scala 196:59]
|
|
node _T_149 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 197:41]
|
|
node _T_150 = and(_T_149, io.dmi_reg_en) @[el2_dbg.scala 197:54]
|
|
node dmcontrol_wren = and(_T_150, io.dmi_reg_wr_en) @[el2_dbg.scala 197:70]
|
|
node _T_151 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 198:70]
|
|
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dbg.scala 198:50]
|
|
node _T_153 = asAsyncReset(_T_152) @[el2_dbg.scala 198:86]
|
|
node _T_154 = bits(io.dmi_reg_wdata, 31, 30) @[el2_dbg.scala 200:27]
|
|
node _T_155 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 200:53]
|
|
node _T_156 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 200:75]
|
|
node _T_157 = cat(_T_154, _T_155) @[Cat.scala 29:58]
|
|
node _T_158 = cat(_T_157, _T_156) @[Cat.scala 29:58]
|
|
reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_153, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp <= _T_158 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_159 = bits(io.dmi_reg_wdata, 0, 0) @[el2_dbg.scala 205:31]
|
|
reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
|
dm_temp_0 <= _T_159 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_160 = bits(dm_temp, 3, 2) @[el2_dbg.scala 208:25]
|
|
node _T_161 = bits(dm_temp, 1, 1) @[el2_dbg.scala 208:45]
|
|
node _T_162 = bits(dm_temp, 0, 0) @[el2_dbg.scala 208:68]
|
|
node _T_163 = cat(UInt<26>("h00"), _T_162) @[Cat.scala 29:58]
|
|
node _T_164 = cat(_T_163, dm_temp_0) @[Cat.scala 29:58]
|
|
node _T_165 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_166 = cat(_T_165, _T_161) @[Cat.scala 29:58]
|
|
node temp = cat(_T_166, _T_164) @[Cat.scala 29:58]
|
|
dmcontrol_reg <= temp @[el2_dbg.scala 209:17]
|
|
node _T_167 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 211:79]
|
|
node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dbg.scala 211:59]
|
|
node _T_169 = asAsyncReset(_T_168) @[el2_dbg.scala 211:95]
|
|
reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_169, UInt<1>("h00"))) @[el2_dbg.scala 212:12]
|
|
dmcontrol_wren_Q <= dmcontrol_wren @[el2_dbg.scala 212:12]
|
|
node _T_170 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_172 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_174 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_175 = mux(_T_174, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_176 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_177 = mux(_T_176, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_178 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_179 = mux(_T_178, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_180 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
|
|
node _T_181 = cat(_T_177, _T_179) @[Cat.scala 29:58]
|
|
node _T_182 = cat(_T_181, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_183 = cat(_T_182, _T_180) @[Cat.scala 29:58]
|
|
node _T_184 = cat(UInt<2>("h00"), _T_175) @[Cat.scala 29:58]
|
|
node _T_185 = cat(UInt<12>("h00"), _T_171) @[Cat.scala 29:58]
|
|
node _T_186 = cat(_T_185, _T_173) @[Cat.scala 29:58]
|
|
node _T_187 = cat(_T_186, _T_184) @[Cat.scala 29:58]
|
|
node _T_188 = cat(_T_187, _T_183) @[Cat.scala 29:58]
|
|
dmstatus_reg <= _T_188 @[el2_dbg.scala 215:16]
|
|
node _T_189 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 217:44]
|
|
node _T_190 = and(_T_189, io.dec_tlu_resume_ack) @[el2_dbg.scala 217:66]
|
|
node _T_191 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 217:127]
|
|
node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dbg.scala 217:113]
|
|
node _T_193 = and(dmstatus_resumeack, _T_192) @[el2_dbg.scala 217:111]
|
|
node dmstatus_resumeack_wren = or(_T_190, _T_193) @[el2_dbg.scala 217:90]
|
|
node _T_194 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 218:43]
|
|
node dmstatus_resumeack_din = and(_T_194, io.dec_tlu_resume_ack) @[el2_dbg.scala 218:65]
|
|
node _T_195 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 219:50]
|
|
node _T_196 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 219:81]
|
|
node _T_197 = and(_T_195, _T_196) @[el2_dbg.scala 219:63]
|
|
node _T_198 = and(_T_197, io.dmi_reg_en) @[el2_dbg.scala 219:85]
|
|
node dmstatus_havereset_wren = and(_T_198, io.dmi_reg_wr_en) @[el2_dbg.scala 219:101]
|
|
node _T_199 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 220:49]
|
|
node _T_200 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 220:80]
|
|
node _T_201 = and(_T_199, _T_200) @[el2_dbg.scala 220:62]
|
|
node _T_202 = and(_T_201, io.dmi_reg_en) @[el2_dbg.scala 220:85]
|
|
node dmstatus_havereset_rst = and(_T_202, io.dmi_reg_wr_en) @[el2_dbg.scala 220:101]
|
|
node temp_rst = asUInt(reset) @[el2_dbg.scala 221:30]
|
|
node _T_203 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 222:37]
|
|
node _T_204 = eq(temp_rst, UInt<1>("h00")) @[el2_dbg.scala 222:43]
|
|
node _T_205 = or(_T_203, _T_204) @[el2_dbg.scala 222:41]
|
|
node _T_206 = bits(_T_205, 0, 0) @[el2_dbg.scala 222:62]
|
|
dmstatus_unavail <= _T_206 @[el2_dbg.scala 222:20]
|
|
node _T_207 = or(dmstatus_unavail, dmstatus_halted) @[el2_dbg.scala 223:42]
|
|
node _T_208 = not(_T_207) @[el2_dbg.scala 223:23]
|
|
dmstatus_running <= _T_208 @[el2_dbg.scala 223:20]
|
|
node _T_209 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 224:78]
|
|
node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dbg.scala 224:58]
|
|
node _T_211 = asAsyncReset(_T_210) @[el2_dbg.scala 224:94]
|
|
reg _T_212 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_211, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmstatus_resumeack_wren : @[Reg.scala 28:19]
|
|
_T_212 <= dmstatus_resumeack_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dmstatus_resumeack <= _T_212 @[el2_dbg.scala 224:22]
|
|
node _T_213 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 228:75]
|
|
node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dbg.scala 228:55]
|
|
node _T_215 = asAsyncReset(_T_214) @[el2_dbg.scala 228:91]
|
|
node _T_216 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[el2_dbg.scala 229:37]
|
|
node _T_217 = and(io.dec_tlu_dbg_halted, _T_216) @[el2_dbg.scala 229:35]
|
|
reg _T_218 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_215, UInt<1>("h00"))) @[el2_dbg.scala 229:12]
|
|
_T_218 <= _T_217 @[el2_dbg.scala 229:12]
|
|
dmstatus_halted <= _T_218 @[el2_dbg.scala 228:19]
|
|
node _T_219 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 232:78]
|
|
node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dbg.scala 232:58]
|
|
node _T_221 = asAsyncReset(_T_220) @[el2_dbg.scala 232:94]
|
|
node _T_222 = not(dmstatus_havereset_rst) @[el2_dbg.scala 233:15]
|
|
reg _T_223 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_221, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dmstatus_havereset_wren : @[Reg.scala 28:19]
|
|
_T_223 <= _T_222 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dmstatus_havereset <= _T_223 @[el2_dbg.scala 232:22]
|
|
node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
|
|
wire abstractcs_reg : UInt<32>
|
|
abstractcs_reg <= UInt<32>("h02")
|
|
node _T_224 = bits(abstractcs_reg, 12, 12) @[el2_dbg.scala 239:45]
|
|
node _T_225 = and(_T_224, io.dmi_reg_en) @[el2_dbg.scala 239:50]
|
|
node _T_226 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 239:106]
|
|
node _T_227 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 239:138]
|
|
node _T_228 = or(_T_226, _T_227) @[el2_dbg.scala 239:119]
|
|
node _T_229 = and(io.dmi_reg_wr_en, _T_228) @[el2_dbg.scala 239:86]
|
|
node _T_230 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 239:171]
|
|
node _T_231 = or(_T_229, _T_230) @[el2_dbg.scala 239:152]
|
|
node abstractcs_error_sel0 = and(_T_225, _T_231) @[el2_dbg.scala 239:66]
|
|
node _T_232 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 240:45]
|
|
node _T_233 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 240:83]
|
|
node _T_234 = and(_T_232, _T_233) @[el2_dbg.scala 240:64]
|
|
node _T_235 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:117]
|
|
node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_dbg.scala 240:126]
|
|
node _T_237 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:154]
|
|
node _T_238 = eq(_T_237, UInt<2>("h02")) @[el2_dbg.scala 240:163]
|
|
node _T_239 = or(_T_236, _T_238) @[el2_dbg.scala 240:135]
|
|
node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dbg.scala 240:98]
|
|
node abstractcs_error_sel1 = and(_T_234, _T_240) @[el2_dbg.scala 240:96]
|
|
node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[el2_dbg.scala 241:52]
|
|
node _T_241 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 242:45]
|
|
node _T_242 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 242:83]
|
|
node _T_243 = and(_T_241, _T_242) @[el2_dbg.scala 242:64]
|
|
node _T_244 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 242:111]
|
|
node _T_245 = eq(_T_244, UInt<1>("h00")) @[el2_dbg.scala 242:98]
|
|
node abstractcs_error_sel3 = and(_T_243, _T_245) @[el2_dbg.scala 242:96]
|
|
node _T_246 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 243:48]
|
|
node _T_247 = and(_T_246, io.dmi_reg_en) @[el2_dbg.scala 243:61]
|
|
node _T_248 = and(_T_247, io.dmi_reg_wr_en) @[el2_dbg.scala 243:77]
|
|
node _T_249 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 244:23]
|
|
node _T_250 = neq(_T_249, UInt<2>("h02")) @[el2_dbg.scala 244:32]
|
|
node _T_251 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 244:66]
|
|
node _T_252 = eq(_T_251, UInt<2>("h02")) @[el2_dbg.scala 244:75]
|
|
node _T_253 = bits(data1_reg, 1, 0) @[el2_dbg.scala 244:99]
|
|
node _T_254 = orr(_T_253) @[el2_dbg.scala 244:106]
|
|
node _T_255 = and(_T_252, _T_254) @[el2_dbg.scala 244:87]
|
|
node _T_256 = or(_T_250, _T_255) @[el2_dbg.scala 244:46]
|
|
node abstractcs_error_sel4 = and(_T_248, _T_256) @[el2_dbg.scala 243:96]
|
|
node _T_257 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 246:48]
|
|
node _T_258 = and(_T_257, io.dmi_reg_en) @[el2_dbg.scala 246:61]
|
|
node abstractcs_error_sel5 = and(_T_258, io.dmi_reg_wr_en) @[el2_dbg.scala 246:77]
|
|
node _T_259 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[el2_dbg.scala 247:54]
|
|
node _T_260 = or(_T_259, abstractcs_error_sel2) @[el2_dbg.scala 247:78]
|
|
node _T_261 = or(_T_260, abstractcs_error_sel3) @[el2_dbg.scala 247:102]
|
|
node _T_262 = or(_T_261, abstractcs_error_sel4) @[el2_dbg.scala 247:126]
|
|
node abstractcs_error_selor = or(_T_262, abstractcs_error_sel5) @[el2_dbg.scala 247:150]
|
|
node _T_263 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_264 = mux(_T_263, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_265 = and(_T_264, UInt<1>("h01")) @[el2_dbg.scala 248:62]
|
|
node _T_266 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_267 = mux(_T_266, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_268 = and(_T_267, UInt<2>("h02")) @[el2_dbg.scala 249:37]
|
|
node _T_269 = or(_T_265, _T_268) @[el2_dbg.scala 248:74]
|
|
node _T_270 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_271 = mux(_T_270, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_272 = and(_T_271, UInt<2>("h03")) @[el2_dbg.scala 250:37]
|
|
node _T_273 = or(_T_269, _T_272) @[el2_dbg.scala 249:49]
|
|
node _T_274 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_275 = mux(_T_274, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_276 = and(_T_275, UInt<3>("h04")) @[el2_dbg.scala 251:37]
|
|
node _T_277 = or(_T_273, _T_276) @[el2_dbg.scala 250:49]
|
|
node _T_278 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_279 = mux(_T_278, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_280 = and(_T_279, UInt<3>("h07")) @[el2_dbg.scala 252:37]
|
|
node _T_281 = or(_T_277, _T_280) @[el2_dbg.scala 251:49]
|
|
node _T_282 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_283 = mux(_T_282, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_284 = bits(io.dmi_reg_wdata, 10, 8) @[el2_dbg.scala 253:57]
|
|
node _T_285 = not(_T_284) @[el2_dbg.scala 253:40]
|
|
node _T_286 = and(_T_283, _T_285) @[el2_dbg.scala 253:37]
|
|
node _T_287 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 253:91]
|
|
node _T_288 = and(_T_286, _T_287) @[el2_dbg.scala 253:75]
|
|
node _T_289 = or(_T_281, _T_288) @[el2_dbg.scala 252:49]
|
|
node _T_290 = not(abstractcs_error_selor) @[el2_dbg.scala 254:15]
|
|
node _T_291 = bits(_T_290, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_292 = mux(_T_291, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_293 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 254:66]
|
|
node _T_294 = and(_T_292, _T_293) @[el2_dbg.scala 254:50]
|
|
node abstractcs_error_din = or(_T_289, _T_294) @[el2_dbg.scala 253:100]
|
|
node _T_295 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 256:74]
|
|
node _T_296 = eq(_T_295, UInt<1>("h00")) @[el2_dbg.scala 256:54]
|
|
node _T_297 = asAsyncReset(_T_296) @[el2_dbg.scala 256:90]
|
|
reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_297, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when abstractcs_busy_wren : @[Reg.scala 28:19]
|
|
abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
node _T_298 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 260:76]
|
|
node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_dbg.scala 260:56]
|
|
node _T_300 = asAsyncReset(_T_299) @[el2_dbg.scala 260:92]
|
|
node _T_301 = bits(abstractcs_error_din, 2, 0) @[el2_dbg.scala 261:33]
|
|
reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_300, UInt<1>("h00"))) @[el2_dbg.scala 261:12]
|
|
abs_temp_10_8 <= _T_301 @[el2_dbg.scala 261:12]
|
|
node _T_302 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
|
|
node _T_303 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
|
|
node _T_304 = cat(_T_303, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_305 = cat(_T_304, _T_302) @[Cat.scala 29:58]
|
|
abstractcs_reg <= _T_305 @[el2_dbg.scala 264:18]
|
|
node _T_306 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 266:39]
|
|
node _T_307 = and(_T_306, io.dmi_reg_en) @[el2_dbg.scala 266:52]
|
|
node _T_308 = and(_T_307, io.dmi_reg_wr_en) @[el2_dbg.scala 266:68]
|
|
node _T_309 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 266:100]
|
|
node command_wren = and(_T_308, _T_309) @[el2_dbg.scala 266:87]
|
|
node _T_310 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 267:41]
|
|
node _T_311 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 267:77]
|
|
node _T_312 = bits(io.dmi_reg_wdata, 16, 0) @[el2_dbg.scala 267:113]
|
|
node _T_313 = cat(UInt<3>("h00"), _T_312) @[Cat.scala 29:58]
|
|
node _T_314 = cat(_T_310, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_315 = cat(_T_314, _T_311) @[Cat.scala 29:58]
|
|
node command_din = cat(_T_315, _T_313) @[Cat.scala 29:58]
|
|
node _T_316 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 268:52]
|
|
node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dbg.scala 268:32]
|
|
node _T_318 = asAsyncReset(_T_317) @[el2_dbg.scala 268:68]
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
|
|
rvclkhdr_5.clock <= clock
|
|
rvclkhdr_5.reset <= _T_318
|
|
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_5.io.en <= command_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
command_reg <= command_din @[el2_lib.scala 514:16]
|
|
node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 272:39]
|
|
node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 272:77]
|
|
node _T_321 = and(_T_319, _T_320) @[el2_dbg.scala 272:58]
|
|
node _T_322 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 272:102]
|
|
node data0_reg_wren0 = and(_T_321, _T_322) @[el2_dbg.scala 272:89]
|
|
node _T_323 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 273:59]
|
|
node _T_324 = and(io.core_dbg_cmd_done, _T_323) @[el2_dbg.scala 273:46]
|
|
node _T_325 = bits(command_reg, 16, 16) @[el2_dbg.scala 273:95]
|
|
node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dbg.scala 273:83]
|
|
node data0_reg_wren1 = and(_T_324, _T_326) @[el2_dbg.scala 273:81]
|
|
node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[el2_dbg.scala 275:40]
|
|
node _T_327 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_328 = mux(_T_327, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_329 = and(_T_328, io.dmi_reg_wdata) @[el2_dbg.scala 276:45]
|
|
node _T_330 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_331 = mux(_T_330, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_332 = and(_T_331, io.core_dbg_rddata) @[el2_dbg.scala 276:92]
|
|
node data0_din = or(_T_329, _T_332) @[el2_dbg.scala 276:64]
|
|
node _T_333 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 277:50]
|
|
node _T_334 = eq(_T_333, UInt<1>("h00")) @[el2_dbg.scala 277:30]
|
|
node _T_335 = asAsyncReset(_T_334) @[el2_dbg.scala 277:66]
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23]
|
|
rvclkhdr_6.clock <= clock
|
|
rvclkhdr_6.reset <= _T_335
|
|
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_6.io.en <= data0_reg_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_335, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
data0_reg <= data0_din @[el2_lib.scala 514:16]
|
|
node _T_336 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 281:39]
|
|
node _T_337 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 281:77]
|
|
node _T_338 = and(_T_336, _T_337) @[el2_dbg.scala 281:58]
|
|
node _T_339 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 281:102]
|
|
node data1_reg_wren = and(_T_338, _T_339) @[el2_dbg.scala 281:89]
|
|
node _T_340 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_341 = mux(_T_340, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node data1_din = and(_T_341, io.dmi_reg_wdata) @[el2_dbg.scala 282:44]
|
|
node _T_342 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 283:47]
|
|
node _T_343 = eq(_T_342, UInt<1>("h00")) @[el2_dbg.scala 283:27]
|
|
node _T_344 = asAsyncReset(_T_343) @[el2_dbg.scala 283:63]
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23]
|
|
rvclkhdr_7.clock <= clock
|
|
rvclkhdr_7.reset <= _T_344
|
|
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
|
|
rvclkhdr_7.io.en <= data1_reg_wren @[el2_lib.scala 511:17]
|
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
|
reg _T_345 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_344, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
|
_T_345 <= data1_din @[el2_lib.scala 514:16]
|
|
data1_reg <= _T_345 @[el2_dbg.scala 283:13]
|
|
wire dbg_nxtstate : UInt<3>
|
|
dbg_nxtstate <= UInt<3>("h00")
|
|
dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 288:16]
|
|
dbg_state_en <= UInt<1>("h00") @[el2_dbg.scala 289:16]
|
|
abstractcs_busy_wren <= UInt<1>("h00") @[el2_dbg.scala 290:24]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 291:23]
|
|
io.dbg_halt_req <= UInt<1>("h00") @[el2_dbg.scala 292:19]
|
|
io.dbg_resume_req <= UInt<1>("h00") @[el2_dbg.scala 293:21]
|
|
node _T_346 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_346 : @[Conditional.scala 40:58]
|
|
node _T_347 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 296:39]
|
|
node _T_348 = or(_T_347, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 296:43]
|
|
node _T_349 = mux(_T_348, UInt<3>("h02"), UInt<3>("h01")) @[el2_dbg.scala 296:26]
|
|
dbg_nxtstate <= _T_349 @[el2_dbg.scala 296:20]
|
|
node _T_350 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 297:38]
|
|
node _T_351 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[el2_dbg.scala 297:45]
|
|
node _T_352 = and(_T_350, _T_351) @[el2_dbg.scala 297:43]
|
|
node _T_353 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 297:83]
|
|
node _T_354 = or(_T_352, _T_353) @[el2_dbg.scala 297:69]
|
|
node _T_355 = or(_T_354, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 297:87]
|
|
node _T_356 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 297:133]
|
|
node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dbg.scala 297:119]
|
|
node _T_358 = and(_T_355, _T_357) @[el2_dbg.scala 297:117]
|
|
dbg_state_en <= _T_358 @[el2_dbg.scala 297:20]
|
|
node _T_359 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 298:40]
|
|
node _T_360 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 298:61]
|
|
node _T_361 = eq(_T_360, UInt<1>("h00")) @[el2_dbg.scala 298:47]
|
|
node _T_362 = and(_T_359, _T_361) @[el2_dbg.scala 298:45]
|
|
node _T_363 = bits(_T_362, 0, 0) @[el2_dbg.scala 298:72]
|
|
io.dbg_halt_req <= _T_363 @[el2_dbg.scala 298:23]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_364 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_364 : @[Conditional.scala 39:67]
|
|
node _T_365 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 301:40]
|
|
node _T_366 = mux(_T_365, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 301:26]
|
|
dbg_nxtstate <= _T_366 @[el2_dbg.scala 301:20]
|
|
node _T_367 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 302:35]
|
|
node _T_368 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 302:54]
|
|
node _T_369 = or(_T_367, _T_368) @[el2_dbg.scala 302:39]
|
|
dbg_state_en <= _T_369 @[el2_dbg.scala 302:20]
|
|
node _T_370 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 303:59]
|
|
node _T_371 = and(dmcontrol_wren_Q, _T_370) @[el2_dbg.scala 303:44]
|
|
node _T_372 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 303:81]
|
|
node _T_373 = not(_T_372) @[el2_dbg.scala 303:67]
|
|
node _T_374 = and(_T_371, _T_373) @[el2_dbg.scala 303:64]
|
|
node _T_375 = bits(_T_374, 0, 0) @[el2_dbg.scala 303:102]
|
|
io.dbg_halt_req <= _T_375 @[el2_dbg.scala 303:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_376 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_376 : @[Conditional.scala 39:67]
|
|
node _T_377 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 306:39]
|
|
node _T_378 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 306:59]
|
|
node _T_379 = eq(_T_378, UInt<1>("h00")) @[el2_dbg.scala 306:45]
|
|
node _T_380 = and(_T_377, _T_379) @[el2_dbg.scala 306:43]
|
|
node _T_381 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 307:26]
|
|
node _T_382 = bits(dmcontrol_reg, 3, 3) @[el2_dbg.scala 307:47]
|
|
node _T_383 = eq(_T_382, UInt<1>("h00")) @[el2_dbg.scala 307:33]
|
|
node _T_384 = and(_T_381, _T_383) @[el2_dbg.scala 307:31]
|
|
node _T_385 = mux(_T_384, UInt<3>("h06"), UInt<3>("h03")) @[el2_dbg.scala 307:12]
|
|
node _T_386 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 308:26]
|
|
node _T_387 = mux(_T_386, UInt<3>("h01"), UInt<3>("h00")) @[el2_dbg.scala 308:12]
|
|
node _T_388 = mux(_T_380, _T_385, _T_387) @[el2_dbg.scala 306:26]
|
|
dbg_nxtstate <= _T_388 @[el2_dbg.scala 306:20]
|
|
node _T_389 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 309:35]
|
|
node _T_390 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 309:54]
|
|
node _T_391 = and(_T_389, _T_390) @[el2_dbg.scala 309:39]
|
|
node _T_392 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 309:75]
|
|
node _T_393 = eq(_T_392, UInt<1>("h00")) @[el2_dbg.scala 309:61]
|
|
node _T_394 = and(_T_391, _T_393) @[el2_dbg.scala 309:59]
|
|
node _T_395 = and(_T_394, dmcontrol_wren_Q) @[el2_dbg.scala 309:80]
|
|
node _T_396 = or(_T_395, command_wren) @[el2_dbg.scala 309:99]
|
|
node _T_397 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 310:22]
|
|
node _T_398 = or(_T_396, _T_397) @[el2_dbg.scala 309:114]
|
|
node _T_399 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 310:42]
|
|
node _T_400 = or(_T_399, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 310:46]
|
|
node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dbg.scala 310:28]
|
|
node _T_402 = or(_T_398, _T_401) @[el2_dbg.scala 310:26]
|
|
dbg_state_en <= _T_402 @[el2_dbg.scala 309:20]
|
|
node _T_403 = eq(dbg_nxtstate, UInt<3>("h03")) @[el2_dbg.scala 311:60]
|
|
node _T_404 = and(dbg_state_en, _T_403) @[el2_dbg.scala 311:44]
|
|
abstractcs_busy_wren <= _T_404 @[el2_dbg.scala 311:28]
|
|
abstractcs_busy_din <= UInt<1>("h01") @[el2_dbg.scala 312:27]
|
|
node _T_405 = eq(dbg_nxtstate, UInt<3>("h06")) @[el2_dbg.scala 313:58]
|
|
node _T_406 = and(dbg_state_en, _T_405) @[el2_dbg.scala 313:42]
|
|
node _T_407 = bits(_T_406, 0, 0) @[el2_dbg.scala 313:87]
|
|
io.dbg_resume_req <= _T_407 @[el2_dbg.scala 313:25]
|
|
node _T_408 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 314:59]
|
|
node _T_409 = and(dmcontrol_wren_Q, _T_408) @[el2_dbg.scala 314:44]
|
|
node _T_410 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 314:81]
|
|
node _T_411 = not(_T_410) @[el2_dbg.scala 314:67]
|
|
node _T_412 = and(_T_409, _T_411) @[el2_dbg.scala 314:64]
|
|
node _T_413 = bits(_T_412, 0, 0) @[el2_dbg.scala 314:102]
|
|
io.dbg_halt_req <= _T_413 @[el2_dbg.scala 314:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_414 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_414 : @[Conditional.scala 39:67]
|
|
node _T_415 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 317:40]
|
|
node _T_416 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 317:77]
|
|
node _T_417 = orr(_T_416) @[el2_dbg.scala 317:85]
|
|
node _T_418 = mux(_T_417, UInt<3>("h05"), UInt<3>("h04")) @[el2_dbg.scala 317:62]
|
|
node _T_419 = mux(_T_415, UInt<3>("h00"), _T_418) @[el2_dbg.scala 317:26]
|
|
dbg_nxtstate <= _T_419 @[el2_dbg.scala 317:20]
|
|
node _T_420 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 318:56]
|
|
node _T_421 = orr(_T_420) @[el2_dbg.scala 318:64]
|
|
node _T_422 = or(io.dbg_cmd_valid, _T_421) @[el2_dbg.scala 318:40]
|
|
node _T_423 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 318:83]
|
|
node _T_424 = or(_T_422, _T_423) @[el2_dbg.scala 318:68]
|
|
dbg_state_en <= _T_424 @[el2_dbg.scala 318:20]
|
|
node _T_425 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 319:59]
|
|
node _T_426 = and(dmcontrol_wren_Q, _T_425) @[el2_dbg.scala 319:44]
|
|
node _T_427 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 319:81]
|
|
node _T_428 = not(_T_427) @[el2_dbg.scala 319:67]
|
|
node _T_429 = and(_T_426, _T_428) @[el2_dbg.scala 319:64]
|
|
node _T_430 = bits(_T_429, 0, 0) @[el2_dbg.scala 319:102]
|
|
io.dbg_halt_req <= _T_430 @[el2_dbg.scala 319:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_431 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_431 : @[Conditional.scala 39:67]
|
|
node _T_432 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 322:40]
|
|
node _T_433 = mux(_T_432, UInt<3>("h00"), UInt<3>("h05")) @[el2_dbg.scala 322:26]
|
|
dbg_nxtstate <= _T_433 @[el2_dbg.scala 322:20]
|
|
node _T_434 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 323:59]
|
|
node _T_435 = or(io.core_dbg_cmd_done, _T_434) @[el2_dbg.scala 323:44]
|
|
dbg_state_en <= _T_435 @[el2_dbg.scala 323:20]
|
|
node _T_436 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 324:59]
|
|
node _T_437 = and(dmcontrol_wren_Q, _T_436) @[el2_dbg.scala 324:44]
|
|
node _T_438 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 324:81]
|
|
node _T_439 = not(_T_438) @[el2_dbg.scala 324:67]
|
|
node _T_440 = and(_T_437, _T_439) @[el2_dbg.scala 324:64]
|
|
node _T_441 = bits(_T_440, 0, 0) @[el2_dbg.scala 324:102]
|
|
io.dbg_halt_req <= _T_441 @[el2_dbg.scala 324:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_442 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_442 : @[Conditional.scala 39:67]
|
|
node _T_443 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 327:40]
|
|
node _T_444 = mux(_T_443, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 327:26]
|
|
dbg_nxtstate <= _T_444 @[el2_dbg.scala 327:20]
|
|
dbg_state_en <= UInt<1>("h01") @[el2_dbg.scala 328:20]
|
|
abstractcs_busy_wren <= dbg_state_en @[el2_dbg.scala 329:28]
|
|
abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 330:27]
|
|
node _T_445 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 331:59]
|
|
node _T_446 = and(dmcontrol_wren_Q, _T_445) @[el2_dbg.scala 331:44]
|
|
node _T_447 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 331:81]
|
|
node _T_448 = not(_T_447) @[el2_dbg.scala 331:67]
|
|
node _T_449 = and(_T_446, _T_448) @[el2_dbg.scala 331:64]
|
|
node _T_450 = bits(_T_449, 0, 0) @[el2_dbg.scala 331:102]
|
|
io.dbg_halt_req <= _T_450 @[el2_dbg.scala 331:23]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_451 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
|
|
when _T_451 : @[Conditional.scala 39:67]
|
|
dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 334:20]
|
|
node _T_452 = bits(dmstatus_reg, 17, 17) @[el2_dbg.scala 335:35]
|
|
node _T_453 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 335:55]
|
|
node _T_454 = or(_T_452, _T_453) @[el2_dbg.scala 335:40]
|
|
dbg_state_en <= _T_454 @[el2_dbg.scala 335:20]
|
|
node _T_455 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 336:59]
|
|
node _T_456 = and(dmcontrol_wren_Q, _T_455) @[el2_dbg.scala 336:44]
|
|
node _T_457 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 336:81]
|
|
node _T_458 = not(_T_457) @[el2_dbg.scala 336:67]
|
|
node _T_459 = and(_T_456, _T_458) @[el2_dbg.scala 336:64]
|
|
node _T_460 = bits(_T_459, 0, 0) @[el2_dbg.scala 336:102]
|
|
io.dbg_halt_req <= _T_460 @[el2_dbg.scala 336:23]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_461 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 339:52]
|
|
node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_463 = mux(_T_462, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_464 = and(_T_463, data0_reg) @[el2_dbg.scala 339:71]
|
|
node _T_465 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 339:110]
|
|
node _T_466 = bits(_T_465, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_467 = mux(_T_466, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_468 = and(_T_467, data1_reg) @[el2_dbg.scala 339:122]
|
|
node _T_469 = or(_T_464, _T_468) @[el2_dbg.scala 339:83]
|
|
node _T_470 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 340:30]
|
|
node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_472 = mux(_T_471, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_473 = and(_T_472, dmcontrol_reg) @[el2_dbg.scala 340:43]
|
|
node _T_474 = or(_T_469, _T_473) @[el2_dbg.scala 339:134]
|
|
node _T_475 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[el2_dbg.scala 340:86]
|
|
node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_477 = mux(_T_476, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_478 = and(_T_477, dmstatus_reg) @[el2_dbg.scala 340:99]
|
|
node _T_479 = or(_T_474, _T_478) @[el2_dbg.scala 340:59]
|
|
node _T_480 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 341:30]
|
|
node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_482 = mux(_T_481, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_483 = and(_T_482, abstractcs_reg) @[el2_dbg.scala 341:43]
|
|
node _T_484 = or(_T_479, _T_483) @[el2_dbg.scala 340:114]
|
|
node _T_485 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 341:87]
|
|
node _T_486 = bits(_T_485, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_487 = mux(_T_486, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_488 = and(_T_487, command_reg) @[el2_dbg.scala 341:100]
|
|
node _T_489 = or(_T_484, _T_488) @[el2_dbg.scala 341:60]
|
|
node _T_490 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[el2_dbg.scala 342:30]
|
|
node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_492 = mux(_T_491, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_493 = and(_T_492, haltsum0_reg) @[el2_dbg.scala 342:43]
|
|
node _T_494 = or(_T_489, _T_493) @[el2_dbg.scala 341:114]
|
|
node _T_495 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 342:85]
|
|
node _T_496 = bits(_T_495, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_497 = mux(_T_496, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_498 = and(_T_497, sbcs_reg) @[el2_dbg.scala 342:98]
|
|
node _T_499 = or(_T_494, _T_498) @[el2_dbg.scala 342:58]
|
|
node _T_500 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 343:30]
|
|
node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_502 = mux(_T_501, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_503 = and(_T_502, sbaddress0_reg) @[el2_dbg.scala 343:43]
|
|
node _T_504 = or(_T_499, _T_503) @[el2_dbg.scala 342:109]
|
|
node _T_505 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 343:87]
|
|
node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_508 = and(_T_507, sbdata0_reg) @[el2_dbg.scala 343:100]
|
|
node _T_509 = or(_T_504, _T_508) @[el2_dbg.scala 343:60]
|
|
node _T_510 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 344:30]
|
|
node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_512 = mux(_T_511, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_513 = and(_T_512, sbdata1_reg) @[el2_dbg.scala 344:43]
|
|
node dmi_reg_rdata_din = or(_T_509, _T_513) @[el2_dbg.scala 343:114]
|
|
node _T_514 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 346:69]
|
|
node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_dbg.scala 346:49]
|
|
node _T_516 = and(_T_515, temp_rst) @[el2_dbg.scala 346:72]
|
|
node _T_517 = asAsyncReset(_T_516) @[el2_dbg.scala 346:96]
|
|
reg _T_518 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_517, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when dbg_state_en : @[Reg.scala 28:19]
|
|
_T_518 <= dbg_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
dbg_state <= _T_518 @[el2_dbg.scala 346:13]
|
|
node _T_519 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 351:76]
|
|
node _T_520 = eq(_T_519, UInt<1>("h00")) @[el2_dbg.scala 351:56]
|
|
node _T_521 = asAsyncReset(_T_520) @[el2_dbg.scala 351:92]
|
|
reg _T_522 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_521, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when io.dmi_reg_en : @[Reg.scala 28:19]
|
|
_T_522 <= dmi_reg_rdata_din @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.dmi_reg_rdata <= _T_522 @[el2_dbg.scala 351:20]
|
|
node _T_523 = bits(command_reg, 31, 24) @[el2_dbg.scala 355:38]
|
|
node _T_524 = eq(_T_523, UInt<2>("h02")) @[el2_dbg.scala 355:47]
|
|
node _T_525 = bits(data1_reg, 31, 2) @[el2_dbg.scala 355:73]
|
|
node _T_526 = cat(_T_525, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_527 = bits(command_reg, 11, 0) @[el2_dbg.scala 355:118]
|
|
node _T_528 = cat(UInt<20>("h00"), _T_527) @[Cat.scala 29:58]
|
|
node _T_529 = mux(_T_524, _T_526, _T_528) @[el2_dbg.scala 355:25]
|
|
io.dbg_cmd_addr <= _T_529 @[el2_dbg.scala 355:19]
|
|
node _T_530 = bits(data0_reg, 31, 0) @[el2_dbg.scala 356:33]
|
|
io.dbg_cmd_wrdata <= _T_530 @[el2_dbg.scala 356:21]
|
|
node _T_531 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 357:35]
|
|
node _T_532 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 357:76]
|
|
node _T_533 = orr(_T_532) @[el2_dbg.scala 357:84]
|
|
node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_dbg.scala 357:60]
|
|
node _T_535 = and(_T_531, _T_534) @[el2_dbg.scala 357:58]
|
|
node _T_536 = and(_T_535, io.dma_dbg_ready) @[el2_dbg.scala 357:89]
|
|
node _T_537 = bits(_T_536, 0, 0) @[el2_dbg.scala 357:115]
|
|
io.dbg_cmd_valid <= _T_537 @[el2_dbg.scala 357:20]
|
|
node _T_538 = bits(command_reg, 16, 16) @[el2_dbg.scala 358:34]
|
|
node _T_539 = bits(_T_538, 0, 0) @[el2_dbg.scala 358:45]
|
|
io.dbg_cmd_write <= _T_539 @[el2_dbg.scala 358:20]
|
|
node _T_540 = bits(command_reg, 31, 24) @[el2_dbg.scala 359:38]
|
|
node _T_541 = eq(_T_540, UInt<2>("h02")) @[el2_dbg.scala 359:47]
|
|
node _T_542 = bits(command_reg, 15, 12) @[el2_dbg.scala 359:93]
|
|
node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dbg.scala 359:102]
|
|
node _T_544 = cat(UInt<1>("h00"), _T_543) @[Cat.scala 29:58]
|
|
node _T_545 = mux(_T_541, UInt<2>("h02"), _T_544) @[el2_dbg.scala 359:25]
|
|
io.dbg_cmd_type <= _T_545 @[el2_dbg.scala 359:19]
|
|
node _T_546 = bits(command_reg, 21, 20) @[el2_dbg.scala 360:33]
|
|
io.dbg_cmd_size <= _T_546 @[el2_dbg.scala 360:19]
|
|
node _T_547 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 361:36]
|
|
node _T_548 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 361:77]
|
|
node _T_549 = orr(_T_548) @[el2_dbg.scala 361:85]
|
|
node _T_550 = eq(_T_549, UInt<1>("h00")) @[el2_dbg.scala 361:61]
|
|
node _T_551 = and(_T_547, _T_550) @[el2_dbg.scala 361:59]
|
|
node _T_552 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 361:103]
|
|
node _T_553 = or(_T_551, _T_552) @[el2_dbg.scala 361:90]
|
|
node _T_554 = bits(_T_553, 0, 0) @[el2_dbg.scala 361:132]
|
|
io.dbg_dma_bubble <= _T_554 @[el2_dbg.scala 361:21]
|
|
wire sb_nxtstate : UInt<4>
|
|
sb_nxtstate <= UInt<4>("h00")
|
|
sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 364:15]
|
|
sbcs_sbbusy_wren <= UInt<1>("h00") @[el2_dbg.scala 366:20]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 367:19]
|
|
sbcs_sberror_wren <= UInt<1>("h00") @[el2_dbg.scala 368:21]
|
|
sbcs_sberror_din <= UInt<3>("h00") @[el2_dbg.scala 369:20]
|
|
sbaddress0_reg_wren1 <= UInt<1>("h00") @[el2_dbg.scala 370:24]
|
|
node _T_555 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_555 : @[Conditional.scala 40:58]
|
|
node _T_556 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[el2_dbg.scala 373:25]
|
|
sb_nxtstate <= _T_556 @[el2_dbg.scala 373:19]
|
|
node _T_557 = or(sbdata0wr_access, sbreadondata_access) @[el2_dbg.scala 374:39]
|
|
node _T_558 = or(_T_557, sbreadonaddr_access) @[el2_dbg.scala 374:61]
|
|
sb_state_en <= _T_558 @[el2_dbg.scala 374:19]
|
|
sbcs_sbbusy_wren <= sb_state_en @[el2_dbg.scala 375:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h01") @[el2_dbg.scala 376:23]
|
|
node _T_559 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 377:56]
|
|
node _T_560 = orr(_T_559) @[el2_dbg.scala 377:65]
|
|
node _T_561 = and(sbcs_wren, _T_560) @[el2_dbg.scala 377:38]
|
|
sbcs_sberror_wren <= _T_561 @[el2_dbg.scala 377:25]
|
|
node _T_562 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 378:44]
|
|
node _T_563 = eq(_T_562, UInt<1>("h00")) @[el2_dbg.scala 378:27]
|
|
node _T_564 = bits(sbcs_reg, 14, 12) @[el2_dbg.scala 378:63]
|
|
node _T_565 = and(_T_563, _T_564) @[el2_dbg.scala 378:53]
|
|
sbcs_sberror_din <= _T_565 @[el2_dbg.scala 378:24]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_566 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_566 : @[Conditional.scala 39:67]
|
|
node _T_567 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 381:41]
|
|
node _T_568 = mux(_T_567, UInt<4>("h09"), UInt<4>("h03")) @[el2_dbg.scala 381:25]
|
|
sb_nxtstate <= _T_568 @[el2_dbg.scala 381:19]
|
|
node _T_569 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 382:40]
|
|
node _T_570 = or(_T_569, sbcs_illegal_size) @[el2_dbg.scala 382:57]
|
|
sb_state_en <= _T_570 @[el2_dbg.scala 382:19]
|
|
node _T_571 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 383:43]
|
|
sbcs_sberror_wren <= _T_571 @[el2_dbg.scala 383:25]
|
|
node _T_572 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 384:30]
|
|
sbcs_sberror_din <= _T_572 @[el2_dbg.scala 384:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_573 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_573 : @[Conditional.scala 39:67]
|
|
node _T_574 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 387:41]
|
|
node _T_575 = mux(_T_574, UInt<4>("h09"), UInt<4>("h04")) @[el2_dbg.scala 387:25]
|
|
sb_nxtstate <= _T_575 @[el2_dbg.scala 387:19]
|
|
node _T_576 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 388:40]
|
|
node _T_577 = or(_T_576, sbcs_illegal_size) @[el2_dbg.scala 388:57]
|
|
sb_state_en <= _T_577 @[el2_dbg.scala 388:19]
|
|
node _T_578 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 389:43]
|
|
sbcs_sberror_wren <= _T_578 @[el2_dbg.scala 389:25]
|
|
node _T_579 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 390:30]
|
|
sbcs_sberror_din <= _T_579 @[el2_dbg.scala 390:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_580 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_580 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h07") @[el2_dbg.scala 393:19]
|
|
node _T_581 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[el2_dbg.scala 394:38]
|
|
sb_state_en <= _T_581 @[el2_dbg.scala 394:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_582 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_582 : @[Conditional.scala 39:67]
|
|
node _T_583 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 397:48]
|
|
node _T_584 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[el2_dbg.scala 397:95]
|
|
node _T_585 = mux(_T_583, UInt<4>("h08"), _T_584) @[el2_dbg.scala 397:25]
|
|
sb_nxtstate <= _T_585 @[el2_dbg.scala 397:19]
|
|
node _T_586 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 398:45]
|
|
node _T_587 = and(_T_586, io.dbg_bus_clk_en) @[el2_dbg.scala 398:70]
|
|
sb_state_en <= _T_587 @[el2_dbg.scala 398:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_588 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_588 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 401:19]
|
|
node _T_589 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[el2_dbg.scala 402:44]
|
|
sb_state_en <= _T_589 @[el2_dbg.scala 402:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_590 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_590 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 405:19]
|
|
node _T_591 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[el2_dbg.scala 406:44]
|
|
sb_state_en <= _T_591 @[el2_dbg.scala 406:19]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_592 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_592 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 409:19]
|
|
node _T_593 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[el2_dbg.scala 410:38]
|
|
sb_state_en <= _T_593 @[el2_dbg.scala 410:19]
|
|
node _T_594 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 411:40]
|
|
sbcs_sberror_wren <= _T_594 @[el2_dbg.scala 411:25]
|
|
sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 412:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_595 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_595 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 415:19]
|
|
node _T_596 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[el2_dbg.scala 416:39]
|
|
sb_state_en <= _T_596 @[el2_dbg.scala 416:19]
|
|
node _T_597 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 417:40]
|
|
sbcs_sberror_wren <= _T_597 @[el2_dbg.scala 417:25]
|
|
sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 418:24]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_598 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
|
|
when _T_598 : @[Conditional.scala 39:67]
|
|
sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 421:19]
|
|
sb_state_en <= UInt<1>("h01") @[el2_dbg.scala 422:19]
|
|
sbcs_sbbusy_wren <= UInt<1>("h01") @[el2_dbg.scala 423:24]
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 424:23]
|
|
node _T_599 = bits(sbcs_reg, 16, 16) @[el2_dbg.scala 425:39]
|
|
sbaddress0_reg_wren1 <= _T_599 @[el2_dbg.scala 425:28]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_600 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 428:67]
|
|
node _T_601 = eq(_T_600, UInt<1>("h00")) @[el2_dbg.scala 428:47]
|
|
node _T_602 = asAsyncReset(_T_601) @[el2_dbg.scala 428:83]
|
|
reg _T_603 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_602, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when sb_state_en : @[Reg.scala 28:19]
|
|
_T_603 <= sb_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
sb_state <= _T_603 @[el2_dbg.scala 428:12]
|
|
node _T_604 = and(io.sb_axi_arvalid, io.sb_axi_arready) @[el2_dbg.scala 432:40]
|
|
sb_bus_cmd_read <= _T_604 @[el2_dbg.scala 432:19]
|
|
node _T_605 = and(io.sb_axi_awvalid, io.sb_axi_awready) @[el2_dbg.scala 433:46]
|
|
sb_bus_cmd_write_addr <= _T_605 @[el2_dbg.scala 433:25]
|
|
node _T_606 = and(io.sb_axi_wvalid, io.sb_axi_wready) @[el2_dbg.scala 434:45]
|
|
sb_bus_cmd_write_data <= _T_606 @[el2_dbg.scala 434:25]
|
|
node _T_607 = and(io.sb_axi_rvalid, io.sb_axi_rready) @[el2_dbg.scala 435:39]
|
|
sb_bus_rsp_read <= _T_607 @[el2_dbg.scala 435:19]
|
|
node _T_608 = and(io.sb_axi_bvalid, io.sb_axi_bready) @[el2_dbg.scala 436:40]
|
|
sb_bus_rsp_write <= _T_608 @[el2_dbg.scala 436:20]
|
|
node _T_609 = bits(io.sb_axi_rresp, 1, 0) @[el2_dbg.scala 437:56]
|
|
node _T_610 = orr(_T_609) @[el2_dbg.scala 437:63]
|
|
node _T_611 = and(sb_bus_rsp_read, _T_610) @[el2_dbg.scala 437:39]
|
|
node _T_612 = bits(io.sb_axi_bresp, 1, 0) @[el2_dbg.scala 437:103]
|
|
node _T_613 = orr(_T_612) @[el2_dbg.scala 437:110]
|
|
node _T_614 = and(sb_bus_rsp_write, _T_613) @[el2_dbg.scala 437:86]
|
|
node _T_615 = or(_T_611, _T_614) @[el2_dbg.scala 437:67]
|
|
sb_bus_rsp_error <= _T_615 @[el2_dbg.scala 437:20]
|
|
node _T_616 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 438:35]
|
|
node _T_617 = eq(sb_state, UInt<4>("h05")) @[el2_dbg.scala 438:70]
|
|
node _T_618 = or(_T_616, _T_617) @[el2_dbg.scala 438:58]
|
|
node _T_619 = bits(_T_618, 0, 0) @[el2_dbg.scala 438:105]
|
|
io.sb_axi_awvalid <= _T_619 @[el2_dbg.scala 438:21]
|
|
io.sb_axi_awaddr <= sbaddress0_reg @[el2_dbg.scala 439:20]
|
|
io.sb_axi_awid <= UInt<1>("h00") @[el2_dbg.scala 440:18]
|
|
node _T_620 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 441:31]
|
|
io.sb_axi_awsize <= _T_620 @[el2_dbg.scala 441:20]
|
|
io.sb_axi_awprot <= UInt<1>("h00") @[el2_dbg.scala 442:20]
|
|
io.sb_axi_awcache <= UInt<4>("h0f") @[el2_dbg.scala 443:21]
|
|
node _T_621 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 444:39]
|
|
io.sb_axi_awregion <= _T_621 @[el2_dbg.scala 444:22]
|
|
io.sb_axi_awlen <= UInt<1>("h00") @[el2_dbg.scala 445:19]
|
|
io.sb_axi_awburst <= UInt<1>("h01") @[el2_dbg.scala 446:21]
|
|
io.sb_axi_awqos <= UInt<1>("h00") @[el2_dbg.scala 447:19]
|
|
io.sb_axi_awlock <= UInt<1>("h00") @[el2_dbg.scala 448:20]
|
|
node _T_622 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 449:34]
|
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node _T_623 = eq(sb_state, UInt<4>("h06")) @[el2_dbg.scala 449:69]
|
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node _T_624 = or(_T_622, _T_623) @[el2_dbg.scala 449:57]
|
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node _T_625 = bits(_T_624, 0, 0) @[el2_dbg.scala 449:104]
|
|
io.sb_axi_wvalid <= _T_625 @[el2_dbg.scala 449:20]
|
|
node _T_626 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:40]
|
|
node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dbg.scala 450:49]
|
|
node _T_628 = bits(_T_627, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_629 = mux(_T_628, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_630 = bits(sbdata0_reg, 7, 0) @[el2_dbg.scala 450:81]
|
|
node _T_631 = cat(_T_630, _T_630) @[Cat.scala 29:58]
|
|
node _T_632 = cat(_T_631, _T_631) @[Cat.scala 29:58]
|
|
node _T_633 = cat(_T_632, _T_632) @[Cat.scala 29:58]
|
|
node _T_634 = and(_T_629, _T_633) @[el2_dbg.scala 450:59]
|
|
node _T_635 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:110]
|
|
node _T_636 = eq(_T_635, UInt<1>("h01")) @[el2_dbg.scala 450:119]
|
|
node _T_637 = bits(_T_636, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_638 = mux(_T_637, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_639 = bits(sbdata0_reg, 15, 0) @[el2_dbg.scala 450:153]
|
|
node _T_640 = cat(_T_639, _T_639) @[Cat.scala 29:58]
|
|
node _T_641 = cat(_T_640, _T_640) @[Cat.scala 29:58]
|
|
node _T_642 = and(_T_638, _T_641) @[el2_dbg.scala 450:132]
|
|
node _T_643 = or(_T_634, _T_642) @[el2_dbg.scala 450:90]
|
|
node _T_644 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:23]
|
|
node _T_645 = eq(_T_644, UInt<2>("h02")) @[el2_dbg.scala 451:32]
|
|
node _T_646 = bits(_T_645, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_647 = mux(_T_646, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_648 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:67]
|
|
node _T_649 = cat(_T_648, _T_648) @[Cat.scala 29:58]
|
|
node _T_650 = and(_T_647, _T_649) @[el2_dbg.scala 451:45]
|
|
node _T_651 = or(_T_643, _T_650) @[el2_dbg.scala 450:162]
|
|
node _T_652 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:97]
|
|
node _T_653 = eq(_T_652, UInt<2>("h03")) @[el2_dbg.scala 451:106]
|
|
node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_655 = mux(_T_654, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_656 = bits(sbdata1_reg, 31, 0) @[el2_dbg.scala 451:136]
|
|
node _T_657 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:156]
|
|
node _T_658 = cat(_T_656, _T_657) @[Cat.scala 29:58]
|
|
node _T_659 = and(_T_655, _T_658) @[el2_dbg.scala 451:119]
|
|
node _T_660 = or(_T_651, _T_659) @[el2_dbg.scala 451:77]
|
|
io.sb_axi_wdata <= _T_660 @[el2_dbg.scala 450:19]
|
|
node _T_661 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 453:39]
|
|
node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dbg.scala 453:48]
|
|
node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_664 = mux(_T_663, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_665 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 453:93]
|
|
node _T_666 = dshl(UInt<8>("h01"), _T_665) @[el2_dbg.scala 453:76]
|
|
node _T_667 = and(_T_664, _T_666) @[el2_dbg.scala 453:61]
|
|
node _T_668 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 454:22]
|
|
node _T_669 = eq(_T_668, UInt<1>("h01")) @[el2_dbg.scala 454:31]
|
|
node _T_670 = bits(_T_669, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_671 = mux(_T_670, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_672 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 454:80]
|
|
node _T_673 = cat(_T_672, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_674 = dshl(UInt<8>("h03"), _T_673) @[el2_dbg.scala 454:59]
|
|
node _T_675 = and(_T_671, _T_674) @[el2_dbg.scala 454:44]
|
|
node _T_676 = or(_T_667, _T_675) @[el2_dbg.scala 453:101]
|
|
node _T_677 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 455:22]
|
|
node _T_678 = eq(_T_677, UInt<2>("h02")) @[el2_dbg.scala 455:31]
|
|
node _T_679 = bits(_T_678, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_680 = mux(_T_679, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_681 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 455:80]
|
|
node _T_682 = cat(_T_681, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_683 = dshl(UInt<8>("h0f"), _T_682) @[el2_dbg.scala 455:59]
|
|
node _T_684 = and(_T_680, _T_683) @[el2_dbg.scala 455:44]
|
|
node _T_685 = or(_T_676, _T_684) @[el2_dbg.scala 454:97]
|
|
node _T_686 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 456:22]
|
|
node _T_687 = eq(_T_686, UInt<2>("h03")) @[el2_dbg.scala 456:31]
|
|
node _T_688 = bits(_T_687, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_689 = mux(_T_688, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_690 = and(_T_689, UInt<8>("h0ff")) @[el2_dbg.scala 456:44]
|
|
node _T_691 = or(_T_685, _T_690) @[el2_dbg.scala 455:95]
|
|
io.sb_axi_wstrb <= _T_691 @[el2_dbg.scala 453:19]
|
|
io.sb_axi_wlast <= UInt<1>("h01") @[el2_dbg.scala 458:19]
|
|
node _T_692 = eq(sb_state, UInt<4>("h03")) @[el2_dbg.scala 459:34]
|
|
node _T_693 = bits(_T_692, 0, 0) @[el2_dbg.scala 459:63]
|
|
io.sb_axi_arvalid <= _T_693 @[el2_dbg.scala 459:21]
|
|
io.sb_axi_araddr <= sbaddress0_reg @[el2_dbg.scala 460:20]
|
|
io.sb_axi_arid <= UInt<1>("h00") @[el2_dbg.scala 461:18]
|
|
node _T_694 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 462:31]
|
|
io.sb_axi_arsize <= _T_694 @[el2_dbg.scala 462:20]
|
|
io.sb_axi_arprot <= UInt<1>("h00") @[el2_dbg.scala 463:20]
|
|
io.sb_axi_arcache <= UInt<1>("h00") @[el2_dbg.scala 464:21]
|
|
node _T_695 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 465:39]
|
|
io.sb_axi_arregion <= _T_695 @[el2_dbg.scala 465:22]
|
|
io.sb_axi_arlen <= UInt<1>("h00") @[el2_dbg.scala 466:19]
|
|
io.sb_axi_arburst <= UInt<1>("h01") @[el2_dbg.scala 467:21]
|
|
io.sb_axi_arqos <= UInt<1>("h00") @[el2_dbg.scala 468:19]
|
|
io.sb_axi_arlock <= UInt<1>("h00") @[el2_dbg.scala 469:20]
|
|
io.sb_axi_bready <= UInt<1>("h01") @[el2_dbg.scala 470:20]
|
|
io.sb_axi_rready <= UInt<1>("h01") @[el2_dbg.scala 471:20]
|
|
node _T_696 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 472:37]
|
|
node _T_697 = eq(_T_696, UInt<1>("h00")) @[el2_dbg.scala 472:46]
|
|
node _T_698 = bits(_T_697, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_699 = mux(_T_698, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_700 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 472:78]
|
|
node _T_701 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 472:109]
|
|
node _T_702 = mul(UInt<4>("h08"), _T_701) @[el2_dbg.scala 472:93]
|
|
node _T_703 = dshr(_T_700, _T_702) @[el2_dbg.scala 472:86]
|
|
node _T_704 = and(_T_703, UInt<64>("h0ff")) @[el2_dbg.scala 472:117]
|
|
node _T_705 = and(_T_699, _T_704) @[el2_dbg.scala 472:59]
|
|
node _T_706 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 473:23]
|
|
node _T_707 = eq(_T_706, UInt<1>("h01")) @[el2_dbg.scala 473:32]
|
|
node _T_708 = bits(_T_707, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_709 = mux(_T_708, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_710 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 473:64]
|
|
node _T_711 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 473:96]
|
|
node _T_712 = mul(UInt<5>("h010"), _T_711) @[el2_dbg.scala 473:80]
|
|
node _T_713 = dshr(_T_710, _T_712) @[el2_dbg.scala 473:72]
|
|
node _T_714 = and(_T_713, UInt<64>("h0ffff")) @[el2_dbg.scala 473:104]
|
|
node _T_715 = and(_T_709, _T_714) @[el2_dbg.scala 473:45]
|
|
node _T_716 = or(_T_705, _T_715) @[el2_dbg.scala 472:134]
|
|
node _T_717 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 474:23]
|
|
node _T_718 = eq(_T_717, UInt<2>("h02")) @[el2_dbg.scala 474:32]
|
|
node _T_719 = bits(_T_718, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_720 = mux(_T_719, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_721 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 474:64]
|
|
node _T_722 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 474:96]
|
|
node _T_723 = mul(UInt<6>("h020"), _T_722) @[el2_dbg.scala 474:80]
|
|
node _T_724 = dshr(_T_721, _T_723) @[el2_dbg.scala 474:72]
|
|
node _T_725 = and(_T_724, UInt<64>("h0ffffffff")) @[el2_dbg.scala 474:101]
|
|
node _T_726 = and(_T_720, _T_725) @[el2_dbg.scala 474:45]
|
|
node _T_727 = or(_T_716, _T_726) @[el2_dbg.scala 473:123]
|
|
node _T_728 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 475:23]
|
|
node _T_729 = eq(_T_728, UInt<2>("h03")) @[el2_dbg.scala 475:32]
|
|
node _T_730 = bits(_T_729, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_731 = mux(_T_730, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_732 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 475:62]
|
|
node _T_733 = and(_T_731, _T_732) @[el2_dbg.scala 475:45]
|
|
node _T_734 = or(_T_727, _T_733) @[el2_dbg.scala 474:125]
|
|
sb_bus_rdata <= _T_734 @[el2_dbg.scala 472:16]
|
|
|