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quasar/el2_dec_tlu_ctl.fir

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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_tlu_ctl :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_dec_timer_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>}
wire mitctl1 : UInt<4>
mitctl1 <= UInt<1>("h00")
wire mitctl0 : UInt<3>
mitctl0 <= UInt<1>("h00")
wire mitb1 : UInt<32>
mitb1 <= UInt<1>("h00")
wire mitb0 : UInt<32>
mitb0 <= UInt<1>("h00")
wire mitcnt1 : UInt<32>
mitcnt1 <= UInt<1>("h00")
wire mitcnt0 : UInt<32>
mitcnt0 <= UInt<1>("h00")
node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2754:36]
node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2755:36]
io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2757:31]
io.dec_timer_t1_pulse <= mit1_match_ns @[el2_dec_tlu_ctl.scala 2758:31]
node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[el2_dec_tlu_ctl.scala 2765:72]
node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[el2_dec_tlu_ctl.scala 2765:49]
node _T_1 = bits(mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2767:37]
node _T_2 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2767:56]
node _T_3 = bits(mitctl0, 2, 2) @[el2_dec_tlu_ctl.scala 2767:85]
node _T_4 = or(_T_2, _T_3) @[el2_dec_tlu_ctl.scala 2767:76]
node _T_5 = and(_T_1, _T_4) @[el2_dec_tlu_ctl.scala 2767:53]
node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2767:112]
node _T_7 = bits(mitctl0, 1, 1) @[el2_dec_tlu_ctl.scala 2767:147]
node _T_8 = or(_T_6, _T_7) @[el2_dec_tlu_ctl.scala 2767:138]
node _T_9 = and(_T_5, _T_8) @[el2_dec_tlu_ctl.scala 2767:109]
node _T_10 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2767:173]
node mitcnt0_inc_ok = and(_T_9, _T_10) @[el2_dec_tlu_ctl.scala 2767:171]
node _T_11 = add(mitcnt0, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2768:35]
node mitcnt0_inc = tail(_T_11, 1) @[el2_dec_tlu_ctl.scala 2768:35]
node _T_12 = bits(mit0_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2769:44]
node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2769:74]
node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2769:60]
node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2769:29]
node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2770:59]
node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2770:76]
node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2770:93]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= _T_17 @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_18 <= mitcnt0_ns @[el2_lib.scala 514:16]
mitcnt0 <= _T_18 @[el2_dec_tlu_ctl.scala 2770:25]
node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[el2_dec_tlu_ctl.scala 2777:72]
node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[el2_dec_tlu_ctl.scala 2777:49]
node _T_20 = bits(mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2779:37]
node _T_21 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2779:56]
node _T_22 = bits(mitctl1, 2, 2) @[el2_dec_tlu_ctl.scala 2779:85]
node _T_23 = or(_T_21, _T_22) @[el2_dec_tlu_ctl.scala 2779:76]
node _T_24 = and(_T_20, _T_23) @[el2_dec_tlu_ctl.scala 2779:53]
node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2779:112]
node _T_26 = bits(mitctl1, 1, 1) @[el2_dec_tlu_ctl.scala 2779:147]
node _T_27 = or(_T_25, _T_26) @[el2_dec_tlu_ctl.scala 2779:138]
node _T_28 = and(_T_24, _T_27) @[el2_dec_tlu_ctl.scala 2779:109]
node _T_29 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2779:173]
node mitcnt1_inc_ok = and(_T_28, _T_29) @[el2_dec_tlu_ctl.scala 2779:171]
node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_31 = bits(mitctl1, 3, 3) @[el2_dec_tlu_ctl.scala 2782:68]
node _T_32 = not(_T_31) @[el2_dec_tlu_ctl.scala 2782:60]
node _T_33 = or(_T_32, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2782:72]
node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58]
node _T_35 = add(mitcnt1, _T_34) @[el2_dec_tlu_ctl.scala 2782:35]
node mitcnt1_inc = tail(_T_35, 1) @[el2_dec_tlu_ctl.scala 2782:35]
node _T_36 = bits(mit1_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2783:45]
node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2783:75]
node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[el2_dec_tlu_ctl.scala 2783:61]
node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[el2_dec_tlu_ctl.scala 2783:30]
node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[el2_dec_tlu_ctl.scala 2784:60]
node _T_40 = or(_T_39, mit1_match_ns) @[el2_dec_tlu_ctl.scala 2784:77]
node _T_41 = bits(_T_40, 0, 0) @[el2_dec_tlu_ctl.scala 2784:94]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 511:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_42 <= mitcnt1_ns @[el2_lib.scala 514:16]
mitcnt1 <= _T_42 @[el2_dec_tlu_ctl.scala 2784:25]
node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[el2_dec_tlu_ctl.scala 2791:70]
node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[el2_dec_tlu_ctl.scala 2791:47]
node _T_44 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2792:38]
node _T_45 = bits(wr_mitb0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2792:71]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 511:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
mitb0_b <= _T_44 @[el2_lib.scala 514:16]
node _T_46 = not(mitb0_b) @[el2_dec_tlu_ctl.scala 2793:22]
mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2793:19]
node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2800:69]
node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2800:47]
node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2801:29]
node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2801:62]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
mitb1_b <= _T_48 @[el2_lib.scala 514:16]
node _T_50 = not(mitb1_b) @[el2_dec_tlu_ctl.scala 2802:18]
mitb1 <= _T_50 @[el2_dec_tlu_ctl.scala 2802:15]
node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[el2_dec_tlu_ctl.scala 2813:72]
node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[el2_dec_tlu_ctl.scala 2813:49]
node _T_52 = bits(wr_mitctl0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2814:45]
node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[el2_dec_tlu_ctl.scala 2814:72]
node _T_54 = bits(mitctl0, 2, 0) @[el2_dec_tlu_ctl.scala 2814:86]
node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[el2_dec_tlu_ctl.scala 2814:31]
node _T_55 = bits(mitctl0_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2816:41]
node mitctl0_0_b_ns = not(_T_55) @[el2_dec_tlu_ctl.scala 2816:30]
reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2817:60]
mitctl0_0_b <= mitctl0_0_b_ns @[el2_dec_tlu_ctl.scala 2817:60]
node _T_56 = bits(mitctl0_ns, 2, 1) @[el2_dec_tlu_ctl.scala 2818:78]
reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2818:67]
_T_57 <= _T_56 @[el2_dec_tlu_ctl.scala 2818:67]
node _T_58 = not(mitctl0_0_b) @[el2_dec_tlu_ctl.scala 2818:90]
node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58]
mitctl0 <= _T_59 @[el2_dec_tlu_ctl.scala 2818:31]
node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[el2_dec_tlu_ctl.scala 2828:71]
node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[el2_dec_tlu_ctl.scala 2828:49]
node _T_61 = bits(wr_mitctl1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2829:45]
node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2829:71]
node _T_63 = bits(mitctl1, 3, 0) @[el2_dec_tlu_ctl.scala 2829:85]
node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[el2_dec_tlu_ctl.scala 2829:31]
node _T_64 = bits(mitctl1_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2830:40]
node mitctl1_0_b_ns = not(_T_64) @[el2_dec_tlu_ctl.scala 2830:29]
reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2831:55]
mitctl1_0_b <= mitctl1_0_b_ns @[el2_dec_tlu_ctl.scala 2831:55]
node _T_65 = bits(mitctl1_ns, 3, 1) @[el2_dec_tlu_ctl.scala 2832:63]
reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2832:52]
_T_66 <= _T_65 @[el2_dec_tlu_ctl.scala 2832:52]
node _T_67 = not(mitctl1_0_b) @[el2_dec_tlu_ctl.scala 2832:75]
node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58]
mitctl1 <= _T_68 @[el2_dec_tlu_ctl.scala 2832:16]
node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[el2_dec_tlu_ctl.scala 2834:51]
node _T_70 = or(_T_69, io.csr_mitb1) @[el2_dec_tlu_ctl.scala 2834:68]
node _T_71 = or(_T_70, io.csr_mitb0) @[el2_dec_tlu_ctl.scala 2834:83]
node _T_72 = or(_T_71, io.csr_mitctl0) @[el2_dec_tlu_ctl.scala 2834:98]
node _T_73 = or(_T_72, io.csr_mitctl1) @[el2_dec_tlu_ctl.scala 2834:115]
io.dec_timer_read_d <= _T_73 @[el2_dec_tlu_ctl.scala 2834:33]
node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[el2_dec_tlu_ctl.scala 2836:25]
node _T_75 = bits(mitcnt0, 31, 0) @[el2_dec_tlu_ctl.scala 2836:44]
node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[el2_dec_tlu_ctl.scala 2837:32]
node _T_77 = bits(io.csr_mitb0, 0, 0) @[el2_dec_tlu_ctl.scala 2838:30]
node _T_78 = bits(io.csr_mitb1, 0, 0) @[el2_dec_tlu_ctl.scala 2839:30]
node _T_79 = bits(io.csr_mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2840:32]
node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58]
node _T_82 = bits(io.csr_mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2841:32]
node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58]
node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72]
node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72]
node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72]
node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72]
node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72]
wire _T_96 : UInt<32> @[Mux.scala 27:72]
_T_96 <= _T_95 @[Mux.scala 27:72]
io.dec_timer_rddata_d <= _T_96 @[el2_dec_tlu_ctl.scala 2835:33]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_12 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_12 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_13 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_13 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_14 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_14 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_15 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_15 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_16 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_16 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_17 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_17 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_18 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_18 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_19 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_19 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_20 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_20 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_21 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_21 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_22 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_22 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_23 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_23 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_24 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_24 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_25 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_25 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_26 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_26 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_27 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_27 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_28 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_28 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_29 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_29 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_30 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_30 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_31 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_31 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_32 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_32 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_33 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_33 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_34 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_34 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_35 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_35 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_36 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_36 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_36 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_37 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_37 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_37 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_38 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_38 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_38 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_39 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_39 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_39 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_40 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_40 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_40 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_41 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_41 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_41 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_42 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_42 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_42 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module csr_tlu :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip ifu_pmu_bus_error : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]}
wire miccme_ce_req : UInt<1>
miccme_ce_req <= UInt<1>("h00")
wire mice_ce_req : UInt<1>
mice_ce_req <= UInt<1>("h00")
wire mdccme_ce_req : UInt<1>
mdccme_ce_req <= UInt<1>("h00")
wire pc_r_d1 : UInt<31>
pc_r_d1 <= UInt<1>("h00")
wire mpmc_b_ns : UInt<1>
mpmc_b_ns <= UInt<1>("h00")
wire mpmc_b : UInt<1>
mpmc_b <= UInt<1>("h00")
wire wr_mcycleh_r : UInt<1>
wr_mcycleh_r <= UInt<1>("h00")
wire mcycleh : UInt<32>
mcycleh <= UInt<1>("h00")
wire minstretl_inc : UInt<33>
minstretl_inc <= UInt<1>("h00")
wire wr_minstreth_r : UInt<1>
wr_minstreth_r <= UInt<1>("h00")
wire minstretl : UInt<32>
minstretl <= UInt<1>("h00")
wire minstreth_inc : UInt<32>
minstreth_inc <= UInt<1>("h00")
wire minstreth : UInt<32>
minstreth <= UInt<1>("h00")
wire mfdc_ns : UInt<15>
mfdc_ns <= UInt<1>("h00")
wire mfdc_int : UInt<15>
mfdc_int <= UInt<1>("h00")
wire mhpmc6_incr : UInt<64>
mhpmc6_incr <= UInt<1>("h00")
wire mhpmc5_incr : UInt<64>
mhpmc5_incr <= UInt<1>("h00")
wire mhpmc4_incr : UInt<64>
mhpmc4_incr <= UInt<1>("h00")
wire perfcnt_halted : UInt<1>
perfcnt_halted <= UInt<1>("h00")
wire mhpmc3_incr : UInt<64>
mhpmc3_incr <= UInt<1>("h00")
wire mhpme_vec : UInt<10>[4] @[el2_dec_tlu_ctl.scala 1475:41]
wire mtdata2_t : UInt<32>[4] @[el2_dec_tlu_ctl.scala 1476:65]
wire wr_meicpct_r : UInt<1>
wr_meicpct_r <= UInt<1>("h00")
wire force_halt_ctr_f : UInt<32>
force_halt_ctr_f <= UInt<1>("h00")
wire mdccmect_inc : UInt<27>
mdccmect_inc <= UInt<1>("h00")
wire miccmect_inc : UInt<27>
miccmect_inc <= UInt<1>("h00")
wire micect_inc : UInt<27>
micect_inc <= UInt<1>("h00")
wire mdseac_en : UInt<1>
mdseac_en <= UInt<1>("h00")
wire mie : UInt<6>
mie <= UInt<1>("h00")
wire mcyclel : UInt<32>
mcyclel <= UInt<1>("h00")
wire mscratch : UInt<32>
mscratch <= UInt<1>("h00")
wire mcause : UInt<32>
mcause <= UInt<1>("h00")
wire mscause : UInt<4>
mscause <= UInt<1>("h00")
wire mtval : UInt<32>
mtval <= UInt<1>("h00")
wire meicurpl : UInt<4>
meicurpl <= UInt<1>("h00")
wire meicidpl : UInt<4>
meicidpl <= UInt<1>("h00")
wire meipt : UInt<4>
meipt <= UInt<1>("h00")
wire mfdc : UInt<19>
mfdc <= UInt<1>("h00")
wire mtsel : UInt<2>
mtsel <= UInt<1>("h00")
wire micect : UInt<32>
micect <= UInt<1>("h00")
wire miccmect : UInt<32>
miccmect <= UInt<1>("h00")
wire mdccmect : UInt<32>
mdccmect <= UInt<1>("h00")
wire mhpmc3h : UInt<32>
mhpmc3h <= UInt<1>("h00")
wire mhpmc3 : UInt<32>
mhpmc3 <= UInt<1>("h00")
wire mhpmc4h : UInt<32>
mhpmc4h <= UInt<1>("h00")
wire mhpmc4 : UInt<32>
mhpmc4 <= UInt<1>("h00")
wire mhpmc5h : UInt<32>
mhpmc5h <= UInt<1>("h00")
wire mhpmc5 : UInt<32>
mhpmc5 <= UInt<1>("h00")
wire mhpmc6h : UInt<32>
mhpmc6h <= UInt<1>("h00")
wire mhpmc6 : UInt<32>
mhpmc6 <= UInt<1>("h00")
wire mhpme3 : UInt<10>
mhpme3 <= UInt<1>("h00")
wire mhpme4 : UInt<10>
mhpme4 <= UInt<1>("h00")
wire mhpme5 : UInt<10>
mhpme5 <= UInt<1>("h00")
wire mhpme6 : UInt<10>
mhpme6 <= UInt<1>("h00")
wire mfdht : UInt<6>
mfdht <= UInt<1>("h00")
wire mfdhs : UInt<2>
mfdhs <= UInt<1>("h00")
wire mcountinhibit : UInt<7>
mcountinhibit <= UInt<1>("h00")
wire mpmc : UInt<1>
mpmc <= UInt<1>("h00")
wire dicad1 : UInt<32>
dicad1 <= UInt<1>("h00")
node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1531:45]
node _T_1 = and(io.dec_csr_wen_r, _T) @[el2_dec_tlu_ctl.scala 1531:43]
node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1531:68]
node _T_3 = and(_T_1, _T_2) @[el2_dec_tlu_ctl.scala 1531:66]
io.dec_csr_wen_r_mod <= _T_3 @[el2_dec_tlu_ctl.scala 1531:23]
node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1532:64]
node _T_5 = eq(_T_4, UInt<12>("h0300")) @[el2_dec_tlu_ctl.scala 1532:71]
node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[el2_dec_tlu_ctl.scala 1532:42]
node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1535:28]
node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[el2_dec_tlu_ctl.scala 1535:39]
node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1538:5]
node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1538:19]
node _T_9 = bits(_T_8, 0, 0) @[el2_dec_tlu_ctl.scala 1538:44]
node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1538:68]
node _T_11 = bits(_T_10, 0, 0) @[el2_dec_tlu_ctl.scala 1538:68]
node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1539:18]
node _T_14 = bits(_T_13, 0, 0) @[el2_dec_tlu_ctl.scala 1539:43]
node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1539:76]
node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1540:17]
node _T_18 = and(io.mret_r, _T_17) @[el2_dec_tlu_ctl.scala 1540:15]
node _T_19 = bits(_T_18, 0, 0) @[el2_dec_tlu_ctl.scala 1540:41]
node _T_20 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1540:70]
node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58]
node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[el2_dec_tlu_ctl.scala 1541:26]
node _T_23 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1541:50]
node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:20]
node _T_26 = and(wr_mstatus_r, _T_25) @[el2_dec_tlu_ctl.scala 1542:18]
node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 1542:44]
node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1542:77]
node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1542:101]
node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58]
node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1543:5]
node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1543:21]
node _T_33 = and(_T_31, _T_32) @[el2_dec_tlu_ctl.scala 1543:19]
node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1543:46]
node _T_35 = and(_T_33, _T_34) @[el2_dec_tlu_ctl.scala 1543:44]
node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1543:59]
node _T_37 = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 1543:57]
node _T_38 = bits(_T_37, 0, 0) @[el2_dec_tlu_ctl.scala 1543:81]
node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_42 = mux(_T_22, _T_24, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_43 = mux(_T_27, _T_30, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_44 = mux(_T_38, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_45 = or(_T_39, _T_40) @[Mux.scala 27:72]
node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72]
node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72]
node _T_48 = or(_T_47, _T_43) @[Mux.scala 27:72]
node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72]
wire mstatus_ns : UInt<2> @[Mux.scala 27:72]
mstatus_ns <= _T_49 @[Mux.scala 27:72]
node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1546:33]
node _T_51 = bits(_T_50, 0, 0) @[el2_dec_tlu_ctl.scala 1546:33]
node _T_52 = not(io.dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 1546:50]
node _T_53 = bits(io.dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 1546:90]
node _T_54 = or(_T_52, _T_53) @[el2_dec_tlu_ctl.scala 1546:81]
node _T_55 = and(_T_51, _T_54) @[el2_dec_tlu_ctl.scala 1546:47]
io.mstatus_mie_ns <= _T_55 @[el2_dec_tlu_ctl.scala 1546:20]
reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1548:11]
_T_56 <= mstatus_ns @[el2_dec_tlu_ctl.scala 1548:11]
io.mstatus <= _T_56 @[el2_dec_tlu_ctl.scala 1547:13]
node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1557:62]
node _T_58 = eq(_T_57, UInt<12>("h0305")) @[el2_dec_tlu_ctl.scala 1557:69]
node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[el2_dec_tlu_ctl.scala 1557:40]
node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[el2_dec_tlu_ctl.scala 1558:40]
node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1558:68]
node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58]
node _T_61 = bits(wr_mtvec_r, 0, 0) @[el2_dec_tlu_ctl.scala 1559:42]
inst rvclkhdr of rvclkhdr_8 @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= _T_61 @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_62 <= mtvec_ns @[el2_lib.scala 514:16]
io.mtvec <= _T_62 @[el2_dec_tlu_ctl.scala 1559:11]
node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[el2_dec_tlu_ctl.scala 1571:30]
node ce_int = or(_T_63, mice_ce_req) @[el2_dec_tlu_ctl.scala 1571:46]
node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58]
node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58]
node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58]
node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58]
node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58]
reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1575:11]
_T_68 <= mip_ns @[el2_dec_tlu_ctl.scala 1575:11]
io.mip <= _T_68 @[el2_dec_tlu_ctl.scala 1574:9]
node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1587:60]
node _T_70 = eq(_T_69, UInt<12>("h0304")) @[el2_dec_tlu_ctl.scala 1587:67]
node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[el2_dec_tlu_ctl.scala 1587:38]
node _T_71 = bits(wr_mie_r, 0, 0) @[el2_dec_tlu_ctl.scala 1588:28]
node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[el2_dec_tlu_ctl.scala 1588:59]
node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1588:88]
node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1588:113]
node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1588:137]
node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58]
node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58]
node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
node _T_79 = mux(_T_71, _T_78, mie) @[el2_dec_tlu_ctl.scala 1588:18]
io.mie_ns <= _T_79 @[el2_dec_tlu_ctl.scala 1588:12]
reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1590:11]
_T_80 <= io.mie_ns @[el2_dec_tlu_ctl.scala 1590:11]
mie <= _T_80 @[el2_dec_tlu_ctl.scala 1589:6]
node _T_81 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1597:63]
node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[el2_dec_tlu_ctl.scala 1597:54]
node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1599:64]
node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[el2_dec_tlu_ctl.scala 1599:71]
node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[el2_dec_tlu_ctl.scala 1599:42]
node _T_84 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1601:80]
node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[el2_dec_tlu_ctl.scala 1601:71]
node _T_86 = or(kill_ebreak_count_r, _T_85) @[el2_dec_tlu_ctl.scala 1601:46]
node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 1601:94]
node _T_88 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 1601:136]
node _T_89 = or(_T_87, _T_88) @[el2_dec_tlu_ctl.scala 1601:121]
node mcyclel_cout_in = not(_T_89) @[el2_dec_tlu_ctl.scala 1601:24]
wire mcyclel_inc : UInt<33>
mcyclel_inc <= UInt<1>("h00")
node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58]
node _T_91 = add(mcyclel, _T_90) @[el2_dec_tlu_ctl.scala 1605:25]
mcyclel_inc <= _T_91 @[el2_dec_tlu_ctl.scala 1605:14]
node _T_92 = bits(wr_mcyclel_r, 0, 0) @[el2_dec_tlu_ctl.scala 1606:36]
node _T_93 = bits(mcyclel_inc, 31, 0) @[el2_dec_tlu_ctl.scala 1606:76]
node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[el2_dec_tlu_ctl.scala 1606:22]
node _T_94 = bits(mcyclel_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1607:32]
node mcyclel_cout = bits(_T_94, 0, 0) @[el2_dec_tlu_ctl.scala 1607:37]
node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[el2_dec_tlu_ctl.scala 1608:46]
node _T_96 = bits(_T_95, 0, 0) @[el2_dec_tlu_ctl.scala 1608:72]
inst rvclkhdr_1 of rvclkhdr_9 @[el2_lib.scala 508:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_1.io.en <= _T_96 @[el2_lib.scala 511:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_97 <= mcyclel_ns @[el2_lib.scala 514:16]
mcyclel <= _T_97 @[el2_dec_tlu_ctl.scala 1608:10]
node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1609:71]
node _T_99 = and(mcyclel_cout, _T_98) @[el2_dec_tlu_ctl.scala 1609:69]
reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1609:54]
mcyclel_cout_f <= _T_99 @[el2_dec_tlu_ctl.scala 1609:54]
node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1615:61]
node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[el2_dec_tlu_ctl.scala 1615:68]
node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[el2_dec_tlu_ctl.scala 1615:39]
wr_mcycleh_r <= _T_102 @[el2_dec_tlu_ctl.scala 1615:15]
node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58]
node _T_104 = add(mcycleh, _T_103) @[el2_dec_tlu_ctl.scala 1617:28]
node mcycleh_inc = tail(_T_104, 1) @[el2_dec_tlu_ctl.scala 1617:28]
node _T_105 = bits(wr_mcycleh_r, 0, 0) @[el2_dec_tlu_ctl.scala 1618:36]
node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[el2_dec_tlu_ctl.scala 1618:22]
node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[el2_dec_tlu_ctl.scala 1620:46]
node _T_107 = bits(_T_106, 0, 0) @[el2_dec_tlu_ctl.scala 1620:64]
inst rvclkhdr_2 of rvclkhdr_10 @[el2_lib.scala 508:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_2.io.en <= _T_107 @[el2_lib.scala 511:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_108 <= mcycleh_ns @[el2_lib.scala 514:16]
mcycleh <= _T_108 @[el2_dec_tlu_ctl.scala 1620:10]
node _T_109 = or(io.ebreak_r, io.ecall_r) @[el2_dec_tlu_ctl.scala 1634:72]
node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 1634:85]
node _T_111 = or(_T_110, io.illegal_r) @[el2_dec_tlu_ctl.scala 1634:113]
node _T_112 = bits(mcountinhibit, 2, 2) @[el2_dec_tlu_ctl.scala 1634:143]
node _T_113 = or(_T_111, _T_112) @[el2_dec_tlu_ctl.scala 1634:128]
node _T_114 = bits(_T_113, 0, 0) @[el2_dec_tlu_ctl.scala 1634:148]
node _T_115 = not(_T_114) @[el2_dec_tlu_ctl.scala 1634:58]
node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[el2_dec_tlu_ctl.scala 1634:56]
node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1636:66]
node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[el2_dec_tlu_ctl.scala 1636:73]
node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[el2_dec_tlu_ctl.scala 1636:44]
node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58]
node _T_119 = add(minstretl, _T_118) @[el2_dec_tlu_ctl.scala 1638:29]
minstretl_inc <= _T_119 @[el2_dec_tlu_ctl.scala 1638:16]
node minstretl_cout = bits(minstretl_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1639:36]
node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[el2_dec_tlu_ctl.scala 1640:52]
node minstret_enable = bits(_T_120, 0, 0) @[el2_dec_tlu_ctl.scala 1640:70]
node _T_121 = bits(wr_minstretl_r, 0, 0) @[el2_dec_tlu_ctl.scala 1642:40]
node _T_122 = bits(minstretl_inc, 31, 0) @[el2_dec_tlu_ctl.scala 1642:83]
node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[el2_dec_tlu_ctl.scala 1642:24]
node _T_123 = bits(minstret_enable, 0, 0) @[el2_dec_tlu_ctl.scala 1643:51]
inst rvclkhdr_3 of rvclkhdr_11 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_123 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_124 <= minstretl_ns @[el2_lib.scala 514:16]
minstretl <= _T_124 @[el2_dec_tlu_ctl.scala 1643:12]
reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1644:56]
minstret_enable_f <= minstret_enable @[el2_dec_tlu_ctl.scala 1644:56]
node _T_125 = not(wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1645:75]
node _T_126 = and(minstretl_cout, _T_125) @[el2_dec_tlu_ctl.scala 1645:73]
reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1645:56]
minstretl_cout_f <= _T_126 @[el2_dec_tlu_ctl.scala 1645:56]
node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1653:64]
node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[el2_dec_tlu_ctl.scala 1653:71]
node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[el2_dec_tlu_ctl.scala 1653:42]
node _T_130 = bits(_T_129, 0, 0) @[el2_dec_tlu_ctl.scala 1653:87]
wr_minstreth_r <= _T_130 @[el2_dec_tlu_ctl.scala 1653:17]
node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58]
node _T_132 = add(minstreth, _T_131) @[el2_dec_tlu_ctl.scala 1656:29]
node _T_133 = tail(_T_132, 1) @[el2_dec_tlu_ctl.scala 1656:29]
minstreth_inc <= _T_133 @[el2_dec_tlu_ctl.scala 1656:16]
node _T_134 = bits(wr_minstreth_r, 0, 0) @[el2_dec_tlu_ctl.scala 1657:41]
node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[el2_dec_tlu_ctl.scala 1657:25]
node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1659:55]
node _T_136 = bits(_T_135, 0, 0) @[el2_dec_tlu_ctl.scala 1659:73]
inst rvclkhdr_4 of rvclkhdr_12 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_4.io.en <= _T_136 @[el2_lib.scala 511:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_137 <= minstreth_ns @[el2_lib.scala 514:16]
minstreth <= _T_137 @[el2_dec_tlu_ctl.scala 1659:12]
node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1667:65]
node _T_139 = eq(_T_138, UInt<12>("h0340")) @[el2_dec_tlu_ctl.scala 1667:72]
node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[el2_dec_tlu_ctl.scala 1667:43]
node _T_140 = bits(wr_mscratch_r, 0, 0) @[el2_dec_tlu_ctl.scala 1669:55]
inst rvclkhdr_5 of rvclkhdr_13 @[el2_lib.scala 508:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_5.io.en <= _T_140 @[el2_lib.scala 511:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_141 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
mscratch <= _T_141 @[el2_dec_tlu_ctl.scala 1669:11]
node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:22]
node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:47]
node _T_144 = and(_T_142, _T_143) @[el2_dec_tlu_ctl.scala 1678:45]
node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1678:72]
node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:24]
node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 1679:47]
node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:75]
node sel_flush_npc_r = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 1679:73]
node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1680:23]
node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1680:40]
node sel_hold_npc_r = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 1680:38]
node _T_150 = bits(sel_exu_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1683:26]
node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1684:13]
node _T_152 = and(_T_151, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1684:35]
node _T_153 = bits(_T_152, 0, 0) @[el2_dec_tlu_ctl.scala 1684:55]
node _T_154 = bits(sel_flush_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1685:28]
node _T_155 = bits(sel_hold_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1686:27]
node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_159 = mux(_T_155, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_160 = or(_T_156, _T_157) @[Mux.scala 27:72]
node _T_161 = or(_T_160, _T_158) @[Mux.scala 27:72]
node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72]
wire _T_163 : UInt<31> @[Mux.scala 27:72]
_T_163 <= _T_162 @[Mux.scala 27:72]
io.npc_r <= _T_163 @[el2_dec_tlu_ctl.scala 1682:11]
node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[el2_dec_tlu_ctl.scala 1688:48]
node _T_165 = or(_T_164, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1688:66]
node _T_166 = bits(_T_165, 0, 0) @[el2_dec_tlu_ctl.scala 1688:86]
inst rvclkhdr_6 of rvclkhdr_14 @[el2_lib.scala 508:23]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_6.io.en <= _T_166 @[el2_lib.scala 511:17]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_167 <= io.npc_r @[el2_lib.scala 514:16]
io.npc_r_d1 <= _T_167 @[el2_dec_tlu_ctl.scala 1688:14]
node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1691:21]
node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1691:44]
node pc0_valid_r = bits(_T_169, 0, 0) @[el2_dec_tlu_ctl.scala 1691:69]
node _T_170 = not(pc0_valid_r) @[el2_dec_tlu_ctl.scala 1695:22]
node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72]
wire pc_r : UInt<31> @[Mux.scala 27:72]
pc_r <= _T_173 @[Mux.scala 27:72]
inst rvclkhdr_7 of rvclkhdr_15 @[el2_lib.scala 508:23]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 511:17]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_174 <= pc_r @[el2_lib.scala 514:16]
pc_r_d1 <= _T_174 @[el2_dec_tlu_ctl.scala 1697:10]
node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1699:61]
node _T_176 = eq(_T_175, UInt<12>("h0341")) @[el2_dec_tlu_ctl.scala 1699:68]
node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[el2_dec_tlu_ctl.scala 1699:39]
node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1702:27]
node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1702:48]
node _T_179 = bits(_T_178, 0, 0) @[el2_dec_tlu_ctl.scala 1702:80]
node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1703:25]
node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:15]
node _T_182 = and(wr_mepc_r, _T_181) @[el2_dec_tlu_ctl.scala 1704:13]
node _T_183 = bits(_T_182, 0, 0) @[el2_dec_tlu_ctl.scala 1704:39]
node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 1704:104]
node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1705:3]
node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1705:16]
node _T_187 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 1705:14]
node _T_188 = bits(_T_187, 0, 0) @[el2_dec_tlu_ctl.scala 1705:40]
node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_192 = mux(_T_188, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_193 = or(_T_189, _T_190) @[Mux.scala 27:72]
node _T_194 = or(_T_193, _T_191) @[Mux.scala 27:72]
node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72]
wire mepc_ns : UInt<31> @[Mux.scala 27:72]
mepc_ns <= _T_195 @[Mux.scala 27:72]
reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1707:47]
_T_196 <= mepc_ns @[el2_dec_tlu_ctl.scala 1707:47]
io.mepc <= _T_196 @[el2_dec_tlu_ctl.scala 1707:10]
node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1714:65]
node _T_198 = eq(_T_197, UInt<12>("h0342")) @[el2_dec_tlu_ctl.scala 1714:72]
node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[el2_dec_tlu_ctl.scala 1714:43]
node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1715:53]
node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[el2_dec_tlu_ctl.scala 1715:67]
node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1716:52]
node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[el2_dec_tlu_ctl.scala 1716:66]
node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1717:51]
node _T_202 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1717:84]
node mcause_sel_nmi_ext = and(_T_201, _T_202) @[el2_dec_tlu_ctl.scala 1717:65]
node _T_203 = andr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1723:53]
node _T_204 = bits(io.lsu_fir_error, 1, 1) @[el2_dec_tlu_ctl.scala 1723:76]
node _T_205 = bits(io.lsu_fir_error, 0, 0) @[el2_dec_tlu_ctl.scala 1723:99]
node _T_206 = not(_T_205) @[el2_dec_tlu_ctl.scala 1723:82]
node _T_207 = and(_T_204, _T_206) @[el2_dec_tlu_ctl.scala 1723:80]
node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58]
node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[el2_dec_tlu_ctl.scala 1726:52]
node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[el2_dec_tlu_ctl.scala 1727:51]
node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[el2_dec_tlu_ctl.scala 1728:50]
node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58]
node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58]
node _T_213 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1729:56]
node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[el2_dec_tlu_ctl.scala 1729:54]
node _T_215 = bits(_T_214, 0, 0) @[el2_dec_tlu_ctl.scala 1729:70]
node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58]
node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58]
node _T_218 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1730:46]
node _T_219 = and(wr_mcause_r, _T_218) @[el2_dec_tlu_ctl.scala 1730:44]
node _T_220 = bits(_T_219, 0, 0) @[el2_dec_tlu_ctl.scala 1730:70]
node _T_221 = not(wr_mcause_r) @[el2_dec_tlu_ctl.scala 1731:32]
node _T_222 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1731:47]
node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 1731:45]
node _T_224 = bits(_T_223, 0, 0) @[el2_dec_tlu_ctl.scala 1731:71]
node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_228 = mux(_T_215, _T_217, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_229 = mux(_T_220, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_230 = mux(_T_224, mcause, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_231 = or(_T_225, _T_226) @[Mux.scala 27:72]
node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72]
node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72]
node _T_234 = or(_T_233, _T_229) @[Mux.scala 27:72]
node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72]
wire mcause_ns : UInt<32> @[Mux.scala 27:72]
mcause_ns <= _T_235 @[Mux.scala 27:72]
reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1733:49]
_T_236 <= mcause_ns @[el2_dec_tlu_ctl.scala 1733:49]
mcause <= _T_236 @[el2_dec_tlu_ctl.scala 1733:12]
node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1740:64]
node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[el2_dec_tlu_ctl.scala 1740:71]
node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[el2_dec_tlu_ctl.scala 1740:42]
node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 1742:56]
node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58]
node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[el2_dec_tlu_ctl.scala 1742:24]
node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1745:36]
node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[el2_dec_tlu_ctl.scala 1746:40]
node _T_243 = bits(io.ebreak_r, 0, 0) @[el2_dec_tlu_ctl.scala 1747:32]
node _T_244 = bits(io.inst_acc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1748:34]
node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_248 = mux(_T_244, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_249 = or(_T_245, _T_246) @[Mux.scala 27:72]
node _T_250 = or(_T_249, _T_247) @[Mux.scala 27:72]
node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72]
wire mscause_type : UInt<4> @[Mux.scala 27:72]
mscause_type <= _T_251 @[Mux.scala 27:72]
node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1752:48]
node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:40]
node _T_254 = and(wr_mscause_r, _T_253) @[el2_dec_tlu_ctl.scala 1753:38]
node _T_255 = bits(_T_254, 0, 0) @[el2_dec_tlu_ctl.scala 1753:64]
node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 1753:103]
node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1754:25]
node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1754:41]
node _T_259 = and(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 1754:39]
node _T_260 = bits(_T_259, 0, 0) @[el2_dec_tlu_ctl.scala 1754:65]
node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_264 = or(_T_261, _T_262) @[Mux.scala 27:72]
node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72]
wire mscause_ns : UInt<4> @[Mux.scala 27:72]
mscause_ns <= _T_265 @[Mux.scala 27:72]
reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1756:47]
_T_266 <= mscause_ns @[el2_dec_tlu_ctl.scala 1756:47]
mscause <= _T_266 @[el2_dec_tlu_ctl.scala 1756:10]
node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1763:62]
node _T_268 = eq(_T_267, UInt<12>("h0343")) @[el2_dec_tlu_ctl.scala 1763:69]
node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[el2_dec_tlu_ctl.scala 1763:40]
node _T_269 = not(io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1764:83]
node _T_270 = and(io.inst_acc_r, _T_269) @[el2_dec_tlu_ctl.scala 1764:81]
node _T_271 = or(io.ebreak_r, _T_270) @[el2_dec_tlu_ctl.scala 1764:64]
node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1764:106]
node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[el2_dec_tlu_ctl.scala 1764:49]
node _T_274 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1764:140]
node mtval_capture_pc_r = and(_T_273, _T_274) @[el2_dec_tlu_ctl.scala 1764:138]
node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1765:72]
node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[el2_dec_tlu_ctl.scala 1765:55]
node _T_277 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1765:98]
node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 1765:96]
node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[el2_dec_tlu_ctl.scala 1766:51]
node _T_279 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1766:68]
node mtval_capture_inst_r = and(_T_278, _T_279) @[el2_dec_tlu_ctl.scala 1766:66]
node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1767:50]
node _T_281 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1767:73]
node mtval_capture_lsu_r = and(_T_280, _T_281) @[el2_dec_tlu_ctl.scala 1767:71]
node _T_282 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1768:46]
node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[el2_dec_tlu_ctl.scala 1768:44]
node _T_284 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1768:68]
node _T_285 = and(_T_283, _T_284) @[el2_dec_tlu_ctl.scala 1768:66]
node _T_286 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1768:92]
node _T_287 = and(_T_285, _T_286) @[el2_dec_tlu_ctl.scala 1768:90]
node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1768:115]
node mtval_clear_r = and(_T_287, _T_288) @[el2_dec_tlu_ctl.scala 1768:113]
node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1772:25]
node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[el2_dec_tlu_ctl.scala 1773:31]
node _T_292 = add(pc_r, UInt<31>("h01")) @[el2_dec_tlu_ctl.scala 1773:83]
node _T_293 = tail(_T_292, 1) @[el2_dec_tlu_ctl.scala 1773:83]
node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[el2_dec_tlu_ctl.scala 1774:27]
node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[el2_dec_tlu_ctl.scala 1775:26]
node _T_297 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1776:18]
node _T_298 = and(wr_mtval_r, _T_297) @[el2_dec_tlu_ctl.scala 1776:16]
node _T_299 = bits(_T_298, 0, 0) @[el2_dec_tlu_ctl.scala 1776:48]
node _T_300 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1777:5]
node _T_301 = not(wr_mtval_r) @[el2_dec_tlu_ctl.scala 1777:20]
node _T_302 = and(_T_300, _T_301) @[el2_dec_tlu_ctl.scala 1777:18]
node _T_303 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1777:34]
node _T_304 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 1777:32]
node _T_305 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1777:56]
node _T_306 = and(_T_304, _T_305) @[el2_dec_tlu_ctl.scala 1777:54]
node _T_307 = not(mtval_clear_r) @[el2_dec_tlu_ctl.scala 1777:80]
node _T_308 = and(_T_306, _T_307) @[el2_dec_tlu_ctl.scala 1777:78]
node _T_309 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1777:97]
node _T_310 = and(_T_308, _T_309) @[el2_dec_tlu_ctl.scala 1777:95]
node _T_311 = bits(_T_310, 0, 0) @[el2_dec_tlu_ctl.scala 1777:119]
node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = mux(_T_296, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_316 = mux(_T_299, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_317 = mux(_T_311, mtval, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_318 = or(_T_312, _T_313) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_316) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72]
wire mtval_ns : UInt<32> @[Mux.scala 27:72]
mtval_ns <= _T_322 @[Mux.scala 27:72]
reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1779:46]
_T_323 <= mtval_ns @[el2_dec_tlu_ctl.scala 1779:46]
mtval <= _T_323 @[el2_dec_tlu_ctl.scala 1779:8]
node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1794:61]
node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[el2_dec_tlu_ctl.scala 1794:68]
node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[el2_dec_tlu_ctl.scala 1794:39]
node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[el2_dec_tlu_ctl.scala 1796:39]
node _T_327 = bits(wr_mcgc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1796:55]
inst rvclkhdr_8 of rvclkhdr_16 @[el2_lib.scala 508:23]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_8.io.en <= _T_327 @[el2_lib.scala 511:17]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
mcgc <= _T_326 @[el2_lib.scala 514:16]
node _T_328 = bits(mcgc, 8, 8) @[el2_dec_tlu_ctl.scala 1798:38]
io.dec_tlu_misc_clk_override <= _T_328 @[el2_dec_tlu_ctl.scala 1798:31]
node _T_329 = bits(mcgc, 7, 7) @[el2_dec_tlu_ctl.scala 1799:38]
io.dec_tlu_dec_clk_override <= _T_329 @[el2_dec_tlu_ctl.scala 1799:31]
node _T_330 = bits(mcgc, 5, 5) @[el2_dec_tlu_ctl.scala 1800:38]
io.dec_tlu_ifu_clk_override <= _T_330 @[el2_dec_tlu_ctl.scala 1800:31]
node _T_331 = bits(mcgc, 4, 4) @[el2_dec_tlu_ctl.scala 1801:38]
io.dec_tlu_lsu_clk_override <= _T_331 @[el2_dec_tlu_ctl.scala 1801:31]
node _T_332 = bits(mcgc, 3, 3) @[el2_dec_tlu_ctl.scala 1802:38]
io.dec_tlu_bus_clk_override <= _T_332 @[el2_dec_tlu_ctl.scala 1802:31]
node _T_333 = bits(mcgc, 2, 2) @[el2_dec_tlu_ctl.scala 1803:38]
io.dec_tlu_pic_clk_override <= _T_333 @[el2_dec_tlu_ctl.scala 1803:31]
node _T_334 = bits(mcgc, 1, 1) @[el2_dec_tlu_ctl.scala 1804:38]
io.dec_tlu_dccm_clk_override <= _T_334 @[el2_dec_tlu_ctl.scala 1804:31]
node _T_335 = bits(mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 1805:38]
io.dec_tlu_icm_clk_override <= _T_335 @[el2_dec_tlu_ctl.scala 1805:31]
node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1824:61]
node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[el2_dec_tlu_ctl.scala 1824:68]
node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[el2_dec_tlu_ctl.scala 1824:39]
node _T_338 = bits(wr_mfdc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1828:39]
inst rvclkhdr_9 of rvclkhdr_17 @[el2_lib.scala 508:23]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_9.io.en <= _T_338 @[el2_lib.scala 511:17]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_339 <= mfdc_ns @[el2_lib.scala 514:16]
mfdc_int <= _T_339 @[el2_dec_tlu_ctl.scala 1828:11]
node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[el2_dec_tlu_ctl.scala 1833:40]
node _T_341 = not(_T_340) @[el2_dec_tlu_ctl.scala 1833:20]
node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[el2_dec_tlu_ctl.scala 1833:67]
node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1833:95]
node _T_344 = not(_T_343) @[el2_dec_tlu_ctl.scala 1833:75]
node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1833:119]
node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58]
node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58]
node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58]
mfdc_ns <= _T_348 @[el2_dec_tlu_ctl.scala 1833:13]
node _T_349 = bits(mfdc_int, 14, 12) @[el2_dec_tlu_ctl.scala 1834:29]
node _T_350 = not(_T_349) @[el2_dec_tlu_ctl.scala 1834:20]
node _T_351 = bits(mfdc_int, 11, 7) @[el2_dec_tlu_ctl.scala 1834:55]
node _T_352 = bits(mfdc_int, 6, 6) @[el2_dec_tlu_ctl.scala 1834:72]
node _T_353 = not(_T_352) @[el2_dec_tlu_ctl.scala 1834:63]
node _T_354 = bits(mfdc_int, 5, 0) @[el2_dec_tlu_ctl.scala 1834:85]
node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58]
node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58]
node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58]
node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58]
mfdc <= _T_358 @[el2_dec_tlu_ctl.scala 1834:13]
node _T_359 = bits(mfdc, 18, 16) @[el2_dec_tlu_ctl.scala 1842:46]
io.dec_tlu_dma_qos_prty <= _T_359 @[el2_dec_tlu_ctl.scala 1842:39]
node _T_360 = bits(mfdc, 11, 11) @[el2_dec_tlu_ctl.scala 1843:58]
io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= _T_360 @[el2_dec_tlu_ctl.scala 1843:51]
node _T_361 = bits(mfdc, 8, 8) @[el2_dec_tlu_ctl.scala 1844:46]
io.dec_tlu_core_ecc_disable <= _T_361 @[el2_dec_tlu_ctl.scala 1844:39]
node _T_362 = bits(mfdc, 6, 6) @[el2_dec_tlu_ctl.scala 1845:58]
io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= _T_362 @[el2_dec_tlu_ctl.scala 1845:51]
node _T_363 = bits(mfdc, 3, 3) @[el2_dec_tlu_ctl.scala 1846:46]
io.dec_tlu_bpred_disable <= _T_363 @[el2_dec_tlu_ctl.scala 1846:39]
node _T_364 = bits(mfdc, 2, 2) @[el2_dec_tlu_ctl.scala 1847:58]
io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= _T_364 @[el2_dec_tlu_ctl.scala 1847:51]
node _T_365 = bits(mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 1848:46]
io.dec_tlu_pipelining_disable <= _T_365 @[el2_dec_tlu_ctl.scala 1848:39]
node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1857:70]
node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 1857:77]
node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[el2_dec_tlu_ctl.scala 1857:48]
node _T_369 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1857:89]
node _T_370 = and(_T_368, _T_369) @[el2_dec_tlu_ctl.scala 1857:87]
node _T_371 = not(io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 1857:113]
node _T_372 = and(_T_370, _T_371) @[el2_dec_tlu_ctl.scala 1857:111]
io.dec_tlu_wr_pause_r <= _T_372 @[el2_dec_tlu_ctl.scala 1857:24]
node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1864:61]
node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[el2_dec_tlu_ctl.scala 1864:68]
node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[el2_dec_tlu_ctl.scala 1864:39]
node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1867:39]
node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[el2_dec_tlu_ctl.scala 1867:64]
node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1867:91]
node _T_378 = not(_T_377) @[el2_dec_tlu_ctl.scala 1867:71]
node _T_379 = and(_T_376, _T_378) @[el2_dec_tlu_ctl.scala 1867:69]
node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1868:41]
node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[el2_dec_tlu_ctl.scala 1868:66]
node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1868:93]
node _T_383 = not(_T_382) @[el2_dec_tlu_ctl.scala 1868:73]
node _T_384 = and(_T_381, _T_383) @[el2_dec_tlu_ctl.scala 1868:71]
node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1869:41]
node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[el2_dec_tlu_ctl.scala 1869:66]
node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1869:93]
node _T_388 = not(_T_387) @[el2_dec_tlu_ctl.scala 1869:73]
node _T_389 = and(_T_386, _T_388) @[el2_dec_tlu_ctl.scala 1869:71]
node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1870:41]
node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 1870:66]
node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1870:93]
node _T_393 = not(_T_392) @[el2_dec_tlu_ctl.scala 1870:73]
node _T_394 = and(_T_391, _T_393) @[el2_dec_tlu_ctl.scala 1870:71]
node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1871:41]
node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[el2_dec_tlu_ctl.scala 1871:66]
node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1871:93]
node _T_398 = not(_T_397) @[el2_dec_tlu_ctl.scala 1871:73]
node _T_399 = and(_T_396, _T_398) @[el2_dec_tlu_ctl.scala 1871:71]
node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1872:41]
node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[el2_dec_tlu_ctl.scala 1872:66]
node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1872:93]
node _T_403 = not(_T_402) @[el2_dec_tlu_ctl.scala 1872:73]
node _T_404 = and(_T_401, _T_403) @[el2_dec_tlu_ctl.scala 1872:71]
node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1873:41]
node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[el2_dec_tlu_ctl.scala 1873:66]
node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1873:93]
node _T_408 = not(_T_407) @[el2_dec_tlu_ctl.scala 1873:73]
node _T_409 = and(_T_406, _T_408) @[el2_dec_tlu_ctl.scala 1873:71]
node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1874:41]
node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[el2_dec_tlu_ctl.scala 1874:66]
node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1874:93]
node _T_413 = not(_T_412) @[el2_dec_tlu_ctl.scala 1874:73]
node _T_414 = and(_T_411, _T_413) @[el2_dec_tlu_ctl.scala 1874:71]
node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1875:41]
node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[el2_dec_tlu_ctl.scala 1875:66]
node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1875:93]
node _T_418 = not(_T_417) @[el2_dec_tlu_ctl.scala 1875:73]
node _T_419 = and(_T_416, _T_418) @[el2_dec_tlu_ctl.scala 1875:71]
node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1876:41]
node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 1876:66]
node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1876:93]
node _T_423 = not(_T_422) @[el2_dec_tlu_ctl.scala 1876:73]
node _T_424 = and(_T_421, _T_423) @[el2_dec_tlu_ctl.scala 1876:71]
node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1877:41]
node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[el2_dec_tlu_ctl.scala 1877:66]
node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1877:93]
node _T_428 = not(_T_427) @[el2_dec_tlu_ctl.scala 1877:73]
node _T_429 = and(_T_426, _T_428) @[el2_dec_tlu_ctl.scala 1877:71]
node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1878:41]
node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[el2_dec_tlu_ctl.scala 1878:66]
node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1878:93]
node _T_433 = not(_T_432) @[el2_dec_tlu_ctl.scala 1878:73]
node _T_434 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 1878:70]
node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1879:41]
node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1879:66]
node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1879:93]
node _T_438 = not(_T_437) @[el2_dec_tlu_ctl.scala 1879:73]
node _T_439 = and(_T_436, _T_438) @[el2_dec_tlu_ctl.scala 1879:70]
node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1880:41]
node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[el2_dec_tlu_ctl.scala 1880:66]
node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1880:93]
node _T_443 = not(_T_442) @[el2_dec_tlu_ctl.scala 1880:73]
node _T_444 = and(_T_441, _T_443) @[el2_dec_tlu_ctl.scala 1880:70]
node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1881:41]
node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 1881:66]
node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1881:93]
node _T_448 = not(_T_447) @[el2_dec_tlu_ctl.scala 1881:73]
node _T_449 = and(_T_446, _T_448) @[el2_dec_tlu_ctl.scala 1881:70]
node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1882:41]
node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1882:66]
node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1882:93]
node _T_453 = not(_T_452) @[el2_dec_tlu_ctl.scala 1882:73]
node _T_454 = and(_T_451, _T_453) @[el2_dec_tlu_ctl.scala 1882:70]
node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58]
node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58]
node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58]
node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58]
node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58]
node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58]
node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58]
node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58]
node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58]
node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58]
node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58]
node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58]
node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58]
node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58]
node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58]
node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58]
node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58]
node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58]
node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58]
node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58]
node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58]
node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58]
node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58]
node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58]
node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58]
node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58]
node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58]
node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58]
node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58]
node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58]
node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58]
node _T_485 = bits(wr_mrac_r, 0, 0) @[el2_dec_tlu_ctl.scala 1885:38]
inst rvclkhdr_10 of rvclkhdr_18 @[el2_lib.scala 508:23]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_10.io.en <= _T_485 @[el2_lib.scala 511:17]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
mrac <= mrac_in @[el2_lib.scala 514:16]
io.dec_tlu_mrac_ff <= mrac @[el2_dec_tlu_ctl.scala 1887:21]
node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1895:62]
node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[el2_dec_tlu_ctl.scala 1895:69]
node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[el2_dec_tlu_ctl.scala 1895:40]
node _T_488 = not(wr_mdeau_r) @[el2_dec_tlu_ctl.scala 1905:59]
node _T_489 = and(io.mdseac_locked_f, _T_488) @[el2_dec_tlu_ctl.scala 1905:57]
node _T_490 = or(mdseac_en, _T_489) @[el2_dec_tlu_ctl.scala 1905:35]
io.mdseac_locked_ns <= _T_490 @[el2_dec_tlu_ctl.scala 1905:22]
node _T_491 = or(io.tlu_busbuff.lsu_imprecise_error_store_any, io.tlu_busbuff.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 1907:61]
node _T_492 = not(io.nmi_int_detected_f) @[el2_dec_tlu_ctl.scala 1907:110]
node _T_493 = and(_T_491, _T_492) @[el2_dec_tlu_ctl.scala 1907:108]
node _T_494 = not(io.mdseac_locked_f) @[el2_dec_tlu_ctl.scala 1907:135]
node _T_495 = and(_T_493, _T_494) @[el2_dec_tlu_ctl.scala 1907:133]
mdseac_en <= _T_495 @[el2_dec_tlu_ctl.scala 1907:12]
node _T_496 = bits(mdseac_en, 0, 0) @[el2_dec_tlu_ctl.scala 1909:76]
inst rvclkhdr_11 of rvclkhdr_19 @[el2_lib.scala 508:23]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_11.io.en <= _T_496 @[el2_lib.scala 511:17]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
mdseac <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[el2_lib.scala 514:16]
node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1918:61]
node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[el2_dec_tlu_ctl.scala 1918:68]
node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[el2_dec_tlu_ctl.scala 1918:39]
node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1922:51]
node _T_500 = and(wr_mpmc_r, _T_499) @[el2_dec_tlu_ctl.scala 1922:30]
node _T_501 = not(io.internal_dbg_halt_mode_f2) @[el2_dec_tlu_ctl.scala 1922:57]
node _T_502 = and(_T_500, _T_501) @[el2_dec_tlu_ctl.scala 1922:55]
node _T_503 = not(io.ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 1922:89]
node _T_504 = and(_T_502, _T_503) @[el2_dec_tlu_ctl.scala 1922:87]
io.fw_halt_req <= _T_504 @[el2_dec_tlu_ctl.scala 1922:17]
wire fw_halted_ns : UInt<1>
fw_halted_ns <= UInt<1>("h00")
reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1924:48]
fw_halted <= fw_halted_ns @[el2_dec_tlu_ctl.scala 1924:48]
node _T_505 = or(io.fw_halt_req, fw_halted) @[el2_dec_tlu_ctl.scala 1925:34]
node _T_506 = not(set_mie_pmu_fw_halt) @[el2_dec_tlu_ctl.scala 1925:49]
node _T_507 = and(_T_505, _T_506) @[el2_dec_tlu_ctl.scala 1925:47]
fw_halted_ns <= _T_507 @[el2_dec_tlu_ctl.scala 1925:15]
node _T_508 = bits(wr_mpmc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1926:29]
node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1926:57]
node _T_510 = not(_T_509) @[el2_dec_tlu_ctl.scala 1926:37]
node _T_511 = not(mpmc) @[el2_dec_tlu_ctl.scala 1926:62]
node _T_512 = mux(_T_508, _T_510, _T_511) @[el2_dec_tlu_ctl.scala 1926:18]
mpmc_b_ns <= _T_512 @[el2_dec_tlu_ctl.scala 1926:12]
reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1928:44]
_T_513 <= mpmc_b_ns @[el2_dec_tlu_ctl.scala 1928:44]
mpmc_b <= _T_513 @[el2_dec_tlu_ctl.scala 1928:9]
node _T_514 = not(mpmc_b) @[el2_dec_tlu_ctl.scala 1931:10]
mpmc <= _T_514 @[el2_dec_tlu_ctl.scala 1931:7]
node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1940:40]
node _T_516 = gt(_T_515, UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 1940:48]
node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1940:92]
node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[el2_dec_tlu_ctl.scala 1940:19]
node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1942:63]
node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[el2_dec_tlu_ctl.scala 1942:70]
node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[el2_dec_tlu_ctl.scala 1942:41]
node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58]
node _T_521 = add(micect, _T_520) @[el2_dec_tlu_ctl.scala 1943:23]
node _T_522 = tail(_T_521, 1) @[el2_dec_tlu_ctl.scala 1943:23]
micect_inc <= _T_522 @[el2_dec_tlu_ctl.scala 1943:13]
node _T_523 = bits(wr_micect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1944:35]
node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1944:75]
node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58]
node _T_526 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1944:95]
node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58]
node micect_ns = mux(_T_523, _T_525, _T_527) @[el2_dec_tlu_ctl.scala 1944:22]
node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 1946:42]
node _T_529 = bits(_T_528, 0, 0) @[el2_dec_tlu_ctl.scala 1946:61]
inst rvclkhdr_12 of rvclkhdr_20 @[el2_lib.scala 508:23]
rvclkhdr_12.clock <= clock
rvclkhdr_12.reset <= reset
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_12.io.en <= _T_529 @[el2_lib.scala 511:17]
rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_530 <= micect_ns @[el2_lib.scala 514:16]
micect <= _T_530 @[el2_dec_tlu_ctl.scala 1946:9]
node _T_531 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1948:48]
node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[el2_dec_tlu_ctl.scala 1948:39]
node _T_533 = bits(micect, 26, 0) @[el2_dec_tlu_ctl.scala 1948:79]
node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58]
node _T_535 = and(_T_532, _T_534) @[el2_dec_tlu_ctl.scala 1948:57]
node _T_536 = orr(_T_535) @[el2_dec_tlu_ctl.scala 1948:88]
mice_ce_req <= _T_536 @[el2_dec_tlu_ctl.scala 1948:14]
node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1957:69]
node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[el2_dec_tlu_ctl.scala 1957:76]
node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[el2_dec_tlu_ctl.scala 1957:47]
node _T_539 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1958:26]
node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1958:70]
node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58]
node _T_542 = add(_T_539, _T_541) @[el2_dec_tlu_ctl.scala 1958:33]
node _T_543 = tail(_T_542, 1) @[el2_dec_tlu_ctl.scala 1958:33]
miccmect_inc <= _T_543 @[el2_dec_tlu_ctl.scala 1958:15]
node _T_544 = bits(wr_miccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1959:45]
node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1959:85]
node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58]
node _T_547 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1959:107]
node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58]
node miccmect_ns = mux(_T_544, _T_546, _T_548) @[el2_dec_tlu_ctl.scala 1959:30]
node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 1961:48]
node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1961:69]
node _T_551 = bits(_T_550, 0, 0) @[el2_dec_tlu_ctl.scala 1961:93]
inst rvclkhdr_13 of rvclkhdr_21 @[el2_lib.scala 508:23]
rvclkhdr_13.clock <= clock
rvclkhdr_13.reset <= reset
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_13.io.en <= _T_551 @[el2_lib.scala 511:17]
rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_552 <= miccmect_ns @[el2_lib.scala 514:16]
miccmect <= _T_552 @[el2_dec_tlu_ctl.scala 1961:11]
node _T_553 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1963:51]
node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[el2_dec_tlu_ctl.scala 1963:40]
node _T_555 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1963:84]
node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58]
node _T_557 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 1963:60]
node _T_558 = orr(_T_557) @[el2_dec_tlu_ctl.scala 1963:93]
miccme_ce_req <= _T_558 @[el2_dec_tlu_ctl.scala 1963:15]
node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1972:69]
node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[el2_dec_tlu_ctl.scala 1972:76]
node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[el2_dec_tlu_ctl.scala 1972:47]
node _T_561 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1973:26]
node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
node _T_563 = add(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 1973:33]
node _T_564 = tail(_T_563, 1) @[el2_dec_tlu_ctl.scala 1973:33]
mdccmect_inc <= _T_564 @[el2_dec_tlu_ctl.scala 1973:15]
node _T_565 = bits(wr_mdccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1974:45]
node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1974:85]
node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58]
node _T_568 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1974:107]
node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58]
node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[el2_dec_tlu_ctl.scala 1974:30]
node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[el2_dec_tlu_ctl.scala 1976:49]
node _T_571 = bits(_T_570, 0, 0) @[el2_dec_tlu_ctl.scala 1976:81]
inst rvclkhdr_14 of rvclkhdr_22 @[el2_lib.scala 508:23]
rvclkhdr_14.clock <= clock
rvclkhdr_14.reset <= reset
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_14.io.en <= _T_571 @[el2_lib.scala 511:17]
rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_572 <= mdccmect_ns @[el2_lib.scala 514:16]
mdccmect <= _T_572 @[el2_dec_tlu_ctl.scala 1976:11]
node _T_573 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1978:52]
node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[el2_dec_tlu_ctl.scala 1978:41]
node _T_575 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1978:85]
node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58]
node _T_577 = and(_T_574, _T_576) @[el2_dec_tlu_ctl.scala 1978:61]
node _T_578 = orr(_T_577) @[el2_dec_tlu_ctl.scala 1978:94]
mdccme_ce_req <= _T_578 @[el2_dec_tlu_ctl.scala 1978:16]
node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1988:62]
node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[el2_dec_tlu_ctl.scala 1988:69]
node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[el2_dec_tlu_ctl.scala 1988:40]
node _T_581 = bits(wr_mfdht_r, 0, 0) @[el2_dec_tlu_ctl.scala 1990:32]
node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1990:59]
node mfdht_ns = mux(_T_581, _T_582, mfdht) @[el2_dec_tlu_ctl.scala 1990:20]
reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1992:43]
_T_583 <= mfdht_ns @[el2_dec_tlu_ctl.scala 1992:43]
mfdht <= _T_583 @[el2_dec_tlu_ctl.scala 1992:8]
node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2001:62]
node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[el2_dec_tlu_ctl.scala 2001:69]
node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[el2_dec_tlu_ctl.scala 2001:40]
node _T_586 = bits(wr_mfdhs_r, 0, 0) @[el2_dec_tlu_ctl.scala 2003:32]
node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2003:60]
node _T_588 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2004:43]
node _T_589 = and(io.dbg_tlu_halted, _T_588) @[el2_dec_tlu_ctl.scala 2004:41]
node _T_590 = bits(_T_589, 0, 0) @[el2_dec_tlu_ctl.scala 2004:65]
node _T_591 = not(io.lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 2004:78]
node _T_592 = not(io.ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 2004:98]
node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58]
node _T_594 = mux(_T_590, _T_593, mfdhs) @[el2_dec_tlu_ctl.scala 2004:21]
node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[el2_dec_tlu_ctl.scala 2003:20]
node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2006:71]
node _T_596 = bits(_T_595, 0, 0) @[el2_dec_tlu_ctl.scala 2006:92]
reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_596 : @[Reg.scala 28:19]
_T_597 <= mfdhs_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
mfdhs <= _T_597 @[el2_dec_tlu_ctl.scala 2006:8]
node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[el2_dec_tlu_ctl.scala 2008:47]
node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2008:74]
node _T_600 = tail(_T_599, 1) @[el2_dec_tlu_ctl.scala 2008:74]
node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[el2_dec_tlu_ctl.scala 2009:48]
node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[el2_dec_tlu_ctl.scala 2009:27]
node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[el2_dec_tlu_ctl.scala 2008:26]
node _T_603 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2011:81]
reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_603 : @[Reg.scala 28:19]
_T_604 <= force_halt_ctr @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
force_halt_ctr_f <= _T_604 @[el2_dec_tlu_ctl.scala 2011:19]
node _T_605 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2013:24]
node _T_606 = bits(mfdht, 5, 1) @[el2_dec_tlu_ctl.scala 2013:79]
node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[el2_dec_tlu_ctl.scala 2013:71]
node _T_608 = and(force_halt_ctr_f, _T_607) @[el2_dec_tlu_ctl.scala 2013:48]
node _T_609 = orr(_T_608) @[el2_dec_tlu_ctl.scala 2013:87]
node _T_610 = and(_T_605, _T_609) @[el2_dec_tlu_ctl.scala 2013:28]
io.force_halt <= _T_610 @[el2_dec_tlu_ctl.scala 2013:16]
node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2021:62]
node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[el2_dec_tlu_ctl.scala 2021:69]
node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[el2_dec_tlu_ctl.scala 2021:40]
node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2023:40]
node _T_614 = bits(wr_meivt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2023:59]
inst rvclkhdr_15 of rvclkhdr_23 @[el2_lib.scala 508:23]
rvclkhdr_15.clock <= clock
rvclkhdr_15.reset <= reset
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_15.io.en <= _T_614 @[el2_lib.scala 511:17]
rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
meivt <= _T_613 @[el2_lib.scala 514:16]
node _T_615 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2035:49]
inst rvclkhdr_16 of rvclkhdr_24 @[el2_lib.scala 508:23]
rvclkhdr_16.clock <= clock
rvclkhdr_16.reset <= reset
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_16.io.en <= _T_615 @[el2_lib.scala 511:17]
rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
meihap <= io.pic_claimid @[el2_lib.scala 514:16]
node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58]
io.dec_tlu_meihap <= _T_616 @[el2_dec_tlu_ctl.scala 2036:20]
node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2045:65]
node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[el2_dec_tlu_ctl.scala 2045:72]
node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[el2_dec_tlu_ctl.scala 2045:43]
node _T_619 = bits(wr_meicurpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2046:38]
node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2046:65]
node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[el2_dec_tlu_ctl.scala 2046:23]
reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2048:46]
_T_621 <= meicurpl_ns @[el2_dec_tlu_ctl.scala 2048:46]
meicurpl <= _T_621 @[el2_dec_tlu_ctl.scala 2048:11]
io.dec_tlu_meicurpl <= meicurpl @[el2_dec_tlu_ctl.scala 2050:22]
node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2060:66]
node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[el2_dec_tlu_ctl.scala 2060:73]
node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[el2_dec_tlu_ctl.scala 2060:44]
node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2060:88]
node _T_625 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2062:37]
node _T_626 = bits(wr_meicidpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2063:38]
node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2063:65]
node _T_628 = mux(_T_626, _T_627, meicidpl) @[el2_dec_tlu_ctl.scala 2063:23]
node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[el2_dec_tlu_ctl.scala 2062:23]
reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2065:44]
_T_629 <= meicidpl_ns @[el2_dec_tlu_ctl.scala 2065:44]
meicidpl <= _T_629 @[el2_dec_tlu_ctl.scala 2065:11]
node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2072:62]
node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[el2_dec_tlu_ctl.scala 2072:69]
node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[el2_dec_tlu_ctl.scala 2072:40]
node _T_633 = or(_T_632, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2072:83]
wr_meicpct_r <= _T_633 @[el2_dec_tlu_ctl.scala 2072:15]
node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2081:62]
node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[el2_dec_tlu_ctl.scala 2081:69]
node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[el2_dec_tlu_ctl.scala 2081:40]
node _T_636 = bits(wr_meipt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2082:32]
node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2082:59]
node meipt_ns = mux(_T_636, _T_637, meipt) @[el2_dec_tlu_ctl.scala 2082:20]
reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2084:43]
_T_638 <= meipt_ns @[el2_dec_tlu_ctl.scala 2084:43]
meipt <= _T_638 @[el2_dec_tlu_ctl.scala 2084:8]
io.dec_tlu_meipt <= meipt @[el2_dec_tlu_ctl.scala 2086:19]
node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 2112:89]
node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[el2_dec_tlu_ctl.scala 2112:66]
node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2115:31]
node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[el2_dec_tlu_ctl.scala 2115:29]
node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2115:63]
node _T_643 = and(_T_641, _T_642) @[el2_dec_tlu_ctl.scala 2115:61]
node _T_644 = not(io.debug_halt_req) @[el2_dec_tlu_ctl.scala 2115:98]
node _T_645 = and(_T_643, _T_644) @[el2_dec_tlu_ctl.scala 2115:96]
node _T_646 = bits(_T_645, 0, 0) @[el2_dec_tlu_ctl.scala 2115:118]
node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2116:48]
node _T_648 = and(io.debug_halt_req, _T_647) @[el2_dec_tlu_ctl.scala 2116:46]
node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2116:80]
node _T_650 = and(_T_648, _T_649) @[el2_dec_tlu_ctl.scala 2116:78]
node _T_651 = bits(_T_650, 0, 0) @[el2_dec_tlu_ctl.scala 2116:114]
node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2117:77]
node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[el2_dec_tlu_ctl.scala 2117:75]
node _T_654 = bits(_T_653, 0, 0) @[el2_dec_tlu_ctl.scala 2117:111]
node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[el2_dec_tlu_ctl.scala 2118:108]
node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72]
node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72]
node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72]
wire dcsr_cause : UInt<3> @[Mux.scala 27:72]
dcsr_cause <= _T_662 @[Mux.scala 27:72]
node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2120:46]
node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2120:91]
node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[el2_dec_tlu_ctl.scala 2120:98]
node wr_dcsr_r = and(_T_663, _T_665) @[el2_dec_tlu_ctl.scala 2120:69]
node _T_666 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2126:69]
node _T_667 = eq(_T_666, UInt<3>("h03")) @[el2_dec_tlu_ctl.scala 2126:75]
node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[el2_dec_tlu_ctl.scala 2126:59]
node _T_668 = not(io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2127:59]
node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[el2_dec_tlu_ctl.scala 2127:78]
node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[el2_dec_tlu_ctl.scala 2127:56]
node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[el2_dec_tlu_ctl.scala 2129:48]
node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[el2_dec_tlu_ctl.scala 2130:44]
node _T_671 = bits(io.dcsr, 15, 9) @[el2_dec_tlu_ctl.scala 2130:64]
node _T_672 = bits(io.dcsr, 5, 2) @[el2_dec_tlu_ctl.scala 2130:91]
node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58]
node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58]
node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58]
node _T_676 = bits(wr_dcsr_r, 0, 0) @[el2_dec_tlu_ctl.scala 2131:18]
node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 2131:49]
node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[el2_dec_tlu_ctl.scala 2131:84]
node _T_679 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2131:110]
node _T_680 = bits(io.dcsr, 3, 3) @[el2_dec_tlu_ctl.scala 2131:154]
node _T_681 = or(nmi_in_debug_mode, _T_680) @[el2_dec_tlu_ctl.scala 2131:145]
node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2131:178]
node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58]
node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58]
node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58]
node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58]
node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58]
node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58]
node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58]
node _T_691 = bits(io.dcsr, 15, 4) @[el2_dec_tlu_ctl.scala 2131:211]
node _T_692 = bits(io.dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 2131:245]
node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58]
node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58]
node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58]
node _T_696 = mux(_T_676, _T_690, _T_695) @[el2_dec_tlu_ctl.scala 2131:7]
node dcsr_ns = mux(_T_670, _T_675, _T_696) @[el2_dec_tlu_ctl.scala 2130:19]
node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[el2_dec_tlu_ctl.scala 2133:54]
node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 2133:66]
node _T_699 = or(_T_698, io.take_nmi) @[el2_dec_tlu_ctl.scala 2133:94]
node _T_700 = bits(_T_699, 0, 0) @[el2_dec_tlu_ctl.scala 2133:109]
inst rvclkhdr_17 of rvclkhdr_25 @[el2_lib.scala 508:23]
rvclkhdr_17.clock <= clock
rvclkhdr_17.reset <= reset
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_17.io.en <= _T_700 @[el2_lib.scala 511:17]
rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_701 <= dcsr_ns @[el2_lib.scala 514:16]
io.dcsr <= _T_701 @[el2_dec_tlu_ctl.scala 2133:10]
node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2141:45]
node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2141:90]
node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[el2_dec_tlu_ctl.scala 2141:97]
node wr_dpc_r = and(_T_702, _T_704) @[el2_dec_tlu_ctl.scala 2141:68]
node _T_705 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2142:44]
node _T_706 = and(io.dbg_tlu_halted, _T_705) @[el2_dec_tlu_ctl.scala 2142:42]
node _T_707 = not(io.request_debug_mode_done) @[el2_dec_tlu_ctl.scala 2142:67]
node dpc_capture_npc = and(_T_706, _T_707) @[el2_dec_tlu_ctl.scala 2142:65]
node _T_708 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2146:21]
node _T_709 = not(dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2146:39]
node _T_710 = and(_T_708, _T_709) @[el2_dec_tlu_ctl.scala 2146:37]
node _T_711 = and(_T_710, wr_dpc_r) @[el2_dec_tlu_ctl.scala 2146:56]
node _T_712 = bits(_T_711, 0, 0) @[el2_dec_tlu_ctl.scala 2146:68]
node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 2146:97]
node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[el2_dec_tlu_ctl.scala 2147:68]
node _T_715 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2148:33]
node _T_716 = and(_T_715, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2148:49]
node _T_717 = bits(_T_716, 0, 0) @[el2_dec_tlu_ctl.scala 2148:68]
node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72]
node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72]
wire dpc_ns : UInt<31> @[Mux.scala 27:72]
dpc_ns <= _T_722 @[Mux.scala 27:72]
node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2150:36]
node _T_724 = or(_T_723, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2150:53]
node _T_725 = bits(_T_724, 0, 0) @[el2_dec_tlu_ctl.scala 2150:72]
inst rvclkhdr_18 of rvclkhdr_26 @[el2_lib.scala 508:23]
rvclkhdr_18.clock <= clock
rvclkhdr_18.reset <= reset
rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_18.io.en <= _T_725 @[el2_lib.scala 511:17]
rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_726 <= dpc_ns @[el2_lib.scala 514:16]
io.dpc <= _T_726 @[el2_dec_tlu_ctl.scala 2150:9]
node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 2164:43]
node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[el2_dec_tlu_ctl.scala 2164:68]
node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[el2_dec_tlu_ctl.scala 2164:96]
node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58]
node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58]
node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2165:50]
node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2165:95]
node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[el2_dec_tlu_ctl.scala 2165:102]
node wr_dicawics_r = and(_T_731, _T_733) @[el2_dec_tlu_ctl.scala 2165:73]
node _T_734 = bits(wr_dicawics_r, 0, 0) @[el2_dec_tlu_ctl.scala 2167:50]
inst rvclkhdr_19 of rvclkhdr_27 @[el2_lib.scala 508:23]
rvclkhdr_19.clock <= clock
rvclkhdr_19.reset <= reset
rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_19.io.en <= _T_734 @[el2_lib.scala 511:17]
rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
dicawics <= dicawics_ns @[el2_lib.scala 514:16]
node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2183:48]
node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2183:93]
node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[el2_dec_tlu_ctl.scala 2183:100]
node wr_dicad0_r = and(_T_735, _T_737) @[el2_dec_tlu_ctl.scala 2183:71]
node _T_738 = bits(wr_dicad0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2184:34]
node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[el2_dec_tlu_ctl.scala 2184:21]
node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2186:46]
node _T_740 = bits(_T_739, 0, 0) @[el2_dec_tlu_ctl.scala 2186:79]
inst rvclkhdr_20 of rvclkhdr_28 @[el2_lib.scala 508:23]
rvclkhdr_20.clock <= clock
rvclkhdr_20.reset <= reset
rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_20.io.en <= _T_740 @[el2_lib.scala 511:17]
rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
dicad0 <= dicad0_ns @[el2_lib.scala 514:16]
node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2196:49]
node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2196:94]
node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[el2_dec_tlu_ctl.scala 2196:101]
node wr_dicad0h_r = and(_T_741, _T_743) @[el2_dec_tlu_ctl.scala 2196:72]
node _T_744 = bits(wr_dicad0h_r, 0, 0) @[el2_dec_tlu_ctl.scala 2198:36]
node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[el2_dec_tlu_ctl.scala 2198:88]
node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[el2_dec_tlu_ctl.scala 2198:22]
node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2200:48]
node _T_747 = bits(_T_746, 0, 0) @[el2_dec_tlu_ctl.scala 2200:81]
inst rvclkhdr_21 of rvclkhdr_29 @[el2_lib.scala 508:23]
rvclkhdr_21.clock <= clock
rvclkhdr_21.reset <= reset
rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_21.io.en <= _T_747 @[el2_lib.scala 511:17]
rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
dicad0h <= dicad0h_ns @[el2_lib.scala 514:16]
wire _T_748 : UInt<7>
_T_748 <= UInt<1>("h00")
node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2208:48]
node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2208:93]
node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[el2_dec_tlu_ctl.scala 2208:100]
node _T_752 = and(_T_749, _T_751) @[el2_dec_tlu_ctl.scala 2208:71]
node _T_753 = bits(_T_752, 0, 0) @[el2_dec_tlu_ctl.scala 2210:34]
node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[el2_dec_tlu_ctl.scala 2210:86]
node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[el2_dec_tlu_ctl.scala 2210:21]
node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2212:78]
node _T_757 = bits(_T_756, 0, 0) @[el2_dec_tlu_ctl.scala 2212:111]
reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_757 : @[Reg.scala 28:19]
_T_758 <= _T_755 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_748 <= _T_758 @[el2_dec_tlu_ctl.scala 2212:13]
node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58]
dicad1 <= _T_759 @[el2_dec_tlu_ctl.scala 2213:9]
node _T_760 = bits(dicad1, 6, 0) @[el2_dec_tlu_ctl.scala 2235:77]
node _T_761 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2235:91]
node _T_762 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2235:105]
node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58]
node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58]
io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[el2_dec_tlu_ctl.scala 2235:64]
io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[el2_dec_tlu_ctl.scala 2238:41]
node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 2240:52]
node _T_766 = and(_T_765, io.dec_i0_decode_d) @[el2_dec_tlu_ctl.scala 2240:75]
node _T_767 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 2240:98]
node _T_768 = and(_T_766, _T_767) @[el2_dec_tlu_ctl.scala 2240:96]
node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[el2_dec_tlu_ctl.scala 2240:142]
node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2240:149]
node icache_rd_valid = and(_T_768, _T_770) @[el2_dec_tlu_ctl.scala 2240:120]
node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2241:52]
node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2241:97]
node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2241:104]
node icache_wr_valid = and(_T_771, _T_773) @[el2_dec_tlu_ctl.scala 2241:75]
reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2243:58]
icache_rd_valid_f <= icache_rd_valid @[el2_dec_tlu_ctl.scala 2243:58]
reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2244:58]
icache_wr_valid_f <= icache_wr_valid @[el2_dec_tlu_ctl.scala 2244:58]
io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[el2_dec_tlu_ctl.scala 2246:41]
io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[el2_dec_tlu_ctl.scala 2247:41]
node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2255:62]
node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[el2_dec_tlu_ctl.scala 2255:69]
node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[el2_dec_tlu_ctl.scala 2255:40]
node _T_776 = bits(wr_mtsel_r, 0, 0) @[el2_dec_tlu_ctl.scala 2256:32]
node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2256:59]
node mtsel_ns = mux(_T_776, _T_777, mtsel) @[el2_dec_tlu_ctl.scala 2256:20]
reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2258:43]
_T_778 <= mtsel_ns @[el2_dec_tlu_ctl.scala 2258:43]
mtsel <= _T_778 @[el2_dec_tlu_ctl.scala 2258:8]
node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2293:38]
node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2293:64]
node _T_781 = not(_T_780) @[el2_dec_tlu_ctl.scala 2293:44]
node tdata_load = and(_T_779, _T_781) @[el2_dec_tlu_ctl.scala 2293:42]
node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2295:40]
node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2295:66]
node _T_784 = not(_T_783) @[el2_dec_tlu_ctl.scala 2295:46]
node tdata_opcode = and(_T_782, _T_784) @[el2_dec_tlu_ctl.scala 2295:44]
node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2297:41]
node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2297:46]
node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 2297:90]
node tdata_action = and(_T_786, _T_787) @[el2_dec_tlu_ctl.scala 2297:69]
node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2299:47]
node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2299:52]
node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[el2_dec_tlu_ctl.scala 2299:94]
node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 2299:136]
node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[el2_dec_tlu_ctl.scala 2300:43]
node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 2300:83]
node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58]
node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58]
node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58]
node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58]
node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58]
node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58]
node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58]
node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2303:92]
node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2303:99]
node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[el2_dec_tlu_ctl.scala 2303:70]
node _T_803 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2303:121]
node _T_804 = and(_T_802, _T_803) @[el2_dec_tlu_ctl.scala 2303:112]
node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2303:154]
node _T_806 = not(_T_805) @[el2_dec_tlu_ctl.scala 2303:138]
node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2303:170]
node _T_808 = and(_T_804, _T_807) @[el2_dec_tlu_ctl.scala 2303:135]
node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2303:92]
node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2303:99]
node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[el2_dec_tlu_ctl.scala 2303:70]
node _T_812 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2303:121]
node _T_813 = and(_T_811, _T_812) @[el2_dec_tlu_ctl.scala 2303:112]
node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2303:154]
node _T_815 = not(_T_814) @[el2_dec_tlu_ctl.scala 2303:138]
node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2303:170]
node _T_817 = and(_T_813, _T_816) @[el2_dec_tlu_ctl.scala 2303:135]
node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2303:92]
node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2303:99]
node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[el2_dec_tlu_ctl.scala 2303:70]
node _T_821 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2303:121]
node _T_822 = and(_T_820, _T_821) @[el2_dec_tlu_ctl.scala 2303:112]
node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2303:154]
node _T_824 = not(_T_823) @[el2_dec_tlu_ctl.scala 2303:138]
node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2303:170]
node _T_826 = and(_T_822, _T_825) @[el2_dec_tlu_ctl.scala 2303:135]
node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2303:92]
node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2303:99]
node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[el2_dec_tlu_ctl.scala 2303:70]
node _T_830 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2303:121]
node _T_831 = and(_T_829, _T_830) @[el2_dec_tlu_ctl.scala 2303:112]
node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2303:154]
node _T_833 = not(_T_832) @[el2_dec_tlu_ctl.scala 2303:138]
node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2303:170]
node _T_835 = and(_T_831, _T_834) @[el2_dec_tlu_ctl.scala 2303:135]
wire wr_mtdata1_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2303:42]
wr_mtdata1_t_r[0] <= _T_808 @[el2_dec_tlu_ctl.scala 2303:42]
wr_mtdata1_t_r[1] <= _T_817 @[el2_dec_tlu_ctl.scala 2303:42]
wr_mtdata1_t_r[2] <= _T_826 @[el2_dec_tlu_ctl.scala 2303:42]
wr_mtdata1_t_r[3] <= _T_835 @[el2_dec_tlu_ctl.scala 2303:42]
node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2304:68]
node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2304:111]
node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2304:135]
node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[el2_dec_tlu_ctl.scala 2304:156]
node _T_840 = or(_T_838, _T_839) @[el2_dec_tlu_ctl.scala 2304:139]
node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[el2_dec_tlu_ctl.scala 2304:176]
node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58]
node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58]
node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[el2_dec_tlu_ctl.scala 2304:49]
node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2304:68]
node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2304:111]
node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[el2_dec_tlu_ctl.scala 2304:135]
node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[el2_dec_tlu_ctl.scala 2304:156]
node _T_849 = or(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2304:139]
node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[el2_dec_tlu_ctl.scala 2304:176]
node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58]
node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58]
node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[el2_dec_tlu_ctl.scala 2304:49]
node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2304:68]
node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2304:111]
node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[el2_dec_tlu_ctl.scala 2304:135]
node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[el2_dec_tlu_ctl.scala 2304:156]
node _T_858 = or(_T_856, _T_857) @[el2_dec_tlu_ctl.scala 2304:139]
node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[el2_dec_tlu_ctl.scala 2304:176]
node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58]
node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58]
node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[el2_dec_tlu_ctl.scala 2304:49]
node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2304:68]
node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2304:111]
node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[el2_dec_tlu_ctl.scala 2304:135]
node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[el2_dec_tlu_ctl.scala 2304:156]
node _T_867 = or(_T_865, _T_866) @[el2_dec_tlu_ctl.scala 2304:139]
node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[el2_dec_tlu_ctl.scala 2304:176]
node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58]
node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58]
node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[el2_dec_tlu_ctl.scala 2304:49]
wire mtdata1_t_ns : UInt<10>[4] @[el2_dec_tlu_ctl.scala 2304:40]
mtdata1_t_ns[0] <= _T_844 @[el2_dec_tlu_ctl.scala 2304:40]
mtdata1_t_ns[1] <= _T_853 @[el2_dec_tlu_ctl.scala 2304:40]
mtdata1_t_ns[2] <= _T_862 @[el2_dec_tlu_ctl.scala 2304:40]
mtdata1_t_ns[3] <= _T_871 @[el2_dec_tlu_ctl.scala 2304:40]
reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2306:74]
_T_872 <= mtdata1_t_ns[0] @[el2_dec_tlu_ctl.scala 2306:74]
io.mtdata1_t[0] <= _T_872 @[el2_dec_tlu_ctl.scala 2306:39]
reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2306:74]
_T_873 <= mtdata1_t_ns[1] @[el2_dec_tlu_ctl.scala 2306:74]
io.mtdata1_t[1] <= _T_873 @[el2_dec_tlu_ctl.scala 2306:39]
reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2306:74]
_T_874 <= mtdata1_t_ns[2] @[el2_dec_tlu_ctl.scala 2306:74]
io.mtdata1_t[2] <= _T_874 @[el2_dec_tlu_ctl.scala 2306:39]
reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2306:74]
_T_875 <= mtdata1_t_ns[3] @[el2_dec_tlu_ctl.scala 2306:74]
io.mtdata1_t[3] <= _T_875 @[el2_dec_tlu_ctl.scala 2306:39]
node _T_876 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2309:58]
node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2309:104]
node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[el2_dec_tlu_ctl.scala 2309:142]
node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[el2_dec_tlu_ctl.scala 2309:174]
node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[el2_dec_tlu_ctl.scala 2309:206]
node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[el2_dec_tlu_ctl.scala 2309:238]
node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58]
node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58]
node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58]
node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58]
node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58]
node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58]
node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58]
node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58]
node _T_891 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2309:58]
node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2309:104]
node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[el2_dec_tlu_ctl.scala 2309:142]
node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[el2_dec_tlu_ctl.scala 2309:174]
node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[el2_dec_tlu_ctl.scala 2309:206]
node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[el2_dec_tlu_ctl.scala 2309:238]
node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58]
node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58]
node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58]
node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58]
node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58]
node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58]
node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58]
node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58]
node _T_906 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2309:58]
node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2309:104]
node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[el2_dec_tlu_ctl.scala 2309:142]
node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[el2_dec_tlu_ctl.scala 2309:174]
node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[el2_dec_tlu_ctl.scala 2309:206]
node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[el2_dec_tlu_ctl.scala 2309:238]
node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58]
node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58]
node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58]
node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58]
node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58]
node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58]
node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58]
node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58]
node _T_921 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2309:58]
node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2309:104]
node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[el2_dec_tlu_ctl.scala 2309:142]
node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[el2_dec_tlu_ctl.scala 2309:174]
node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[el2_dec_tlu_ctl.scala 2309:206]
node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[el2_dec_tlu_ctl.scala 2309:238]
node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58]
node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58]
node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58]
node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58]
node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58]
node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58]
node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58]
node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58]
node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72]
node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72]
node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72]
wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72]
mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72]
node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2311:58]
io.trigger_pkt_any[0].select <= _T_943 @[el2_dec_tlu_ctl.scala 2311:40]
node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2312:61]
io.trigger_pkt_any[0].match_pkt <= _T_944 @[el2_dec_tlu_ctl.scala 2312:43]
node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2313:58]
io.trigger_pkt_any[0].store <= _T_945 @[el2_dec_tlu_ctl.scala 2313:40]
node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2314:58]
io.trigger_pkt_any[0].load <= _T_946 @[el2_dec_tlu_ctl.scala 2314:40]
node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 2315:58]
io.trigger_pkt_any[0].execute <= _T_947 @[el2_dec_tlu_ctl.scala 2315:40]
node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 2316:58]
io.trigger_pkt_any[0].m <= _T_948 @[el2_dec_tlu_ctl.scala 2316:40]
node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2311:58]
io.trigger_pkt_any[1].select <= _T_949 @[el2_dec_tlu_ctl.scala 2311:40]
node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2312:61]
io.trigger_pkt_any[1].match_pkt <= _T_950 @[el2_dec_tlu_ctl.scala 2312:43]
node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2313:58]
io.trigger_pkt_any[1].store <= _T_951 @[el2_dec_tlu_ctl.scala 2313:40]
node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2314:58]
io.trigger_pkt_any[1].load <= _T_952 @[el2_dec_tlu_ctl.scala 2314:40]
node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 2315:58]
io.trigger_pkt_any[1].execute <= _T_953 @[el2_dec_tlu_ctl.scala 2315:40]
node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 2316:58]
io.trigger_pkt_any[1].m <= _T_954 @[el2_dec_tlu_ctl.scala 2316:40]
node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2311:58]
io.trigger_pkt_any[2].select <= _T_955 @[el2_dec_tlu_ctl.scala 2311:40]
node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2312:61]
io.trigger_pkt_any[2].match_pkt <= _T_956 @[el2_dec_tlu_ctl.scala 2312:43]
node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2313:58]
io.trigger_pkt_any[2].store <= _T_957 @[el2_dec_tlu_ctl.scala 2313:40]
node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2314:58]
io.trigger_pkt_any[2].load <= _T_958 @[el2_dec_tlu_ctl.scala 2314:40]
node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 2315:58]
io.trigger_pkt_any[2].execute <= _T_959 @[el2_dec_tlu_ctl.scala 2315:40]
node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 2316:58]
io.trigger_pkt_any[2].m <= _T_960 @[el2_dec_tlu_ctl.scala 2316:40]
node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2311:58]
io.trigger_pkt_any[3].select <= _T_961 @[el2_dec_tlu_ctl.scala 2311:40]
node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2312:61]
io.trigger_pkt_any[3].match_pkt <= _T_962 @[el2_dec_tlu_ctl.scala 2312:43]
node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2313:58]
io.trigger_pkt_any[3].store <= _T_963 @[el2_dec_tlu_ctl.scala 2313:40]
node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2314:58]
io.trigger_pkt_any[3].load <= _T_964 @[el2_dec_tlu_ctl.scala 2314:40]
node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 2315:58]
io.trigger_pkt_any[3].execute <= _T_965 @[el2_dec_tlu_ctl.scala 2315:40]
node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 2316:58]
io.trigger_pkt_any[3].m <= _T_966 @[el2_dec_tlu_ctl.scala 2316:40]
node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2323:91]
node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2323:98]
node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[el2_dec_tlu_ctl.scala 2323:69]
node _T_970 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2323:120]
node _T_971 = and(_T_969, _T_970) @[el2_dec_tlu_ctl.scala 2323:111]
node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2323:153]
node _T_973 = not(_T_972) @[el2_dec_tlu_ctl.scala 2323:137]
node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2323:169]
node _T_975 = and(_T_971, _T_974) @[el2_dec_tlu_ctl.scala 2323:134]
node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2323:91]
node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2323:98]
node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[el2_dec_tlu_ctl.scala 2323:69]
node _T_979 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2323:120]
node _T_980 = and(_T_978, _T_979) @[el2_dec_tlu_ctl.scala 2323:111]
node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2323:153]
node _T_982 = not(_T_981) @[el2_dec_tlu_ctl.scala 2323:137]
node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2323:169]
node _T_984 = and(_T_980, _T_983) @[el2_dec_tlu_ctl.scala 2323:134]
node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2323:91]
node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2323:98]
node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[el2_dec_tlu_ctl.scala 2323:69]
node _T_988 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2323:120]
node _T_989 = and(_T_987, _T_988) @[el2_dec_tlu_ctl.scala 2323:111]
node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2323:153]
node _T_991 = not(_T_990) @[el2_dec_tlu_ctl.scala 2323:137]
node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2323:169]
node _T_993 = and(_T_989, _T_992) @[el2_dec_tlu_ctl.scala 2323:134]
node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2323:91]
node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2323:98]
node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[el2_dec_tlu_ctl.scala 2323:69]
node _T_997 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2323:120]
node _T_998 = and(_T_996, _T_997) @[el2_dec_tlu_ctl.scala 2323:111]
node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2323:153]
node _T_1000 = not(_T_999) @[el2_dec_tlu_ctl.scala 2323:137]
node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2323:169]
node _T_1002 = and(_T_998, _T_1001) @[el2_dec_tlu_ctl.scala 2323:134]
wire wr_mtdata2_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2323:42]
wr_mtdata2_t_r[0] <= _T_975 @[el2_dec_tlu_ctl.scala 2323:42]
wr_mtdata2_t_r[1] <= _T_984 @[el2_dec_tlu_ctl.scala 2323:42]
wr_mtdata2_t_r[2] <= _T_993 @[el2_dec_tlu_ctl.scala 2323:42]
wr_mtdata2_t_r[3] <= _T_1002 @[el2_dec_tlu_ctl.scala 2323:42]
node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2324:84]
inst rvclkhdr_22 of rvclkhdr_30 @[el2_lib.scala 508:23]
rvclkhdr_22.clock <= clock
rvclkhdr_22.reset <= reset
rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_22.io.en <= _T_1003 @[el2_lib.scala 511:17]
rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_1004 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
mtdata2_t[0] <= _T_1004 @[el2_dec_tlu_ctl.scala 2324:36]
node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2324:84]
inst rvclkhdr_23 of rvclkhdr_31 @[el2_lib.scala 508:23]
rvclkhdr_23.clock <= clock
rvclkhdr_23.reset <= reset
rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_23.io.en <= _T_1005 @[el2_lib.scala 511:17]
rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_1006 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
mtdata2_t[1] <= _T_1006 @[el2_dec_tlu_ctl.scala 2324:36]
node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2324:84]
inst rvclkhdr_24 of rvclkhdr_32 @[el2_lib.scala 508:23]
rvclkhdr_24.clock <= clock
rvclkhdr_24.reset <= reset
rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_24.io.en <= _T_1007 @[el2_lib.scala 511:17]
rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_1008 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
mtdata2_t[2] <= _T_1008 @[el2_dec_tlu_ctl.scala 2324:36]
node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2324:84]
inst rvclkhdr_25 of rvclkhdr_33 @[el2_lib.scala 508:23]
rvclkhdr_25.clock <= clock
rvclkhdr_25.reset <= reset
rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_25.io.en <= _T_1009 @[el2_lib.scala 511:17]
rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_1010 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16]
mtdata2_t[3] <= _T_1010 @[el2_dec_tlu_ctl.scala 2324:36]
node _T_1011 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2328:57]
node _T_1012 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2328:57]
node _T_1013 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2328:57]
node _T_1014 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2328:57]
node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72]
node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72]
node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72]
wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72]
mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72]
io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[el2_dec_tlu_ctl.scala 2329:51]
io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[el2_dec_tlu_ctl.scala 2329:51]
io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[el2_dec_tlu_ctl.scala 2329:51]
io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[el2_dec_tlu_ctl.scala 2329:51]
mhpme_vec[0] <= mhpme3 @[el2_dec_tlu_ctl.scala 2339:15]
mhpme_vec[1] <= mhpme4 @[el2_dec_tlu_ctl.scala 2340:15]
mhpme_vec[2] <= mhpme5 @[el2_dec_tlu_ctl.scala 2341:15]
mhpme_vec[3] <= mhpme6 @[el2_dec_tlu_ctl.scala 2342:15]
node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[el2_dec_tlu_ctl.scala 2348:59]
wire mhpmc_inc_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2349:24]
wire mhpmc_inc_r_d1 : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2350:27]
node _T_1024 = bits(mcountinhibit, 3, 3) @[el2_dec_tlu_ctl.scala 2354:38]
node _T_1025 = not(_T_1024) @[el2_dec_tlu_ctl.scala 2354:24]
node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2355:34]
node _T_1027 = bits(_T_1026, 0, 0) @[el2_dec_tlu_ctl.scala 2355:62]
node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2356:34]
node _T_1029 = bits(_T_1028, 0, 0) @[el2_dec_tlu_ctl.scala 2356:62]
node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2357:34]
node _T_1031 = bits(_T_1030, 0, 0) @[el2_dec_tlu_ctl.scala 2357:62]
node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2358:34]
node _T_1033 = bits(_T_1032, 0, 0) @[el2_dec_tlu_ctl.scala 2358:62]
node _T_1034 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2358:96]
node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[el2_dec_tlu_ctl.scala 2358:94]
node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2359:34]
node _T_1037 = bits(_T_1036, 0, 0) @[el2_dec_tlu_ctl.scala 2359:62]
node _T_1038 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2359:96]
node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[el2_dec_tlu_ctl.scala 2359:94]
node _T_1040 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2359:117]
node _T_1041 = and(_T_1039, _T_1040) @[el2_dec_tlu_ctl.scala 2359:115]
node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2360:34]
node _T_1043 = bits(_T_1042, 0, 0) @[el2_dec_tlu_ctl.scala 2360:62]
node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2360:94]
node _T_1045 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2360:117]
node _T_1046 = and(_T_1044, _T_1045) @[el2_dec_tlu_ctl.scala 2360:115]
node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2361:34]
node _T_1048 = bits(_T_1047, 0, 0) @[el2_dec_tlu_ctl.scala 2361:62]
node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2362:34]
node _T_1050 = bits(_T_1049, 0, 0) @[el2_dec_tlu_ctl.scala 2362:62]
node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2363:34]
node _T_1052 = bits(_T_1051, 0, 0) @[el2_dec_tlu_ctl.scala 2363:62]
node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2364:34]
node _T_1054 = bits(_T_1053, 0, 0) @[el2_dec_tlu_ctl.scala 2364:62]
node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2364:91]
node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2365:34]
node _T_1057 = bits(_T_1056, 0, 0) @[el2_dec_tlu_ctl.scala 2365:62]
node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2365:105]
node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2366:34]
node _T_1060 = bits(_T_1059, 0, 0) @[el2_dec_tlu_ctl.scala 2366:62]
node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2366:91]
node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2367:34]
node _T_1063 = bits(_T_1062, 0, 0) @[el2_dec_tlu_ctl.scala 2367:62]
node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2367:91]
node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2368:34]
node _T_1066 = bits(_T_1065, 0, 0) @[el2_dec_tlu_ctl.scala 2368:62]
node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2368:91]
node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[el2_dec_tlu_ctl.scala 2368:100]
node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2369:34]
node _T_1070 = bits(_T_1069, 0, 0) @[el2_dec_tlu_ctl.scala 2369:62]
node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2369:91]
node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2369:142]
node _T_1073 = and(_T_1071, _T_1072) @[el2_dec_tlu_ctl.scala 2369:101]
node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2370:34]
node _T_1075 = bits(_T_1074, 0, 0) @[el2_dec_tlu_ctl.scala 2370:59]
node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2370:89]
node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2371:34]
node _T_1078 = bits(_T_1077, 0, 0) @[el2_dec_tlu_ctl.scala 2371:59]
node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2371:89]
node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2372:34]
node _T_1081 = bits(_T_1080, 0, 0) @[el2_dec_tlu_ctl.scala 2372:59]
node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2372:89]
node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2373:34]
node _T_1084 = bits(_T_1083, 0, 0) @[el2_dec_tlu_ctl.scala 2373:59]
node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2373:89]
node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2374:34]
node _T_1087 = bits(_T_1086, 0, 0) @[el2_dec_tlu_ctl.scala 2374:59]
node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2374:89]
node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2375:34]
node _T_1090 = bits(_T_1089, 0, 0) @[el2_dec_tlu_ctl.scala 2375:59]
node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2375:89]
node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2376:34]
node _T_1093 = bits(_T_1092, 0, 0) @[el2_dec_tlu_ctl.scala 2376:59]
node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2376:89]
node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2377:34]
node _T_1096 = bits(_T_1095, 0, 0) @[el2_dec_tlu_ctl.scala 2377:59]
node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2377:89]
node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2378:34]
node _T_1099 = bits(_T_1098, 0, 0) @[el2_dec_tlu_ctl.scala 2378:59]
node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2378:89]
node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2379:34]
node _T_1102 = bits(_T_1101, 0, 0) @[el2_dec_tlu_ctl.scala 2379:59]
node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2379:89]
node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2379:122]
node _T_1105 = or(_T_1103, _T_1104) @[el2_dec_tlu_ctl.scala 2379:101]
node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2380:34]
node _T_1107 = bits(_T_1106, 0, 0) @[el2_dec_tlu_ctl.scala 2380:62]
node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:95]
node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2381:34]
node _T_1110 = bits(_T_1109, 0, 0) @[el2_dec_tlu_ctl.scala 2381:62]
node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2381:97]
node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2382:34]
node _T_1113 = bits(_T_1112, 0, 0) @[el2_dec_tlu_ctl.scala 2382:62]
node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2382:110]
node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2383:34]
node _T_1116 = bits(_T_1115, 0, 0) @[el2_dec_tlu_ctl.scala 2383:62]
node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2384:34]
node _T_1118 = bits(_T_1117, 0, 0) @[el2_dec_tlu_ctl.scala 2384:62]
node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2385:34]
node _T_1120 = bits(_T_1119, 0, 0) @[el2_dec_tlu_ctl.scala 2385:62]
node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2386:34]
node _T_1122 = bits(_T_1121, 0, 0) @[el2_dec_tlu_ctl.scala 2386:62]
node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2387:34]
node _T_1124 = bits(_T_1123, 0, 0) @[el2_dec_tlu_ctl.scala 2387:62]
node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2388:34]
node _T_1126 = bits(_T_1125, 0, 0) @[el2_dec_tlu_ctl.scala 2388:62]
node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2389:34]
node _T_1128 = bits(_T_1127, 0, 0) @[el2_dec_tlu_ctl.scala 2389:62]
node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2390:34]
node _T_1130 = bits(_T_1129, 0, 0) @[el2_dec_tlu_ctl.scala 2390:62]
node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2390:98]
node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2390:120]
node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2391:34]
node _T_1134 = bits(_T_1133, 0, 0) @[el2_dec_tlu_ctl.scala 2391:62]
node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2391:92]
node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2391:117]
node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2392:34]
node _T_1138 = bits(_T_1137, 0, 0) @[el2_dec_tlu_ctl.scala 2392:62]
node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2393:34]
node _T_1140 = bits(_T_1139, 0, 0) @[el2_dec_tlu_ctl.scala 2393:62]
node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2394:34]
node _T_1142 = bits(_T_1141, 0, 0) @[el2_dec_tlu_ctl.scala 2394:62]
node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2394:97]
node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2394:129]
node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2395:34]
node _T_1146 = bits(_T_1145, 0, 0) @[el2_dec_tlu_ctl.scala 2395:62]
node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2396:34]
node _T_1148 = bits(_T_1147, 0, 0) @[el2_dec_tlu_ctl.scala 2396:62]
node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2397:34]
node _T_1150 = bits(_T_1149, 0, 0) @[el2_dec_tlu_ctl.scala 2397:62]
node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2398:34]
node _T_1152 = bits(_T_1151, 0, 0) @[el2_dec_tlu_ctl.scala 2398:62]
node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2399:34]
node _T_1154 = bits(_T_1153, 0, 0) @[el2_dec_tlu_ctl.scala 2399:62]
node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2400:34]
node _T_1156 = bits(_T_1155, 0, 0) @[el2_dec_tlu_ctl.scala 2400:62]
node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2401:34]
node _T_1158 = bits(_T_1157, 0, 0) @[el2_dec_tlu_ctl.scala 2401:62]
node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2402:34]
node _T_1160 = bits(_T_1159, 0, 0) @[el2_dec_tlu_ctl.scala 2402:62]
node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1162 = bits(_T_1161, 0, 0) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1163 = not(_T_1162) @[el2_dec_tlu_ctl.scala 2402:73]
node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2403:34]
node _T_1165 = bits(_T_1164, 0, 0) @[el2_dec_tlu_ctl.scala 2403:62]
node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1167 = bits(_T_1166, 0, 0) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1168 = not(_T_1167) @[el2_dec_tlu_ctl.scala 2403:73]
node _T_1169 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2403:107]
node _T_1170 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2403:118]
node _T_1171 = and(_T_1169, _T_1170) @[el2_dec_tlu_ctl.scala 2403:113]
node _T_1172 = orr(_T_1171) @[el2_dec_tlu_ctl.scala 2403:125]
node _T_1173 = and(_T_1168, _T_1172) @[el2_dec_tlu_ctl.scala 2403:98]
node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2404:34]
node _T_1175 = bits(_T_1174, 0, 0) @[el2_dec_tlu_ctl.scala 2404:62]
node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2404:91]
node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2405:34]
node _T_1178 = bits(_T_1177, 0, 0) @[el2_dec_tlu_ctl.scala 2405:62]
node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2405:94]
node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2406:34]
node _T_1181 = bits(_T_1180, 0, 0) @[el2_dec_tlu_ctl.scala 2406:62]
node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2406:94]
node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2408:34]
node _T_1184 = bits(_T_1183, 0, 0) @[el2_dec_tlu_ctl.scala 2408:62]
node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2409:34]
node _T_1186 = bits(_T_1185, 0, 0) @[el2_dec_tlu_ctl.scala 2409:62]
node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2410:34]
node _T_1188 = bits(_T_1187, 0, 0) @[el2_dec_tlu_ctl.scala 2410:62]
node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2411:34]
node _T_1190 = bits(_T_1189, 0, 0) @[el2_dec_tlu_ctl.scala 2411:62]
node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2412:34]
node _T_1192 = bits(_T_1191, 0, 0) @[el2_dec_tlu_ctl.scala 2412:62]
node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1234 = mux(_T_1148, io.tlu_busbuff.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1235 = mux(_T_1150, io.tlu_busbuff.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1237 = mux(_T_1154, io.tlu_busbuff.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1239 = mux(_T_1158, io.tlu_busbuff.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72]
node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72]
node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72]
node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72]
node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72]
node _T_1255 = or(_T_1254, _T_1199) @[Mux.scala 27:72]
node _T_1256 = or(_T_1255, _T_1200) @[Mux.scala 27:72]
node _T_1257 = or(_T_1256, _T_1201) @[Mux.scala 27:72]
node _T_1258 = or(_T_1257, _T_1202) @[Mux.scala 27:72]
node _T_1259 = or(_T_1258, _T_1203) @[Mux.scala 27:72]
node _T_1260 = or(_T_1259, _T_1204) @[Mux.scala 27:72]
node _T_1261 = or(_T_1260, _T_1205) @[Mux.scala 27:72]
node _T_1262 = or(_T_1261, _T_1206) @[Mux.scala 27:72]
node _T_1263 = or(_T_1262, _T_1207) @[Mux.scala 27:72]
node _T_1264 = or(_T_1263, _T_1208) @[Mux.scala 27:72]
node _T_1265 = or(_T_1264, _T_1209) @[Mux.scala 27:72]
node _T_1266 = or(_T_1265, _T_1210) @[Mux.scala 27:72]
node _T_1267 = or(_T_1266, _T_1211) @[Mux.scala 27:72]
node _T_1268 = or(_T_1267, _T_1212) @[Mux.scala 27:72]
node _T_1269 = or(_T_1268, _T_1213) @[Mux.scala 27:72]
node _T_1270 = or(_T_1269, _T_1214) @[Mux.scala 27:72]
node _T_1271 = or(_T_1270, _T_1215) @[Mux.scala 27:72]
node _T_1272 = or(_T_1271, _T_1216) @[Mux.scala 27:72]
node _T_1273 = or(_T_1272, _T_1217) @[Mux.scala 27:72]
node _T_1274 = or(_T_1273, _T_1218) @[Mux.scala 27:72]
node _T_1275 = or(_T_1274, _T_1219) @[Mux.scala 27:72]
node _T_1276 = or(_T_1275, _T_1220) @[Mux.scala 27:72]
node _T_1277 = or(_T_1276, _T_1221) @[Mux.scala 27:72]
node _T_1278 = or(_T_1277, _T_1222) @[Mux.scala 27:72]
node _T_1279 = or(_T_1278, _T_1223) @[Mux.scala 27:72]
node _T_1280 = or(_T_1279, _T_1224) @[Mux.scala 27:72]
node _T_1281 = or(_T_1280, _T_1225) @[Mux.scala 27:72]
node _T_1282 = or(_T_1281, _T_1226) @[Mux.scala 27:72]
node _T_1283 = or(_T_1282, _T_1227) @[Mux.scala 27:72]
node _T_1284 = or(_T_1283, _T_1228) @[Mux.scala 27:72]
node _T_1285 = or(_T_1284, _T_1229) @[Mux.scala 27:72]
node _T_1286 = or(_T_1285, _T_1230) @[Mux.scala 27:72]
node _T_1287 = or(_T_1286, _T_1231) @[Mux.scala 27:72]
node _T_1288 = or(_T_1287, _T_1232) @[Mux.scala 27:72]
node _T_1289 = or(_T_1288, _T_1233) @[Mux.scala 27:72]
node _T_1290 = or(_T_1289, _T_1234) @[Mux.scala 27:72]
node _T_1291 = or(_T_1290, _T_1235) @[Mux.scala 27:72]
node _T_1292 = or(_T_1291, _T_1236) @[Mux.scala 27:72]
node _T_1293 = or(_T_1292, _T_1237) @[Mux.scala 27:72]
node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72]
node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72]
node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72]
node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72]
node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72]
node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72]
node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72]
node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72]
node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72]
node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72]
node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72]
node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72]
wire _T_1306 : UInt<1> @[Mux.scala 27:72]
_T_1306 <= _T_1305 @[Mux.scala 27:72]
node _T_1307 = and(_T_1025, _T_1306) @[el2_dec_tlu_ctl.scala 2354:44]
mhpmc_inc_r[0] <= _T_1307 @[el2_dec_tlu_ctl.scala 2354:19]
node _T_1308 = bits(mcountinhibit, 4, 4) @[el2_dec_tlu_ctl.scala 2354:38]
node _T_1309 = not(_T_1308) @[el2_dec_tlu_ctl.scala 2354:24]
node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2355:34]
node _T_1311 = bits(_T_1310, 0, 0) @[el2_dec_tlu_ctl.scala 2355:62]
node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2356:34]
node _T_1313 = bits(_T_1312, 0, 0) @[el2_dec_tlu_ctl.scala 2356:62]
node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2357:34]
node _T_1315 = bits(_T_1314, 0, 0) @[el2_dec_tlu_ctl.scala 2357:62]
node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2358:34]
node _T_1317 = bits(_T_1316, 0, 0) @[el2_dec_tlu_ctl.scala 2358:62]
node _T_1318 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2358:96]
node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[el2_dec_tlu_ctl.scala 2358:94]
node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2359:34]
node _T_1321 = bits(_T_1320, 0, 0) @[el2_dec_tlu_ctl.scala 2359:62]
node _T_1322 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2359:96]
node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[el2_dec_tlu_ctl.scala 2359:94]
node _T_1324 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2359:117]
node _T_1325 = and(_T_1323, _T_1324) @[el2_dec_tlu_ctl.scala 2359:115]
node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2360:34]
node _T_1327 = bits(_T_1326, 0, 0) @[el2_dec_tlu_ctl.scala 2360:62]
node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2360:94]
node _T_1329 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2360:117]
node _T_1330 = and(_T_1328, _T_1329) @[el2_dec_tlu_ctl.scala 2360:115]
node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2361:34]
node _T_1332 = bits(_T_1331, 0, 0) @[el2_dec_tlu_ctl.scala 2361:62]
node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2362:34]
node _T_1334 = bits(_T_1333, 0, 0) @[el2_dec_tlu_ctl.scala 2362:62]
node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2363:34]
node _T_1336 = bits(_T_1335, 0, 0) @[el2_dec_tlu_ctl.scala 2363:62]
node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2364:34]
node _T_1338 = bits(_T_1337, 0, 0) @[el2_dec_tlu_ctl.scala 2364:62]
node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2364:91]
node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2365:34]
node _T_1341 = bits(_T_1340, 0, 0) @[el2_dec_tlu_ctl.scala 2365:62]
node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2365:105]
node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2366:34]
node _T_1344 = bits(_T_1343, 0, 0) @[el2_dec_tlu_ctl.scala 2366:62]
node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2366:91]
node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2367:34]
node _T_1347 = bits(_T_1346, 0, 0) @[el2_dec_tlu_ctl.scala 2367:62]
node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2367:91]
node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2368:34]
node _T_1350 = bits(_T_1349, 0, 0) @[el2_dec_tlu_ctl.scala 2368:62]
node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2368:91]
node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[el2_dec_tlu_ctl.scala 2368:100]
node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2369:34]
node _T_1354 = bits(_T_1353, 0, 0) @[el2_dec_tlu_ctl.scala 2369:62]
node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2369:91]
node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2369:142]
node _T_1357 = and(_T_1355, _T_1356) @[el2_dec_tlu_ctl.scala 2369:101]
node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2370:34]
node _T_1359 = bits(_T_1358, 0, 0) @[el2_dec_tlu_ctl.scala 2370:59]
node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2370:89]
node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2371:34]
node _T_1362 = bits(_T_1361, 0, 0) @[el2_dec_tlu_ctl.scala 2371:59]
node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2371:89]
node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2372:34]
node _T_1365 = bits(_T_1364, 0, 0) @[el2_dec_tlu_ctl.scala 2372:59]
node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2372:89]
node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2373:34]
node _T_1368 = bits(_T_1367, 0, 0) @[el2_dec_tlu_ctl.scala 2373:59]
node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2373:89]
node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2374:34]
node _T_1371 = bits(_T_1370, 0, 0) @[el2_dec_tlu_ctl.scala 2374:59]
node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2374:89]
node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2375:34]
node _T_1374 = bits(_T_1373, 0, 0) @[el2_dec_tlu_ctl.scala 2375:59]
node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2375:89]
node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2376:34]
node _T_1377 = bits(_T_1376, 0, 0) @[el2_dec_tlu_ctl.scala 2376:59]
node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2376:89]
node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2377:34]
node _T_1380 = bits(_T_1379, 0, 0) @[el2_dec_tlu_ctl.scala 2377:59]
node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2377:89]
node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2378:34]
node _T_1383 = bits(_T_1382, 0, 0) @[el2_dec_tlu_ctl.scala 2378:59]
node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2378:89]
node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2379:34]
node _T_1386 = bits(_T_1385, 0, 0) @[el2_dec_tlu_ctl.scala 2379:59]
node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2379:89]
node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2379:122]
node _T_1389 = or(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2379:101]
node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2380:34]
node _T_1391 = bits(_T_1390, 0, 0) @[el2_dec_tlu_ctl.scala 2380:62]
node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:95]
node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2381:34]
node _T_1394 = bits(_T_1393, 0, 0) @[el2_dec_tlu_ctl.scala 2381:62]
node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2381:97]
node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2382:34]
node _T_1397 = bits(_T_1396, 0, 0) @[el2_dec_tlu_ctl.scala 2382:62]
node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2382:110]
node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2383:34]
node _T_1400 = bits(_T_1399, 0, 0) @[el2_dec_tlu_ctl.scala 2383:62]
node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2384:34]
node _T_1402 = bits(_T_1401, 0, 0) @[el2_dec_tlu_ctl.scala 2384:62]
node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2385:34]
node _T_1404 = bits(_T_1403, 0, 0) @[el2_dec_tlu_ctl.scala 2385:62]
node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2386:34]
node _T_1406 = bits(_T_1405, 0, 0) @[el2_dec_tlu_ctl.scala 2386:62]
node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2387:34]
node _T_1408 = bits(_T_1407, 0, 0) @[el2_dec_tlu_ctl.scala 2387:62]
node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2388:34]
node _T_1410 = bits(_T_1409, 0, 0) @[el2_dec_tlu_ctl.scala 2388:62]
node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2389:34]
node _T_1412 = bits(_T_1411, 0, 0) @[el2_dec_tlu_ctl.scala 2389:62]
node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2390:34]
node _T_1414 = bits(_T_1413, 0, 0) @[el2_dec_tlu_ctl.scala 2390:62]
node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2390:98]
node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2390:120]
node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2391:34]
node _T_1418 = bits(_T_1417, 0, 0) @[el2_dec_tlu_ctl.scala 2391:62]
node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2391:92]
node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2391:117]
node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2392:34]
node _T_1422 = bits(_T_1421, 0, 0) @[el2_dec_tlu_ctl.scala 2392:62]
node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2393:34]
node _T_1424 = bits(_T_1423, 0, 0) @[el2_dec_tlu_ctl.scala 2393:62]
node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2394:34]
node _T_1426 = bits(_T_1425, 0, 0) @[el2_dec_tlu_ctl.scala 2394:62]
node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2394:97]
node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2394:129]
node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2395:34]
node _T_1430 = bits(_T_1429, 0, 0) @[el2_dec_tlu_ctl.scala 2395:62]
node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2396:34]
node _T_1432 = bits(_T_1431, 0, 0) @[el2_dec_tlu_ctl.scala 2396:62]
node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2397:34]
node _T_1434 = bits(_T_1433, 0, 0) @[el2_dec_tlu_ctl.scala 2397:62]
node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2398:34]
node _T_1436 = bits(_T_1435, 0, 0) @[el2_dec_tlu_ctl.scala 2398:62]
node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2399:34]
node _T_1438 = bits(_T_1437, 0, 0) @[el2_dec_tlu_ctl.scala 2399:62]
node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2400:34]
node _T_1440 = bits(_T_1439, 0, 0) @[el2_dec_tlu_ctl.scala 2400:62]
node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2401:34]
node _T_1442 = bits(_T_1441, 0, 0) @[el2_dec_tlu_ctl.scala 2401:62]
node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2402:34]
node _T_1444 = bits(_T_1443, 0, 0) @[el2_dec_tlu_ctl.scala 2402:62]
node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1446 = bits(_T_1445, 0, 0) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1447 = not(_T_1446) @[el2_dec_tlu_ctl.scala 2402:73]
node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2403:34]
node _T_1449 = bits(_T_1448, 0, 0) @[el2_dec_tlu_ctl.scala 2403:62]
node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1451 = bits(_T_1450, 0, 0) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1452 = not(_T_1451) @[el2_dec_tlu_ctl.scala 2403:73]
node _T_1453 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2403:107]
node _T_1454 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2403:118]
node _T_1455 = and(_T_1453, _T_1454) @[el2_dec_tlu_ctl.scala 2403:113]
node _T_1456 = orr(_T_1455) @[el2_dec_tlu_ctl.scala 2403:125]
node _T_1457 = and(_T_1452, _T_1456) @[el2_dec_tlu_ctl.scala 2403:98]
node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2404:34]
node _T_1459 = bits(_T_1458, 0, 0) @[el2_dec_tlu_ctl.scala 2404:62]
node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2404:91]
node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2405:34]
node _T_1462 = bits(_T_1461, 0, 0) @[el2_dec_tlu_ctl.scala 2405:62]
node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2405:94]
node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2406:34]
node _T_1465 = bits(_T_1464, 0, 0) @[el2_dec_tlu_ctl.scala 2406:62]
node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2406:94]
node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2408:34]
node _T_1468 = bits(_T_1467, 0, 0) @[el2_dec_tlu_ctl.scala 2408:62]
node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2409:34]
node _T_1470 = bits(_T_1469, 0, 0) @[el2_dec_tlu_ctl.scala 2409:62]
node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2410:34]
node _T_1472 = bits(_T_1471, 0, 0) @[el2_dec_tlu_ctl.scala 2410:62]
node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2411:34]
node _T_1474 = bits(_T_1473, 0, 0) @[el2_dec_tlu_ctl.scala 2411:62]
node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2412:34]
node _T_1476 = bits(_T_1475, 0, 0) @[el2_dec_tlu_ctl.scala 2412:62]
node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1518 = mux(_T_1432, io.tlu_busbuff.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1519 = mux(_T_1434, io.tlu_busbuff.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1521 = mux(_T_1438, io.tlu_busbuff.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1523 = mux(_T_1442, io.tlu_busbuff.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72]
node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72]
node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72]
node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72]
node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72]
node _T_1539 = or(_T_1538, _T_1483) @[Mux.scala 27:72]
node _T_1540 = or(_T_1539, _T_1484) @[Mux.scala 27:72]
node _T_1541 = or(_T_1540, _T_1485) @[Mux.scala 27:72]
node _T_1542 = or(_T_1541, _T_1486) @[Mux.scala 27:72]
node _T_1543 = or(_T_1542, _T_1487) @[Mux.scala 27:72]
node _T_1544 = or(_T_1543, _T_1488) @[Mux.scala 27:72]
node _T_1545 = or(_T_1544, _T_1489) @[Mux.scala 27:72]
node _T_1546 = or(_T_1545, _T_1490) @[Mux.scala 27:72]
node _T_1547 = or(_T_1546, _T_1491) @[Mux.scala 27:72]
node _T_1548 = or(_T_1547, _T_1492) @[Mux.scala 27:72]
node _T_1549 = or(_T_1548, _T_1493) @[Mux.scala 27:72]
node _T_1550 = or(_T_1549, _T_1494) @[Mux.scala 27:72]
node _T_1551 = or(_T_1550, _T_1495) @[Mux.scala 27:72]
node _T_1552 = or(_T_1551, _T_1496) @[Mux.scala 27:72]
node _T_1553 = or(_T_1552, _T_1497) @[Mux.scala 27:72]
node _T_1554 = or(_T_1553, _T_1498) @[Mux.scala 27:72]
node _T_1555 = or(_T_1554, _T_1499) @[Mux.scala 27:72]
node _T_1556 = or(_T_1555, _T_1500) @[Mux.scala 27:72]
node _T_1557 = or(_T_1556, _T_1501) @[Mux.scala 27:72]
node _T_1558 = or(_T_1557, _T_1502) @[Mux.scala 27:72]
node _T_1559 = or(_T_1558, _T_1503) @[Mux.scala 27:72]
node _T_1560 = or(_T_1559, _T_1504) @[Mux.scala 27:72]
node _T_1561 = or(_T_1560, _T_1505) @[Mux.scala 27:72]
node _T_1562 = or(_T_1561, _T_1506) @[Mux.scala 27:72]
node _T_1563 = or(_T_1562, _T_1507) @[Mux.scala 27:72]
node _T_1564 = or(_T_1563, _T_1508) @[Mux.scala 27:72]
node _T_1565 = or(_T_1564, _T_1509) @[Mux.scala 27:72]
node _T_1566 = or(_T_1565, _T_1510) @[Mux.scala 27:72]
node _T_1567 = or(_T_1566, _T_1511) @[Mux.scala 27:72]
node _T_1568 = or(_T_1567, _T_1512) @[Mux.scala 27:72]
node _T_1569 = or(_T_1568, _T_1513) @[Mux.scala 27:72]
node _T_1570 = or(_T_1569, _T_1514) @[Mux.scala 27:72]
node _T_1571 = or(_T_1570, _T_1515) @[Mux.scala 27:72]
node _T_1572 = or(_T_1571, _T_1516) @[Mux.scala 27:72]
node _T_1573 = or(_T_1572, _T_1517) @[Mux.scala 27:72]
node _T_1574 = or(_T_1573, _T_1518) @[Mux.scala 27:72]
node _T_1575 = or(_T_1574, _T_1519) @[Mux.scala 27:72]
node _T_1576 = or(_T_1575, _T_1520) @[Mux.scala 27:72]
node _T_1577 = or(_T_1576, _T_1521) @[Mux.scala 27:72]
node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72]
node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72]
node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72]
node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72]
node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72]
node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72]
node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72]
node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72]
node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72]
node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72]
node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72]
node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72]
wire _T_1590 : UInt<1> @[Mux.scala 27:72]
_T_1590 <= _T_1589 @[Mux.scala 27:72]
node _T_1591 = and(_T_1309, _T_1590) @[el2_dec_tlu_ctl.scala 2354:44]
mhpmc_inc_r[1] <= _T_1591 @[el2_dec_tlu_ctl.scala 2354:19]
node _T_1592 = bits(mcountinhibit, 5, 5) @[el2_dec_tlu_ctl.scala 2354:38]
node _T_1593 = not(_T_1592) @[el2_dec_tlu_ctl.scala 2354:24]
node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2355:34]
node _T_1595 = bits(_T_1594, 0, 0) @[el2_dec_tlu_ctl.scala 2355:62]
node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2356:34]
node _T_1597 = bits(_T_1596, 0, 0) @[el2_dec_tlu_ctl.scala 2356:62]
node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2357:34]
node _T_1599 = bits(_T_1598, 0, 0) @[el2_dec_tlu_ctl.scala 2357:62]
node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2358:34]
node _T_1601 = bits(_T_1600, 0, 0) @[el2_dec_tlu_ctl.scala 2358:62]
node _T_1602 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2358:96]
node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[el2_dec_tlu_ctl.scala 2358:94]
node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2359:34]
node _T_1605 = bits(_T_1604, 0, 0) @[el2_dec_tlu_ctl.scala 2359:62]
node _T_1606 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2359:96]
node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[el2_dec_tlu_ctl.scala 2359:94]
node _T_1608 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2359:117]
node _T_1609 = and(_T_1607, _T_1608) @[el2_dec_tlu_ctl.scala 2359:115]
node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2360:34]
node _T_1611 = bits(_T_1610, 0, 0) @[el2_dec_tlu_ctl.scala 2360:62]
node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2360:94]
node _T_1613 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2360:117]
node _T_1614 = and(_T_1612, _T_1613) @[el2_dec_tlu_ctl.scala 2360:115]
node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2361:34]
node _T_1616 = bits(_T_1615, 0, 0) @[el2_dec_tlu_ctl.scala 2361:62]
node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2362:34]
node _T_1618 = bits(_T_1617, 0, 0) @[el2_dec_tlu_ctl.scala 2362:62]
node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2363:34]
node _T_1620 = bits(_T_1619, 0, 0) @[el2_dec_tlu_ctl.scala 2363:62]
node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2364:34]
node _T_1622 = bits(_T_1621, 0, 0) @[el2_dec_tlu_ctl.scala 2364:62]
node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2364:91]
node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2365:34]
node _T_1625 = bits(_T_1624, 0, 0) @[el2_dec_tlu_ctl.scala 2365:62]
node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2365:105]
node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2366:34]
node _T_1628 = bits(_T_1627, 0, 0) @[el2_dec_tlu_ctl.scala 2366:62]
node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2366:91]
node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2367:34]
node _T_1631 = bits(_T_1630, 0, 0) @[el2_dec_tlu_ctl.scala 2367:62]
node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2367:91]
node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2368:34]
node _T_1634 = bits(_T_1633, 0, 0) @[el2_dec_tlu_ctl.scala 2368:62]
node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2368:91]
node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[el2_dec_tlu_ctl.scala 2368:100]
node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2369:34]
node _T_1638 = bits(_T_1637, 0, 0) @[el2_dec_tlu_ctl.scala 2369:62]
node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2369:91]
node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2369:142]
node _T_1641 = and(_T_1639, _T_1640) @[el2_dec_tlu_ctl.scala 2369:101]
node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2370:34]
node _T_1643 = bits(_T_1642, 0, 0) @[el2_dec_tlu_ctl.scala 2370:59]
node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2370:89]
node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2371:34]
node _T_1646 = bits(_T_1645, 0, 0) @[el2_dec_tlu_ctl.scala 2371:59]
node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2371:89]
node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2372:34]
node _T_1649 = bits(_T_1648, 0, 0) @[el2_dec_tlu_ctl.scala 2372:59]
node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2372:89]
node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2373:34]
node _T_1652 = bits(_T_1651, 0, 0) @[el2_dec_tlu_ctl.scala 2373:59]
node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2373:89]
node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2374:34]
node _T_1655 = bits(_T_1654, 0, 0) @[el2_dec_tlu_ctl.scala 2374:59]
node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2374:89]
node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2375:34]
node _T_1658 = bits(_T_1657, 0, 0) @[el2_dec_tlu_ctl.scala 2375:59]
node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2375:89]
node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2376:34]
node _T_1661 = bits(_T_1660, 0, 0) @[el2_dec_tlu_ctl.scala 2376:59]
node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2376:89]
node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2377:34]
node _T_1664 = bits(_T_1663, 0, 0) @[el2_dec_tlu_ctl.scala 2377:59]
node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2377:89]
node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2378:34]
node _T_1667 = bits(_T_1666, 0, 0) @[el2_dec_tlu_ctl.scala 2378:59]
node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2378:89]
node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2379:34]
node _T_1670 = bits(_T_1669, 0, 0) @[el2_dec_tlu_ctl.scala 2379:59]
node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2379:89]
node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2379:122]
node _T_1673 = or(_T_1671, _T_1672) @[el2_dec_tlu_ctl.scala 2379:101]
node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2380:34]
node _T_1675 = bits(_T_1674, 0, 0) @[el2_dec_tlu_ctl.scala 2380:62]
node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:95]
node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2381:34]
node _T_1678 = bits(_T_1677, 0, 0) @[el2_dec_tlu_ctl.scala 2381:62]
node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2381:97]
node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2382:34]
node _T_1681 = bits(_T_1680, 0, 0) @[el2_dec_tlu_ctl.scala 2382:62]
node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2382:110]
node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2383:34]
node _T_1684 = bits(_T_1683, 0, 0) @[el2_dec_tlu_ctl.scala 2383:62]
node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2384:34]
node _T_1686 = bits(_T_1685, 0, 0) @[el2_dec_tlu_ctl.scala 2384:62]
node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2385:34]
node _T_1688 = bits(_T_1687, 0, 0) @[el2_dec_tlu_ctl.scala 2385:62]
node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2386:34]
node _T_1690 = bits(_T_1689, 0, 0) @[el2_dec_tlu_ctl.scala 2386:62]
node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2387:34]
node _T_1692 = bits(_T_1691, 0, 0) @[el2_dec_tlu_ctl.scala 2387:62]
node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2388:34]
node _T_1694 = bits(_T_1693, 0, 0) @[el2_dec_tlu_ctl.scala 2388:62]
node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2389:34]
node _T_1696 = bits(_T_1695, 0, 0) @[el2_dec_tlu_ctl.scala 2389:62]
node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2390:34]
node _T_1698 = bits(_T_1697, 0, 0) @[el2_dec_tlu_ctl.scala 2390:62]
node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2390:98]
node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2390:120]
node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2391:34]
node _T_1702 = bits(_T_1701, 0, 0) @[el2_dec_tlu_ctl.scala 2391:62]
node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2391:92]
node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2391:117]
node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2392:34]
node _T_1706 = bits(_T_1705, 0, 0) @[el2_dec_tlu_ctl.scala 2392:62]
node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2393:34]
node _T_1708 = bits(_T_1707, 0, 0) @[el2_dec_tlu_ctl.scala 2393:62]
node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2394:34]
node _T_1710 = bits(_T_1709, 0, 0) @[el2_dec_tlu_ctl.scala 2394:62]
node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2394:97]
node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2394:129]
node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2395:34]
node _T_1714 = bits(_T_1713, 0, 0) @[el2_dec_tlu_ctl.scala 2395:62]
node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2396:34]
node _T_1716 = bits(_T_1715, 0, 0) @[el2_dec_tlu_ctl.scala 2396:62]
node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2397:34]
node _T_1718 = bits(_T_1717, 0, 0) @[el2_dec_tlu_ctl.scala 2397:62]
node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2398:34]
node _T_1720 = bits(_T_1719, 0, 0) @[el2_dec_tlu_ctl.scala 2398:62]
node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2399:34]
node _T_1722 = bits(_T_1721, 0, 0) @[el2_dec_tlu_ctl.scala 2399:62]
node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2400:34]
node _T_1724 = bits(_T_1723, 0, 0) @[el2_dec_tlu_ctl.scala 2400:62]
node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2401:34]
node _T_1726 = bits(_T_1725, 0, 0) @[el2_dec_tlu_ctl.scala 2401:62]
node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2402:34]
node _T_1728 = bits(_T_1727, 0, 0) @[el2_dec_tlu_ctl.scala 2402:62]
node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1730 = bits(_T_1729, 0, 0) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_1731 = not(_T_1730) @[el2_dec_tlu_ctl.scala 2402:73]
node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2403:34]
node _T_1733 = bits(_T_1732, 0, 0) @[el2_dec_tlu_ctl.scala 2403:62]
node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1735 = bits(_T_1734, 0, 0) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_1736 = not(_T_1735) @[el2_dec_tlu_ctl.scala 2403:73]
node _T_1737 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2403:107]
node _T_1738 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2403:118]
node _T_1739 = and(_T_1737, _T_1738) @[el2_dec_tlu_ctl.scala 2403:113]
node _T_1740 = orr(_T_1739) @[el2_dec_tlu_ctl.scala 2403:125]
node _T_1741 = and(_T_1736, _T_1740) @[el2_dec_tlu_ctl.scala 2403:98]
node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2404:34]
node _T_1743 = bits(_T_1742, 0, 0) @[el2_dec_tlu_ctl.scala 2404:62]
node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2404:91]
node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2405:34]
node _T_1746 = bits(_T_1745, 0, 0) @[el2_dec_tlu_ctl.scala 2405:62]
node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2405:94]
node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2406:34]
node _T_1749 = bits(_T_1748, 0, 0) @[el2_dec_tlu_ctl.scala 2406:62]
node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2406:94]
node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2408:34]
node _T_1752 = bits(_T_1751, 0, 0) @[el2_dec_tlu_ctl.scala 2408:62]
node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2409:34]
node _T_1754 = bits(_T_1753, 0, 0) @[el2_dec_tlu_ctl.scala 2409:62]
node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2410:34]
node _T_1756 = bits(_T_1755, 0, 0) @[el2_dec_tlu_ctl.scala 2410:62]
node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2411:34]
node _T_1758 = bits(_T_1757, 0, 0) @[el2_dec_tlu_ctl.scala 2411:62]
node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2412:34]
node _T_1760 = bits(_T_1759, 0, 0) @[el2_dec_tlu_ctl.scala 2412:62]
node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1802 = mux(_T_1716, io.tlu_busbuff.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1803 = mux(_T_1718, io.tlu_busbuff.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1805 = mux(_T_1722, io.tlu_busbuff.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1807 = mux(_T_1726, io.tlu_busbuff.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72]
node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72]
node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72]
node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72]
node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72]
node _T_1823 = or(_T_1822, _T_1767) @[Mux.scala 27:72]
node _T_1824 = or(_T_1823, _T_1768) @[Mux.scala 27:72]
node _T_1825 = or(_T_1824, _T_1769) @[Mux.scala 27:72]
node _T_1826 = or(_T_1825, _T_1770) @[Mux.scala 27:72]
node _T_1827 = or(_T_1826, _T_1771) @[Mux.scala 27:72]
node _T_1828 = or(_T_1827, _T_1772) @[Mux.scala 27:72]
node _T_1829 = or(_T_1828, _T_1773) @[Mux.scala 27:72]
node _T_1830 = or(_T_1829, _T_1774) @[Mux.scala 27:72]
node _T_1831 = or(_T_1830, _T_1775) @[Mux.scala 27:72]
node _T_1832 = or(_T_1831, _T_1776) @[Mux.scala 27:72]
node _T_1833 = or(_T_1832, _T_1777) @[Mux.scala 27:72]
node _T_1834 = or(_T_1833, _T_1778) @[Mux.scala 27:72]
node _T_1835 = or(_T_1834, _T_1779) @[Mux.scala 27:72]
node _T_1836 = or(_T_1835, _T_1780) @[Mux.scala 27:72]
node _T_1837 = or(_T_1836, _T_1781) @[Mux.scala 27:72]
node _T_1838 = or(_T_1837, _T_1782) @[Mux.scala 27:72]
node _T_1839 = or(_T_1838, _T_1783) @[Mux.scala 27:72]
node _T_1840 = or(_T_1839, _T_1784) @[Mux.scala 27:72]
node _T_1841 = or(_T_1840, _T_1785) @[Mux.scala 27:72]
node _T_1842 = or(_T_1841, _T_1786) @[Mux.scala 27:72]
node _T_1843 = or(_T_1842, _T_1787) @[Mux.scala 27:72]
node _T_1844 = or(_T_1843, _T_1788) @[Mux.scala 27:72]
node _T_1845 = or(_T_1844, _T_1789) @[Mux.scala 27:72]
node _T_1846 = or(_T_1845, _T_1790) @[Mux.scala 27:72]
node _T_1847 = or(_T_1846, _T_1791) @[Mux.scala 27:72]
node _T_1848 = or(_T_1847, _T_1792) @[Mux.scala 27:72]
node _T_1849 = or(_T_1848, _T_1793) @[Mux.scala 27:72]
node _T_1850 = or(_T_1849, _T_1794) @[Mux.scala 27:72]
node _T_1851 = or(_T_1850, _T_1795) @[Mux.scala 27:72]
node _T_1852 = or(_T_1851, _T_1796) @[Mux.scala 27:72]
node _T_1853 = or(_T_1852, _T_1797) @[Mux.scala 27:72]
node _T_1854 = or(_T_1853, _T_1798) @[Mux.scala 27:72]
node _T_1855 = or(_T_1854, _T_1799) @[Mux.scala 27:72]
node _T_1856 = or(_T_1855, _T_1800) @[Mux.scala 27:72]
node _T_1857 = or(_T_1856, _T_1801) @[Mux.scala 27:72]
node _T_1858 = or(_T_1857, _T_1802) @[Mux.scala 27:72]
node _T_1859 = or(_T_1858, _T_1803) @[Mux.scala 27:72]
node _T_1860 = or(_T_1859, _T_1804) @[Mux.scala 27:72]
node _T_1861 = or(_T_1860, _T_1805) @[Mux.scala 27:72]
node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72]
node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72]
node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72]
node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72]
node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72]
node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72]
node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72]
node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72]
node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72]
node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72]
node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72]
node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72]
wire _T_1874 : UInt<1> @[Mux.scala 27:72]
_T_1874 <= _T_1873 @[Mux.scala 27:72]
node _T_1875 = and(_T_1593, _T_1874) @[el2_dec_tlu_ctl.scala 2354:44]
mhpmc_inc_r[2] <= _T_1875 @[el2_dec_tlu_ctl.scala 2354:19]
node _T_1876 = bits(mcountinhibit, 6, 6) @[el2_dec_tlu_ctl.scala 2354:38]
node _T_1877 = not(_T_1876) @[el2_dec_tlu_ctl.scala 2354:24]
node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2355:34]
node _T_1879 = bits(_T_1878, 0, 0) @[el2_dec_tlu_ctl.scala 2355:62]
node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2356:34]
node _T_1881 = bits(_T_1880, 0, 0) @[el2_dec_tlu_ctl.scala 2356:62]
node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2357:34]
node _T_1883 = bits(_T_1882, 0, 0) @[el2_dec_tlu_ctl.scala 2357:62]
node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2358:34]
node _T_1885 = bits(_T_1884, 0, 0) @[el2_dec_tlu_ctl.scala 2358:62]
node _T_1886 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2358:96]
node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[el2_dec_tlu_ctl.scala 2358:94]
node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2359:34]
node _T_1889 = bits(_T_1888, 0, 0) @[el2_dec_tlu_ctl.scala 2359:62]
node _T_1890 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2359:96]
node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[el2_dec_tlu_ctl.scala 2359:94]
node _T_1892 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2359:117]
node _T_1893 = and(_T_1891, _T_1892) @[el2_dec_tlu_ctl.scala 2359:115]
node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2360:34]
node _T_1895 = bits(_T_1894, 0, 0) @[el2_dec_tlu_ctl.scala 2360:62]
node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2360:94]
node _T_1897 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2360:117]
node _T_1898 = and(_T_1896, _T_1897) @[el2_dec_tlu_ctl.scala 2360:115]
node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2361:34]
node _T_1900 = bits(_T_1899, 0, 0) @[el2_dec_tlu_ctl.scala 2361:62]
node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2362:34]
node _T_1902 = bits(_T_1901, 0, 0) @[el2_dec_tlu_ctl.scala 2362:62]
node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2363:34]
node _T_1904 = bits(_T_1903, 0, 0) @[el2_dec_tlu_ctl.scala 2363:62]
node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2364:34]
node _T_1906 = bits(_T_1905, 0, 0) @[el2_dec_tlu_ctl.scala 2364:62]
node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2364:91]
node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2365:34]
node _T_1909 = bits(_T_1908, 0, 0) @[el2_dec_tlu_ctl.scala 2365:62]
node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2365:105]
node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2366:34]
node _T_1912 = bits(_T_1911, 0, 0) @[el2_dec_tlu_ctl.scala 2366:62]
node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2366:91]
node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2367:34]
node _T_1915 = bits(_T_1914, 0, 0) @[el2_dec_tlu_ctl.scala 2367:62]
node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2367:91]
node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2368:34]
node _T_1918 = bits(_T_1917, 0, 0) @[el2_dec_tlu_ctl.scala 2368:62]
node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2368:91]
node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[el2_dec_tlu_ctl.scala 2368:100]
node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2369:34]
node _T_1922 = bits(_T_1921, 0, 0) @[el2_dec_tlu_ctl.scala 2369:62]
node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2369:91]
node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2369:142]
node _T_1925 = and(_T_1923, _T_1924) @[el2_dec_tlu_ctl.scala 2369:101]
node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2370:34]
node _T_1927 = bits(_T_1926, 0, 0) @[el2_dec_tlu_ctl.scala 2370:59]
node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2370:89]
node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2371:34]
node _T_1930 = bits(_T_1929, 0, 0) @[el2_dec_tlu_ctl.scala 2371:59]
node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2371:89]
node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2372:34]
node _T_1933 = bits(_T_1932, 0, 0) @[el2_dec_tlu_ctl.scala 2372:59]
node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2372:89]
node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2373:34]
node _T_1936 = bits(_T_1935, 0, 0) @[el2_dec_tlu_ctl.scala 2373:59]
node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2373:89]
node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2374:34]
node _T_1939 = bits(_T_1938, 0, 0) @[el2_dec_tlu_ctl.scala 2374:59]
node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2374:89]
node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2375:34]
node _T_1942 = bits(_T_1941, 0, 0) @[el2_dec_tlu_ctl.scala 2375:59]
node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2375:89]
node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2376:34]
node _T_1945 = bits(_T_1944, 0, 0) @[el2_dec_tlu_ctl.scala 2376:59]
node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2376:89]
node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2377:34]
node _T_1948 = bits(_T_1947, 0, 0) @[el2_dec_tlu_ctl.scala 2377:59]
node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2377:89]
node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2378:34]
node _T_1951 = bits(_T_1950, 0, 0) @[el2_dec_tlu_ctl.scala 2378:59]
node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2378:89]
node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2379:34]
node _T_1954 = bits(_T_1953, 0, 0) @[el2_dec_tlu_ctl.scala 2379:59]
node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2379:89]
node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2379:122]
node _T_1957 = or(_T_1955, _T_1956) @[el2_dec_tlu_ctl.scala 2379:101]
node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2380:34]
node _T_1959 = bits(_T_1958, 0, 0) @[el2_dec_tlu_ctl.scala 2380:62]
node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:95]
node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2381:34]
node _T_1962 = bits(_T_1961, 0, 0) @[el2_dec_tlu_ctl.scala 2381:62]
node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2381:97]
node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2382:34]
node _T_1965 = bits(_T_1964, 0, 0) @[el2_dec_tlu_ctl.scala 2382:62]
node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2382:110]
node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2383:34]
node _T_1968 = bits(_T_1967, 0, 0) @[el2_dec_tlu_ctl.scala 2383:62]
node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2384:34]
node _T_1970 = bits(_T_1969, 0, 0) @[el2_dec_tlu_ctl.scala 2384:62]
node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2385:34]
node _T_1972 = bits(_T_1971, 0, 0) @[el2_dec_tlu_ctl.scala 2385:62]
node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2386:34]
node _T_1974 = bits(_T_1973, 0, 0) @[el2_dec_tlu_ctl.scala 2386:62]
node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2387:34]
node _T_1976 = bits(_T_1975, 0, 0) @[el2_dec_tlu_ctl.scala 2387:62]
node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2388:34]
node _T_1978 = bits(_T_1977, 0, 0) @[el2_dec_tlu_ctl.scala 2388:62]
node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2389:34]
node _T_1980 = bits(_T_1979, 0, 0) @[el2_dec_tlu_ctl.scala 2389:62]
node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2390:34]
node _T_1982 = bits(_T_1981, 0, 0) @[el2_dec_tlu_ctl.scala 2390:62]
node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2390:98]
node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2390:120]
node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2391:34]
node _T_1986 = bits(_T_1985, 0, 0) @[el2_dec_tlu_ctl.scala 2391:62]
node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2391:92]
node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2391:117]
node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2392:34]
node _T_1990 = bits(_T_1989, 0, 0) @[el2_dec_tlu_ctl.scala 2392:62]
node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2393:34]
node _T_1992 = bits(_T_1991, 0, 0) @[el2_dec_tlu_ctl.scala 2393:62]
node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2394:34]
node _T_1994 = bits(_T_1993, 0, 0) @[el2_dec_tlu_ctl.scala 2394:62]
node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2394:97]
node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2394:129]
node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2395:34]
node _T_1998 = bits(_T_1997, 0, 0) @[el2_dec_tlu_ctl.scala 2395:62]
node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2396:34]
node _T_2000 = bits(_T_1999, 0, 0) @[el2_dec_tlu_ctl.scala 2396:62]
node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2397:34]
node _T_2002 = bits(_T_2001, 0, 0) @[el2_dec_tlu_ctl.scala 2397:62]
node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2398:34]
node _T_2004 = bits(_T_2003, 0, 0) @[el2_dec_tlu_ctl.scala 2398:62]
node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2399:34]
node _T_2006 = bits(_T_2005, 0, 0) @[el2_dec_tlu_ctl.scala 2399:62]
node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2400:34]
node _T_2008 = bits(_T_2007, 0, 0) @[el2_dec_tlu_ctl.scala 2400:62]
node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2401:34]
node _T_2010 = bits(_T_2009, 0, 0) @[el2_dec_tlu_ctl.scala 2401:62]
node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2402:34]
node _T_2012 = bits(_T_2011, 0, 0) @[el2_dec_tlu_ctl.scala 2402:62]
node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_2014 = bits(_T_2013, 0, 0) @[el2_dec_tlu_ctl.scala 2402:84]
node _T_2015 = not(_T_2014) @[el2_dec_tlu_ctl.scala 2402:73]
node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2403:34]
node _T_2017 = bits(_T_2016, 0, 0) @[el2_dec_tlu_ctl.scala 2403:62]
node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_2019 = bits(_T_2018, 0, 0) @[el2_dec_tlu_ctl.scala 2403:84]
node _T_2020 = not(_T_2019) @[el2_dec_tlu_ctl.scala 2403:73]
node _T_2021 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2403:107]
node _T_2022 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2403:118]
node _T_2023 = and(_T_2021, _T_2022) @[el2_dec_tlu_ctl.scala 2403:113]
node _T_2024 = orr(_T_2023) @[el2_dec_tlu_ctl.scala 2403:125]
node _T_2025 = and(_T_2020, _T_2024) @[el2_dec_tlu_ctl.scala 2403:98]
node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2404:34]
node _T_2027 = bits(_T_2026, 0, 0) @[el2_dec_tlu_ctl.scala 2404:62]
node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2404:91]
node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2405:34]
node _T_2030 = bits(_T_2029, 0, 0) @[el2_dec_tlu_ctl.scala 2405:62]
node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2405:94]
node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2406:34]
node _T_2033 = bits(_T_2032, 0, 0) @[el2_dec_tlu_ctl.scala 2406:62]
node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2406:94]
node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2408:34]
node _T_2036 = bits(_T_2035, 0, 0) @[el2_dec_tlu_ctl.scala 2408:62]
node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2409:34]
node _T_2038 = bits(_T_2037, 0, 0) @[el2_dec_tlu_ctl.scala 2409:62]
node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2410:34]
node _T_2040 = bits(_T_2039, 0, 0) @[el2_dec_tlu_ctl.scala 2410:62]
node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2411:34]
node _T_2042 = bits(_T_2041, 0, 0) @[el2_dec_tlu_ctl.scala 2411:62]
node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2412:34]
node _T_2044 = bits(_T_2043, 0, 0) @[el2_dec_tlu_ctl.scala 2412:62]
node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2086 = mux(_T_2000, io.tlu_busbuff.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2087 = mux(_T_2002, io.tlu_busbuff.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2089 = mux(_T_2006, io.tlu_busbuff.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2091 = mux(_T_2010, io.tlu_busbuff.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72]
node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72]
node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72]
node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72]
node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72]
node _T_2107 = or(_T_2106, _T_2051) @[Mux.scala 27:72]
node _T_2108 = or(_T_2107, _T_2052) @[Mux.scala 27:72]
node _T_2109 = or(_T_2108, _T_2053) @[Mux.scala 27:72]
node _T_2110 = or(_T_2109, _T_2054) @[Mux.scala 27:72]
node _T_2111 = or(_T_2110, _T_2055) @[Mux.scala 27:72]
node _T_2112 = or(_T_2111, _T_2056) @[Mux.scala 27:72]
node _T_2113 = or(_T_2112, _T_2057) @[Mux.scala 27:72]
node _T_2114 = or(_T_2113, _T_2058) @[Mux.scala 27:72]
node _T_2115 = or(_T_2114, _T_2059) @[Mux.scala 27:72]
node _T_2116 = or(_T_2115, _T_2060) @[Mux.scala 27:72]
node _T_2117 = or(_T_2116, _T_2061) @[Mux.scala 27:72]
node _T_2118 = or(_T_2117, _T_2062) @[Mux.scala 27:72]
node _T_2119 = or(_T_2118, _T_2063) @[Mux.scala 27:72]
node _T_2120 = or(_T_2119, _T_2064) @[Mux.scala 27:72]
node _T_2121 = or(_T_2120, _T_2065) @[Mux.scala 27:72]
node _T_2122 = or(_T_2121, _T_2066) @[Mux.scala 27:72]
node _T_2123 = or(_T_2122, _T_2067) @[Mux.scala 27:72]
node _T_2124 = or(_T_2123, _T_2068) @[Mux.scala 27:72]
node _T_2125 = or(_T_2124, _T_2069) @[Mux.scala 27:72]
node _T_2126 = or(_T_2125, _T_2070) @[Mux.scala 27:72]
node _T_2127 = or(_T_2126, _T_2071) @[Mux.scala 27:72]
node _T_2128 = or(_T_2127, _T_2072) @[Mux.scala 27:72]
node _T_2129 = or(_T_2128, _T_2073) @[Mux.scala 27:72]
node _T_2130 = or(_T_2129, _T_2074) @[Mux.scala 27:72]
node _T_2131 = or(_T_2130, _T_2075) @[Mux.scala 27:72]
node _T_2132 = or(_T_2131, _T_2076) @[Mux.scala 27:72]
node _T_2133 = or(_T_2132, _T_2077) @[Mux.scala 27:72]
node _T_2134 = or(_T_2133, _T_2078) @[Mux.scala 27:72]
node _T_2135 = or(_T_2134, _T_2079) @[Mux.scala 27:72]
node _T_2136 = or(_T_2135, _T_2080) @[Mux.scala 27:72]
node _T_2137 = or(_T_2136, _T_2081) @[Mux.scala 27:72]
node _T_2138 = or(_T_2137, _T_2082) @[Mux.scala 27:72]
node _T_2139 = or(_T_2138, _T_2083) @[Mux.scala 27:72]
node _T_2140 = or(_T_2139, _T_2084) @[Mux.scala 27:72]
node _T_2141 = or(_T_2140, _T_2085) @[Mux.scala 27:72]
node _T_2142 = or(_T_2141, _T_2086) @[Mux.scala 27:72]
node _T_2143 = or(_T_2142, _T_2087) @[Mux.scala 27:72]
node _T_2144 = or(_T_2143, _T_2088) @[Mux.scala 27:72]
node _T_2145 = or(_T_2144, _T_2089) @[Mux.scala 27:72]
node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72]
node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72]
node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72]
node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72]
node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72]
node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72]
node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72]
node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72]
node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72]
node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72]
node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72]
node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72]
wire _T_2158 : UInt<1> @[Mux.scala 27:72]
_T_2158 <= _T_2157 @[Mux.scala 27:72]
node _T_2159 = and(_T_1877, _T_2158) @[el2_dec_tlu_ctl.scala 2354:44]
mhpmc_inc_r[3] <= _T_2159 @[el2_dec_tlu_ctl.scala 2354:19]
reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2415:53]
_T_2160 <= mhpmc_inc_r[0] @[el2_dec_tlu_ctl.scala 2415:53]
mhpmc_inc_r_d1[0] <= _T_2160 @[el2_dec_tlu_ctl.scala 2415:20]
reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2416:53]
_T_2161 <= mhpmc_inc_r[1] @[el2_dec_tlu_ctl.scala 2416:53]
mhpmc_inc_r_d1[1] <= _T_2161 @[el2_dec_tlu_ctl.scala 2416:20]
reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2417:53]
_T_2162 <= mhpmc_inc_r[2] @[el2_dec_tlu_ctl.scala 2417:53]
mhpmc_inc_r_d1[2] <= _T_2162 @[el2_dec_tlu_ctl.scala 2417:20]
reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2418:53]
_T_2163 <= mhpmc_inc_r[3] @[el2_dec_tlu_ctl.scala 2418:53]
mhpmc_inc_r_d1[3] <= _T_2163 @[el2_dec_tlu_ctl.scala 2418:20]
reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2419:56]
perfcnt_halted_d1 <= perfcnt_halted @[el2_dec_tlu_ctl.scala 2419:56]
node _T_2164 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2422:53]
node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[el2_dec_tlu_ctl.scala 2422:44]
node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2422:67]
perfcnt_halted <= _T_2166 @[el2_dec_tlu_ctl.scala 2422:17]
node _T_2167 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2423:70]
node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[el2_dec_tlu_ctl.scala 2423:61]
node _T_2169 = not(_T_2168) @[el2_dec_tlu_ctl.scala 2423:37]
node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15]
node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_2172 = bits(mhpme_vec[3], 9, 9) @[el2_dec_tlu_ctl.scala 2423:104]
node _T_2173 = bits(mhpme_vec[2], 9, 9) @[el2_dec_tlu_ctl.scala 2423:120]
node _T_2174 = bits(mhpme_vec[1], 9, 9) @[el2_dec_tlu_ctl.scala 2423:136]
node _T_2175 = bits(mhpme_vec[0], 9, 9) @[el2_dec_tlu_ctl.scala 2423:152]
node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58]
node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58]
node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58]
node perfcnt_during_sleep = and(_T_2171, _T_2178) @[el2_dec_tlu_ctl.scala 2423:86]
node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2425:88]
node _T_2180 = not(_T_2179) @[el2_dec_tlu_ctl.scala 2425:67]
node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[el2_dec_tlu_ctl.scala 2425:65]
node _T_2182 = not(_T_2181) @[el2_dec_tlu_ctl.scala 2425:45]
node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[el2_dec_tlu_ctl.scala 2425:43]
io.dec_tlu_perfcnt0 <= _T_2183 @[el2_dec_tlu_ctl.scala 2425:22]
node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2426:88]
node _T_2185 = not(_T_2184) @[el2_dec_tlu_ctl.scala 2426:67]
node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[el2_dec_tlu_ctl.scala 2426:65]
node _T_2187 = not(_T_2186) @[el2_dec_tlu_ctl.scala 2426:45]
node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[el2_dec_tlu_ctl.scala 2426:43]
io.dec_tlu_perfcnt1 <= _T_2188 @[el2_dec_tlu_ctl.scala 2426:22]
node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2427:88]
node _T_2190 = not(_T_2189) @[el2_dec_tlu_ctl.scala 2427:67]
node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[el2_dec_tlu_ctl.scala 2427:65]
node _T_2192 = not(_T_2191) @[el2_dec_tlu_ctl.scala 2427:45]
node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[el2_dec_tlu_ctl.scala 2427:43]
io.dec_tlu_perfcnt2 <= _T_2193 @[el2_dec_tlu_ctl.scala 2427:22]
node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2428:88]
node _T_2195 = not(_T_2194) @[el2_dec_tlu_ctl.scala 2428:67]
node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[el2_dec_tlu_ctl.scala 2428:65]
node _T_2197 = not(_T_2196) @[el2_dec_tlu_ctl.scala 2428:45]
node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[el2_dec_tlu_ctl.scala 2428:43]
io.dec_tlu_perfcnt3 <= _T_2198 @[el2_dec_tlu_ctl.scala 2428:22]
node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2434:65]
node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[el2_dec_tlu_ctl.scala 2434:72]
node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[el2_dec_tlu_ctl.scala 2434:43]
node _T_2201 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2435:23]
node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2435:61]
node _T_2203 = or(_T_2201, _T_2202) @[el2_dec_tlu_ctl.scala 2435:39]
node _T_2204 = orr(mhpmc_inc_r[0]) @[el2_dec_tlu_ctl.scala 2435:86]
node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[el2_dec_tlu_ctl.scala 2435:66]
node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2436:36]
node _T_2205 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2439:28]
node _T_2206 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2439:41]
node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58]
node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58]
node _T_2209 = add(_T_2207, _T_2208) @[el2_dec_tlu_ctl.scala 2439:49]
node _T_2210 = tail(_T_2209, 1) @[el2_dec_tlu_ctl.scala 2439:49]
mhpmc3_incr <= _T_2210 @[el2_dec_tlu_ctl.scala 2439:14]
node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2440:36]
node _T_2212 = bits(mhpmc3_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2440:76]
node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[el2_dec_tlu_ctl.scala 2440:21]
node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2442:42]
inst rvclkhdr_26 of rvclkhdr_34 @[el2_lib.scala 508:23]
rvclkhdr_26.clock <= clock
rvclkhdr_26.reset <= reset
rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_26.io.en <= _T_2213 @[el2_lib.scala 511:17]
rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2214 <= mhpmc3_ns @[el2_lib.scala 514:16]
mhpmc3 <= _T_2214 @[el2_dec_tlu_ctl.scala 2442:9]
node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2444:66]
node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[el2_dec_tlu_ctl.scala 2444:73]
node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[el2_dec_tlu_ctl.scala 2444:44]
node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2445:38]
node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2446:38]
node _T_2218 = bits(mhpmc3_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2446:78]
node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[el2_dec_tlu_ctl.scala 2446:22]
node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2448:46]
inst rvclkhdr_27 of rvclkhdr_35 @[el2_lib.scala 508:23]
rvclkhdr_27.clock <= clock
rvclkhdr_27.reset <= reset
rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_27.io.en <= _T_2219 @[el2_lib.scala 511:17]
rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2220 <= mhpmc3h_ns @[el2_lib.scala 514:16]
mhpmc3h <= _T_2220 @[el2_dec_tlu_ctl.scala 2448:10]
node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2453:65]
node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[el2_dec_tlu_ctl.scala 2453:72]
node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[el2_dec_tlu_ctl.scala 2453:43]
node _T_2223 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2454:23]
node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2454:61]
node _T_2225 = or(_T_2223, _T_2224) @[el2_dec_tlu_ctl.scala 2454:39]
node _T_2226 = orr(mhpmc_inc_r[1]) @[el2_dec_tlu_ctl.scala 2454:86]
node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[el2_dec_tlu_ctl.scala 2454:66]
node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2455:36]
node _T_2227 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2459:28]
node _T_2228 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2459:41]
node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58]
node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58]
node _T_2231 = add(_T_2229, _T_2230) @[el2_dec_tlu_ctl.scala 2459:49]
node _T_2232 = tail(_T_2231, 1) @[el2_dec_tlu_ctl.scala 2459:49]
mhpmc4_incr <= _T_2232 @[el2_dec_tlu_ctl.scala 2459:14]
node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2460:36]
node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[el2_dec_tlu_ctl.scala 2460:63]
node _T_2235 = bits(mhpmc4_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2460:82]
node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[el2_dec_tlu_ctl.scala 2460:21]
node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2461:43]
inst rvclkhdr_28 of rvclkhdr_36 @[el2_lib.scala 508:23]
rvclkhdr_28.clock <= clock
rvclkhdr_28.reset <= reset
rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_28.io.en <= _T_2236 @[el2_lib.scala 511:17]
rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2237 <= mhpmc4_ns @[el2_lib.scala 514:16]
mhpmc4 <= _T_2237 @[el2_dec_tlu_ctl.scala 2461:9]
node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2463:66]
node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[el2_dec_tlu_ctl.scala 2463:73]
node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[el2_dec_tlu_ctl.scala 2463:44]
node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2464:38]
node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2465:38]
node _T_2241 = bits(mhpmc4_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2465:78]
node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[el2_dec_tlu_ctl.scala 2465:22]
node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2466:46]
inst rvclkhdr_29 of rvclkhdr_37 @[el2_lib.scala 508:23]
rvclkhdr_29.clock <= clock
rvclkhdr_29.reset <= reset
rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_29.io.en <= _T_2242 @[el2_lib.scala 511:17]
rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2243 <= mhpmc4h_ns @[el2_lib.scala 514:16]
mhpmc4h <= _T_2243 @[el2_dec_tlu_ctl.scala 2466:10]
node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2472:65]
node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[el2_dec_tlu_ctl.scala 2472:72]
node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[el2_dec_tlu_ctl.scala 2472:43]
node _T_2246 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2473:23]
node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2473:61]
node _T_2248 = or(_T_2246, _T_2247) @[el2_dec_tlu_ctl.scala 2473:39]
node _T_2249 = orr(mhpmc_inc_r[2]) @[el2_dec_tlu_ctl.scala 2473:86]
node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[el2_dec_tlu_ctl.scala 2473:66]
node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2474:36]
node _T_2250 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2476:28]
node _T_2251 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2476:41]
node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58]
node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58]
node _T_2254 = add(_T_2252, _T_2253) @[el2_dec_tlu_ctl.scala 2476:49]
node _T_2255 = tail(_T_2254, 1) @[el2_dec_tlu_ctl.scala 2476:49]
mhpmc5_incr <= _T_2255 @[el2_dec_tlu_ctl.scala 2476:14]
node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2477:36]
node _T_2257 = bits(mhpmc5_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2477:76]
node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[el2_dec_tlu_ctl.scala 2477:21]
node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2479:43]
inst rvclkhdr_30 of rvclkhdr_38 @[el2_lib.scala 508:23]
rvclkhdr_30.clock <= clock
rvclkhdr_30.reset <= reset
rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_30.io.en <= _T_2258 @[el2_lib.scala 511:17]
rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2259 <= mhpmc5_ns @[el2_lib.scala 514:16]
mhpmc5 <= _T_2259 @[el2_dec_tlu_ctl.scala 2479:9]
node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2481:66]
node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[el2_dec_tlu_ctl.scala 2481:73]
node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[el2_dec_tlu_ctl.scala 2481:44]
node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2482:38]
node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2483:38]
node _T_2263 = bits(mhpmc5_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2483:78]
node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[el2_dec_tlu_ctl.scala 2483:22]
node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2485:46]
inst rvclkhdr_31 of rvclkhdr_39 @[el2_lib.scala 508:23]
rvclkhdr_31.clock <= clock
rvclkhdr_31.reset <= reset
rvclkhdr_31.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_31.io.en <= _T_2264 @[el2_lib.scala 511:17]
rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2265 <= mhpmc5h_ns @[el2_lib.scala 514:16]
mhpmc5h <= _T_2265 @[el2_dec_tlu_ctl.scala 2485:10]
node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2490:65]
node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[el2_dec_tlu_ctl.scala 2490:72]
node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[el2_dec_tlu_ctl.scala 2490:43]
node _T_2268 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2491:23]
node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2491:61]
node _T_2270 = or(_T_2268, _T_2269) @[el2_dec_tlu_ctl.scala 2491:39]
node _T_2271 = orr(mhpmc_inc_r[3]) @[el2_dec_tlu_ctl.scala 2491:86]
node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[el2_dec_tlu_ctl.scala 2491:66]
node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2492:36]
node _T_2272 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2494:28]
node _T_2273 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2494:41]
node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58]
node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58]
node _T_2276 = add(_T_2274, _T_2275) @[el2_dec_tlu_ctl.scala 2494:49]
node _T_2277 = tail(_T_2276, 1) @[el2_dec_tlu_ctl.scala 2494:49]
mhpmc6_incr <= _T_2277 @[el2_dec_tlu_ctl.scala 2494:14]
node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2495:36]
node _T_2279 = bits(mhpmc6_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2495:76]
node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[el2_dec_tlu_ctl.scala 2495:21]
node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2497:43]
inst rvclkhdr_32 of rvclkhdr_40 @[el2_lib.scala 508:23]
rvclkhdr_32.clock <= clock
rvclkhdr_32.reset <= reset
rvclkhdr_32.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_32.io.en <= _T_2280 @[el2_lib.scala 511:17]
rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2281 <= mhpmc6_ns @[el2_lib.scala 514:16]
mhpmc6 <= _T_2281 @[el2_dec_tlu_ctl.scala 2497:9]
node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2499:66]
node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[el2_dec_tlu_ctl.scala 2499:73]
node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[el2_dec_tlu_ctl.scala 2499:44]
node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2500:38]
node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2501:38]
node _T_2285 = bits(mhpmc6_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2501:78]
node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[el2_dec_tlu_ctl.scala 2501:22]
node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2503:46]
inst rvclkhdr_33 of rvclkhdr_41 @[el2_lib.scala 508:23]
rvclkhdr_33.clock <= clock
rvclkhdr_33.reset <= reset
rvclkhdr_33.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_33.io.en <= _T_2286 @[el2_lib.scala 511:17]
rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_2287 <= mhpmc6h_ns @[el2_lib.scala 514:16]
mhpmc6h <= _T_2287 @[el2_dec_tlu_ctl.scala 2503:10]
node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2510:50]
node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2510:56]
node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2510:93]
node _T_2291 = orr(_T_2290) @[el2_dec_tlu_ctl.scala 2510:102]
node _T_2292 = or(_T_2289, _T_2291) @[el2_dec_tlu_ctl.scala 2510:71]
node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2510:141]
node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[el2_dec_tlu_ctl.scala 2510:28]
node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2512:63]
node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[el2_dec_tlu_ctl.scala 2512:70]
node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[el2_dec_tlu_ctl.scala 2512:41]
node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[el2_dec_tlu_ctl.scala 2514:80]
reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2296 : @[Reg.scala 28:19]
_T_2297 <= event_saturate_r @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
mhpme3 <= _T_2297 @[el2_dec_tlu_ctl.scala 2514:9]
node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2519:63]
node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[el2_dec_tlu_ctl.scala 2519:70]
node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[el2_dec_tlu_ctl.scala 2519:41]
node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[el2_dec_tlu_ctl.scala 2520:80]
reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2300 : @[Reg.scala 28:19]
_T_2301 <= event_saturate_r @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
mhpme4 <= _T_2301 @[el2_dec_tlu_ctl.scala 2520:9]
node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2526:63]
node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[el2_dec_tlu_ctl.scala 2526:70]
node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[el2_dec_tlu_ctl.scala 2526:41]
node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[el2_dec_tlu_ctl.scala 2527:80]
reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2304 : @[Reg.scala 28:19]
_T_2305 <= event_saturate_r @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
mhpme5 <= _T_2305 @[el2_dec_tlu_ctl.scala 2527:9]
node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2533:63]
node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[el2_dec_tlu_ctl.scala 2533:70]
node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[el2_dec_tlu_ctl.scala 2533:41]
node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[el2_dec_tlu_ctl.scala 2534:80]
reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2308 : @[Reg.scala 28:19]
_T_2309 <= event_saturate_r @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
mhpme6 <= _T_2309 @[el2_dec_tlu_ctl.scala 2534:9]
node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2550:70]
node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[el2_dec_tlu_ctl.scala 2550:77]
node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[el2_dec_tlu_ctl.scala 2550:48]
node _T_2312 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2552:54]
wire temp_ncount0 : UInt<1>
temp_ncount0 <= _T_2312
node _T_2313 = bits(mcountinhibit, 1, 1) @[el2_dec_tlu_ctl.scala 2553:54]
wire temp_ncount1 : UInt<1>
temp_ncount1 <= _T_2313
node _T_2314 = bits(mcountinhibit, 6, 2) @[el2_dec_tlu_ctl.scala 2554:55]
wire temp_ncount6_2 : UInt<5>
temp_ncount6_2 <= _T_2314
node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[el2_dec_tlu_ctl.scala 2555:74]
node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:103]
reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2316 : @[Reg.scala 28:19]
_T_2317 <= _T_2315 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
temp_ncount6_2 <= _T_2317 @[el2_dec_tlu_ctl.scala 2555:17]
node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2557:72]
node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2557:99]
reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2319 : @[Reg.scala 28:19]
_T_2320 <= _T_2318 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
temp_ncount0 <= _T_2320 @[el2_dec_tlu_ctl.scala 2557:15]
node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58]
mcountinhibit <= _T_2322 @[el2_dec_tlu_ctl.scala 2558:16]
node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 2565:51]
node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 2565:78]
node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[el2_dec_tlu_ctl.scala 2565:104]
node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[el2_dec_tlu_ctl.scala 2565:130]
node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[el2_dec_tlu_ctl.scala 2566:32]
node _T_2328 = or(_T_2327, io.clk_override) @[el2_dec_tlu_ctl.scala 2566:59]
node _T_2329 = bits(_T_2328, 0, 0) @[el2_dec_tlu_ctl.scala 2566:78]
inst rvclkhdr_34 of rvclkhdr_42 @[el2_lib.scala 483:22]
rvclkhdr_34.clock <= clock
rvclkhdr_34.reset <= reset
rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_34.io.en <= _T_2329 @[el2_lib.scala 485:16]
rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2568:62]
_T_2330 <= io.i0_valid_wb @[el2_dec_tlu_ctl.scala 2568:62]
io.dec_tlu_i0_valid_wb1 <= _T_2330 @[el2_dec_tlu_ctl.scala 2568:30]
node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[el2_dec_tlu_ctl.scala 2569:91]
node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 2569:137]
node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[el2_dec_tlu_ctl.scala 2569:135]
node _T_2334 = or(_T_2331, _T_2333) @[el2_dec_tlu_ctl.scala 2569:112]
reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2569:62]
_T_2335 <= _T_2334 @[el2_dec_tlu_ctl.scala 2569:62]
io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[el2_dec_tlu_ctl.scala 2569:30]
reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2570:62]
_T_2336 <= io.exc_cause_wb @[el2_dec_tlu_ctl.scala 2570:62]
io.dec_tlu_exc_cause_wb1 <= _T_2336 @[el2_dec_tlu_ctl.scala 2570:30]
reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2571:62]
_T_2337 <= io.interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 2571:62]
io.dec_tlu_int_valid_wb1 <= _T_2337 @[el2_dec_tlu_ctl.scala 2571:30]
io.dec_tlu_mtval_wb1 <= mtval @[el2_dec_tlu_ctl.scala 2573:24]
node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[el2_dec_tlu_ctl.scala 2579:61]
node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[el2_dec_tlu_ctl.scala 2580:42]
node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[el2_dec_tlu_ctl.scala 2581:40]
node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[el2_dec_tlu_ctl.scala 2582:39]
node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[el2_dec_tlu_ctl.scala 2583:40]
node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2584:40]
node _T_2345 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 2584:103]
node _T_2346 = bits(io.mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2584:128]
node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58]
node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58]
node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58]
node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58]
node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2585:38]
node _T_2354 = bits(io.mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 2585:70]
node _T_2355 = bits(io.mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2585:96]
node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58]
node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[el2_dec_tlu_ctl.scala 2586:36]
node _T_2359 = bits(io.mip, 5, 3) @[el2_dec_tlu_ctl.scala 2586:78]
node _T_2360 = bits(io.mip, 2, 2) @[el2_dec_tlu_ctl.scala 2586:102]
node _T_2361 = bits(io.mip, 1, 1) @[el2_dec_tlu_ctl.scala 2586:123]
node _T_2362 = bits(io.mip, 0, 0) @[el2_dec_tlu_ctl.scala 2586:144]
node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58]
node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58]
node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58]
node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58]
node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58]
node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[el2_dec_tlu_ctl.scala 2587:36]
node _T_2372 = bits(mie, 5, 3) @[el2_dec_tlu_ctl.scala 2587:75]
node _T_2373 = bits(mie, 2, 2) @[el2_dec_tlu_ctl.scala 2587:96]
node _T_2374 = bits(mie, 1, 1) @[el2_dec_tlu_ctl.scala 2587:114]
node _T_2375 = bits(mie, 0, 0) @[el2_dec_tlu_ctl.scala 2587:132]
node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58]
node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58]
node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58]
node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58]
node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58]
node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[el2_dec_tlu_ctl.scala 2588:40]
node _T_2385 = bits(mcyclel, 31, 0) @[el2_dec_tlu_ctl.scala 2588:65]
node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[el2_dec_tlu_ctl.scala 2589:40]
node _T_2387 = bits(mcycleh_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2589:69]
node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[el2_dec_tlu_ctl.scala 2590:42]
node _T_2389 = bits(minstretl, 31, 0) @[el2_dec_tlu_ctl.scala 2590:72]
node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[el2_dec_tlu_ctl.scala 2591:42]
node _T_2391 = bits(minstreth_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2591:72]
node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[el2_dec_tlu_ctl.scala 2592:41]
node _T_2393 = bits(mscratch, 31, 0) @[el2_dec_tlu_ctl.scala 2592:66]
node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[el2_dec_tlu_ctl.scala 2593:37]
node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[el2_dec_tlu_ctl.scala 2594:39]
node _T_2397 = bits(mcause, 31, 0) @[el2_dec_tlu_ctl.scala 2594:64]
node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[el2_dec_tlu_ctl.scala 2595:40]
node _T_2399 = bits(mscause, 3, 0) @[el2_dec_tlu_ctl.scala 2595:80]
node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58]
node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[el2_dec_tlu_ctl.scala 2596:38]
node _T_2402 = bits(mtval, 31, 0) @[el2_dec_tlu_ctl.scala 2596:63]
node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[el2_dec_tlu_ctl.scala 2597:37]
node _T_2404 = bits(mrac, 31, 0) @[el2_dec_tlu_ctl.scala 2597:62]
node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[el2_dec_tlu_ctl.scala 2598:39]
node _T_2406 = bits(mdseac, 31, 0) @[el2_dec_tlu_ctl.scala 2598:64]
node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[el2_dec_tlu_ctl.scala 2599:38]
node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[el2_dec_tlu_ctl.scala 2600:39]
node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58]
node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[el2_dec_tlu_ctl.scala 2601:41]
node _T_2413 = bits(meicurpl, 3, 0) @[el2_dec_tlu_ctl.scala 2601:81]
node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58]
node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[el2_dec_tlu_ctl.scala 2602:41]
node _T_2416 = bits(meicidpl, 3, 0) @[el2_dec_tlu_ctl.scala 2602:81]
node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58]
node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[el2_dec_tlu_ctl.scala 2603:38]
node _T_2419 = bits(meipt, 3, 0) @[el2_dec_tlu_ctl.scala 2603:78]
node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58]
node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 2604:37]
node _T_2422 = bits(mcgc, 8, 0) @[el2_dec_tlu_ctl.scala 2604:77]
node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58]
node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 2605:37]
node _T_2425 = bits(mfdc, 18, 0) @[el2_dec_tlu_ctl.scala 2605:77]
node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58]
node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[el2_dec_tlu_ctl.scala 2606:37]
node _T_2428 = bits(io.dcsr, 15, 2) @[el2_dec_tlu_ctl.scala 2606:85]
node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58]
node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58]
node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[el2_dec_tlu_ctl.scala 2607:36]
node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[el2_dec_tlu_ctl.scala 2608:39]
node _T_2434 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2608:64]
node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[el2_dec_tlu_ctl.scala 2609:40]
node _T_2436 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2609:65]
node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[el2_dec_tlu_ctl.scala 2610:39]
node _T_2438 = bits(dicad1, 31, 0) @[el2_dec_tlu_ctl.scala 2610:64]
node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[el2_dec_tlu_ctl.scala 2611:41]
node _T_2440 = bits(dicawics, 16, 16) @[el2_dec_tlu_ctl.scala 2611:80]
node _T_2441 = bits(dicawics, 15, 14) @[el2_dec_tlu_ctl.scala 2611:104]
node _T_2442 = bits(dicawics, 13, 0) @[el2_dec_tlu_ctl.scala 2611:131]
node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58]
node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58]
node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58]
node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58]
node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58]
node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[el2_dec_tlu_ctl.scala 2612:38]
node _T_2450 = bits(mtsel, 1, 0) @[el2_dec_tlu_ctl.scala 2612:78]
node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58]
node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[el2_dec_tlu_ctl.scala 2613:40]
node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2613:74]
node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[el2_dec_tlu_ctl.scala 2614:40]
node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2614:74]
node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[el2_dec_tlu_ctl.scala 2615:39]
node _T_2457 = bits(micect, 31, 0) @[el2_dec_tlu_ctl.scala 2615:64]
node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2616:41]
node _T_2459 = bits(miccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2616:66]
node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2617:41]
node _T_2461 = bits(mdccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2617:66]
node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[el2_dec_tlu_ctl.scala 2618:39]
node _T_2463 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2618:64]
node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[el2_dec_tlu_ctl.scala 2619:39]
node _T_2465 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2619:64]
node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[el2_dec_tlu_ctl.scala 2620:39]
node _T_2467 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2620:64]
node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[el2_dec_tlu_ctl.scala 2621:39]
node _T_2469 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2621:64]
node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[el2_dec_tlu_ctl.scala 2622:40]
node _T_2471 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2622:65]
node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[el2_dec_tlu_ctl.scala 2623:40]
node _T_2473 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2623:65]
node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[el2_dec_tlu_ctl.scala 2624:40]
node _T_2475 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2624:65]
node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[el2_dec_tlu_ctl.scala 2625:40]
node _T_2477 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2625:65]
node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2626:38]
node _T_2479 = bits(mfdht, 5, 0) @[el2_dec_tlu_ctl.scala 2626:78]
node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58]
node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[el2_dec_tlu_ctl.scala 2627:38]
node _T_2482 = bits(mfdhs, 1, 0) @[el2_dec_tlu_ctl.scala 2627:78]
node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58]
node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[el2_dec_tlu_ctl.scala 2628:39]
node _T_2485 = bits(mhpme3, 9, 0) @[el2_dec_tlu_ctl.scala 2628:79]
node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58]
node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[el2_dec_tlu_ctl.scala 2629:39]
node _T_2488 = bits(mhpme4, 9, 0) @[el2_dec_tlu_ctl.scala 2629:79]
node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58]
node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[el2_dec_tlu_ctl.scala 2630:39]
node _T_2491 = bits(mhpme5, 9, 0) @[el2_dec_tlu_ctl.scala 2630:78]
node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58]
node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[el2_dec_tlu_ctl.scala 2631:39]
node _T_2494 = bits(mhpme6, 9, 0) @[el2_dec_tlu_ctl.scala 2631:78]
node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58]
node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2632:46]
node _T_2497 = bits(mcountinhibit, 6, 0) @[el2_dec_tlu_ctl.scala 2632:86]
node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58]
node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[el2_dec_tlu_ctl.scala 2633:37]
node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[el2_dec_tlu_ctl.scala 2634:37]
node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[el2_dec_tlu_ctl.scala 2634:76]
node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72]
node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72]
node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72]
node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72]
node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72]
node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72]
node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72]
node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72]
node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72]
node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72]
node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72]
node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72]
node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72]
node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72]
node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72]
node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72]
node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72]
node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72]
node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72]
node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72]
node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72]
node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72]
node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72]
node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72]
node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72]
node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72]
node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72]
node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72]
node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72]
node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72]
node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72]
node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72]
node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72]
node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72]
node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72]
node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72]
node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72]
node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72]
node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72]
node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72]
node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72]
node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72]
node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72]
node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72]
node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72]
node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72]
node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72]
node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72]
node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72]
node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72]
node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72]
node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72]
node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72]
node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72]
node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72]
wire _T_2615 : UInt @[Mux.scala 27:72]
_T_2615 <= _T_2614 @[Mux.scala 27:72]
io.dec_csr_rddata_d <= _T_2615 @[el2_dec_tlu_ctl.scala 2578:21]
module el2_dec_decode_csr_read :
input clock : Clock
input reset : AsyncReset
output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}}
node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1 = eq(_T, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_3 = eq(_T_2, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_5 = eq(_T_4, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_9 = and(_T_1, _T_3) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_10 = and(_T_9, _T_5) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_11 = and(_T_10, _T_7) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_12 = and(_T_11, _T_8) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_misa <= _T_12 @[el2_dec_tlu_ctl.scala 2652:57]
node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_17 = eq(_T_16, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_19 = and(_T_13, _T_15) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_20 = and(_T_19, _T_17) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_21 = and(_T_20, _T_18) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mvendorid <= _T_21 @[el2_dec_tlu_ctl.scala 2653:57]
node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_28 = and(_T_22, _T_24) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_29 = and(_T_28, _T_25) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_30 = and(_T_29, _T_27) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_marchid <= _T_30 @[el2_dec_tlu_ctl.scala 2654:57]
node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_36 = and(_T_31, _T_33) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_37 = and(_T_36, _T_34) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_38 = and(_T_37, _T_35) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mimpid <= _T_38 @[el2_dec_tlu_ctl.scala 2655:57]
node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_43 = and(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_44 = and(_T_43, _T_42) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhartid <= _T_44 @[el2_dec_tlu_ctl.scala 2656:57]
node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_55 = and(_T_46, _T_48) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_56 = and(_T_55, _T_50) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_57 = and(_T_56, _T_52) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_58 = and(_T_57, _T_54) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mstatus <= _T_58 @[el2_dec_tlu_ctl.scala 2657:57]
node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_67 = and(_T_60, _T_62) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_68 = and(_T_67, _T_64) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_69 = and(_T_68, _T_65) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_70 = and(_T_69, _T_66) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mtvec <= _T_70 @[el2_dec_tlu_ctl.scala 2658:57]
node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_75 = and(_T_72, _T_73) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_76 = and(_T_75, _T_74) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mip <= _T_76 @[el2_dec_tlu_ctl.scala 2659:65]
node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_86 = and(_T_78, _T_80) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_87 = and(_T_86, _T_82) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_88 = and(_T_87, _T_83) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_89 = and(_T_88, _T_85) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mie <= _T_89 @[el2_dec_tlu_ctl.scala 2660:65]
node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_101 = and(_T_90, _T_92) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_102 = and(_T_101, _T_94) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_103 = and(_T_102, _T_96) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_104 = and(_T_103, _T_98) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_105 = and(_T_104, _T_100) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcyclel <= _T_105 @[el2_dec_tlu_ctl.scala 2661:57]
node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_108 = eq(_T_107, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_119 = and(_T_106, _T_108) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_120 = and(_T_119, _T_110) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_121 = and(_T_120, _T_112) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_122 = and(_T_121, _T_114) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_123 = and(_T_122, _T_116) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_124 = and(_T_123, _T_118) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcycleh <= _T_124 @[el2_dec_tlu_ctl.scala 2662:57]
node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_128 = eq(_T_127, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_138 = and(_T_126, _T_128) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_139 = and(_T_138, _T_130) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_140 = and(_T_139, _T_132) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_141 = and(_T_140, _T_134) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_142 = and(_T_141, _T_135) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_143 = and(_T_142, _T_137) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_minstretl <= _T_143 @[el2_dec_tlu_ctl.scala 2663:57]
node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_145 = eq(_T_144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_156 = and(_T_145, _T_146) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_157 = and(_T_156, _T_148) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_158 = and(_T_157, _T_150) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_159 = and(_T_158, _T_152) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_160 = and(_T_159, _T_153) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_161 = and(_T_160, _T_155) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_minstreth <= _T_161 @[el2_dec_tlu_ctl.scala 2664:57]
node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_171 = and(_T_163, _T_164) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_172 = and(_T_171, _T_166) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_173 = and(_T_172, _T_168) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_174 = and(_T_173, _T_170) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mscratch <= _T_174 @[el2_dec_tlu_ctl.scala 2665:57]
node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_181 = and(_T_176, _T_177) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_182 = and(_T_181, _T_179) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_183 = and(_T_182, _T_180) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mepc <= _T_183 @[el2_dec_tlu_ctl.scala 2666:57]
node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_190 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_191 = and(_T_190, _T_187) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_192 = and(_T_191, _T_189) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcause <= _T_192 @[el2_dec_tlu_ctl.scala 2667:57]
node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_196 = and(_T_193, _T_194) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_197 = and(_T_196, _T_195) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mscause <= _T_197 @[el2_dec_tlu_ctl.scala 2668:57]
node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_203 = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_204 = and(_T_203, _T_201) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_205 = and(_T_204, _T_202) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mtval <= _T_205 @[el2_dec_tlu_ctl.scala 2669:57]
node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_217 = and(_T_207, _T_208) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_218 = and(_T_217, _T_210) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_219 = and(_T_218, _T_212) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_220 = and(_T_219, _T_214) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_221 = and(_T_220, _T_216) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mrac <= _T_221 @[el2_dec_tlu_ctl.scala 2670:57]
node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_230 = and(_T_222, _T_224) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_231 = and(_T_230, _T_226) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_232 = and(_T_231, _T_227) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_233 = and(_T_232, _T_229) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dmst <= _T_233 @[el2_dec_tlu_ctl.scala 2671:57]
node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_237 = eq(_T_236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_240 = and(_T_234, _T_235) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_241 = and(_T_240, _T_237) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_242 = and(_T_241, _T_239) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mdseac <= _T_242 @[el2_dec_tlu_ctl.scala 2672:57]
node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_246 = and(_T_243, _T_244) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_247 = and(_T_246, _T_245) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meihap <= _T_247 @[el2_dec_tlu_ctl.scala 2673:57]
node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_258 = and(_T_249, _T_250) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_259 = and(_T_258, _T_251) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_260 = and(_T_259, _T_253) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_261 = and(_T_260, _T_255) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_262 = and(_T_261, _T_257) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meivt <= _T_262 @[el2_dec_tlu_ctl.scala 2674:57]
node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_266 = eq(_T_265, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_268 = and(_T_263, _T_264) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_269 = and(_T_268, _T_266) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_270 = and(_T_269, _T_267) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meipt <= _T_270 @[el2_dec_tlu_ctl.scala 2675:57]
node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_274 = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_275 = and(_T_274, _T_273) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meicurpl <= _T_275 @[el2_dec_tlu_ctl.scala 2676:57]
node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_280 = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_281 = and(_T_280, _T_278) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_282 = and(_T_281, _T_279) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meicidpl <= _T_282 @[el2_dec_tlu_ctl.scala 2677:57]
node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_290 = and(_T_283, _T_285) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_291 = and(_T_290, _T_286) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_292 = and(_T_291, _T_287) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_293 = and(_T_292, _T_289) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dcsr <= _T_293 @[el2_dec_tlu_ctl.scala 2678:57]
node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_299 = and(_T_294, _T_295) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_300 = and(_T_299, _T_296) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_301 = and(_T_300, _T_298) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcgc <= _T_301 @[el2_dec_tlu_ctl.scala 2679:57]
node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_308 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_309 = and(_T_308, _T_304) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_310 = and(_T_309, _T_306) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_311 = and(_T_310, _T_307) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mfdc <= _T_311 @[el2_dec_tlu_ctl.scala 2680:57]
node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_318 = and(_T_312, _T_314) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_319 = and(_T_318, _T_315) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_320 = and(_T_319, _T_316) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_321 = and(_T_320, _T_317) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dpc <= _T_321 @[el2_dec_tlu_ctl.scala 2681:65]
node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_330 = and(_T_322, _T_323) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_331 = and(_T_330, _T_325) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_332 = and(_T_331, _T_327) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_333 = and(_T_332, _T_329) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mtsel <= _T_333 @[el2_dec_tlu_ctl.scala 2682:57]
node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_340 = and(_T_334, _T_336) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_341 = and(_T_340, _T_338) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_342 = and(_T_341, _T_339) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mtdata1 <= _T_342 @[el2_dec_tlu_ctl.scala 2683:57]
node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_348 = and(_T_343, _T_344) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_349 = and(_T_348, _T_346) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_350 = and(_T_349, _T_347) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mtdata2 <= _T_350 @[el2_dec_tlu_ctl.scala 2684:57]
node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_361 = and(_T_351, _T_353) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_362 = and(_T_361, _T_355) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_363 = and(_T_362, _T_357) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_364 = and(_T_363, _T_359) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_365 = and(_T_364, _T_360) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc3 <= _T_365 @[el2_dec_tlu_ctl.scala 2685:57]
node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_368 = eq(_T_367, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_370 = eq(_T_369, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_378 = and(_T_366, _T_368) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_379 = and(_T_378, _T_370) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_380 = and(_T_379, _T_372) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_381 = and(_T_380, _T_373) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_382 = and(_T_381, _T_375) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_383 = and(_T_382, _T_377) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc4 <= _T_383 @[el2_dec_tlu_ctl.scala 2686:57]
node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_394 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_395 = and(_T_394, _T_388) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_396 = and(_T_395, _T_390) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_397 = and(_T_396, _T_392) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_398 = and(_T_397, _T_393) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc5 <= _T_398 @[el2_dec_tlu_ctl.scala 2687:57]
node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_411 = and(_T_400, _T_402) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_412 = and(_T_411, _T_404) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_413 = and(_T_412, _T_406) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_414 = and(_T_413, _T_407) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_415 = and(_T_414, _T_408) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_416 = and(_T_415, _T_410) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc6 <= _T_416 @[el2_dec_tlu_ctl.scala 2688:57]
node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_423 = eq(_T_422, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_426 = and(_T_417, _T_419) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_427 = and(_T_426, _T_421) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_428 = and(_T_427, _T_423) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_429 = and(_T_428, _T_424) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_430 = and(_T_429, _T_425) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc3h <= _T_430 @[el2_dec_tlu_ctl.scala 2689:57]
node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_443 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_444 = and(_T_443, _T_435) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_445 = and(_T_444, _T_437) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_446 = and(_T_445, _T_438) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_447 = and(_T_446, _T_440) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_448 = and(_T_447, _T_442) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc4h <= _T_448 @[el2_dec_tlu_ctl.scala 2690:57]
node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_456 = eq(_T_455, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_458 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_459 = and(_T_458, _T_453) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_460 = and(_T_459, _T_454) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_461 = and(_T_460, _T_456) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_462 = and(_T_461, _T_457) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc5h <= _T_462 @[el2_dec_tlu_ctl.scala 2691:57]
node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_469 = eq(_T_468, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_474 = and(_T_463, _T_465) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_475 = and(_T_474, _T_467) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_476 = and(_T_475, _T_469) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_477 = and(_T_476, _T_470) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_478 = and(_T_477, _T_471) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_479 = and(_T_478, _T_473) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpmc6h <= _T_479 @[el2_dec_tlu_ctl.scala 2692:57]
node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_488 = eq(_T_487, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_490 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_491 = and(_T_490, _T_484) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_492 = and(_T_491, _T_486) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_493 = and(_T_492, _T_488) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_494 = and(_T_493, _T_489) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpme3 <= _T_494 @[el2_dec_tlu_ctl.scala 2693:57]
node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_504 = eq(_T_503, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_505 = and(_T_495, _T_497) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_506 = and(_T_505, _T_499) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_507 = and(_T_506, _T_500) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_508 = and(_T_507, _T_502) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_509 = and(_T_508, _T_504) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpme4 <= _T_509 @[el2_dec_tlu_ctl.scala 2694:57]
node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_512 = eq(_T_511, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_517 = eq(_T_516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_519 = and(_T_510, _T_512) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_520 = and(_T_519, _T_514) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_521 = and(_T_520, _T_515) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_522 = and(_T_521, _T_517) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_523 = and(_T_522, _T_518) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpme5 <= _T_523 @[el2_dec_tlu_ctl.scala 2695:57]
node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_528 = eq(_T_527, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_533 = and(_T_524, _T_526) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_534 = and(_T_533, _T_528) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_535 = and(_T_534, _T_529) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_536 = and(_T_535, _T_530) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_537 = and(_T_536, _T_532) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mhpme6 <= _T_537 @[el2_dec_tlu_ctl.scala 2696:57]
node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_549 = and(_T_539, _T_540) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_550 = and(_T_549, _T_542) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_551 = and(_T_550, _T_544) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_552 = and(_T_551, _T_546) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_553 = and(_T_552, _T_548) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcountinhibit <= _T_553 @[el2_dec_tlu_ctl.scala 2697:49]
node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_562 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_563 = and(_T_562, _T_557) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_564 = and(_T_563, _T_559) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_565 = and(_T_564, _T_561) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitctl0 <= _T_565 @[el2_dec_tlu_ctl.scala 2698:57]
node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_572 = and(_T_566, _T_568) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_573 = and(_T_572, _T_569) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_574 = and(_T_573, _T_570) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_575 = and(_T_574, _T_571) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitctl1 <= _T_575 @[el2_dec_tlu_ctl.scala 2699:57]
node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_583 = and(_T_576, _T_578) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_584 = and(_T_583, _T_579) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_585 = and(_T_584, _T_581) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_586 = and(_T_585, _T_582) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitb0 <= _T_586 @[el2_dec_tlu_ctl.scala 2700:57]
node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_592 = eq(_T_591, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_593 = and(_T_587, _T_588) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_594 = and(_T_593, _T_589) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_595 = and(_T_594, _T_590) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_596 = and(_T_595, _T_592) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitb1 <= _T_596 @[el2_dec_tlu_ctl.scala 2701:57]
node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_599 = eq(_T_598, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_605 = and(_T_597, _T_599) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_606 = and(_T_605, _T_600) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_607 = and(_T_606, _T_602) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_608 = and(_T_607, _T_604) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitcnt0 <= _T_608 @[el2_dec_tlu_ctl.scala 2702:57]
node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_612 = eq(_T_611, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_614 = and(_T_609, _T_610) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_615 = and(_T_614, _T_612) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_616 = and(_T_615, _T_613) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mitcnt1 <= _T_616 @[el2_dec_tlu_ctl.scala 2703:57]
node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_624 = and(_T_617, _T_619) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_625 = and(_T_624, _T_621) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_626 = and(_T_625, _T_622) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_627 = and(_T_626, _T_623) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mpmc <= _T_627 @[el2_dec_tlu_ctl.scala 2704:57]
node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_637 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_638 = and(_T_637, _T_631) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_639 = and(_T_638, _T_633) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_640 = and(_T_639, _T_635) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_641 = and(_T_640, _T_636) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mcpc <= _T_641 @[el2_dec_tlu_ctl.scala 2705:57]
node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_647 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_648 = and(_T_647, _T_644) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_649 = and(_T_648, _T_646) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_meicpct <= _T_649 @[el2_dec_tlu_ctl.scala 2706:57]
node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_651 = eq(_T_650, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_656 = and(_T_651, _T_652) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_657 = and(_T_656, _T_653) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_658 = and(_T_657, _T_655) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mdeau <= _T_658 @[el2_dec_tlu_ctl.scala 2707:57]
node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_664 = eq(_T_663, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_667 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_668 = and(_T_667, _T_662) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_669 = and(_T_668, _T_664) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_670 = and(_T_669, _T_666) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_micect <= _T_670 @[el2_dec_tlu_ctl.scala 2708:57]
node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_676 = and(_T_671, _T_672) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_677 = and(_T_676, _T_674) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_678 = and(_T_677, _T_675) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_miccmect <= _T_678 @[el2_dec_tlu_ctl.scala 2709:57]
node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_683 = eq(_T_682, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_684 = and(_T_679, _T_680) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_685 = and(_T_684, _T_681) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_686 = and(_T_685, _T_683) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mdccmect <= _T_686 @[el2_dec_tlu_ctl.scala 2710:57]
node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_692 = eq(_T_691, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_693 = and(_T_687, _T_688) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_694 = and(_T_693, _T_689) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_695 = and(_T_694, _T_690) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_696 = and(_T_695, _T_692) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mfdht <= _T_696 @[el2_dec_tlu_ctl.scala 2711:57]
node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_702 = and(_T_697, _T_699) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_703 = and(_T_702, _T_700) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_704 = and(_T_703, _T_701) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_mfdhs <= _T_704 @[el2_dec_tlu_ctl.scala 2712:57]
node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_708 = eq(_T_707, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_711 = eq(_T_710, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_713 = eq(_T_712, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_716 = and(_T_706, _T_708) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_717 = and(_T_716, _T_709) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_718 = and(_T_717, _T_711) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_719 = and(_T_718, _T_713) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_720 = and(_T_719, _T_715) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dicawics <= _T_720 @[el2_dec_tlu_ctl.scala 2713:57]
node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_725 = eq(_T_724, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_726 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_727 = and(_T_726, _T_723) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_728 = and(_T_727, _T_725) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dicad0h <= _T_728 @[el2_dec_tlu_ctl.scala 2714:57]
node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_731 = eq(_T_730, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_734 = eq(_T_733, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_736 = and(_T_729, _T_731) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_737 = and(_T_736, _T_732) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_738 = and(_T_737, _T_734) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_739 = and(_T_738, _T_735) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dicad0 <= _T_739 @[el2_dec_tlu_ctl.scala 2715:57]
node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_746 = eq(_T_745, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_747 = and(_T_740, _T_741) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_748 = and(_T_747, _T_743) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_749 = and(_T_748, _T_744) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_750 = and(_T_749, _T_746) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dicad1 <= _T_750 @[el2_dec_tlu_ctl.scala 2716:57]
node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_754 = eq(_T_753, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_757 = and(_T_751, _T_752) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_758 = and(_T_757, _T_754) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_759 = and(_T_758, _T_755) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_760 = and(_T_759, _T_756) @[el2_dec_tlu_ctl.scala 2650:198]
io.csr_pkt.csr_dicago <= _T_760 @[el2_dec_tlu_ctl.scala 2717:57]
node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_765 = eq(_T_764, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_767 = and(_T_761, _T_762) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_768 = and(_T_767, _T_763) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_769 = and(_T_768, _T_765) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_770 = and(_T_769, _T_766) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_779 = eq(_T_778, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_782 = and(_T_772, _T_773) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_783 = and(_T_782, _T_775) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_784 = and(_T_783, _T_777) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_785 = and(_T_784, _T_779) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_786 = and(_T_785, _T_781) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_787 = or(_T_770, _T_786) @[el2_dec_tlu_ctl.scala 2718:81]
node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_789 = eq(_T_788, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_795 = eq(_T_794, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_799 = and(_T_789, _T_791) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_800 = and(_T_799, _T_793) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_801 = and(_T_800, _T_795) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_802 = and(_T_801, _T_797) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_803 = and(_T_802, _T_798) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_804 = or(_T_787, _T_803) @[el2_dec_tlu_ctl.scala 2718:121]
node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_807 = eq(_T_806, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_809 = eq(_T_808, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_813 = and(_T_805, _T_807) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_814 = and(_T_813, _T_809) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_815 = and(_T_814, _T_810) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_816 = and(_T_815, _T_812) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_817 = or(_T_804, _T_816) @[el2_dec_tlu_ctl.scala 2718:155]
node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_820 = eq(_T_819, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_826 = and(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_827 = and(_T_826, _T_822) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_828 = and(_T_827, _T_823) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_829 = and(_T_828, _T_825) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_830 = or(_T_817, _T_829) @[el2_dec_tlu_ctl.scala 2719:97]
node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_835 = eq(_T_834, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_841 = and(_T_831, _T_833) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_842 = and(_T_841, _T_835) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_843 = and(_T_842, _T_837) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_844 = and(_T_843, _T_839) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_845 = and(_T_844, _T_840) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_846 = or(_T_830, _T_845) @[el2_dec_tlu_ctl.scala 2719:137]
io.csr_pkt.presync <= _T_846 @[el2_dec_tlu_ctl.scala 2718:34]
node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_853 = and(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_854 = and(_T_853, _T_849) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_855 = and(_T_854, _T_851) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_856 = and(_T_855, _T_852) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_862 = eq(_T_861, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_865 = and(_T_858, _T_860) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_866 = and(_T_865, _T_862) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_867 = and(_T_866, _T_863) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_868 = and(_T_867, _T_864) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_869 = or(_T_856, _T_868) @[el2_dec_tlu_ctl.scala 2720:81]
node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_874 = eq(_T_873, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_876 = and(_T_871, _T_872) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_877 = and(_T_876, _T_874) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_878 = and(_T_877, _T_875) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_879 = or(_T_869, _T_878) @[el2_dec_tlu_ctl.scala 2720:121]
node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_886 = and(_T_880, _T_882) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_887 = and(_T_886, _T_884) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_888 = and(_T_887, _T_885) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_889 = or(_T_879, _T_888) @[el2_dec_tlu_ctl.scala 2720:162]
node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_893 = eq(_T_892, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_897 = eq(_T_896, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_904 = and(_T_891, _T_893) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_905 = and(_T_904, _T_895) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_906 = and(_T_905, _T_897) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_907 = and(_T_906, _T_899) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_908 = and(_T_907, _T_901) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_909 = and(_T_908, _T_903) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_910 = or(_T_889, _T_909) @[el2_dec_tlu_ctl.scala 2721:105]
node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_912 = eq(_T_911, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_918 = eq(_T_917, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_921 = and(_T_912, _T_913) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_922 = and(_T_921, _T_914) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_923 = and(_T_922, _T_916) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_924 = and(_T_923, _T_918) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_925 = and(_T_924, _T_920) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_926 = or(_T_910, _T_925) @[el2_dec_tlu_ctl.scala 2721:145]
node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_931 = eq(_T_930, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_935 = and(_T_927, _T_929) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_936 = and(_T_935, _T_931) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_937 = and(_T_936, _T_933) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_938 = and(_T_937, _T_934) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_939 = or(_T_926, _T_938) @[el2_dec_tlu_ctl.scala 2721:178]
io.csr_pkt.postsync <= _T_939 @[el2_dec_tlu_ctl.scala 2720:30]
node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_955 = and(_T_941, _T_942) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_956 = and(_T_955, _T_943) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_957 = and(_T_956, _T_944) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_958 = and(_T_957, _T_945) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_959 = and(_T_958, _T_946) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_960 = and(_T_959, _T_947) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_961 = and(_T_960, _T_949) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_962 = and(_T_961, _T_951) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_963 = and(_T_962, _T_952) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_964 = and(_T_963, _T_954) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_966 = eq(_T_965, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_976 = eq(_T_975, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_983 = and(_T_966, _T_968) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_984 = and(_T_983, _T_969) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_985 = and(_T_984, _T_970) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_986 = and(_T_985, _T_972) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_987 = and(_T_986, _T_974) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_988 = and(_T_987, _T_976) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_989 = and(_T_988, _T_978) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_990 = and(_T_989, _T_980) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_991 = and(_T_990, _T_982) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_992 = or(_T_964, _T_991) @[el2_dec_tlu_ctl.scala 2723:81]
node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1000 = eq(_T_999, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1008 = and(_T_994, _T_996) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1009 = and(_T_1008, _T_997) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1010 = and(_T_1009, _T_998) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1011 = and(_T_1010, _T_1000) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1012 = and(_T_1011, _T_1002) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1013 = and(_T_1012, _T_1003) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1014 = and(_T_1013, _T_1005) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1015 = and(_T_1014, _T_1007) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1016 = or(_T_992, _T_1015) @[el2_dec_tlu_ctl.scala 2723:129]
node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1032 = and(_T_1017, _T_1018) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1033 = and(_T_1032, _T_1019) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1034 = and(_T_1033, _T_1020) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1035 = and(_T_1034, _T_1021) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1036 = and(_T_1035, _T_1023) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1037 = and(_T_1036, _T_1025) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1038 = and(_T_1037, _T_1027) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1039 = and(_T_1038, _T_1029) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1040 = and(_T_1039, _T_1031) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1041 = or(_T_1016, _T_1040) @[el2_dec_tlu_ctl.scala 2724:105]
node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1053 = and(_T_1042, _T_1044) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1054 = and(_T_1053, _T_1045) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1055 = and(_T_1054, _T_1046) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1056 = and(_T_1055, _T_1048) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1057 = and(_T_1056, _T_1050) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1058 = and(_T_1057, _T_1052) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1059 = or(_T_1041, _T_1058) @[el2_dec_tlu_ctl.scala 2724:153]
node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1073 = and(_T_1061, _T_1062) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1074 = and(_T_1073, _T_1063) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1075 = and(_T_1074, _T_1064) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1076 = and(_T_1075, _T_1065) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1077 = and(_T_1076, _T_1066) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1078 = and(_T_1077, _T_1067) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1079 = and(_T_1078, _T_1068) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1080 = and(_T_1079, _T_1069) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1081 = and(_T_1080, _T_1070) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1082 = and(_T_1081, _T_1071) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1083 = and(_T_1082, _T_1072) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1084 = or(_T_1059, _T_1083) @[el2_dec_tlu_ctl.scala 2725:105]
node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1098 = and(_T_1086, _T_1087) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1099 = and(_T_1098, _T_1088) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1100 = and(_T_1099, _T_1089) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1101 = and(_T_1100, _T_1090) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1102 = and(_T_1101, _T_1091) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1103 = and(_T_1102, _T_1092) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1104 = and(_T_1103, _T_1093) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1105 = and(_T_1104, _T_1095) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1106 = and(_T_1105, _T_1097) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1107 = or(_T_1084, _T_1106) @[el2_dec_tlu_ctl.scala 2725:153]
node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1123 = and(_T_1108, _T_1109) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1124 = and(_T_1123, _T_1110) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1125 = and(_T_1124, _T_1112) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1126 = and(_T_1125, _T_1114) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1127 = and(_T_1126, _T_1116) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1128 = and(_T_1127, _T_1117) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1129 = and(_T_1128, _T_1119) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1130 = and(_T_1129, _T_1121) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1131 = and(_T_1130, _T_1122) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1132 = or(_T_1107, _T_1131) @[el2_dec_tlu_ctl.scala 2726:105]
node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1148 = and(_T_1134, _T_1135) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1149 = and(_T_1148, _T_1136) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1150 = and(_T_1149, _T_1137) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1151 = and(_T_1150, _T_1138) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1152 = and(_T_1151, _T_1140) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1153 = and(_T_1152, _T_1141) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1154 = and(_T_1153, _T_1143) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1155 = and(_T_1154, _T_1145) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1156 = and(_T_1155, _T_1147) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1157 = or(_T_1132, _T_1156) @[el2_dec_tlu_ctl.scala 2726:161]
node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1170 = and(_T_1159, _T_1161) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1171 = and(_T_1170, _T_1162) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1172 = and(_T_1171, _T_1163) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1173 = and(_T_1172, _T_1165) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1174 = and(_T_1173, _T_1167) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1175 = and(_T_1174, _T_1168) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1176 = and(_T_1175, _T_1169) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1177 = or(_T_1157, _T_1176) @[el2_dec_tlu_ctl.scala 2727:105]
node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1195 = and(_T_1178, _T_1179) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1196 = and(_T_1195, _T_1180) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1197 = and(_T_1196, _T_1182) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1198 = and(_T_1197, _T_1184) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1199 = and(_T_1198, _T_1186) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1200 = and(_T_1199, _T_1187) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1201 = and(_T_1200, _T_1189) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1202 = and(_T_1201, _T_1190) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1203 = and(_T_1202, _T_1192) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1204 = and(_T_1203, _T_1194) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1205 = or(_T_1177, _T_1204) @[el2_dec_tlu_ctl.scala 2727:161]
node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1219 = and(_T_1207, _T_1208) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1220 = and(_T_1219, _T_1209) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1221 = and(_T_1220, _T_1210) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1222 = and(_T_1221, _T_1211) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1223 = and(_T_1222, _T_1212) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1224 = and(_T_1223, _T_1214) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1225 = and(_T_1224, _T_1216) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1226 = and(_T_1225, _T_1217) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1227 = and(_T_1226, _T_1218) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1228 = or(_T_1205, _T_1227) @[el2_dec_tlu_ctl.scala 2728:97]
node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1242 = and(_T_1230, _T_1231) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1243 = and(_T_1242, _T_1232) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1244 = and(_T_1243, _T_1233) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1245 = and(_T_1244, _T_1234) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1246 = and(_T_1245, _T_1235) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1247 = and(_T_1246, _T_1237) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1248 = and(_T_1247, _T_1238) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1249 = and(_T_1248, _T_1240) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1250 = and(_T_1249, _T_1241) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1251 = or(_T_1228, _T_1250) @[el2_dec_tlu_ctl.scala 2728:153]
node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1267 = and(_T_1252, _T_1253) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1268 = and(_T_1267, _T_1254) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1269 = and(_T_1268, _T_1256) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1270 = and(_T_1269, _T_1258) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1271 = and(_T_1270, _T_1260) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1272 = and(_T_1271, _T_1261) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1273 = and(_T_1272, _T_1263) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1274 = and(_T_1273, _T_1265) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1275 = and(_T_1274, _T_1266) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1276 = or(_T_1251, _T_1275) @[el2_dec_tlu_ctl.scala 2729:105]
node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1290 = and(_T_1278, _T_1280) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1291 = and(_T_1290, _T_1281) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1292 = and(_T_1291, _T_1282) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1293 = and(_T_1292, _T_1284) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1294 = and(_T_1293, _T_1286) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1295 = and(_T_1294, _T_1287) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1296 = and(_T_1295, _T_1288) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1297 = and(_T_1296, _T_1289) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1298 = or(_T_1276, _T_1297) @[el2_dec_tlu_ctl.scala 2729:161]
node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1312 = and(_T_1299, _T_1301) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1313 = and(_T_1312, _T_1302) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1314 = and(_T_1313, _T_1303) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1315 = and(_T_1314, _T_1304) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1316 = and(_T_1315, _T_1306) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1317 = and(_T_1316, _T_1308) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1318 = and(_T_1317, _T_1309) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1319 = and(_T_1318, _T_1311) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1320 = or(_T_1298, _T_1319) @[el2_dec_tlu_ctl.scala 2730:105]
node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1336 = and(_T_1321, _T_1323) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1337 = and(_T_1336, _T_1324) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1338 = and(_T_1337, _T_1325) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1339 = and(_T_1338, _T_1326) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1340 = and(_T_1339, _T_1328) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1341 = and(_T_1340, _T_1330) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1342 = and(_T_1341, _T_1331) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1343 = and(_T_1342, _T_1333) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1344 = and(_T_1343, _T_1335) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1345 = or(_T_1320, _T_1344) @[el2_dec_tlu_ctl.scala 2730:161]
node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1356 = and(_T_1346, _T_1348) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1357 = and(_T_1356, _T_1349) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1358 = and(_T_1357, _T_1350) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1359 = and(_T_1358, _T_1352) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1360 = and(_T_1359, _T_1354) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1361 = and(_T_1360, _T_1355) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1362 = or(_T_1345, _T_1361) @[el2_dec_tlu_ctl.scala 2731:105]
node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1376 = and(_T_1364, _T_1365) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1377 = and(_T_1376, _T_1366) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1378 = and(_T_1377, _T_1367) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1379 = and(_T_1378, _T_1368) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1380 = and(_T_1379, _T_1369) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1381 = and(_T_1380, _T_1371) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1382 = and(_T_1381, _T_1372) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1383 = and(_T_1382, _T_1374) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1384 = and(_T_1383, _T_1375) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1385 = or(_T_1362, _T_1384) @[el2_dec_tlu_ctl.scala 2731:161]
node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1399 = and(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1400 = and(_T_1399, _T_1389) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1401 = and(_T_1400, _T_1390) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1402 = and(_T_1401, _T_1391) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1403 = and(_T_1402, _T_1392) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1404 = and(_T_1403, _T_1394) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1405 = and(_T_1404, _T_1396) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1406 = and(_T_1405, _T_1398) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1407 = or(_T_1385, _T_1406) @[el2_dec_tlu_ctl.scala 2732:105]
node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1422 = and(_T_1409, _T_1410) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1423 = and(_T_1422, _T_1411) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1424 = and(_T_1423, _T_1412) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1425 = and(_T_1424, _T_1413) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1426 = and(_T_1425, _T_1414) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1427 = and(_T_1426, _T_1416) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1428 = and(_T_1427, _T_1418) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1429 = and(_T_1428, _T_1419) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1430 = and(_T_1429, _T_1421) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1431 = or(_T_1407, _T_1430) @[el2_dec_tlu_ctl.scala 2732:161]
node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1449 = and(_T_1433, _T_1434) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1450 = and(_T_1449, _T_1435) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1451 = and(_T_1450, _T_1436) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1452 = and(_T_1451, _T_1437) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1453 = and(_T_1452, _T_1439) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1454 = and(_T_1453, _T_1440) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1455 = and(_T_1454, _T_1442) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1456 = and(_T_1455, _T_1444) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1457 = and(_T_1456, _T_1446) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1458 = and(_T_1457, _T_1448) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1459 = or(_T_1431, _T_1458) @[el2_dec_tlu_ctl.scala 2733:105]
node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1470 = and(_T_1460, _T_1462) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1471 = and(_T_1470, _T_1463) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1472 = and(_T_1471, _T_1464) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1473 = and(_T_1472, _T_1466) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1474 = and(_T_1473, _T_1468) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1475 = and(_T_1474, _T_1469) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1476 = or(_T_1459, _T_1475) @[el2_dec_tlu_ctl.scala 2733:153]
node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1494 = and(_T_1478, _T_1480) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1495 = and(_T_1494, _T_1481) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1496 = and(_T_1495, _T_1482) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1497 = and(_T_1496, _T_1484) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1498 = and(_T_1497, _T_1485) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1499 = and(_T_1498, _T_1487) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1500 = and(_T_1499, _T_1489) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1501 = and(_T_1500, _T_1491) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1502 = and(_T_1501, _T_1493) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1503 = or(_T_1476, _T_1502) @[el2_dec_tlu_ctl.scala 2734:113]
node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2650:185]
node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:165]
node _T_1522 = and(_T_1505, _T_1507) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1523 = and(_T_1522, _T_1508) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1524 = and(_T_1523, _T_1509) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1525 = and(_T_1524, _T_1511) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1526 = and(_T_1525, _T_1513) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1527 = and(_T_1526, _T_1515) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1528 = and(_T_1527, _T_1517) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1529 = and(_T_1528, _T_1519) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1530 = and(_T_1529, _T_1521) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1531 = or(_T_1503, _T_1530) @[el2_dec_tlu_ctl.scala 2734:161]
node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1544 = and(_T_1533, _T_1535) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1545 = and(_T_1544, _T_1536) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1546 = and(_T_1545, _T_1537) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1547 = and(_T_1546, _T_1539) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1548 = and(_T_1547, _T_1541) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1549 = and(_T_1548, _T_1542) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1550 = and(_T_1549, _T_1543) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1551 = or(_T_1531, _T_1550) @[el2_dec_tlu_ctl.scala 2735:97]
node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1562 = and(_T_1552, _T_1554) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1563 = and(_T_1562, _T_1555) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1564 = and(_T_1563, _T_1556) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1565 = and(_T_1564, _T_1558) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1566 = and(_T_1565, _T_1560) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1567 = and(_T_1566, _T_1561) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1568 = or(_T_1551, _T_1567) @[el2_dec_tlu_ctl.scala 2735:153]
node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1581 = and(_T_1570, _T_1572) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1582 = and(_T_1581, _T_1573) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1583 = and(_T_1582, _T_1574) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1584 = and(_T_1583, _T_1576) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1585 = and(_T_1584, _T_1578) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1586 = and(_T_1585, _T_1579) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1587 = and(_T_1586, _T_1580) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1588 = or(_T_1568, _T_1587) @[el2_dec_tlu_ctl.scala 2736:113]
node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2650:149]
node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2650:129]
node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2650:106]
node _T_1599 = and(_T_1589, _T_1591) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1600 = and(_T_1599, _T_1592) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1601 = and(_T_1600, _T_1593) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1602 = and(_T_1601, _T_1595) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1603 = and(_T_1602, _T_1597) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1604 = and(_T_1603, _T_1598) @[el2_dec_tlu_ctl.scala 2650:198]
node _T_1605 = or(_T_1588, _T_1604) @[el2_dec_tlu_ctl.scala 2736:169]
io.csr_pkt.legal <= _T_1605 @[el2_dec_tlu_ctl.scala 2723:26]
module el2_dec_tlu_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}}
wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 233:67]
wire pause_expired_wb : UInt<1>
pause_expired_wb <= UInt<1>("h00")
wire take_nmi_r_d1 : UInt<1>
take_nmi_r_d1 <= UInt<1>("h00")
wire exc_or_int_valid_r_d1 : UInt<1>
exc_or_int_valid_r_d1 <= UInt<1>("h00")
wire interrupt_valid_r_d1 : UInt<1>
interrupt_valid_r_d1 <= UInt<1>("h00")
wire tlu_flush_lower_r : UInt<1>
tlu_flush_lower_r <= UInt<1>("h00")
wire synchronous_flush_r : UInt<1>
synchronous_flush_r <= UInt<1>("h00")
wire interrupt_valid_r : UInt<1>
interrupt_valid_r <= UInt<1>("h00")
wire take_nmi : UInt<1>
take_nmi <= UInt<1>("h00")
wire take_reset : UInt<1>
take_reset <= UInt<1>("h00")
wire take_int_timer1_int : UInt<1>
take_int_timer1_int <= UInt<1>("h00")
wire take_int_timer0_int : UInt<1>
take_int_timer0_int <= UInt<1>("h00")
wire take_timer_int : UInt<1>
take_timer_int <= UInt<1>("h00")
wire take_soft_int : UInt<1>
take_soft_int <= UInt<1>("h00")
wire take_ce_int : UInt<1>
take_ce_int <= UInt<1>("h00")
wire take_ext_int_start : UInt<1>
take_ext_int_start <= UInt<1>("h00")
wire ext_int_freeze : UInt<1>
ext_int_freeze <= UInt<1>("h00")
wire ext_int_freeze_d1 : UInt<1>
ext_int_freeze_d1 <= UInt<1>("h00")
wire take_ext_int_start_d1 : UInt<1>
take_ext_int_start_d1 <= UInt<1>("h00")
wire take_ext_int_start_d2 : UInt<1>
take_ext_int_start_d2 <= UInt<1>("h00")
wire take_ext_int_start_d3 : UInt<1>
take_ext_int_start_d3 <= UInt<1>("h00")
wire fast_int_meicpct : UInt<1>
fast_int_meicpct <= UInt<1>("h00")
wire ignore_ext_int_due_to_lsu_stall : UInt<1>
ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00")
wire take_ext_int : UInt<1>
take_ext_int <= UInt<1>("h00")
wire internal_dbg_halt_timers : UInt<1>
internal_dbg_halt_timers <= UInt<1>("h00")
wire int_timer1_int_hold : UInt<1>
int_timer1_int_hold <= UInt<1>("h00")
wire int_timer0_int_hold : UInt<1>
int_timer0_int_hold <= UInt<1>("h00")
wire mhwakeup_ready : UInt<1>
mhwakeup_ready <= UInt<1>("h00")
wire ext_int_ready : UInt<1>
ext_int_ready <= UInt<1>("h00")
wire ce_int_ready : UInt<1>
ce_int_ready <= UInt<1>("h00")
wire soft_int_ready : UInt<1>
soft_int_ready <= UInt<1>("h00")
wire timer_int_ready : UInt<1>
timer_int_ready <= UInt<1>("h00")
wire ebreak_to_debug_mode_r_d1 : UInt<1>
ebreak_to_debug_mode_r_d1 <= UInt<1>("h00")
wire ebreak_to_debug_mode_r : UInt<1>
ebreak_to_debug_mode_r <= UInt<1>("h00")
wire inst_acc_r : UInt<1>
inst_acc_r <= UInt<1>("h00")
wire inst_acc_r_raw : UInt<1>
inst_acc_r_raw <= UInt<1>("h00")
wire iccm_sbecc_r : UInt<1>
iccm_sbecc_r <= UInt<1>("h00")
wire ic_perr_r : UInt<1>
ic_perr_r <= UInt<1>("h00")
wire fence_i_r : UInt<1>
fence_i_r <= UInt<1>("h00")
wire ebreak_r : UInt<1>
ebreak_r <= UInt<1>("h00")
wire ecall_r : UInt<1>
ecall_r <= UInt<1>("h00")
wire illegal_r : UInt<1>
illegal_r <= UInt<1>("h00")
wire mret_r : UInt<1>
mret_r <= UInt<1>("h00")
wire iccm_repair_state_ns : UInt<1>
iccm_repair_state_ns <= UInt<1>("h00")
wire rfpc_i0_r : UInt<1>
rfpc_i0_r <= UInt<1>("h00")
wire tlu_i0_kill_writeb_r : UInt<1>
tlu_i0_kill_writeb_r <= UInt<1>("h00")
wire lsu_exc_valid_r_d1 : UInt<1>
lsu_exc_valid_r_d1 <= UInt<1>("h00")
wire lsu_i0_exc_r_raw : UInt<1>
lsu_i0_exc_r_raw <= UInt<1>("h00")
wire mdseac_locked_f : UInt<1>
mdseac_locked_f <= UInt<1>("h00")
wire i_cpu_run_req_d1 : UInt<1>
i_cpu_run_req_d1 <= UInt<1>("h00")
wire cpu_run_ack : UInt<1>
cpu_run_ack <= UInt<1>("h00")
wire cpu_halt_status : UInt<1>
cpu_halt_status <= UInt<1>("h00")
wire cpu_halt_ack : UInt<1>
cpu_halt_ack <= UInt<1>("h00")
wire pmu_fw_tlu_halted : UInt<1>
pmu_fw_tlu_halted <= UInt<1>("h00")
wire internal_pmu_fw_halt_mode : UInt<1>
internal_pmu_fw_halt_mode <= UInt<1>("h00")
wire pmu_fw_halt_req_ns : UInt<1>
pmu_fw_halt_req_ns <= UInt<1>("h00")
wire pmu_fw_halt_req_f : UInt<1>
pmu_fw_halt_req_f <= UInt<1>("h00")
wire pmu_fw_tlu_halted_f : UInt<1>
pmu_fw_tlu_halted_f <= UInt<1>("h00")
wire int_timer0_int_hold_f : UInt<1>
int_timer0_int_hold_f <= UInt<1>("h00")
wire int_timer1_int_hold_f : UInt<1>
int_timer1_int_hold_f <= UInt<1>("h00")
wire trigger_hit_dmode_r : UInt<1>
trigger_hit_dmode_r <= UInt<1>("h00")
wire i0_trigger_hit_r : UInt<1>
i0_trigger_hit_r <= UInt<1>("h00")
wire pause_expired_r : UInt<1>
pause_expired_r <= UInt<1>("h00")
wire dec_tlu_pmu_fw_halted : UInt<1>
dec_tlu_pmu_fw_halted <= UInt<1>("h00")
wire dec_tlu_flush_noredir_r_d1 : UInt<1>
dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00")
wire halt_taken_f : UInt<1>
halt_taken_f <= UInt<1>("h00")
wire lsu_idle_any_f : UInt<1>
lsu_idle_any_f <= UInt<1>("h00")
wire ifu_miss_state_idle_f : UInt<1>
ifu_miss_state_idle_f <= UInt<1>("h00")
wire dbg_tlu_halted_f : UInt<1>
dbg_tlu_halted_f <= UInt<1>("h00")
wire debug_halt_req_f : UInt<1>
debug_halt_req_f <= UInt<1>("h00")
wire debug_resume_req_f : UInt<1>
debug_resume_req_f <= UInt<1>("h00")
wire trigger_hit_dmode_r_d1 : UInt<1>
trigger_hit_dmode_r_d1 <= UInt<1>("h00")
wire dcsr_single_step_done_f : UInt<1>
dcsr_single_step_done_f <= UInt<1>("h00")
wire debug_halt_req_d1 : UInt<1>
debug_halt_req_d1 <= UInt<1>("h00")
wire request_debug_mode_r_d1 : UInt<1>
request_debug_mode_r_d1 <= UInt<1>("h00")
wire request_debug_mode_done_f : UInt<1>
request_debug_mode_done_f <= UInt<1>("h00")
wire dcsr_single_step_running_f : UInt<1>
dcsr_single_step_running_f <= UInt<1>("h00")
wire dec_tlu_flush_pause_r_d1 : UInt<1>
dec_tlu_flush_pause_r_d1 <= UInt<1>("h00")
wire dbg_halt_req_held : UInt<1>
dbg_halt_req_held <= UInt<1>("h00")
wire debug_halt_req_ns : UInt<1>
debug_halt_req_ns <= UInt<1>("h00")
wire internal_dbg_halt_mode : UInt<1>
internal_dbg_halt_mode <= UInt<1>("h00")
wire core_empty : UInt<1>
core_empty <= UInt<1>("h00")
wire dbg_halt_req_final : UInt<1>
dbg_halt_req_final <= UInt<1>("h00")
wire debug_brkpt_status_ns : UInt<1>
debug_brkpt_status_ns <= UInt<1>("h00")
wire mpc_debug_halt_ack_ns : UInt<1>
mpc_debug_halt_ack_ns <= UInt<1>("h00")
wire mpc_debug_run_ack_ns : UInt<1>
mpc_debug_run_ack_ns <= UInt<1>("h00")
wire mpc_halt_state_ns : UInt<1>
mpc_halt_state_ns <= UInt<1>("h00")
wire mpc_run_state_ns : UInt<1>
mpc_run_state_ns <= UInt<1>("h00")
wire dbg_halt_state_ns : UInt<1>
dbg_halt_state_ns <= UInt<1>("h00")
wire dbg_run_state_ns : UInt<1>
dbg_run_state_ns <= UInt<1>("h00")
wire dbg_halt_state_f : UInt<1>
dbg_halt_state_f <= UInt<1>("h00")
wire mpc_halt_state_f : UInt<1>
mpc_halt_state_f <= UInt<1>("h00")
wire nmi_int_detected : UInt<1>
nmi_int_detected <= UInt<1>("h00")
wire nmi_lsu_load_type : UInt<1>
nmi_lsu_load_type <= UInt<1>("h00")
wire nmi_lsu_store_type : UInt<1>
nmi_lsu_store_type <= UInt<1>("h00")
wire reset_delayed : UInt<1>
reset_delayed <= UInt<1>("h00")
wire debug_mode_status : UInt<1>
debug_mode_status <= UInt<1>("h00")
wire e5_valid : UInt<1>
e5_valid <= UInt<1>("h00")
wire ic_perr_r_d1 : UInt<1>
ic_perr_r_d1 <= UInt<1>("h00")
wire iccm_sbecc_r_d1 : UInt<1>
iccm_sbecc_r_d1 <= UInt<1>("h00")
wire npc_r : UInt<31>
npc_r <= UInt<1>("h00")
wire npc_r_d1 : UInt<31>
npc_r_d1 <= UInt<1>("h00")
wire mie_ns : UInt<6>
mie_ns <= UInt<1>("h00")
wire mepc : UInt<31>
mepc <= UInt<1>("h00")
wire mdseac_locked_ns : UInt<1>
mdseac_locked_ns <= UInt<1>("h00")
wire force_halt : UInt<1>
force_halt <= UInt<1>("h00")
wire dpc : UInt<31>
dpc <= UInt<1>("h00")
wire mstatus_mie_ns : UInt<1>
mstatus_mie_ns <= UInt<1>("h00")
wire dec_csr_wen_r_mod : UInt<1>
dec_csr_wen_r_mod <= UInt<1>("h00")
wire fw_halt_req : UInt<1>
fw_halt_req <= UInt<1>("h00")
wire mstatus : UInt<2>
mstatus <= UInt<1>("h00")
wire dcsr : UInt<16>
dcsr <= UInt<1>("h00")
wire mtvec : UInt<31>
mtvec <= UInt<1>("h00")
wire mip : UInt<6>
mip <= UInt<1>("h00")
wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 348:41]
wire dec_tlu_mpc_halted_only_ns : UInt<1>
dec_tlu_mpc_halted_only_ns <= UInt<1>("h00")
node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 351:39]
node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 351:57]
dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 351:36]
inst int_timers of el2_dec_timer_ctl @[el2_dec_tlu_ctl.scala 352:30]
int_timers.clock <= clock
int_timers.reset <= reset
int_timers.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 353:57]
int_timers.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 354:57]
int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 355:49]
int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 356:49]
int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 357:49]
int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 358:49]
int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 359:57]
int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 360:57]
int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 361:57]
int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 362:57]
int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 363:57]
int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 364:57]
int_timers.io.dec_pause_state <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 365:49]
int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 366:49]
int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[el2_dec_tlu_ctl.scala 367:47]
node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58]
node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58]
node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58]
node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58]
node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58]
node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58]
reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81]
_T_8 <= _T_7 @[el2_lib.scala 177:81]
reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58]
syncro_ff <= _T_8 @[el2_lib.scala 177:58]
node nmi_int_sync = bits(syncro_ff, 6, 6) @[el2_dec_tlu_ctl.scala 379:67]
node timer_int_sync = bits(syncro_ff, 5, 5) @[el2_dec_tlu_ctl.scala 380:59]
node soft_int_sync = bits(syncro_ff, 4, 4) @[el2_dec_tlu_ctl.scala 381:59]
node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[el2_dec_tlu_ctl.scala 382:59]
node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[el2_dec_tlu_ctl.scala 383:59]
node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[el2_dec_tlu_ctl.scala 384:51]
node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[el2_dec_tlu_ctl.scala 385:51]
node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 388:58]
node _T_10 = bits(_T_9, 0, 0) @[el2_dec_tlu_ctl.scala 388:74]
inst rvclkhdr of rvclkhdr_4 @[el2_lib.scala 483:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr.io.en <= _T_10 @[el2_lib.scala 485:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[el2_dec_tlu_ctl.scala 389:67]
node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 389:88]
node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 389:104]
inst rvclkhdr_1 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[el2_dec_tlu_ctl.scala 392:30]
node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 393:50]
node _T_15 = or(_T_14, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 393:69]
node _T_16 = or(_T_15, interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 393:89]
node _T_17 = or(_T_16, reset_delayed) @[el2_dec_tlu_ctl.scala 393:112]
node _T_18 = or(_T_17, pause_expired_r) @[el2_dec_tlu_ctl.scala 393:128]
node _T_19 = or(_T_18, pause_expired_wb) @[el2_dec_tlu_ctl.scala 393:146]
node _T_20 = or(_T_19, ic_perr_r) @[el2_dec_tlu_ctl.scala 393:165]
node _T_21 = or(_T_20, ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 393:177]
node _T_22 = or(_T_21, iccm_sbecc_r) @[el2_dec_tlu_ctl.scala 393:192]
node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 393:207]
node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 393:225]
node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 395:49]
node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 395:65]
inst rvclkhdr_2 of rvclkhdr_6 @[el2_lib.scala 483:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
node _T_26 = or(e4e5_valid, flush_clkvalid) @[el2_dec_tlu_ctl.scala 396:53]
node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 396:71]
inst rvclkhdr_3 of rvclkhdr_7 @[el2_lib.scala 483:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 485:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 398:80]
iccm_repair_state_d1 <= iccm_repair_state_ns @[el2_dec_tlu_ctl.scala 398:80]
reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 399:89]
_T_28 <= ic_perr_r @[el2_dec_tlu_ctl.scala 399:89]
ic_perr_r_d1 <= _T_28 @[el2_dec_tlu_ctl.scala 399:57]
reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 400:89]
_T_29 <= iccm_sbecc_r @[el2_dec_tlu_ctl.scala 400:89]
iccm_sbecc_r_d1 <= _T_29 @[el2_dec_tlu_ctl.scala 400:57]
reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 401:97]
_T_30 <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 401:97]
e5_valid <= _T_30 @[el2_dec_tlu_ctl.scala 401:65]
reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 402:81]
_T_31 <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 402:81]
debug_mode_status <= _T_31 @[el2_dec_tlu_ctl.scala 402:49]
reg lsu_pmu_load_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 403:80]
lsu_pmu_load_external_r <= io.lsu_pmu_load_external_m @[el2_dec_tlu_ctl.scala 403:80]
reg lsu_pmu_store_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 404:72]
lsu_pmu_store_external_r <= io.lsu_pmu_store_external_m @[el2_dec_tlu_ctl.scala 404:72]
reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 405:80]
tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 405:80]
reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 406:73]
_T_32 <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 406:73]
io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[el2_dec_tlu_ctl.scala 406:41]
reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 407:72]
internal_dbg_halt_mode_f2 <= debug_mode_status @[el2_dec_tlu_ctl.scala 407:72]
reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 408:89]
_T_33 <= force_halt @[el2_dec_tlu_ctl.scala 408:89]
io.tlu_mem.dec_tlu_force_halt <= _T_33 @[el2_dec_tlu_ctl.scala 408:57]
io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 412:41]
reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 413:88]
reset_detect <= UInt<1>("h01") @[el2_dec_tlu_ctl.scala 413:88]
reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 414:88]
reset_detected <= reset_detect @[el2_dec_tlu_ctl.scala 414:88]
node _T_34 = xor(reset_detect, reset_detected) @[el2_dec_tlu_ctl.scala 415:64]
reset_delayed <= _T_34 @[el2_dec_tlu_ctl.scala 415:49]
reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 417:72]
nmi_int_delayed <= nmi_int_sync @[el2_dec_tlu_ctl.scala 417:72]
reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 418:72]
nmi_int_detected_f <= nmi_int_detected @[el2_dec_tlu_ctl.scala 418:72]
reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 419:72]
nmi_lsu_load_type_f <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 419:72]
reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 420:72]
nmi_lsu_store_type_f <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 420:72]
node _T_35 = not(mdseac_locked_f) @[el2_dec_tlu_ctl.scala 424:32]
node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 424:96]
node nmi_lsu_detected = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 424:49]
node _T_37 = not(nmi_int_delayed) @[el2_dec_tlu_ctl.scala 426:45]
node _T_38 = and(nmi_int_sync, _T_37) @[el2_dec_tlu_ctl.scala 426:43]
node _T_39 = or(_T_38, nmi_lsu_detected) @[el2_dec_tlu_ctl.scala 426:63]
node _T_40 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 426:106]
node _T_41 = and(nmi_int_detected_f, _T_40) @[el2_dec_tlu_ctl.scala 426:104]
node _T_42 = or(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 426:82]
node _T_43 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 426:165]
node _T_44 = and(take_ext_int_start_d3, _T_43) @[el2_dec_tlu_ctl.scala 426:146]
node _T_45 = or(_T_42, _T_44) @[el2_dec_tlu_ctl.scala 426:122]
nmi_int_detected <= _T_45 @[el2_dec_tlu_ctl.scala 426:26]
node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 428:48]
node _T_47 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 428:119]
node _T_48 = and(nmi_int_detected_f, _T_47) @[el2_dec_tlu_ctl.scala 428:117]
node _T_49 = not(_T_48) @[el2_dec_tlu_ctl.scala 428:96]
node _T_50 = and(_T_46, _T_49) @[el2_dec_tlu_ctl.scala 428:94]
node _T_51 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 428:161]
node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[el2_dec_tlu_ctl.scala 428:159]
node _T_53 = or(_T_50, _T_52) @[el2_dec_tlu_ctl.scala 428:136]
nmi_lsu_load_type <= _T_53 @[el2_dec_tlu_ctl.scala 428:27]
node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 429:49]
node _T_55 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:121]
node _T_56 = and(nmi_int_detected_f, _T_55) @[el2_dec_tlu_ctl.scala 429:119]
node _T_57 = not(_T_56) @[el2_dec_tlu_ctl.scala 429:98]
node _T_58 = and(_T_54, _T_57) @[el2_dec_tlu_ctl.scala 429:96]
node _T_59 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:164]
node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[el2_dec_tlu_ctl.scala 429:162]
node _T_61 = or(_T_58, _T_60) @[el2_dec_tlu_ctl.scala 429:138]
nmi_lsu_store_type <= _T_61 @[el2_dec_tlu_ctl.scala 429:28]
node _T_62 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 436:69]
node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[el2_dec_tlu_ctl.scala 436:67]
reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 437:72]
mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[el2_dec_tlu_ctl.scala 437:72]
reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 438:72]
mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[el2_dec_tlu_ctl.scala 438:72]
reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 439:89]
_T_63 <= mpc_halt_state_ns @[el2_dec_tlu_ctl.scala 439:89]
mpc_halt_state_f <= _T_63 @[el2_dec_tlu_ctl.scala 439:57]
reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 440:88]
mpc_run_state_f <= mpc_run_state_ns @[el2_dec_tlu_ctl.scala 440:88]
reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 441:80]
debug_brkpt_status_f <= debug_brkpt_status_ns @[el2_dec_tlu_ctl.scala 441:80]
reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 442:80]
mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[el2_dec_tlu_ctl.scala 442:80]
reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 443:80]
mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[el2_dec_tlu_ctl.scala 443:80]
reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 444:89]
_T_64 <= dbg_halt_state_ns @[el2_dec_tlu_ctl.scala 444:89]
dbg_halt_state_f <= _T_64 @[el2_dec_tlu_ctl.scala 444:57]
reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 445:88]
dbg_run_state_f <= dbg_run_state_ns @[el2_dec_tlu_ctl.scala 445:88]
reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 446:81]
_T_65 <= dec_tlu_mpc_halted_only_ns @[el2_dec_tlu_ctl.scala 446:81]
io.dec_tlu_mpc_halted_only <= _T_65 @[el2_dec_tlu_ctl.scala 446:49]
node _T_66 = not(mpc_debug_halt_req_sync_f) @[el2_dec_tlu_ctl.scala 450:71]
node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[el2_dec_tlu_ctl.scala 450:69]
node _T_67 = not(mpc_debug_run_req_sync_f) @[el2_dec_tlu_ctl.scala 451:70]
node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[el2_dec_tlu_ctl.scala 451:68]
node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[el2_dec_tlu_ctl.scala 453:48]
node _T_69 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 453:99]
node _T_70 = and(reset_delayed, _T_69) @[el2_dec_tlu_ctl.scala 453:97]
node _T_71 = or(_T_68, _T_70) @[el2_dec_tlu_ctl.scala 453:80]
node _T_72 = not(mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 453:125]
node _T_73 = and(_T_71, _T_72) @[el2_dec_tlu_ctl.scala 453:123]
mpc_halt_state_ns <= _T_73 @[el2_dec_tlu_ctl.scala 453:27]
node _T_74 = not(mpc_debug_run_ack_f) @[el2_dec_tlu_ctl.scala 454:80]
node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[el2_dec_tlu_ctl.scala 454:78]
node _T_76 = or(mpc_run_state_f, _T_75) @[el2_dec_tlu_ctl.scala 454:46]
node _T_77 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 454:133]
node _T_78 = and(debug_mode_status, _T_77) @[el2_dec_tlu_ctl.scala 454:131]
node _T_79 = and(_T_76, _T_78) @[el2_dec_tlu_ctl.scala 454:103]
mpc_run_state_ns <= _T_79 @[el2_dec_tlu_ctl.scala 454:26]
node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 456:70]
node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 456:96]
node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 456:121]
node _T_83 = or(dbg_halt_state_f, _T_82) @[el2_dec_tlu_ctl.scala 456:48]
node _T_84 = not(io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 456:153]
node _T_85 = and(_T_83, _T_84) @[el2_dec_tlu_ctl.scala 456:151]
dbg_halt_state_ns <= _T_85 @[el2_dec_tlu_ctl.scala 456:27]
node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 457:46]
node _T_87 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 457:97]
node _T_88 = and(debug_mode_status, _T_87) @[el2_dec_tlu_ctl.scala 457:95]
node _T_89 = and(_T_86, _T_88) @[el2_dec_tlu_ctl.scala 457:67]
dbg_run_state_ns <= _T_89 @[el2_dec_tlu_ctl.scala 457:26]
node _T_90 = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 460:39]
node _T_91 = and(_T_90, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 460:57]
dec_tlu_mpc_halted_only_ns <= _T_91 @[el2_dec_tlu_ctl.scala 460:36]
node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 463:59]
node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[el2_dec_tlu_ctl.scala 464:53]
node _T_93 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 464:105]
node _T_94 = and(internal_dbg_halt_mode, _T_93) @[el2_dec_tlu_ctl.scala 464:103]
node _T_95 = and(_T_92, _T_94) @[el2_dec_tlu_ctl.scala 464:77]
debug_brkpt_status_ns <= _T_95 @[el2_dec_tlu_ctl.scala 464:31]
node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[el2_dec_tlu_ctl.scala 467:51]
node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 467:78]
node _T_98 = and(_T_97, core_empty) @[el2_dec_tlu_ctl.scala 467:104]
mpc_debug_halt_ack_ns <= _T_98 @[el2_dec_tlu_ctl.scala 467:31]
node _T_99 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 468:59]
node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[el2_dec_tlu_ctl.scala 468:57]
node _T_101 = not(mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 468:80]
node _T_102 = and(_T_100, _T_101) @[el2_dec_tlu_ctl.scala 468:78]
node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 468:129]
node _T_104 = or(_T_102, _T_103) @[el2_dec_tlu_ctl.scala 468:106]
mpc_debug_run_ack_ns <= _T_104 @[el2_dec_tlu_ctl.scala 468:30]
io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[el2_dec_tlu_ctl.scala 471:31]
io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[el2_dec_tlu_ctl.scala 472:31]
io.debug_brkpt_status <= debug_brkpt_status_f @[el2_dec_tlu_ctl.scala 473:31]
node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 476:53]
node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 476:74]
node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 477:48]
node _T_107 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 477:71]
node _T_108 = and(_T_106, _T_107) @[el2_dec_tlu_ctl.scala 477:69]
dbg_halt_req_final <= _T_108 @[el2_dec_tlu_ctl.scala 477:28]
node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 480:50]
node _T_110 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 480:95]
node _T_111 = and(reset_delayed, _T_110) @[el2_dec_tlu_ctl.scala 480:93]
node _T_112 = or(_T_109, _T_111) @[el2_dec_tlu_ctl.scala 480:76]
node _T_113 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 480:121]
node _T_114 = and(_T_112, _T_113) @[el2_dec_tlu_ctl.scala 480:119]
node _T_115 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 480:149]
node debug_halt_req = and(_T_114, _T_115) @[el2_dec_tlu_ctl.scala 480:147]
node _T_116 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 482:32]
node _T_117 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 482:75]
node _T_118 = and(mpc_run_state_ns, _T_117) @[el2_dec_tlu_ctl.scala 482:73]
node _T_119 = not(mpc_halt_state_ns) @[el2_dec_tlu_ctl.scala 482:117]
node _T_120 = and(dbg_run_state_ns, _T_119) @[el2_dec_tlu_ctl.scala 482:115]
node _T_121 = or(_T_118, _T_120) @[el2_dec_tlu_ctl.scala 482:95]
node debug_resume_req = and(_T_116, _T_121) @[el2_dec_tlu_ctl.scala 482:52]
node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 487:43]
node _T_123 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 487:66]
node _T_124 = and(_T_122, _T_123) @[el2_dec_tlu_ctl.scala 487:64]
node _T_125 = not(mret_r) @[el2_dec_tlu_ctl.scala 487:89]
node _T_126 = and(_T_124, _T_125) @[el2_dec_tlu_ctl.scala 487:87]
node _T_127 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 487:99]
node _T_128 = and(_T_126, _T_127) @[el2_dec_tlu_ctl.scala 487:97]
node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[el2_dec_tlu_ctl.scala 487:115]
node _T_130 = and(_T_128, _T_129) @[el2_dec_tlu_ctl.scala 487:113]
node _T_131 = not(take_reset) @[el2_dec_tlu_ctl.scala 487:145]
node take_halt = and(_T_130, _T_131) @[el2_dec_tlu_ctl.scala 487:143]
node _T_132 = not(dec_tlu_flush_pause_r_d1) @[el2_dec_tlu_ctl.scala 490:56]
node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[el2_dec_tlu_ctl.scala 490:54]
node _T_134 = not(take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 490:84]
node _T_135 = and(_T_133, _T_134) @[el2_dec_tlu_ctl.scala 490:82]
node _T_136 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 490:126]
node _T_137 = and(halt_taken_f, _T_136) @[el2_dec_tlu_ctl.scala 490:124]
node _T_138 = not(pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 490:146]
node _T_139 = and(_T_137, _T_138) @[el2_dec_tlu_ctl.scala 490:144]
node _T_140 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 490:169]
node _T_141 = and(_T_139, _T_140) @[el2_dec_tlu_ctl.scala 490:167]
node halt_taken = or(_T_135, _T_141) @[el2_dec_tlu_ctl.scala 490:108]
node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 494:53]
node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[el2_dec_tlu_ctl.scala 494:70]
node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 494:103]
node _T_145 = not(debug_halt_req) @[el2_dec_tlu_ctl.scala 494:129]
node _T_146 = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 494:127]
node _T_147 = not(debug_halt_req_d1) @[el2_dec_tlu_ctl.scala 494:147]
node _T_148 = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 494:145]
node _T_149 = not(io.dec_div_active) @[el2_dec_tlu_ctl.scala 494:168]
node _T_150 = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 494:166]
node _T_151 = or(force_halt, _T_150) @[el2_dec_tlu_ctl.scala 494:34]
core_empty <= _T_151 @[el2_dec_tlu_ctl.scala 494:20]
node _T_152 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 500:37]
node _T_153 = and(_T_152, debug_halt_req) @[el2_dec_tlu_ctl.scala 500:63]
node _T_154 = or(_T_153, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 500:81]
node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 500:107]
node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 500:132]
node _T_156 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 503:111]
node _T_157 = not(_T_156) @[el2_dec_tlu_ctl.scala 503:106]
node _T_158 = and(debug_resume_req_f, _T_157) @[el2_dec_tlu_ctl.scala 503:104]
node _T_159 = not(_T_158) @[el2_dec_tlu_ctl.scala 503:83]
node _T_160 = and(debug_mode_status, _T_159) @[el2_dec_tlu_ctl.scala 503:81]
node _T_161 = or(debug_halt_req_ns, _T_160) @[el2_dec_tlu_ctl.scala 503:53]
internal_dbg_halt_mode <= _T_161 @[el2_dec_tlu_ctl.scala 503:32]
node _T_162 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 505:67]
node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[el2_dec_tlu_ctl.scala 505:65]
node _T_163 = and(debug_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 510:48]
node _T_164 = and(_T_163, halt_taken) @[el2_dec_tlu_ctl.scala 510:61]
node _T_165 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 510:97]
node _T_166 = and(dbg_tlu_halted_f, _T_165) @[el2_dec_tlu_ctl.scala 510:95]
node dbg_tlu_halted = or(_T_164, _T_166) @[el2_dec_tlu_ctl.scala 510:75]
node _T_167 = not(dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 511:73]
node _T_168 = and(debug_halt_req_f, _T_167) @[el2_dec_tlu_ctl.scala 511:71]
node _T_169 = or(enter_debug_halt_req, _T_168) @[el2_dec_tlu_ctl.scala 511:51]
debug_halt_req_ns <= _T_169 @[el2_dec_tlu_ctl.scala 511:27]
node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 512:49]
node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[el2_dec_tlu_ctl.scala 512:68]
node _T_171 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 514:61]
node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[el2_dec_tlu_ctl.scala 514:59]
node _T_173 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 514:90]
node _T_174 = and(_T_172, _T_173) @[el2_dec_tlu_ctl.scala 514:84]
node _T_175 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 514:104]
node dcsr_single_step_done = and(_T_174, _T_175) @[el2_dec_tlu_ctl.scala 514:102]
node _T_176 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 516:66]
node _T_177 = and(debug_resume_req_f, _T_176) @[el2_dec_tlu_ctl.scala 516:60]
node _T_178 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 516:111]
node _T_179 = and(dcsr_single_step_running_f, _T_178) @[el2_dec_tlu_ctl.scala 516:109]
node dcsr_single_step_running = or(_T_177, _T_179) @[el2_dec_tlu_ctl.scala 516:79]
node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 518:53]
node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 521:57]
node _T_181 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 521:112]
node _T_182 = and(request_debug_mode_r_d1, _T_181) @[el2_dec_tlu_ctl.scala 521:110]
node request_debug_mode_r = or(_T_180, _T_182) @[el2_dec_tlu_ctl.scala 521:83]
node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[el2_dec_tlu_ctl.scala 523:64]
node _T_184 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 523:95]
node request_debug_mode_done = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 523:93]
reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 526:81]
_T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[el2_dec_tlu_ctl.scala 526:81]
dec_tlu_flush_noredir_r_d1 <= _T_185 @[el2_dec_tlu_ctl.scala 526:49]
reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 527:89]
_T_186 <= halt_taken @[el2_dec_tlu_ctl.scala 527:89]
halt_taken_f <= _T_186 @[el2_dec_tlu_ctl.scala 527:57]
reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 528:89]
_T_187 <= io.lsu_idle_any @[el2_dec_tlu_ctl.scala 528:89]
lsu_idle_any_f <= _T_187 @[el2_dec_tlu_ctl.scala 528:57]
reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 529:81]
_T_188 <= io.tlu_mem.ifu_miss_state_idle @[el2_dec_tlu_ctl.scala 529:81]
ifu_miss_state_idle_f <= _T_188 @[el2_dec_tlu_ctl.scala 529:49]
reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 530:89]
_T_189 <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 530:89]
dbg_tlu_halted_f <= _T_189 @[el2_dec_tlu_ctl.scala 530:57]
reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 531:81]
_T_190 <= resume_ack_ns @[el2_dec_tlu_ctl.scala 531:81]
io.dec_tlu_resume_ack <= _T_190 @[el2_dec_tlu_ctl.scala 531:49]
reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 532:89]
_T_191 <= debug_halt_req_ns @[el2_dec_tlu_ctl.scala 532:89]
debug_halt_req_f <= _T_191 @[el2_dec_tlu_ctl.scala 532:57]
reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 533:89]
_T_192 <= debug_resume_req @[el2_dec_tlu_ctl.scala 533:89]
debug_resume_req_f <= _T_192 @[el2_dec_tlu_ctl.scala 533:57]
reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 534:81]
_T_193 <= trigger_hit_dmode_r @[el2_dec_tlu_ctl.scala 534:81]
trigger_hit_dmode_r_d1 <= _T_193 @[el2_dec_tlu_ctl.scala 534:49]
reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 535:81]
_T_194 <= dcsr_single_step_done @[el2_dec_tlu_ctl.scala 535:81]
dcsr_single_step_done_f <= _T_194 @[el2_dec_tlu_ctl.scala 535:49]
reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 536:89]
_T_195 <= debug_halt_req @[el2_dec_tlu_ctl.scala 536:89]
debug_halt_req_d1 <= _T_195 @[el2_dec_tlu_ctl.scala 536:57]
reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 537:81]
dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 537:81]
reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 538:81]
dec_pause_state_f <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 538:81]
reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 539:81]
_T_196 <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 539:81]
request_debug_mode_r_d1 <= _T_196 @[el2_dec_tlu_ctl.scala 539:49]
reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 540:73]
_T_197 <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 540:73]
request_debug_mode_done_f <= _T_197 @[el2_dec_tlu_ctl.scala 540:41]
reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 541:73]
_T_198 <= dcsr_single_step_running @[el2_dec_tlu_ctl.scala 541:73]
dcsr_single_step_running_f <= _T_198 @[el2_dec_tlu_ctl.scala 541:41]
reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 542:73]
_T_199 <= io.dec_tlu_flush_pause_r @[el2_dec_tlu_ctl.scala 542:73]
dec_tlu_flush_pause_r_d1 <= _T_199 @[el2_dec_tlu_ctl.scala 542:41]
reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 543:81]
_T_200 <= dbg_halt_req_held_ns @[el2_dec_tlu_ctl.scala 543:81]
dbg_halt_req_held <= _T_200 @[el2_dec_tlu_ctl.scala 543:49]
io.dec_tlu_debug_stall <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 546:41]
io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 547:41]
io.dec_tlu_debug_mode <= debug_mode_status @[el2_dec_tlu_ctl.scala 548:41]
dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[el2_dec_tlu_ctl.scala 549:41]
node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 552:71]
node _T_202 = or(take_halt, _T_201) @[el2_dec_tlu_ctl.scala 552:58]
node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[el2_dec_tlu_ctl.scala 552:97]
node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 552:144]
node _T_205 = or(_T_203, _T_204) @[el2_dec_tlu_ctl.scala 552:124]
node _T_206 = or(_T_205, take_ext_int_start) @[el2_dec_tlu_ctl.scala 552:167]
io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[el2_dec_tlu_ctl.scala 552:45]
io.dec_tlu_flush_extint <= take_ext_int_start @[el2_dec_tlu_ctl.scala 554:33]
node _T_207 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 557:61]
node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[el2_dec_tlu_ctl.scala 557:59]
node _T_209 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 557:82]
node _T_210 = and(_T_208, _T_209) @[el2_dec_tlu_ctl.scala 557:80]
io.dec_tlu_flush_pause_r <= _T_210 @[el2_dec_tlu_ctl.scala 557:34]
node _T_211 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 559:28]
node _T_212 = and(_T_211, dec_pause_state_f) @[el2_dec_tlu_ctl.scala 559:48]
node _T_213 = or(ext_int_ready, ce_int_ready) @[el2_dec_tlu_ctl.scala 559:86]
node _T_214 = or(_T_213, timer_int_ready) @[el2_dec_tlu_ctl.scala 559:101]
node _T_215 = or(_T_214, soft_int_ready) @[el2_dec_tlu_ctl.scala 559:119]
node _T_216 = or(_T_215, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 559:136]
node _T_217 = or(_T_216, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 559:160]
node _T_218 = or(_T_217, nmi_int_detected) @[el2_dec_tlu_ctl.scala 559:184]
node _T_219 = or(_T_218, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 559:203]
node _T_220 = not(_T_219) @[el2_dec_tlu_ctl.scala 559:70]
node _T_221 = and(_T_212, _T_220) @[el2_dec_tlu_ctl.scala 559:68]
node _T_222 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 559:226]
node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 559:224]
node _T_224 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 559:250]
node _T_225 = and(_T_223, _T_224) @[el2_dec_tlu_ctl.scala 559:248]
node _T_226 = not(pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 559:270]
node _T_227 = and(_T_225, _T_226) @[el2_dec_tlu_ctl.scala 559:268]
node _T_228 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 559:291]
node _T_229 = and(_T_227, _T_228) @[el2_dec_tlu_ctl.scala 559:289]
pause_expired_r <= _T_229 @[el2_dec_tlu_ctl.scala 559:25]
node _T_230 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 561:88]
node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[el2_dec_tlu_ctl.scala 561:82]
node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 561:125]
node _T_233 = and(_T_231, _T_232) @[el2_dec_tlu_ctl.scala 561:100]
node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[el2_dec_tlu_ctl.scala 561:155]
node _T_235 = and(_T_233, _T_234) @[el2_dec_tlu_ctl.scala 561:153]
io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[el2_dec_tlu_ctl.scala 561:45]
node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 562:93]
node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[el2_dec_tlu_ctl.scala 562:77]
io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[el2_dec_tlu_ctl.scala 562:41]
io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[el2_dec_tlu_ctl.scala 565:29]
node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[el2_dec_tlu_ctl.scala 566:42]
io.dec_dbg_cmd_fail <= _T_238 @[el2_dec_tlu_ctl.scala 566:29]
node _T_239 = bits(mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 579:48]
node _T_240 = bits(mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 579:75]
node _T_241 = bits(mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 579:102]
node _T_242 = bits(mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 579:129]
node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58]
node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58]
node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58]
node _T_245 = bits(mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 580:52]
node _T_246 = bits(mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 580:79]
node _T_247 = bits(mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 580:106]
node _T_248 = bits(mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 580:133]
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58]
node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58]
node _T_251 = bits(mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 581:52]
node _T_252 = bits(mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 581:79]
node _T_253 = bits(mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 581:106]
node _T_254 = bits(mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 581:133]
node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58]
node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58]
node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58]
node _T_257 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 584:45]
node _T_258 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 584:71]
node _T_259 = or(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 584:62]
node _T_260 = bits(mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 584:100]
node _T_261 = and(_T_259, _T_260) @[el2_dec_tlu_ctl.scala 584:86]
node _T_262 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 584:133]
node _T_263 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 584:159]
node _T_264 = or(_T_262, _T_263) @[el2_dec_tlu_ctl.scala 584:150]
node _T_265 = bits(mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 584:188]
node _T_266 = and(_T_264, _T_265) @[el2_dec_tlu_ctl.scala 584:174]
node _T_267 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 584:222]
node _T_268 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 584:248]
node _T_269 = or(_T_267, _T_268) @[el2_dec_tlu_ctl.scala 584:239]
node _T_270 = bits(mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 584:277]
node _T_271 = and(_T_269, _T_270) @[el2_dec_tlu_ctl.scala 584:263]
node _T_272 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 584:311]
node _T_273 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 584:337]
node _T_274 = or(_T_272, _T_273) @[el2_dec_tlu_ctl.scala 584:328]
node _T_275 = bits(mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 584:366]
node _T_276 = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 584:352]
node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58]
node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58]
node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58]
node _T_279 = and(trigger_execute, trigger_data) @[el2_dec_tlu_ctl.scala 587:57]
node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15]
node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_282 = and(_T_279, _T_281) @[el2_dec_tlu_ctl.scala 587:72]
node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 587:137]
node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15]
node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_286 = or(_T_282, _T_285) @[el2_dec_tlu_ctl.scala 587:98]
node i0_iside_trigger_has_pri_r = not(_T_286) @[el2_dec_tlu_ctl.scala 587:38]
node _T_287 = and(trigger_store, trigger_data) @[el2_dec_tlu_ctl.scala 590:51]
node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15]
node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_290 = and(_T_287, _T_289) @[el2_dec_tlu_ctl.scala 590:66]
node i0_lsu_trigger_has_pri_r = not(_T_290) @[el2_dec_tlu_ctl.scala 590:35]
node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15]
node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[el2_dec_tlu_ctl.scala 595:84]
node _T_294 = and(_T_292, _T_293) @[el2_dec_tlu_ctl.scala 595:53]
node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 595:90]
node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 595:119]
node i0trigger_qual_r = and(_T_296, trigger_enabled) @[el2_dec_tlu_ctl.scala 595:146]
node _T_297 = or(io.tlu_bp.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 597:65]
node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15]
node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_300 = not(_T_299) @[el2_dec_tlu_ctl.scala 597:23]
node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[el2_dec_tlu_ctl.scala 597:91]
node _T_301 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 600:53]
node _T_302 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 600:73]
node _T_303 = not(_T_302) @[el2_dec_tlu_ctl.scala 600:60]
node _T_304 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 600:103]
node _T_305 = or(_T_303, _T_304) @[el2_dec_tlu_ctl.scala 600:89]
node _T_306 = and(_T_301, _T_305) @[el2_dec_tlu_ctl.scala 600:57]
node _T_307 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 600:121]
node _T_308 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 600:141]
node _T_309 = not(_T_308) @[el2_dec_tlu_ctl.scala 600:128]
node _T_310 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 600:171]
node _T_311 = or(_T_309, _T_310) @[el2_dec_tlu_ctl.scala 600:157]
node _T_312 = and(_T_307, _T_311) @[el2_dec_tlu_ctl.scala 600:125]
node _T_313 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 600:189]
node _T_314 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 600:209]
node _T_315 = not(_T_314) @[el2_dec_tlu_ctl.scala 600:196]
node _T_316 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 600:239]
node _T_317 = or(_T_315, _T_316) @[el2_dec_tlu_ctl.scala 600:225]
node _T_318 = and(_T_313, _T_317) @[el2_dec_tlu_ctl.scala 600:193]
node _T_319 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 600:257]
node _T_320 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 600:277]
node _T_321 = not(_T_320) @[el2_dec_tlu_ctl.scala 600:264]
node _T_322 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 600:307]
node _T_323 = or(_T_321, _T_322) @[el2_dec_tlu_ctl.scala 600:293]
node _T_324 = and(_T_319, _T_323) @[el2_dec_tlu_ctl.scala 600:261]
node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58]
node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58]
node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58]
node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 603:57]
i0_trigger_hit_r <= i0_trigger_hit_raw_r @[el2_dec_tlu_ctl.scala 605:25]
node _T_327 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 609:44]
node _T_328 = bits(mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 609:75]
node _T_329 = and(_T_327, _T_328) @[el2_dec_tlu_ctl.scala 609:61]
node _T_330 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 609:104]
node _T_331 = bits(mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 609:135]
node _T_332 = and(_T_330, _T_331) @[el2_dec_tlu_ctl.scala 609:121]
node _T_333 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 609:164]
node _T_334 = bits(mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 609:195]
node _T_335 = and(_T_333, _T_334) @[el2_dec_tlu_ctl.scala 609:181]
node _T_336 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 609:224]
node _T_337 = bits(mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 609:255]
node _T_338 = and(_T_336, _T_337) @[el2_dec_tlu_ctl.scala 609:241]
node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58]
node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58]
node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58]
node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15]
node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 612:56]
node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[el2_dec_tlu_ctl.scala 615:57]
node i0_trigger_action_r = orr(_T_343) @[el2_dec_tlu_ctl.scala 615:75]
node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[el2_dec_tlu_ctl.scala 617:45]
trigger_hit_dmode_r <= _T_344 @[el2_dec_tlu_ctl.scala 617:24]
node _T_345 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 619:55]
node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[el2_dec_tlu_ctl.scala 619:53]
node _T_346 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 646:62]
node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[el2_dec_tlu_ctl.scala 646:60]
node _T_348 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 646:87]
node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[el2_dec_tlu_ctl.scala 646:85]
node _T_349 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 647:60]
node _T_350 = and(i_cpu_run_req_sync, _T_349) @[el2_dec_tlu_ctl.scala 647:58]
node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 647:83]
node _T_352 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 647:107]
node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[el2_dec_tlu_ctl.scala 647:105]
reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 649:80]
i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[el2_dec_tlu_ctl.scala 649:80]
reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 650:80]
i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[el2_dec_tlu_ctl.scala 650:80]
reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 651:81]
_T_353 <= cpu_halt_status @[el2_dec_tlu_ctl.scala 651:81]
io.o_cpu_halt_status <= _T_353 @[el2_dec_tlu_ctl.scala 651:49]
reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 652:81]
_T_354 <= cpu_halt_ack @[el2_dec_tlu_ctl.scala 652:81]
io.o_cpu_halt_ack <= _T_354 @[el2_dec_tlu_ctl.scala 652:49]
reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 653:81]
_T_355 <= cpu_run_ack @[el2_dec_tlu_ctl.scala 653:81]
io.o_cpu_run_ack <= _T_355 @[el2_dec_tlu_ctl.scala 653:49]
reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 654:68]
internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[el2_dec_tlu_ctl.scala 654:68]
reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 655:73]
_T_356 <= pmu_fw_halt_req_ns @[el2_dec_tlu_ctl.scala 655:73]
pmu_fw_halt_req_f <= _T_356 @[el2_dec_tlu_ctl.scala 655:41]
reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 656:73]
_T_357 <= pmu_fw_tlu_halted @[el2_dec_tlu_ctl.scala 656:73]
pmu_fw_tlu_halted_f <= _T_357 @[el2_dec_tlu_ctl.scala 656:41]
reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 657:73]
_T_358 <= int_timer0_int_hold @[el2_dec_tlu_ctl.scala 657:73]
int_timer0_int_hold_f <= _T_358 @[el2_dec_tlu_ctl.scala 657:41]
reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 658:73]
_T_359 <= int_timer1_int_hold @[el2_dec_tlu_ctl.scala 658:73]
int_timer1_int_hold_f <= _T_359 @[el2_dec_tlu_ctl.scala 658:41]
node _T_360 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 662:52]
node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[el2_dec_tlu_ctl.scala 662:50]
node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[el2_dec_tlu_ctl.scala 663:48]
node _T_361 = not(pmu_fw_tlu_halted) @[el2_dec_tlu_ctl.scala 664:72]
node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[el2_dec_tlu_ctl.scala 664:70]
node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[el2_dec_tlu_ctl.scala 664:49]
node _T_364 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 664:95]
node _T_365 = and(_T_363, _T_364) @[el2_dec_tlu_ctl.scala 664:93]
pmu_fw_halt_req_ns <= _T_365 @[el2_dec_tlu_ctl.scala 664:23]
node _T_366 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 665:85]
node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[el2_dec_tlu_ctl.scala 665:83]
node _T_368 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 665:105]
node _T_369 = and(_T_367, _T_368) @[el2_dec_tlu_ctl.scala 665:103]
node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[el2_dec_tlu_ctl.scala 665:52]
internal_pmu_fw_halt_mode <= _T_370 @[el2_dec_tlu_ctl.scala 665:30]
node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 668:45]
node _T_372 = and(_T_371, halt_taken) @[el2_dec_tlu_ctl.scala 668:58]
node _T_373 = not(enter_debug_halt_req) @[el2_dec_tlu_ctl.scala 668:73]
node _T_374 = and(_T_372, _T_373) @[el2_dec_tlu_ctl.scala 668:71]
node _T_375 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 668:121]
node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[el2_dec_tlu_ctl.scala 668:119]
node _T_377 = or(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 668:96]
node _T_378 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 668:143]
node _T_379 = and(_T_377, _T_378) @[el2_dec_tlu_ctl.scala 668:141]
pmu_fw_tlu_halted <= _T_379 @[el2_dec_tlu_ctl.scala 668:22]
node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 670:38]
cpu_halt_ack <= _T_380 @[el2_dec_tlu_ctl.scala 670:17]
node _T_381 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:46]
node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[el2_dec_tlu_ctl.scala 671:44]
node _T_383 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:91]
node _T_384 = and(io.o_cpu_halt_status, _T_383) @[el2_dec_tlu_ctl.scala 671:89]
node _T_385 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 671:111]
node _T_386 = and(_T_384, _T_385) @[el2_dec_tlu_ctl.scala 671:109]
node _T_387 = or(_T_382, _T_386) @[el2_dec_tlu_ctl.scala 671:65]
cpu_halt_status <= _T_387 @[el2_dec_tlu_ctl.scala 671:20]
node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 672:41]
node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 672:88]
node _T_390 = or(_T_388, _T_389) @[el2_dec_tlu_ctl.scala 672:68]
cpu_run_ack <= _T_390 @[el2_dec_tlu_ctl.scala 672:16]
io.o_debug_mode_status <= debug_mode_status @[el2_dec_tlu_ctl.scala 674:27]
node _T_391 = or(nmi_int_detected, timer_int_ready) @[el2_dec_tlu_ctl.scala 677:66]
node _T_392 = or(_T_391, soft_int_ready) @[el2_dec_tlu_ctl.scala 677:84]
node _T_393 = or(_T_392, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 677:101]
node _T_394 = or(_T_393, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 677:125]
node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[el2_dec_tlu_ctl.scala 677:164]
node _T_396 = or(_T_394, _T_395) @[el2_dec_tlu_ctl.scala 677:149]
node _T_397 = and(_T_396, io.o_cpu_halt_status) @[el2_dec_tlu_ctl.scala 677:183]
node _T_398 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 677:208]
node _T_399 = and(_T_397, _T_398) @[el2_dec_tlu_ctl.scala 677:206]
node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[el2_dec_tlu_ctl.scala 677:45]
i_cpu_run_req_d1 <= _T_400 @[el2_dec_tlu_ctl.scala 677:21]
reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 683:89]
_T_401 <= mdseac_locked_ns @[el2_dec_tlu_ctl.scala 683:89]
mdseac_locked_f <= _T_401 @[el2_dec_tlu_ctl.scala 683:57]
reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 684:72]
lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[el2_dec_tlu_ctl.scala 684:72]
node _T_402 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 686:57]
node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[el2_dec_tlu_ctl.scala 686:55]
lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 687:21]
node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[el2_dec_tlu_ctl.scala 688:40]
node _T_404 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 688:64]
node _T_405 = and(_T_403, _T_404) @[el2_dec_tlu_ctl.scala 688:62]
node _T_406 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 688:84]
node lsu_exc_valid_r = and(_T_405, _T_406) @[el2_dec_tlu_ctl.scala 688:82]
reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 690:74]
_T_407 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 690:74]
lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 690:41]
reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 691:73]
lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 691:73]
node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 692:40]
node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 692:38]
node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 693:38]
node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 694:38]
node _T_409 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 698:49]
node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[el2_dec_tlu_ctl.scala 698:47]
node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 698:70]
node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[el2_dec_tlu_ctl.scala 698:105]
node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[el2_dec_tlu_ctl.scala 698:67]
node _T_413 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 701:52]
node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[el2_dec_tlu_ctl.scala 701:50]
node _T_415 = not(lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 701:65]
node _T_416 = and(_T_414, _T_415) @[el2_dec_tlu_ctl.scala 701:63]
node _T_417 = not(inst_acc_r) @[el2_dec_tlu_ctl.scala 701:82]
node _T_418 = and(_T_416, _T_417) @[el2_dec_tlu_ctl.scala 701:79]
node _T_419 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 701:96]
node _T_420 = and(_T_418, _T_419) @[el2_dec_tlu_ctl.scala 701:94]
node _T_421 = not(request_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 701:121]
node _T_422 = and(_T_420, _T_421) @[el2_dec_tlu_ctl.scala 701:119]
node _T_423 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 701:148]
node tlu_i0_commit_cmt = and(_T_422, _T_423) @[el2_dec_tlu_ctl.scala 701:146]
node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 704:38]
node _T_425 = or(_T_424, inst_acc_r) @[el2_dec_tlu_ctl.scala 704:53]
node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 704:79]
node _T_427 = or(_T_425, _T_426) @[el2_dec_tlu_ctl.scala 704:66]
node _T_428 = or(_T_427, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 704:104]
tlu_i0_kill_writeb_r <= _T_428 @[el2_dec_tlu_ctl.scala 704:25]
io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 705:37]
node _T_429 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 710:44]
node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[el2_dec_tlu_ctl.scala 710:42]
node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 710:98]
node _T_432 = and(_T_430, _T_431) @[el2_dec_tlu_ctl.scala 710:66]
node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 710:154]
node _T_434 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 710:175]
node _T_435 = and(_T_433, _T_434) @[el2_dec_tlu_ctl.scala 710:173]
node _T_436 = or(_T_432, _T_435) @[el2_dec_tlu_ctl.scala 710:137]
node _T_437 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 710:199]
node _T_438 = and(_T_436, _T_437) @[el2_dec_tlu_ctl.scala 710:196]
node _T_439 = not(lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 710:220]
node _T_440 = and(_T_438, _T_439) @[el2_dec_tlu_ctl.scala 710:217]
rfpc_i0_r <= _T_440 @[el2_dec_tlu_ctl.scala 710:14]
node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[el2_dec_tlu_ctl.scala 713:70]
node _T_442 = and(iccm_repair_state_d1, _T_441) @[el2_dec_tlu_ctl.scala 713:68]
node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[el2_dec_tlu_ctl.scala 713:44]
iccm_repair_state_ns <= _T_443 @[el2_dec_tlu_ctl.scala 713:25]
node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[el2_dec_tlu_ctl.scala 719:52]
node _T_445 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 719:88]
node _T_446 = or(_T_445, mret_r) @[el2_dec_tlu_ctl.scala 719:98]
node _T_447 = or(_T_446, take_reset) @[el2_dec_tlu_ctl.scala 719:107]
node _T_448 = or(_T_447, illegal_r) @[el2_dec_tlu_ctl.scala 719:120]
node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 719:176]
node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[el2_dec_tlu_ctl.scala 719:153]
node _T_451 = or(_T_448, _T_450) @[el2_dec_tlu_ctl.scala 719:132]
node _T_452 = not(_T_451) @[el2_dec_tlu_ctl.scala 719:77]
node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[el2_dec_tlu_ctl.scala 719:75]
node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 722:59]
node _T_454 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 722:85]
node dec_tlu_br0_error_r = and(_T_453, _T_454) @[el2_dec_tlu_ctl.scala 722:83]
node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 723:71]
node _T_456 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 723:97]
node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[el2_dec_tlu_ctl.scala 723:95]
node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 724:55]
node _T_458 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 724:81]
node _T_459 = and(_T_457, _T_458) @[el2_dec_tlu_ctl.scala 724:79]
node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[el2_dec_tlu_ctl.scala 724:106]
node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 724:135]
node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 724:133]
node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 724:103]
io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 727:65]
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 728:57]
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 729:57]
io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 730:57]
io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 731:65]
io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 732:65]
node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 735:51]
node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 735:64]
node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 735:90]
node _T_466 = and(_T_464, _T_465) @[el2_dec_tlu_ctl.scala 735:88]
node _T_467 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 735:115]
node _T_468 = not(_T_467) @[el2_dec_tlu_ctl.scala 735:110]
node _T_469 = and(_T_466, _T_468) @[el2_dec_tlu_ctl.scala 735:108]
node _T_470 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 735:132]
node _T_471 = and(_T_469, _T_470) @[el2_dec_tlu_ctl.scala 735:130]
ebreak_r <= _T_471 @[el2_dec_tlu_ctl.scala 735:13]
node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 736:51]
node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 736:64]
node _T_474 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 736:90]
node _T_475 = and(_T_473, _T_474) @[el2_dec_tlu_ctl.scala 736:88]
node _T_476 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 736:110]
node _T_477 = and(_T_475, _T_476) @[el2_dec_tlu_ctl.scala 736:108]
ecall_r <= _T_477 @[el2_dec_tlu_ctl.scala 736:13]
node _T_478 = not(io.dec_tlu_packet_r.legal) @[el2_dec_tlu_ctl.scala 737:17]
node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 737:46]
node _T_480 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 737:72]
node _T_481 = and(_T_479, _T_480) @[el2_dec_tlu_ctl.scala 737:70]
node _T_482 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 737:92]
node _T_483 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 737:90]
illegal_r <= _T_483 @[el2_dec_tlu_ctl.scala 737:13]
node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 738:51]
node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64]
node _T_486 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90]
node _T_487 = and(_T_485, _T_486) @[el2_dec_tlu_ctl.scala 738:88]
node _T_488 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 738:110]
node _T_489 = and(_T_487, _T_488) @[el2_dec_tlu_ctl.scala 738:108]
mret_r <= _T_489 @[el2_dec_tlu_ctl.scala 738:13]
node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 740:50]
node _T_491 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 740:76]
node _T_492 = and(_T_490, _T_491) @[el2_dec_tlu_ctl.scala 740:74]
node _T_493 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 740:97]
node _T_494 = and(_T_492, _T_493) @[el2_dec_tlu_ctl.scala 740:95]
fence_i_r <= _T_494 @[el2_dec_tlu_ctl.scala 740:17]
node _T_495 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 741:53]
node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[el2_dec_tlu_ctl.scala 741:51]
node _T_497 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 741:75]
node _T_498 = or(_T_497, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 741:101]
node _T_499 = and(_T_496, _T_498) @[el2_dec_tlu_ctl.scala 741:72]
node _T_500 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 741:131]
node _T_501 = and(_T_499, _T_500) @[el2_dec_tlu_ctl.scala 741:129]
ic_perr_r <= _T_501 @[el2_dec_tlu_ctl.scala 741:17]
node _T_502 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 742:61]
node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[el2_dec_tlu_ctl.scala 742:59]
node _T_504 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 742:83]
node _T_505 = or(_T_504, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 742:109]
node _T_506 = and(_T_503, _T_505) @[el2_dec_tlu_ctl.scala 742:80]
node _T_507 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 742:139]
node _T_508 = and(_T_506, _T_507) @[el2_dec_tlu_ctl.scala 742:137]
iccm_sbecc_r <= _T_508 @[el2_dec_tlu_ctl.scala 742:17]
node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 743:49]
inst_acc_r_raw <= _T_509 @[el2_dec_tlu_ctl.scala 743:20]
node _T_510 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 744:35]
node _T_511 = and(inst_acc_r_raw, _T_510) @[el2_dec_tlu_ctl.scala 744:33]
node _T_512 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 744:48]
node _T_513 = and(_T_511, _T_512) @[el2_dec_tlu_ctl.scala 744:46]
inst_acc_r <= _T_513 @[el2_dec_tlu_ctl.scala 744:15]
node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 747:64]
node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 747:77]
node _T_516 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 747:103]
node _T_517 = and(_T_515, _T_516) @[el2_dec_tlu_ctl.scala 747:101]
node _T_518 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 747:127]
node _T_519 = and(_T_517, _T_518) @[el2_dec_tlu_ctl.scala 747:121]
node _T_520 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 747:144]
node _T_521 = and(_T_519, _T_520) @[el2_dec_tlu_ctl.scala 747:142]
ebreak_to_debug_mode_r <= _T_521 @[el2_dec_tlu_ctl.scala 747:27]
reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 749:64]
_T_522 <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 749:64]
ebreak_to_debug_mode_r_d1 <= _T_522 @[el2_dec_tlu_ctl.scala 749:34]
io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[el2_dec_tlu_ctl.scala 750:39]
node _T_523 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 763:41]
node _T_524 = or(_T_523, illegal_r) @[el2_dec_tlu_ctl.scala 763:51]
node _T_525 = or(_T_524, inst_acc_r) @[el2_dec_tlu_ctl.scala 763:63]
node _T_526 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 763:79]
node _T_527 = and(_T_525, _T_526) @[el2_dec_tlu_ctl.scala 763:77]
node _T_528 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 763:92]
node i0_exception_valid_r = and(_T_527, _T_528) @[el2_dec_tlu_ctl.scala 763:90]
node _T_529 = not(take_nmi) @[el2_dec_tlu_ctl.scala 772:33]
node _T_530 = and(take_ext_int, _T_529) @[el2_dec_tlu_ctl.scala 772:31]
node _T_531 = bits(_T_530, 0, 0) @[el2_dec_tlu_ctl.scala 772:44]
node _T_532 = not(take_nmi) @[el2_dec_tlu_ctl.scala 773:27]
node _T_533 = and(take_timer_int, _T_532) @[el2_dec_tlu_ctl.scala 773:25]
node _T_534 = bits(_T_533, 0, 0) @[el2_dec_tlu_ctl.scala 773:38]
node _T_535 = not(take_nmi) @[el2_dec_tlu_ctl.scala 774:26]
node _T_536 = and(take_soft_int, _T_535) @[el2_dec_tlu_ctl.scala 774:24]
node _T_537 = bits(_T_536, 0, 0) @[el2_dec_tlu_ctl.scala 774:37]
node _T_538 = not(take_nmi) @[el2_dec_tlu_ctl.scala 775:32]
node _T_539 = and(take_int_timer0_int, _T_538) @[el2_dec_tlu_ctl.scala 775:30]
node _T_540 = bits(_T_539, 0, 0) @[el2_dec_tlu_ctl.scala 775:43]
node _T_541 = not(take_nmi) @[el2_dec_tlu_ctl.scala 776:32]
node _T_542 = and(take_int_timer1_int, _T_541) @[el2_dec_tlu_ctl.scala 776:30]
node _T_543 = bits(_T_542, 0, 0) @[el2_dec_tlu_ctl.scala 776:43]
node _T_544 = not(take_nmi) @[el2_dec_tlu_ctl.scala 777:24]
node _T_545 = and(take_ce_int, _T_544) @[el2_dec_tlu_ctl.scala 777:22]
node _T_546 = bits(_T_545, 0, 0) @[el2_dec_tlu_ctl.scala 777:35]
node _T_547 = not(take_nmi) @[el2_dec_tlu_ctl.scala 778:22]
node _T_548 = and(illegal_r, _T_547) @[el2_dec_tlu_ctl.scala 778:20]
node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 778:33]
node _T_550 = not(take_nmi) @[el2_dec_tlu_ctl.scala 779:21]
node _T_551 = and(ecall_r, _T_550) @[el2_dec_tlu_ctl.scala 779:19]
node _T_552 = bits(_T_551, 0, 0) @[el2_dec_tlu_ctl.scala 779:32]
node _T_553 = not(take_nmi) @[el2_dec_tlu_ctl.scala 780:24]
node _T_554 = and(inst_acc_r, _T_553) @[el2_dec_tlu_ctl.scala 780:22]
node _T_555 = bits(_T_554, 0, 0) @[el2_dec_tlu_ctl.scala 780:35]
node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 781:20]
node _T_557 = not(take_nmi) @[el2_dec_tlu_ctl.scala 781:42]
node _T_558 = and(_T_556, _T_557) @[el2_dec_tlu_ctl.scala 781:40]
node _T_559 = bits(_T_558, 0, 0) @[el2_dec_tlu_ctl.scala 781:53]
node _T_560 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 782:25]
node _T_561 = and(lsu_exc_ma_r, _T_560) @[el2_dec_tlu_ctl.scala 782:23]
node _T_562 = not(take_nmi) @[el2_dec_tlu_ctl.scala 782:41]
node _T_563 = and(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 782:39]
node _T_564 = bits(_T_563, 0, 0) @[el2_dec_tlu_ctl.scala 782:52]
node _T_565 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 783:26]
node _T_566 = and(lsu_exc_acc_r, _T_565) @[el2_dec_tlu_ctl.scala 783:24]
node _T_567 = not(take_nmi) @[el2_dec_tlu_ctl.scala 783:42]
node _T_568 = and(_T_566, _T_567) @[el2_dec_tlu_ctl.scala 783:40]
node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 783:53]
node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 784:23]
node _T_571 = not(take_nmi) @[el2_dec_tlu_ctl.scala 784:40]
node _T_572 = and(_T_570, _T_571) @[el2_dec_tlu_ctl.scala 784:38]
node _T_573 = bits(_T_572, 0, 0) @[el2_dec_tlu_ctl.scala 784:51]
node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 785:24]
node _T_575 = not(take_nmi) @[el2_dec_tlu_ctl.scala 785:41]
node _T_576 = and(_T_574, _T_575) @[el2_dec_tlu_ctl.scala 785:39]
node _T_577 = bits(_T_576, 0, 0) @[el2_dec_tlu_ctl.scala 785:52]
node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72]
node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72]
node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72]
node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72]
node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72]
node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72]
node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72]
node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72]
node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72]
node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72]
node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72]
node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72]
node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72]
wire exc_cause_r : UInt<5> @[Mux.scala 27:72]
exc_cause_r <= _T_604 @[Mux.scala 27:72]
node _T_605 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 796:24]
node _T_606 = and(_T_605, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 796:49]
node _T_607 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 796:71]
node _T_608 = and(_T_606, _T_607) @[el2_dec_tlu_ctl.scala 796:66]
node _T_609 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 796:92]
node _T_610 = and(_T_608, _T_609) @[el2_dec_tlu_ctl.scala 796:84]
mhwakeup_ready <= _T_610 @[el2_dec_tlu_ctl.scala 796:20]
node _T_611 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 797:23]
node _T_612 = and(_T_611, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 797:48]
node _T_613 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 797:70]
node _T_614 = and(_T_612, _T_613) @[el2_dec_tlu_ctl.scala 797:65]
node _T_615 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 797:91]
node _T_616 = and(_T_614, _T_615) @[el2_dec_tlu_ctl.scala 797:83]
node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[el2_dec_tlu_ctl.scala 797:104]
node _T_618 = and(_T_616, _T_617) @[el2_dec_tlu_ctl.scala 797:102]
ext_int_ready <= _T_618 @[el2_dec_tlu_ctl.scala 797:20]
node _T_619 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 798:23]
node _T_620 = and(_T_619, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 798:48]
node _T_621 = bits(mip, 5, 5) @[el2_dec_tlu_ctl.scala 798:70]
node _T_622 = and(_T_620, _T_621) @[el2_dec_tlu_ctl.scala 798:65]
node _T_623 = bits(mie_ns, 5, 5) @[el2_dec_tlu_ctl.scala 798:91]
node _T_624 = and(_T_622, _T_623) @[el2_dec_tlu_ctl.scala 798:83]
ce_int_ready <= _T_624 @[el2_dec_tlu_ctl.scala 798:20]
node _T_625 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 799:23]
node _T_626 = and(_T_625, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 799:48]
node _T_627 = bits(mip, 0, 0) @[el2_dec_tlu_ctl.scala 799:70]
node _T_628 = and(_T_626, _T_627) @[el2_dec_tlu_ctl.scala 799:65]
node _T_629 = bits(mie_ns, 0, 0) @[el2_dec_tlu_ctl.scala 799:91]
node _T_630 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 799:83]
soft_int_ready <= _T_630 @[el2_dec_tlu_ctl.scala 799:20]
node _T_631 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 800:23]
node _T_632 = and(_T_631, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 800:48]
node _T_633 = bits(mip, 1, 1) @[el2_dec_tlu_ctl.scala 800:70]
node _T_634 = and(_T_632, _T_633) @[el2_dec_tlu_ctl.scala 800:65]
node _T_635 = bits(mie_ns, 1, 1) @[el2_dec_tlu_ctl.scala 800:91]
node _T_636 = and(_T_634, _T_635) @[el2_dec_tlu_ctl.scala 800:83]
timer_int_ready <= _T_636 @[el2_dec_tlu_ctl.scala 800:20]
node _T_637 = bits(mie_ns, 4, 4) @[el2_dec_tlu_ctl.scala 803:57]
node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[el2_dec_tlu_ctl.scala 803:49]
node _T_638 = bits(mip, 4, 4) @[el2_dec_tlu_ctl.scala 804:34]
node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 804:47]
node _T_639 = bits(mie_ns, 3, 3) @[el2_dec_tlu_ctl.scala 805:57]
node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[el2_dec_tlu_ctl.scala 805:49]
node _T_640 = bits(mip, 3, 3) @[el2_dec_tlu_ctl.scala 806:34]
node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 806:47]
node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 810:52]
node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 810:74]
node int_timer_stalled = or(_T_642, mret_r) @[el2_dec_tlu_ctl.scala 810:98]
node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 812:72]
node _T_644 = and(int_timer0_int_ready, _T_643) @[el2_dec_tlu_ctl.scala 812:49]
node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 812:121]
node _T_646 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 812:147]
node _T_647 = and(_T_645, _T_646) @[el2_dec_tlu_ctl.scala 812:145]
node _T_648 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 812:168]
node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 812:166]
node _T_650 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 812:190]
node _T_651 = and(_T_649, _T_650) @[el2_dec_tlu_ctl.scala 812:188]
node _T_652 = or(_T_644, _T_651) @[el2_dec_tlu_ctl.scala 812:94]
int_timer0_int_hold <= _T_652 @[el2_dec_tlu_ctl.scala 812:24]
node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 813:72]
node _T_654 = and(int_timer1_int_ready, _T_653) @[el2_dec_tlu_ctl.scala 813:49]
node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 813:121]
node _T_656 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 813:147]
node _T_657 = and(_T_655, _T_656) @[el2_dec_tlu_ctl.scala 813:145]
node _T_658 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 813:168]
node _T_659 = and(_T_657, _T_658) @[el2_dec_tlu_ctl.scala 813:166]
node _T_660 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 813:190]
node _T_661 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 813:188]
node _T_662 = or(_T_654, _T_661) @[el2_dec_tlu_ctl.scala 813:94]
int_timer1_int_hold <= _T_662 @[el2_dec_tlu_ctl.scala 813:24]
node _T_663 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 815:59]
node _T_664 = and(debug_mode_status, _T_663) @[el2_dec_tlu_ctl.scala 815:57]
internal_dbg_halt_timers <= _T_664 @[el2_dec_tlu_ctl.scala 815:29]
node _T_665 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 817:55]
node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 817:81]
node _T_667 = and(internal_dbg_halt_mode, _T_666) @[el2_dec_tlu_ctl.scala 817:52]
node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 817:107]
node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 817:135]
node _T_670 = or(_T_669, take_nmi) @[el2_dec_tlu_ctl.scala 817:155]
node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 817:166]
node _T_672 = or(_T_671, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 817:191]
node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 817:214]
node _T_674 = or(_T_673, mret_r) @[el2_dec_tlu_ctl.scala 817:238]
node block_interrupts = or(_T_674, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 817:247]
reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 821:62]
_T_675 <= take_ext_int_start @[el2_dec_tlu_ctl.scala 821:62]
take_ext_int_start_d1 <= _T_675 @[el2_dec_tlu_ctl.scala 821:30]
reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 822:62]
_T_676 <= take_ext_int_start_d1 @[el2_dec_tlu_ctl.scala 822:62]
take_ext_int_start_d2 <= _T_676 @[el2_dec_tlu_ctl.scala 822:30]
reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 823:62]
_T_677 <= take_ext_int_start_d2 @[el2_dec_tlu_ctl.scala 823:62]
take_ext_int_start_d3 <= _T_677 @[el2_dec_tlu_ctl.scala 823:30]
reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 824:66]
_T_678 <= ext_int_freeze @[el2_dec_tlu_ctl.scala 824:66]
ext_int_freeze_d1 <= _T_678 @[el2_dec_tlu_ctl.scala 824:34]
node _T_679 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 825:47]
node _T_680 = and(ext_int_ready, _T_679) @[el2_dec_tlu_ctl.scala 825:45]
take_ext_int_start <= _T_680 @[el2_dec_tlu_ctl.scala 825:28]
node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 827:46]
node _T_682 = or(_T_681, take_ext_int_start_d2) @[el2_dec_tlu_ctl.scala 827:70]
node _T_683 = or(_T_682, take_ext_int_start_d3) @[el2_dec_tlu_ctl.scala 827:94]
ext_int_freeze <= _T_683 @[el2_dec_tlu_ctl.scala 827:24]
node _T_684 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 828:67]
node _T_685 = not(_T_684) @[el2_dec_tlu_ctl.scala 828:49]
node _T_686 = and(take_ext_int_start_d3, _T_685) @[el2_dec_tlu_ctl.scala 828:47]
take_ext_int <= _T_686 @[el2_dec_tlu_ctl.scala 828:22]
node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 829:49]
fast_int_meicpct <= _T_687 @[el2_dec_tlu_ctl.scala 829:26]
ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[el2_dec_tlu_ctl.scala 830:41]
node _T_688 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 843:35]
node _T_689 = and(ce_int_ready, _T_688) @[el2_dec_tlu_ctl.scala 843:33]
node _T_690 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 843:52]
node _T_691 = and(_T_689, _T_690) @[el2_dec_tlu_ctl.scala 843:50]
take_ce_int <= _T_691 @[el2_dec_tlu_ctl.scala 843:17]
node _T_692 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 844:38]
node _T_693 = and(soft_int_ready, _T_692) @[el2_dec_tlu_ctl.scala 844:36]
node _T_694 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 844:55]
node _T_695 = and(_T_693, _T_694) @[el2_dec_tlu_ctl.scala 844:53]
node _T_696 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 844:71]
node _T_697 = and(_T_695, _T_696) @[el2_dec_tlu_ctl.scala 844:69]
take_soft_int <= _T_697 @[el2_dec_tlu_ctl.scala 844:18]
node _T_698 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 845:40]
node _T_699 = and(timer_int_ready, _T_698) @[el2_dec_tlu_ctl.scala 845:38]
node _T_700 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 845:58]
node _T_701 = and(_T_699, _T_700) @[el2_dec_tlu_ctl.scala 845:56]
node _T_702 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 845:75]
node _T_703 = and(_T_701, _T_702) @[el2_dec_tlu_ctl.scala 845:73]
node _T_704 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 845:91]
node _T_705 = and(_T_703, _T_704) @[el2_dec_tlu_ctl.scala 845:89]
take_timer_int <= _T_705 @[el2_dec_tlu_ctl.scala 845:19]
node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 846:49]
node _T_707 = and(_T_706, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 846:74]
node _T_708 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 846:102]
node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 846:100]
node _T_710 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 846:129]
node _T_711 = and(_T_709, _T_710) @[el2_dec_tlu_ctl.scala 846:127]
node _T_712 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 846:148]
node _T_713 = and(_T_711, _T_712) @[el2_dec_tlu_ctl.scala 846:146]
node _T_714 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 846:166]
node _T_715 = and(_T_713, _T_714) @[el2_dec_tlu_ctl.scala 846:164]
node _T_716 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 846:183]
node _T_717 = and(_T_715, _T_716) @[el2_dec_tlu_ctl.scala 846:181]
node _T_718 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 846:199]
node _T_719 = and(_T_717, _T_718) @[el2_dec_tlu_ctl.scala 846:197]
take_int_timer0_int <= _T_719 @[el2_dec_tlu_ctl.scala 846:24]
node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 847:49]
node _T_721 = and(_T_720, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 847:74]
node _T_722 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 847:102]
node _T_723 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 847:100]
node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 847:152]
node _T_725 = not(_T_724) @[el2_dec_tlu_ctl.scala 847:129]
node _T_726 = and(_T_723, _T_725) @[el2_dec_tlu_ctl.scala 847:127]
node _T_727 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 847:179]
node _T_728 = and(_T_726, _T_727) @[el2_dec_tlu_ctl.scala 847:177]
node _T_729 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 847:198]
node _T_730 = and(_T_728, _T_729) @[el2_dec_tlu_ctl.scala 847:196]
node _T_731 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 847:216]
node _T_732 = and(_T_730, _T_731) @[el2_dec_tlu_ctl.scala 847:214]
node _T_733 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 847:233]
node _T_734 = and(_T_732, _T_733) @[el2_dec_tlu_ctl.scala 847:231]
node _T_735 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 847:249]
node _T_736 = and(_T_734, _T_735) @[el2_dec_tlu_ctl.scala 847:247]
take_int_timer1_int <= _T_736 @[el2_dec_tlu_ctl.scala 847:24]
node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 848:32]
take_reset <= _T_737 @[el2_dec_tlu_ctl.scala 848:15]
node _T_738 = not(internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 849:35]
node _T_739 = and(nmi_int_detected, _T_738) @[el2_dec_tlu_ctl.scala 849:33]
node _T_740 = not(internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 849:65]
node _T_741 = bits(dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 849:125]
node _T_742 = and(dcsr_single_step_running_f, _T_741) @[el2_dec_tlu_ctl.scala 849:119]
node _T_743 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 849:141]
node _T_744 = and(_T_742, _T_743) @[el2_dec_tlu_ctl.scala 849:139]
node _T_745 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 849:166]
node _T_746 = and(_T_744, _T_745) @[el2_dec_tlu_ctl.scala 849:164]
node _T_747 = or(_T_740, _T_746) @[el2_dec_tlu_ctl.scala 849:89]
node _T_748 = and(_T_739, _T_747) @[el2_dec_tlu_ctl.scala 849:62]
node _T_749 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 849:195]
node _T_750 = and(_T_748, _T_749) @[el2_dec_tlu_ctl.scala 849:193]
node _T_751 = not(mret_r) @[el2_dec_tlu_ctl.scala 849:218]
node _T_752 = and(_T_750, _T_751) @[el2_dec_tlu_ctl.scala 849:216]
node _T_753 = not(take_reset) @[el2_dec_tlu_ctl.scala 849:228]
node _T_754 = and(_T_752, _T_753) @[el2_dec_tlu_ctl.scala 849:226]
node _T_755 = not(ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 849:242]
node _T_756 = and(_T_754, _T_755) @[el2_dec_tlu_ctl.scala 849:240]
node _T_757 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 849:269]
node _T_758 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 849:332]
node _T_759 = and(take_ext_int_start_d3, _T_758) @[el2_dec_tlu_ctl.scala 849:313]
node _T_760 = or(_T_757, _T_759) @[el2_dec_tlu_ctl.scala 849:288]
node _T_761 = and(_T_756, _T_760) @[el2_dec_tlu_ctl.scala 849:266]
take_nmi <= _T_761 @[el2_dec_tlu_ctl.scala 849:13]
node _T_762 = or(take_ext_int, take_timer_int) @[el2_dec_tlu_ctl.scala 852:38]
node _T_763 = or(_T_762, take_soft_int) @[el2_dec_tlu_ctl.scala 852:55]
node _T_764 = or(_T_763, take_nmi) @[el2_dec_tlu_ctl.scala 852:71]
node _T_765 = or(_T_764, take_ce_int) @[el2_dec_tlu_ctl.scala 852:82]
node _T_766 = or(_T_765, take_int_timer0_int) @[el2_dec_tlu_ctl.scala 852:96]
node _T_767 = or(_T_766, take_int_timer1_int) @[el2_dec_tlu_ctl.scala 852:118]
interrupt_valid_r <= _T_767 @[el2_dec_tlu_ctl.scala 852:22]
node _T_768 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 857:34]
node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58]
node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_772 = add(_T_769, _T_771) @[el2_dec_tlu_ctl.scala 857:51]
node vectored_path = tail(_T_772, 1) @[el2_dec_tlu_ctl.scala 857:51]
node _T_773 = bits(take_nmi, 0, 0) @[el2_dec_tlu_ctl.scala 858:38]
node _T_774 = bits(mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 858:67]
node _T_775 = eq(_T_774, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 858:71]
node _T_776 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 858:104]
node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_778 = mux(_T_775, vectored_path, _T_777) @[el2_dec_tlu_ctl.scala 858:61]
node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[el2_dec_tlu_ctl.scala 858:28]
node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[el2_dec_tlu_ctl.scala 859:36]
node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 859:48]
node _T_781 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 859:96]
node _T_782 = and(i_cpu_run_req_d1, _T_781) @[el2_dec_tlu_ctl.scala 859:94]
node _T_783 = or(_T_780, _T_782) @[el2_dec_tlu_ctl.scala 859:74]
node _T_784 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 859:131]
node _T_785 = and(rfpc_i0_r, _T_784) @[el2_dec_tlu_ctl.scala 859:129]
node sel_npc_r = or(_T_783, _T_785) @[el2_dec_tlu_ctl.scala 859:116]
node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 860:43]
node sel_npc_resume = or(_T_786, pause_expired_r) @[el2_dec_tlu_ctl.scala 860:66]
node _T_787 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 861:65]
node _T_788 = not(_T_787) @[el2_dec_tlu_ctl.scala 861:47]
node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[el2_dec_tlu_ctl.scala 861:45]
node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[el2_dec_tlu_ctl.scala 862:49]
node _T_790 = or(_T_789, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 862:61]
node _T_791 = or(_T_790, fence_i_r) @[el2_dec_tlu_ctl.scala 862:79]
node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 862:91]
node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 862:108]
node _T_794 = or(_T_793, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 862:135]
node _T_795 = or(_T_794, sel_npc_resume) @[el2_dec_tlu_ctl.scala 862:157]
node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[el2_dec_tlu_ctl.scala 862:175]
node _T_797 = or(_T_796, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 862:201]
synchronous_flush_r <= _T_797 @[el2_dec_tlu_ctl.scala 862:25]
node _T_798 = or(interrupt_valid_r, mret_r) @[el2_dec_tlu_ctl.scala 863:43]
node _T_799 = or(_T_798, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 863:52]
node _T_800 = or(_T_799, take_halt) @[el2_dec_tlu_ctl.scala 863:74]
node _T_801 = or(_T_800, take_reset) @[el2_dec_tlu_ctl.scala 863:86]
node _T_802 = or(_T_801, take_ext_int_start) @[el2_dec_tlu_ctl.scala 863:99]
tlu_flush_lower_r <= _T_802 @[el2_dec_tlu_ctl.scala 863:22]
node _T_803 = bits(take_reset, 0, 0) @[el2_dec_tlu_ctl.scala 865:42]
node _T_804 = bits(sel_fir_addr, 0, 0) @[el2_dec_tlu_ctl.scala 866:72]
node _T_805 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 867:66]
node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 867:84]
node _T_807 = and(_T_805, _T_806) @[el2_dec_tlu_ctl.scala 867:73]
node _T_808 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 868:66]
node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 868:84]
node _T_810 = and(_T_808, _T_809) @[el2_dec_tlu_ctl.scala 868:73]
node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 868:114]
node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 868:91]
node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 868:132]
node _T_814 = and(_T_812, _T_813) @[el2_dec_tlu_ctl.scala 868:121]
node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 869:75]
node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 869:96]
node _T_817 = and(_T_815, _T_816) @[el2_dec_tlu_ctl.scala 869:82]
node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 870:80]
node _T_819 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 870:120]
node _T_820 = and(i0_trigger_hit_r, _T_819) @[el2_dec_tlu_ctl.scala 870:118]
node _T_821 = or(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 870:98]
node _T_822 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 870:145]
node _T_823 = and(_T_821, _T_822) @[el2_dec_tlu_ctl.scala 870:143]
node _T_824 = not(sel_fir_addr) @[el2_dec_tlu_ctl.scala 870:166]
node _T_825 = and(_T_823, _T_824) @[el2_dec_tlu_ctl.scala 870:164]
node _T_826 = bits(_T_825, 0, 0) @[el2_dec_tlu_ctl.scala 870:181]
node _T_827 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 870:205]
node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_829 = not(take_nmi) @[el2_dec_tlu_ctl.scala 871:58]
node _T_830 = and(_T_829, mret_r) @[el2_dec_tlu_ctl.scala 871:68]
node _T_831 = bits(_T_830, 0, 0) @[el2_dec_tlu_ctl.scala 871:78]
node _T_832 = not(take_nmi) @[el2_dec_tlu_ctl.scala 872:58]
node _T_833 = and(_T_832, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 872:68]
node _T_834 = bits(_T_833, 0, 0) @[el2_dec_tlu_ctl.scala 872:90]
node _T_835 = not(take_nmi) @[el2_dec_tlu_ctl.scala 873:58]
node _T_836 = and(_T_835, sel_npc_resume) @[el2_dec_tlu_ctl.scala 873:68]
node _T_837 = bits(_T_836, 0, 0) @[el2_dec_tlu_ctl.scala 873:86]
node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72]
node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72]
node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72]
node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72]
node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72]
node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72]
node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72]
wire _T_853 : UInt<31> @[Mux.scala 27:72]
_T_853 <= _T_852 @[Mux.scala 27:72]
node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[el2_dec_tlu_ctl.scala 865:30]
reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 876:64]
tlu_flush_path_r_d1 <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 876:64]
io.tlu_bp.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 878:49]
io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[el2_dec_tlu_ctl.scala 879:41]
io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 880:49]
io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 881:49]
node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[el2_dec_tlu_ctl.scala 884:45]
node _T_855 = or(_T_854, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 884:68]
node _T_856 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 884:110]
node _T_857 = and(i0_trigger_hit_r, _T_856) @[el2_dec_tlu_ctl.scala 884:108]
node exc_or_int_valid_r = or(_T_855, _T_857) @[el2_dec_tlu_ctl.scala 884:88]
reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 886:90]
_T_858 <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 886:90]
interrupt_valid_r_d1 <= _T_858 @[el2_dec_tlu_ctl.scala 886:57]
reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 887:89]
i0_exception_valid_r_d1 <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 887:89]
reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 888:90]
_T_859 <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 888:90]
exc_or_int_valid_r_d1 <= _T_859 @[el2_dec_tlu_ctl.scala 888:57]
reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 889:89]
exc_cause_wb <= exc_cause_r @[el2_dec_tlu_ctl.scala 889:89]
node _T_860 = not(illegal_r) @[el2_dec_tlu_ctl.scala 890:119]
node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[el2_dec_tlu_ctl.scala 890:117]
reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 890:97]
i0_valid_wb <= _T_861 @[el2_dec_tlu_ctl.scala 890:97]
reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 891:89]
trigger_hit_r_d1 <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 891:89]
reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 892:98]
_T_862 <= take_nmi @[el2_dec_tlu_ctl.scala 892:98]
take_nmi_r_d1 <= _T_862 @[el2_dec_tlu_ctl.scala 892:65]
reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 893:90]
_T_863 <= pause_expired_r @[el2_dec_tlu_ctl.scala 893:90]
pause_expired_wb <= _T_863 @[el2_dec_tlu_ctl.scala 893:57]
inst csr of csr_tlu @[el2_dec_tlu_ctl.scala 895:15]
csr.clock <= clock
csr.reset <= reset
csr.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 896:44]
csr.io.active_clk <= io.active_clk @[el2_dec_tlu_ctl.scala 897:44]
csr.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 898:44]
csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 899:44]
csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 900:44]
csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 901:44]
csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[el2_dec_tlu_ctl.scala 902:44]
csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[el2_dec_tlu_ctl.scala 903:44]
csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[el2_dec_tlu_ctl.scala 904:44]
csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 905:44]
csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec_tlu_ctl.scala 906:44]
csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec_tlu_ctl.scala 907:44]
csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec_tlu_ctl.scala 908:44]
csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[el2_dec_tlu_ctl.scala 909:44]
csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[el2_dec_tlu_ctl.scala 910:44]
csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[el2_dec_tlu_ctl.scala 911:44]
csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[el2_dec_tlu_ctl.scala 912:44]
csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[el2_dec_tlu_ctl.scala 913:44]
csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[el2_dec_tlu_ctl.scala 913:44]
csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[el2_dec_tlu_ctl.scala 914:44]
csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[el2_dec_tlu_ctl.scala 915:44]
csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[el2_dec_tlu_ctl.scala 916:44]
csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec_tlu_ctl.scala 917:44]
csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[el2_dec_tlu_ctl.scala 918:44]
csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[el2_dec_tlu_ctl.scala 919:44]
csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[el2_dec_tlu_ctl.scala 920:44]
csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[el2_dec_tlu_ctl.scala 921:44]
csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[el2_dec_tlu_ctl.scala 922:44]
csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec_tlu_ctl.scala 923:44]
csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec_tlu_ctl.scala 924:44]
csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec_tlu_ctl.scala 925:44]
csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec_tlu_ctl.scala 926:44]
csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[el2_dec_tlu_ctl.scala 927:44]
csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 928:44]
csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[el2_dec_tlu_ctl.scala 929:44]
csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[el2_dec_tlu_ctl.scala 930:44]
csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 931:44]
csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[el2_dec_tlu_ctl.scala 932:44]
csr.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[el2_dec_tlu_ctl.scala 933:18]
io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[el2_dec_tlu_ctl.scala 933:18]
io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[el2_dec_tlu_ctl.scala 933:18]
io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[el2_dec_tlu_ctl.scala 933:18]
csr.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 933:18]
csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[el2_dec_tlu_ctl.scala 944:44]
csr.io.pic_pl <= io.pic_pl @[el2_dec_tlu_ctl.scala 945:44]
csr.io.pic_claimid <= io.pic_claimid @[el2_dec_tlu_ctl.scala 946:44]
csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec_tlu_ctl.scala 947:44]
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 949:44]
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 950:44]
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 950:44]
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 950:44]
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 950:44]
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 950:44]
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 950:44]
csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 951:44]
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[el2_dec_tlu_ctl.scala 952:44]
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 953:44]
csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 954:44]
csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 955:44]
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 956:44]
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 957:44]
io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[el2_dec_tlu_ctl.scala 958:44]
io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[el2_dec_tlu_ctl.scala 959:52]
io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[el2_dec_tlu_ctl.scala 960:44]
io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[el2_dec_tlu_ctl.scala 961:44]
io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec_tlu_ctl.scala 962:44]
io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[el2_dec_tlu_ctl.scala 963:44]
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec_tlu_ctl.scala 964:52]
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec_tlu_ctl.scala 964:52]
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec_tlu_ctl.scala 964:52]
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec_tlu_ctl.scala 964:52]
io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 965:40]
io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 965:40]
io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 966:40]
io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 967:40]
io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[el2_dec_tlu_ctl.scala 968:40]
io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[el2_dec_tlu_ctl.scala 969:40]
io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[el2_dec_tlu_ctl.scala 970:40]
io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[el2_dec_tlu_ctl.scala 971:40]
io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[el2_dec_tlu_ctl.scala 972:40]
io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 973:40]
io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[el2_dec_tlu_ctl.scala 974:40]
io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[el2_dec_tlu_ctl.scala 975:40]
io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[el2_dec_tlu_ctl.scala 976:40]
io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[el2_dec_tlu_ctl.scala 977:40]
io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[el2_dec_tlu_ctl.scala 978:40]
io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[el2_dec_tlu_ctl.scala 979:40]
io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[el2_dec_tlu_ctl.scala 980:40]
io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[el2_dec_tlu_ctl.scala 981:40]
io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 982:40]
io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[el2_dec_tlu_ctl.scala 983:48]
io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[el2_dec_tlu_ctl.scala 984:47]
io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[el2_dec_tlu_ctl.scala 985:48]
io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[el2_dec_tlu_ctl.scala 986:40]
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 987:44]
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 988:44]
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 988:44]
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 988:44]
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 988:44]
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 988:44]
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 988:44]
csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 989:44]
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[el2_dec_tlu_ctl.scala 990:44]
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 991:44]
csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 992:44]
csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 993:44]
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 994:44]
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 995:44]
csr.io.rfpc_i0_r <= rfpc_i0_r @[el2_dec_tlu_ctl.scala 998:39]
csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 999:39]
csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 1000:39]
csr.io.mret_r <= mret_r @[el2_dec_tlu_ctl.scala 1001:39]
csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[el2_dec_tlu_ctl.scala 1002:39]
csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[el2_dec_tlu_ctl.scala 1003:39]
csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[el2_dec_tlu_ctl.scala 1004:39]
csr.io.timer_int_sync <= timer_int_sync @[el2_dec_tlu_ctl.scala 1005:39]
csr.io.soft_int_sync <= soft_int_sync @[el2_dec_tlu_ctl.scala 1006:39]
csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[el2_dec_tlu_ctl.scala 1007:39]
csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 1008:39]
csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 1009:39]
csr.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec_tlu_ctl.scala 1010:39]
csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 1011:39]
csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[el2_dec_tlu_ctl.scala 1012:39]
csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[el2_dec_tlu_ctl.scala 1013:39]
csr.io.reset_delayed <= reset_delayed @[el2_dec_tlu_ctl.scala 1014:39]
csr.io.interrupt_valid_r <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 1015:39]
csr.io.i0_exception_valid_r <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 1016:39]
csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1017:39]
csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[el2_dec_tlu_ctl.scala 1018:39]
csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[el2_dec_tlu_ctl.scala 1019:39]
csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1020:39]
csr.io.inst_acc_r <= inst_acc_r @[el2_dec_tlu_ctl.scala 1021:39]
csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 1022:39]
csr.io.take_nmi <= take_nmi @[el2_dec_tlu_ctl.scala 1023:39]
csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 1024:39]
csr.io.exc_cause_r <= exc_cause_r @[el2_dec_tlu_ctl.scala 1025:39]
csr.io.i0_valid_wb <= i0_valid_wb @[el2_dec_tlu_ctl.scala 1026:39]
csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[el2_dec_tlu_ctl.scala 1027:39]
csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 1028:39]
csr.io.clk_override <= io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 1029:39]
csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[el2_dec_tlu_ctl.scala 1030:39]
csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[el2_dec_tlu_ctl.scala 1031:39]
csr.io.exc_cause_wb <= exc_cause_wb @[el2_dec_tlu_ctl.scala 1032:39]
csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 1033:39]
csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 1034:39]
csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 1035:39]
csr.io.ebreak_r <= ebreak_r @[el2_dec_tlu_ctl.scala 1036:39]
csr.io.ecall_r <= ecall_r @[el2_dec_tlu_ctl.scala 1037:39]
csr.io.illegal_r <= illegal_r @[el2_dec_tlu_ctl.scala 1038:39]
csr.io.mdseac_locked_f <= mdseac_locked_f @[el2_dec_tlu_ctl.scala 1039:39]
csr.io.nmi_int_detected_f <= nmi_int_detected_f @[el2_dec_tlu_ctl.scala 1040:39]
csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[el2_dec_tlu_ctl.scala 1041:39]
csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[el2_dec_tlu_ctl.scala 1042:39]
csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[el2_dec_tlu_ctl.scala 1043:39]
csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[el2_dec_tlu_ctl.scala 1044:39]
csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[el2_dec_tlu_ctl.scala 1045:39]
csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[el2_dec_tlu_ctl.scala 1046:39]
csr.io.lsu_idle_any_f <= lsu_idle_any_f @[el2_dec_tlu_ctl.scala 1047:39]
csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 1048:39]
csr.io.dbg_tlu_halted <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 1049:39]
csr.io.debug_halt_req_f <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 1050:51]
csr.io.take_ext_int_start <= take_ext_int_start @[el2_dec_tlu_ctl.scala 1051:47]
csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[el2_dec_tlu_ctl.scala 1052:43]
csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[el2_dec_tlu_ctl.scala 1053:43]
csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[el2_dec_tlu_ctl.scala 1054:43]
csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[el2_dec_tlu_ctl.scala 1055:39]
csr.io.debug_halt_req <= debug_halt_req @[el2_dec_tlu_ctl.scala 1056:51]
csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[el2_dec_tlu_ctl.scala 1057:39]
csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[el2_dec_tlu_ctl.scala 1058:39]
csr.io.enter_debug_halt_req <= enter_debug_halt_req @[el2_dec_tlu_ctl.scala 1059:39]
csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 1060:39]
csr.io.request_debug_mode_done <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 1061:39]
csr.io.request_debug_mode_r <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 1062:39]
csr.io.update_hit_bit_r <= update_hit_bit_r @[el2_dec_tlu_ctl.scala 1063:39]
csr.io.take_timer_int <= take_timer_int @[el2_dec_tlu_ctl.scala 1064:39]
csr.io.take_int_timer0_int <= take_int_timer0_int @[el2_dec_tlu_ctl.scala 1065:39]
csr.io.take_int_timer1_int <= take_int_timer1_int @[el2_dec_tlu_ctl.scala 1066:39]
csr.io.take_ext_int <= take_ext_int @[el2_dec_tlu_ctl.scala 1067:39]
csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 1068:39]
csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 1069:39]
csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 1070:39]
csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[el2_dec_tlu_ctl.scala 1071:39]
csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[el2_dec_tlu_ctl.scala 1072:39]
csr.io.csr_pkt.legal <= csr_pkt.legal @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.postsync <= csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.presync <= csr_pkt.presync @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1073:39]
csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1073:39]
npc_r <= csr.io.npc_r @[el2_dec_tlu_ctl.scala 1075:31]
npc_r_d1 <= csr.io.npc_r_d1 @[el2_dec_tlu_ctl.scala 1076:31]
mie_ns <= csr.io.mie_ns @[el2_dec_tlu_ctl.scala 1077:31]
mepc <= csr.io.mepc @[el2_dec_tlu_ctl.scala 1078:31]
mdseac_locked_ns <= csr.io.mdseac_locked_ns @[el2_dec_tlu_ctl.scala 1079:31]
force_halt <= csr.io.force_halt @[el2_dec_tlu_ctl.scala 1080:31]
dpc <= csr.io.dpc @[el2_dec_tlu_ctl.scala 1081:31]
mstatus_mie_ns <= csr.io.mstatus_mie_ns @[el2_dec_tlu_ctl.scala 1082:31]
dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 1083:31]
fw_halt_req <= csr.io.fw_halt_req @[el2_dec_tlu_ctl.scala 1084:31]
mstatus <= csr.io.mstatus @[el2_dec_tlu_ctl.scala 1085:31]
dcsr <= csr.io.dcsr @[el2_dec_tlu_ctl.scala 1086:31]
mtvec <= csr.io.mtvec @[el2_dec_tlu_ctl.scala 1087:31]
mip <= csr.io.mip @[el2_dec_tlu_ctl.scala 1088:31]
mtdata1_t[0] <= csr.io.mtdata1_t[0] @[el2_dec_tlu_ctl.scala 1089:33]
mtdata1_t[1] <= csr.io.mtdata1_t[1] @[el2_dec_tlu_ctl.scala 1089:33]
mtdata1_t[2] <= csr.io.mtdata1_t[2] @[el2_dec_tlu_ctl.scala 1089:33]
mtdata1_t[3] <= csr.io.mtdata1_t[3] @[el2_dec_tlu_ctl.scala 1089:33]
inst csr_read of el2_dec_decode_csr_read @[el2_dec_tlu_ctl.scala 1090:22]
csr_read.clock <= clock
csr_read.reset <= reset
csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 1091:37]
csr_pkt.legal <= csr_read.io.csr_pkt.legal @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.presync <= csr_read.io.csr_pkt.presync @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1092:16]
csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1092:16]
node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1094:42]
node _T_865 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 1094:67]
node _T_866 = and(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 1094:65]
io.dec_tlu_presync_d <= _T_866 @[el2_dec_tlu_ctl.scala 1094:23]
node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1095:43]
io.dec_tlu_postsync_d <= _T_867 @[el2_dec_tlu_ctl.scala 1095:23]
node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[el2_dec_tlu_ctl.scala 1098:50]
node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[el2_dec_tlu_ctl.scala 1098:72]
node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[el2_dec_tlu_ctl.scala 1098:92]
node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[el2_dec_tlu_ctl.scala 1098:112]
node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[el2_dec_tlu_ctl.scala 1098:134]
node _T_873 = not(UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 1098:159]
node conditionally_illegal = and(_T_872, _T_873) @[el2_dec_tlu_ctl.scala 1098:157]
node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[el2_dec_tlu_ctl.scala 1099:55]
node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[el2_dec_tlu_ctl.scala 1099:73]
node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[el2_dec_tlu_ctl.scala 1099:92]
node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[el2_dec_tlu_ctl.scala 1099:115]
node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[el2_dec_tlu_ctl.scala 1099:136]
node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[el2_dec_tlu_ctl.scala 1099:158]
node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[el2_dec_tlu_ctl.scala 1099:179]
node _T_881 = not(_T_880) @[el2_dec_tlu_ctl.scala 1099:36]
node _T_882 = or(_T_881, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 1099:201]
node _T_883 = and(csr_pkt.legal, _T_882) @[el2_dec_tlu_ctl.scala 1099:33]
node _T_884 = not(fast_int_meicpct) @[el2_dec_tlu_ctl.scala 1099:223]
node _T_885 = and(_T_883, _T_884) @[el2_dec_tlu_ctl.scala 1099:221]
node _T_886 = not(conditionally_illegal) @[el2_dec_tlu_ctl.scala 1099:243]
node valid_csr = and(_T_885, _T_886) @[el2_dec_tlu_ctl.scala 1099:241]
node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[el2_dec_tlu_ctl.scala 1101:46]
node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[el2_dec_tlu_ctl.scala 1101:107]
node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[el2_dec_tlu_ctl.scala 1101:129]
node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[el2_dec_tlu_ctl.scala 1101:150]
node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[el2_dec_tlu_ctl.scala 1101:172]
node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[el2_dec_tlu_ctl.scala 1101:193]
node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[el2_dec_tlu_ctl.scala 1101:82]
node _T_894 = not(_T_893) @[el2_dec_tlu_ctl.scala 1101:59]
node _T_895 = and(_T_887, _T_894) @[el2_dec_tlu_ctl.scala 1101:57]
io.dec_csr_legal_d <= _T_895 @[el2_dec_tlu_ctl.scala 1101:20]
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