954 lines
69 KiB
Plaintext
954 lines
69 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit lsu_lsc_ctl :
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module lsu_addrcheck :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
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node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
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node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
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wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
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node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
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node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
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start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
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node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
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node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
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wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
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node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
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node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
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end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
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wire addr_in_iccm : UInt<1>
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addr_in_iccm <= UInt<1>("h00")
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node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
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node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
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addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
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node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
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node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
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node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
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wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
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node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
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node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
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start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
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node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
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node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
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node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
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wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
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node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
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node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
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end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
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node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
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node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
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node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
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node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
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node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
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node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
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node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
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node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
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io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
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node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
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io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
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node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
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node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
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io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
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node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
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node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
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node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
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node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
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node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
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node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
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node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
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node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
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node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
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node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
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node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
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node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
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node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
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node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
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node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
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node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
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node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
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node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
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node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
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node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
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node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
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node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
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node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
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node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
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node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
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node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
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node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
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node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
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node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
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node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
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node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
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node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
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node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
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node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
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node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
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node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
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node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
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node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
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node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
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node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
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node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
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node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
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node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
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node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
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node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
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node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
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node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
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node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
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node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
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node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
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node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
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node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
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node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
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node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
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node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
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node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
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node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
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node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
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node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
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node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
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node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
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node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
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node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
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node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
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node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
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node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
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node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
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node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
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node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
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node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
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node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
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node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
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node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
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node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
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node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
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node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
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node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
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node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
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node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
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node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
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node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
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node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
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node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
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node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
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node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
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node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
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node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
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node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
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node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
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node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
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node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
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node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
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node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
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node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
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node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
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node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
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node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
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node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
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node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
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node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
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node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
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node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
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node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
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node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
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node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
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node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
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node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
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node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
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node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
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node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
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node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
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node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
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node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
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node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
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node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
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node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
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node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
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node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
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node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
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node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
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node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
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node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
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node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
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node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
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wire unmapped_access_fault_d : UInt<1>
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unmapped_access_fault_d <= UInt<1>("h01")
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wire mpu_access_fault_d : UInt<1>
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mpu_access_fault_d <= UInt<1>("h01")
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node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
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node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
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node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
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node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
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node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
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node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
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node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
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node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
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node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
|
|
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
|
|
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
|
|
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
|
|
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
|
|
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
|
|
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
|
|
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
|
|
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
|
|
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
|
|
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
|
|
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
|
|
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
|
|
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
|
|
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
|
|
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
|
|
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
|
|
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
|
|
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
|
|
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
|
|
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
|
|
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
|
|
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
|
|
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
|
|
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
|
|
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
|
|
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
|
|
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
|
|
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
|
|
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
|
|
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
|
|
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
|
|
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
|
|
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
|
|
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
|
|
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
|
|
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
|
|
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
|
|
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
|
|
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
|
|
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
|
|
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
|
|
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
|
|
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
|
|
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
|
|
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
|
|
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
|
|
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
|
|
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
|
|
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
|
|
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
|
|
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
|
|
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
|
|
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
|
|
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
|
|
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
|
|
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
|
|
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
|
|
|
|
extmodule gated_latch :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
module rvclkhdr :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of gated_latch @[lib.scala 334:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
extmodule gated_latch_1 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
module rvclkhdr_1 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
extmodule gated_latch_2 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
module rvclkhdr_2 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
extmodule gated_latch_3 :
|
|
output Q : Clock
|
|
input CK : Clock
|
|
input EN : UInt<1>
|
|
input SE : UInt<1>
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
module rvclkhdr_3 :
|
|
input clock : Clock
|
|
input reset : Reset
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
|
|
clkhdr.SE is invalid
|
|
clkhdr.EN is invalid
|
|
clkhdr.CK is invalid
|
|
clkhdr.Q is invalid
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
module lsu_lsc_ctl :
|
|
input clock : Clock
|
|
input reset : AsyncReset
|
|
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
|
|
|
|
wire end_addr_pre_m : UInt<29>
|
|
end_addr_pre_m <= UInt<29>("h00")
|
|
wire end_addr_pre_r : UInt<29>
|
|
end_addr_pre_r <= UInt<29>("h00")
|
|
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
|
|
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
|
|
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
|
|
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29]
|
|
node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
|
|
node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
|
|
node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
|
|
node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
|
|
node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 101:51]
|
|
node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
|
|
node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
|
|
node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
|
|
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
|
|
node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
|
|
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
|
|
node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39]
|
|
node _T_10 = tail(_T_9, 1) @[lib.scala 92:39]
|
|
node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
|
|
node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50]
|
|
node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46]
|
|
node _T_14 = not(_T_13) @[lib.scala 93:33]
|
|
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
|
|
node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58]
|
|
node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
|
|
node _T_20 = not(_T_19) @[lib.scala 94:18]
|
|
node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34]
|
|
node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30]
|
|
node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
|
|
node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54]
|
|
node _T_27 = tail(_T_26, 1) @[lib.scala 94:54]
|
|
node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41]
|
|
node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72]
|
|
node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
|
|
node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34]
|
|
node _T_32 = not(_T_31) @[lib.scala 95:31]
|
|
node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29]
|
|
node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
|
|
node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54]
|
|
node _T_38 = tail(_T_37, 1) @[lib.scala 95:54]
|
|
node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41]
|
|
node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61]
|
|
node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22]
|
|
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
|
|
node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_44 = and(_T_43, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
|
|
node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_47 = and(_T_46, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
|
|
node _T_48 = or(_T_44, _T_47) @[lsu_lsc_ctl.scala 109:70]
|
|
node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_51 = and(_T_50, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
|
|
node addr_offset_d = or(_T_48, _T_51) @[lsu_lsc_ctl.scala 110:52]
|
|
node _T_52 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
|
|
node _T_53 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
|
|
node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
|
|
node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_56 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
|
|
node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58]
|
|
node _T_58 = add(_T_54, _T_57) @[lsu_lsc_ctl.scala 113:60]
|
|
node end_addr_offset_d = tail(_T_58, 1) @[lsu_lsc_ctl.scala 113:60]
|
|
node _T_59 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
|
|
node _T_60 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
|
|
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_63 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
|
|
node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58]
|
|
node _T_65 = add(_T_59, _T_64) @[lsu_lsc_ctl.scala 114:39]
|
|
node full_end_addr_d = tail(_T_65, 1) @[lsu_lsc_ctl.scala 114:39]
|
|
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
|
|
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
|
|
addrcheck.clock <= clock
|
|
addrcheck.reset <= reset
|
|
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
|
|
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
|
|
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
|
|
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
|
|
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
|
|
node _T_66 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
|
|
addrcheck.io.rs1_region_d <= _T_66 @[lsu_lsc_ctl.scala 126:42]
|
|
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
|
|
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
|
|
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
|
|
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
|
|
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
|
|
wire exc_mscause_r : UInt<4>
|
|
exc_mscause_r <= UInt<4>("h00")
|
|
wire fir_dccm_access_error_r : UInt<1>
|
|
fir_dccm_access_error_r <= UInt<1>("h00")
|
|
wire fir_nondccm_access_error_r : UInt<1>
|
|
fir_nondccm_access_error_r <= UInt<1>("h00")
|
|
wire access_fault_r : UInt<1>
|
|
access_fault_r <= UInt<1>("h00")
|
|
wire misaligned_fault_r : UInt<1>
|
|
misaligned_fault_r <= UInt<1>("h00")
|
|
wire lsu_fir_error_m : UInt<2>
|
|
lsu_fir_error_m <= UInt<2>("h00")
|
|
wire fir_dccm_access_error_m : UInt<1>
|
|
fir_dccm_access_error_m <= UInt<1>("h00")
|
|
wire fir_nondccm_access_error_m : UInt<1>
|
|
fir_nondccm_access_error_m <= UInt<1>("h00")
|
|
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
|
|
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
|
|
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
|
|
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
|
|
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
|
|
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
|
|
reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
|
|
_T_67 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
|
|
fir_dccm_access_error_m <= _T_67 @[lsu_lsc_ctl.scala 152:38]
|
|
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
|
|
_T_68 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
|
|
fir_nondccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 153:38]
|
|
node _T_69 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
|
|
io.lsu_exc_m <= _T_69 @[lsu_lsc_ctl.scala 155:16]
|
|
node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
|
|
node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[lsu_lsc_ctl.scala 156:62]
|
|
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
|
|
node _T_73 = and(_T_71, _T_72) @[lsu_lsc_ctl.scala 156:92]
|
|
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
|
|
io.lsu_single_ecc_error_incr <= _T_74 @[lsu_lsc_ctl.scala 156:32]
|
|
node _T_75 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 178:46]
|
|
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 178:67]
|
|
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 178:96]
|
|
node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:119]
|
|
node _T_79 = and(_T_77, _T_78) @[lsu_lsc_ctl.scala 178:117]
|
|
node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:144]
|
|
node _T_81 = and(_T_79, _T_80) @[lsu_lsc_ctl.scala 178:142]
|
|
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:174]
|
|
node _T_83 = and(_T_81, _T_82) @[lsu_lsc_ctl.scala 178:172]
|
|
lsu_error_pkt_m.valid <= _T_83 @[lsu_lsc_ctl.scala 178:27]
|
|
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:75]
|
|
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[lsu_lsc_ctl.scala 179:73]
|
|
node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:101]
|
|
node _T_87 = and(_T_85, _T_86) @[lsu_lsc_ctl.scala 179:99]
|
|
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[lsu_lsc_ctl.scala 179:43]
|
|
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 180:43]
|
|
node _T_88 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 181:46]
|
|
lsu_error_pkt_m.bits.exc_type <= _T_88 @[lsu_lsc_ctl.scala 181:43]
|
|
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:80]
|
|
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[lsu_lsc_ctl.scala 182:78]
|
|
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:102]
|
|
node _T_92 = and(_T_90, _T_91) @[lsu_lsc_ctl.scala 182:100]
|
|
node _T_93 = eq(_T_92, UInt<1>("h01")) @[lsu_lsc_ctl.scala 182:118]
|
|
node _T_94 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 182:149]
|
|
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[lsu_lsc_ctl.scala 182:49]
|
|
lsu_error_pkt_m.bits.mscause <= _T_95 @[lsu_lsc_ctl.scala 182:43]
|
|
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 183:59]
|
|
lsu_error_pkt_m.bits.addr <= _T_96 @[lsu_lsc_ctl.scala 183:43]
|
|
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:72]
|
|
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:117]
|
|
node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 184:166]
|
|
node _T_100 = bits(_T_99, 0, 0) @[lsu_lsc_ctl.scala 184:195]
|
|
node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 184:137]
|
|
node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[lsu_lsc_ctl.scala 184:92]
|
|
node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[lsu_lsc_ctl.scala 184:44]
|
|
lsu_fir_error_m <= _T_103 @[lsu_lsc_ctl.scala 184:38]
|
|
node _T_104 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 185:73]
|
|
node _T_105 = or(_T_104, io.clk_override) @[lsu_lsc_ctl.scala 185:113]
|
|
node _T_106 = bits(_T_105, 0, 0) @[lib.scala 8:44]
|
|
node _T_107 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
|
inst rvclkhdr of rvclkhdr @[lib.scala 378:23]
|
|
rvclkhdr.clock <= clock
|
|
rvclkhdr.reset <= reset
|
|
rvclkhdr.io.clk <= clock @[lib.scala 380:18]
|
|
rvclkhdr.io.en <= _T_106 @[lib.scala 381:17]
|
|
rvclkhdr.io.scan_mode <= _T_107 @[lib.scala 382:24]
|
|
wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 384:33]
|
|
_T_108.bits.addr <= UInt<32>("h00") @[lib.scala 384:33]
|
|
_T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 384:33]
|
|
_T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 384:33]
|
|
_T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 384:33]
|
|
_T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 384:33]
|
|
_T_108.valid <= UInt<1>("h00") @[lib.scala 384:33]
|
|
reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 384:16]
|
|
_T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 384:16]
|
|
_T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 384:16]
|
|
_T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 384:16]
|
|
_T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 384:16]
|
|
_T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 384:16]
|
|
_T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 384:16]
|
|
io.lsu_error_pkt_r.bits.addr <= _T_109.bits.addr @[lsu_lsc_ctl.scala 185:24]
|
|
io.lsu_error_pkt_r.bits.mscause <= _T_109.bits.mscause @[lsu_lsc_ctl.scala 185:24]
|
|
io.lsu_error_pkt_r.bits.exc_type <= _T_109.bits.exc_type @[lsu_lsc_ctl.scala 185:24]
|
|
io.lsu_error_pkt_r.bits.inst_type <= _T_109.bits.inst_type @[lsu_lsc_ctl.scala 185:24]
|
|
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_109.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:24]
|
|
io.lsu_error_pkt_r.valid <= _T_109.valid @[lsu_lsc_ctl.scala 185:24]
|
|
reg _T_110 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:83]
|
|
_T_110 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 186:83]
|
|
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110 @[lsu_lsc_ctl.scala 186:46]
|
|
reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67]
|
|
_T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67]
|
|
io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30]
|
|
reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 193:48]
|
|
_T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 193:48]
|
|
io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 193:38]
|
|
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 195:27]
|
|
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 196:27]
|
|
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 197:22]
|
|
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 198:27]
|
|
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 199:27]
|
|
node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 200:30]
|
|
dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 200:27]
|
|
node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 201:56]
|
|
node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 201:62]
|
|
dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 201:27]
|
|
node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 202:56]
|
|
node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 202:62]
|
|
dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 202:27]
|
|
node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 203:56]
|
|
node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 203:62]
|
|
dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 203:27]
|
|
node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 204:56]
|
|
node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 204:62]
|
|
dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 204:27]
|
|
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 205:39]
|
|
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 206:39]
|
|
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 207:39]
|
|
wire lsu_ld_datafn_r : UInt<32>
|
|
lsu_ld_datafn_r <= UInt<32>("h00")
|
|
wire lsu_ld_datafn_corr_r : UInt<32>
|
|
lsu_ld_datafn_corr_r <= UInt<32>("h00")
|
|
wire lsu_ld_datafn_m : UInt<32>
|
|
lsu_ld_datafn_m <= UInt<32>("h00")
|
|
node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 213:50]
|
|
node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 213:26]
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io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 213:20]
|
|
io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 213:20]
|
|
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 214:20]
|
|
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 215:20]
|
|
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 215:20]
|
|
node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:64]
|
|
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 217:61]
|
|
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:45]
|
|
node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 217:43]
|
|
node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 217:90]
|
|
io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 217:24]
|
|
node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:68]
|
|
node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 218:65]
|
|
node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:49]
|
|
node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 218:47]
|
|
lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 218:24]
|
|
node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:68]
|
|
node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 219:65]
|
|
node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:49]
|
|
node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 219:47]
|
|
lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 219:24]
|
|
wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
_T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
|
|
reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 221:65]
|
|
_T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 221:65]
|
|
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 221:28]
|
|
io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 221:28]
|
|
wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
_T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
|
|
reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 222:65]
|
|
_T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 222:65]
|
|
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 222:28]
|
|
io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 222:28]
|
|
reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 223:65]
|
|
_T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 223:65]
|
|
io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 223:28]
|
|
reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:65]
|
|
_T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 224:65]
|
|
io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 224:28]
|
|
node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 226:59]
|
|
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 226:100]
|
|
node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 226:66]
|
|
node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 227:63]
|
|
node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 227:91]
|
|
node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 227:122]
|
|
node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 227:34]
|
|
node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 228:73]
|
|
node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 228:95]
|
|
node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 228:114]
|
|
node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 228:34]
|
|
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:72]
|
|
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 230:72]
|
|
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62]
|
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_T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 231:62]
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|
io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 231:24]
|
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reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
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_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 232:62]
|
|
io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 232:24]
|
|
node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
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node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 234:71]
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node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 234:27]
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node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 234:128]
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reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:114]
|
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_T_158 <= _T_157 @[lsu_lsc_ctl.scala 234:114]
|
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node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
|
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io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 234:17]
|
|
node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
|
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node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 235:71]
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node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 235:27]
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node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 235:128]
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reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:114]
|
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_T_164 <= _T_163 @[lsu_lsc_ctl.scala 235:114]
|
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node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
|
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io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 235:17]
|
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node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 237:41]
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node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 237:69]
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node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 237:87]
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node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
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node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
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rvclkhdr_1.clock <= clock
|
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
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rvclkhdr_1.io.en <= _T_169 @[lib.scala 371:17]
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rvclkhdr_1.io.scan_mode <= _T_170 @[lib.scala 372:24]
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reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
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_T_171 <= _T_166 @[lib.scala 374:16]
|
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end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 237:18]
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|
node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 238:41]
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node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 238:69]
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node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 238:87]
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node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
|
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node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
|
|
rvclkhdr_2.clock <= clock
|
|
rvclkhdr_2.reset <= reset
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
|
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rvclkhdr_2.io.en <= _T_175 @[lib.scala 371:17]
|
|
rvclkhdr_2.io.scan_mode <= _T_176 @[lib.scala 372:24]
|
|
reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
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_T_177 <= _T_172 @[lib.scala 374:16]
|
|
end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 238:18]
|
|
reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62]
|
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_T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 241:62]
|
|
io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 241:24]
|
|
reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62]
|
|
_T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 242:62]
|
|
io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 242:24]
|
|
reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:62]
|
|
_T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 243:62]
|
|
io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 243:24]
|
|
reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 244:62]
|
|
_T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 244:62]
|
|
io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 244:24]
|
|
reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 245:62]
|
|
_T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 245:62]
|
|
io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 245:24]
|
|
reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 246:62]
|
|
_T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 246:62]
|
|
io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 246:24]
|
|
reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 247:62]
|
|
_T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 247:62]
|
|
io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 247:24]
|
|
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 248:66]
|
|
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 248:66]
|
|
node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 249:77]
|
|
node _T_186 = bits(_T_185, 0, 0) @[lib.scala 8:44]
|
|
node _T_187 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
|
|
rvclkhdr_3.clock <= clock
|
|
rvclkhdr_3.reset <= reset
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
|
|
rvclkhdr_3.io.en <= _T_186 @[lib.scala 371:17]
|
|
rvclkhdr_3.io.scan_mode <= _T_187 @[lib.scala 372:24]
|
|
reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
|
bus_read_data_r <= io.bus_read_data_m @[lib.scala 374:16]
|
|
node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 252:52]
|
|
io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 252:28]
|
|
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 254:28]
|
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node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 256:68]
|
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node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 256:41]
|
|
node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:96]
|
|
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 256:94]
|
|
node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:110]
|
|
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 256:108]
|
|
io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 256:19]
|
|
node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 257:52]
|
|
node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:69]
|
|
node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 257:59]
|
|
node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 257:133]
|
|
node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 257:94]
|
|
node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 257:89]
|
|
io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 257:29]
|
|
node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 278:53]
|
|
node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 278:33]
|
|
lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 278:27]
|
|
node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 279:49]
|
|
node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 279:33]
|
|
lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 279:27]
|
|
node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 280:66]
|
|
node _T_208 = bits(_T_207, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_209 = mux(_T_208, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 280:125]
|
|
node _T_211 = cat(UInt<24>("h00"), _T_210) @[Cat.scala 29:58]
|
|
node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 280:94]
|
|
node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 281:43]
|
|
node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 281:102]
|
|
node _T_217 = cat(UInt<16>("h00"), _T_216) @[Cat.scala 29:58]
|
|
node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 281:71]
|
|
node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 280:133]
|
|
node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17]
|
|
node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 282:43]
|
|
node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_223 = mux(_T_222, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 282:102]
|
|
node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_226 = mux(_T_225, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 282:125]
|
|
node _T_228 = cat(_T_226, _T_227) @[Cat.scala 29:58]
|
|
node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 282:71]
|
|
node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 281:114]
|
|
node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17]
|
|
node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 283:43]
|
|
node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_234 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 283:101]
|
|
node _T_236 = bits(_T_235, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_237 = mux(_T_236, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 283:125]
|
|
node _T_239 = cat(_T_237, _T_238) @[Cat.scala 29:58]
|
|
node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 283:71]
|
|
node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 282:134]
|
|
node _T_242 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_243 = mux(_T_242, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 284:60]
|
|
node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 284:43]
|
|
node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 283:134]
|
|
io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 280:27]
|
|
node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 285:66]
|
|
node _T_248 = bits(_T_247, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_249 = mux(_T_248, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 285:130]
|
|
node _T_251 = cat(UInt<24>("h00"), _T_250) @[Cat.scala 29:58]
|
|
node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 285:94]
|
|
node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 286:43]
|
|
node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 286:107]
|
|
node _T_257 = cat(UInt<16>("h00"), _T_256) @[Cat.scala 29:58]
|
|
node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 286:71]
|
|
node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 285:138]
|
|
node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 287:17]
|
|
node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 287:43]
|
|
node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_263 = mux(_T_262, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 287:107]
|
|
node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_266 = mux(_T_265, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 287:135]
|
|
node _T_268 = cat(_T_266, _T_267) @[Cat.scala 29:58]
|
|
node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 287:71]
|
|
node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 286:119]
|
|
node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 288:17]
|
|
node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 288:43]
|
|
node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_274 = mux(_T_273, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 288:106]
|
|
node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_277 = mux(_T_276, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 288:135]
|
|
node _T_279 = cat(_T_277, _T_278) @[Cat.scala 29:58]
|
|
node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 288:71]
|
|
node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 287:144]
|
|
node _T_282 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_283 = mux(_T_282, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 289:65]
|
|
node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 289:43]
|
|
node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 288:144]
|
|
io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 285:27]
|
|
|