72 lines
5.8 KiB
Plaintext
72 lines
5.8 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_dec_ib_ctl :
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module el2_dec_ib_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
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io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31]
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io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31]
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io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31]
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io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31]
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io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31]
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io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31]
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io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31]
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io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31]
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io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31]
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node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60]
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node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41]
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node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38]
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node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36]
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node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36]
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node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55]
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node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37]
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node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55]
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node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37]
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node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55]
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node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37]
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node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55]
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node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37]
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node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40]
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node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40]
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node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20]
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node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
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node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
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node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
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node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21]
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node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
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node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
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node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20]
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node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
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node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21]
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node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
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node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
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node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
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node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
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wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
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ib0_debug_in <= _T_23 @[Mux.scala 27:72]
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node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47]
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io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28]
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node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51]
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node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43]
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io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24]
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node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41]
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io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22]
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node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41]
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node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28]
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io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22]
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