236 lines
12 KiB
Systemverilog
236 lines
12 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: DCCM for LSU pipe
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// Comments: Single ported memory
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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// //********************************************************************************
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module lsu_dccm_mem
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#(
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parameter DCCM_BYTE_WIDTH,
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parameter DCCM_BITS,
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parameter DCCM_NUM_BANKS,
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parameter DCCM_BANK_BITS,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH )(
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input logic clk, // clock
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input logic rst_l,
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input logic clk_override, // clock override
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input logic dccm_wren, // write enable
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input logic dccm_rden, // read enable
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
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input logic scan_mode
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);
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localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
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localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
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localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
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logic [DCCM_NUM_BANKS-1:0] wren_bank;
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logic [DCCM_NUM_BANKS-1:0] rden_bank;
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logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
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logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
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logic rd_unaligned, wr_unaligned;
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logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
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logic [DCCM_FDATA_WIDTH-1:0] wrdata;
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logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
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logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
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logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
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logic [DCCM_NUM_BANKS-1:0] dccm_clken;
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assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
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assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
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// Align the read data
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assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
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assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
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// Generate even/odd address
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// 8 Banks, 16KB each (2048 x 72)
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for (genvar i=0; i<32'(DCCM_NUM_BANKS); i++) begin: mem_bank
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assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
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assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
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assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
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dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
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dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
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(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
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dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
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dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
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assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
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// clock gating section
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assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
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// end clock gating section
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`ifdef VERILATOR
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el2_ram #(DCCM_INDEX_DEPTH,39) ram (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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`else
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if (DCCM_INDEX_DEPTH == 32768) begin : dccm
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ram_32768x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
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ram_16384x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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ram_8192x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
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ram_4096x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
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ram_3072x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
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ram_2048x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
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ram_1024x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 512) begin : dccm
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ram_512x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 256) begin : dccm
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ram_256x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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`endif // VERILATOR
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end : mem_bank
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// Flops
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rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
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rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
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`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS
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endmodule // el2_lsu_dccm_mem
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