214 lines
12 KiB
Systemverilog
Executable File
214 lines
12 KiB
Systemverilog
Executable File
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module el2_lsu_ecc
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`include "parameter.sv"
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(
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input logic clk,
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input logic lsu_c2_r_clk, // clocks
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input logic rst_l,
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input logic scan_mode, // scan
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input el2_lsu_pkt_t lsu_pkt_m, // packet in m
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input el2_lsu_pkt_t lsu_pkt_r, // packet in r
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input logic [DCCM_DATA_WIDTH-1:0] stbuf_data_any,
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input logic dec_tlu_core_ecc_disable, // disables the ecc computation and error flagging
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input logic lsu_dccm_rden_r, // dccm rden
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input logic addr_in_dccm_r, // address in dccm
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input logic [DCCM_BITS-1:0] lsu_addr_r, // start address
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input logic [DCCM_BITS-1:0] end_addr_r, // end address
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input logic [DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r, // data from the dccm
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input logic [DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r, // data from the dccm
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input logic [DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc
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input logic [DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r,
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_hi_r,
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_lo_r,
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff,
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff,
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input logic ld_single_ecc_error_r, // ld has a single ecc error
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input logic ld_single_ecc_error_r_ff, // ld has a single ecc error
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input logic lsu_dccm_rden_m, // dccm rden
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input logic addr_in_dccm_m, // address in dccm
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input logic [DCCM_BITS-1:0] lsu_addr_m, // start address
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input logic [DCCM_BITS-1:0] end_addr_m, // end address
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input logic [DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // raw data from mem
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input logic [DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // raw data from mem
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input logic [DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // ecc read out from mem
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input logic [DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m, // ecc read out from mem
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_hi_m,
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output logic [DCCM_DATA_WIDTH-1:0] sec_data_lo_m,
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input logic dma_dccm_wen,
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input logic [31:0] dma_dccm_wdata_lo,
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input logic [31:0] dma_dccm_wdata_hi,
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output logic [DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_hi, // ECC bits for the DMA wdata
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output logic [DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, // ECC bits for the DMA wdata
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output logic [DCCM_ECC_WIDTH-1:0] stbuf_ecc_any,
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output logic [DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff,
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output logic [DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff,
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output logic single_ecc_error_hi_r, // sec detected
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output logic single_ecc_error_lo_r, // sec detected on lower dccm bank
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output logic lsu_single_ecc_error_r, // or of the 2
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output logic lsu_double_ecc_error_r, // double error detected
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output logic lsu_single_ecc_error_m, // or of the 2
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output logic lsu_double_ecc_error_m // double error detected
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);
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logic is_ldst_r;
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logic is_ldst_hi_any, is_ldst_lo_any;
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logic [DCCM_DATA_WIDTH-1:0] dccm_wdata_hi_any, dccm_wdata_lo_any;
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logic [DCCM_ECC_WIDTH-1:0] dccm_wdata_ecc_hi_any, dccm_wdata_ecc_lo_any;
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logic [DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_any, dccm_rdata_lo_any;
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logic [DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_any, dccm_data_ecc_lo_any;
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logic [DCCM_DATA_WIDTH-1:0] sec_data_hi_any, sec_data_lo_any;
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logic single_ecc_error_hi_any, single_ecc_error_lo_any;
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logic double_ecc_error_hi_any, double_ecc_error_lo_any;
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logic double_ecc_error_hi_m, double_ecc_error_lo_m;
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logic double_ecc_error_hi_r, double_ecc_error_lo_r;
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logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
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if (LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
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logic ldst_dual_m, ldst_dual_r;
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logic is_ldst_m;
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logic is_ldst_hi_m, is_ldst_lo_m;
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logic is_ldst_hi_r, is_ldst_lo_r;
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assign ldst_dual_r = (lsu_addr_r[2] != end_addr_r[2]);
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assign is_ldst_r = lsu_pkt_r.valid & (lsu_pkt_r.load | lsu_pkt_r.store) & addr_in_dccm_r & lsu_dccm_rden_r;
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assign is_ldst_lo_r = is_ldst_r & ~dec_tlu_core_ecc_disable;
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assign is_ldst_hi_r = is_ldst_r & (ldst_dual_r | lsu_pkt_r.dma) & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA
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assign is_ldst_hi_any = is_ldst_hi_r;
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assign dccm_rdata_hi_any[DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_r[DCCM_DATA_WIDTH-1:0];
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assign dccm_data_ecc_hi_any[DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_r[DCCM_ECC_WIDTH-1:0];
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assign is_ldst_lo_any = is_ldst_lo_r;
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assign dccm_rdata_lo_any[DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_r[DCCM_DATA_WIDTH-1:0];
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assign dccm_data_ecc_lo_any[DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_r[DCCM_ECC_WIDTH-1:0];
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assign sec_data_hi_r[DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[DCCM_DATA_WIDTH-1:0];
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assign single_ecc_error_hi_r = single_ecc_error_hi_any;
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assign double_ecc_error_hi_r = double_ecc_error_hi_any;
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assign sec_data_lo_r[DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[DCCM_DATA_WIDTH-1:0];
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assign single_ecc_error_lo_r = single_ecc_error_lo_any;
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assign double_ecc_error_lo_r = double_ecc_error_lo_any;
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assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r;
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assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r;
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end else begin: L2U_Plus1_0
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logic ldst_dual_m;
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logic is_ldst_m;
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logic is_ldst_hi_m, is_ldst_lo_m;
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assign ldst_dual_m = (lsu_addr_m[2] != end_addr_m[2]);
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assign is_ldst_m = lsu_pkt_m.valid & (lsu_pkt_m.load | lsu_pkt_m.store) & addr_in_dccm_m & lsu_dccm_rden_m;
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assign is_ldst_lo_m = is_ldst_m & ~dec_tlu_core_ecc_disable;
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assign is_ldst_hi_m = is_ldst_m & (ldst_dual_m | lsu_pkt_m.dma) & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA
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assign is_ldst_hi_any = is_ldst_hi_m;
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assign dccm_rdata_hi_any[DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_m[DCCM_DATA_WIDTH-1:0];
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assign dccm_data_ecc_hi_any[DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_m[DCCM_ECC_WIDTH-1:0];
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assign is_ldst_lo_any = is_ldst_lo_m;
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assign dccm_rdata_lo_any[DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_m[DCCM_DATA_WIDTH-1:0];
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assign dccm_data_ecc_lo_any[DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_m[DCCM_ECC_WIDTH-1:0];
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assign sec_data_hi_m[DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[DCCM_DATA_WIDTH-1:0];
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assign double_ecc_error_hi_m = double_ecc_error_hi_any;
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assign sec_data_lo_m[DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[DCCM_DATA_WIDTH-1:0];
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assign double_ecc_error_lo_m = double_ecc_error_lo_any;
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assign lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any;
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assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m;
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// Flops
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rvdff #(1) lsu_single_ecc_err_r (.din(lsu_single_ecc_error_m), .dout(lsu_single_ecc_error_r), .clk(lsu_c2_r_clk), .*);
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rvdff #(1) lsu_double_ecc_err_r (.din(lsu_double_ecc_error_m), .dout(lsu_double_ecc_error_r), .clk(lsu_c2_r_clk), .*);
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rvdff #(.WIDTH(1)) ldst_sec_lo_rff (.din(single_ecc_error_lo_any), .dout(single_ecc_error_lo_r), .clk(lsu_c2_r_clk), .*);
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rvdff #(.WIDTH(1)) ldst_sec_hi_rff (.din(single_ecc_error_hi_any), .dout(single_ecc_error_hi_r), .clk(lsu_c2_r_clk), .*);
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rvdff #(.WIDTH(DCCM_DATA_WIDTH)) sec_data_hi_rff (.din(sec_data_hi_m[DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r[DCCM_DATA_WIDTH-1:0]), .clk(lsu_c2_r_clk), .*);
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rvdff #(.WIDTH(DCCM_DATA_WIDTH)) sec_data_lo_rff (.din(sec_data_lo_m[DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r[DCCM_DATA_WIDTH-1:0]), .clk(lsu_c2_r_clk), .*);
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end
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// Logic for ECC generation during write
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assign dccm_wdata_lo_any[DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_lo_r_ff[DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_lo[DCCM_DATA_WIDTH-1:0] : stbuf_data_any[DCCM_DATA_WIDTH-1:0]);
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assign dccm_wdata_hi_any[DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_hi_r_ff[DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_hi[DCCM_DATA_WIDTH-1:0] : stbuf_data_any[DCCM_DATA_WIDTH-1:0]);
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assign sec_data_ecc_hi_r_ff[DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[DCCM_ECC_WIDTH-1:0];
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assign sec_data_ecc_lo_r_ff[DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[DCCM_ECC_WIDTH-1:0];
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assign stbuf_ecc_any[DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[DCCM_ECC_WIDTH-1:0];
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assign dma_dccm_wdata_ecc_hi[DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[DCCM_ECC_WIDTH-1:0];
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assign dma_dccm_wdata_ecc_lo[DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[DCCM_ECC_WIDTH-1:0];
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// Instantiate ECC blocks
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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//Detect/Repair for Hi
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rvecc_decode lsu_ecc_decode_hi (
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// Inputs
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.en(is_ldst_hi_any),
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.sed_ded (1'b0), // 1 : means only detection
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.din(dccm_rdata_hi_any[DCCM_DATA_WIDTH-1:0]),
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.ecc_in(dccm_data_ecc_hi_any[DCCM_ECC_WIDTH-1:0]),
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// Outputs
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.dout(sec_data_hi_any[DCCM_DATA_WIDTH-1:0]),
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.ecc_out (ecc_out_hi_nc[6:0]),
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.single_ecc_error(single_ecc_error_hi_any),
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.double_ecc_error(double_ecc_error_hi_any),
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.*
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);
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//Detect/Repair for Lo
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rvecc_decode lsu_ecc_decode_lo (
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// Inputs
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.en(is_ldst_lo_any),
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.sed_ded (1'b0), // 1 : means only detection
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.din(dccm_rdata_lo_any[DCCM_DATA_WIDTH-1:0] ),
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.ecc_in(dccm_data_ecc_lo_any[DCCM_ECC_WIDTH-1:0]),
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// Outputs
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.dout(sec_data_lo_any[DCCM_DATA_WIDTH-1:0]),
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.ecc_out (ecc_out_lo_nc[6:0]),
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.single_ecc_error(single_ecc_error_lo_any),
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.double_ecc_error(double_ecc_error_lo_any),
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.*
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);
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rvecc_encode lsu_ecc_encode_hi (
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//Inputs
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.din(dccm_wdata_hi_any[DCCM_DATA_WIDTH-1:0]),
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//Outputs
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.ecc_out(dccm_wdata_ecc_hi_any[DCCM_ECC_WIDTH-1:0]),
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.*
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);
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rvecc_encode lsu_ecc_encode_lo (
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//Inputs
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.din(dccm_wdata_lo_any[DCCM_DATA_WIDTH-1:0]),
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//Outputs
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.ecc_out(dccm_wdata_ecc_lo_any[DCCM_ECC_WIDTH-1:0]),
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.*
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);
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end else begin: Gen_dccm_disable // block: Gen_dccm_enable
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assign sec_data_hi_any[DCCM_DATA_WIDTH-1:0] = '0;
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assign sec_data_lo_any[DCCM_DATA_WIDTH-1:0] = '0;
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assign single_ecc_error_hi_any = '0;
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assign double_ecc_error_hi_any = '0;
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assign single_ecc_error_lo_any = '0;
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assign double_ecc_error_lo_any = '0;
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assign stbuf_ecc_any[DCCM_ECC_WIDTH-1:0] = '0;
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end
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rvdffe #(.WIDTH(DCCM_DATA_WIDTH)) sec_data_hi_rplus1ff (.din(sec_data_hi_r[DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r_ff[DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r), .clk(clk), .*);
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rvdffe #(.WIDTH(DCCM_DATA_WIDTH)) sec_data_lo_rplus1ff (.din(sec_data_lo_r[DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r_ff[DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r), .clk(clk), .*);
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endmodule // el2_lsu_ecc
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