157 lines
4.9 KiB
Systemverilog
157 lines
4.9 KiB
Systemverilog
typedef struct packed {
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bit [3:0] BHT_ADDR_HI;
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bit [1:0] BHT_ADDR_LO;
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bit [10:0] BHT_ARRAY_DEPTH;
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bit BHT_GHR_HASH_1;
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bit [3:0] BHT_GHR_SIZE;
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bit [11:0] BHT_SIZE;
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bit [4:0] BTB_ADDR_HI;
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bit [1:0] BTB_ADDR_LO;
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bit [8:0] BTB_ARRAY_DEPTH;
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bit BTB_BTAG_FOLD;
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bit [3:0] BTB_BTAG_SIZE;
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bit BTB_FOLD2_INDEX_HASH;
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bit [4:0] BTB_INDEX1_HI;
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bit [4:0] BTB_INDEX1_LO;
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bit [4:0] BTB_INDEX2_HI;
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bit [4:0] BTB_INDEX2_LO;
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bit [4:0] BTB_INDEX3_HI;
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bit [4:0] BTB_INDEX3_LO;
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bit [9:0] BTB_SIZE;
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bit BUILD_AHB_LITE;
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bit BUILD_AXI4;
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bit BUILD_AXI_NATIVE;
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bit [1:0] BUS_PRTY_DEFAULT;
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bit [31:0] DATA_ACCESS_ADDR0;
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bit [31:0] DATA_ACCESS_ADDR1;
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bit [31:0] DATA_ACCESS_ADDR2;
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bit [31:0] DATA_ACCESS_ADDR3;
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bit [31:0] DATA_ACCESS_ADDR4;
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bit [31:0] DATA_ACCESS_ADDR5;
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bit [31:0] DATA_ACCESS_ADDR6;
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bit [31:0] DATA_ACCESS_ADDR7;
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bit DATA_ACCESS_ENABLE0;
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bit DATA_ACCESS_ENABLE1;
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bit DATA_ACCESS_ENABLE2;
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bit DATA_ACCESS_ENABLE3;
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bit DATA_ACCESS_ENABLE4;
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bit DATA_ACCESS_ENABLE5;
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bit DATA_ACCESS_ENABLE6;
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bit DATA_ACCESS_ENABLE7;
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bit [31:0] DATA_ACCESS_MASK0;
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bit [31:0] DATA_ACCESS_MASK1;
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bit [31:0] DATA_ACCESS_MASK2;
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bit [31:0] DATA_ACCESS_MASK3;
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bit [31:0] DATA_ACCESS_MASK4;
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bit [31:0] DATA_ACCESS_MASK5;
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bit [31:0] DATA_ACCESS_MASK6;
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bit [31:0] DATA_ACCESS_MASK7;
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bit [2:0] DCCM_BANK_BITS;
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bit [4:0] DCCM_BITS;
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bit [2:0] DCCM_BYTE_WIDTH;
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bit [5:0] DCCM_DATA_WIDTH;
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bit [2:0] DCCM_ECC_WIDTH;
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bit DCCM_ENABLE;
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bit [5:0] DCCM_FDATA_WIDTH;
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bit [3:0] DCCM_INDEX_BITS;
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bit [4:0] DCCM_NUM_BANKS;
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bit [3:0] DCCM_REGION;
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bit [31:0] DCCM_SADR;
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bit [9:0] DCCM_SIZE;
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bit [1:0] DCCM_WIDTH_BITS;
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bit [2:0] DMA_BUF_DEPTH;
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bit DMA_BUS_ID;
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bit [1:0] DMA_BUS_PRTY;
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bit [3:0] DMA_BUS_TAG;
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bit FAST_INTERRUPT_REDIRECT;
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bit ICACHE_2BANKS;
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bit [2:0] ICACHE_BANK_BITS;
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bit [2:0] ICACHE_BANK_HI;
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bit [1:0] ICACHE_BANK_LO;
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bit [3:0] ICACHE_BANK_WIDTH;
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bit [2:0] ICACHE_BANKS_WAY;
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bit [3:0] ICACHE_BEAT_ADDR_HI;
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bit [3:0] ICACHE_BEAT_BITS;
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bit [13:0] ICACHE_DATA_DEPTH;
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bit [2:0] ICACHE_DATA_INDEX_LO;
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bit [6:0] ICACHE_DATA_WIDTH;
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bit ICACHE_ECC;
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bit ICACHE_ENABLE;
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bit [6:0] ICACHE_FDATA_WIDTH;
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bit [4:0] ICACHE_INDEX_HI;
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bit [6:0] ICACHE_LN_SZ;
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bit [3:0] ICACHE_NUM_BEATS;
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bit [2:0] ICACHE_NUM_WAYS;
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bit ICACHE_ONLY;
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bit [3:0] ICACHE_SCND_LAST;
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bit [8:0] ICACHE_SIZE;
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bit [2:0] ICACHE_STATUS_BITS;
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bit [12:0] ICACHE_TAG_DEPTH;
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bit [2:0] ICACHE_TAG_INDEX_LO;
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bit [4:0] ICACHE_TAG_LO;
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bit ICACHE_WAYPACK;
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bit [2:0] ICCM_BANK_BITS;
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bit [4:0] ICCM_BANK_HI;
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bit [4:0] ICCM_BANK_INDEX_LO;
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bit [4:0] ICCM_BITS;
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bit ICCM_ENABLE;
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bit ICCM_ICACHE;
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bit [3:0] ICCM_INDEX_BITS;
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bit [4:0] ICCM_NUM_BANKS;
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bit ICCM_ONLY;
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bit [3:0] ICCM_REGION;
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bit [31:0] ICCM_SADR;
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bit [9:0] ICCM_SIZE;
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bit IFU_BUS_ID;
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bit [1:0] IFU_BUS_PRTY;
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bit [3:0] IFU_BUS_TAG;
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bit [31:0] INST_ACCESS_ADDR0;
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bit [31:0] INST_ACCESS_ADDR1;
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bit [31:0] INST_ACCESS_ADDR2;
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bit [31:0] INST_ACCESS_ADDR3;
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bit [31:0] INST_ACCESS_ADDR4;
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bit [31:0] INST_ACCESS_ADDR5;
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bit [31:0] INST_ACCESS_ADDR6;
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bit [31:0] INST_ACCESS_ADDR7;
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bit INST_ACCESS_ENABLE0;
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bit INST_ACCESS_ENABLE1;
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bit INST_ACCESS_ENABLE2;
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bit INST_ACCESS_ENABLE3;
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bit INST_ACCESS_ENABLE4;
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bit INST_ACCESS_ENABLE5;
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bit INST_ACCESS_ENABLE6;
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bit INST_ACCESS_ENABLE7;
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bit [31:0] INST_ACCESS_MASK0;
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bit [31:0] INST_ACCESS_MASK1;
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bit [31:0] INST_ACCESS_MASK2;
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bit [31:0] INST_ACCESS_MASK3;
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bit [31:0] INST_ACCESS_MASK4;
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bit [31:0] INST_ACCESS_MASK5;
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bit [31:0] INST_ACCESS_MASK6;
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bit [31:0] INST_ACCESS_MASK7;
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bit LOAD_TO_USE_PLUS1;
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bit LSU2DMA;
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bit LSU_BUS_ID;
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bit [1:0] LSU_BUS_PRTY;
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bit [3:0] LSU_BUS_TAG;
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bit [4:0] LSU_NUM_NBLOAD;
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bit [2:0] LSU_NUM_NBLOAD_WIDTH;
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bit [4:0] LSU_SB_BITS;
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bit [3:0] LSU_STBUF_DEPTH;
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bit NO_ICCM_NO_ICACHE;
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bit PIC_2CYCLE;
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bit [31:0] PIC_BASE_ADDR;
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bit [4:0] PIC_BITS;
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bit [3:0] PIC_INT_WORDS;
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bit [3:0] PIC_REGION;
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bit [8:0] PIC_SIZE;
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bit [7:0] PIC_TOTAL_INT;
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bit [8:0] PIC_TOTAL_INT_PLUS1;
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bit [3:0] RET_STACK_SIZE;
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bit SB_BUS_ID;
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bit [1:0] SB_BUS_PRTY;
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bit [3:0] SB_BUS_TAG;
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bit TIMER_LEGAL_EN;
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} el2_param_t;
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