165 lines
5.6 KiB
Scala
165 lines
5.6 KiB
Scala
//import chisel3._
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//import mem._
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//import chisel3.util._
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//import dmi._
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//import include._
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//import lib._
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//class quasar_wrapper extends Module with lib with RequireAsyncReset {
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// val io = IO(new Bundle{
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// val dbg_rst_l = Input(AsyncReset())
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// val rst_vec = Input(UInt(31.W))
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// val nmi_int = Input(Bool())
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// val nmi_vec = Input(UInt(31.W))
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// val jtag_id = Input(UInt(31.W))
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//
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// // AXI Signals
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// val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
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// val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
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// val sb_brg = bridge_gen(SB_BUS_TAG , false)
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// val dma_brg = bridge_gen(DMA_BUS_TAG, true)
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//
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// val lsu_bus_clk_en = Input(Bool())
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// val ifu_bus_clk_en = Input(Bool())
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// val dbg_bus_clk_en = Input(Bool())
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// val dma_bus_clk_en = Input(Bool())
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//
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// val timer_int = Input(Bool())
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// val soft_int = Input(Bool())
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//
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// val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
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//
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// val dec_tlu_perfcnt0 = Output(Bool())
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// val dec_tlu_perfcnt1 = Output(Bool())
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// val dec_tlu_perfcnt2 = Output(Bool())
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// val dec_tlu_perfcnt3 = Output(Bool())
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//
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// val jtag_tck = Input(Clock())
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// val jtag_tms = Input(Bool())
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// val jtag_tdi = Input(Bool())
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// val jtag_trst_n = Input(Bool())
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// val jtag_tdo = Output(Bool())
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//
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// val core_id = Input(UInt(28.W))
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//
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// val mpc_debug_halt_req = Input(Bool())
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// val mpc_debug_run_req = Input(Bool())
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// val mpc_reset_run_req = Input(Bool())
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// val mpc_debug_halt_ack = Output(Bool())
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// val mpc_debug_run_ack = Output(Bool())
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// val debug_brkpt_status = Output(Bool())
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//
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// val i_cpu_halt_req = Input(Bool())
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// val i_cpu_run_req = Input(Bool())
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// val o_cpu_halt_ack = Output(Bool())
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// val o_cpu_halt_status = Output(Bool())
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// val o_debug_mode_status = Output(Bool())
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// val o_cpu_run_ack = Output(Bool())
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// val mbist_mode = Input(Bool())
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//
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// val rv_trace_pkt = new trace_pkt_t()
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// val scan_mode = Input(Bool())
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//
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// })
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// val mem = Module(new quasar.mem())
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// val dmi_wrapper = Module(new dmi_wrapper())
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// val core = Module(new quasar())
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// core.io.scan_mode := io.scan_mode
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// dmi_wrapper.io.trst_n := io.jtag_trst_n
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// dmi_wrapper.io.tck := io.jtag_tck
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// dmi_wrapper.io.tms := io.jtag_tms
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// dmi_wrapper.io.tdi := io.jtag_tdi
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// dmi_wrapper.io.core_clk := clock
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// dmi_wrapper.io.jtag_id := io.jtag_id
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// dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
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// dmi_wrapper.io.core_rst_n := io.dbg_rst_l
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// core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
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// core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
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// core.io.dmi_reg_en := dmi_wrapper.io.reg_en
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// core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
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// core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
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// io.jtag_tdo := dmi_wrapper.io.tdo
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//
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// // Memory signals
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// mem.io.dccm_clk_override := core.io.dccm_clk_override
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// mem.io.icm_clk_override := core.io.icm_clk_override
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// mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
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// mem.io.dccm <> core.io.dccm
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// mem.io.rst_l := reset
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// mem.io.clk := clock
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// mem.io.scan_mode := io.scan_mode
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// // Memory outputs
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// core.io.dbg_rst_l := io.dbg_rst_l
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// core.io.ic <> mem.io.ic
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// core.io.iccm <> mem.io.iccm
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//
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//
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// if(BUILD_AXI4) {
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// core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb)
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// core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
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// core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
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// core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb)
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//
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// core.io.lsu_axi <> io.lsu_brg
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// core.io.ifu_axi <> io.ifu_brg
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// core.io.sb_axi <> io.sb_brg
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// core.io.dma_axi <> io.dma_brg
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// }
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// else {
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// core.io.ifu_ahb <> io.ifu_brg
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// core.io.lsu_ahb <> io.lsu_brg
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// core.io.sb_ahb <> io.sb_brg
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// core.io.dma_ahb <> io.dma_brg
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//
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// core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
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// core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
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// core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
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// core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
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// }
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// // core Inputs
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// core.io.dbg_rst_l := io.dbg_rst_l
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// core.io.rst_vec := io.rst_vec
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// core.io.nmi_int := io.nmi_int
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// core.io.nmi_vec := io.nmi_vec
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//
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// // external halt/run interface
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// core.io.i_cpu_halt_req := io.i_cpu_halt_req
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// core.io.i_cpu_run_req := io.i_cpu_run_req
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// core.io.core_id := io.core_id
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//
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// // external MPC halt/run interface
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// core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
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// core.io.mpc_debug_run_req := io.mpc_debug_run_req
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// core.io.mpc_reset_run_req := io.mpc_reset_run_req
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//
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// core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
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// core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
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// core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
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// core.io.dma_bus_clk_en := io.dma_bus_clk_en
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//
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// core.io.timer_int := io.timer_int
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// core.io.soft_int := io.soft_int
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// core.io.extintsrc_req := io.extintsrc_req
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//
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// // Outputs
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// val core_rst_l = core.io.core_rst_l
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// io.rv_trace_pkt <> core.io.rv_trace_pkt
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//
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// // external halt/run interface
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// io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
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// io.o_cpu_halt_status := core.io.o_cpu_halt_status
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// io.o_cpu_run_ack := core.io.o_cpu_run_ack
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// io.o_debug_mode_status := core.io.o_debug_mode_status
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//
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// io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
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// io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
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// io.debug_brkpt_status := core.io.debug_brkpt_status
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//
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// io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
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// io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
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// io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
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// io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
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//
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//}
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//object QUASAR_Wrp extends App {
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// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
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//} |