444 lines
20 KiB
Plaintext
444 lines
20 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_lsu_clkdomain :
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extmodule TEC_RV_ICG :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_8 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_8 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_9 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_9 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_10 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_10 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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extmodule TEC_RV_ICG_11 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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module rvclkhdr_11 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 332:24]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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module el2_lsu_clkdomain :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
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wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:37]
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wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:37]
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wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:37]
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wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:37]
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node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:52]
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node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:71]
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node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:52]
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node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:71]
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node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:52]
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node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:71]
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node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:48]
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node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:67]
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node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:48]
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node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:67]
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node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 70:50]
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node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:72]
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node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 71:50]
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node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:72]
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node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:56]
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node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:78]
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node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:108]
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node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:50]
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node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:62]
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node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:80]
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node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:99]
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node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:34]
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node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:63]
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node _T_13 = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:81]
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node lsu_bus_buf_c1_clken = bits(_T_13, 0, 0) @[el2_lsu_clkdomain.scala 75:100]
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node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:49]
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node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:70]
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node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:91]
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node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:115]
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node _T_18 = or(_T_16, _T_17) @[el2_lsu_clkdomain.scala 77:113]
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node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:146]
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node _T_20 = or(_T_18, _T_19) @[el2_lsu_clkdomain.scala 77:144]
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node lsu_free_c1_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 77:170]
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node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:51]
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node lsu_free_c2_clken = or(_T_21, io.clk_override) @[el2_lsu_clkdomain.scala 78:73]
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reg _T_22 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:61]
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_T_22 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:61]
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lsu_free_c1_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 81:27]
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reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:68]
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_T_23 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:68]
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lsu_c1_d_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 82:27]
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reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:68]
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_T_24 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:68]
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lsu_c1_m_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 83:27]
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reg _T_25 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:68]
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_T_25 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:68]
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lsu_c1_r_clken_q <= _T_25 @[el2_lsu_clkdomain.scala 84:27]
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node _T_26 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:60]
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inst rvclkhdr of rvclkhdr @[beh_lib.scala 341:20]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr.io.en <= _T_26 @[beh_lib.scala 343:14]
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rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:27]
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node _T_27 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:60]
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inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 341:20]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_1.io.en <= _T_27 @[beh_lib.scala 343:14]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:27]
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node _T_28 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:60]
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inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 341:20]
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rvclkhdr_2.clock <= clock
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rvclkhdr_2.reset <= reset
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rvclkhdr_2.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_2.io.en <= _T_28 @[beh_lib.scala 343:14]
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rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:27]
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node _T_29 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:60]
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inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 341:20]
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rvclkhdr_3.clock <= clock
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rvclkhdr_3.reset <= reset
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rvclkhdr_3.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_3.io.en <= _T_29 @[beh_lib.scala 343:14]
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rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:27]
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node _T_30 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:66]
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inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 341:20]
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rvclkhdr_4.clock <= clock
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rvclkhdr_4.reset <= reset
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rvclkhdr_4.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_4.io.en <= _T_30 @[beh_lib.scala 343:14]
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rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:27]
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node _T_31 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:66]
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inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 341:20]
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rvclkhdr_5.clock <= clock
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rvclkhdr_5.reset <= reset
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rvclkhdr_5.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_5.io.en <= _T_31 @[beh_lib.scala 343:14]
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rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:27]
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node _T_32 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:64]
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inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 341:20]
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rvclkhdr_6.clock <= clock
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rvclkhdr_6.reset <= reset
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rvclkhdr_6.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_6.io.en <= _T_32 @[beh_lib.scala 343:14]
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rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:27]
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node _T_33 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:67]
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inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 341:20]
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rvclkhdr_7.clock <= clock
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rvclkhdr_7.reset <= reset
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rvclkhdr_7.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_7.io.en <= _T_33 @[beh_lib.scala 343:14]
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rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:27]
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node _T_34 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:67]
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inst rvclkhdr_8 of rvclkhdr_8 @[beh_lib.scala 341:20]
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rvclkhdr_8.clock <= clock
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rvclkhdr_8.reset <= reset
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rvclkhdr_8.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_8.io.en <= _T_34 @[beh_lib.scala 343:14]
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rvclkhdr_8.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:27]
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node _T_35 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:66]
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inst rvclkhdr_9 of rvclkhdr_9 @[beh_lib.scala 341:20]
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rvclkhdr_9.clock <= clock
|
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rvclkhdr_9.reset <= reset
|
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rvclkhdr_9.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_9.io.en <= _T_35 @[beh_lib.scala 343:14]
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rvclkhdr_9.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:27]
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node _T_36 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:63]
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inst rvclkhdr_10 of rvclkhdr_10 @[beh_lib.scala 341:20]
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rvclkhdr_10.clock <= clock
|
|
rvclkhdr_10.reset <= reset
|
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rvclkhdr_10.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_10.io.en <= _T_36 @[beh_lib.scala 343:14]
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rvclkhdr_10.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:27]
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node _T_37 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:63]
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inst rvclkhdr_11 of rvclkhdr_11 @[beh_lib.scala 341:20]
|
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rvclkhdr_11.clock <= clock
|
|
rvclkhdr_11.reset <= reset
|
|
rvclkhdr_11.io.clk <= clock @[beh_lib.scala 342:15]
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rvclkhdr_11.io.en <= _T_37 @[beh_lib.scala 343:14]
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rvclkhdr_11.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
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io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:27]
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