39 lines
1.4 KiB
Verilog
39 lines
1.4 KiB
Verilog
module el2_ifu_ic_mem(
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input clock,
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input reset,
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input io_clk,
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input io_rst_l,
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input io_clk_override,
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input io_dec_tlu_core_ecc_disable,
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input [30:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input io_ic_rd_en,
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input [8:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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input [1:0] io_ic_debug_way,
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input [63:0] io_ic_premux_data,
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input io_ic_sel_premux_data,
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input [70:0] io_ic_wr_data_0,
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input [70:0] io_ic_wr_data_1,
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output [63:0] io_ic_rd_data,
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output [70:0] io_ic_debug_rd_data,
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output [25:0] io_ictag_debug_rd_data,
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input [70:0] io_ic_debug_wr_data,
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output [1:0] io_ic_eccerr,
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output [1:0] io_ic_parerr,
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input [1:0] io_ic_tag_valid,
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output [1:0] io_ic_rd_hit,
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output io_ic_tag_perr,
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input io_scan_mode
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);
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
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endmodule
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