102 lines
3.8 KiB
JSON
102 lines
3.8 KiB
JSON
[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_misaligned",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_load",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_bus_buffer_full_any",
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"sources":[
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_dec_lsu_valid_raw_d",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_d",
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"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_d"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_lsu_bus_intf.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_lsu_bus_intf"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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] |