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quasar/lsu_addrcheck.fir

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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_addrcheck :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
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